Re: [PATCH v1 2/2] RISC-V: Add testcases for form 4 of signed scalar SAT_ADD

[Kito Cheng]

LGTM

 於 2024年9月20日 週五 10:21 寫道：

> From: Pan Li 
>
> Form 4:
>   #define DEF_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)   \
>   T __attribute__((noinline))\
>   sat_s_add_##T##_fmt_4 (T x, T y)   \
>   {  \
> T sum;   \
> bool overflow = __builtin_add_overflow (x, y, &sum); \
> return !overflow ? sum : x < 0 ? MIN : MAX;  \
>   }
>
> DEF_SAT_S_ADD_FMT_4 (int64_t, uint64_t, INT64_MIN, INT64_MAX)
>
> The below test are passed for this patch.
> * The rv64gcv fully regression test.
>
> It is test only patch and obvious up to a point, will commit it
> directly if no comments in next 48H.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/sat_arith.h: Add test helper macros.
> * gcc.target/riscv/sat_s_add-13.c: New test.
> * gcc.target/riscv/sat_s_add-14.c: New test.
> * gcc.target/riscv/sat_s_add-15.c: New test.
> * gcc.target/riscv/sat_s_add-16.c: New test.
> * gcc.target/riscv/sat_s_add-run-13.c: New test.
> * gcc.target/riscv/sat_s_add-run-14.c: New test.
> * gcc.target/riscv/sat_s_add-run-15.c: New test.
> * gcc.target/riscv/sat_s_add-run-16.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/testsuite/gcc.target/riscv/sat_arith.h| 14 
>  gcc/testsuite/gcc.target/riscv/sat_s_add-13.c | 30 +
>  gcc/testsuite/gcc.target/riscv/sat_s_add-14.c | 32 +++
>  gcc/testsuite/gcc.target/riscv/sat_s_add-15.c | 31 ++
>  gcc/testsuite/gcc.target/riscv/sat_s_add-16.c | 29 +
>  .../gcc.target/riscv/sat_s_add-run-13.c   | 16 ++
>  .../gcc.target/riscv/sat_s_add-run-14.c   | 16 ++
>  .../gcc.target/riscv/sat_s_add-run-15.c   | 16 ++
>  .../gcc.target/riscv/sat_s_add-run-16.c   | 16 ++
>  9 files changed, 200 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-13.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-14.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-15.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-16.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-13.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-14.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-15.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-16.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
> b/gcc/testsuite/gcc.target/riscv/sat_arith.h
> index ab141bb1779..a2617b6db70 100644
> --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
> +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
> @@ -153,6 +153,17 @@ sat_s_add_##T##_fmt_3 (T x, T y)
>  \
>  #define DEF_SAT_S_ADD_FMT_3_WRAP(T, UT, MIN, MAX) \
>DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)
>
> +#define DEF_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)   \
> +T __attribute__((noinline))\
> +sat_s_add_##T##_fmt_4 (T x, T y)   \
> +{  \
> +  T sum;   \
> +  bool overflow = __builtin_add_overflow (x, y, &sum); \
> +  return !overflow ? sum : x < 0 ? MIN : MAX;  \
> +}
> +#define DEF_SAT_S_ADD_FMT_4_WRAP(T, UT, MIN, MAX) \
> +  DEF_SAT_S_ADD_FMT_4(T, UT, MIN, MAX)
> +
>  #define RUN_SAT_S_ADD_FMT_1(T, x, y) sat_s_add_##T##_fmt_1(x, y)
>  #define RUN_SAT_S_ADD_FMT_1_WRAP(T, x, y) RUN_SAT_S_ADD_FMT_1(T, x, y)
>
> @@ -162,6 +173,9 @@ sat_s_add_##T##_fmt_3 (T x, T y)
>  \
>  #define RUN_SAT_S_ADD_FMT_3(T, x, y) sat_s_add_##T##_fmt_3(x, y)
>  #define RUN_SAT_S_ADD_FMT_3_WRAP(T, x, y) RUN_SAT_S_ADD_FMT_3(T, x, y)
>
> +#define RUN_SAT_S_ADD_FMT_4(T, x, y) sat_s_add_##T##_fmt_4(x, y)
> +#define RUN_SAT_S_ADD_FMT_4_WRAP(T, x, y) RUN_SAT_S_ADD_FMT_4(T, x, y)
> +
>
>  
> /**/
>  /* Saturation Sub (Unsigned and Signed)
>  */
>
>  
> /**/
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-13.c
> b/gcc/testsuite/gcc.target/riscv/sat_s_add-13.c
> new file mode 100644
> index 000..0923764cde4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-13.c
> @@ -0,0 +1,30 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
> -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "sat_arith.h"
> +
> +/*
> +** sat_s_add_int8_t_fmt_4:
> +** add\s+[atx][0-9]+,\s*a0,\s*a1
> +** xor\s+[atx][0-9]+,\s*a0,\s*a1
> +** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
> +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7
> +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*7
> +** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
> 

Re: [PATCH v1 1/2] RISC-V: Add testcases for form 3 of signed scalar SAT_ADD

[Kito Cheng]

LGTM

 於 2024年9月20日 週五 10:19 寫道：

> From: Pan Li 
>
> This patch would like to add testcases of the signed scalar SAT_ADD
> for form 3.  Aka:
>
> Form 3:
>   #define DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)   \
>   T __attribute__((noinline))\
>   sat_s_add_##T##_fmt_3 (T x, T y)   \
>   {  \
> T sum;   \
> bool overflow = __builtin_add_overflow (x, y, &sum); \
> return overflow ? x < 0 ? MIN : MAX : sum;   \
>   }
>
> DEF_SAT_S_ADD_FMT_3 (int64_t, uint64_t, INT64_MIN, INT64_MAX)
>
> The below test are passed for this patch.
> * The rv64gcv fully regression test.
>
> It is test only patch and obvious up to a point, will commit it
> directly if no comments in next 48H.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/sat_arith.h: Add test helper macros.
> * gcc.target/riscv/sat_s_add-10.c: New test.
> * gcc.target/riscv/sat_s_add-11.c: New test.
> * gcc.target/riscv/sat_s_add-12.c: New test.
> * gcc.target/riscv/sat_s_add-9.c: New test.
> * gcc.target/riscv/sat_s_add-run-10.c: New test.
> * gcc.target/riscv/sat_s_add-run-11.c: New test.
> * gcc.target/riscv/sat_s_add-run-12.c: New test.
> * gcc.target/riscv/sat_s_add-run-9.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/testsuite/gcc.target/riscv/sat_arith.h| 14 
>  gcc/testsuite/gcc.target/riscv/sat_s_add-10.c | 32 +++
>  gcc/testsuite/gcc.target/riscv/sat_s_add-11.c | 31 ++
>  gcc/testsuite/gcc.target/riscv/sat_s_add-12.c | 29 +
>  gcc/testsuite/gcc.target/riscv/sat_s_add-9.c  | 30 +
>  .../gcc.target/riscv/sat_s_add-run-10.c   | 16 ++
>  .../gcc.target/riscv/sat_s_add-run-11.c   | 16 ++
>  .../gcc.target/riscv/sat_s_add-run-12.c   | 16 ++
>  .../gcc.target/riscv/sat_s_add-run-9.c| 16 ++
>  9 files changed, 200 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-10.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-11.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-12.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-9.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-10.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-11.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-12.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_s_add-run-9.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
> b/gcc/testsuite/gcc.target/riscv/sat_arith.h
> index b4fbf5dc662..ab141bb1779 100644
> --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
> +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
> @@ -142,12 +142,26 @@ sat_s_add_##T##_fmt_2 (T x, T y) \
>return x < 0 ? MIN : MAX;  \
>  }
>
> +#define DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)   \
> +T __attribute__((noinline))\
> +sat_s_add_##T##_fmt_3 (T x, T y)   \
> +{  \
> +  T sum;   \
> +  bool overflow = __builtin_add_overflow (x, y, &sum); \
> +  return overflow ? x < 0 ? MIN : MAX : sum;   \
> +}
> +#define DEF_SAT_S_ADD_FMT_3_WRAP(T, UT, MIN, MAX) \
> +  DEF_SAT_S_ADD_FMT_3(T, UT, MIN, MAX)
> +
>  #define RUN_SAT_S_ADD_FMT_1(T, x, y) sat_s_add_##T##_fmt_1(x, y)
>  #define RUN_SAT_S_ADD_FMT_1_WRAP(T, x, y) RUN_SAT_S_ADD_FMT_1(T, x, y)
>
>  #define RUN_SAT_S_ADD_FMT_2(T, x, y) sat_s_add_##T##_fmt_2(x, y)
>  #define RUN_SAT_S_ADD_FMT_2_WRAP(T, x, y) RUN_SAT_S_ADD_FMT_2(T, x, y)
>
> +#define RUN_SAT_S_ADD_FMT_3(T, x, y) sat_s_add_##T##_fmt_3(x, y)
> +#define RUN_SAT_S_ADD_FMT_3_WRAP(T, x, y) RUN_SAT_S_ADD_FMT_3(T, x, y)
> +
>
>  
> /**/
>  /* Saturation Sub (Unsigned and Signed)
>  */
>
>  
> /**/
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_s_add-10.c
> b/gcc/testsuite/gcc.target/riscv/sat_s_add-10.c
> new file mode 100644
> index 000..45329619f9d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_s_add-10.c
> @@ -0,0 +1,32 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
> -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "sat_arith.h"
> +
> +/*
> +** sat_s_add_int16_t_fmt_3:
> +** add\s+[atx][0-9]+,\s*a0,\s*a1
> +** xor\s+[atx][0-9]+,\s*a0,\s*a1
> +** xor\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
> +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15
> +** srli\s+[atx][0-9]+,\s*[atx][0-9]+,\s*15
> +** xori\s+[atx][0-9]+,\s*[atx][0-9]+,\s*1
> +

Re: [PATCH] RISC-V: Allow zero operand for DI variants of vssubu.vx

[Kito Cheng]

LGTM, thanks :)

Bohan Lei  於 2024年9月18日 週三 05:28 寫道：

> The RISC-V vector machine description relies on the helper function
> `sew64_scalar_helper` to emit actual insns for the DI variants of
> vssub.vx and vssubu.vx.  This works with vssub.vx, but can cause
> problems with vssubu.vx with the scalar operand being constant zero,
> because `has_vi_variant_p` returns false, and the operand will be taken
> without being loaded into a reg.  The attached testcases can cause an
> internal compiler error as a result.
>
> Allowing a constant zero operand in those insns seems to be a simple
> solution that only affects minimum existing code.
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md: Allow zero operand for DI variants of
> vssubu.vx
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/vssubu-1.c: New test.
> * gcc.target/riscv/rvv/base/vssubu-2.c: New test.
> ---
>  gcc/config/riscv/vector.md |  8 
>  gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c | 11 +++
>  gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c | 11 +++
>  3 files changed, 26 insertions(+), 4 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c
>
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index d0677325ba1..66a2a477faf 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -4400,10 +4400,10 @@ (define_insn "*pred__scalar"
>   (sat_int_minus_binop:VI_D
> (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")
> (vec_duplicate:VI_D
> - (match_operand: 4 "register_operand"  "  r,  r,  r,
> r")))
> + (match_operand: 4 "reg_or_0_operand"  "  rJ, rJ, rJ,
> rJ")))
>   (match_operand:VI_D 2 "vector_merge_operand"   " vu,  0, vu,
> 0")))]
>"TARGET_VECTOR"
> -  "v.vx\t%0,%3,%4%p1"
> +  "v.vx\t%0,%3,%z4%p1"
>[(set_attr "type" "")
> (set_attr "mode" "")])
>
> @@ -4422,10 +4422,10 @@ (define_insn "*pred__extended_scalar"
> (match_operand:VI_D 3 "register_operand" " vr, vr, vr,
> vr")
> (vec_duplicate:VI_D
>   (sign_extend:
> -   (match_operand: 4 "register_operand" "  r,  r,
> r,  r"
> +   (match_operand: 4 "reg_or_0_operand" "  rJ, rJ,
> rJ, rJ"
>   (match_operand:VI_D 2 "vector_merge_operand"   " vu,  0,
> vu,  0")))]
>"TARGET_VECTOR && !TARGET_64BIT"
> -  "v.vx\t%0,%3,%4%p1"
> +  "v.vx\t%0,%3,%z4%p1"
>[(set_attr "type" "")
> (set_attr "mode" "")])
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c
> new file mode 100644
> index 000..f19b42aed04
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-1.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv64gcv -mabi=lp64d" } */
> +
> +#include 
> +
> +vuint64m1_t test_vssubu_vx_u64m1(vuint64m1_t op1)
> +{
> +  return __riscv_vssubu_vx_u64m1(op1,0,0);
> +}
> +
> +/* { dg-final { scan-assembler-not {\tvssubu} } } */
> \ No newline at end of file
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c
> new file mode 100644
> index 000..cb4e4f48a9b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vssubu-2.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv32gcv -mabi=ilp32d" } */
> +
> +#include 
> +
> +vuint64m1_t test_vssubu_vx_u64m1(vuint64m1_t op1)
> +{
> +  return __riscv_vssubu_vx_u64m1(op1,0,0);
> +}
> +
> +/* { dg-final { scan-assembler-not {\tvssubu} } } */
> \ No newline at end of file
> --
> 2.46.0
>
>

Re: [PATCH] riscv: Fix duplicate assmbler label in @tlsdesc insn

[Kito Cheng]

LGTM, thanks :)

Andreas Schwab  於 2024年9月16日 週一 10:21 寫道：

> Use %= instead of maintaining a sequence number manually, so that it
> doesn't result in a duplicate assembler label when the insn is duplicated.
>
> PR target/116693
> * config/riscv/riscv.cc (riscv_legitimize_tls_address): Don't pass
> seqno to gen_tlsdesc and remove it.
> * config/riscv/riscv.md (@tlsdesc): Remove operand 1.  Use
> %= instead of %1 in template.
> ---
>  gcc/config/riscv/riscv.cc |  4 +---
>  gcc/config/riscv/riscv.md | 15 +++
>  2 files changed, 8 insertions(+), 11 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 6efe14ff199..fbf2da71e10 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -2779,14 +2779,12 @@ riscv_legitimize_tls_address (rtx loc)
>  case TLS_MODEL_GLOBAL_DYNAMIC:
>if (TARGET_TLSDESC)
> {
> - static unsigned seqno;
>   tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM);
>   a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST);
>   dest = gen_reg_rtx (Pmode);
>
> - emit_insn (gen_tlsdesc (Pmode, loc, GEN_INT (seqno)));
> + emit_insn (gen_tlsdesc (Pmode, loc));
>   emit_insn (gen_add3_insn (dest, a0, tp));
> - seqno++;
> }
>else
> {
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 9f94b5aa023..fd1cbebc435 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -2327,17 +2327,16 @@
>
>  (define_insn "@tlsdesc"
>[(set (reg:P A0_REGNUM)
> -   (unspec:P
> -   [(match_operand:P 0 "symbolic_operand" "")
> -(match_operand:P 1 "const_int_operand")]
> -   UNSPEC_TLSDESC))
> +   (unspec:P
> +   [(match_operand:P 0 "symbolic_operand" "")]
> +   UNSPEC_TLSDESC))
> (clobber (reg:P T0_REGNUM))]
>"TARGET_TLSDESC"
>{
> -return ".LT%1: auipc\ta0,%%tlsdesc_hi(%0)\;"
> -   "\tt0,%%tlsdesc_load_lo(.LT%1)(a0)\;"
> -   "addi\ta0,a0,%%tlsdesc_add_lo(.LT%1)\;"
> -   "jalr\tt0,t0,%%tlsdesc_call(.LT%1)";
> +return ".LT%=: auipc\ta0,%%tlsdesc_hi(%0)\;"
> +   "\tt0,%%tlsdesc_load_lo(.LT%=)(a0)\;"
> +   "addi\ta0,a0,%%tlsdesc_add_lo(.LT%=)\;"
> +   "jalr\tt0,t0,%%tlsdesc_call(.LT%=)";
>}
>[(set_attr "type" "multi")
> (set_attr "length" "16")
> --
> 2.46.1
>
>
> --
> Andreas Schwab, SUSE Labs, sch...@suse.de
> GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
> "And now for something completely different."
>

Re: [PATCH] RISC-V: Lookup reversely in riscv_select_multilib_by_abi

[Kito Cheng]

LGTM, thanks for catching this, but commit log seems not right?
should it be -print-multi-directory or -print-multi-os-directory
rather than --print-multilib-os-dir?
(I guess should be -print-multi-directory per your output)

Anyway, you can go ahead and push that after the fix:)


On Thu, Sep 5, 2024 at 3:30 PM YunQiang Su  wrote:
>
> From: YunQiang Su 
>
> When use --print-multilib-os-dir, gcc outputs different value
> with full -march option and the base one only.
>
> $ ./gcc/xgcc --print-multilib-os-dir -mabi=lp64d -march=rv64gc
> lib64/lp64d
>
> $ ./gcc/xgcc --print-multilib-os-dir -mabi=lp64d -march=rv64gc_zba
> .
>
> The reason is that in multilib.h, the fallback value of multilib
> is listed as the 1st one in `multilib_raw[]`.
>
> gcc
> * common/config/riscv/riscv-common.cc(riscv_select_multilib_by_abi):
> look up reversely as the fallback path is listed as the 1st one.
> ---
>  gcc/common/config/riscv/riscv-common.cc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 62c6e1dab1f..2c1ce7fc7cb 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -2079,7 +2079,7 @@ riscv_select_multilib_by_abi (
>const std::string &riscv_current_abi_str,
>const std::vector &multilib_infos)
>  {
> -  for (size_t i = 0; i < multilib_infos.size (); ++i)
> +  for (ssize_t i = multilib_infos.size (); i >= 0; --i)
>  if (riscv_current_abi_str == multilib_infos[i].abi_str)
>return xstrdup (multilib_infos[i].path.c_str ());
>
> --
> 2.39.3 (Apple Git-146)
>

Re: [RFC PATCH] RISC-V: Add support for LP64DV

[Kito Cheng]

Just remember adding a system wide vector calling convention has wide
compatible issues we need to worry about, like jump buf (for
setjmp/longjmp) will need to keep vector status, it doesn't need to
keep before since all vectors are call-clobber by default.

Also that may cause performance issue for vector, that will increase
the init cost for vector register - because part of vector reg become
callee save register now, so most case in current vector code gen
don't need backup/restore at prologue/epilogue, but it will change
once we change the default to vector calling convention by default.

So I would suggest system wilde should still keep using lp64d even
though the vector is available as one of the proposers for the vector
calling convention, but I am fine if the intention is having an option
to do some exercise or experiment.

On Thu, Sep 5, 2024 at 6:56 AM Jeff Law  wrote:
>
>
>
> On 9/4/24 2:26 PM, Palmer Dabbelt wrote:
> > Now that we've got the riscv_vector_cc attribute it's pretty much free
> > to add a system-wide ABI -- at least in terms of implementation.  So
> > this just adds a new ABI command-line value that defaults to enabling
> > the vector calling convention, essentially the same as scattering the
> > attribute on every function.
> >
> > gcc/ChangeLog:
> >
> >   * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add LP64DV.
> >   * config/riscv/riscv-d.cc (riscv_d_handle_target_float_abi):
> >   Likewise.
> >   * config/riscv/riscv-opts.h (enum riscv_abi_type): Likewise.
> >   * config/riscv/riscv.cc (riscv_vector_cc_function_p): Use
> >   LP64DV.
> >   (riscv_option_override): Likewise.
> >   * config/riscv/riscv.opt: Add LP64DV.
> >
> > gcc/testsuite/ChangeLog:
> >
> >   * gcc.target/riscv/rvv/base/lp64dv.c: New test.
> > ---
> > So this is very much an RFC, again.  As such it's basically not tested,
> > I just manually inspected the test case and it looks sane.
> >
> > This concept of a yes-V-by-default ABI has come up a bunch of times.
> > There's some marginal performance benefit here (the added test saves a
> > stack spill, for example).  I have no idea how exciting this would be in
> > real code, but I don't think having autovectorized values with lifetimes
> > that cross function calls is super esoteric or anything.  The
> > implementation is basically free, though, and it seems kind of odd to
> > just leave some performance on the floor for the sake of compatibility
> > with the pre-official distro ABIs.
> Well, that's really the question, isn't it.  Will the distros pick it up
> or not?  If they don't, then it's just an academic exercise.  I don't
> think we've ever managed to get any kind of distro level buy-in on a
> baseline architecture.
>
> So I don't object to the idea, I just don't know if it's going to end up
> being a dead end of effort or not.
>
> jeff
>

Re: [PATCH v4] RISC-V: Supports Profiles in '-march' option.

[Kito Cheng]

I don't see there is conflict if we want to support both gnu2024 and
RVI profiles?
also I am not sure what the usage scenarios for the gnu2024 and how we
defined that?


On Wed, Sep 4, 2024 at 6:49 AM Palmer Dabbelt  wrote:
>
> On Tue, 20 Aug 2024 23:18:36 PDT (-0700), jia...@iscas.ac.cn wrote:
> >
> > 在 2024/8/21 3:23, Palmer Dabbelt 写道:
> >> On Mon, 19 Aug 2024 21:53:54 PDT (-0700), jia...@iscas.ac.cn wrote:
> >>> Supports RISC-V profiles[1] in -march option.
> >>>
> >>> Default input set the profile before other formal extensions.
> >>>
> >>> V2: Fixes some format errors and adds code comments for parse function
> >>> Thanks for Jeff Law's review and comments.
> >>>
> >>> V3: Update testcases and profiles extensions support.Remove S/M mode
> >>> Profiles.
> >>> Thanks for Christoph Müllner,Palmer Dabbelt's  review and comments.
> >>>
> >>> V4: Fix format issue, adjust test name.
> >>>
> >>> [1]https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc
> >>>
> >>> gcc/ChangeLog:
> >>>
> >>> * common/config/riscv/riscv-common.cc (struct riscv_profiles):
> >>> * New struct.
> >>> (riscv_subset_list::parse_profiles): New function.
> >>> (riscv_subset_list::parse_base_ext): New process.
> >>> * config/riscv/riscv-subset.h: New protype.
> >>>
> >>> gcc/testsuite/ChangeLog:
> >>>
> >>> * gcc.target/riscv/arch-44.c: New test.
> >>> * gcc.target/riscv/arch-45.c: New test.
> >>> * gcc.target/riscv/arch-46.c: New test.
> >>>
> >>> ---
> >>>  gcc/common/config/riscv/riscv-common.cc  | 75 +++-
> >>>  gcc/config/riscv/riscv-subset.h  |  2 +
> >>>  gcc/testsuite/gcc.target/riscv/arch-44.c |  5 ++
> >>>  gcc/testsuite/gcc.target/riscv/arch-45.c | 12 
> >>>  gcc/testsuite/gcc.target/riscv/arch-46.c | 12 
> >>>  5 files changed, 105 insertions(+), 1 deletion(-)
> >>>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-44.c
> >>>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-45.c
> >>>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-46.c
> >>>
> >>> diff --git a/gcc/common/config/riscv/riscv-common.cc
> >>> b/gcc/common/config/riscv/riscv-common.cc
> >>> index 62c6e1dab1f..0bad4426971 100644
> >>> --- a/gcc/common/config/riscv/riscv-common.cc
> >>> +++ b/gcc/common/config/riscv/riscv-common.cc
> >>> @@ -234,6 +234,12 @@ struct riscv_ext_version
> >>>int minor_version;
> >>>  };
> >>>
> >>> +struct riscv_profiles
> >>> +{
> >>> +  const char *profile_name;
> >>> +  const char *profile_string;
> >>> +};
> >>> +
> >>>  /* All standard extensions defined in all supported ISA spec. */
> >>>  static const struct riscv_ext_version riscv_ext_version_table[] =
> >>>  {
> >>> @@ -449,6 +455,31 @@ static const struct riscv_ext_version
> >>> riscv_combine_info[] =
> >>>{NULL, ISA_SPEC_CLASS_NONE, 0, 0}
> >>>  };
> >>>
> >>> +/* This table records the mapping form RISC-V Profiles into march
> >>> string.  */
> >>> +static const riscv_profiles riscv_profiles_table[] =
> >>> +{
> >>> +  /* RVI20U only contains the base extension 'i' as mandatory
> >>> extension.  */
> >>> +  {"RVI20U64", "rv64i"},
> >>> +  {"RVI20U32", "rv32i"},
> >>> +
> >>> +  /* RVA20U contains the
> >>> 'i,m,a,f,d,c,zicsr,zicntr,ziccif,ziccrse,ziccamoa,
> >>> + zicclsm,za128rs' as mandatory extensions.  */
> >>> +  {"RVA20U64", "rv64imafdc_zicsr_zicntr_ziccif_ziccrse_ziccamoa"
> >>> +   "_zicclsm_za128rs"},
> >>> +
> >>> +  /* RVA22U contains the
> >>> 'i,m,a,f,d,c,zicsr,zihintpause,zba,zbb,zbs,zicntr,
> >>> + zihpm,ziccif,ziccrse,ziccamoa,
> >>> zicclsm,zic64b,za64rs,zicbom,zicbop,zicboz,
> >>
> >> Except at least the Spacemit stuff that claims RVA22 doesn't actually
> >> have Zicclsm, at least assuming the "supports" in there means "doesn't
> >> trap" (we could just say "supports" includes traps, and thus Zicclsm
> >> means nothing).
> >>
> >> I'd argue we should just punt on the profiles until we figure out what
> >> they're actually going to be.  The pre-23 profiles were all minor
> >> releases anyway, so it's not like we should be losing much there (as
> >> they're not meant for software).  At least if we wait we don't end up
> >> committing to this whole "profiles don't mean anything" spot we're in,
> >> like we did for the other spec flavors.
> >>
> >> Though now that I'm writing that it actually just sounds kind of silly
> >> to keep hoping that we're going to get any meaningful compatibility
> >> rules enforced by the RISC-V foundation.  There's really just no
> >> incentive for that to happen, as we keep bailing out vendors who ship
> >> broken systems and thus there's no pushback from their members.
> >>
> >> So maybe the right answer here is to just break users and tell them to
> >> go complain to someone else?  At least that way everyone will be
> >> upset, maybe that'll be enough to get things to change?
> >
> > Okay, let's continue to wait for the RVA/B23 forzen.
>
> I actually don't think that's going to change anything.  The problem
> here 

Re: [PATCH] RISC-V: Add missing mode_idx for vrol and vror

[Kito Cheng]

committed to trunk.

> You don't need an OK of course but LGTM.
>
> When I found another instance of this I was thinking about having
> exhaustive self tests for those attributes.  Maybe a good learning
> exercise?

Yeah, that would be great, otherwise it's not really easy to maintain
those attributes right :(


>
> --
> Regards
>  Robin
>

[PATCH] RISC-V: Add missing mode_idx for vrol and vror

[Kito Cheng]

We add pattern for vector rotate, but seems like we forgot adding
mode_idx which used in AVL propgation (riscv-avlprop.cc).

gcc/ChangeLog:

* config/riscv/vector.md (mode_idx): Add vrol and vror.

gcctestsuite/ChangeLog:

* gcc.target/riscv/rvv/autovec/rotr.c: New.
---
 gcc/config/riscv/vector.md|  2 +-
 gcc/testsuite/gcc.target/riscv/rvv/autovec/rotr.c | 13 +
 2 files changed, 14 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/rotr.c

diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 666719330c6..d0677325ba1 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -816,7 +816,7 @@
vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\

vfcvtitof,vfncvtitof,vfncvtftoi,vfncvtftof,vmalu,vmiota,vmidx,\

vimovxv,vfmovfv,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\
-   
vgather,vcompress,vmov,vnclip,vnshift,vandn,vcpop,vclz,vctz")
+   
vgather,vcompress,vmov,vnclip,vnshift,vandn,vcpop,vclz,vctz,vrol,vror")
   (const_int 0)
 
   (eq_attr "type" "vimovvx,vfmovvf")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/rotr.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/rotr.c
new file mode 100644
index 000..055b28d1e78
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/rotr.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvbb -mabi=lp64d -fno-vect-cost-model 
-mrvv-vector-bits=zvl" } */
+
+typedef int a;
+void *b;
+a c;
+void d() {
+  a e = c, f =0;
+  short *g = b;
+  for (; f < e; f++)
+*(g + f) = (255 & (*(g + f) >> 8)) | *(g + f) << 8;
+}
+
-- 
2.34.1

Re: [PATCH] RISC-V: Optimize the cost of the DFmode register move for RV32.

[Kito Cheng]

LGTM, good catch, and I am a little suppressed that we don't handle
"case REG" in riscv_rtx_costs...but adding that might disturb too much
at once, so this fix is fine for now, and ...and I guess we should
improve that in future.


On Tue, Aug 27, 2024 at 5:19 PM Xianmiao Qu  wrote:
>
> Currently, in RV32, even with the D extension enabled, the cost of DFmode
> register moves is still set to 'COSTS_N_INSNS (2)'. This results in the
> 'lower-subreg' pass splitting DFmode register moves into two SImode SUBREG
> register moves, leading to the generation of many redundant instructions.
>
> As an example, consider the following test case:
>   double foo (int t, double a, double b)
>   {
> if (t > 0)
>   return a;
> else
>   return b;
>   }
>
> When compiling with -march=rv32imafdc -mabi=ilp32d, the following code is 
> generated:
>   .cfi_startproc
>   addisp,sp,-32
>   .cfi_def_cfa_offset 32
>   fsd fa0,8(sp)
>   fsd fa1,16(sp)
>   lw  a4,8(sp)
>   lw  a5,12(sp)
>   lw  a2,16(sp)
>   lw  a3,20(sp)
>   bgt a0,zero,.L1
>   mv  a4,a2
>   mv  a5,a3
>   .L1:
>   sw  a4,24(sp)
>   sw  a5,28(sp)
>   fld fa0,24(sp)
>   addisp,sp,32
>   .cfi_def_cfa_offset 0
>   jr  ra
>   .cfi_endproc
>
> After adjust the DFmode register move's cost to 'COSTS_N_INSNS (1)', the
> generated code is as follows, with a significant reduction in the number
> of instructions.
>   .cfi_startproc
>   ble a0,zero,.L5
>   ret
>   .L5:
>   fmv.d   fa0,fa1
>   ret
>   .cfi_endproc
>
> gcc/
> * config/riscv/riscv.cc (riscv_rtx_costs): Optimize the cost of the
> DFmode register move for RV32.
>
> gcc/testsuite/
> * gcc.target/riscv/rv32-movdf-cost.c: New test.
> ---
>  gcc/config/riscv/riscv.cc|  5 +
>  gcc/testsuite/gcc.target/riscv/rv32-movdf-cost.c | 13 +
>  2 files changed, 18 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rv32-movdf-cost.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 1f544c1287ec..a47dedf73c10 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -3560,6 +3560,11 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
> outer_code, int opno ATTRIBUTE_UN
>if (outer_code == INSN
>   && register_operand (SET_DEST (x), GET_MODE (SET_DEST (x
> {
> + if (REG_P (SET_SRC (x)) && TARGET_DOUBLE_FLOAT && mode == DFmode)
> +   {
> + *total = COSTS_N_INSNS (1);
> + return true;
> +   }
>   riscv_rtx_costs (SET_SRC (x), mode, outer_code, opno, total, speed);
>   return true;
> }
> diff --git a/gcc/testsuite/gcc.target/riscv/rv32-movdf-cost.c 
> b/gcc/testsuite/gcc.target/riscv/rv32-movdf-cost.c
> new file mode 100644
> index ..cb679e7b95fb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rv32-movdf-cost.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32imafdc -mabi=ilp32d" } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" } } */
> +
> +double foo (int t, double a, double b)
> +{
> +  if (t > 0)
> +return a;
> +  else
> +return b;
> +}
> +
> +/* { dg-final { scan-assembler-not "fsd\t" } } */
> --
> 2.43.0
>

Re: [PATCH] RISC-V: Expand vec abs without masking.

[Kito Cheng]

LGTM

Robin Dapp  於 2024年8月23日 週五 00:04 寫道：

> Hi,
>
> standard abs synthesis during expand is max (a, -a).  This
> expansion has the advantage of avoiding masking and is thus potentially
> faster than the a < 0 ? -a : a synthesis.
>
> Regtested on rv64gcv_zvfh_zvbb.
>
> Regards
>  Robin
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md (abs2): Expand via max (a, -a).
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/unop/abs-rv32gcv.c: Adjust test
> expectation.
> * gcc.target/riscv/rvv/autovec/unop/abs-rv64gcv.c: Ditto.
> * gcc.target/riscv/rvv/autovec/vls/abs-2.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-3.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-4.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-5.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-6.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-7.c: Ditto.
> * gcc.target/riscv/rvv/autovec/cond/cond_unary-8.c: Ditto.
> ---
>  gcc/config/riscv/autovec.md   | 26 ++-
>  .../riscv/rvv/autovec/cond/cond_unary-1.c |  6 +++--
>  .../riscv/rvv/autovec/cond/cond_unary-2.c |  6 +++--
>  .../riscv/rvv/autovec/cond/cond_unary-3.c |  6 +++--
>  .../riscv/rvv/autovec/cond/cond_unary-4.c |  6 +++--
>  .../riscv/rvv/autovec/cond/cond_unary-5.c |  6 +++--
>  .../riscv/rvv/autovec/cond/cond_unary-6.c |  6 +++--
>  .../riscv/rvv/autovec/cond/cond_unary-7.c |  6 +++--
>  .../riscv/rvv/autovec/cond/cond_unary-8.c |  6 +++--
>  .../riscv/rvv/autovec/unop/abs-rv32gcv.c  |  6 ++---
>  .../riscv/rvv/autovec/unop/abs-rv64gcv.c  |  6 ++---
>  .../gcc.target/riscv/rvv/autovec/vls/abs-2.c  |  2 +-
>  12 files changed, 47 insertions(+), 41 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index bf1651de60a..6544ac78c9c 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1073,29 +1073,19 @@ (define_insn_and_split "2"
>  [(set_attr "type" "vialu")])
>
>  ;;
> ---
> -;; - [INT] ABS expansion to vmslt and vneg.
> +;; - [INT] ABS expansion to vneg and vmax.
>  ;;
> ---
>
> -(define_insn_and_split "abs2"
> +(define_expand "abs2"
>[(set (match_operand:V_VLSI 0 "register_operand")
> - (abs:V_VLSI
> -   (match_operand:V_VLSI 1 "register_operand")))]
> -  "TARGET_VECTOR && can_create_pseudo_p ()"
> -  "#"
> -  "&& 1"
> -  [(const_int 0)]
> +(smax:V_VLSI
> + (match_dup 0)
> + (neg:V_VLSI
> +   (match_operand:V_VLSI 1 "register_operand"]
> +  "TARGET_VECTOR"
>  {
> -  rtx zero = gen_const_vec_duplicate (mode, GEN_INT (0));
> -  machine_mode mask_mode = riscv_vector::get_mask_mode (mode);
> -  rtx mask = gen_reg_rtx (mask_mode);
> -  riscv_vector::expand_vec_cmp (mask, LT, operands[1], zero);
> -
> -  rtx ops[] = {operands[0], mask, operands[1], operands[1]};
> -  riscv_vector::emit_vlmax_insn (code_for_pred (NEG, mode),
> -  riscv_vector::UNARY_OP_TAMU, ops);
>DONE;
> -}
> -[(set_attr "type" "vector")])
> +})
>
>  ;;
> ---
>  ;;  [FP] Unary operations
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
> index 2233c6eeecb..4866b221ca4 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-1.c
> @@ -36,8 +36,10 @@
>
>  TEST_ALL (DEF_LOOP)
>
> -/* NOTE: int abs operator is converted to vmslt + vneg.v */
> -/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 8
> } } */
> +/* NOTE: int abs operator is converted to vneg.v + vmax.vv */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+} 8 } } */
> +/* { dg-final { scan-assembler-times
> {\tvmax\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-times {\tvneg\.v\tv[0-9]+,v[0-9]+,v0\.t} 4
> } } */
>  /* { dg-final { scan-assembler-times {\tvnot\.v\tv[0-9]+,v[0-9]+,v0\.t} 4
> } } */
>  /* { dg-final { scan-assembler-times {\tvfabs\.v\tv[0-9]+,v[0-9]+,v0\.t}
> 3 } } */
>  /* { dg-final { scan-assembler-times {\tvfneg\.v\tv[0-9]+,v[0-9]+,v0\.t}
> 3 } } */
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
> index 4886bff67d8..651df9f8646 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_unary-2.c
> @@

Re: [PATCH v1 2/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 3

[Kito Cheng]

LGTM

 於 2024年8月17日 週六 19:37 寫道：

> From: Pan Li 
>
> This patch would like to add test cases for the unsigned scalar
> .SAT_TRUNC form 3.  Aka:
>
> Form 3:
>   #define DEF_SAT_U_TRUC_FMT_3(NT, WT) \
>   NT __attribute__((noinline)) \
>   sat_u_truc_##WT##_to_##NT##_fmt_3 (WT x) \
>   {\
> WT max = (WT)(NT)-1;   \
> return x <= max ? (NT)x : (NT) max;\
>   }
>
> DEF_SAT_U_TRUC_FMT_3 (uint32_t, uint64_t)
>
> The below test is passed for this patch.
> * The rv64gcv regression test.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/sat_arith.h: Add test helper macros.
> * gcc.target/riscv/sat_u_trunc-13.c: New test.
> * gcc.target/riscv/sat_u_trunc-14.c: New test.
> * gcc.target/riscv/sat_u_trunc-15.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-13.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-14.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-15.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/testsuite/gcc.target/riscv/sat_arith.h| 12 +++
>  .../gcc.target/riscv/sat_u_trunc-13.c | 17 
>  .../gcc.target/riscv/sat_u_trunc-14.c | 20 +++
>  .../gcc.target/riscv/sat_u_trunc-15.c | 19 ++
>  .../gcc.target/riscv/sat_u_trunc-run-13.c | 16 +++
>  .../gcc.target/riscv/sat_u_trunc-run-14.c | 16 +++
>  .../gcc.target/riscv/sat_u_trunc-run-15.c | 16 +++
>  7 files changed, 116 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-15.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-13.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-14.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-15.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
> b/gcc/testsuite/gcc.target/riscv/sat_arith.h
> index 576a4926d1f..cf055410fd1 100644
> --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
> +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
> @@ -236,10 +236,22 @@ sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
>  }
>  #define DEF_SAT_U_TRUC_FMT_2_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_2(NT, WT)
>
> +#define DEF_SAT_U_TRUC_FMT_3(NT, WT) \
> +NT __attribute__((noinline)) \
> +sat_u_truc_##WT##_to_##NT##_fmt_3 (WT x) \
> +{\
> +  WT max = (WT)(NT)-1;   \
> +  return x <= max ? (NT)x : (NT) max;\
> +}
> +#define DEF_SAT_U_TRUC_FMT_3_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_3(NT, WT)
> +
>  #define RUN_SAT_U_TRUC_FMT_1(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_1
> (x)
>  #define RUN_SAT_U_TRUC_FMT_1_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_1(NT, WT,
> x)
>
>  #define RUN_SAT_U_TRUC_FMT_2(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_2
> (x)
>  #define RUN_SAT_U_TRUC_FMT_2_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_2(NT, WT,
> x)
>
> +#define RUN_SAT_U_TRUC_FMT_3(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_3
> (x)
> +#define RUN_SAT_U_TRUC_FMT_3_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_3(NT, WT,
> x)
> +
>  #endif
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c
> b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c
> new file mode 100644
> index 000..58910793a80
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-13.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
> -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "sat_arith.h"
> +
> +/*
> +** sat_u_truc_uint16_t_to_uint8_t_fmt_3:
> +** sltiu\s+[atx][0-9]+,\s*a0,\s*255
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
> +** ret
> +*/
> +DEF_SAT_U_TRUC_FMT_3(uint8_t, uint16_t)
> +
> +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c
> b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c
> new file mode 100644
> index 000..236ea1d45f7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-14.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
> -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "sat_arith.h"
> +
> +/*
> +** sat_u_truc_uint32_t_to_uint16_t_fmt_3:
> +** li\s+[atx][0-9]+,\s*65536
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** slli\s+a0,\s*a0,\s*48
> +** srli\s+a0,\s*a0,\s*48
> +**

Re: [PATCH v1 1/2] RISC-V: Add testcases for unsigned scalar .SAT_TRUNC form 2

[Kito Cheng]

LGTM

 於 2024年8月17日 週六 19:37 寫道：

> From: Pan Li 
>
> This patch would like to add test cases for the unsigned scalar
> .SAT_TRUNC form 2.  Aka:
>
> Form 2:
>   #define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
>   NT __attribute__((noinline)) \
>   sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
>   {\
> WT max = (WT)(NT)-1;   \
> return x > max ? (NT) max : (NT)x; \
>   }
>
> DEF_SAT_U_TRUC_FMT_2 (uint32_t, uint64_t)
>
> The below test is passed for this patch.
> * The rv64gcv regression test.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/sat_arith.h: Add test helper macros.
> * gcc.target/riscv/sat_u_trunc-7.c: New test.
> * gcc.target/riscv/sat_u_trunc-8.c: New test.
> * gcc.target/riscv/sat_u_trunc-9.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-7.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-8.c: New test.
> * gcc.target/riscv/sat_u_trunc-run-9.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/testsuite/gcc.target/riscv/sat_arith.h| 12 +++
>  .../gcc.target/riscv/sat_u_trunc-7.c  | 17 
>  .../gcc.target/riscv/sat_u_trunc-8.c  | 20 +++
>  .../gcc.target/riscv/sat_u_trunc-9.c  | 19 ++
>  .../gcc.target/riscv/sat_u_trunc-run-7.c  | 16 +++
>  .../gcc.target/riscv/sat_u_trunc-run-8.c  | 16 +++
>  .../gcc.target/riscv/sat_u_trunc-run-9.c  | 16 +++
>  7 files changed, 116 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-9.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-7.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-8.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/sat_u_trunc-run-9.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h
> b/gcc/testsuite/gcc.target/riscv/sat_arith.h
> index 37e0a60f21b..576a4926d1f 100644
> --- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
> +++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
> @@ -227,7 +227,19 @@ sat_u_truc_##WT##_to_##NT##_fmt_1 (WT x) \
>  }
>  #define DEF_SAT_U_TRUC_FMT_1_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_1(NT, WT)
>
> +#define DEF_SAT_U_TRUC_FMT_2(NT, WT) \
> +NT __attribute__((noinline)) \
> +sat_u_truc_##WT##_to_##NT##_fmt_2 (WT x) \
> +{\
> +  WT max = (WT)(NT)-1;   \
> +  return x > max ? (NT) max : (NT)x; \
> +}
> +#define DEF_SAT_U_TRUC_FMT_2_WRAP(NT, WT) DEF_SAT_U_TRUC_FMT_2(NT, WT)
> +
>  #define RUN_SAT_U_TRUC_FMT_1(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_1
> (x)
>  #define RUN_SAT_U_TRUC_FMT_1_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_1(NT, WT,
> x)
>
> +#define RUN_SAT_U_TRUC_FMT_2(NT, WT, x) sat_u_truc_##WT##_to_##NT##_fmt_2
> (x)
> +#define RUN_SAT_U_TRUC_FMT_2_WRAP(NT, WT, x) RUN_SAT_U_TRUC_FMT_2(NT, WT,
> x)
> +
>  #endif
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c
> b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c
> new file mode 100644
> index 000..95d513a15fb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-7.c
> @@ -0,0 +1,17 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
> -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "sat_arith.h"
> +
> +/*
> +** sat_u_truc_uint16_t_to_uint8_t_fmt_2:
> +** sltiu\s+[atx][0-9]+,\s*a0,\s*255
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** andi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*0xff
> +** ret
> +*/
> +DEF_SAT_U_TRUC_FMT_2(uint8_t, uint16_t)
> +
> +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c
> b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c
> new file mode 100644
> index 000..f168912293d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/sat_u_trunc-8.c
> @@ -0,0 +1,20 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details
> -fno-schedule-insns -fno-schedule-insns2" } */
> +/* { dg-final { check-function-bodies "**" "" } } */
> +
> +#include "sat_arith.h"
> +
> +/*
> +** sat_u_truc_uint32_t_to_uint16_t_fmt_2:
> +** li\s+[atx][0-9]+,\s*65536
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** sltu\s+[atx][0-9]+,\s*a0,\s*[atx][0-9]+
> +** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
> +** or\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
> +** slli\s+a0,\s*a0,\s*48
> +** srli\s+a0,\s*a0,\s*48
> +** ret
> +*/
> +DEF_SAT_U_TRUC_FMT_2(uint16_t, uint32_t)
> +
> +/* { dg-final { scan-rtl-dump-times ".SAT_TRUNC " 2 "expand" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_trun

Re: [PATCH] RISC-V: Fix factor in dwarf_poly_indeterminate_value [PR116305]

[Kito Cheng]

LGTM, thanks for fixing that :)

On Wed, Aug 14, 2024 at 2:06 PM 曾治金  wrote:
>
> This patch is to fix the bug (BugId:116305) introduced by the commit
> bd93ef for risc-v target.
>
> The commit bd93ef changes the chunk_num from 1 to TARGET_MIN_VLEN/128
> if TARGET_MIN_VLEN is larger than 128 in riscv_convert_vector_bits. So
> it changes the value of BYTES_PER_RISCV_VECTOR. For example, before
> merging the commit bd93ef and if TARGET_MIN_VLEN is 256, the value
> of BYTES_PER_RISCV_VECTOR should be [8, 8], but now [16, 16]. The value
> of riscv_bytes_per_vector_chunk and BYTES_PER_RISCV_VECTOR are no longer
> equal.
>
> Prologue will use BYTES_PER_RISCV_VECTOR.coeffs[1] to estimate the vlenb
> register value in riscv_legitimize_poly_move, and dwarf2cfi will also
> get the estimated vlenb register value in riscv_dwarf_poly_indeterminate_value
> to calculate the number of times to multiply the vlenb register value.
>
> So need to change the factor from riscv_bytes_per_vector_chunk to
> BYTES_PER_RISCV_VECTOR, otherwise we will get the incorrect dwarf
> information. The incorrect example as follow:
>
> ```
> csrrt0,vlenb
> sllit1,t0,1
> sub sp,sp,t1
>
> .cfi_escape 0xf,0xb,0x72,0,0x92,0xa2,0x38,0,0x34,0x1e,0x23,0x50,0x22
> ```
>
> The sequence '0x92,0xa2,0x38,0' means the vlenb register, '0x34' means
> the literal 4, '0x1e' means the multiply operation. But in fact, the
> vlenb register value just need to multiply the literal 2.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_dwarf_poly_indeterminate_value):
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/scalable_vector_cfi.c: New test.
>
> Signed-off-by: Zhijin Zeng 
> ---
>  gcc/config/riscv/riscv.cc |  4 +--
>  .../riscv/rvv/base/scalable_vector_cfi.c  | 32 +++
>  2 files changed, 34 insertions(+), 2 deletions(-)
>  create mode 100644 
> gcc/testsuite/gcc.target/riscv/rvv/base/scalable_vector_cfi.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 5fe4273beb7..e740fc159dd 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -10773,12 +10773,12 @@ static unsigned int
>  riscv_dwarf_poly_indeterminate_value (unsigned int i, unsigned int *factor,
>   int *offset)
>  {
> -  /* Polynomial invariant 1 == (VLENB / riscv_bytes_per_vector_chunk) - 1.
> +  /* Polynomial invariant 1 == (VLENB / BYTES_PER_RISCV_VECTOR) - 1.
>   1. TARGET_MIN_VLEN == 32, polynomial invariant 1 == (VLENB / 4) - 1.
>   2. TARGET_MIN_VLEN > 32, polynomial invariant 1 == (VLENB / 8) - 1.
>*/
>gcc_assert (i == 1);
> -  *factor = riscv_bytes_per_vector_chunk;
> +  *factor = BYTES_PER_RISCV_VECTOR.coeffs[1];
>*offset = 1;
>return RISCV_DWARF_VLENB;
>  }
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalable_vector_cfi.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/scalable_vector_cfi.c
> new file mode 100644
> index 000..184da10caf3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalable_vector_cfi.c
> @@ -0,0 +1,32 @@
> +/* { dg-do compile } */
> +/* { dg-options "-g -O3 -march=rv64gcv -mabi=lp64d" } */
> +/* { dg-skip-if "" { *-*-* } {"-O2" "-O1" "-O0" "-Og" "-Oz" "-flto"} } */
> +/* { dg-final { scan-assembler {cfi_escape .*0x92,0xa2,0x38,0,0x32,0x1e} } } 
> */
> +
> +#include "riscv_vector.h"
> +
> +#define PI_2 1.570796326795
> +
> +extern void func(float *result);
> +
> +void test(const float *ys, const float *xs, float *result, size_t length) {
> +size_t gvl = __riscv_vsetvlmax_e32m2();
> +vfloat32m2_t vpi2 = __riscv_vfmv_v_f_f32m2(PI_2, gvl);
> +
> +for(size_t i = 0; i < length;) {
> +gvl = __riscv_vsetvl_e32m2(length - i);
> +vfloat32m2_t y = __riscv_vle32_v_f32m2(ys, gvl);
> +vfloat32m2_t x = __riscv_vle32_v_f32m2(xs, gvl);
> +vbool16_t mask0  = __riscv_vmflt_vv_f32m2_b16(x, y, gvl);
> +vfloat32m2_t fixpi = __riscv_vfrsub_vf_f32m2_mu(mask0, vpi2, vpi2, 
> 0, gvl);
> +
> +__riscv_vse32_v_f32m2(result, fixpi, gvl);
> +
> +func(result);
> +
> +i += gvl;
> +ys += gvl;
> +xs += gvl;
> +result += gvl;
> +}
> +}
> --
> 2.34.1
>
>
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Re: [PATCH] RISC-V: Add --with-cmodel configure option

[Kito Cheng]

compact code mode is our downstream stuffs, so...it should drop it from the
patch

Hau Hsu  於 2024年8月2日 週五 12:17 寫道：

> Sometimes we want to use default cmodel other than medlow. Add a GCC
> configure option for that.
>
> gcc/ChangeLog:
>
> * config.gcc (riscv*-*-*): Add support for --with-cmodel configure
> option.
> * config/riscv/riscv.h (TARGET_RISCV_DEFAULT_CMODEL): Define default
> cmodel.
> * configure: Regenerate.
> * configure.ac: Add --with-cmodel configure option.
> * doc/install.texi: Document --with-cmodel configure option.
> * doc/invoke.texi (-mcmodel): Mention --with-cmodel configure option.
> ---
>  gcc/config.gcc   | 19 +--
>  gcc/config/riscv/riscv.h |  2 ++
>  gcc/configure| 15 +--
>  gcc/configure.ac |  5 +
>  gcc/doc/install.texi |  4 
>  gcc/doc/invoke.texi  |  6 --
>  6 files changed, 45 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/config.gcc b/gcc/config.gcc
> index a36dd1bcbc6..a4537d4b940 100644
> --- a/gcc/config.gcc
> +++ b/gcc/config.gcc
> @@ -4723,7 +4723,7 @@ case "${target}" in
> ;;
>
> riscv*-*-*)
> -   supported_defaults="abi arch tune riscv_attribute isa_spec
> tls"
> +   supported_defaults="abi arch tune riscv_attribute isa_spec
> tls cmodel"
>
> case "${target}" in
> riscv-* | riscv32*) xlen=32 ;;
> @@ -4879,6 +4879,21 @@ case "${target}" in
> exit 1
> esac
> fi
> +
> +   # Handle --with-cmodel.
> +   if test "x${with_cmodel}" != xdefault; then
> +   # Make sure --with-cmodel is valid.  If it was not
> specified,
> +   # use medlow as the default value.
> +   case "${with_cmodel}" in
> +   medlow | medany | compact)
> +   ;;
> +   *)
> +   echo "invalid option for --with-cmodel:
> '${with_cmodel}', available values are 'medlow' 'medany' 'compact'" 1>&2
> +   exit 1
> +   ;;
> +   esac
> +   tm_defines="${tm_defines}
> TARGET_RISCV_DEFAULT_CMODEL=${with_cmodel}"
> +   fi
> ;;
>
> mips*-*-*)
> @@ -6071,7 +6086,7 @@ case ${target} in
>  esac
>
>  t=
> -all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32
> tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt
> synci tls lxc1-sxc1 madd4 isa_spec compact-branches msa"
> +all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32
> tune_64 schedule float mode fpu nan fp_32 odd_spreg_32 divide llsc mips-plt
> synci tls lxc1-sxc1 madd4 isa_spec compact-branches msa cmodel"
>  for option in $all_defaults
>  do
> eval "val=\$with_"`echo $option | sed s/-/_/g`
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index 6f040011864..68173ebccb4 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -65,6 +65,7 @@ extern const char *riscv_arch_help (int argc, const char
> **argv);
> --with-tune is ignored if -mtune or -mcpu is specified.
> --with-isa-spec is ignored if -misa-spec is specified.
> --with-tls is ignored if -mtls-dialect is specified.
> +   --with-cmodel is ignored if -mcmodel is specified.
>
> But using default -march/-mtune value if -mcpu don't have valid
> option.  */
>  #define OPTION_DEFAULT_SPECS \
> @@ -77,6 +78,7 @@ extern const char *riscv_arch_help (int argc, const char
> **argv);
>{"abi", "%{!mabi=*:-mabi=%(VALUE)}" },   \
>{"isa_spec", "%{!misa-spec=*:-misa-spec=%(VALUE)}" },
>   \
>{"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"},\
> +  {"cmodel", "%{!mcmodel=*:-mcmodel=%(VALUE)}" }, \
>
>  #ifdef IN_LIBGCC2
>  #undef TARGET_64BIT
> diff --git a/gcc/configure b/gcc/configure
> index 557ea5fa3ac..826caf8dc2c 100755
> --- a/gcc/configure
> +++ b/gcc/configure
> @@ -1000,6 +1000,7 @@ with_changes_root_url
>  enable_languages
>  with_multilib_list
>  with_multilib_generator
> +with_cmodel
>  with_zstd
>  with_zstd_include
>  with_zstd_lib
> @@ -1880,6 +1881,7 @@ Optional Packages:
>SH and x86-64 only)
>--with-multilib-generator
>Multi-libs configuration string (RISC-V only)
> +  --with-cmodel   Code model configuration string (RISC-V only)
>--with-zstd=PATHspecify prefix directory for installed zstd
> library.
>Equivalent to --with-zstd-include=PATH/include
> plus
>--with-zstd-lib=PATH/lib
> @@ -8381,6 +8383,15 @@ else
>  fi
>
>
> +
> +# Check whether --with-cmodel was given.
> +if test "${with_cmodel+set}" = set; then :
> +  withval=$with_cmod

Re: [PATCH] RISC-V: Reject 'd' extension with ILP32E ABI

[Kito Cheng]

LGTM, although I thought for a few seconds whether to use sorry or
error, but I think we don't really feel sorry for that case, so just
error is fine :P

On Wed, Jul 31, 2024 at 5:33 AM Patrick O'Neill  wrote:
>
> Also add a testcase for -mabi=lp64d where 'd' is required.
>
> gcc/ChangeLog:
>
> PR 116111
> * config/riscv/riscv.cc (riscv_option_override):
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-41.c: New test.
> * gcc.target/riscv/pr116111.c: New test.
>
> Signed-off-by: Patrick O'Neill 
> ---
>  gcc/config/riscv/riscv.cc | 5 +
>  gcc/testsuite/gcc.target/riscv/arch-41.c  | 7 +++
>  gcc/testsuite/gcc.target/riscv/pr116111.c | 7 +++
>  3 files changed, 19 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-41.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/pr116111.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 8ece7859945..b19d56149e7 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -9818,6 +9818,11 @@ riscv_option_override (void)
> error ("rv64e requires lp64e ABI");
>  }
>
> +  /* ILP32E does not support the 'd' extension.  */
> +  if (riscv_abi == ABI_ILP32E && UNITS_PER_FP_REG > 4)
> +error ("ILP32E ABI does not support the %qc extension",
> +  UNITS_PER_FP_REG > 8 ? 'Q' : 'D');
> +
>/* Zfinx require abi ilp32, ilp32e, lp64 or lp64e.  */
>if (TARGET_ZFINX
>&& riscv_abi != ABI_ILP32 && riscv_abi != ABI_LP64
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-41.c 
> b/gcc/testsuite/gcc.target/riscv/arch-41.c
> new file mode 100644
> index 000..699eeb20a58
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-41.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64i -mabi=lp64d" } */
> +int
> +foo ()
> +{}
> +
> +/* { dg-error "requested ABI requires '-march' to subsume the 'D' extension" 
> "" { target *-*-* } 0 } */
> diff --git a/gcc/testsuite/gcc.target/riscv/pr116111.c 
> b/gcc/testsuite/gcc.target/riscv/pr116111.c
> new file mode 100644
> index 000..5c824be2e93
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/pr116111.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32ed -mabi=ilp32e" } */
> +int
> +foo ()
> +{}
> +
> +/* { dg-error "ILP32E ABI does not support the 'D' extension" "" { target 
> *-*-* } 0 } */
> --
> 2.34.1
>

Re: [PATCH] RISC-V: Remove configure check for zabha

[Kito Cheng]

LGTM, thanks :)

On Tue, Jul 30, 2024 at 10:53 AM Patrick O'Neill  wrote:
>
> This patch removes the zabha configure check since it's not a breaking change
> and updates the existing zaamo/zalrsc comment.
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc
>   (riscv_subset_list::to_string): Remove zabha configure check
>   handling and clarify zaamo/zalrsc comment.
> * config.in: Regenerate.
> * configure: Regenerate.
> * configure.ac: Remove zabha configure check.
>
> Signed-off-by: Patrick O'Neill 
> ---
> The user has to specify zabha in order for binutils to throw an error.
> This is in contrast to zaamo/zalrsc which are expanded from 'a' without being
> specified.
>
> Relying on precommit to do testing.
> ---
>  gcc/common/config/riscv/riscv-common.cc | 12 +++---
>  gcc/config.in   |  6 -
>  gcc/configure   | 31 -
>  gcc/configure.ac|  5 
>  4 files changed, 3 insertions(+), 51 deletions(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 682826c0e34..d2912877784 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -855,7 +855,6 @@ riscv_subset_list::to_string (bool version_p) const
>
>bool skip_zifencei = false;
>bool skip_zaamo_zalrsc = false;
> -  bool skip_zabha = false;
>bool skip_zicsr = false;
>bool i2p0 = false;
>
> @@ -884,13 +883,11 @@ riscv_subset_list::to_string (bool version_p) const
>skip_zifencei = true;
>  #endif
>  #ifndef HAVE_AS_MARCH_ZAAMO_ZALRSC
> -  /* Skip since binutils 2.42 and earlier don't recognize zaamo/zalrsc.  */
> +  /* Skip since binutils 2.42 and earlier don't recognize zaamo/zalrsc.
> + Expanding 'a' to zaamo/zalrsc would otherwise break compilations
> + for users with an older version of binutils.  */
>skip_zaamo_zalrsc = true;
>  #endif
> -#ifndef HAVE_AS_MARCH_ZABHA
> -  /* Skip since binutils 2.42 and earlier don't recognize zabha.  */
> -  skip_zabha = true;
> -#endif
>
>for (subset = m_head; subset != NULL; subset = subset->next)
>  {
> @@ -908,9 +905,6 @@ riscv_subset_list::to_string (bool version_p) const
>if (skip_zaamo_zalrsc && subset->name == "zalrsc")
> continue;
>
> -  if (skip_zabha && subset->name == "zabha")
> -   continue;
> -
>/* For !version_p, we only separate extension with underline for
>  multi-letter extension.  */
>if (!first &&
> diff --git a/gcc/config.in b/gcc/config.in
> index bc819005bd6..3af153eaec5 100644
> --- a/gcc/config.in
> +++ b/gcc/config.in
> @@ -635,12 +635,6 @@
>  #endif
>
>
> -/* Define if the assembler understands -march=rv*_zabha. */
> -#ifndef USED_FOR_TARGET
> -#undef HAVE_AS_MARCH_ZABHA
> -#endif
> -
> -
>  /* Define if the assembler understands -march=rv*_zifencei. */
>  #ifndef USED_FOR_TARGET
>  #undef HAVE_AS_MARCH_ZIFENCEI
> diff --git a/gcc/configure b/gcc/configure
> index 01acca7fb5c..7541bdeb724 100755
> --- a/gcc/configure
> +++ b/gcc/configure
> @@ -30882,37 +30882,6 @@ if test $gcc_cv_as_riscv_march_zaamo_zalrsc = yes; 
> then
>
>  $as_echo "#define HAVE_AS_MARCH_ZAAMO_ZALRSC 1" >>confdefs.h
>
> -fi
> -
> -{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for 
> -march=rv32i_zabha support" >&5
> -$as_echo_n "checking assembler for -march=rv32i_zabha support... " >&6; }
> -if ${gcc_cv_as_riscv_march_zabha+:} false; then :
> -  $as_echo_n "(cached) " >&6
> -else
> -  gcc_cv_as_riscv_march_zabha=no
> -  if test x$gcc_cv_as != x; then
> -$as_echo '' > conftest.s
> -if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_zabha -o 
> conftest.o conftest.s >&5'
> -  { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
> -  (eval $ac_try) 2>&5
> -  ac_status=$?
> -  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
> -  test $ac_status = 0; }; }
> -then
> -   gcc_cv_as_riscv_march_zabha=yes
> -else
> -  echo "configure: failed program was" >&5
> -  cat conftest.s >&5
> -fi
> -rm -f conftest.o conftest.s
> -  fi
> -fi
> -{ $as_echo "$as_me:${as_lineno-$LINENO}: result: 
> $gcc_cv_as_riscv_march_zabha" >&5
> -$as_echo "$gcc_cv_as_riscv_march_zabha" >&6; }
> -if test $gcc_cv_as_riscv_march_zabha = yes; then
> -
> -$as_echo "#define HAVE_AS_MARCH_ZABHA 1" >>confdefs.h
> -
>  fi
>
>  ;;
> diff --git a/gcc/configure.ac b/gcc/configure.ac
> index 3f20c107b6a..52c1780379d 100644
> --- a/gcc/configure.ac
> +++ b/gcc/configure.ac
> @@ -5461,11 +5461,6 @@ configured with --enable-newlib-nano-formatted-io.])
>[-march=rv32i_zaamo_zalrsc],,,
>[AC_DEFINE(HAVE_AS_MARCH_ZAAMO_ZALRSC, 1,
>  [Define if the assembler understands 
> -march=rv*_zaamo_zalrsc.])])
> -gcc_GAS_CHECK_FEATURE([-march=rv32i_zabha support],
> -  gcc_cv_as_riscv_march_zabha,
> -

Re: [PATCH v3] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

[Kito Cheng]

> > This API is intended to provide the capability to query minimal common 
> > available extensions on the system.
> >
> > Proposal in riscv-c-api-doc: 
> > https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74
>
> That's not merged, but I'm not sure what the rules are on stability for
> the C API doc.

The general rule is wait until achieving consensus between the GNU and
LLVM community,
you may know we (sifive folks) still have some discussion with Philip
Reames, so that's why

> > +static void __init_riscv_features_bits_linux ()
> > +{
> > +  struct riscv_hwprobe hwprobes[] = {
> > +{RISCV_HWPROBE_KEY_BASE_BEHAVIOR, 0},
> > +{RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
> > +{RISCV_HWPROBE_KEY_MVENDORID, 0},
> > +  };
> > +
> > +  long rv = syscall_5_args (__NR_riscv_hwprobe, (long)&hwprobes,
> > + sizeof (hwprobes) / sizeof (hwprobes[0]), 0,
> > + 0, 0);
>
> We were talking about this on the patchwork call, but went on to
> something else.  I was still kind of curious as to how this worked, and
> it's because this is just calling the syscall directly.  I think that's
> OK, as we're not resolving the hwprobe libc function.  It means we lose
> the caching from the VDSO, but we're caching again here so maybe that
> doesn't really matter -- we're just caching twice, but it's not like
> the performance is going to be worse than Arm/Intel (just a bit clunky).
>
> We did come back to it in the patchwork call, though, and were a bit
> worried about those symbol lookups.  So the conclusion was to put
> together a test to make sure we can actually look up these symbols from
> IFUNCs.

This function may also be used by __builtin_cpu_init, so IFUNC's parameter
is not available for that situation.

>
> > +
> > +  if (rv)
> > +return;
>
> Don't we need to also zero out the extension list when the syscalls
> fails?

We don't really need that since global variables should be zero-initialized
by default :)

and following zero out logic is only used for local variable copy only.

> > +void __init_riscv_feature_bits ()
> > +{
> > +  if (__init)
> > +return;
> > +
> > +#ifdef __linux
> > +  __init_riscv_features_bits_linux ();
>
> Just thinking a bit here: if we have an ABI where
> __init_riscv_feature_bits() takes an argument that's either 0 (ie, "do
> the syscall") or the pre-resolved VDSO function then we can avoid going
> into the kernel

Yeah, sounds like a reasonable way, and call that a platform specific argument.

Re: [PATCH] RISC-V: Add configure check for B extention support

[Kito Cheng]

LGTM, although I said no binutils check for zacas and zabha, but B is
a different situation since GCC will add that if zba, zbb and zbs are
all present.



On Thu, Jul 25, 2024 at 7:51 AM Edwin Lu  wrote:
>
> Binutils 2.42 and before don't recognize the B extension in the march
> strings even though it supports zba_zbb_zbs. Add a configure check to
> ignore the B in the march string if found.
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc (riscv_subset_list::to_string):
> Skip b in march string
> * config.in: Regenerate.
> * configure: Regenerate.
> * configure.ac: Add B assembler check
>
> Signed-off-by: Edwin Lu 
> ---
>  gcc/common/config/riscv/riscv-common.cc |  8 +++
>  gcc/config.in   |  6 +
>  gcc/configure   | 31 +
>  gcc/configure.ac|  5 
>  4 files changed, 50 insertions(+)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 682826c0e34..200a57e1bc8 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -857,6 +857,7 @@ riscv_subset_list::to_string (bool version_p) const
>bool skip_zaamo_zalrsc = false;
>bool skip_zabha = false;
>bool skip_zicsr = false;
> +  bool skip_b = false;
>bool i2p0 = false;
>
>/* For RISC-V ISA version 2.2 or earlier version, zicsr and zifencei is
> @@ -891,6 +892,10 @@ riscv_subset_list::to_string (bool version_p) const
>/* Skip since binutils 2.42 and earlier don't recognize zabha.  */
>skip_zabha = true;
>  #endif
> +#ifndef HAVE_AS_MARCH_B
> +  /* Skip since binutils 2.42 and earlier don't recognize b.  */
> +  skip_b = true;
> +#endif
>
>for (subset = m_head; subset != NULL; subset = subset->next)
>  {
> @@ -911,6 +916,9 @@ riscv_subset_list::to_string (bool version_p) const
>if (skip_zabha && subset->name == "zabha")
> continue;
>
> +  if (skip_b && subset->name == "b")
> +   continue;
> +
>/* For !version_p, we only separate extension with underline for
>  multi-letter extension.  */
>if (!first &&
> diff --git a/gcc/config.in b/gcc/config.in
> index bc819005bd6..96e829b9c93 100644
> --- a/gcc/config.in
> +++ b/gcc/config.in
> @@ -629,6 +629,12 @@
>  #endif
>
>
> +/* Define if the assembler understands -march=rv*_b. */
> +#ifndef USED_FOR_TARGET
> +#undef HAVE_AS_MARCH_B
> +#endif
> +
> +
>  /* Define if the assembler understands -march=rv*_zaamo_zalrsc. */
>  #ifndef USED_FOR_TARGET
>  #undef HAVE_AS_MARCH_ZAAMO_ZALRSC
> diff --git a/gcc/configure b/gcc/configure
> index 01acca7fb5c..c5725c4cd44 100755
> --- a/gcc/configure
> +++ b/gcc/configure
> @@ -30913,6 +30913,37 @@ if test $gcc_cv_as_riscv_march_zabha = yes; then
>
>  $as_echo "#define HAVE_AS_MARCH_ZABHA 1" >>confdefs.h
>
> +fi
> +
> +{ $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for 
> -march=rv32i_b support" >&5
> +$as_echo_n "checking assembler for -march=rv32i_b support... " >&6; }
> +if ${gcc_cv_as_riscv_march_b+:} false; then :
> +  $as_echo_n "(cached) " >&6
> +else
> +  gcc_cv_as_riscv_march_b=no
> +  if test x$gcc_cv_as != x; then
> +$as_echo '' > conftest.s
> +if { ac_try='$gcc_cv_as $gcc_cv_as_flags -march=rv32i_b -o conftest.o 
> conftest.s >&5'
> +  { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5
> +  (eval $ac_try) 2>&5
> +  ac_status=$?
> +  $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5
> +  test $ac_status = 0; }; }
> +then
> +   gcc_cv_as_riscv_march_b=yes
> +else
> +  echo "configure: failed program was" >&5
> +  cat conftest.s >&5
> +fi
> +rm -f conftest.o conftest.s
> +  fi
> +fi
> +{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_riscv_march_b" 
> >&5
> +$as_echo "$gcc_cv_as_riscv_march_b" >&6; }
> +if test $gcc_cv_as_riscv_march_b = yes; then
> +
> +$as_echo "#define HAVE_AS_MARCH_B 1" >>confdefs.h
> +
>  fi
>
>  ;;
> diff --git a/gcc/configure.ac b/gcc/configure.ac
> index 3f20c107b6a..93d9236ff36 100644
> --- a/gcc/configure.ac
> +++ b/gcc/configure.ac
> @@ -5466,6 +5466,11 @@ configured with --enable-newlib-nano-formatted-io.])
>[-march=rv32i_zabha],,,
>[AC_DEFINE(HAVE_AS_MARCH_ZABHA, 1,
>  [Define if the assembler understands -march=rv*_zabha.])])
> +gcc_GAS_CHECK_FEATURE([-march=rv32i_b support],
> +  gcc_cv_as_riscv_march_b,
> +  [-march=rv32i_b],,,
> +  [AC_DEFINE(HAVE_AS_MARCH_B, 1,
> +[Define if the assembler understands -march=rv*_b.])])
>  ;;
>  loongarch*-*-*)
>  gcc_GAS_CHECK_FEATURE([.dtprelword support],
> --
> 2.34.1
>

Re: [PATCH] RISC-V: xtheadmemidx: Disable pre/post-modify addressing if RVV is enabled

[Kito Cheng]

LGTM :)

On Wed, Jul 24, 2024 at 9:31 PM Christoph Müllner
 wrote:
>
> When enabling XTheadMemIdx, we enable the pre- and post-modify
> addressing modes in the RISC-V backend.
> Unfortunately, the auto_inc_dec pass will then attempt to utilize
> this feature regardless of the mode class (i.e. scalar or vector).
> The assumption seems to be, that an enabled addressing mode for
> scalar instructions will also be available for vector instructions.
>
> In case of XTheadMemIdx and RVV, this is ovbiously not the case.
> Still, auto_inc_dec (-O3) performs optimizations like the following:
>
> (insn 23 20 27 3 (set (mem:V4QI (reg:DI 136 [ ivtmp.13 ]) [0 MEM  char> [(char *)_39]+0 S4 A32])
> (reg:V4QI 168)) "gcc/testsuite/gcc.target/riscv/pr116033.c":12:27 
> 3183 {*movv4qi}
>  (nil))
> (insn 40 39 41 3 (set (reg:DI 136 [ ivtmp.13 ])
> (plus:DI (reg:DI 136 [ ivtmp.13 ])
> (const_int 20 [0x14]))) 5 {adddi3}
>  (nil))
> >
> (insn 23 20 27 3 (set (mem:V4QI (post_modify:DI (reg:DI 136 [ ivtmp.13 ])
> (plus:DI (reg:DI 136 [ ivtmp.13 ])
> (const_int 20 [0x14]))) [0 MEM  [(char 
> *)_39]+0 S4 A32])
> (reg:V4QI 168)) "gcc/testsuite/gcc.target/riscv/pr116033.c":12:27 
> 3183 {*movv4qi}
>  (expr_list:REG_INC (reg:DI 136 [ ivtmp.13 ])
> (nil)))
>
> The resulting memory-store with post-modify addressing cannot be
> lowered to an existing instruction (see PR116033).
> At a lower optimization level (-O2) this is currently fine,
> but we can't rely on that.
>
> One solution would be to introduce a target hook to check if a certain
> type can be used for pre-/post-modify optimizations.
> However, it will be hard to justify such a hook, if only a single
> RISC-V vendor extension requires that.
> Therefore, this patch takes a more drastic approach and disables
> pre-/post-modify addressing if TARGET_VECTOR is set.
> This results in not emitting pre-/post-modify instructions from
> XTheadMemIdx if RVV is enabled.
>
> Note, that this is not an issue with XTheadVector, because
> we currently don't have auto-vectorization for that extension.
> To ensure this won't changed without being noticed, an additional
> test is added.
>
> PR target/116033
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.h (HAVE_POST_MODIFY_DISP): Disable for RVV.
> (HAVE_PRE_MODIFY_DISP): Likewise.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/pr116033-1.c: New test.
> * gcc.target/riscv/pr116033-2.c: New test.
> * gcc.target/riscv/pr116033-3.c: New test.
>
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/config/riscv/riscv.h|  6 ++--
>  gcc/testsuite/gcc.target/riscv/pr116033-1.c | 40 +
>  gcc/testsuite/gcc.target/riscv/pr116033-2.c | 40 +
>  gcc/testsuite/gcc.target/riscv/pr116033-3.c | 38 
>  4 files changed, 122 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/pr116033-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/pr116033-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/pr116033-3.c
>
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index 6f040011864..e5760294506 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -1254,8 +1254,10 @@ extern void riscv_remove_unneeded_save_restore_calls 
> (void);
> e.g. RVVMF64BI vs RVVMF1BI on zvl512b, which is [1, 1] vs [64, 64].  */
>  #define MAX_POLY_VARIANT 64
>
> -#define HAVE_POST_MODIFY_DISP TARGET_XTHEADMEMIDX
> -#define HAVE_PRE_MODIFY_DISP  TARGET_XTHEADMEMIDX
> +#define HAVE_POST_MODIFY_DISP \
> +  (TARGET_XTHEADMEMIDX && (!TARGET_VECTOR || TARGET_XTHEADVECTOR))
> +#define HAVE_PRE_MODIFY_DISP \
> +  (TARGET_XTHEADMEMIDX && (!TARGET_VECTOR || TARGET_XTHEADVECTOR))
>
>  /* Check TLS Descriptors mechanism is selected.  */
>  #define TARGET_TLSDESC (riscv_tls_dialect == TLS_DESCRIPTORS)
> diff --git a/gcc/testsuite/gcc.target/riscv/pr116033-1.c 
> b/gcc/testsuite/gcc.target/riscv/pr116033-1.c
> new file mode 100644
> index 000..8dcbe6cc2b8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/pr116033-1.c
> @@ -0,0 +1,40 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-O2" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64gv_xtheadmemidx" { target { rv64 } } } */
> +/* { dg-options "-march=rv32gv_xtheadmemidx" { target { rv32 } } } */
> +
> +char arr_3[20][20];
> +void init()
> +{
> +  for (int i_0 = 0; i_0 < 20; ++i_0)
> +for (int i_1 = 0; i_0 < 20; ++i_0)
> +  for (int i_1 = 0; i_1 < 20; ++i_0)
> +for (int i_1 = 0; i_1 < 20; ++i_1)
> +  arr_3[i_0][i_1] = i_1;
> +}
> +
> +long
> +lr_reg_imm_upd_char_1 (long *rs1, long rs2)
> +{
> +  /* Register+register addressing still works.  */
> +  *rs1 = *rs1 + (rs2 << 1);
> +  return *(char*)(*rs1);
> +}
> +
> +void
> +char_pre_dec_load_1 (char *p)
> +{
> +  /* Missed optimization for V

Re: [PATCH] RISC-V: Disable Zba optimization pattern if XTheadMemIdx is enabled

[Kito Cheng]

Yeah, OK once your local test passes :)

On Wed, Jul 24, 2024 at 4:38 PM Christoph Müllner
 wrote:
>
> Is it OK to backport to GCC 14 (patch applies cleanly, test is running)?
>
> On Wed, Jul 24, 2024 at 9:25 AM Kito Cheng  wrote:
> >
> > LGTM :)
> >
> > On Wed, Jul 24, 2024 at 3:16 PM Christoph Müllner
> >  wrote:
> > >
> > > It is possible that the Zba optimization pattern zero_extendsidi2_bitmanip
> > > matches for a XTheadMemIdx INSN with the effect of emitting an invalid
> > > instruction as reported in PR116035.
> > >
> > > The pattern above is used to emit a zext.w instruction to zero-extend
> > > SI mode registers to DI mode.  A similar functionality can be achieved
> > > by XTheadBb's th.extu instruction.  And indeed, we have the equivalent
> > > pattern in thead.md (zero_extendsidi2_th_extu).  However, that pattern
> > > depends on !TARGET_XTHEADMEMIDX.  To compensate for that, there are
> > > specific patterns that ensure that zero-extension instruction can still
> > > be emitted (th_memidx_bb_zero_extendsidi2 and friends).
> > >
> > > While we could implement something similar 
> > > (th_memidx_zba_zero_extendsidi2)
> > > it would only make sense, if there existed real HW that does implement Zba
> > > and XTheadMemIdx, but not XTheadBb.  Unless such a machine exists, let's
> > > simply disable zero_extendsidi2_bitmanip if XTheadMemIdx is available.
> > >
> > > PR target/116035
> > >
> > > gcc/ChangeLog:
> > >
> > > * config/riscv/bitmanip.md: Disable zero_extendsidi2_bitmanip
> > > for XTheadMemIdx.
> > >
> > > gcc/testsuite/ChangeLog:
> > >
> > > * gcc.target/riscv/pr116035-1.c: New test.
> > > * gcc.target/riscv/pr116035-2.c: New test.
> > >
> > > Reported-by: Patrick O'Neill 
> > > Signed-off-by: Christoph Müllner 
> > > ---
> > >  gcc/config/riscv/bitmanip.md|  2 +-
> > >  gcc/testsuite/gcc.target/riscv/pr116035-1.c | 29 +
> > >  gcc/testsuite/gcc.target/riscv/pr116035-2.c | 26 ++
> > >  3 files changed, 56 insertions(+), 1 deletion(-)
> > >  create mode 100644 gcc/testsuite/gcc.target/riscv/pr116035-1.c
> > >  create mode 100644 gcc/testsuite/gcc.target/riscv/pr116035-2.c
> > >
> > > diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
> > > index f403ba8dbba..6b720992ca3 100644
> > > --- a/gcc/config/riscv/bitmanip.md
> > > +++ b/gcc/config/riscv/bitmanip.md
> > > @@ -22,7 +22,7 @@
> > >  (define_insn "*zero_extendsidi2_bitmanip"
> > >[(set (match_operand:DI 0 "register_operand" "=r,r")
> > > (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" 
> > > "r,m")))]
> > > -  "TARGET_64BIT && TARGET_ZBA"
> > > +  "TARGET_64BIT && TARGET_ZBA && !TARGET_XTHEADMEMIDX"
> > >"@
> > > zext.w\t%0,%1
> > > lwu\t%0,%1"
> > > diff --git a/gcc/testsuite/gcc.target/riscv/pr116035-1.c 
> > > b/gcc/testsuite/gcc.target/riscv/pr116035-1.c
> > > new file mode 100644
> > > index 000..bc45941ff8f
> > > --- /dev/null
> > > +++ b/gcc/testsuite/gcc.target/riscv/pr116035-1.c
> > > @@ -0,0 +1,29 @@
> > > +/* { dg-do compile } */
> > > +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" } } */
> > > +/* { dg-options "-march=rv64g_zba_xtheadmemidx" { target { rv64 } } } */
> > > +/* { dg-options "-march=rv32g_zba_xtheadmemidx" { target { rv32 } } } */
> > > +
> > > +void a(long);
> > > +unsigned b[11];
> > > +void c()
> > > +{
> > > +  for (int d = 0; d < 11; ++d)
> > > +a(b[d]);
> > > +}
> > > +
> > > +#if __riscv_xlen == 64
> > > +unsigned long zext64_32(unsigned int u32)
> > > +{
> > > +  /* Missed optimization for Zba+XTheadMemIdx.  */
> > > +  return u32; //zext.w a0, a0
> > > +}
> > > +#endif
> > > +
> > > +/* { dg-final { scan-assembler 
> > > "th.lwuia\t\[a-x0-9\]+,\\(\[a-x0-9\]+\\),4,0" { target rv64 } } } */
> > > +/* { dg-final { scan-assembler 
> > > "th.lwia\t\[a-x0-9\]+,\\(\[a-x0-9\]+\\),4,0" { target rv32 } } } */

Re: [PATCH] RISC-V: Error early with V and no M extension. [PR116036]

[Kito Cheng]

LGTM, although I was a little late to join the meeting yesterday, but
I vaguely know you guys are discussing this, that combination really
does not make too much sense and also the LLVM side already does the
same thing :)

On Wed, Jul 24, 2024 at 8:50 PM Robin Dapp  wrote:
>
> Hi,
>
> for calculating the value of a poly_int at runtime we use a multiplication
> instruction that requires the M extension.  Instead of just asserting and
> ICEing this patch emits an early error at option-parsing time.
>
> We have several tests that use only "i" (without "m") and I adjusted all of
> them to "im".  For now, I didn't verify if the original error just with "i"
> still occurs but just added "m".
>
> Tested on rv64gcv_zvfh_zvbb.
>
> Regards
>  Robin
>
> gcc/ChangeLog:
>
> PR target/116036
>
> * config/riscv/riscv.cc (riscv_override_options_internal): Error
> with TARGET_VECTOR && !TARGET_MUL.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr116036.c: New test.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-31.c: Add m to arch string and expect it.
> * gcc.target/riscv/arch-32.c: Ditto.
> * gcc.target/riscv/arch-37.c: Ditto.
> * gcc.target/riscv/arch-38.c: Ditto.
> * gcc.target/riscv/predef-14.c: Ditto.
> * gcc.target/riscv/predef-15.c: Ditto.
> * gcc.target/riscv/predef-16.c: Ditto.
> * gcc.target/riscv/predef-26.c: Ditto.
> * gcc.target/riscv/predef-27.c: Ditto.
> * gcc.target/riscv/predef-32.c: Ditto.
> * gcc.target/riscv/predef-33.c: Ditto.
> * gcc.target/riscv/predef-36.c: Ditto.
> * gcc.target/riscv/predef-37.c: Ditto.
> * gcc.target/riscv/rvv/autovec/pr111486.c: Add m to arch string.
> * gcc.target/riscv/compare-debug-1.c: Ditto.
> * gcc.target/riscv/compare-debug-2.c: Ditto.
> * gcc.target/riscv/rvv/base/pr116036.c: New test.
> ---
>  gcc/config/riscv/riscv.cc |  5 +
>  gcc/internal-fn.cc|  3 ++-
>  gcc/testsuite/gcc.target/riscv/arch-31.c  |  2 +-
>  gcc/testsuite/gcc.target/riscv/arch-32.c  |  2 +-
>  gcc/testsuite/gcc.target/riscv/arch-37.c  |  2 +-
>  gcc/testsuite/gcc.target/riscv/arch-38.c  |  2 +-
>  gcc/testsuite/gcc.target/riscv/compare-debug-1.c  |  2 +-
>  gcc/testsuite/gcc.target/riscv/compare-debug-2.c  |  2 +-
>  gcc/testsuite/gcc.target/riscv/predef-14.c|  6 +++---
>  gcc/testsuite/gcc.target/riscv/predef-15.c|  4 ++--
>  gcc/testsuite/gcc.target/riscv/predef-16.c|  4 ++--
>  gcc/testsuite/gcc.target/riscv/predef-26.c|  6 +-
>  gcc/testsuite/gcc.target/riscv/predef-27.c|  6 +-
>  gcc/testsuite/gcc.target/riscv/predef-32.c|  6 +-
>  gcc/testsuite/gcc.target/riscv/predef-33.c|  6 +-
>  gcc/testsuite/gcc.target/riscv/predef-36.c|  6 +-
>  gcc/testsuite/gcc.target/riscv/predef-37.c|  6 +-
>  gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111486.c |  2 +-
>  gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c| 11 +++
>  19 files changed, 62 insertions(+), 21 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr116036.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index ca9ea1b70f3..487698a8e4f 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -9690,6 +9690,11 @@ riscv_override_options_internal (struct gcc_options 
> *opts)
>else if (!TARGET_MUL_OPTS_P (opts) && TARGET_DIV_OPTS_P (opts))
>  error ("%<-mdiv%> requires %<-march%> to subsume the % extension");
>
> +  /* We might use a multiplication to calculate the scalable vector length at
> + runtime.  Therefore, require the M extension.  */
> +  if (TARGET_VECTOR && !TARGET_MUL)
> +sorry ("the % extension requires the % extension");
> +
>/* Likewise floating-point division and square root.  */
>if ((TARGET_HARD_FLOAT_OPTS_P (opts) || TARGET_ZFINX_OPTS_P (opts))
>&& ((target_flags_explicit & MASK_FDIV) == 0))
> diff --git a/gcc/internal-fn.cc b/gcc/internal-fn.cc
> index 826d552a6fd..eb6c033535c 100644
> --- a/gcc/internal-fn.cc
> +++ b/gcc/internal-fn.cc
> @@ -5049,7 +5049,8 @@ internal_len_load_store_bias (internal_fn ifn, 
> machine_mode mode)
>  }
>
>  /* Return true if the given ELS_VALUE is supported for a
> -   MASK_LOAD or MASK_LEN_LOAD with mode MODE.  */
> +   MASK_LOAD or MASK_LEN_LOAD with mode MODE.  The target's
> +   preferred else value is return in ELSVAL.  */
>
>  bool
>  internal_mask_load_else_supported_p (internal_fn ifn,
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-31.c 
> b/gcc/testsuite/gcc.target/riscv/arch-31.c
> index 5180753b905..9b867c5ecd2 100644
> --- a/gcc/testsuite/gcc.target/riscv/arch-31.c
> +++ b/gcc/testsuite/gcc.target/riscv/arch-31.c
> @@ -1,5 +1,

Re: [PATCH] RISC-V: Disable Zba optimization pattern if XTheadMemIdx is enabled

[Kito Cheng]

LGTM :)

On Wed, Jul 24, 2024 at 3:16 PM Christoph Müllner
 wrote:
>
> It is possible that the Zba optimization pattern zero_extendsidi2_bitmanip
> matches for a XTheadMemIdx INSN with the effect of emitting an invalid
> instruction as reported in PR116035.
>
> The pattern above is used to emit a zext.w instruction to zero-extend
> SI mode registers to DI mode.  A similar functionality can be achieved
> by XTheadBb's th.extu instruction.  And indeed, we have the equivalent
> pattern in thead.md (zero_extendsidi2_th_extu).  However, that pattern
> depends on !TARGET_XTHEADMEMIDX.  To compensate for that, there are
> specific patterns that ensure that zero-extension instruction can still
> be emitted (th_memidx_bb_zero_extendsidi2 and friends).
>
> While we could implement something similar (th_memidx_zba_zero_extendsidi2)
> it would only make sense, if there existed real HW that does implement Zba
> and XTheadMemIdx, but not XTheadBb.  Unless such a machine exists, let's
> simply disable zero_extendsidi2_bitmanip if XTheadMemIdx is available.
>
> PR target/116035
>
> gcc/ChangeLog:
>
> * config/riscv/bitmanip.md: Disable zero_extendsidi2_bitmanip
> for XTheadMemIdx.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/pr116035-1.c: New test.
> * gcc.target/riscv/pr116035-2.c: New test.
>
> Reported-by: Patrick O'Neill 
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/config/riscv/bitmanip.md|  2 +-
>  gcc/testsuite/gcc.target/riscv/pr116035-1.c | 29 +
>  gcc/testsuite/gcc.target/riscv/pr116035-2.c | 26 ++
>  3 files changed, 56 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/pr116035-1.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/pr116035-2.c
>
> diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
> index f403ba8dbba..6b720992ca3 100644
> --- a/gcc/config/riscv/bitmanip.md
> +++ b/gcc/config/riscv/bitmanip.md
> @@ -22,7 +22,7 @@
>  (define_insn "*zero_extendsidi2_bitmanip"
>[(set (match_operand:DI 0 "register_operand" "=r,r")
> (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))]
> -  "TARGET_64BIT && TARGET_ZBA"
> +  "TARGET_64BIT && TARGET_ZBA && !TARGET_XTHEADMEMIDX"
>"@
> zext.w\t%0,%1
> lwu\t%0,%1"
> diff --git a/gcc/testsuite/gcc.target/riscv/pr116035-1.c 
> b/gcc/testsuite/gcc.target/riscv/pr116035-1.c
> new file mode 100644
> index 000..bc45941ff8f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/pr116035-1.c
> @@ -0,0 +1,29 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64g_zba_xtheadmemidx" { target { rv64 } } } */
> +/* { dg-options "-march=rv32g_zba_xtheadmemidx" { target { rv32 } } } */
> +
> +void a(long);
> +unsigned b[11];
> +void c()
> +{
> +  for (int d = 0; d < 11; ++d)
> +a(b[d]);
> +}
> +
> +#if __riscv_xlen == 64
> +unsigned long zext64_32(unsigned int u32)
> +{
> +  /* Missed optimization for Zba+XTheadMemIdx.  */
> +  return u32; //zext.w a0, a0
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler "th.lwuia\t\[a-x0-9\]+,\\(\[a-x0-9\]+\\),4,0" 
> { target rv64 } } } */
> +/* { dg-final { scan-assembler "th.lwia\t\[a-x0-9\]+,\\(\[a-x0-9\]+\\),4,0" 
> { target rv32 } } } */
> +
> +/* { dg-final { scan-assembler-not "lwu\t\[a-x0-9\]+,\(\[a-x0-9\]+\),4,0" } 
> } */
> +
> +/* Missed optimizations for Zba+XTheadMemIdx.  */
> +/* { dg-final { scan-assembler "zext.w\t" { target rv64 xfail rv64 } } } */
> +
> diff --git a/gcc/testsuite/gcc.target/riscv/pr116035-2.c 
> b/gcc/testsuite/gcc.target/riscv/pr116035-2.c
> new file mode 100644
> index 000..2c1a9694860
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/pr116035-2.c
> @@ -0,0 +1,26 @@
> +/* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" "-Os" "-Oz" } } */
> +/* { dg-options "-march=rv64g_xtheadbb_xtheadmemidx" { target { rv64 } } } */
> +/* { dg-options "-march=rv32g_xtheadbb_xtheadmemidx" { target { rv32 } } } */
> +
> +void a(long);
> +unsigned b[11];
> +void c()
> +{
> +  for (int d = 0; d < 11; ++d)
> +a(b[d]);
> +}
> +
> +#if __riscv_xlen == 64
> +unsigned long zext64_32(unsigned int u32)
> +{
> +return u32; //th.extu a0, a0, 31, 0
> +}
> +#endif
> +
> +/* { dg-final { scan-assembler "th.lwuia\t\[a-x0-9\]+,\\(\[a-x0-9\]+\\),4,0" 
> { target { rv64 } } } } */
> +/* { dg-final { scan-assembler "th.lwia\t\[a-x0-9\]+,\\(\[a-x0-9\]+\\),4,0" 
> { target { rv32 } } } } */
> +
> +/* { dg-final { scan-assembler-not "lwu\t\[a-x0-9\]+,\\(\[a-x0-9\]+\\),4,0" 
> } } */
> +
> +/* { dg-final { scan-assembler "th.extu\t" { target rv64 } } } */
> --
> 2.45.2
>

Re: [PATCH v2] RISC-V: Add basic support for the Zacas extension

[Kito Cheng]

I incline do not add skip_zacas stuffs (although skip_zabha is already
there but that's fine), because that's different situation compare to
the zaamo/zalrsc, zaamo/zalrsc should automatically append if a
extension is available, which is new behavior and new extensions.

But zacas is only added when users explicitly add that in -march
string unlike zaamo/zalrsc, so I am not sure if we need to check the
binutils support and drop that if unsupported,

My biggest concern is : should we do so for every new extension?

I think we didn't do that so far, so we should

[PATCH v4] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

[Kito Cheng]

This provides a common abstraction layer to probe the available extensions at
run-time. These functions can be used to implement function multi-versioning or
to detect available extensions.

The advantages of providing this abstraction layer are:
- Easy to port to other new platforms.
- Easier to maintain in GCC for function multi-versioning.
  - For example, maintaining platform-dependent code in C code/libgcc is much
easier than maintaining it in GCC by creating GIMPLEs...

This API is intended to provide the capability to query minimal common 
available extensions on the system.

Proposal in riscv-c-api-doc: 
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74

Full function multi-versioning implementation will come later. We are posting
this first because we intend to backport it to the GCC 14 branch to unblock
LLVM 19 to use this with GCC 14.2, rather than waiting for GCC 15.

Changes since v3:
- Fix non-linux build.
- Let __init_riscv_feature_bits become constructor

Changes since v2:
- Prevent it initialize more than once.

Changes since v1:
- Fix the format.
- Prevented race conditions by introducing a local variable to avoid load/store
  operations during the computation of the feature bit.

libgcc/ChangeLog:

* config/riscv/feature_bits.c: New.
* config/riscv/t-elf (LIB2ADD): Add feature_bits.c.
---
 libgcc/config/riscv/feature_bits.c | 315 +
 libgcc/config/riscv/t-elf  |   1 +
 2 files changed, 316 insertions(+)
 create mode 100644 libgcc/config/riscv/feature_bits.c

diff --git a/libgcc/config/riscv/feature_bits.c 
b/libgcc/config/riscv/feature_bits.c
new file mode 100644
index 000..208283e4d74
--- /dev/null
+++ b/libgcc/config/riscv/feature_bits.c
@@ -0,0 +1,315 @@
+/* Helper function for function multi-versioning for RISC-V.
+
+   Copyright (C) 2024 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+.  */
+
+#define RISCV_FEATURE_BITS_LENGTH 1
+struct {
+  unsigned length;
+  unsigned long long features[RISCV_FEATURE_BITS_LENGTH];
+} __riscv_feature_bits __attribute__((visibility("hidden"), nocommon));
+
+#define RISCV_VENDOR_FEATURE_BITS_LENGTH 1
+
+struct {
+  unsigned vendorID;
+  unsigned length;
+  unsigned long long features[RISCV_VENDOR_FEATURE_BITS_LENGTH];
+} __riscv_vendor_feature_bits __attribute__((visibility("hidden"), nocommon));
+
+#define A_GROUPID 0
+#define A_BITMASK (1ULL << 0)
+#define C_GROUPID 0
+#define C_BITMASK (1ULL << 2)
+#define D_GROUPID 0
+#define D_BITMASK (1ULL << 3)
+#define F_GROUPID 0
+#define F_BITMASK (1ULL << 5)
+#define I_GROUPID 0
+#define I_BITMASK (1ULL << 8)
+#define M_GROUPID 0
+#define M_BITMASK (1ULL << 12)
+#define V_GROUPID 0
+#define V_BITMASK (1ULL << 21)
+#define ZACAS_GROUPID 0
+#define ZACAS_BITMASK (1ULL << 26)
+#define ZBA_GROUPID 0
+#define ZBA_BITMASK (1ULL << 27)
+#define ZBB_GROUPID 0
+#define ZBB_BITMASK (1ULL << 28)
+#define ZBC_GROUPID 0
+#define ZBC_BITMASK (1ULL << 29)
+#define ZBKB_GROUPID 0
+#define ZBKB_BITMASK (1ULL << 30)
+#define ZBKC_GROUPID 0
+#define ZBKC_BITMASK (1ULL << 31)
+#define ZBKX_GROUPID 0
+#define ZBKX_BITMASK (1ULL << 32)
+#define ZBS_GROUPID 0
+#define ZBS_BITMASK (1ULL << 33)
+#define ZFA_GROUPID 0
+#define ZFA_BITMASK (1ULL << 34)
+#define ZFH_GROUPID 0
+#define ZFH_BITMASK (1ULL << 35)
+#define ZFHMIN_GROUPID 0
+#define ZFHMIN_BITMASK (1ULL << 36)
+#define ZICBOZ_GROUPID 0
+#define ZICBOZ_BITMASK (1ULL << 37)
+#define ZICOND_GROUPID 0
+#define ZICOND_BITMASK (1ULL << 38)
+#define ZIHINTNTL_GROUPID 0
+#define ZIHINTNTL_BITMASK (1ULL << 39)
+#define ZIHINTPAUSE_GROUPID 0
+#define ZIHINTPAUSE_BITMASK (1ULL << 40)
+#define ZKND_GROUPID 0
+#define ZKND_BITMASK (1ULL << 41)
+#define ZKNE_GROUPID 0
+#define ZKNE_BITMASK (1ULL << 42)
+#define ZKNH_GROUPID 0
+#define ZKNH_BITMASK (1ULL << 43)
+#define ZKSED_GROUPID 0
+#define ZKSED_BITMASK (1ULL << 44)
+#define ZKSH_GROUPID 0
+#define ZKSH_BITMASK (1ULL << 45)
+#define ZKT_GROUPID 0
+#define ZKT_BITMASK (1ULL << 46)
+#define ZTSO_GROUPID 0
+#define ZTSO_BITMASK (1ULL << 47)
+#define ZVBB_GROUPID 0
+#define ZVBB_BITMASK (1U

Re: [PATCH v3] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

[Kito Cheng]

thanks for catching that, seem like we only check for the linux path :)

Edwin Lu  於 2024年7月23日 週二 02:45 寫道：

> Hi Kito,
>
>
> On 7/22/2024 8:19 AM, Kito Cheng wrote:
> > Corresponding implementation in compiler-rt already merged in LLVM
> > side, so I plan to merge this into trunk tomorrow if no strong
> > objections.
> >
> > NOTE: This has been tested with clang/llvm within our internal CI.
>
> > On Mon, Jul 22, 2024 at 10:16 PM Kito Cheng 
> wrote:
> >>
> >> This provides a common abstraction layer to probe the available
> extensions at
> >> run-time. These functions can be used to implement function
> multi-versioning or
> >> to detect available extensions.
> >>
> >> The advantages of providing this abstraction layer are:
> >> - Easy to port to other new platforms.
> >> - Easier to maintain in GCC for function multi-versioning.
> >>- For example, maintaining platform-dependent code in C code/libgcc
> is much
> >>  easier than maintaining it in GCC by creating GIMPLEs...
> >>
> >> This API is intended to provide the capability to query minimal common
> available extensions on the system.
> >>
> >> Proposal in riscv-c-api-doc:
> https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74
> >>
> >> Full function multi-versioning implementation will come later. We are
> posting
> >> this first because we intend to backport it to the GCC 14 branch to
> unblock
> >> LLVM 19 to use this with GCC 14.2, rather than waiting for GCC 15.
> >>
> >> Changes since v2:
> >> - Prevent it initialize more than once.
> >>
> >> Changes since v1:
> >> - Fix the format.
> >> - Prevented race conditions by introducing a local variable to avoid
> load/store
> >>operations during the computation of the feature bit.
> >>
> >> libgcc/ChangeLog:
> >>
> >>  * config/riscv/feature_bits.c: New.
> >>  * config/riscv/t-elf (LIB2ADD): Add feature_bits.c.
> >> ---
> >>   libgcc/config/riscv/feature_bits.c | 313 +
> >>   libgcc/config/riscv/t-elf  |   1 +
> >>   2 files changed, 314 insertions(+)
> >>   create mode 100644 libgcc/config/riscv/feature_bits.c
> >>
> >> diff --git a/libgcc/config/riscv/feature_bits.c
> b/libgcc/config/riscv/feature_bits.c
> >> new file mode 100644
> >> index 000..cce4fbfa6be
> >> --- /dev/null
> >> +++ b/libgcc/config/riscv/feature_bits.c
> >> @@ -0,0 +1,313 @@
> >> +
> >> +void __init_riscv_feature_bits ()
> >> +{
> >> +  if (__init)
> >> +return;
> >> +
> >> +#ifdef __linux
> >> +  __init_riscv_features_bits_linux ();
> >> +#else
> >> +  /* Unsupported, just initlizaed that into all zeros.  */
> >> +  __riscv_feature_bits.length = 0
>
> I don't know enough about this to be able to comment on the patch
> itself. There's just a missing semicolon here which slipped its way into
> the v3 patch which would cause errors when trying to build on non-linux
> targets.
>
> ../../../../../../gcc/libgcc/config/riscv/feature_bits.c:307:34: error:
> expected ';' before '__riscv_vendor_feature_bits'
>307 |   __riscv_feature_bits.length = 0
>|  ^
>|  ;
>308 |   __riscv_vendor_feature_bits.length = 0;
>|   ~~~
> make[5]: *** [../../../../../../gcc/libgcc/static-object.mk:17:
> feature_bits.o] Error 1
>
>
> >> +  __riscv_vendor_feature_bits.length = 0;
> >> +  __riscv_vendor_feature_bits.vendorID = 0;
> >> +#endif
> >> +
> >> +  __init = 1;
> >> +}
>
> Edwin
>
>
>
>

Re: [PATCH v3] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

[Kito Cheng]

Corresponding implementation in compiler-rt already merged in LLVM
side, so I plan to merge this into trunk tomorrow if no strong
objections.

NOTE: This has been tested with clang/llvm within our internal CI.

On Mon, Jul 22, 2024 at 10:16 PM Kito Cheng  wrote:
>
> This provides a common abstraction layer to probe the available extensions at
> run-time. These functions can be used to implement function multi-versioning 
> or
> to detect available extensions.
>
> The advantages of providing this abstraction layer are:
> - Easy to port to other new platforms.
> - Easier to maintain in GCC for function multi-versioning.
>   - For example, maintaining platform-dependent code in C code/libgcc is much
> easier than maintaining it in GCC by creating GIMPLEs...
>
> This API is intended to provide the capability to query minimal common 
> available extensions on the system.
>
> Proposal in riscv-c-api-doc: 
> https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74
>
> Full function multi-versioning implementation will come later. We are posting
> this first because we intend to backport it to the GCC 14 branch to unblock
> LLVM 19 to use this with GCC 14.2, rather than waiting for GCC 15.
>
> Changes since v2:
> - Prevent it initialize more than once.
>
> Changes since v1:
> - Fix the format.
> - Prevented race conditions by introducing a local variable to avoid 
> load/store
>   operations during the computation of the feature bit.
>
> libgcc/ChangeLog:
>
> * config/riscv/feature_bits.c: New.
> * config/riscv/t-elf (LIB2ADD): Add feature_bits.c.
> ---
>  libgcc/config/riscv/feature_bits.c | 313 +
>  libgcc/config/riscv/t-elf  |   1 +
>  2 files changed, 314 insertions(+)
>  create mode 100644 libgcc/config/riscv/feature_bits.c
>
> diff --git a/libgcc/config/riscv/feature_bits.c 
> b/libgcc/config/riscv/feature_bits.c
> new file mode 100644
> index 000..cce4fbfa6be
> --- /dev/null
> +++ b/libgcc/config/riscv/feature_bits.c
> @@ -0,0 +1,313 @@
> +/* Helper function for function multi-versioning for RISC-V.
> +
> +   Copyright (C) 2024 Free Software Foundation, Inc.
> +
> +This file is part of GCC.
> +
> +GCC is free software; you can redistribute it and/or modify it under
> +the terms of the GNU General Public License as published by the Free
> +Software Foundation; either version 3, or (at your option) any later
> +version.
> +
> +GCC is distributed in the hope that it will be useful, but WITHOUT ANY
> +WARRANTY; without even the implied warranty of MERCHANTABILITY or
> +FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
> +for more details.
> +
> +Under Section 7 of GPL version 3, you are granted additional
> +permissions described in the GCC Runtime Library Exception, version
> +3.1, as published by the Free Software Foundation.
> +
> +You should have received a copy of the GNU General Public License and
> +a copy of the GCC Runtime Library Exception along with this program;
> +see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
> +<http://www.gnu.org/licenses/>.  */
> +
> +#define RISCV_FEATURE_BITS_LENGTH 1
> +struct {
> +  unsigned length;
> +  unsigned long long features[RISCV_FEATURE_BITS_LENGTH];
> +} __riscv_feature_bits __attribute__((visibility("hidden"), nocommon));
> +
> +#define RISCV_VENDOR_FEATURE_BITS_LENGTH 1
> +
> +struct {
> +  unsigned vendorID;
> +  unsigned length;
> +  unsigned long long features[RISCV_VENDOR_FEATURE_BITS_LENGTH];
> +} __riscv_vendor_feature_bits __attribute__((visibility("hidden"), 
> nocommon));
> +
> +#define A_GROUPID 0
> +#define A_BITMASK (1ULL << 0)
> +#define C_GROUPID 0
> +#define C_BITMASK (1ULL << 2)
> +#define D_GROUPID 0
> +#define D_BITMASK (1ULL << 3)
> +#define F_GROUPID 0
> +#define F_BITMASK (1ULL << 5)
> +#define I_GROUPID 0
> +#define I_BITMASK (1ULL << 8)
> +#define M_GROUPID 0
> +#define M_BITMASK (1ULL << 12)
> +#define V_GROUPID 0
> +#define V_BITMASK (1ULL << 21)
> +#define ZACAS_GROUPID 0
> +#define ZACAS_BITMASK (1ULL << 26)
> +#define ZBA_GROUPID 0
> +#define ZBA_BITMASK (1ULL << 27)
> +#define ZBB_GROUPID 0
> +#define ZBB_BITMASK (1ULL << 28)
> +#define ZBC_GROUPID 0
> +#define ZBC_BITMASK (1ULL << 29)
> +#define ZBKB_GROUPID 0
> +#define ZBKB_BITMASK (1ULL << 30)
> +#define ZBKC_GROUPID 0
> +#define ZBKC_BITMASK (1ULL << 31)
> +#define ZBKX_GROUPID 0
> +#define ZBKX_BITMASK (1ULL << 32)
> +#define ZBS_GROUPID 0
> +#define ZBS_BITMASK (1ULL << 33)
> +#define ZFA_GROUPID 0

[PATCH v3] RISC-V: Implement __init_riscv_feature_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

[Kito Cheng]

This provides a common abstraction layer to probe the available extensions at
run-time. These functions can be used to implement function multi-versioning or
to detect available extensions.

The advantages of providing this abstraction layer are:
- Easy to port to other new platforms.
- Easier to maintain in GCC for function multi-versioning.
  - For example, maintaining platform-dependent code in C code/libgcc is much
easier than maintaining it in GCC by creating GIMPLEs...

This API is intended to provide the capability to query minimal common 
available extensions on the system.

Proposal in riscv-c-api-doc: 
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74

Full function multi-versioning implementation will come later. We are posting
this first because we intend to backport it to the GCC 14 branch to unblock
LLVM 19 to use this with GCC 14.2, rather than waiting for GCC 15.

Changes since v2:
- Prevent it initialize more than once.

Changes since v1:
- Fix the format.
- Prevented race conditions by introducing a local variable to avoid load/store
  operations during the computation of the feature bit.

libgcc/ChangeLog:

* config/riscv/feature_bits.c: New.
* config/riscv/t-elf (LIB2ADD): Add feature_bits.c.
---
 libgcc/config/riscv/feature_bits.c | 313 +
 libgcc/config/riscv/t-elf  |   1 +
 2 files changed, 314 insertions(+)
 create mode 100644 libgcc/config/riscv/feature_bits.c

diff --git a/libgcc/config/riscv/feature_bits.c 
b/libgcc/config/riscv/feature_bits.c
new file mode 100644
index 000..cce4fbfa6be
--- /dev/null
+++ b/libgcc/config/riscv/feature_bits.c
@@ -0,0 +1,313 @@
+/* Helper function for function multi-versioning for RISC-V.
+
+   Copyright (C) 2024 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+.  */
+
+#define RISCV_FEATURE_BITS_LENGTH 1
+struct {
+  unsigned length;
+  unsigned long long features[RISCV_FEATURE_BITS_LENGTH];
+} __riscv_feature_bits __attribute__((visibility("hidden"), nocommon));
+
+#define RISCV_VENDOR_FEATURE_BITS_LENGTH 1
+
+struct {
+  unsigned vendorID;
+  unsigned length;
+  unsigned long long features[RISCV_VENDOR_FEATURE_BITS_LENGTH];
+} __riscv_vendor_feature_bits __attribute__((visibility("hidden"), nocommon));
+
+#define A_GROUPID 0
+#define A_BITMASK (1ULL << 0)
+#define C_GROUPID 0
+#define C_BITMASK (1ULL << 2)
+#define D_GROUPID 0
+#define D_BITMASK (1ULL << 3)
+#define F_GROUPID 0
+#define F_BITMASK (1ULL << 5)
+#define I_GROUPID 0
+#define I_BITMASK (1ULL << 8)
+#define M_GROUPID 0
+#define M_BITMASK (1ULL << 12)
+#define V_GROUPID 0
+#define V_BITMASK (1ULL << 21)
+#define ZACAS_GROUPID 0
+#define ZACAS_BITMASK (1ULL << 26)
+#define ZBA_GROUPID 0
+#define ZBA_BITMASK (1ULL << 27)
+#define ZBB_GROUPID 0
+#define ZBB_BITMASK (1ULL << 28)
+#define ZBC_GROUPID 0
+#define ZBC_BITMASK (1ULL << 29)
+#define ZBKB_GROUPID 0
+#define ZBKB_BITMASK (1ULL << 30)
+#define ZBKC_GROUPID 0
+#define ZBKC_BITMASK (1ULL << 31)
+#define ZBKX_GROUPID 0
+#define ZBKX_BITMASK (1ULL << 32)
+#define ZBS_GROUPID 0
+#define ZBS_BITMASK (1ULL << 33)
+#define ZFA_GROUPID 0
+#define ZFA_BITMASK (1ULL << 34)
+#define ZFH_GROUPID 0
+#define ZFH_BITMASK (1ULL << 35)
+#define ZFHMIN_GROUPID 0
+#define ZFHMIN_BITMASK (1ULL << 36)
+#define ZICBOZ_GROUPID 0
+#define ZICBOZ_BITMASK (1ULL << 37)
+#define ZICOND_GROUPID 0
+#define ZICOND_BITMASK (1ULL << 38)
+#define ZIHINTNTL_GROUPID 0
+#define ZIHINTNTL_BITMASK (1ULL << 39)
+#define ZIHINTPAUSE_GROUPID 0
+#define ZIHINTPAUSE_BITMASK (1ULL << 40)
+#define ZKND_GROUPID 0
+#define ZKND_BITMASK (1ULL << 41)
+#define ZKNE_GROUPID 0
+#define ZKNE_BITMASK (1ULL << 42)
+#define ZKNH_GROUPID 0
+#define ZKNH_BITMASK (1ULL << 43)
+#define ZKSED_GROUPID 0
+#define ZKSED_BITMASK (1ULL << 44)
+#define ZKSH_GROUPID 0
+#define ZKSH_BITMASK (1ULL << 45)
+#define ZKT_GROUPID 0
+#define ZKT_BITMASK (1ULL << 46)
+#define ZTSO_GROUPID 0
+#define ZTSO_BITMASK (1ULL << 47)
+#define ZVBB_GROUPID 0
+#define ZVBB_BITMASK (1ULL << 48)
+#define ZVBC_GROUPID 0
+#define ZVBC_BITMASK (1ULL << 49)
+#define ZVFH_GROUPID 0

[PATCH v2] RISC-V: Implement __init_riscv_features_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

[Kito Cheng]

This provides a common abstraction layer to probe the available extensions at
run-time. These functions can be used to implement function multi-versioning or
to detect available extensions.

The advantages of providing this abstraction layer are:
- Easy to port to other new platforms.
- Easier to maintain in GCC for function multi-versioning.
  - For example, maintaining platform-dependent code in C code/libgcc is much
easier than maintaining it in GCC by creating GIMPLEs...

This API is intended to provide the capability to query minimal common 
available extensions on the system.

Proposal in riscv-c-api-doc: 
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74

Full function multi-versioning implementation will come later. We are posting
this first because we intend to backport it to the GCC 14 branch to unblock
LLVM 19 to use this with GCC 14.2, rather than waiting for GCC 15.

Changes since v1:
- Fix the format.
- Prevented race conditions by introducing a local variable to avoid load/store
  operations during the computation of the feature bit.

libgcc/ChangeLog:

* config/riscv/feature_bits.c: New.
* config/riscv/t-elf (LIB2ADD): Add feature_bits.c.
---
 libgcc/config/riscv/feature_bits.c | 306 +
 libgcc/config/riscv/t-elf  |   1 +
 2 files changed, 307 insertions(+)
 create mode 100644 libgcc/config/riscv/feature_bits.c

diff --git a/libgcc/config/riscv/feature_bits.c 
b/libgcc/config/riscv/feature_bits.c
new file mode 100644
index 000..5649606039f
--- /dev/null
+++ b/libgcc/config/riscv/feature_bits.c
@@ -0,0 +1,306 @@
+/* Helper function for function multi-versioning for RISC-V.
+
+   Copyright (C) 2024 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+.  */
+
+#define RISCV_FEATURE_BITS_LENGTH 1
+struct {
+  unsigned length;
+  unsigned long long features[RISCV_FEATURE_BITS_LENGTH];
+} __riscv_feature_bits __attribute__((visibility("hidden"), nocommon));
+
+#define RISCV_VENDOR_FEATURE_BITS_LENGTH 1
+
+struct {
+  unsigned vendorID;
+  unsigned length;
+  unsigned long long features[RISCV_VENDOR_FEATURE_BITS_LENGTH];
+} __riscv_vendor_feature_bits __attribute__((visibility("hidden"), nocommon));
+
+#define A_GROUPID 0
+#define A_BITMASK (1ULL << 0)
+#define C_GROUPID 0
+#define C_BITMASK (1ULL << 2)
+#define D_GROUPID 0
+#define D_BITMASK (1ULL << 3)
+#define F_GROUPID 0
+#define F_BITMASK (1ULL << 5)
+#define I_GROUPID 0
+#define I_BITMASK (1ULL << 8)
+#define M_GROUPID 0
+#define M_BITMASK (1ULL << 12)
+#define V_GROUPID 0
+#define V_BITMASK (1ULL << 21)
+#define ZACAS_GROUPID 0
+#define ZACAS_BITMASK (1ULL << 26)
+#define ZBA_GROUPID 0
+#define ZBA_BITMASK (1ULL << 27)
+#define ZBB_GROUPID 0
+#define ZBB_BITMASK (1ULL << 28)
+#define ZBC_GROUPID 0
+#define ZBC_BITMASK (1ULL << 29)
+#define ZBKB_GROUPID 0
+#define ZBKB_BITMASK (1ULL << 30)
+#define ZBKC_GROUPID 0
+#define ZBKC_BITMASK (1ULL << 31)
+#define ZBKX_GROUPID 0
+#define ZBKX_BITMASK (1ULL << 32)
+#define ZBS_GROUPID 0
+#define ZBS_BITMASK (1ULL << 33)
+#define ZFA_GROUPID 0
+#define ZFA_BITMASK (1ULL << 34)
+#define ZFH_GROUPID 0
+#define ZFH_BITMASK (1ULL << 35)
+#define ZFHMIN_GROUPID 0
+#define ZFHMIN_BITMASK (1ULL << 36)
+#define ZICBOZ_GROUPID 0
+#define ZICBOZ_BITMASK (1ULL << 37)
+#define ZICOND_GROUPID 0
+#define ZICOND_BITMASK (1ULL << 38)
+#define ZIHINTNTL_GROUPID 0
+#define ZIHINTNTL_BITMASK (1ULL << 39)
+#define ZIHINTPAUSE_GROUPID 0
+#define ZIHINTPAUSE_BITMASK (1ULL << 40)
+#define ZKND_GROUPID 0
+#define ZKND_BITMASK (1ULL << 41)
+#define ZKNE_GROUPID 0
+#define ZKNE_BITMASK (1ULL << 42)
+#define ZKNH_GROUPID 0
+#define ZKNH_BITMASK (1ULL << 43)
+#define ZKSED_GROUPID 0
+#define ZKSED_BITMASK (1ULL << 44)
+#define ZKSH_GROUPID 0
+#define ZKSH_BITMASK (1ULL << 45)
+#define ZKT_GROUPID 0
+#define ZKT_BITMASK (1ULL << 46)
+#define ZTSO_GROUPID 0
+#define ZTSO_BITMASK (1ULL << 47)
+#define ZVBB_GROUPID 0
+#define ZVBB_BITMASK (1ULL << 48)
+#define ZVBC_GROUPID 0
+#define ZVBC_BITMASK (1ULL << 49)
+#define ZVFH_GROUPID 0
+#define ZVFH_BITMASK (1ULL << 50)
+#define ZVFHMIN_GROUPID

Re: [PATCH] RISC-V: Fix testcase missing arch attribute

[Kito Cheng]

LGTM :)

On Wed, Jul 17, 2024 at 9:15 AM Edwin Lu  wrote:
>
> The C + F extentions implies the zcf extension on rv32. Add missing zcf
> extension for the rv32 target.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/target-attr-16.c: Update expected assembly
>
> Signed-off-by: Edwin Lu 
> ---
>  gcc/testsuite/gcc.target/riscv/target-attr-16.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/target-attr-16.c 
> b/gcc/testsuite/gcc.target/riscv/target-attr-16.c
> index 1c7badccdee..c6b626d0c6c 100644
> --- a/gcc/testsuite/gcc.target/riscv/target-attr-16.c
> +++ b/gcc/testsuite/gcc.target/riscv/target-attr-16.c
> @@ -24,5 +24,5 @@ void bar (void)
>  {
>  }
>
> -/* { dg-final { scan-assembler-times ".option arch, 
> rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0"
>  4 { target { rv32 } } } } */
> +/* { dg-final { scan-assembler-times ".option arch, 
> rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0"
>  4 { target { rv32 } } } } */
>  /* { dg-final { scan-assembler-times ".option arch, 
> rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0"
>  4 { target { rv64 } } } } */
> --
> 2.34.1
>

Re: [PATCH] RISC-V: Implement __init_riscv_features_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

[Kito Cheng]

On Wed, Jul 17, 2024 at 1:14 AM Palmer Dabbelt  wrote:
>
> On Tue, 16 Jul 2024 07:49:13 PDT (-0700), kito.ch...@sifive.com wrote:
> > This provides a common abstraction layer to probe the available extensions 
> > at
> > run-time. These functions can be used to implement function 
> > multi-versioning or
> > to detect available extensions.
> >
> > The advantages of providing this abstraction layer are:
> > - Easy to port to other new platforms.
> > - Easier to maintain in GCC for function multi-versioning.
> >   - For example, maintaining platform-dependent code in C code/libgcc is 
> > much
> > easier than maintaining it in GCC by creating GIMPLEs...
> >
> > This API is intended to provide the capability to query minimal common 
> > available extensions on the system.
> >
> > Proposal in riscv-c-api-doc: 
> > https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74
> >
> > Full function multi-versioning implementation will come later. We are 
> > posting
> > this first because we intend to backport it to the GCC 14 branch to unblock
> > LLVM 19 to use this with GCC 14.2, rather than waiting for GCC 15.
>
> Is LLVM actually going to use this?  Last I heard the plan was to just
> wait until we're much closer to the glibc release so the hwprobe() libc
> ABI is frozen and then just call that directly.

Yes, current LLVM implementation(PR, not merged yet) still use that,
the guy who implement the LLVM part is our LLVM folk in Taiwan and he
would prefer this libgcc/compiler-rt over call hwprobe (either call by
ifunc resolver's function parameter or syscall directly), one another
point is we feel that's kinda layering violation if we implement that
in compiler (which without libgcc/compiler-rt), also again, it's not
easy to maintain and implement in either LLVM IR or GCC GIMPLE.

[PATCH] RISC-V: Implement __init_riscv_features_bits, __riscv_feature_bits, and __riscv_vendor_feature_bits

[Kito Cheng]

This provides a common abstraction layer to probe the available extensions at
run-time. These functions can be used to implement function multi-versioning or
to detect available extensions.

The advantages of providing this abstraction layer are:
- Easy to port to other new platforms.
- Easier to maintain in GCC for function multi-versioning.
  - For example, maintaining platform-dependent code in C code/libgcc is much
easier than maintaining it in GCC by creating GIMPLEs...

This API is intended to provide the capability to query minimal common 
available extensions on the system.

Proposal in riscv-c-api-doc: 
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74

Full function multi-versioning implementation will come later. We are posting
this first because we intend to backport it to the GCC 14 branch to unblock
LLVM 19 to use this with GCC 14.2, rather than waiting for GCC 15.

libgcc/ChangeLog:

* config/riscv/feature_bits.c: New.
* config/riscv/t-elf (LIB2ADD): Add feature_bits.c.
---
 libgcc/config/riscv/feature_bits.c | 298 +
 libgcc/config/riscv/t-elf  |   1 +
 2 files changed, 299 insertions(+)
 create mode 100644 libgcc/config/riscv/feature_bits.c

diff --git a/libgcc/config/riscv/feature_bits.c 
b/libgcc/config/riscv/feature_bits.c
new file mode 100644
index 000..c207dbba67c
--- /dev/null
+++ b/libgcc/config/riscv/feature_bits.c
@@ -0,0 +1,298 @@
+/* Helper function for function multi-versioning for RISC-V.
+
+   Copyright (C) 2024 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+for more details.
+
+Under Section 7 of GPL version 3, you are granted additional
+permissions described in the GCC Runtime Library Exception, version
+3.1, as published by the Free Software Foundation.
+
+You should have received a copy of the GNU General Public License and
+a copy of the GCC Runtime Library Exception along with this program;
+see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+.  */
+
+#define RISCV_FEATURE_BITS_LENGTH 1
+struct {
+  unsigned length;
+  unsigned long long features[RISCV_FEATURE_BITS_LENGTH];
+} __riscv_feature_bits __attribute__((visibility("hidden"), nocommon));
+
+#define RISCV_VENDOR_FEATURE_BITS_LENGTH 1
+
+struct {
+  unsigned vendorID;
+  unsigned length;
+  unsigned long long features[RISCV_VENDOR_FEATURE_BITS_LENGTH];
+} __riscv_vendor_feature_bits __attribute__((visibility("hidden"), nocommon));
+
+#define A_GROUPID 0
+#define A_BITMASK (1ULL << 0)
+#define C_GROUPID 0
+#define C_BITMASK (1ULL << 2)
+#define D_GROUPID 0
+#define D_BITMASK (1ULL << 3)
+#define F_GROUPID 0
+#define F_BITMASK (1ULL << 5)
+#define I_GROUPID 0
+#define I_BITMASK (1ULL << 8)
+#define M_GROUPID 0
+#define M_BITMASK (1ULL << 12)
+#define V_GROUPID 0
+#define V_BITMASK (1ULL << 21)
+#define ZACAS_GROUPID 0
+#define ZACAS_BITMASK (1ULL << 26)
+#define ZBA_GROUPID 0
+#define ZBA_BITMASK (1ULL << 27)
+#define ZBB_GROUPID 0
+#define ZBB_BITMASK (1ULL << 28)
+#define ZBC_GROUPID 0
+#define ZBC_BITMASK (1ULL << 29)
+#define ZBKB_GROUPID 0
+#define ZBKB_BITMASK (1ULL << 30)
+#define ZBKC_GROUPID 0
+#define ZBKC_BITMASK (1ULL << 31)
+#define ZBKX_GROUPID 0
+#define ZBKX_BITMASK (1ULL << 32)
+#define ZBS_GROUPID 0
+#define ZBS_BITMASK (1ULL << 33)
+#define ZFA_GROUPID 0
+#define ZFA_BITMASK (1ULL << 34)
+#define ZFH_GROUPID 0
+#define ZFH_BITMASK (1ULL << 35)
+#define ZFHMIN_GROUPID 0
+#define ZFHMIN_BITMASK (1ULL << 36)
+#define ZICBOZ_GROUPID 0
+#define ZICBOZ_BITMASK (1ULL << 37)
+#define ZICOND_GROUPID 0
+#define ZICOND_BITMASK (1ULL << 38)
+#define ZIHINTNTL_GROUPID 0
+#define ZIHINTNTL_BITMASK (1ULL << 39)
+#define ZIHINTPAUSE_GROUPID 0
+#define ZIHINTPAUSE_BITMASK (1ULL << 40)
+#define ZKND_GROUPID 0
+#define ZKND_BITMASK (1ULL << 41)
+#define ZKNE_GROUPID 0
+#define ZKNE_BITMASK (1ULL << 42)
+#define ZKNH_GROUPID 0
+#define ZKNH_BITMASK (1ULL << 43)
+#define ZKSED_GROUPID 0
+#define ZKSED_BITMASK (1ULL << 44)
+#define ZKSH_GROUPID 0
+#define ZKSH_BITMASK (1ULL << 45)
+#define ZKT_GROUPID 0
+#define ZKT_BITMASK (1ULL << 46)
+#define ZTSO_GROUPID 0
+#define ZTSO_BITMASK (1ULL << 47)
+#define ZVBB_GROUPID 0
+#define ZVBB_BITMASK (1ULL << 48)
+#define ZVBC_GROUPID 0
+#define ZVBC_BITMASK (1ULL << 49)
+#define ZVFH_GROUPID 0
+#define ZVFH_BITMASK (1ULL << 50)
+#define ZVFHMIN_GROUPID 0
+#define ZVFHMIN_BITMASK (1ULL << 51)
+#define ZVKB_GROUPID 0
+#define ZVKB_BITMASK (1ULL << 52)
+#define ZVKG_GROUPID 0
+#define ZVKG_BITMASK (1ULL << 53)
+#define ZVKNE

Re: [PATCH 5/6] RISC-V: Rewrite target attribute handling

[Kito Cheng]

On Tue, Jul 16, 2024 at 4:25 PM Christoph Müllner
 wrote:
>
> On Tue, Jul 16, 2024 at 4:45 AM Kito Cheng  wrote:
> >
> > On Tue, Jul 16, 2024 at 1:09 AM Christoph Müllner
> >  wrote:
> > >
> > > On Mon, Jul 15, 2024 at 11:10 AM Kito Cheng  wrote:
> > > >
> > > > LGTM, and could you backport this to the GCC 14 branch as well?
> > >
> > > Rebased, retested (multilib), fixed an issue related to Zca/Zcd and 
> > > pushed.
> > >
> > > Should the GCC 14 backport be posted for review before pushing?
> >
> > I guess the patch for GCC 14 may little different than this patch
> > series since Pan's rewrite isn't applied on that,
> > however I trust you will handle this well, so pre-approved for that  :P
>
> The hashtable rewrite is on GCC 14:
> git branch -a --contains 9941f0295a14659e25260458efd2e46a68ad0342
> [...]
>   remotes/origin/master
>   remotes/origin/releases/gcc-14
> [...]
>
> So the backport to GCC 14 would include all patches of this series
> with the exception of the alloca() patch.
> Adjustments are just needed for some of the tests, because "rv64gc" expands
> to less instruction sets in GCC14 (no zaamo1p0_zalrsc1p0_zca1p0_zcd1p0).
> I've already cherry-picked, adjusted and successfully tested that and
> will push if that's ok.

Yeah, I am ok with that :)

>
> BTW, I accidentally pushed the alloca()-patch to master.
> But I reverted that as soon as I noticed my mistake.
> Apologies for that!
>
> >
> > but don't forget to send committed patches to the mailing list (with
> > [committed][GCC-14] prefix in the title), so that we know you are done
> > :)

Re: [PATCH 5/6] RISC-V: Rewrite target attribute handling

[Kito Cheng]

On Tue, Jul 16, 2024 at 1:09 AM Christoph Müllner
 wrote:
>
> On Mon, Jul 15, 2024 at 11:10 AM Kito Cheng  wrote:
> >
> > LGTM, and could you backport this to the GCC 14 branch as well?
>
> Rebased, retested (multilib), fixed an issue related to Zca/Zcd and pushed.
>
> Should the GCC 14 backport be posted for review before pushing?

I guess the patch for GCC 14 may little different than this patch
series since Pan's rewrite isn't applied on that,
however I trust you will handle this well, so pre-approved for that  :P

but don't forget to send committed patches to the mailing list (with
[committed][GCC-14] prefix in the title), so that we know you are done
:)




>
> Thanks,
> Christoph
>
> >
> > On Tue, Jul 9, 2024 at 8:50 PM Christoph Müllner
> >  wrote:
> > >
> > > The target-arch attribute handling in RISC-V is only a few months old,
> > > but already saw a rewrite (9941f0295a14), which addressed an important
> > > issue.  This rewrite introduced a hash table in the backend, which is
> > > used to keep track of target-arch attributes of all functions.
> > > The index of this hash table is the pointer to the function declaration
> > > object (fndecl).  However, objects like these don't have the lifetime
> > > that is assumed here, which resulted in observing two fndecl objects
> > > with the same address for different objects (triggering the assertion
> > > in riscv_func_target_put() -- see also PR115562).
> > >
> > > This patch removes the hash table approach in favor of storing target
> > > specific options using the DECL_FUNCTION_SPECIFIC_TARGET() macro, which
> > > is also used by other backends and is specifically designed for this
> > > purpose (https://gcc.gnu.org/onlinedocs/gccint/Function-Properties.html).
> > >
> > > To have an accessible field in the target options, we need to
> > > adjust riscv.opt and introduce the field riscv_arch_string
> > > (for the already existing option '-march=').
> > >
> > > Using this macro allows to remove much code from riscv-common.cc, which
> > > controls access to the objects 'func_target_table' and 
> > > 'current_subset_list'.
> > >
> > > One thing to mention is, that we had two subset lists:
> > > current_subset_list and cmdline_subset_list, with the latter being
> > > introduced recently for target attribute handling.
> > > This patch reduces them back to one (cmdline_subset_list) which
> > > contains the list of extensions that have been enabled by the command
> > > line arguments.
> > >
> > > Note that the patch keeps the existing behavior of rejecting
> > > duplications of extensions when added via the '+' operator in a function
> > > target attribute.  E.g. "-march=rv64gc_zbb" and "arch=+zbb" will trigger
> > > an error (see pr115554.c).  However, at the same time this patch breaks
> > > the acceptance of adding implied extensions, which causes the following
> > > six regressions (with the error "extension 'EXT' appear more than one 
> > > time"):
> > > * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-39.c
> > > * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-42.c
> > > * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-43.c
> > > * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-44.c
> > > * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-45.c
> > > * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-46.c
> > >
> > > New tests were added to document the behavior and to ensure it won't
> > > regress.  This patch did not show any regressions for rv32/rv64
> > > and fixes the ICEs from PR115554 and PR115562.
> > >
> > > PR 115554
> > > PR 115562
> > >
> > > gcc/ChangeLog:
> > >
> > > * common/config/riscv/riscv-common.cc (struct 
> > > riscv_func_target_info):
> > > Remove.
> > > (struct riscv_func_target_hasher): Likewise.
> > > (riscv_func_decl_hash): Likewise.
> > > (riscv_func_target_hasher::hash): Likewise.
> > > (riscv_func_target_hasher::equal): Likewise.
> > > (riscv_current_subset_list): Likewise.
> > > (riscv_cmdline_subset_list): Remove obsolete space.
> > > (riscv_func_target_table_lazy_init): Remove.
> > > (riscv_func_target_get): Likew

Re: [PATCH 5/6] RISC-V: Rewrite target attribute handling

[Kito Cheng]

LGTM, and could you backport this to the GCC 14 branch as well?

On Tue, Jul 9, 2024 at 8:50 PM Christoph Müllner
 wrote:
>
> The target-arch attribute handling in RISC-V is only a few months old,
> but already saw a rewrite (9941f0295a14), which addressed an important
> issue.  This rewrite introduced a hash table in the backend, which is
> used to keep track of target-arch attributes of all functions.
> The index of this hash table is the pointer to the function declaration
> object (fndecl).  However, objects like these don't have the lifetime
> that is assumed here, which resulted in observing two fndecl objects
> with the same address for different objects (triggering the assertion
> in riscv_func_target_put() -- see also PR115562).
>
> This patch removes the hash table approach in favor of storing target
> specific options using the DECL_FUNCTION_SPECIFIC_TARGET() macro, which
> is also used by other backends and is specifically designed for this
> purpose (https://gcc.gnu.org/onlinedocs/gccint/Function-Properties.html).
>
> To have an accessible field in the target options, we need to
> adjust riscv.opt and introduce the field riscv_arch_string
> (for the already existing option '-march=').
>
> Using this macro allows to remove much code from riscv-common.cc, which
> controls access to the objects 'func_target_table' and 'current_subset_list'.
>
> One thing to mention is, that we had two subset lists:
> current_subset_list and cmdline_subset_list, with the latter being
> introduced recently for target attribute handling.
> This patch reduces them back to one (cmdline_subset_list) which
> contains the list of extensions that have been enabled by the command
> line arguments.
>
> Note that the patch keeps the existing behavior of rejecting
> duplications of extensions when added via the '+' operator in a function
> target attribute.  E.g. "-march=rv64gc_zbb" and "arch=+zbb" will trigger
> an error (see pr115554.c).  However, at the same time this patch breaks
> the acceptance of adding implied extensions, which causes the following
> six regressions (with the error "extension 'EXT' appear more than one time"):
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-39.c
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-42.c
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-43.c
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-44.c
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-45.c
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-46.c
>
> New tests were added to document the behavior and to ensure it won't
> regress.  This patch did not show any regressions for rv32/rv64
> and fixes the ICEs from PR115554 and PR115562.
>
> PR 115554
> PR 115562
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc (struct riscv_func_target_info):
> Remove.
> (struct riscv_func_target_hasher): Likewise.
> (riscv_func_decl_hash): Likewise.
> (riscv_func_target_hasher::hash): Likewise.
> (riscv_func_target_hasher::equal): Likewise.
> (riscv_current_subset_list): Likewise.
> (riscv_cmdline_subset_list): Remove obsolete space.
> (riscv_func_target_table_lazy_init): Remove.
> (riscv_func_target_get): Likewise.
> (riscv_func_target_put): Likewise.
> (riscv_func_target_remove_and_destory): Likewise.
> (riscv_arch_str): Generate from cmdline_subset_list.
> (riscv_set_arch_by_subset_list): Don't set current_subset_list.
> (riscv_parse_arch_string): Remove current_subset_list.
> * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
> Get subset list via riscv_cmdline_subset_list().
> * config/riscv/riscv-subset.h (riscv_current_subset_list):
> Remove prototype.
> (riscv_func_target_get): Likewise.
> (riscv_func_target_put): Likewise.
> (riscv_func_target_remove_and_destory): Likewise.
> * config/riscv/riscv-target-attr.cc 
> (riscv_target_attr_parser::parse_arch):
> Build base arch string from existing target options, if any.
> (riscv_target_attr_parser::update_settings): Store new arch
> string in target options.
> (riscv_process_one_target_attr): Whitespace fix.
> (riscv_process_target_attr): Drop opts argument.
> (riscv_option_valid_attribute_p): Properly save, change and restore
> target options.
> * config/riscv/riscv.cc (get_arch_str): New function.
> (riscv_declare_function_name): Get arch string for option-arch
> directive from function's target options.
> * config/riscv/riscv.opt: Add riscv_arch_string variable to
> march option.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/target-attr-01.c: Add test for option-arch 
> directive.
> * gcc.target/riscv/target-attr-02.c: Likewise.
> * gcc.target/riscv/target-attr-03

[committed] RISC-V: Add SiFive extensions, xsfvcp and xsfcease

[Kito Cheng]

We have already upstreamed these extensions into binutils, and now we need GCC
to recognize these extensions and pass them to binutils as well. We also plan
to upstream intrinsics in the near future. :)

gcc/ChangeLog:

* common/config/riscv/riscv-common.cc (riscv_implied_info): Add xsfvcp.
(riscv_ext_version_table): Add xsfvcp, xsfcease.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv.opt (riscv_sifive_subext): New.
(XSFVCP): New.
(XSFCEASE): New.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/predef-sf-1.c: New.
* gcc.target/riscv/predef-sf-2.c: New.
---
 gcc/common/config/riscv/riscv-common.cc  |  8 
 gcc/config/riscv/riscv.opt   |  7 +++
 gcc/testsuite/gcc.target/riscv/predef-sf-1.c | 19 +++
 gcc/testsuite/gcc.target/riscv/predef-sf-2.c | 14 ++
 4 files changed, 48 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-sf-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/predef-sf-2.c

diff --git a/gcc/common/config/riscv/riscv-common.cc 
b/gcc/common/config/riscv/riscv-common.cc
index 3c4178c19c9..d883efa7a3a 100644
--- a/gcc/common/config/riscv/riscv-common.cc
+++ b/gcc/common/config/riscv/riscv-common.cc
@@ -216,6 +216,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
   {"ssstateen", "zicsr"},
   {"sstc", "zicsr"},
 
+  {"xsfvcp", "zve32x"},
+
   {NULL, NULL}
 };
 
@@ -415,6 +417,9 @@ static const struct riscv_ext_version 
riscv_ext_version_table[] =
 
   {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
 
+  {"xsfvcp",   ISA_SPEC_CLASS_NONE, 1, 0},
+  {"xsfcease", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -1822,6 +1827,9 @@ static const riscv_ext_flag_table_t 
riscv_ext_flag_table[] =
 
   {"xventanacondops", &gcc_options::x_riscv_xventana_subext, 
MASK_XVENTANACONDOPS},
 
+  {"xsfvcp",   &gcc_options::x_riscv_sifive_subext, MASK_XSFVCP},
+  {"xsfcease", &gcc_options::x_riscv_sifive_subext, MASK_XSFCEASE},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 32a0dda5843..a1d70b63638 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -507,6 +507,13 @@ int riscv_xventana_subext
 
 Mask(XVENTANACONDOPS) Var(riscv_xventana_subext)
 
+TargetVariable
+int riscv_sifive_subext
+
+Mask(XSFVCP) Var(riscv_sifive_subext)
+
+Mask(XSFCEASE) Var(riscv_sifive_subext)
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/testsuite/gcc.target/riscv/predef-sf-1.c 
b/gcc/testsuite/gcc.target/riscv/predef-sf-1.c
new file mode 100644
index 000..d6c07e7d920
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-sf-1.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xsfvcp -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_zve32x)
+#error "__riscv_zve32x"
+#endif
+
+
+#if !defined(__riscv_xsfvcp)
+#error "__riscv_xsfvcp"
+#endif
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/riscv/predef-sf-2.c 
b/gcc/testsuite/gcc.target/riscv/predef-sf-2.c
new file mode 100644
index 000..dcb746bcd26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/predef-sf-2.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_xsfcease -mabi=lp64" } */
+
+int main () {
+#if !defined(__riscv)
+#error "__riscv"
+#endif
+
+#if !defined(__riscv_xsfcease)
+#error "__riscv_xsfvcp"
+#endif
+
+  return 0;
+}
-- 
2.34.1

Re: Re: [PATCH v2] RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access[PR115862]

[Kito Cheng]

Oh, okay, my fault, I didn't read the bugzilla, so you can go ahead :P


On Fri, Jul 12, 2024 at 3:51 PM Li Xu  wrote:
>
> Sorry, I didn't understand.
>
> >>but...this seems to have discovered another bug in the current  trunk?
>
> Isn't PR115862 the same bug as this one?
>
> ____
> xu...@eswincomputing.com
>
>
> From: Kito Cheng
> Date: 2024-07-12 14:33
> To: Li Xu
> CC: gcc-patches; juzhe.zhong; rdapp.gcc
> Subject: Re: [PATCH v2] RISC-V: Disable misaligned vector access in hook 
> riscv_slow_unaligned_access[PR115862]
> LGTM, but...this seems to have discovered another bug in the current
> trunk? could you take a look?
>
> Will trigger by -O2 -march=rv64gcv_zvl512b -mabi=lp64d or -O2
> -march=rv64gcv_zvl256b -mabi=lp64d
>
> during RTL pass: combine
> x.c: In function '__libc_mallinfo':
> x.c:47:1: internal compiler error: in smallest_mode_for_size, at
> stor-layout.cc:356
>   47 | }
>  | ^
> 0x2dc82e2 internal_error(char const*, ...)
>
> ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/diagnostic-global-context.cc:491
> 0xc8fdfe fancy_abort(char const*, int, char const*)
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/diagnostic.cc:1725
> 0x13bf6b7 smallest_mode_for_size(poly_int<2u, unsigned long>, mode_class)
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/stor-layout.cc:356
> 0x126efea smallest_int_mode_for_size(poly_int<2u, unsigned long>)
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/machmode.h:916
> 0x126efea get_best_extraction_insn
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs-query.cc:208
> 0x269ac14 make_extraction
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:7779
> 0x269beff make_compound_operation_int
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:8186
> 0x269cf3f make_compound_operation(rtx_def*, rtx_code)
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:8471
> 0x26a0c8e simplify_set
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:6975
> 0x26a0c8e combine_simplify_rtx
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:6374
> 0x26a2f2f subst
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:5630
> 0x26a6fc1 try_combine
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:3312
> 0x26ac211 combine_instructions
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:1264
> 0x26ac211 rest_of_handle_combine
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:15127
> 0x26ac211 execute
>../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:15171
> Please submit a full bug report, with preprocessed source (by using
> -freport-bug).
> Please include the complete backtrace with any bug report.
> See <https://gcc.gnu.org/bugs/> for instructions.
>
> On Fri, Jul 12, 2024 at 8:48 AM Li Xu  wrote:
> >
> > From: xuli 
> >
> > The reason is that in the following code, icode = movmisalignv8si has
> > already been rejected by TARGET_VECTOR_MISALIGN_SUPPORTED, but it is
> > allowed by targetm.slow_unaligned_access,which is contradictory.
> >
> > (((icode = optab_handler (movmisalign_optab, mode))
> >!= CODE_FOR_nothing)
> >   || targetm.slow_unaligned_access (mode, align))
> >
> > misaligned vector access should be enabled by -mno-vector-strict-align 
> > option.
> >
> > PR Target/115862
> >
> > gcc/ChangeLog:
> >
> > * config/riscv/riscv.cc (riscv_slow_unaligned_access): Disable 
> > vector misalign.
> >
> > Signed-off-by: Li Xu 
> > ---
> >  gcc/config/riscv/riscv.cc |  5 +-
> >  .../gcc.target/riscv/rvv/base/pr115862.c  | 52 +++
> >  2 files changed, 55 insertions(+), 2 deletions(-)
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c
> >
> > diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> > index 61fa74e9322..16b210f323e 100644
> > --- a/gcc/config/riscv/riscv.cc
> > +++ b/gcc/config/riscv/riscv.cc
> > @@ -10269,9 +10269,10 @@ riscv_cannot_copy_insn_p (rtx_insn *insn)
> >  /* Implement TARGET_SLOW_UNALIGNED_ACCESS.  */
> >
> >  static bool
> > -riscv_slow_unaligned_access (machine_mode, unsigned int)
> > +riscv_slow_unaligned_access (machine_mode mode, unsigned int)
> >  {
> > -  return riscv_slow_unaligned_access_p;
> > +  return VECTOR_MODE_P (mode) ? TARGET_VECTOR_MISALIGN_SUPPORTED
> > + : riscv_slow_unaligned_access_p;
> >  }
> &

Re: [PATCH v2] RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access[PR115862]

[Kito Cheng]

LGTM, but...this seems to have discovered another bug in the current
trunk? could you take a look?

Will trigger by -O2 -march=rv64gcv_zvl512b -mabi=lp64d or -O2
-march=rv64gcv_zvl256b -mabi=lp64d

during RTL pass: combine
x.c: In function '__libc_mallinfo':
x.c:47:1: internal compiler error: in smallest_mode_for_size, at
stor-layout.cc:356
  47 | }
 | ^
0x2dc82e2 internal_error(char const*, ...)
   
../../../../riscv-gnu-toolchain-trunk/gcc/gcc/diagnostic-global-context.cc:491
0xc8fdfe fancy_abort(char const*, int, char const*)
   ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/diagnostic.cc:1725
0x13bf6b7 smallest_mode_for_size(poly_int<2u, unsigned long>, mode_class)
   ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/stor-layout.cc:356
0x126efea smallest_int_mode_for_size(poly_int<2u, unsigned long>)
   ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/machmode.h:916
0x126efea get_best_extraction_insn
   ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/optabs-query.cc:208
0x269ac14 make_extraction
   ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:7779
0x269beff make_compound_operation_int
   ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:8186
0x269cf3f make_compound_operation(rtx_def*, rtx_code)
   ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:8471
0x26a0c8e simplify_set
   ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:6975
0x26a0c8e combine_simplify_rtx
   ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:6374
0x26a2f2f subst
   ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:5630
0x26a6fc1 try_combine
   ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:3312
0x26ac211 combine_instructions
   ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:1264
0x26ac211 rest_of_handle_combine
   ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:15127
0x26ac211 execute
   ../../../../riscv-gnu-toolchain-trunk/gcc/gcc/combine.cc:15171
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See  for instructions.

On Fri, Jul 12, 2024 at 8:48 AM Li Xu  wrote:
>
> From: xuli 
>
> The reason is that in the following code, icode = movmisalignv8si has
> already been rejected by TARGET_VECTOR_MISALIGN_SUPPORTED, but it is
> allowed by targetm.slow_unaligned_access,which is contradictory.
>
> (((icode = optab_handler (movmisalign_optab, mode))
>!= CODE_FOR_nothing)
>   || targetm.slow_unaligned_access (mode, align))
>
> misaligned vector access should be enabled by -mno-vector-strict-align option.
>
> PR Target/115862
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_slow_unaligned_access): Disable vector 
> misalign.
>
> Signed-off-by: Li Xu 
> ---
>  gcc/config/riscv/riscv.cc |  5 +-
>  .../gcc.target/riscv/rvv/base/pr115862.c  | 52 +++
>  2 files changed, 55 insertions(+), 2 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 61fa74e9322..16b210f323e 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -10269,9 +10269,10 @@ riscv_cannot_copy_insn_p (rtx_insn *insn)
>  /* Implement TARGET_SLOW_UNALIGNED_ACCESS.  */
>
>  static bool
> -riscv_slow_unaligned_access (machine_mode, unsigned int)
> +riscv_slow_unaligned_access (machine_mode mode, unsigned int)
>  {
> -  return riscv_slow_unaligned_access_p;
> +  return VECTOR_MODE_P (mode) ? TARGET_VECTOR_MISALIGN_SUPPORTED
> + : riscv_slow_unaligned_access_p;
>  }
>
>  static bool
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c
> new file mode 100644
> index 000..3cbc3c3a0ea
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115862.c
> @@ -0,0 +1,52 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=rv64gcv_zvl512b -mabi=lp64d" } */
> +
> +struct mallinfo2
> +{
> +  int arena;
> +  int ordblks;
> +  int smblks;
> +  int hblks;
> +  int hblkhd;
> +  int usmblks;
> +  int fsmblks;
> +  int uordblks;
> +  int fordblks;
> +  int keepcost;
> +};
> +
> +struct mallinfo
> +{
> +  int arena;
> +  int ordblks;
> +  int smblks;
> +  int hblks;
> +  int hblkhd;
> +  int usmblks;
> +  int fsmblks;
> +  int uordblks;
> +  int fordblks;
> +  int keepcost;
> +};
> +
> +struct mallinfo
> +__libc_mallinfo (void)
> +{
> +  struct mallinfo m;
> +  struct mallinfo2 m2;
> +
> +  m.arena = m2.arena;
> +  m.ordblks = m2.ordblks;
> +  m.smblks = m2.smblks;
> +  m.hblks = m2.hblks;
> +  m.hblkhd = m2.hblkhd;
> +  m.usmblks = m2.usmblks;
> +  m.fsmblks = m2.fsmblks;
> +  m.uordblks = m2.uordblks;
> +  m.fordblks = m2.fordblks;
> +  m.keepcost = m2.keepcost;
> +
> +  return m;
> +}
> +
> +/* { dg-final { scan-assembler {vle

Re: [PATCH v2] RISC-V: NO_WARNING preferred else value for RVV

[Kito Cheng]

Lgtm, thanks :)

YunQiang Su 於 2024年7月11日 週四，20:45寫道：

> From: YunQiang Su 
>
> PR target/115840.
>
> In riscv_preferred_else_value, we create an uninitialized tmp var
> for else value, instead of the 0 (as default_preferred_else_value)
> or the pre-exists VAR (as aarch64 does), so that we can use agnostic
> policy.
>
> The problem is that `warn_uninit` will emit a warning:
>   '({anonymous})' may be used uninitialized
>
> Let's mark this tmp var as NO_WARNING.
>
> This problem is found when I try to build glibc with V extension.
>
> gcc
> PR target/115840.
> * config/riscv/riscv.cc(riscv_preferred_else_value): Mark
> tmp_var as NO_WARNING.
>
> gcc/testsuite
> * gcc.dg/vect/pr115840.c: New testcase.
> ---
>  gcc/config/riscv/riscv.cc|  6 +-
>  gcc/testsuite/gcc.dg/vect/pr115840.c | 11 +++
>  2 files changed, 16 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.dg/vect/pr115840.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 61fa74e9322..276998a992b 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -11431,7 +11431,11 @@ riscv_preferred_else_value (unsigned ifn, tree
> vectype, unsigned int nops,
> tree *ops)
>  {
>if (riscv_v_ext_mode_p (TYPE_MODE (vectype)))
> -return get_or_create_ssa_default_def (cfun, create_tmp_var (vectype));
> +{
> +  tree tmp_var = create_tmp_var (vectype);
> +  TREE_NO_WARNING (tmp_var) = 1;
> +  return get_or_create_ssa_default_def (cfun, tmp_var);
> +}
>
>return default_preferred_else_value (ifn, vectype, nops, ops);
>  }
> diff --git a/gcc/testsuite/gcc.dg/vect/pr115840.c
> b/gcc/testsuite/gcc.dg/vect/pr115840.c
> new file mode 100644
> index 000..09dc9e4eb7c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.dg/vect/pr115840.c
> @@ -0,0 +1,11 @@
> +/* { dg-do compile } */
> +/* { dg-additional-options "-Wall -Werror" } */
> +
> +double loads[16];
> +
> +void
> +foo (double loadavg[], int count)
> +{
> +  for (int i = 0; i < count; i++)
> +loadavg[i] = loads[i] / 1.5;
> +}
> --
> 2.45.1
>
>

Re: [PATCH 1/3 v3] RISC-V: Add vector type of BFloat16 format

[Kito Cheng]

OK for this patch set, I know you already got LGTM from JuZhe or me
before, so just an explicitly ack to let you know it's still OK once
CI is passed.

On Thu, Jul 11, 2024 at 3:11 PM Feng Wang  wrote:
>
> v3: Rebase
> v2: Rebase
> The vector type of BFloat16 format is added in this patch,
> subsequent extensions to zvfbfmin and zvfwma need to be based
> on this patch.
>
> Signed-off-by: Feng Wang 
> gcc/ChangeLog:
>
> * config/riscv/genrvv-type-indexer.cc (bfloat16_type):
> Generate bf16 vector_type and scalar_type in DEF_RVV_TYPE_INDEX.
> (bfloat16_wide_type): Ditto.
> (same_ratio_eew_bf16_type): Ditto.
> (main): Ditto.
> * config/riscv/riscv-modes.def (ADJUST_BYTESIZE):
> (RVV_WHOLE_MODES): Add vector type for BFloat16.
> (RVV_FRACT_MODE): Ditto.
> (RVV_NF4_MODES): Ditto.
> (RVV_NF8_MODES): Ditto.
> (RVV_NF2_MODES): Ditto.
> * config/riscv/riscv-vector-builtins-types.def (vbfloat16mf4_t):
> (vbfloat16mf2_t): Add builtin vector type for BFloat16.
> (vbfloat16m1_t): Ditto.
> (vbfloat16m2_t): Ditto.
> (vbfloat16m4_t): Ditto.
> (vbfloat16m8_t): Ditto.
> (vbfloat16mf4x2_t): Ditto.
> (vbfloat16mf4x3_t): Ditto.
> (vbfloat16mf4x4_t): Ditto.
> (vbfloat16mf4x5_t): Ditto.
> (vbfloat16mf4x6_t): Ditto.
> (vbfloat16mf4x7_t): Ditto.
> (vbfloat16mf4x8_t): Ditto.
> (vbfloat16mf2x2_t): Ditto.
> (vbfloat16mf2x3_t): Ditto.
> (vbfloat16mf2x4_t): Ditto.
> (vbfloat16mf2x5_t): Ditto.
> (vbfloat16mf2x6_t): Ditto.
> (vbfloat16mf2x7_t): Ditto.
> (vbfloat16mf2x8_t): Ditto.
> (vbfloat16m1x2_t): Ditto.
> (vbfloat16m1x3_t): Ditto.
> (vbfloat16m1x4_t): Ditto.
> (vbfloat16m1x5_t): Ditto.
> (vbfloat16m1x6_t): Ditto.
> (vbfloat16m1x7_t): Ditto.
> (vbfloat16m1x8_t): Ditto.
> (vbfloat16m2x2_t): Ditto.
> (vbfloat16m2x3_t): Ditto.
> (vbfloat16m2x4_t): Ditto.
> (vbfloat16m4x2_t): Ditto.
> * config/riscv/riscv-vector-builtins.cc (check_required_extensions):
> Add required_ext checking for BFloat16.
> * config/riscv/riscv-vector-builtins.def (vbfloat16mf4_t):
> Add vector_type for BFloat16 in builtins.def.
> (vbfloat16mf4x2_t): Ditto.
> (vbfloat16mf4x3_t): Ditto.
> (vbfloat16mf4x4_t): Ditto.
> (vbfloat16mf4x5_t): Ditto.
> (vbfloat16mf4x6_t): Ditto.
> (vbfloat16mf4x7_t): Ditto.
> (vbfloat16mf4x8_t): Ditto.
> (vbfloat16mf2_t): Ditto.
> (vbfloat16mf2x2_t): Ditto.
> (vbfloat16mf2x3_t): Ditto.
> (vbfloat16mf2x4_t): Ditto.
> (vbfloat16mf2x5_t): Ditto.
> (vbfloat16mf2x6_t): Ditto.
> (vbfloat16mf2x7_t): Ditto.
> (vbfloat16mf2x8_t): Ditto.
> (vbfloat16m1_t): Ditto.
> (vbfloat16m1x2_t): Ditto.
> (vbfloat16m1x3_t): Ditto.
> (vbfloat16m1x4_t): Ditto.
> (vbfloat16m1x5_t): Ditto.
> (vbfloat16m1x6_t): Ditto.
> (vbfloat16m1x7_t): Ditto.
> (vbfloat16m1x8_t): Ditto.
> (vbfloat16m2_t): Ditto.
> (vbfloat16m2x2_t): Ditto.
> (vbfloat16m2x3_t): Ditto.
> (vbfloat16m2x4_t): Ditto.
> (vbfloat16m4_t): Ditto.
> (vbfloat16m4x2_t): Ditto.
> (vbfloat16m8_t): Ditto.
> (double_trunc_bfloat_scalar): Add scalar_type def for BFloat16.
> (double_trunc_bfloat_vector): Add vector_type def for BFloat16.
> * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_BF_16):
> Add required defination of BFloat16 ext.
> * config/riscv/riscv-vector-switch.def (ENTRY):
> Add vector_type information for BFloat16.
> (TUPLE_ENTRY): Add tuple vector_type information for BFloat16.
>
> ---
>  gcc/config/riscv/genrvv-type-indexer.cc   | 115 ++
>  gcc/config/riscv/riscv-modes.def  |  30 -
>  .../riscv/riscv-vector-builtins-types.def |  50 
>  gcc/config/riscv/riscv-vector-builtins.cc |   7 +-
>  gcc/config/riscv/riscv-vector-builtins.def|  55 -
>  gcc/config/riscv/riscv-vector-builtins.h  |   1 +
>  gcc/config/riscv/riscv-vector-switch.def  |  36 ++
>  7 files changed, 291 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/genrvv-type-indexer.cc 
> b/gcc/config/riscv/genrvv-type-indexer.cc
> index 27cbd14982c..8626ddeaaa8 100644
> --- a/gcc/config/riscv/genrvv-type-indexer.cc
> +++ b/gcc/config/riscv/genrvv-type-indexer.cc
> @@ -117,6 +117,42 @@ inttype (unsigned sew, int lmul_log2, unsigned nf, bool 
> unsigned_p)
>return mode.str ();
>  }
>
> +std::string
> +bfloat16_type (int lmul_log2)
> +{
> +  if (!valid_type (16, lmul_log2, /*float_t*/ true))
> +return "INVALID";
> +
> +  std::stringstream mode;
> +  mode << "vbfloat16" << to_l

Re: [PATCH] RISC-V: Disable misaligned vector access in hook riscv_slow_unaligned_access

[Kito Cheng]

> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 61fa74e9322..87270fd7af4 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -10271,7 +10271,7 @@ riscv_cannot_copy_insn_p (rtx_insn *insn)
>  static bool
>  riscv_slow_unaligned_access (machine_mode, unsigned int)
>  {
> -  return riscv_slow_unaligned_access_p;
> +  return !TARGET_VECTOR && riscv_slow_unaligned_access_p;

I guess this should be considered whether the mode is vector mode or
not, something like that?

return VECTOR_MODE_P (mode) ? TARGET_VECTOR_MISALIGN_SUPPORTED
 : riscv_slow_unaligned_access_p;

>  }
>
>  static bool
> --
> 2.17.1
>

Re: [PATCH 6/6] RISC-V: Allow adding enabled extension via target arch attributes

[Kito Cheng]

LGTM, thanks for fixing this...and will take a detailed review on the
remaining patch in the next few days :)


On Tue, Jul 9, 2024 at 8:51 PM Christoph Müllner
 wrote:
>
> The set of enabled extensions can be extended via target arch function
> attributes by listing each extension with a '+' prefix and a comma as
> list separator.  E.g.:
>   __attribute__((target("arch=+zba,+zbb"))) void foo();
>
> The programmer intends to ensure that one or more extensions
> are enabled when building the code.  This is independent of the arch
> string that is passed at build time via the -march= option.
>
> Therefore, it is reasonable to allow enabling extensions via target arch
> attributes, which have already been enabled via the -march= string.
>
> The subset list code already supports such duplication for implied
> extensions.  This patch adds an interface so the subset list
> parser can be switched into a mode where duplication is allowed.
>
> This commit fixes the following regressed test cases:
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-39.c
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-42.c
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-43.c
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-44.c
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-45.c
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-46.c
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc (riscv_subset_list::add):
> Allow adding enabled extension if m_allow_adding_dup is set.
> * config/riscv/riscv-subset.h: Add m_allow_adding_dup and setter.
> * config/riscv/riscv-target-attr.cc 
> (riscv_target_attr_parser::parse_arch):
> Allow adding enabled extensions.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/pr115554.c: Change expected fail to expected pass.
> * gcc.target/riscv/target-attr-16.c: New test.
>
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/common/config/riscv/riscv-common.cc   | 17 +++-
>  gcc/config/riscv/riscv-subset.h   |  5 
>  gcc/config/riscv/riscv-target-attr.cc |  3 +++
>  gcc/testsuite/gcc.target/riscv/pr115554.c |  2 --
>  .../gcc.target/riscv/target-attr-16.c | 26 +++
>  5 files changed, 45 insertions(+), 8 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/target-attr-16.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index c215484c287b..be4a87abee6d 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -677,12 +677,17 @@ riscv_subset_list::add (const char *subset, int 
> major_version,
>   ext->minor_version = minor_version;
> }
>else
> -   error_at (
> - m_loc,
> - "%<-march=%s%>: extension %qs appear more than one time",
> - m_arch,
> - subset);
> -
> +   {
> + /* The extension is already in the list.  */
> + if (!m_allow_adding_dup
> + || ext->major_version != major_version
> + || ext->minor_version != minor_version)
> +   error_at (
> + m_loc,
> + "%<-march=%s%>: extension %qs appear more than one time",
> + m_arch,
> + subset);
> +   }
>return;
>  }
>else if (strlen (subset) == 1 && !standard_extensions_p (subset))
> diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
> index 256d28657460..c2d213c1734f 100644
> --- a/gcc/config/riscv/riscv-subset.h
> +++ b/gcc/config/riscv/riscv-subset.h
> @@ -62,6 +62,9 @@ private:
>/* X-len of m_arch. */
>unsigned m_xlen;
>
> +  /* Allow adding the same extension more than once.  */
> +  bool m_allow_adding_dup;
> +
>riscv_subset_list (const char *, location_t);
>
>const char *parsing_subset_version (const char *, const char *, unsigned *,
> @@ -106,6 +109,8 @@ public:
>
>void set_loc (location_t);
>
> +  void set_allow_adding_dup (bool v) { m_allow_adding_dup = v; }
> +
>void finalize ();
>  };
>
> diff --git a/gcc/config/riscv/riscv-target-attr.cc 
> b/gcc/config/riscv/riscv-target-attr.cc
> index 317806143949..57235c9c0a7e 100644
> --- a/gcc/config/riscv/riscv-target-attr.cc
> +++ b/gcc/config/riscv/riscv-target-attr.cc
> @@ -109,6 +109,8 @@ riscv_target_attr_parser::parse_arch (const char *str)
>   ? riscv_subset_list::parse (local_arch_str, m_loc)
>   : riscv_cmdline_subset_list ()->clone ();
>m_subset_list->set_loc (m_loc);
> +  m_subset_list->set_allow_adding_dup (true);
> +
>while (token)
> {
>   if (token[0] != '+')
> @@ -134,6 +136,7 @@ riscv_target_attr_parser::parse_arch (const char *str)
>   token = strtok_r (NULL, ",", &str_to_check);
> }
>
> +  m_subset_list->set_allow_adding_dup (false);
> 

Re: [PATCH 2/6] RISC-V: Deduplicate arch subset list processing

[Kito Cheng]

LGTM, thanks for simplifying this :)

On Tue, Jul 9, 2024 at 8:48 PM Christoph Müllner
 wrote:
>
> We have a code duplication in riscv_set_arch_by_subset_list() and
> riscv_parse_arch_string(), where the latter function parses an ISA string
> into a subset_list before doing the same as the former function.
>
> riscv_parse_arch_string() is used to process command line options and
> riscv_set_arch_by_subset_list() processes target attributes.
> So, it is obvious that both functions should do the same.
> Let's deduplicate the code to enforce this.
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc (riscv_set_arch_by_subset_list):
> Fix overlong line.
> (riscv_parse_arch_string): Replace duplicated code by a call to
> riscv_set_arch_by_subset_list.
>
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/common/config/riscv/riscv-common.cc | 32 +
>  1 file changed, 6 insertions(+), 26 deletions(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 16bdb3fd2259..dfe960e51293 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -1818,7 +1818,8 @@ riscv_set_arch_by_subset_list (riscv_subset_list 
> *subset_list,
>else if (subset_list->xlen () == 64)
> opts->x_target_flags |= MASK_64BIT;
>
> -  for (arch_ext_flag_tab = &riscv_ext_flag_table[0]; 
> arch_ext_flag_tab->ext;
> +  for (arch_ext_flag_tab = &riscv_ext_flag_table[0];
> +  arch_ext_flag_tab->ext;
>++arch_ext_flag_tab)
> {
>   if (subset_list->lookup (arch_ext_flag_tab->ext))
> @@ -1842,30 +1843,6 @@ riscv_parse_arch_string (const char *isa,
>if (!subset_list)
>  return;
>
> -  if (opts)
> -{
> -  const riscv_ext_flag_table_t *arch_ext_flag_tab;
> -  /* Clean up target flags before we set.  */
> -  for (arch_ext_flag_tab = &riscv_ext_flag_table[0];
> -  arch_ext_flag_tab->ext;
> -  ++arch_ext_flag_tab)
> -   opts->*arch_ext_flag_tab->var_ref &= ~arch_ext_flag_tab->mask;
> -
> -  if (subset_list->xlen () == 32)
> -   opts->x_target_flags &= ~MASK_64BIT;
> -  else if (subset_list->xlen () == 64)
> -   opts->x_target_flags |= MASK_64BIT;
> -
> -
> -  for (arch_ext_flag_tab = &riscv_ext_flag_table[0];
> -  arch_ext_flag_tab->ext;
> -  ++arch_ext_flag_tab)
> -   {
> - if (subset_list->lookup (arch_ext_flag_tab->ext))
> -   opts->*arch_ext_flag_tab->var_ref |= arch_ext_flag_tab->mask;
> -   }
> -}
> -
>/* Avoid double delete if current_subset_list equals cmdline_subset_list.  
> */
>if (current_subset_list && current_subset_list != cmdline_subset_list)
>  delete current_subset_list;
> @@ -1873,7 +1850,10 @@ riscv_parse_arch_string (const char *isa,
>if (cmdline_subset_list)
>  delete cmdline_subset_list;
>
> -  current_subset_list = cmdline_subset_list = subset_list;
> +  cmdline_subset_list = subset_list;
> +  /* current_subset_list is set in the call below.  */
> +
> +  riscv_set_arch_by_subset_list (subset_list, opts);
>  }
>
>  /* Return the riscv_cpu_info entry for CPU, NULL if not found.  */
> --
> 2.45.2
>

Re: [PATCH 1/6] RISC-V: testsuite: Properly gate LTO tests

[Kito Cheng]

LGTM

On Tue, Jul 9, 2024 at 8:48 PM Christoph Müllner
 wrote:
>
> There are two test cases with the following skip directive:
>   dg-skip-if "" { *-*-* } { "-flto -fno-fat-lto-objects" }
> This reads as: skip if both '-flto' and '-fno-fat-lto-objects'
> are present.  This is not the case if only '-flto' is present.
>
> Since both tests depend on instruction sequences (one does
> check-function-bodies the other tests for an assembler error
> message), they won't work reliably with fat LTO objects.
>
> Let's change the skip line to gate the test on '-flto'
> to avoid failing tests like this:
>
> FAIL: gcc.target/riscv/interrupt-misaligned.c   -O2 -flto   
> check-function-bodies interrupt
> FAIL: gcc.target/riscv/interrupt-misaligned.c   -O2 -flto 
> -flto-partition=none   check-function-bodies interrupt
> FAIL: gcc.target/riscv/pr93202.c   -O2 -flto   (test for errors, line 10)
> FAIL: gcc.target/riscv/pr93202.c   -O2 -flto   (test for errors, line 9)
> FAIL: gcc.target/riscv/pr93202.c   -O2 -flto -flto-partition=none   (test for 
> errors, line 10)
> FAIL: gcc.target/riscv/pr93202.c   -O2 -flto -flto-partition=none   (test for 
> errors, line 9)
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/interrupt-misaligned.c: Remove
>   "-fno-fat-lto-objects" from skip condition.
> * gcc.target/riscv/pr93202.c: Likewise.
>
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c | 2 +-
>  gcc/testsuite/gcc.target/riscv/pr93202.c  | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c 
> b/gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c
> index b5f8e6c2bbef..912f180e4d65 100644
> --- a/gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c
> +++ b/gcc/testsuite/gcc.target/riscv/interrupt-misaligned.c
> @@ -1,6 +1,6 @@
>  /* { dg-do compile } */
>  /* { dg-options "-O2 -march=rv64gc -mabi=lp64d -fno-schedule-insns 
> -fno-schedule-insns2" } */
> -/* { dg-skip-if "" { *-*-* } { "-flto -fno-fat-lto-objects" } } */
> +/* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  /*  Make sure no stack offset are misaligned.
>  **  interrupt:
> diff --git a/gcc/testsuite/gcc.target/riscv/pr93202.c 
> b/gcc/testsuite/gcc.target/riscv/pr93202.c
> index 5501191ea52c..5de003fac421 100644
> --- a/gcc/testsuite/gcc.target/riscv/pr93202.c
> +++ b/gcc/testsuite/gcc.target/riscv/pr93202.c
> @@ -1,7 +1,7 @@
>  /* PR inline-asm/93202 */
>  /* { dg-do compile { target fpic } } */
>  /* { dg-options "-fpic" } */
> -/* { dg-skip-if "" { *-*-* } { "-flto -fno-fat-lto-objects" } } */
> +/* { dg-skip-if "" { *-*-* } { "-flto" } } */
>
>  void
>  foo (void)
> --
> 2.45.2
>

Re: [PATCH 4/6] RISC-V: Fix comment/naming in attribute parsing code

[Kito Cheng]

LGTM, that must be something I didn't update during...reference code from ARM :P


On Tue, Jul 9, 2024 at 8:48 PM Christoph Müllner
 wrote:
>
> Function target attributes have to be separated by semi-colons.
> Let's fix the comment and variable naming to better explain what
> the code does.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-target-attr.cc (riscv_process_target_attr):
> Fix comments and variable names.
>
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/config/riscv/riscv-target-attr.cc | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-target-attr.cc 
> b/gcc/config/riscv/riscv-target-attr.cc
> index e59cc53f23c6..3d7753f64574 100644
> --- a/gcc/config/riscv/riscv-target-attr.cc
> +++ b/gcc/config/riscv/riscv-target-attr.cc
> @@ -335,11 +335,11 @@ riscv_process_target_attr (tree fndecl, tree args, 
> location_t loc,
>char *str_to_check = (char *) alloca (len + 1);
>strcpy (str_to_check, TREE_STRING_POINTER (args));
>
> -  /* Used to catch empty spaces between commas i.e.
> +  /* Used to catch empty spaces between semi-colons i.e.
>   attribute ((target ("attr1;;attr2"))).  */
> -  unsigned int num_commas = num_occurences_in_str (';', str_to_check);
> +  unsigned int num_semicolons = num_occurences_in_str (';', str_to_check);
>
> -  /* Handle multiple target attributes separated by ','.  */
> +  /* Handle multiple target attributes separated by ';'.  */
>char *token = strtok_r (str_to_check, ";", &str_to_check);
>
>riscv_target_attr_parser attr_parser (loc);
> @@ -351,7 +351,7 @@ riscv_process_target_attr (tree fndecl, tree args, 
> location_t loc,
>token = strtok_r (NULL, ";", &str_to_check);
>  }
>
> -  if (num_attrs != num_commas + 1)
> +  if (num_attrs != num_semicolons + 1)
>  {
>error_at (loc, "malformed % attribute",
> TREE_STRING_POINTER (args));
> --
> 2.45.2
>

Re: [PATCH 3/6] RISC-V: Attribute parser: Use alloca() instead of new + std::unique_ptr

[Kito Cheng]

IIRC Jeff mentions that it may introduce buffer overflow if the input
string is long enough.

On Tue, Jul 9, 2024 at 8:48 PM Christoph Müllner
 wrote:
>
> Allocating an object on the heap with new, wrapping it in a
> std::unique_ptr and finally getting the buffer via buf.get()
> is a correct way to allocate a buffer that is automatically
> freed on return.  However, a simple invocation of alloca()
> does the same with less overhead.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-target-attr.cc 
> (riscv_target_attr_parser::parse_arch):
> Replace new + std::unique_ptr by alloca().
> (riscv_process_one_target_attr): Likewise.
> (riscv_process_target_attr): Likewise.
>
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/config/riscv/riscv-target-attr.cc | 9 +++--
>  1 file changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-target-attr.cc 
> b/gcc/config/riscv/riscv-target-attr.cc
> index 19eb7b06d548..e59cc53f23c6 100644
> --- a/gcc/config/riscv/riscv-target-attr.cc
> +++ b/gcc/config/riscv/riscv-target-attr.cc
> @@ -109,8 +109,7 @@ riscv_target_attr_parser::parse_arch (const char *str)
>  {
>/* Parsing the extension list like "+[,+]*".  */
>size_t len = strlen (str);
> -  std::unique_ptr buf (new char[len+1]);
> -  char *str_to_check = buf.get ();
> +  char *str_to_check = (char *) alloca (len + 1);
>strcpy (str_to_check, str);
>const char *token = strtok_r (str_to_check, ",", &str_to_check);
>m_subset_list = riscv_cmdline_subset_list ()->clone ();
> @@ -247,8 +246,7 @@ riscv_process_one_target_attr (char *arg_str,
>return false;
>  }
>
> -  std::unique_ptr buf (new char[len+1]);
> -  char *str_to_check = buf.get();
> +  char *str_to_check = (char *) alloca (len + 1);
>strcpy (str_to_check, arg_str);
>
>char *arg = strchr (str_to_check, '=');
> @@ -334,8 +332,7 @@ riscv_process_target_attr (tree fndecl, tree args, 
> location_t loc,
>return false;
>  }
>
> -  std::unique_ptr buf (new char[len+1]);
> -  char *str_to_check = buf.get ();
> +  char *str_to_check = (char *) alloca (len + 1);
>strcpy (str_to_check, TREE_STRING_POINTER (args));
>
>/* Used to catch empty spaces between commas i.e.
> --
> 2.45.2
>

Re: [PATCH 1/2] RISC-V: Add support for B standard extension

[Kito Cheng]

Forgot to say: either v2 or another patch are fine to me :)

On Tue, Jul 9, 2024 at 11:13 AM Kito Cheng  wrote:
>
> Hi Edwin:
>
> Could you add B into riscv_combine_info as well? extension should list
> there if that extension is just an alias of those extensions, so that
> GCC will add b into arch string when zba, zbb, zbs, that's necessary
> during arch string canonicalize, which could be used during multilib
> match :)
>
>
> On Tue, Jul 9, 2024 at 1:24 AM Jeff Law  wrote:
> >
> >
> >
> > On 7/8/24 11:20 AM, Edwin Lu wrote:
> > > This patch adds support for recognizing the B standard extension to be the
> > > collection of Zba, Zbb, Zbs extensions for consistency and conciseness 
> > > across
> > > toolchains
> > >
> > > * https://github.com/riscv/riscv-b/tags
> > >
> > > gcc/ChangeLog:
> > >
> > >   * common/config/riscv/riscv-common.cc: Add imply rules for B
> > > extension
> > >   * config/riscv/arch-canonicalize: Ditto
> > Both patches in this series are OK for the trunk.
> >
> > jeff
> >

Re: [PATCH 1/2] RISC-V: Add support for B standard extension

[Kito Cheng]

Hi Edwin:

Could you add B into riscv_combine_info as well? extension should list
there if that extension is just an alias of those extensions, so that
GCC will add b into arch string when zba, zbb, zbs, that's necessary
during arch string canonicalize, which could be used during multilib
match :)


On Tue, Jul 9, 2024 at 1:24 AM Jeff Law  wrote:
>
>
>
> On 7/8/24 11:20 AM, Edwin Lu wrote:
> > This patch adds support for recognizing the B standard extension to be the
> > collection of Zba, Zbb, Zbs extensions for consistency and conciseness 
> > across
> > toolchains
> >
> > * https://github.com/riscv/riscv-b/tags
> >
> > gcc/ChangeLog:
> >
> >   * common/config/riscv/riscv-common.cc: Add imply rules for B
> > extension
> >   * config/riscv/arch-canonicalize: Ditto
> Both patches in this series are OK for the trunk.
>
> jeff
>

Re: [PATCH 2/2] [RISC-V] c implies zca, and conditionally zcf & zcd

[Kito Cheng]

LGTM, thanks :)

On Tue, Jul 9, 2024 at 10:47 AM Fei Gao  wrote:

> According to Zc-1.0.4-3.pdf from
>
> https://github.com/riscvarchive/riscv-code-size-reduction/releases/tag/v1.0.4-3
> The rule is that:
> 1. C always implies Zca
> 2. C+F implies Zcf (RV32 only)
> 3. C+D implies Zcd
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc:
> c implies zca, and conditionally zcf & zcd.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/attribute-15.c: adapt TC.
> * gcc.target/riscv/attribute-18.c: likewise.
> * gcc.target/riscv/pr110696.c: likewise.
> * gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c: likewise.
> * gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c: likewise.
> * gcc.target/riscv/rvv/base/pr114352-1.c: likewise.
> * gcc.target/riscv/rvv/base/pr114352-3.c: likewise.
> * gcc.target/riscv/arch-39.c: New test.
> * gcc.target/riscv/arch-40.c: New test.
>
>
> Signed-off-by: Fei Gao 
> ---
>  gcc/common/config/riscv/riscv-common.cc  | 12 
>  gcc/testsuite/gcc.target/riscv/arch-39.c |  7 +++
>  gcc/testsuite/gcc.target/riscv/arch-40.c |  7 +++
>  gcc/testsuite/gcc.target/riscv/attribute-15.c|  2 +-
>  gcc/testsuite/gcc.target/riscv/attribute-18.c|  2 +-
>  gcc/testsuite/gcc.target/riscv/pr110696.c|  2 +-
>  .../riscv/rvv/base/abi-callee-saved-1-zcmp.c |  2 +-
>  .../riscv/rvv/base/abi-callee-saved-2-zcmp.c |  2 +-
>  gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-1.c |  4 ++--
>  gcc/testsuite/gcc.target/riscv/rvv/base/pr114352-3.c |  8 
>  10 files changed, 37 insertions(+), 11 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-39.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-40.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc
> b/gcc/common/config/riscv/riscv-common.cc
> index cad3551feb6..a02f1fe19a0 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -82,6 +82,18 @@ static const riscv_implied_info_t riscv_implied_info[] =
>{"a", "zaamo"},
>{"a", "zalrsc"},
>
> +  {"c", "zca"},
> +  {"c", "zcf",
> +   [] (const riscv_subset_list *subset_list) -> bool
> +   {
> + return subset_list->xlen () == 32 && subset_list->lookup ("f");
> +   }},
> +  {"c", "zcd",
> +   [] (const riscv_subset_list *subset_list) -> bool
> +   {
> + return subset_list->lookup ("d");
> +   }},
> +
>{"zdinx", "zfinx"},
>{"zfinx", "zicsr"},
>{"zdinx", "zicsr"},
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-39.c
> b/gcc/testsuite/gcc.target/riscv/arch-39.c
> new file mode 100644
> index 000..beeb81e44c5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-39.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64idc_zcmt -mabi=lp64d" } */
> +int
> +foo ()
> +{}
> +
> +/* { dg-error "zcd conflicts with zcmt" "" { target *-*-* } 0 } */
> diff --git a/gcc/testsuite/gcc.target/riscv/arch-40.c
> b/gcc/testsuite/gcc.target/riscv/arch-40.c
> new file mode 100644
> index 000..eaefaf1d0d7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/arch-40.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64idc_zcmp -mabi=lp64d" } */
> +int
> +foo ()
> +{}
> +
> +/* { dg-error "zcd conflicts with zcmp" "" { target *-*-* } 0 } */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-15.c
> b/gcc/testsuite/gcc.target/riscv/attribute-15.c
> index a2e394b6489..ac6caaecd4f 100644
> --- a/gcc/testsuite/gcc.target/riscv/attribute-15.c
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-15.c
> @@ -3,4 +3,4 @@
>  int foo()
>  {
>  }
> -/* { dg-final { scan-assembler ".attribute arch,
> \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
> +/* { dg-final { scan-assembler ".attribute arch,
> \"rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0\""
> } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-18.c
> b/gcc/testsuite/gcc.target/riscv/attribute-18.c
> index eefd602103d..9f7199f331a 100644
> --- a/gcc/testsuite/gcc.target/riscv/attribute-18.c
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-18.c
> @@ -1,4 +1,4 @@
>  /* { dg-do compile } */
>  /* { dg-options "-mriscv-attribute -march=rv64imafdc -mabi=lp64d
> -misa-spec=2.2" } */
>  int foo() {}
> -/* { dg-final { scan-assembler ".attribute arch,
> \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0\"" } } */
> +/* { dg-final { scan-assembler ".attribute arch,
> \"rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0\"" } }
> */
> diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c
> b/gcc/testsuite/gcc.target/riscv/pr110696.c
> index 08682a047e0..8aa6cd07f4f 100644
> --- a/gcc/testsuite/gcc.target/riscv/pr110696.c
> +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c
> @@ -4,4 +4,4 @@ int foo()
>  {
>  }
>
> -/* { dg-final { scan-assemb

Re: [PATCH v1] RISC-V: Bugfix vfmv insn honor zvfhmin for FP16 SEW [PR115763]

[Kito Cheng]

LGTM and ok for gcc 14 as well,
btw an idea is that actually could passed via gpr, I mean fpr->gpr and then
vmv.v.x, but it's not block commend for this patch.

钟居哲  於 2024年7月3日 週三 22:18 寫道：

> LGTM。
>
> --
> juzhe.zh...@rivai.ai
>
>
> *From:* pan2.li 
> *Date:* 2024-07-03 22:17
> *To:* gcc-patches 
> *CC:* juzhe.zhong ; kito.cheng
> ; jeffreyalaw ; rdapp.gcc
> ; Pan Li 
> *Subject:* [PATCH v1] RISC-V: Bugfix vfmv insn honor zvfhmin for FP16 SEW
> [PR115763]
> From: Pan Li 
>
> According to the ISA,  the zvfhmin sub extension should only contain
> convertion insn.  Thus,  the vfmv insn acts on FP16 should not be
> present when only the zvfhmin option is given.
>
> This patch would like to fix it by split the pred_broadcast define_insn
> into zvfhmin and zvfh part.  Given below example:
>
> void test (_Float16 *dest, _Float16 bias) {
>   dest[0] = bias;
>   dest[1] = bias;
> }
>
> when compile with -march=rv64gcv_zfh_zvfhmin
>
> Before this patch:
> test:
>   vsetivlizero,2,e16,mf4,ta,ma
>   vfmv.v.fv1,fa0 // should not leverage vfmv for zvfhmin
>   vse16.v v1,0(a0)
>   ret
>
> After this patch:
> test:
>   addi sp,sp,-16
>   fsh  fa0,14(sp)
>   addi a5,sp,14
>   vsetivli zero,2,e16,mf4,ta,ma
>   vlse16.v v1,0(a5),zero
>   vse16.v  v1,0(a0)
>   addi sp,sp,16
>   jr   ra
>
> PR target/115763
>
> gcc/ChangeLog:
>
> * config/riscv/vector.md (*pred_broadcast): Split into
> zvfh and zvfhmin part.
> (*pred_broadcast_zvfh): New define_insn for zvfh part.
> (*pred_broadcast_zvfhmin): Ditto but for zvfhmin.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/scalar_move-5.c: Adjust asm check.
> * gcc.target/riscv/rvv/base/scalar_move-6.c: Ditto.
> * gcc.target/riscv/rvv/base/scalar_move-7.c: Ditto.
> * gcc.target/riscv/rvv/base/scalar_move-8.c: Ditto.
> * gcc.target/riscv/rvv/base/pr115763-1.c: New test.
> * gcc.target/riscv/rvv/base/pr115763-2.c: New test.
>
> Signed-off-by: Pan Li 
> ---
> gcc/config/riscv/vector.md| 49 +--
> .../gcc.target/riscv/rvv/base/pr115763-1.c|  9 
> .../gcc.target/riscv/rvv/base/pr115763-2.c| 10 
> .../gcc.target/riscv/rvv/base/scalar_move-5.c |  4 +-
> .../gcc.target/riscv/rvv/base/scalar_move-6.c |  6 +--
> .../gcc.target/riscv/rvv/base/scalar_move-7.c |  6 +--
> .../gcc.target/riscv/rvv/base/scalar_move-8.c |  6 +--
> 7 files changed, 64 insertions(+), 26 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115763-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115763-2.c
>
> diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
> index fe18ee5b5f7..d9474262d54 100644
> --- a/gcc/config/riscv/vector.md
> +++ b/gcc/config/riscv/vector.md
> @@ -2080,31 +2080,50 @@ (define_insn_and_split "*pred_broadcast"
>[(set_attr "type" "vimov,vimov,vlds,vlds,vlds,vlds,vimovxv,vimovxv")
> (set_attr "mode" "")])
> -(define_insn "*pred_broadcast"
> -  [(set (match_operand:V_VLSF_ZVFHMIN 0 "register_operand" "=vr,
> vr, vr, vr, vr, vr, vr, vr")
> - (if_then_else:V_VLSF_ZVFHMIN
> +(define_insn "*pred_broadcast_zvfh"
> +  [(set (match_operand:V_VLSF0 "register_operand"  "=vr,
> vr,  vr,  vr")
> + (if_then_else:V_VLSF
>   (unspec:
> - [(match_operand: 1 "vector_broadcast_mask_operand" "Wc1,Wc1, vm,
> vm,Wc1,Wc1,Wb1,Wb1")
> -  (match_operand 4 "vector_length_operand"  " rK, rK, rK,
> rK, rK, rK, rK, rK")
> -  (match_operand 5 "const_int_operand"  "  i,  i,
> i,  i,  i,  i,  i,  i")
> -  (match_operand 6 "const_int_operand"  "  i,  i,
> i,  i,  i,  i,  i,  i")
> -  (match_operand 7 "const_int_operand"  "  i,  i,
> i,  i,  i,  i,  i,  i")
> + [(match_operand: 1 "vector_broadcast_mask_operand" "Wc1, Wc1,
> Wb1, Wb1")
> +  (match_operand  4 "vector_length_operand" " rK,  rK,
> rK,  rK")
> +  (match_operand  5 "const_int_operand" "  i,   i,
> i,   i")
> +  (match_operand  6 "const_int_operand" "  i,   i,
> i,   i")
> +  (match_operand  7 "const_int_operand" "  i,   i,
> i,   i")
>  (reg:SI VL_REGNUM)
>  (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> -   (vec_duplicate:V_VLSF_ZVFHMIN
> - (match_operand: 3 "direct_broadcast_operand"   " f,
> f,Wdm,Wdm,Wdm,Wdm,  f,  f"))
> -   (match_operand:V_VLSF_ZVFHMIN 2 "vector_merge_operand""vu,  0,
> vu,  0, vu,  0, vu,  0")))]
> +   (vec_duplicate:V_VLSF
> + (match_operand: 3 "direct_broadcast_operand"  "  f,   f,
> f,   f"))
> +   (match_operand:V_VLSF  2 "vector_merge_operand"  " vu,   0,
> vu,   0")))]
>"TARGET_VECTOR"
>"@
> vfmv.v.f\t%0,%3
> vfmv.v.f\t%0,%3
> +   vfmv.s.f\t%0,%3
> +   vfmv.s.f\t%0,%3"
> +  [(set_attr "type" "vfmov,vfmov,vfmovfv,vfmovfv")
> +   (set_attr "mode" "")])
> +
> +(define_insn "*pred_broadcast_zvfhmin"
> +  [(set (match_operand:V_

Re: [PATCH] RISC-V: Use tu policy for first-element vec_set [PR115725].

[Kito Cheng]

Ok for trunk and gcc 14

juzhe.zh...@rivai.ai  於 2024年7月3日 週三 17:43 寫道：

> LGTM
>
> --
> juzhe.zh...@rivai.ai
>
>
> *From:* Robin Dapp 
> *Date:* 2024-07-03 17:39
> *To:* gcc-patches 
> *CC:* rdapp.gcc ; palmer ; Kito
> Cheng ; juzhe.zh...@rivai.ai; jeffreyalaw
> ; Li, Pan2 
> *Subject:* [PATCH] RISC-V: Use tu policy for first-element vec_set
> [PR115725].
> Hi,
>
> this patch changes the tail policy for vmv.s.x from ta to tu.
> By default the bug does not show up with qemu because qemu's
> current vmv.s.x implementation always uses the tail-undisturbed
> policy.  With a local qemu version that overwrites the tail
> with ones when the tail-agnostic policy is specified, the bug
> shows.
>
> Regtested on rv64gcv_zvfh.
>
> OK for trunk and GCC 14 backport?
>
> Regards
> Robin
>
> gcc/ChangeLog:
>
> * config/riscv/autovec.md: Add TU policy.
> * config/riscv/riscv-protos.h (enum insn_type): Define
> SCALAR_MOVE_MERGED_OP_TU.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c: Adjust
> test expectation.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-2.c: Ditto.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-3.c: Ditto.
> * gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-4.c: Ditto.
> ---
> gcc/config/riscv/autovec.md  |  3 ++-
> gcc/config/riscv/riscv-protos.h  |  4 
> .../riscv/rvv/autovec/vls-vlmax/vec_set-1.c  | 12 
> .../riscv/rvv/autovec/vls-vlmax/vec_set-2.c  | 12 
> .../riscv/rvv/autovec/vls-vlmax/vec_set-3.c  | 12 
> .../riscv/rvv/autovec/vls-vlmax/vec_set-4.c  | 12 
> 6 files changed, 22 insertions(+), 33 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 1af50a46c4c..aa7dd526804 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -1341,7 +1341,8 @@ (define_expand "vec_set"
>  {
>rtx ops[] = {operands[0], operands[0], operands[1]};
>riscv_vector::emit_nonvlmax_insn (code_for_pred_broadcast
> (mode),
> - riscv_vector::SCALAR_MOVE_MERGED_OP, ops, CONST1_RTX (Pmode));
> + riscv_vector::SCALAR_MOVE_MERGED_OP_TU,
> + ops, CONST1_RTX (Pmode));
>  }
>else
>  {
> diff --git a/gcc/config/riscv/riscv-protos.h
> b/gcc/config/riscv/riscv-protos.h
> index 39b723a590b..064aa082742 100644
> --- a/gcc/config/riscv/riscv-protos.h
> +++ b/gcc/config/riscv/riscv-protos.h
> @@ -524,6 +524,10 @@ enum insn_type : unsigned int
>SCALAR_MOVE_MERGED_OP = HAS_DEST_P | HAS_MASK_P | USE_ONE_TRUE_MASK_P
>   | HAS_MERGE_P | TDEFAULT_POLICY_P | MDEFAULT_POLICY_P
>   | UNARY_OP_P,
> +
> +  SCALAR_MOVE_MERGED_OP_TU = HAS_DEST_P | HAS_MASK_P | USE_ONE_TRUE_MASK_P
> +   | HAS_MERGE_P | TU_POLICY_P | MDEFAULT_POLICY_P
> +   | UNARY_OP_P,
> };
> enum vlmul_type
> diff --git
> a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
> index ecb160933d6..99b0f625c83 100644
> --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c
> @@ -64,14 +64,10 @@ typedef double vnx2df __attribute__((vector_size
> (16)));
> TEST_ALL1 (VEC_SET)
> TEST_ALL_VAR1 (VEC_SET_VAR1)
> -/* { dg-final { scan-assembler-times
> {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m1,\s*ta,\s*ma} 1 } } */
> -/* { dg-final { scan-assembler-times
> {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m1,\s*tu,\s*ma} 5 } } */
> -/* { dg-final { scan-assembler-times
> {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m1,\s*ta,\s*ma} 2 } } */
> -/* { dg-final { scan-assembler-times
> {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m1,\s*tu,\s*ma} 6 } } */
> -/* { dg-final { scan-assembler-times
> {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m1,\s*ta,\s*ma} 2 } } */
> -/* { dg-final { scan-assembler-times
> {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m1,\s*tu,\s*ma} 6 } } */
> -/* { dg-final { scan-assembler-times
> {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m1,\s*ta,\s*ma} 2 } } */
> -/* { dg-final { scan-assembler-times
> {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m1,\s*tu,\s*ma} 4 } } */
> +/* { dg-final { scan-assembler-times
> {vset[i]*vli\s+[a-z0-9,]+,\s*e8,\s*m1,\s*tu,\s*ma} 6 } } */
> +/* { dg-final { scan-assembler-times
> {vset[i]*vli\s+[a-z0-9,]+,\s*e16,\s*m1,\s*tu,\s*ma} 8 } } */
> +/* { dg-final { scan-assembler-times
> {vset[i]*vli\s+[a-z0-9,]+,\s*e32,\s*m1,\s*tu,\s*ma} 8 } } */
> +/* { dg-final { scan-assembler-times
> {vset[i]*vli\s+[a-z0-9,]+,\s*e64,\s*m1,\s*tu,\s*ma} 6 } } */
> /* { dg-final { scan-assembler-times {\

Re: [PATCH] RISC-V: Describe -march behavior for dependent extensions

[Kito Cheng]

LGTM, BTW, based on the discussion[1], my understanding is: depend  ==
require  == imply  for the RISC-V ISA spec.
[1] https://github.com/riscv/riscv-v-spec/issues/723#issuecomment-922153867

On Wed, Jul 3, 2024 at 9:21 AM Patrick O'Neill  wrote:

> From: Palmer Dabbelt 
>
> gcc/ChangeLog:
>
> * doc/invoke.texi: Describe -march behavior for dependent
> extensions on
> RISC-V.
> ---
> Ok'd by Jeff Law here:
> https://inbox.sourceware.org/gcc-patches/fae68675-519f-4d80-b0fb-dfd5d8a22...@gmail.com/
> I'll let it sit on the lists overnight and commit in the morning tomorrow
> (PST timezone).
> ---
>  gcc/doc/invoke.texi | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index 68ebd79d676..1181ee2de14 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -31063,6 +31063,10 @@ If both @option{-march} and @option{-mcpu=} are
> not specified, the default for
>  this argument is system dependent, users who want a specific architecture
>  extensions should specify one explicitly.
>
> +When the RISC-V specifications define an extension as depending on other
> +extensions, GCC will implicitly add the dependent extensions to the
> enabled
> +extension set if they weren't added explicitly.
> +
>  @opindex mcpu
>  @item -mcpu=@var{processor-string}
>  Use architecture of and optimize the output for the given processor,
> specified
> --
> 2.43.2
>
>

Re: [PATCH] RISC-V: Fix unresolved mcpu-[67].c tests

[Kito Cheng]

LGTM, thanks :)

On Fri, Jun 21, 2024 at 7:33 PM Craig Blackmore <
craig.blackm...@embecosm.com> wrote:

> These tests check the sched2 dump, so skip them for optimization levels
> that do not enable sched2.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/mcpu-6.c: Skip for -O0, -O1, -Og.
> * gcc.target/riscv/mcpu-7.c: Likewise.
> ---
>  gcc/testsuite/gcc.target/riscv/mcpu-6.c | 1 +
>  gcc/testsuite/gcc.target/riscv/mcpu-7.c | 1 +
>  2 files changed, 2 insertions(+)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-6.c
> b/gcc/testsuite/gcc.target/riscv/mcpu-6.c
> index 96faa01653e..0126011939f 100644
> --- a/gcc/testsuite/gcc.target/riscv/mcpu-6.c
> +++ b/gcc/testsuite/gcc.target/riscv/mcpu-6.c
> @@ -1,4 +1,5 @@
>  /* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
>  /* Verify -mtune has higher priority than -mcpu for pipeline model .  */
>  /* { dg-options "-mcpu=sifive-u74 -mtune=rocket -fdump-rtl-sched2-details
> -march=rv32i -mabi=ilp32" } */
>  /* { dg-final { scan-rtl-dump "simple_return\[ \]+:alu" "sched2" } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-7.c
> b/gcc/testsuite/gcc.target/riscv/mcpu-7.c
> index 6832323e529..656436343bd 100644
> --- a/gcc/testsuite/gcc.target/riscv/mcpu-7.c
> +++ b/gcc/testsuite/gcc.target/riscv/mcpu-7.c
> @@ -1,4 +1,5 @@
>  /* { dg-do compile } */
> +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */
>  /* Verify -mtune has higher priority than -mcpu for pipeline model .  */
>  /* { dg-options "-mcpu=sifive-s21 -mtune=sifive-u74
> -fdump-rtl-sched2-details -march=rv32i -mabi=ilp32" } */
>  /* { dg-final { scan-rtl-dump "simple_return\[ \]+:sifive_7_B" "sched2" }
> } */
> --
> 2.34.1
>
>

Re: [PATCH 3/3] RISC-V: Add md files for vector BFloat16

[Kito Cheng]

LGTM

On Fri, Jun 21, 2024 at 9:56 AM Feng Wang 
wrote:

> Accroding to the BFloat16 spec, some vector iterators and new pattern
> are added in md files.
>
> All these changes passed the rvv test and rvv-intrinsic test for bfloat16.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add new insn name for vector BFloat16.
> * config/riscv/vector-iterators.md: Add some iterators for vector
> BFloat16.
> * config/riscv/vector.md: Add some attribute for vector BFloat16.
> * config/riscv/vector-bfloat16.md: New file. Add insn pattern
> vector BFloat16.
>
> ---
>  gcc/config/riscv/riscv.md|  13 ++-
>  gcc/config/riscv/vector-bfloat16.md  | 135 +
>  gcc/config/riscv/vector-iterators.md | 169 ++-
>  gcc/config/riscv/vector.md   | 103 ++--
>  4 files changed, 405 insertions(+), 15 deletions(-)
>  create mode 100644 gcc/config/riscv/vector-bfloat16.md
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 7a9454de430..31dcd5f2507 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -200,6 +200,7 @@
>RVVMF64BI,RVVMF32BI,RVVMF16BI,RVVMF8BI,RVVMF4BI,RVVMF2BI,RVVM1BI,
>RVVM8QI,RVVM4QI,RVVM2QI,RVVM1QI,RVVMF2QI,RVVMF4QI,RVVMF8QI,
>RVVM8HI,RVVM4HI,RVVM2HI,RVVM1HI,RVVMF2HI,RVVMF4HI,
> +  RVVM8BF,RVVM4BF,RVVM2BF,RVVM1BF,RVVMF2BF,RVVMF4BF,
>RVVM8HF,RVVM4HF,RVVM2HF,RVVM1HF,RVVMF2HF,RVVMF4HF,
>RVVM8SI,RVVM4SI,RVVM2SI,RVVM1SI,RVVMF2SI,
>RVVM8SF,RVVM4SF,RVVM2SF,RVVM1SF,RVVMF2SF,
> @@ -219,6 +220,11 @@
>RVVM2x4HI,RVVM1x4HI,RVVMF2x4HI,RVVMF4x4HI,
>RVVM2x3HI,RVVM1x3HI,RVVMF2x3HI,RVVMF4x3HI,
>RVVM4x2HI,RVVM2x2HI,RVVM1x2HI,RVVMF2x2HI,RVVMF4x2HI,
> +  RVVM1x8BF,RVVMF2x8BF,RVVMF4x8BF,RVVM1x7BF,RVVMF2x7BF,
> +  RVVMF4x7BF,RVVM1x6BF,RVVMF2x6BF,RVVMF4x6BF,RVVM1x5BF,
> +  RVVMF2x5BF,RVVMF4x5BF,RVVM2x4BF,RVVM1x4BF,RVVMF2x4BF,
> +  RVVMF4x4BF,RVVM2x3BF,RVVM1x3BF,RVVMF2x3BF,RVVMF4x3BF,
> +  RVVM4x2BF,RVVM2x2BF,RVVM1x2BF,RVVMF2x2BF,RVVMF4x2BF,
>RVVM1x8HF,RVVMF2x8HF,RVVMF4x8HF,RVVM1x7HF,RVVMF2x7HF,
>RVVMF4x7HF,RVVM1x6HF,RVVMF2x6HF,RVVMF4x6HF,RVVM1x5HF,
>RVVMF2x5HF,RVVMF4x5HF,RVVM2x4HF,RVVM1x4HF,RVVMF2x4HF,
> @@ -462,6 +468,10 @@
>  ;; vsm4rcrypto vector SM4 Rounds instructions
>  ;; vsm3me   crypto vector SM3 Message Expansion instructions
>  ;; vsm3ccrypto vector SM3 Compression instructions
> +;; 18.Vector BF16 instrctions
> +;; vfncvtbf16  vector narrowing single floating-point to brain
> floating-point instruction
> +;; vfwcvtbf16  vector widening brain floating-point to single
> floating-point instruction
> +;; vfwmaccbf16  vector BF16 widening multiply-accumulate
>  (define_attr "type"
>"unknown,branch,jump,jalr,ret,call,load,fpload,store,fpstore,
> mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
> @@ -483,7 +493,7 @@
> vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,
>
> vgather,vcompress,vmov,vector,vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll,
>
> vclmul,vclmulh,vghsh,vgmul,vaesef,vaesem,vaesdf,vaesdm,vaeskf1,vaeskf2,vaesz,
> -   vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c"
> +
>  
> vsha2ms,vsha2ch,vsha2cl,vsm4k,vsm4r,vsm3me,vsm3c,vfncvtbf16,vfwcvtbf16,vfwmaccbf16"
>(cond [(eq_attr "got" "load") (const_string "load")
>
>  ;; If a doubleword move uses these expensive instructions,
> @@ -4311,6 +4321,7 @@
>  (include "generic-ooo.md")
>  (include "vector.md")
>  (include "vector-crypto.md")
> +(include "vector-bfloat16.md")
>  (include "zicond.md")
>  (include "sfb.md")
>  (include "zc.md")
> diff --git a/gcc/config/riscv/vector-bfloat16.md
> b/gcc/config/riscv/vector-bfloat16.md
> new file mode 100644
> index 000..562aa8ee5ed
> --- /dev/null
> +++ b/gcc/config/riscv/vector-bfloat16.md
> @@ -0,0 +1,135 @@
> +;; Machine description for RISC-V bfloat16 extensions.
> +;; Copyright (C) 2024 Free Software Foundation, Inc.
> +
> +;; This file is part of GCC.
> +
> +;; GCC is free software; you can redistribute it and/or modify
> +;; it under the terms of the GNU General Public License as published by
> +;; the Free Software Foundation; either version 3, or (at your option)
> +;; any later version.
> +
> +;; GCC is distributed in the hope that it will be useful,
> +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
> +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +;; GNU General Public License for more details.
> +
> +;; You should have received a copy of the GNU General Public License
> +;; along with GCC; see the file COPYING3.  If not see
> +;; .
> +
> +(define_mode_iterator VWEXTF_ZVFBF [
> +  (RVVM8SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")
> +  (RVVM4SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")
> +  (RVVM2SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")
> +  (RVVM1SF  "TARGET_VECTOR_ELEN_BF_16 && TARGET_VECTOR_ELEN_FP_32")

Re: [PATCH 1/3] RISC-V: Add vector type of BFloat16 format

[Kito Cheng]

LGTM

juzhe.zh...@rivai.ai  於 2024年6月21日 週五 12:25 寫道：

> LGTM
>
> --
> juzhe.zh...@rivai.ai
>
>
> *From:* Feng Wang 
> *Date:* 2024-06-21 09:54
> *To:* gcc-patches 
> *CC:* kito.cheng ; juzhe.zhong
> ; jinma.contrib ; Feng Wang
> 
> *Subject:* [PATCH 1/3] RISC-V: Add vector type of BFloat16 format
> The vector type of BFloat16 format is added in this patch,
> subsequent extensions to zvfbfmin and zvfwma need to be based
> on this patch.
>
> gcc/ChangeLog:
>
> * config/riscv/genrvv-type-indexer.cc (bfloat16_type):
> Generate bf16 vector_type and scalar_type in DEF_RVV_TYPE_INDEX.
> (bfloat16_wide_type): Ditto.
> (same_ratio_eew_bf16_type): Ditto.
> (main): Ditto.
> * config/riscv/riscv-modes.def (ADJUST_BYTESIZE):
> (RVV_WHOLE_MODES): Add vector type for BFloat16.
> (RVV_FRACT_MODE): Ditto.
> (RVV_NF4_MODES): Ditto.
> (RVV_NF8_MODES): Ditto.
> (RVV_NF2_MODES): Ditto.
> * config/riscv/riscv-vector-builtins-types.def (vbfloat16mf4_t):
> (vbfloat16mf2_t): Add builtin vector type for BFloat16.
> (vbfloat16m1_t): Ditto.
> (vbfloat16m2_t): Ditto.
> (vbfloat16m4_t): Ditto.
> (vbfloat16m8_t): Ditto.
> (vbfloat16mf4x2_t): Ditto.
> (vbfloat16mf4x3_t): Ditto.
> (vbfloat16mf4x4_t): Ditto.
> (vbfloat16mf4x5_t): Ditto.
> (vbfloat16mf4x6_t): Ditto.
> (vbfloat16mf4x7_t): Ditto.
> (vbfloat16mf4x8_t): Ditto.
> (vbfloat16mf2x2_t): Ditto.
> (vbfloat16mf2x3_t): Ditto.
> (vbfloat16mf2x4_t): Ditto.
> (vbfloat16mf2x5_t): Ditto.
> (vbfloat16mf2x6_t): Ditto.
> (vbfloat16mf2x7_t): Ditto.
> (vbfloat16mf2x8_t): Ditto.
> (vbfloat16m1x2_t): Ditto.
> (vbfloat16m1x3_t): Ditto.
> (vbfloat16m1x4_t): Ditto.
> (vbfloat16m1x5_t): Ditto.
> (vbfloat16m1x6_t): Ditto.
> (vbfloat16m1x7_t): Ditto.
> (vbfloat16m1x8_t): Ditto.
> (vbfloat16m2x2_t): Ditto.
> (vbfloat16m2x3_t): Ditto.
> (vbfloat16m2x4_t): Ditto.
> (vbfloat16m4x2_t): Ditto.
> * config/riscv/riscv-vector-builtins.cc (check_required_extensions):
> Add required_ext checking for BFloat16.
> * config/riscv/riscv-vector-builtins.def (vbfloat16mf4_t):
> Add vector_type for BFloat16 in builtins.def.
> (vbfloat16mf4x2_t): Ditto.
> (vbfloat16mf4x3_t): Ditto.
> (vbfloat16mf4x4_t): Ditto.
> (vbfloat16mf4x5_t): Ditto.
> (vbfloat16mf4x6_t): Ditto.
> (vbfloat16mf4x7_t): Ditto.
> (vbfloat16mf4x8_t): Ditto.
> (vbfloat16mf2_t): Ditto.
> (vbfloat16mf2x2_t): Ditto.
> (vbfloat16mf2x3_t): Ditto.
> (vbfloat16mf2x4_t): Ditto.
> (vbfloat16mf2x5_t): Ditto.
> (vbfloat16mf2x6_t): Ditto.
> (vbfloat16mf2x7_t): Ditto.
> (vbfloat16mf2x8_t): Ditto.
> (vbfloat16m1_t): Ditto.
> (vbfloat16m1x2_t): Ditto.
> (vbfloat16m1x3_t): Ditto.
> (vbfloat16m1x4_t): Ditto.
> (vbfloat16m1x5_t): Ditto.
> (vbfloat16m1x6_t): Ditto.
> (vbfloat16m1x7_t): Ditto.
> (vbfloat16m1x8_t): Ditto.
> (vbfloat16m2_t): Ditto.
> (vbfloat16m2x2_t): Ditto.
> (vbfloat16m2x3_t): Ditto.
> (vbfloat16m2x4_t): Ditto.
> (vbfloat16m4_t): Ditto.
> (vbfloat16m4x2_t): Ditto.
> (vbfloat16m8_t): Ditto.
> (double_trunc_bfloat_scalar): Add scalar_type def for BFloat16.
> (double_trunc_bfloat_vector): Add vector_type def for BFloat16.
> * config/riscv/riscv-vector-builtins.h (RVV_REQUIRE_ELEN_BF_16):
> Add required defination of BFloat16 ext.
> * config/riscv/riscv-vector-switch.def (ENTRY):
> Add vector_type information for BFloat16.
> (TUPLE_ENTRY): Add tuple vector_type information for BFloat16.
>
> ---
> gcc/config/riscv/genrvv-type-indexer.cc   | 113 ++
> gcc/config/riscv/riscv-modes.def  |  30 -
> .../riscv/riscv-vector-builtins-types.def |  50 
> gcc/config/riscv/riscv-vector-builtins.cc |   7 +-
> gcc/config/riscv/riscv-vector-builtins.def|  55 -
> gcc/config/riscv/riscv-vector-builtins.h  |   1 +
> gcc/config/riscv/riscv-vector-switch.def  |  36 ++
> 7 files changed, 289 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/genrvv-type-indexer.cc
> b/gcc/config/riscv/genrvv-type-indexer.cc
> index 27cbd14982c..31300d55e1d 100644
> --- a/gcc/config/riscv/genrvv-type-indexer.cc
> +++ b/gcc/config/riscv/genrvv-type-indexer.cc
> @@ -117,6 +117,42 @@ inttype (unsigned sew, int lmul_log2, unsigned nf,
> bool unsigned_p)
>return mode.str ();
> }
> +std::string
> +bfloat16_type (int lmul_log2)
> +{
> +  if (!valid_type (16, lmul_log2, /*float_t*/ true))
> +return "INVALID";
> +
> +  std::stringstream mode;
> +  mode << "vbfloat16" << to_lmul (lmul_log2) << "_t";
> +  return mode.str ();
> +}
> +
> +std::string
> +bfloat16_wide_type (int lmul_log2)
> +{
> +  if (!valid_type (32, lmul_log2, /*float_t*/ true))
> +return "INVALID";
> +
> +  std::stringstream mode;
> +  mode << "vfloat32" << to_lmul (lmul_log2) << "_t";
> +  return mode.str ();
> +}
> +
> +std::string
> +bfloat16_type (int lmul_log2, unsigned nf)
> +{
> +  if (!valid_type (16, lmul_log2, nf, /*float_t*/ true))
> +return "INVALID";
> +
> +  std::stringstream mode;
> +  mode << "vbfloat16" << to_lmul (lmul_log2);
> +  if (nf > 1)
> +mode << "x" << nf;
> +  mode <

Re: [PATCH v4] RISC-V: Promote Zaamo/Zalrsc to a when using an old binutils

[Kito Cheng]

LGTM :)

Patrick O'Neill  於 2024年6月19日 週三 05:40 寫道：

> Binutils 2.42 and before don't support Zaamo/Zalrsc. When users specify
> both Zaamo and Zalrsc, promote them to 'a' in the -march string.
>
> This does not affect testsuite results for users with old versions of
> binutils.
> Testcases that failed due to 'call'/isa string continue to fail after this
> PATCH
> when using an old version of binutils.
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc: Add 'a' extension to
> riscv_combine_info.
>
> Signed-off-by: Patrick O'Neill 
> ---
> We will emit calls if the user only specifies Zaamo or Zalrsc.
> To my knowledge there isn't a way to make a testcase for this in dejagnu.
> I used the most recent version of the 'a' extension arbitrarily since
> AFAICT the
> version of the extension doesn't affect the combine logic.
> ---
>  gcc/common/config/riscv/riscv-common.cc | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc
> b/gcc/common/config/riscv/riscv-common.cc
> index 1dc1d9904c7..410e673f5e0 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -401,6 +401,7 @@ static const struct riscv_ext_version
> riscv_ext_version_table[] =
>  /* Combine extensions defined in this table  */
>  static const struct riscv_ext_version riscv_combine_info[] =
>  {
> +  {"a", ISA_SPEC_CLASS_20191213, 2, 1},
>{"zk",  ISA_SPEC_CLASS_NONE, 1, 0},
>{"zkn",  ISA_SPEC_CLASS_NONE, 1, 0},
>{"zks",  ISA_SPEC_CLASS_NONE, 1, 0},
> --
> 2.34.1
>
>

Re: [RFC v3] RISC-V: Promote Zaamo/Zalrsc to a when using an old binutils

[Kito Cheng]

When 'a' is put into riscv_combine_info, 'a' will only be added into
arch string only if zaamo *AND* zalrsc is there, so zalrsc only won't
trigger that.

On Tue, Jun 18, 2024 at 1:35 PM Patrick O'Neill  wrote:
>
>
>
> On Mon, Jun 17, 2024 at 5:51 PM Kito Cheng  wrote:
>>
>> Maybe just add 'a' to riscv_combine_info and other logic to keep the
>> same (e.g. keep the logic for skip_zaamo_zalrsc)?
>
>
> I did consider unconditionally upgrading zaamo/zalrsc to ‘a’ (I think that’s 
> what you’re suggesting w/ riscv_combine_info).
> That could cause issues if users are trying to compile for a zalrsc-only chip 
> with an old version of binutils. If we upgrade zalrsc -> ‘a’ for both cc1 and 
> binutils then cc1 will emit amo ops instead of their lr/sc equivalent.
> GCC would end up emitting insns that are illegal for the user-provided -march 
> string.
>
> Patrick
>
>>
>> On Tue, Jun 18, 2024 at 8:03 AM Patrick O'Neill  wrote:
>> >
>> > Binutils 2.42 and before don't support Zaamo/Zalrsc. Promote Zaamo/Zalrsc 
>> > to
>> > 'a' in the -march string when assembling.
>> >
>> > This change respects Zaamo/Zalrsc when generating code.
>> >
>> > Testcases that check for the default isa string will fail with the old 
>> > binutils
>> > since zaamo/zalrsc aren't emitted anymore. All other Zaamo/Zalrsc testcases
>> > pass.
>> >
>> > gcc/ChangeLog:
>> >
>> > * common/config/riscv/riscv-common.cc
>> > (riscv_subset_list::to_string): Add toggle to promote Zaamo/Zalrsc
>> > extensions to 'a'.
>> > (riscv_arch_str): Ditto.
>> > (riscv_expand_arch): Ditto.
>> > (riscv_expand_arch_from_cpu): Ditto.
>> > (riscv_expand_arch_upgrade_exts): New function. Wrapper around
>> > riscv_expand_arch to preserve the function signature.
>> > (riscv_expand_arch_no_upgrade_exts): Ditto
>> > (riscv_expand_arch_from_cpu_upgrade_exts): New function. Wrapper 
>> > around
>> > riscv_expand_arch_from_cpu to preserve the function signature.
>> > (riscv_expand_arch_from_cpu_no_upgrade_exts): Ditto.
>> > * config/riscv/riscv-protos.h (riscv_arch_str): Add toggle to 
>> > function
>> > prototype.
>> > * config/riscv/riscv-subset.h: Ditto.
>> > * config/riscv/riscv-target-attr.cc (riscv_process_target_attr):
>> > * config/riscv/riscv.cc (riscv_emit_attribute):
>> > (riscv_declare_function_name):
>> > * config/riscv/riscv.h (riscv_expand_arch): Remove.
>> > (riscv_expand_arch_from_cpu): Ditto.
>> > (riscv_expand_arch_upgrade_exts): Add toggle wrapper functions.
>> > (riscv_expand_arch_no_upgrade_exts): Ditto.
>> > (riscv_expand_arch_from_cpu_upgrade_exts): Ditto.
>> > (riscv_expand_arch_from_cpu_no_upgrade_exts): Ditto.
>> > (EXTRA_SPEC_FUNCTIONS): Ditto.
>> > (OPTION_DEFAULT_SPECS): Use non-upgraded march string when 
>> > invoking the
>> > compiler.
>> > (ASM_SPEC): Use upgraded march string when invoking the assembler.
>> >
>> > Signed-off-by: Patrick O'Neill 
>> > ---
>> > v3 ChangeLog:
>> > Rebased on non-promoting patch.
>> > Wrap all Zaamo/Zalrsc upgrade code in #ifndef to prevent compiler
>> > warnings about unused/potentially undefined variables.
>> > Silence unused parameter warning with a voidcast.
>> > ---
>> > RFC since I'm not sure if this upgrade behavior is more trouble than
>> > it's worth - this is a pretty invasive change. Happy to iterate further
>> > or just drop these changes.
>> > ---
>> >  gcc/common/config/riscv/riscv-common.cc | 111 +---
>> >  gcc/config/riscv/riscv-protos.h |   3 +-
>> >  gcc/config/riscv/riscv-subset.h |   2 +-
>> >  gcc/config/riscv/riscv-target-attr.cc   |   4 +-
>> >  gcc/config/riscv/riscv.cc   |   7 +-
>> >  gcc/config/riscv/riscv.h|  46 ++
>> >  6 files changed, 137 insertions(+), 36 deletions(-)
>> >
>> > diff --git a/gcc/common/config/riscv/riscv-common.cc 
>> > b/gcc/common/config/riscv/riscv-common.cc
>> > index 1dc1d9904c7..05c26f73b73 100644
>> > --- a/gcc/common/config/riscv/riscv-common.cc
>> > +++ b/gcc/common/c

Re: [RFC v3] RISC-V: Promote Zaamo/Zalrsc to a when using an old binutils

[Kito Cheng]

Maybe just add 'a' to riscv_combine_info and other logic to keep the
same (e.g. keep the logic for skip_zaamo_zalrsc)?

On Tue, Jun 18, 2024 at 8:03 AM Patrick O'Neill  wrote:
>
> Binutils 2.42 and before don't support Zaamo/Zalrsc. Promote Zaamo/Zalrsc to
> 'a' in the -march string when assembling.
>
> This change respects Zaamo/Zalrsc when generating code.
>
> Testcases that check for the default isa string will fail with the old 
> binutils
> since zaamo/zalrsc aren't emitted anymore. All other Zaamo/Zalrsc testcases
> pass.
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc
> (riscv_subset_list::to_string): Add toggle to promote Zaamo/Zalrsc
> extensions to 'a'.
> (riscv_arch_str): Ditto.
> (riscv_expand_arch): Ditto.
> (riscv_expand_arch_from_cpu): Ditto.
> (riscv_expand_arch_upgrade_exts): New function. Wrapper around
> riscv_expand_arch to preserve the function signature.
> (riscv_expand_arch_no_upgrade_exts): Ditto
> (riscv_expand_arch_from_cpu_upgrade_exts): New function. Wrapper 
> around
> riscv_expand_arch_from_cpu to preserve the function signature.
> (riscv_expand_arch_from_cpu_no_upgrade_exts): Ditto.
> * config/riscv/riscv-protos.h (riscv_arch_str): Add toggle to function
> prototype.
> * config/riscv/riscv-subset.h: Ditto.
> * config/riscv/riscv-target-attr.cc (riscv_process_target_attr):
> * config/riscv/riscv.cc (riscv_emit_attribute):
> (riscv_declare_function_name):
> * config/riscv/riscv.h (riscv_expand_arch): Remove.
> (riscv_expand_arch_from_cpu): Ditto.
> (riscv_expand_arch_upgrade_exts): Add toggle wrapper functions.
> (riscv_expand_arch_no_upgrade_exts): Ditto.
> (riscv_expand_arch_from_cpu_upgrade_exts): Ditto.
> (riscv_expand_arch_from_cpu_no_upgrade_exts): Ditto.
> (EXTRA_SPEC_FUNCTIONS): Ditto.
> (OPTION_DEFAULT_SPECS): Use non-upgraded march string when invoking 
> the
> compiler.
> (ASM_SPEC): Use upgraded march string when invoking the assembler.
>
> Signed-off-by: Patrick O'Neill 
> ---
> v3 ChangeLog:
> Rebased on non-promoting patch.
> Wrap all Zaamo/Zalrsc upgrade code in #ifndef to prevent compiler
> warnings about unused/potentially undefined variables.
> Silence unused parameter warning with a voidcast.
> ---
> RFC since I'm not sure if this upgrade behavior is more trouble than
> it's worth - this is a pretty invasive change. Happy to iterate further
> or just drop these changes.
> ---
>  gcc/common/config/riscv/riscv-common.cc | 111 +---
>  gcc/config/riscv/riscv-protos.h |   3 +-
>  gcc/config/riscv/riscv-subset.h |   2 +-
>  gcc/config/riscv/riscv-target-attr.cc   |   4 +-
>  gcc/config/riscv/riscv.cc   |   7 +-
>  gcc/config/riscv/riscv.h|  46 ++
>  6 files changed, 137 insertions(+), 36 deletions(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 1dc1d9904c7..05c26f73b73 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -907,7 +907,7 @@ riscv_subset_list::add (const char *subset, bool 
> implied_p)
> VERSION_P to determine append version info or not.  */
>
>  std::string
> -riscv_subset_list::to_string (bool version_p) const
> +riscv_subset_list::to_string (bool version_p, bool upgrade_exts) const
>  {
>std::ostringstream oss;
>oss << "rv" << m_xlen;
> @@ -916,10 +916,17 @@ riscv_subset_list::to_string (bool version_p) const
>riscv_subset_t *subset;
>
>bool skip_zifencei = false;
> -  bool skip_zaamo_zalrsc = false;
>bool skip_zicsr = false;
>bool i2p0 = false;
>
> +#ifndef HAVE_AS_MARCH_ZAAMO_ZALRSC
> +  bool upgrade_zaamo_zalrsc = false;
> +  bool has_a_ext = false;
> +  bool insert_a_ext = false;
> +  bool inserted_a_ext = false;
> +  riscv_subset_t *a_subset;
> +#endif
> +
>/* For RISC-V ISA version 2.2 or earlier version, zicsr and zifencei is
>   included in the base ISA.  */
>if (riscv_isa_spec == ISA_SPEC_CLASS_2P2)
> @@ -945,8 +952,33 @@ riscv_subset_list::to_string (bool version_p) const
>skip_zifencei = true;
>  #endif
>  #ifndef HAVE_AS_MARCH_ZAAMO_ZALRSC
> -  /* Skip since binutils 2.42 and earlier don't recognize zaamo/zalrsc.  */
> -  skip_zaamo_zalrsc = true;
> +  /* Upgrade Zaamo/Zalrsc extensions to 'a' since binutils 2.42 and earlier
> + don't recognize zaamo/zalrsc.  */
> +  upgrade_zaamo_zalrsc = upgrade_exts;
> +  if (upgrade_zaamo_zalrsc)
> +{
> +  for (subset = m_head; subset != NULL; subset = subset->next)
> +   {
> + if (subset->name == "a")
> +   has_a_ext = true;
> + if (subset->name == "zaamo" || subset->name == "zalrsc")
> +   insert_a_ext = true;
> +   }
> +  if (insert_a_ext && !has_a_ext)
> +   {
> +

Re: [PATCH] riscv: Allocate enough space to strcpy() string

[Kito Cheng]

Ok for gcc 14 too :)

Christoph Müllner  於 2024年6月15日 週六 15:14 寫道：

>
>
> On Sat, Jun 15, 2024, 08:25 Kito Cheng  wrote:
>
>> Oooops, thanks for catching that! It's LGTM:)
>>
>
> Also OK for the GCC 14 branch?
>
>
>> Christoph Müllner  於 2024年6月15日 週六 04:58 寫道：
>>
>>> I triggered an ICE on Ubuntu 24.04 when compiling code that uses
>>> function attributes. Looking into the sources shows that we have
>>> a systematic issue in the attribute handling code:
>>> * we determine the length with strlen() (excluding the terminating null)
>>> * we allocate a buffer with this length
>>> * we copy the original string using strcpy() (incl. the terminating null)
>>>
>>> To quote the man page of strcpy():
>>> "The programmer is responsible for allocating a  destination  buffer
>>> large  enough,  that  is, strlen(src)  + 1."
>>>
>>> The ICE looks like this:
>>>
>>> *** buffer overflow detected ***: terminated
>>> xtheadmempair_bench.c:14:1: internal compiler error: Aborted
>>>14 | {
>>>   | ^
>>> 0xaf3b99 crash_signal
>>> /home/ubuntu/src/gcc/scaleff/gcc/toplev.cc:319
>>> 0xe5b957 strcpy
>>> /usr/include/riscv64-linux-gnu/bits/string_fortified.h:79
>>> 0xe5b957 riscv_process_target_attr
>>>
>>> /home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:339
>>> 0xe5baaf riscv_process_target_attr
>>>
>>> /home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:314
>>> 0xe5bc5f riscv_option_valid_attribute_p(tree_node*, tree_node*,
>>> tree_node*, int)
>>>
>>> /home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:389
>>> 0x6a31e5 handle_target_attribute
>>> /home/ubuntu/src/gcc/scaleff/gcc/c-family/c-attribs.cc:5915
>>> 0x5d3a07 decl_attributes(tree_node**, tree_node*, int, tree_node*)
>>> /home/ubuntu/src/gcc/scaleff/gcc/attribs.cc:900
>>> 0x5db403 c_decl_attributes
>>> /home/ubuntu/src/gcc/scaleff/gcc/c/c-decl.cc:5501
>>> 0x5e8965 start_function(c_declspecs*, c_declarator*, tree_node*)
>>> /home/ubuntu/src/gcc/scaleff/gcc/c/c-decl.cc:10562
>>> 0x6318ed c_parser_declaration_or_fndef
>>> /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:2914
>>> 0x63a8ad c_parser_external_declaration
>>> /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:2048
>>> 0x63b219 c_parser_translation_unit
>>> /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:1902
>>> 0x63b219 c_parse_file()
>>> /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:27277
>>> 0x68fec5 c_common_parse_file()
>>> /home/ubuntu/src/gcc/scaleff/gcc/c-family/c-opts.cc:1311
>>> Please submit a full bug report, with preprocessed source (by using
>>> -freport-bug).
>>> Please include the complete backtrace with any bug report.
>>> See <https://gcc.gnu.org/bugs/> for instructions.
>>>
>>> gcc/ChangeLog:
>>>
>>> * config/riscv/riscv-target-attr.cc
>>> (riscv_target_attr_parser::parse_arch):
>>> Fix allocation size of buffer.
>>> (riscv_process_one_target_attr): Likewise.
>>> (riscv_process_target_attr): Likewise.
>>>
>>> Signed-off-by: Christoph Müllner 
>>> ---
>>>  gcc/config/riscv/riscv-target-attr.cc | 6 +++---
>>>  1 file changed, 3 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/gcc/config/riscv/riscv-target-attr.cc
>>> b/gcc/config/riscv/riscv-target-attr.cc
>>> index 1a73d69bf50..19eb7b06d54 100644
>>> --- a/gcc/config/riscv/riscv-target-attr.cc
>>> +++ b/gcc/config/riscv/riscv-target-attr.cc
>>> @@ -109,7 +109,7 @@ riscv_target_attr_parser::parse_arch (const char
>>> *str)
>>>  {
>>>/* Parsing the extension list like "+[,+]*".  */
>>>size_t len = strlen (str);
>>> -  std::unique_ptr buf (new char[len]);
>>> +  std::unique_ptr buf (new char[len+1]);
>>>char *str_to_check = buf.get ();
>>>strcpy (str_to_check, str);
>>>const char *token = strtok_r (str_to_check, ",", &str_to_check);
>>> @@ -247,7 +247,7 @@ riscv_process_one_target_attr (char *arg_str,
>>>return false;
>>>  }
>>>
>>> -  std::unique_ptr buf (new char[len]);
>>> +  std::unique_ptr buf (new char[len+1]);
>>>char *str_to_check = buf.get();
>>>strcpy (str_to_check, arg_str);
>>>
>>> @@ -334,7 +334,7 @@ riscv_process_target_attr (tree fndecl, tree args,
>>> location_t loc,
>>>return false;
>>>  }
>>>
>>> -  std::unique_ptr buf (new char[len]);
>>> +  std::unique_ptr buf (new char[len+1]);
>>>char *str_to_check = buf.get ();
>>>strcpy (str_to_check, TREE_STRING_POINTER (args));
>>>
>>> --
>>> 2.45.1
>>>
>>>

Re: [PATCH] riscv: Allocate enough space to strcpy() string

[Kito Cheng]

Oooops, thanks for catching that! It's LGTM:)

Christoph Müllner  於 2024年6月15日 週六 04:58 寫道：

> I triggered an ICE on Ubuntu 24.04 when compiling code that uses
> function attributes. Looking into the sources shows that we have
> a systematic issue in the attribute handling code:
> * we determine the length with strlen() (excluding the terminating null)
> * we allocate a buffer with this length
> * we copy the original string using strcpy() (incl. the terminating null)
>
> To quote the man page of strcpy():
> "The programmer is responsible for allocating a  destination  buffer
> large  enough,  that  is, strlen(src)  + 1."
>
> The ICE looks like this:
>
> *** buffer overflow detected ***: terminated
> xtheadmempair_bench.c:14:1: internal compiler error: Aborted
>14 | {
>   | ^
> 0xaf3b99 crash_signal
> /home/ubuntu/src/gcc/scaleff/gcc/toplev.cc:319
> 0xe5b957 strcpy
> /usr/include/riscv64-linux-gnu/bits/string_fortified.h:79
> 0xe5b957 riscv_process_target_attr
>
> /home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:339
> 0xe5baaf riscv_process_target_attr
>
> /home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:314
> 0xe5bc5f riscv_option_valid_attribute_p(tree_node*, tree_node*,
> tree_node*, int)
>
> /home/ubuntu/src/gcc/scaleff/gcc/config/riscv/riscv-target-attr.cc:389
> 0x6a31e5 handle_target_attribute
> /home/ubuntu/src/gcc/scaleff/gcc/c-family/c-attribs.cc:5915
> 0x5d3a07 decl_attributes(tree_node**, tree_node*, int, tree_node*)
> /home/ubuntu/src/gcc/scaleff/gcc/attribs.cc:900
> 0x5db403 c_decl_attributes
> /home/ubuntu/src/gcc/scaleff/gcc/c/c-decl.cc:5501
> 0x5e8965 start_function(c_declspecs*, c_declarator*, tree_node*)
> /home/ubuntu/src/gcc/scaleff/gcc/c/c-decl.cc:10562
> 0x6318ed c_parser_declaration_or_fndef
> /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:2914
> 0x63a8ad c_parser_external_declaration
> /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:2048
> 0x63b219 c_parser_translation_unit
> /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:1902
> 0x63b219 c_parse_file()
> /home/ubuntu/src/gcc/scaleff/gcc/c/c-parser.cc:27277
> 0x68fec5 c_common_parse_file()
> /home/ubuntu/src/gcc/scaleff/gcc/c-family/c-opts.cc:1311
> Please submit a full bug report, with preprocessed source (by using
> -freport-bug).
> Please include the complete backtrace with any bug report.
> See  for instructions.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-target-attr.cc
> (riscv_target_attr_parser::parse_arch):
> Fix allocation size of buffer.
> (riscv_process_one_target_attr): Likewise.
> (riscv_process_target_attr): Likewise.
>
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/config/riscv/riscv-target-attr.cc | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-target-attr.cc
> b/gcc/config/riscv/riscv-target-attr.cc
> index 1a73d69bf50..19eb7b06d54 100644
> --- a/gcc/config/riscv/riscv-target-attr.cc
> +++ b/gcc/config/riscv/riscv-target-attr.cc
> @@ -109,7 +109,7 @@ riscv_target_attr_parser::parse_arch (const char *str)
>  {
>/* Parsing the extension list like "+[,+]*".  */
>size_t len = strlen (str);
> -  std::unique_ptr buf (new char[len]);
> +  std::unique_ptr buf (new char[len+1]);
>char *str_to_check = buf.get ();
>strcpy (str_to_check, str);
>const char *token = strtok_r (str_to_check, ",", &str_to_check);
> @@ -247,7 +247,7 @@ riscv_process_one_target_attr (char *arg_str,
>return false;
>  }
>
> -  std::unique_ptr buf (new char[len]);
> +  std::unique_ptr buf (new char[len+1]);
>char *str_to_check = buf.get();
>strcpy (str_to_check, arg_str);
>
> @@ -334,7 +334,7 @@ riscv_process_target_attr (tree fndecl, tree args,
> location_t loc,
>return false;
>  }
>
> -  std::unique_ptr buf (new char[len]);
> +  std::unique_ptr buf (new char[len+1]);
>char *str_to_check = buf.get ();
>strcpy (str_to_check, TREE_STRING_POINTER (args));
>
> --
> 2.45.1
>
>

Re: [PATCH v1] RISC-V: Bugfix vec_extract v mode iterator restriction mismatch

[Kito Cheng]

LGTM, thanks :)

On Fri, Jun 14, 2024 at 3:02 PM  wrote:
>
> From: Pan Li 
>
> We have vec_extract pattern which takes ZVFHMIN as the mode
> iterator of the V mode.  Aka VF_ZVFHMIN iterator.  But it will
> expand to pred_extract_first pattern which takes the ZVFH as the mode
> iterator of the V mode.  AKa VF.  The mismatch will result in one ICE
> similar as below:
>
> insn 30 29 31 2 (set (reg:HF 156 [ _2 ])
> (unspec:HF [
> (vec_select:HF (reg:RVVMF2HF 134 [ _1 ])
> (parallel [
> (const_int 0 [0])
> ]))
> (reg:SI 67 vtype)
> ] UNSPEC_VPREDICATE)) "compress_run-2.c":22:3 -1
>  (nil))
> during RTL pass: vregs
> compress_run-2.c:25:1: internal compiler error: in extract_insn, at
> recog.cc:2812
> 0xb3bc47 _fatal_insn(char const*, rtx_def const*, char const*, int, char
> const*)
> ../../../gcc/gcc/rtl-error.cc:108
> 0xb3bc69 _fatal_insn_not_found(rtx_def const*, char const*, int, char
> const*)
> ../../../gcc/gcc/rtl-error.cc:116
> 0xb3a545 extract_insn(rtx_insn*)
> ../../../gcc/gcc/recog.cc:2812
> 0x1010e9e instantiate_virtual_regs_in_insn
> ../../../gcc/gcc/function.cc:1612
> 0x1010e9e instantiate_virtual_regs
> ../../../gcc/gcc/function.cc:1995
> 0x1010e9e execute
> ../../../gcc/gcc/function.cc:2042
>
> The below test suites are passed for this patch.
> 1. The rv64gcv fully regression test.
> 2. The rv64gcv build with glibc.
>
> There may be other similar issue(s) for the mismatch,  we will take care
> of them by test cases one by one.
>
> PR target/115456
>
> gcc/ChangeLog:
>
> * config/riscv/vector-iterators.md: Leverage V_ZVFH instead of V
> which contains the VF_ZVFHMIN for alignment.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr115456-2.c: New test.
> * gcc.target/riscv/rvv/base/pr115456-3.c: New test.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/vector-iterators.md  |  4 ++-
>  .../gcc.target/riscv/rvv/base/pr115456-2.c| 31 +++
>  .../gcc.target/riscv/rvv/base/pr115456-3.c| 31 +++
>  3 files changed, 65 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c
>
> diff --git a/gcc/config/riscv/vector-iterators.md 
> b/gcc/config/riscv/vector-iterators.md
> index 47392d0da4c..43137a2a379 100644
> --- a/gcc/config/riscv/vector-iterators.md
> +++ b/gcc/config/riscv/vector-iterators.md
> @@ -1578,9 +1578,11 @@ (define_mode_iterator VLS_ZVFH [VLSI VLSF])
>
>  (define_mode_iterator V [VI VF_ZVFHMIN])
>
> +(define_mode_iterator V_ZVFH [VI VF])
> +
>  (define_mode_iterator V_VLS [V VLS])
>
> -(define_mode_iterator V_VLS_ZVFH [V VLS_ZVFH])
> +(define_mode_iterator V_VLS_ZVFH [V_ZVFH VLS_ZVFH])
>
>  (define_mode_iterator V_VLSI [VI VLSI])
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c
> new file mode 100644
> index 000..453e18b1c79
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-2.c
> @@ -0,0 +1,31 @@
> +/* Test there is no ICE when compile.  */
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfhmin -mrvv-vector-bits=zvl -mabi=lp64d 
> -O3 -ftree-vectorize" } */
> +
> +#include 
> +#include 
> +
> +typedef _Float16 vnx4f __attribute__ ((vector_size (8)));
> +
> +vnx4f __attribute__ ((noinline, noclone))
> +test_5 (vnx4f x, vnx4f y)
> +{
> +  return __builtin_shufflevector (x, y, 1, 3, 6, 7);
> +}
> +
> +int
> +main (void)
> +{
> +  vnx4f test_5_x = {0, 1, 3, 4};
> +  vnx4f test_5_y = {4, 5, 6, 7};
> +  vnx4f test_5_except = {1, 4, 6, 7};
> +  vnx4f test_5_real;
> +  test_5_real = test_5 (test_5_x, test_5_y);
> +
> +  for (int i = 0; i < 4; i++)
> +assert (test_5_real[i] == test_5_except[i]);
> +
> +  return 0;
> +}
> +
> +/* { dg-final { scan-assembler-times {call\s+__extendhfsf2} 8 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c
> new file mode 100644
> index 000..2c54f1d7538
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr115456-3.c
> @@ -0,0 +1,31 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize" } */
> +
> +#include 
> +#include 
> +
> +typedef _Float16 vnx4f __attribute__ ((vector_size (8)));
> +
> +vnx4f __attribute__ ((noinline, noclone))
> +test_5 (vnx4f x, vnx4f y)
> +{
> +  return __builtin_shufflevector (x, y, 1, 3, 6, 7);
> +}
> +
> +int
> +main (void)
> +{
> +  vnx4f test_5_x = {0, 1, 3, 4};
> +  vnx4f test_5_y = {4, 5, 6, 7};
> +  vnx4f test_5_except = {1, 4, 6, 7};
> +  vnx4f test_5_real;
> +  test_5_real = test_5 (test_5_x, test_5_y);
> +
> +  for (int i = 0; i < 4; i++)
> +assert (test_5_real[

Re: [PATCH 0/2] fix RISC-V zcmp popretz [PR113715]

[Kito Cheng]

Thanks for fixing this issue, and I am wondering doest it possible to
fix that without introduce target hook? I ask that because...GCC 14
also has this bug, but I am not sure it's OK to introduce new target
hook for release branch? or would you suggest we just revert patch to
fix that on GCC 14?

On Wed, Jun 5, 2024 at 9:50 AM Fei Gao  wrote:
>
> The 1st patch adds a hook to allow post processing after epilogue inserted.
> The 2nd one implement the RISC-V hook to solve PR113715.
>
> Fei Gao (2):
>   target hooks: allow post processing after epilogue inserted.
>   [RISC-V]: fix zcmp popretz [PR113715].
>
>  gcc/config/riscv/riscv.cc   | 191 ++--
>  gcc/doc/tm.texi |   5 +
>  gcc/doc/tm.texi.in  |   2 +
>  gcc/function.cc |   2 +
>  gcc/hooks.cc|   7 +
>  gcc/hooks.h |   1 +
>  gcc/target.def  |   8 +
>  gcc/testsuite/gcc.target/riscv/rv32i_zcmp.c |  56 ++
>  8 files changed, 219 insertions(+), 53 deletions(-)
>
> --
> 2.17.1
>

Re: pushed: wwwdocs: [PATCH] gcc-14/changes: Fix mislocated in RISC-V changes

[Kito Cheng]

Ohh, thanks for fixing that!

On Wed, Jun 5, 2024 at 1:16 PM Xi Ruoyao  wrote:
>
> ---
>
> Pushed as obvious.
>
>  htdocs/gcc-14/changes.html | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
> index 6447898e..7a5eb449 100644
> --- a/htdocs/gcc-14/changes.html
> +++ b/htdocs/gcc-14/changes.html
> @@ -1218,9 +1218,9 @@ __asm (".global __flmap_lock"  "\n\t"
>configured with --with-tls=[trad|desc].
>Support for the TLS descriptors, this can be enabled by
>-mtls-dialect=desc and the default behavior can be 
> configure
> -  by --with-tls=[trad|desc], and this feature require glibc 2.40,
> +  by --with-tls=[trad|desc], and this feature require glibc 
> 2.40,
>thanks to Tatsuyuki Ishi from
> -  https://bluewhale.systems/";>Blue Whale Systems
> +  https://bluewhale.systems/";>Blue Whale Systems.
>
>Support for the following standard extensions has been added:
>  
> --
> 2.45.2
>

Re: [PATCH v2 1/3] RISC-V: Add basic Zaamo and Zalrsc support

[Kito Cheng]

Hi Patrick:

One dumb question around Zaamo and Zalrsc, could we still got correct
atomic semantic with only Zaamo or only Zalrsc? I guess Zalrsc only
probably ok, but how about Zaamo only?

And another question around authorship: I notice you are listed as
co-authored, and signed off by Edwin, but according to the mail (and
the result of git pw patch apply) the main author is you? So I'm just
curious who the main author is? not necessary to list co-authored
again if it's you, and need to update author info if it's Edwin, I
know you guy are in same the company, so that's may not big issue is
not clear, but personally I would like to mention correct authorship
if possible :P

[1] How to update author for single commit:
https://stackoverflow.com/questions/3042437/how-can-i-change-the-commit-author-for-a-single-commit

On Tue, Jun 4, 2024 at 5:54 AM Patrick O'Neill  wrote:
>
> The A extension has been split into two parts: Zaamo and Zalrsc.
> This patch adds basic support by making the A extension imply Zaamo and
> Zalrsc.
>
> Zaamo/Zalrsc spec: https://github.com/riscv/riscv-zaamo-zalrsc/tags
> Ratification: https://jira.riscv.org/browse/RVS-1995
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc: Add Zaamo and Zalrsc.
> * config/riscv/arch-canonicalize: Make A imply Zaamo and Zalrsc.
> * config/riscv/riscv.opt: Add Zaamo and Zalrsc
> * config/riscv/sync.md: Convert TARGET_ATOMIC to TARGET_ZAAMO and
> TARGET_ZALRSC.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/attribute-15.c: Adjust expected arch string.
> * gcc.target/riscv/attribute-16.c: Ditto.
> * gcc.target/riscv/attribute-17.c: Ditto.
> * gcc.target/riscv/attribute-18.c: Ditto.
> * gcc.target/riscv/pr110696.c: Ditto.
> * gcc.target/riscv/rvv/base/pr114352-1.c: Ditto.
> * gcc.target/riscv/rvv/base/pr114352-3.c: Ditto.
>
> Signed-off-by: Edwin Lu 
> Co-authored-by: Patrick O'Neill 
> ---
>  gcc/common/config/riscv/riscv-common.cc   | 11 +--
>  gcc/config/riscv/arch-canonicalize|  1 +
>  gcc/config/riscv/riscv.opt|  6 +++-
>  gcc/config/riscv/sync.md  | 30 +--
>  gcc/testsuite/gcc.target/riscv/attribute-15.c |  2 +-
>  gcc/testsuite/gcc.target/riscv/attribute-16.c |  2 +-
>  gcc/testsuite/gcc.target/riscv/attribute-17.c |  2 +-
>  gcc/testsuite/gcc.target/riscv/attribute-18.c |  2 +-
>  gcc/testsuite/gcc.target/riscv/pr110696.c |  2 +-
>  .../gcc.target/riscv/rvv/base/pr114352-1.c|  4 +--
>  .../gcc.target/riscv/rvv/base/pr114352-3.c|  8 ++---
>  11 files changed, 41 insertions(+), 29 deletions(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 88204393fde..78dfd6b1470 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -79,6 +79,9 @@ static const riscv_implied_info_t riscv_implied_info[] =
>{"f", "zicsr"},
>{"d", "zicsr"},
>
> +  {"a", "zaamo"},
> +  {"a", "zalrsc"},
> +
>{"zdinx", "zfinx"},
>{"zfinx", "zicsr"},
>{"zdinx", "zicsr"},
> @@ -255,6 +258,8 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>{"za64rs",  ISA_SPEC_CLASS_NONE, 1, 0},
>{"za128rs", ISA_SPEC_CLASS_NONE, 1, 0},
>{"zawrs", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zaamo", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zalrsc", ISA_SPEC_CLASS_NONE, 1, 0},
>
>{"zba", ISA_SPEC_CLASS_NONE, 1, 0},
>{"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
> @@ -1616,9 +1621,11 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>{"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
>{"zicond",   &gcc_options::x_riscv_zi_subext, MASK_ZICOND},
>
> -  {"za64rs", &gcc_options::x_riscv_za_subext, MASK_ZA64RS},
> +  {"za64rs",  &gcc_options::x_riscv_za_subext, MASK_ZA64RS},
>{"za128rs", &gcc_options::x_riscv_za_subext, MASK_ZA128RS},
> -  {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
> +  {"zawrs",   &gcc_options::x_riscv_za_subext, MASK_ZAWRS},
> +  {"zaamo",   &gcc_options::x_riscv_za_subext, MASK_ZAAMO},
> +  {"zalrsc",  &gcc_options::x_riscv_za_subext, MASK_ZALRSC},
>
>{"zba",&gcc_options::x_riscv_zb_subext, MASK_ZBA},
>{"zbb",&gcc_options::x_riscv_zb_subext, MASK_ZBB},
> diff --git a/gcc/config/riscv/arch-canonicalize 
> b/gcc/config/riscv/arch-canonicalize
> index 8f7d040cdeb..6c10d1aa81b 100755
> --- a/gcc/config/riscv/arch-canonicalize
> +++ b/gcc/config/riscv/arch-canonicalize
> @@ -40,6 +40,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x']
>  #
>  IMPLIED_EXT = {
>"d" : ["f", "zicsr"],
> +  "a" : ["zaamo", "zalrsc"],
>"f" : ["zicsr"],
>"zdinx" : ["zfinx", "zicsr"],
>"zfinx" : ["zicsr"],
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 87f58332016..fa57b4b1090 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -248,7 +248,

Re: RISC-V: Patches need to be backport to GCC-14

[Kito Cheng]

Yeah, I think both should back port to GCC-14, but I would like to
wait one more week like the convention within the GCC community :)

On Mon, Jun 3, 2024 at 10:05 AM juzhe.zh...@rivai.ai
 wrote:
>
> Hi, I saw Robin commit these following patches:
> https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=9781885a624f3e29634d95c14cd10940cefb1a5a
> https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=a2fd0812a54cf51520f15e900df4cfb5874b75ed
>
> I think they need to be backport to GCC-14.
>
> Any objections ? or can some one backport them to GCC-14 ?
>
> Thanks.
> 
> juzhe.zh...@rivai.ai

Re: [PATCH 41/52] riscv: New hook implementation riscv_c_mode_for_floating_type

[Kito Cheng]

LGTM from RISC-V, thanks :)

On Mon, Jun 3, 2024 at 11:08 AM Kewen Lin  wrote:
>
> This is to remove macros {FLOAT,{,LONG_}DOUBLE}_TYPE_SIZE
> defines in riscv port, and add new port specific hook
> implementation riscv_c_mode_for_floating_type.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_c_mode_for_floating_type): New 
> function.
> (TARGET_C_MODE_FOR_FLOATING_TYPE): New macro.
> * config/riscv/riscv.h (FLOAT_TYPE_SIZE): Remove.
> (DOUBLE_TYPE_SIZE): Likewise.
> (LONG_DOUBLE_TYPE_SIZE): Likewise.
> ---
>  gcc/config/riscv/riscv.cc | 15 +++
>  gcc/config/riscv/riscv.h  |  4 
>  2 files changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 92935275aaa..b011344cabe 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -11449,6 +11449,18 @@ riscv_expand_usadd (rtx dest, rtx x, rtx y)
>emit_move_insn (dest, gen_lowpart (mode, xmode_dest));
>  }
>
> +/* Implement TARGET_C_MODE_FOR_FLOATING_TYPE.  Return TFmode for
> +   TI_LONG_DOUBLE_TYPE which is for long double type, go with the
> +   default one for the others.  */
> +
> +static machine_mode
> +riscv_c_mode_for_floating_type (enum tree_index ti)
> +{
> +  if (ti == TI_LONG_DOUBLE_TYPE)
> +return TFmode;
> +  return default_mode_for_floating_type (ti);
> +}
> +
>  /* Initialize the GCC target structure.  */
>  #undef TARGET_ASM_ALIGNED_HI_OP
>  #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
> @@ -11804,6 +11816,9 @@ riscv_expand_usadd (rtx dest, rtx x, rtx y)
>  #undef TARGET_GET_RAW_RESULT_MODE
>  #define TARGET_GET_RAW_RESULT_MODE riscv_get_raw_result_mode
>
> +#undef TARGET_C_MODE_FOR_FLOATING_TYPE
> +#define TARGET_C_MODE_FOR_FLOATING_TYPE riscv_c_mode_for_floating_type
> +
>  struct gcc_target targetm = TARGET_INITIALIZER;
>
>  #include "gt-riscv.h"
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index d6b14c4d620..83c4677c6a1 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -188,10 +188,6 @@ ASM_MISA_SPEC
>  #define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32)
>  #define LONG_TYPE_SIZE POINTER_SIZE
>
> -#define FLOAT_TYPE_SIZE 32
> -#define DOUBLE_TYPE_SIZE 64
> -#define LONG_DOUBLE_TYPE_SIZE 128
> -
>  /* Allocation boundary (in *bits*) for storing arguments in argument list.  
> */
>  #define PARM_BOUNDARY BITS_PER_WORD
>
> --
> 2.43.0
>

Re: [PATCH v4] RISC-V: Introduce -mvector-strict-align.

[Kito Cheng]

I just created two PRs for adding those new options into
riscv-toolchain-conventions, so that we could make sure it aligned
with clang/LLVM community.

https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/49
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/50

On Wed, May 29, 2024 at 3:20 AM Robin Dapp  wrote:
>
> Hi,
>
> this patch disables movmisalign by default and introduces
> the -mno-vector-strict-align option to override it and re-enable
> movmisalign.  For now, generic-ooo is the only uarch that supports
> misaligned vector access.
>
> The patch also adds a check_effective_target_riscv_v_misalign_ok to
> the testsuite which enables or disables the vector misalignment tests
> depending on whether the target under test can execute a misaligned
> vle32.
>
> Changes from v3:
>  - Adressed Kito's comments.
>  - Made -mscalar-strict-align a real alias.
>
> Regards
>  Robin
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-opts.h (TARGET_VECTOR_MISALIGN_SUPPORTED):
> Move from here...
> * config/riscv/riscv.h (TARGET_VECTOR_MISALIGN_SUPPORTED):
> ...to here and map to riscv_vector_unaligned_access_p.
> * config/riscv/riscv.opt: Add -mvector-strict-align.
> * config/riscv/riscv.cc (struct riscv_tune_param): Add
> vector_unaligned_access.
> (riscv_override_options_internal): Set
> riscv_vector_unaligned_access_p.
> * doc/invoke.texi: Document -mvector-strict-align.
>
> gcc/testsuite/ChangeLog:
>
> * lib/target-supports.exp: Add
> check_effective_target_riscv_v_misalign_ok.
> * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul2-7.c: Add
> -mno-vector-strict-align.
> * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-10.c: Ditto.
> * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-11.c: Ditto.
> * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-12.c: Ditto.
> * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-8.c: Ditto.
> * gcc.dg/vect/costmodel/riscv/rvv/vla_vs_vls-9.c: Ditto.
> * gcc.target/riscv/rvv/autovec/vls/misalign-1.c: Ditto.
> ---
>  gcc/config/riscv/riscv-opts.h |  3 --
>  gcc/config/riscv/riscv.cc | 19 +++
>  gcc/config/riscv/riscv.h  |  5 +++
>  gcc/config/riscv/riscv.opt|  8 +
>  gcc/doc/invoke.texi   | 22 
>  .../costmodel/riscv/rvv/dynamic-lmul2-7.c |  2 +-
>  .../vect/costmodel/riscv/rvv/vla_vs_vls-10.c  |  2 +-
>  .../vect/costmodel/riscv/rvv/vla_vs_vls-11.c  |  2 +-
>  .../vect/costmodel/riscv/rvv/vla_vs_vls-12.c  |  2 +-
>  .../vect/costmodel/riscv/rvv/vla_vs_vls-8.c   |  2 +-
>  .../vect/costmodel/riscv/rvv/vla_vs_vls-9.c   |  2 +-
>  .../riscv/rvv/autovec/vls/misalign-1.c|  2 +-
>  gcc/testsuite/lib/target-supports.exp | 34 +--
>  13 files changed, 93 insertions(+), 12 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index 1b2dd5757a8..f58a07abffc 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -147,9 +147,6 @@ enum rvv_vector_bits_enum {
>   ? 0 
>   \
>   : 32 << (__builtin_popcount (opts->x_riscv_zvl_flags) - 1))
>
> -/* TODO: Enable RVV movmisalign by default for now.  */
> -#define TARGET_VECTOR_MISALIGN_SUPPORTED 1
> -
>  /* The maximmum LMUL according to user configuration.  */
>  #define TARGET_MAX_LMUL  
>   \
>(int) (rvv_max_lmul == RVV_DYNAMIC ? RVV_M8 : rvv_max_lmul)
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index a99211d56b1..13cd61a4a22 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -287,6 +287,7 @@ struct riscv_tune_param
>unsigned short memory_cost;
>unsigned short fmv_cost;
>bool slow_unaligned_access;
> +  bool vector_unaligned_access;
>bool use_divmod_expansion;
>bool overlap_op_by_pieces;
>unsigned int fusible_ops;
> @@ -299,6 +300,10 @@ struct riscv_tune_param
>  /* Whether unaligned accesses execute very slowly.  */
>  bool riscv_slow_unaligned_access_p;
>
> +/* Whether misaligned vector accesses are supported (i.e. do not
> +   throw an exception).  */
> +bool riscv_vector_unaligned_access_p;
> +
>  /* Whether user explicitly passed -mstrict-align.  */
>  bool riscv_user_wants_strict_align;
>
> @@ -441,6 +446,7 @@ static const struct riscv_tune_param rocket_tune_info = {
>5,   /* memory_cost */
>8,   /* fmv_cost */
>true,/* 
> slow_unaligned_access */
> +  false,   /* vector_unaligned_access */
>false,   /* use_divmod_expansion */
>false,  

Re: [PATCH v3] RISC-V: Introduce -mvector-strict-align.

[Kito Cheng]

> @@ -9536,6 +9549,12 @@ riscv_override_options_internal (struct gcc_options 
> *opts)
>riscv_slow_unaligned_access_p = (cpu->tune_param->slow_unaligned_access
>|| TARGET_STRICT_ALIGN);
>
> +  /* By default, when -mno-vector-strict-align is not specified, do not allow
> + unaligned vector memory accesses except if -mtune's setting explicitly
> + allows it.  */
> +  riscv_vector_unaligned_access_p = rvv_vector_strict_align == 0 ||

opts->x_rvv_vector_strict_align rather than rvv_vector_strict_align,
rvv_vector_strict_align is alias of global_options.x_rvv_vector_strict_align

> +cpu->tune_param->vector_unaligned_access;
> +
>/* Make a note if user explicitly passed -mstrict-align for later
>   builtin macro generation.  Can't use target_flags_explicitly since
>   it is set even for -mno-strict-align.  */

Re: [PATCH V2] RISC-V: Fix missing boolean_expression in zmmul extension

[Kito Cheng]

Committed to trunk :)

On Fri, May 24, 2024 at 7:58 PM Kito Cheng  wrote:
>
> LGTM
>
> Liao Shihua  於 2024年5月24日 週五 13:05 寫道：
>>
>> Update v1->v2
>> Add testcase for this patch.
>>
>> Missing boolean_expression TARGET_ZMMUL in riscv_rtx_costs() cause different 
>> instructions when
>> multiplying an integer with a constant. ( 
>> https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1482 )
>>
>> int foo(int *ib) {
>> *ib = *ib * 33938;
>> return 0;
>> }
>>
>> rv64im:
>> lw  a4,0(a1)
>> li  a5,32768
>> addiw   a5,a5,1170
>> mulwa5,a5,a4
>> sw  a5,0(a1)
>> ret
>>
>> rv64i_zmmul:
>> lw  a4,0(a1)
>> slliw   a5,a4,5
>> addwa5,a5,a4
>> slliw   a5,a5,3
>> addwa5,a5,a4
>> slliw   a5,a5,3
>> addwa5,a5,a4
>> slliw   a5,a5,3
>> addwa5,a5,a4
>> slliw   a5,a5,1
>> sw  a5,0(a1)
>> ret
>>
>> Fixed.
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv.cc (riscv_rtx_costs): Add TARGET_ZMMUL.
>>
>> gcc/testsuite/ChangeLog:
>>
>> * gcc.target/riscv/zmmul-3.c: New test.
>>
>> ---
>>  gcc/config/riscv/riscv.cc| 2 +-
>>  gcc/testsuite/gcc.target/riscv/zmmul-3.c | 8 
>>  2 files changed, 9 insertions(+), 1 deletion(-)
>>  create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-3.c
>>
>> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>> index 85df5b7ab49..580ae007181 100644
>> --- a/gcc/config/riscv/riscv.cc
>> +++ b/gcc/config/riscv/riscv.cc
>> @@ -3753,7 +3753,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int 
>> outer_code, int opno ATTRIBUTE_UN
>>  case MULT:
>>if (float_mode_p)
>> *total = tune_param->fp_mul[mode == DFmode];
>> -  else if (!TARGET_MUL)
>> +  else if (!(TARGET_MUL || TARGET_ZMMUL))
>> /* Estimate the cost of a library call.  */
>> *total = COSTS_N_INSNS (speed ? 32 : 6);
>>else if (GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD)
>> diff --git a/gcc/testsuite/gcc.target/riscv/zmmul-3.c 
>> b/gcc/testsuite/gcc.target/riscv/zmmul-3.c
>> new file mode 100644
>> index 000..ae9752462e4
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/riscv/zmmul-3.c
>> @@ -0,0 +1,8 @@
>> +/* { dg-do compile } */
>> +/* { dg-options "-march=rv64iafdc_zmmul -mabi=lp64d" } */
>> +int foo1(int a)
>> +{
>> +return a * 99;
>> +}
>> +
>> +/* { dg-final { scan-assembler-times "mulw\t" 1 } } */
>> \ No newline at end of file
>> --
>> 2.34.1
>>

Re: [PATCH V2] RISC-V: Fix missing boolean_expression in zmmul extension

[Kito Cheng]

LGTM

Liao Shihua  於 2024年5月24日 週五 13:05 寫道：

> Update v1->v2
> Add testcase for this patch.
>
> Missing boolean_expression TARGET_ZMMUL in riscv_rtx_costs() cause
> different instructions when
> multiplying an integer with a constant. (
> https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1482 )
>
> int foo(int *ib) {
> *ib = *ib * 33938;
> return 0;
> }
>
> rv64im:
> lw  a4,0(a1)
> li  a5,32768
> addiw   a5,a5,1170
> mulwa5,a5,a4
> sw  a5,0(a1)
> ret
>
> rv64i_zmmul:
> lw  a4,0(a1)
> slliw   a5,a4,5
> addwa5,a5,a4
> slliw   a5,a5,3
> addwa5,a5,a4
> slliw   a5,a5,3
> addwa5,a5,a4
> slliw   a5,a5,3
> addwa5,a5,a4
> slliw   a5,a5,1
> sw  a5,0(a1)
> ret
>
> Fixed.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_rtx_costs): Add TARGET_ZMMUL.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/zmmul-3.c: New test.
>
> ---
>  gcc/config/riscv/riscv.cc| 2 +-
>  gcc/testsuite/gcc.target/riscv/zmmul-3.c | 8 
>  2 files changed, 9 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-3.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 85df5b7ab49..580ae007181 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -3753,7 +3753,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
> outer_code, int opno ATTRIBUTE_UN
>  case MULT:
>if (float_mode_p)
> *total = tune_param->fp_mul[mode == DFmode];
> -  else if (!TARGET_MUL)
> +  else if (!(TARGET_MUL || TARGET_ZMMUL))
> /* Estimate the cost of a library call.  */
> *total = COSTS_N_INSNS (speed ? 32 : 6);
>else if (GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD)
> diff --git a/gcc/testsuite/gcc.target/riscv/zmmul-3.c
> b/gcc/testsuite/gcc.target/riscv/zmmul-3.c
> new file mode 100644
> index 000..ae9752462e4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zmmul-3.c
> @@ -0,0 +1,8 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64iafdc_zmmul -mabi=lp64d" } */
> +int foo1(int a)
> +{
> +return a * 99;
> +}
> +
> +/* { dg-final { scan-assembler-times "mulw\t" 1 } } */
> \ No newline at end of file
> --
> 2.34.1
>
>

Re: [PATCH] RISC-V: Fix missing boolean_expression in zmmul extension

[Kito Cheng]

Could you add a testcase to make sure zmmul will generate mul instruction?

Liao Shihua  於 2024年5月23日 週四 18:48 寫道：

> Missing boolean_expression TARGET_ZMMUL in riscv_rtx_costs() casuse
> different instructions when multiplying an integer with a constant.
> ( https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1482 )
>
> int foo(int *ib) {
> *ib = *ib * 33938;
> return 0;
> }
>
> rv64im:
> lw  a4,0(a1)
> li  a5,32768
> addiw   a5,a5,1170
> mulwa5,a5,a4
> sw  a5,0(a1)
> ret
>
> rv64i_zmmul:
> lw  a4,0(a1)
> slliw   a5,a4,5
> addwa5,a5,a4
> slliw   a5,a5,3
> addwa5,a5,a4
> slliw   a5,a5,3
> addwa5,a5,a4
> slliw   a5,a5,3
> addwa5,a5,a4
> slliw   a5,a5,1
> sw  a5,0(a1)
> ret
>
> Fixed.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_rtx_costs): Add TARGET_ZMMUL.
>
> ---
>  gcc/config/riscv/riscv.cc | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 85df5b7ab49..580ae007181 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -3753,7 +3753,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int
> outer_code, int opno ATTRIBUTE_UN
>  case MULT:
>if (float_mode_p)
> *total = tune_param->fp_mul[mode == DFmode];
> -  else if (!TARGET_MUL)
> +  else if (!(TARGET_MUL || TARGET_ZMMUL))
> /* Estimate the cost of a library call.  */
> *total = COSTS_N_INSNS (speed ? 32 : 6);
>else if (GET_MODE_SIZE (mode).to_constant () > UNITS_PER_WORD)
> --
> 2.34.1
>
>

Re: [PATCH] RISC-V: Modify _Bfloat16 to __bf16

[Kito Cheng]

LGTM, thanks for fixing this :)

On Fri, May 17, 2024 at 4:05 PM Xiao Zeng  wrote:
>
> According to the description in:
> <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/367>,
> the type representation symbol of BF16 has been corrected.
>
> Kito Cheng pointed out relevant information in the email:
> <https://gcc.gnu.org/pipermail/gcc-patches/2024-May/651850.html>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-builtins.cc (riscv_init_builtin_types):
> Modify _Bfloat16 to __bf16.
> * config/riscv/riscv.cc (riscv_mangle_type): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/_Bfloat16-nanboxing.c: Move to...
> * gcc.target/riscv/__bf16-nanboxing.c: ...here.
> * gcc.target/riscv/bf16_arithmetic.c: Modify _Bfloat16 to __bf16.
> * gcc.target/riscv/bf16_call.c: Ditto.
> * gcc.target/riscv/bf16_comparison.c: Ditto.
> * gcc.target/riscv/bf16_float_libcall_convert.c: Ditto.
> * gcc.target/riscv/bf16_integer_libcall_convert.c: Ditto.
> ---
>  gcc/config/riscv/riscv-builtins.cc   |  6 +++---
>  gcc/config/riscv/riscv.cc|  2 +-
>  .../{_Bfloat16-nanboxing.c => __bf16-nanboxing.c}| 12 ++--
>  gcc/testsuite/gcc.target/riscv/bf16_arithmetic.c |  6 +++---
>  gcc/testsuite/gcc.target/riscv/bf16_call.c   |  4 ++--
>  gcc/testsuite/gcc.target/riscv/bf16_comparison.c |  6 +++---
>  .../gcc.target/riscv/bf16_float_libcall_convert.c|  2 +-
>  .../gcc.target/riscv/bf16_integer_libcall_convert.c  |  2 +-
>  8 files changed, 20 insertions(+), 20 deletions(-)
>  rename gcc/testsuite/gcc.target/riscv/{_Bfloat16-nanboxing.c => 
> __bf16-nanboxing.c} (83%)
>
> diff --git a/gcc/config/riscv/riscv-builtins.cc 
> b/gcc/config/riscv/riscv-builtins.cc
> index 4c08834288a..dc54e1a59b5 100644
> --- a/gcc/config/riscv/riscv-builtins.cc
> +++ b/gcc/config/riscv/riscv-builtins.cc
> @@ -275,7 +275,7 @@ riscv_init_builtin_types (void)
>  lang_hooks.types.register_builtin_type (riscv_float16_type_node,
> "_Float16");
>
> -  /* Provide the _Bfloat16 type and bfloat16_type_node if needed.  */
> +  /* Provide the __bf16 type and bfloat16_type_node if needed.  */
>if (!bfloat16_type_node)
>  {
>riscv_bfloat16_type_node = make_node (REAL_TYPE);
> @@ -286,9 +286,9 @@ riscv_init_builtin_types (void)
>else
>  riscv_bfloat16_type_node = bfloat16_type_node;
>
> -  if (!maybe_get_identifier ("_Bfloat16"))
> +  if (!maybe_get_identifier ("__bf16"))
>  lang_hooks.types.register_builtin_type (riscv_bfloat16_type_node,
> -   "_Bfloat16");
> +   "__bf16");
>  }
>
>  /* Implement TARGET_INIT_BUILTINS.  */
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 4067505270e..cf15a12de3a 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -10262,7 +10262,7 @@ riscv_asan_shadow_offset (void)
>  static const char *
>  riscv_mangle_type (const_tree type)
>  {
> -  /* Half-precision float, _Float16 is "DF16_" and _Bfloat16 is "DF16b".  */
> +  /* Half-precision float, _Float16 is "DF16_" and __bf16 is "DF16b".  */
>if (SCALAR_FLOAT_TYPE_P (type) && TYPE_PRECISION (type) == 16)
>  {
>if (TYPE_MODE (type) == HFmode)
> diff --git a/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c 
> b/gcc/testsuite/gcc.target/riscv/__bf16-nanboxing.c
> similarity index 83%
> rename from gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
> rename to gcc/testsuite/gcc.target/riscv/__bf16-nanboxing.c
> index 11a73d22234..a9a586c98b9 100644
> --- a/gcc/testsuite/gcc.target/riscv/_Bfloat16-nanboxing.c
> +++ b/gcc/testsuite/gcc.target/riscv/__bf16-nanboxing.c
> @@ -1,14 +1,14 @@
>  /* { dg-do compile } */
>  /* { dg-options "-march=rv64ifd -mabi=lp64d -mcmodel=medlow -O" } */
>
> -_Bfloat16 gvar = 9.87654;
> +__bf16 gvar = 9.87654;
>  union U
>  {
>unsigned short i16;
> -  _Bfloat16 f16;
> +  __bf16 f16;
>  };
>
> -_Bfloat16
> +__bf16
>  test1 (unsigned short input)
>  {
>union U tmp;
> @@ -16,19 +16,19 @@ test1 (unsigned short input)
>return tmp.f16;
>  }
>
> -_Bfloat16
> +__bf16
>  test2 ()
>  {
>return 1.234f;
>  }
>
> -_Bfloat16
> +__bf16
>  test3 ()
>  {
>return gvar;
>  }
>
> -_Bfloat16
> +__bf16
>  test ()
>  {
>return 0.0f;
> diff --git a/gcc/testsuite/gcc.target/riscv/bf16_

Re: [PATCH] RISC-V: testsuite: Drop march-string in cmpmemsi/cpymemsi tests

[Kito Cheng]

LGTM

On Thu, May 16, 2024 at 5:09 PM Christoph Müllner
 wrote:
>
> The tests cmpmemsi-1.c and cpymemsi-1.c are execution ("dg-do run")
> tests, which does not have any restrictions for the enabled extensions.
> Further, no other listed options are required.
> Let's drop the options, so that the test can also be executed on
> non-f and non-d targets.  However, we need to set options to the
> defaults without '-ansi', because the included test file uses the
> 'asm' keyword, which is not part of ANSI C.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/cmpmemsi-1.c: Drop options.
> * gcc.target/riscv/cpymemsi-1.c: Likewise.
>
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/testsuite/gcc.target/riscv/cmpmemsi-1.c | 3 +--
>  gcc/testsuite/gcc.target/riscv/cpymemsi-1.c | 4 +---
>  2 files changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/gcc/testsuite/gcc.target/riscv/cmpmemsi-1.c 
> b/gcc/testsuite/gcc.target/riscv/cmpmemsi-1.c
> index d7e0bc47407..698f27d89fb 100644
> --- a/gcc/testsuite/gcc.target/riscv/cmpmemsi-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/cmpmemsi-1.c
> @@ -1,6 +1,5 @@
>  /* { dg-do run } */
> -/* { dg-options "-march=rv32gc_zbb -save-temps -g0 -fno-lto" { target { rv32 
> } } } */
> -/* { dg-options "-march=rv64gc_zbb -save-temps -g0 -fno-lto" { target { rv64 
> } } } */
> +/* { dg-options "-pedantic-errors" } */
>  /* { dg-timeout-factor 2 } */
>
>  #include "../../gcc.dg/memcmp-1.c"
> diff --git a/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c 
> b/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
> index 983b564ccaf..30e9f119bed 100644
> --- a/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
> @@ -1,7 +1,5 @@
>  /* { dg-do run } */
> -/* { dg-options "-march=rv32gc -save-temps -g0 -fno-lto" { target { rv32 } } 
> } */
> -/* { dg-options "-march=rv64gc -save-temps -g0 -fno-lto" { target { rv64 } } 
> } */
> -/* { dg-additional-options "-DRUN_FRACTION=11" { target simulator } } */
> +/* { dg-options "-pedantic-errors" } */
>  /* { dg-timeout-factor 2 } */
>
>  #include "../../gcc.dg/memcmp-1.c"
> --
> 2.44.0
>

Re: [NOT CODE REVIEW] [PATCH v3 1/1] [RISC-V] Add support for _Bfloat16

[Kito Cheng]

Hi Xiao Zeng:

Just wondering why use _Bfloat16 rather than __bf16? you mention
__bf16 in comment, but implementation use _Bfloat16? I would like to
use __bf16 to make it consistent between LLVM and psABI if possible :)

Re: [PATCH] RISC-V: testsuite: Drop march-string in cpymemsi-1.c

[Kito Cheng]

Just one minor question

> diff --git a/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c 
> b/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
> index 983b564ccaf..aee54d9aa00 100644
> --- a/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/cpymemsi-1.c
> @@ -1,6 +1,5 @@
>  /* { dg-do run } */
> -/* { dg-options "-march=rv32gc -save-temps -g0 -fno-lto" { target { rv32 } } 
> } */
> -/* { dg-options "-march=rv64gc -save-temps -g0 -fno-lto" { target { rv64 } } 
> } */
> +/* { dg-options "-save-temps -g0 -fno-lto" } */

I know -save-temps -g0 already exists, but I am wondering why we need
those 2 options here?

Re: [PATCH] RISC-V: Fix cbo.zero expansion for rv32

[Kito Cheng]

LGTM :)

On Wed, May 15, 2024 at 2:48 PM Christoph Müllner
 wrote:
>
> Emitting a DI pattern won't find a match for rv32 and manifests in
> the failing test case gcc.target/riscv/cmo-zicboz-zic64-1.c.
> Let's fix this in the expansion and also address the different
> code that gets generated for rv32/rv64.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-string.cc 
> (riscv_expand_block_clear_zicboz_zic64b):
> Fix expansion for rv32.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/cmo-zicboz-zic64-1.c: Fix for rv32.
>
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/config/riscv/riscv-string.cc  |  5 ++-
>  .../gcc.target/riscv/cmo-zicboz-zic64-1.c | 36 ++-
>  2 files changed, 14 insertions(+), 27 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-string.cc 
> b/gcc/config/riscv/riscv-string.cc
> index 87f5fdee3c1..b515f44d17a 100644
> --- a/gcc/config/riscv/riscv-string.cc
> +++ b/gcc/config/riscv/riscv-string.cc
> @@ -827,7 +827,10 @@ riscv_expand_block_clear_zicboz_zic64b (rtx dest, rtx 
> length)
>  {
>rtx mem = adjust_address (dest, BLKmode, offset);
>rtx addr = force_reg (Pmode, XEXP (mem, 0));
> -  emit_insn (gen_riscv_zero_di (addr));
> +  if (TARGET_64BIT)
> +   emit_insn (gen_riscv_zero_di (addr));
> +  else
> +   emit_insn (gen_riscv_zero_si (addr));
>offset += cbo_bytes;
>  }
>
> diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c 
> b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c
> index c2d79eb7ae6..9192b391b11 100644
> --- a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c
> +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-zic64-1.c
> @@ -1,25 +1,9 @@
>  /* { dg-do compile } */
> -/* { dg-options "-march=rv64gc_zic64b_zicboz" { target { rv64 } } } */
>  /* { dg-options "-march=rv32gc_zic64b_zicboz" { target { rv32 } } } */
> +/* { dg-options "-march=rv64gc_zic64b_zicboz" { target { rv64 } } } */
>  /* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
> -/* { dg-final { check-function-bodies "**" "" } } */
> -/* { dg-allow-blank-lines-in-output 1 } */
>
> -/*
> -**clear_buf_123:
> -**...
> -**cbo\.zero\t0\(a[0-9]+\)
> -**sd\tzero,64\(a[0-9]+\)
> -**sd\tzero,72\(a[0-9]+\)
> -**sd\tzero,80\(a[0-9]+\)
> -**sd\tzero,88\(a[0-9]+\)
> -**sd\tzero,96\(a[0-9]+\)
> -**sd\tzero,104\(a[0-9]+\)
> -**sd\tzero,112\(a[0-9]+\)
> -**sh\tzero,120\(a[0-9]+\)
> -**sb\tzero,122\(a[0-9]+\)
> -**...
> -*/
> +// 1x cbo.zero, 7x sd (rv64) or 14x sw (rv32), 1x sh, 1x sb
>  int
>  clear_buf_123 (void *p)
>  {
> @@ -27,17 +11,17 @@ clear_buf_123 (void *p)
>__builtin_memset (p, 0, 123);
>  }
>
> -/*
> -**clear_buf_128:
> -**...
> -**cbo\.zero\t0\(a[0-9]+\)
> -**addi\ta[0-9]+,a[0-9]+,64
> -**cbo\.zero\t0\(a[0-9]+\)
> -**...
> -*/
> +// 2x cbo.zero, 1x addi 64
>  int
>  clear_buf_128 (void *p)
>  {
>p = __builtin_assume_aligned(p, 64);
>__builtin_memset (p, 0, 128);
>  }
> +
> +/* { dg-final { scan-assembler-times "cbo\.zero\t" 3 } } */
> +/* { dg-final { scan-assembler-times "addi\ta\[0-9\]+,a\[0-9\]+,64" 1 } } */
> +/* { dg-final { scan-assembler-times "sd\t" 7 { target { rv64 } } } } */
> +/* { dg-final { scan-assembler-times "sw\t" 14 { target { rv32 } } } } */
> +/* { dg-final { scan-assembler-times "sh\t" 1 } } */
> +/* { dg-final { scan-assembler-times "sb\t" 1 } } */
> --
> 2.44.0
>

Re: [PATCH] RISC-V: Add Zvfbfwma extension to the -march= option

[Kito Cheng]

LGTM, I agree we should only implement what Embedded Processor
implies, we have no way to know that from the arch string

On Wed, May 15, 2024 at 1:35 PM Xiao Zeng  wrote:
>
> This patch would like to add new sub extension (aka Zvfbfwma) to the
> -march= option. It introduces a new data type BF16.
>
> 1 In spec: "Zvfbfwma requires the Zvfbfmin extension and the Zfbfmin 
> extension."
>   1.1 In EmbeddedProcessor: Zvfbfwma -> Zvfbfmin -> Zve32f
>   1.2 In Application Processor: Zvfbfwma -> Zvfbfmin -> V
>   1.3 In both scenarios, there are: Zvfbfwma -> Zfbfmin
>
> 2 Zvfbfmin's information is in:
> 
>
> 3 Zfbfmin's formation is in:
> 
>
> 4 Depending on different usage scenarios, the Zvfbfwma extension may
> depend on 'V' or 'Zve32f'. This patch only implements dependencies in
> scenario of Embedded Processor. This is consistent with the processing
> strategy in Zvfbfmin. In scenario of Application Processor, it is
> necessary to explicitly indicate the dependent 'V' extension.
>
> 5 You can locate more information about Zvfbfwma from below spec doc:
> 
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc:
> (riscv_implied_info): Add zvfbfwma item.
> (riscv_ext_version_table): Ditto.
> (riscv_ext_flag_table): Ditto.
> * config/riscv/riscv.opt:
> (MASK_ZVFBFWMA): New macro.
> (TARGET_ZVFBFWMA): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/arch-37.c: New test.
> * gcc.target/riscv/arch-38.c: New test.
> * gcc.target/riscv/predef-36.c: New test.
> * gcc.target/riscv/predef-37.c: New test.
> ---
>  gcc/common/config/riscv/riscv-common.cc|  5 +++
>  gcc/config/riscv/riscv.opt |  2 +
>  gcc/testsuite/gcc.target/riscv/arch-37.c   |  5 +++
>  gcc/testsuite/gcc.target/riscv/arch-38.c   |  5 +++
>  gcc/testsuite/gcc.target/riscv/predef-36.c | 48 ++
>  gcc/testsuite/gcc.target/riscv/predef-37.c | 48 ++
>  6 files changed, 113 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-37.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/arch-38.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-36.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/predef-37.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index fb76017ffbc..88204393fde 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -162,6 +162,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
>{"zfa", "f"},
>
>{"zvfbfmin", "zve32f"},
> +  {"zvfbfwma", "zvfbfmin"},
> +  {"zvfbfwma", "zfbfmin"},
>{"zvfhmin", "zve32f"},
>{"zvfh", "zve32f"},
>{"zvfh", "zfhmin"},
> @@ -336,6 +338,7 @@ static const struct riscv_ext_version 
> riscv_ext_version_table[] =
>{"zfh",   ISA_SPEC_CLASS_NONE, 1, 0},
>{"zfhmin",ISA_SPEC_CLASS_NONE, 1, 0},
>{"zvfbfmin",  ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zvfbfwma",  ISA_SPEC_CLASS_NONE, 1, 0},
>{"zvfhmin",   ISA_SPEC_CLASS_NONE, 1, 0},
>{"zvfh",  ISA_SPEC_CLASS_NONE, 1, 0},
>
> @@ -1667,6 +1670,7 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>{"zve64f",   &gcc_options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_FP_32},
>{"zve64d",   &gcc_options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_FP_64},
>{"zvfbfmin", &gcc_options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_BF_16},
> +  {"zvfbfwma", &gcc_options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_BF_16},
>{"zvfhmin",  &gcc_options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_FP_16},
>{"zvfh", &gcc_options::x_riscv_vector_elen_flags, 
> MASK_VECTOR_ELEN_FP_16},
>
> @@ -1704,6 +1708,7 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>{"zfhmin",&gcc_options::x_riscv_zf_subext, MASK_ZFHMIN},
>{"zfh",   &gcc_options::x_riscv_zf_subext, MASK_ZFH},
>{"zvfbfmin",  &gcc_options::x_riscv_zf_subext, MASK_ZVFBFMIN},
> +  {"zvfbfwma",  &gcc_options::x_riscv_zf_subext, MASK_ZVFBFWMA},
>{"zvfhmin",   &gcc_options::x_riscv_zf_subext, MASK_ZVFHMIN},
>{"zvfh",  &gcc_options::x_riscv_zf_subext, MASK_ZVFH},
>
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 1252834aec5..d209ac896fd 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -401,6 +401,8 @@ Mask(ZFH) Var(riscv_zf_subext)
>
>  Mask(ZVFBFMIN) Var(riscv_zf_subext)
>
> +Mask(ZVFBFWMA) Var(riscv_zf_subext)
> +
>  Mask(ZVFHMIN) Var(riscv_zf_subext)
>
>  Mask(ZVFH)Var(riscv_zf_subext)
> diff --git a/gcc/testsuite/

Re: [PATCH v1] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar

[Kito Cheng]

LGTM as well :)

On Sat, May 11, 2024 at 3:58 PM juzhe.zh...@rivai.ai
 wrote:
>
> LGTM from my side. Wait for kito chime in.
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: pan2.li
> Date: 2024-05-11 15:54
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; Pan Li
> Subject: [PATCH v1] RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 
> scalar
> From: Pan Li 
>
> For the vfw vx format RVV intrinsic, the scalar type _Float16 also
> requires the zvfh extension.  Unfortunately,  we only check the
> vector tree type and miss the scalar _Float16 type checking.  For
> example:
>
> vfloat32mf2_t test_vfwsub_wf_f32mf2(vfloat32mf2_t vs2, _Float16 rs1, size_t 
> vl)
> {
>   return __riscv_vfwsub_wf_f32mf2(vs2, rs1, vl);
> }
>
> It should report some error message like zvfh extension is required
> instead of ICE for unreg insn.
>
> This patch would like to make up such kind of validation for _Float16
> in the RVV intrinsic API.  It will report some error like below when
> there is no zvfh enabled.
>
> error: built-in function '__riscv_vfwsub_wf_f32mf2(vs2,  rs1,  vl)'
>   requires the zvfhmin or zvfh ISA extension
>
> PR target/114988
>
> Passed the rv64gcv fully regression tests, included c/c++/fortran.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc
> (validate_instance_type_required_extensions): New func impl to
> validate the intrinisc func type ops.
> (expand_builtin): Validate instance type before expand.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr114988-1.c: New test.
> * gcc.target/riscv/rvv/base/pr114988-2.c: New test.
>
> Signed-off-by: Pan Li 
> ---
> gcc/config/riscv/riscv-vector-builtins.cc | 51 +++
> .../gcc.target/riscv/rvv/base/pr114988-1.c|  9 
> .../gcc.target/riscv/rvv/base/pr114988-2.c|  9 
> 3 files changed, 69 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-2.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc 
> b/gcc/config/riscv/riscv-vector-builtins.cc
> index 192a6c230d1..3fdb4400d70 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -4632,6 +4632,54 @@ gimple_fold_builtin (unsigned int code, 
> gimple_stmt_iterator *gsi, gcall *stmt)
>return gimple_folder (rfn.instance, rfn.decl, gsi, stmt).fold ();
> }
> +static bool
> +validate_instance_type_required_extensions (const rvv_type_info type,
> + tree exp)
> +{
> +  uint64_t exts = type.required_extensions;
> +
> +  if ((exts & RVV_REQUIRE_ELEN_FP_16) &&
> +!TARGET_VECTOR_ELEN_FP_16_P (riscv_vector_elen_flags))
> +{
> +  error_at (EXPR_LOCATION (exp),
> + "built-in function %qE requires the "
> + "zvfhmin or zvfh ISA extension",
> + exp);
> +  return false;
> +}
> +
> +  if ((exts & RVV_REQUIRE_ELEN_FP_32) &&
> +!TARGET_VECTOR_ELEN_FP_32_P (riscv_vector_elen_flags))
> +{
> +  error_at (EXPR_LOCATION (exp),
> + "built-in function %qE requires the "
> + "zve32f, zve64f, zve64d or v ISA extension",
> + exp);
> +  return false;
> +}
> +
> +  if ((exts & RVV_REQUIRE_ELEN_FP_64) &&
> +!TARGET_VECTOR_ELEN_FP_64_P (riscv_vector_elen_flags))
> +{
> +  error_at (EXPR_LOCATION (exp),
> + "built-in function %qE requires the zve64d or v ISA extension",
> + exp);
> +  return false;
> +}
> +
> +  if ((exts & RVV_REQUIRE_ELEN_64) &&
> +!TARGET_VECTOR_ELEN_64_P (riscv_vector_elen_flags))
> +{
> +  error_at (EXPR_LOCATION (exp),
> + "built-in function %qE requires the "
> + "zve64x, zve64f, zve64d or v ISA extension",
> + exp);
> +  return false;
> +}
> +
> +  return true;
> +}
> +
> /* Expand a call to the RVV function with subcode CODE.  EXP is the call
> expression and TARGET is the preferred location for the result.
> Return the value of the lhs.  */
> @@ -4649,6 +4697,9 @@ expand_builtin (unsigned int code, tree exp, rtx target)
>return target;
>  }
> +  if (!validate_instance_type_required_extensions (rfn.instance.type, exp))
> +return target;
> +
>return function_expander (rfn.instance, rfn.decl, exp, target).expand ();
> }
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c
> new file mode 100644
> index 000..b8474804c88
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-1.c
> @@ -0,0 +1,9 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +vfloat32mf2_t test_vfwsub_wf_f32mf2(vfloat32mf2_t vs2, _Float16 rs1, size_t 
> vl)
> +{
> +  return __riscv_vfwsub_wf_f32mf2(vs2, rs1, vl); /* { dg-error {built-in 
> function '__riscv_vfwsub_wf_f32mf2\(vs2,  rs1,  vl\)' requires the zvfhmin or 
> zvfh ISA extension} } */
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr114988-2.c 
> b/gcc/tes

[committed] RISC-V: Fix typos in code or comment [NFC]

[Kito Cheng]

Just found some typo when fixing bugs and then use aspell to find few
more typos, this patch didn't do anything other than fix typo.

gcc/ChangeLog:

* config/riscv/riscv-vsetvl.cc: Fix typos in comments.
(get_all_predecessors): Ditto.
(pre_vsetvl::m_unknow_info): Rename to...
(pre_vsetvl::m_unknown_info): this.
(pre_vsetvl::compute_vsetvl_def_data): Rename m_unknow_info to
m_unknown_info.
(pre_vsetvl::cleaup): Rename to...
(pre_vsetvl::cleanup): this.
(pre_vsetvl::compute_vsetvl_def_data): Fix typos.
(pass_vsetvl::lazy_vsetvl): Update function name and fix typos.
* config/riscv/riscv.cc: Fix typos in comments.
(struct machine_function): Fix typo in comments.
(riscv_valid_lo_sum_p): Ditto.
(riscv_force_address): Ditto.
(riscv_immediate_operand_p): Ditto.
(riscv_in_small_data_p): Ditto.
(riscv_first_stack_step): Ditto.
(riscv_expand_prologue): Ditto.
(riscv_convert_vector_chunks): Ditto.
(riscv_override_options_internal): Ditto.
(get_common_costs): Ditto.
---
 gcc/config/riscv/riscv-vsetvl.cc | 64 
 gcc/config/riscv/riscv.cc| 36 +-
 2 files changed, 50 insertions(+), 50 deletions(-)

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 48ce757a6ee..bbea2b5fd4f 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -95,7 +95,7 @@ using namespace riscv_vector;
It's a bit different from bitmap_union_of_preds in cfganal.cc. This function
takes into account the case where pred is ENTRY basic block. The main reason
for this difference is to make it easier to insert some special value into
-   the ENTRY base block. For example, vsetvl_info with a status of UNKNOW.  */
+   the ENTRY base block. For example, vsetvl_info with a status of UNKNOWN.  */
 static void
 bitmap_union_of_preds_with_entry (sbitmap dst, sbitmap *src, basic_block b)
 {
@@ -126,9 +126,9 @@ bitmap_union_of_preds_with_entry (sbitmap dst, sbitmap 
*src, basic_block b)
   }
 }
 
-/* Compute the reaching defintion in and out based on the gen and KILL
-   informations in each Base Blocks.
-   This function references the compute_avaiable implementation in lcm.cc  */
+/* Compute the reaching definition in and out based on the gen and KILL
+   information's in each Base Blocks.
+   This function references the compute_available implementation in lcm.cc  */
 static void
 compute_reaching_defintion (sbitmap *gen, sbitmap *kill, sbitmap *in,
sbitmap *out)
@@ -719,7 +719,7 @@ get_all_predecessors (basic_block bb)
require SEW and LMUL to be fixed.
Therefore, if the former RVV instruction needs DEMAND_RATIO_P and the latter
instruction needs DEMAND_SEW_LMUL_P and its SEW/LMUL is the same as that of
-   the former instruction, then we can make the minimu demand of the former
+   the former instruction, then we can make the minimum demand of the former
instruction strict to DEMAND_SEW_LMUL_P, and its required SEW and LMUL are
the SEW and LMUL of the latter instruction, and the vsetvl instruction
generated according to the new demand can also be used for the latter
@@ -741,7 +741,7 @@ enum demand_flags : unsigned
 /* We split the demand information into three parts. They are sew and lmul
related (sew_lmul_demand_type), tail and mask policy related
(policy_demand_type) and avl related (avl_demand_type). Then we define three
-   interfaces avaiable_with, compatible_p and merge. avaiable_with is
+   interfaces available_p, compatible_p and merge. available_p is
used to determine whether the two vsetvl infos prev_info and next_info are
available or not. If prev_info is available for next_info, it means that the
RVV insn corresponding to next_info on the path from prev_info to next_info
@@ -1361,17 +1361,17 @@ public:
 
 /* Demand system is the RVV-based VSETVL info analysis tools wrapper.
It defines compatible rules for SEW/LMUL, POLICY and AVL.
-   Also, it provides 3 iterfaces avaiable_p, compatible_p and
+   Also, it provides 3 interfaces available_p, compatible_p and
merge for the VSETVL PASS analysis and optimization.
 
- - avaiable_p: Determine whether the next info can get the
-   avaiable VSETVL status from previous info.
+ - available_p: Determine whether the next info can get the
+   available VSETVL status from previous info.
e.g. bb 2 (demand SEW = 32, LMUL = M2) -> bb 3 (demand RATIO = 16).
Since bb 2 demand info (SEW/LMUL = 32/2 = 16) satisfies the bb 3
demand, the VSETVL instruction in bb 3 can be elided.
-   avaiable_p (previous, next) is true in such situation.
+   available_p (previous, next) is true in such situation.
  - compatible_p: Determine whether prev_info is compatible with next_info
-   so that we can ha

Re: [PATCH][GCC 13] RISC-V: Fix vsetvli local eliminate [PR114747]

[Kito Cheng]

Committed to gcc 13 branch, thanks:)

On Tue, May 7, 2024 at 9:20 AM juzhe.zh...@rivai.ai
 wrote:
>
> LGTM。
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: Kito Cheng
> Date: 2024-05-07 09:17
> To: gcc-patches; kito.cheng; palmer; jeffreyalaw; rdapp; juzhe.zhong; pan2.li
> CC: Kito Cheng
> Subject: [PATCH][GCC 13] RISC-V: Fix vsetvli local eliminate [PR114747]
> vsetvli local eliminate is only consider the current demand instead of
> full demand, and it will use that incomplete info to remove vsetvli.
>
> Give following example from PR114747:
>
> vsetvli a5,a1,e8,m4,ta,mu   # 57, ratio=2, sew=8, lmul=4
> vsetvli zero,a5,e16,m8,ta,ma# 58, ratio=2, sew=16, lmul=8
> vle8.v  v8,0(a0)# 13, demand ratio=2
> vzext.vf2   v24,v8  # 14, demand sew=16 and lmul=8
>
> Insn #58 will removed because #57 has satisfied demand of #13, but it's
> not consider #14.
>
> It should doing more demand analyze, but this bug only present in GCC 13
> branch, and we should not change too much on this release branch, so the best
> way is make the check more conservative - remove only if the target
> vsetvl_discard_result having same SEW and LMUL as the source vsetvli.
>
> gcc/ChangeLog:
>
> PR target/114747
> * config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn):
> Check target vsetvl_discard_result and source vsetvli has same
> SEW and LMUL.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/vsetvl/pr114747.c: New.
> ---
> gcc/config/riscv/riscv-vsetvl.cc   | 10 ++
> .../gcc.target/riscv/rvv/vsetvl/pr114747.c | 18 ++
> 2 files changed, 28 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 587c6975a70..e6606b1e4de 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -1106,6 +1106,16 @@ local_eliminate_vsetvl_insn (const vector_insn_info 
> &dem)
>   if (!new_info.skip_avl_compatible_p (dem))
> return;
> +   /* Be more conservative here since we don't really get full
> + demand info for following instructions, also that instruction
> + isn't exist in RTL-SSA yet so we need parse that by low level
> + API rather than vector_insn_info::parse_insn, see PR114747.  */
> +   unsigned last_vsetvli_sew = ::get_sew (PREV_INSN (i->rtl ()));
> +   unsigned last_vsetvli_lmul = ::get_vlmul (PREV_INSN (i->rtl ()));
> +   if (new_info.get_sew() != last_vsetvli_sew ||
> +   new_info.get_vlmul() != last_vsetvli_lmul)
> + return;
> +
>   new_info.set_avl_info (dem.get_avl_info ());
>   new_info = dem.merge (new_info, LOCAL_MERGE);
>   change_vsetvl_insn (insn, new_info);
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c
> new file mode 100644
> index 000..c478405e8d6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c
> @@ -0,0 +1,18 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize 
> -fno-schedule-insns -fno-schedule-insns2" } */
> +
> +#include "riscv_vector.h"
> +
> +typedef unsigned short char16_t;
> +
> +size_t convert_latin1_to_utf16le(const char *src, size_t len, char16_t *dst) 
> {
> +  char16_t *beg = dst;
> +  for (size_t vl; len > 0; len -= vl, src += vl, dst += vl) {
> +vl = __riscv_vsetvl_e8m4(len);
> +vuint8m4_t v = __riscv_vle8_v_u8m4((uint8_t*)src, vl);
> +__riscv_vse16_v_u16m8((uint16_t*)dst, __riscv_vzext_vf2_u16m8(v, vl), 
> vl);
> +  }
> +  return dst - beg;
> +}
> +
> +/* { dg-final { scan-assembler 
> {vsetvli\s+[a-z0-9]+,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} } } */
> --
> 2.34.1
>
>

[PATCH][GCC 13] RISC-V: Fix vsetvli local eliminate [PR114747]

[Kito Cheng]

vsetvli local eliminate is only consider the current demand instead of
full demand, and it will use that incomplete info to remove vsetvli.

Give following example from PR114747:

vsetvli a5,a1,e8,m4,ta,mu   # 57, ratio=2, sew=8, lmul=4
vsetvli zero,a5,e16,m8,ta,ma# 58, ratio=2, sew=16, lmul=8
vle8.v  v8,0(a0)# 13, demand ratio=2
vzext.vf2   v24,v8  # 14, demand sew=16 and lmul=8

Insn #58 will removed because #57 has satisfied demand of #13, but it's
not consider #14.

It should doing more demand analyze, but this bug only present in GCC 13
branch, and we should not change too much on this release branch, so the best
way is make the check more conservative - remove only if the target
vsetvl_discard_result having same SEW and LMUL as the source vsetvli.

gcc/ChangeLog:

PR target/114747
* config/riscv/riscv-vsetvl.cc (local_eliminate_vsetvl_insn):
Check target vsetvl_discard_result and source vsetvli has same
SEW and LMUL.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/vsetvl/pr114747.c: New.
---
 gcc/config/riscv/riscv-vsetvl.cc   | 10 ++
 .../gcc.target/riscv/rvv/vsetvl/pr114747.c | 18 ++
 2 files changed, 28 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 587c6975a70..e6606b1e4de 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1106,6 +1106,16 @@ local_eliminate_vsetvl_insn (const vector_insn_info &dem)
  if (!new_info.skip_avl_compatible_p (dem))
return;
 
+ /* Be more conservative here since we don't really get full
+demand info for following instructions, also that instruction
+isn't exist in RTL-SSA yet so we need parse that by low level
+API rather than vector_insn_info::parse_insn, see PR114747.  */
+ unsigned last_vsetvli_sew = ::get_sew (PREV_INSN (i->rtl ()));
+ unsigned last_vsetvli_lmul = ::get_vlmul (PREV_INSN (i->rtl ()));
+ if (new_info.get_sew() != last_vsetvli_sew ||
+ new_info.get_vlmul() != last_vsetvli_lmul)
+   return;
+
  new_info.set_avl_info (dem.get_avl_info ());
  new_info = dem.merge (new_info, LOCAL_MERGE);
  change_vsetvl_insn (insn, new_info);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c
new file mode 100644
index 000..c478405e8d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114747.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize 
-fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+typedef unsigned short char16_t;
+
+size_t convert_latin1_to_utf16le(const char *src, size_t len, char16_t *dst) {
+  char16_t *beg = dst;
+  for (size_t vl; len > 0; len -= vl, src += vl, dst += vl) {
+vl = __riscv_vsetvl_e8m4(len);
+vuint8m4_t v = __riscv_vle8_v_u8m4((uint8_t*)src, vl);
+__riscv_vse16_v_u16m8((uint16_t*)dst, __riscv_vzext_vf2_u16m8(v, vl), vl);
+  }
+  return dst - beg;
+}
+
+/* { dg-final { scan-assembler 
{vsetvli\s+[a-z0-9]+,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} } } */
-- 
2.34.1

Re: [PATCH v2] RISC-V: Fix ICE for legitimize move on subreg const_poly_int [PR114885]

[Kito Cheng]

Hi Pan:

LGTM.

Hi Jakub:

Is this OK for GCC 14 branch? it's fix ICE on valid code, thanks :)

On Mon, Apr 29, 2024 at 3:40 PM  wrote:
>
> From: Pan Li 
>
> When we build with isl, there will be a ICE for graphite in both
> the c/c++ and fortran.  The legitimize move cannot take care of
> below rtl.
>
> (set (subreg:DI (reg:TI 237) 8) (subreg:DI (const_poly_int:TI [4, 2]) 8))
>
> Then we will have ice similar to below:
>
> internal compiler error: in extract_insn, at recog.cc:2812.
>
> This patch would like to take care of the above rtl.  Given the value of
> const_poly_int can hardly excceed the max of int64,  we can simply
> consider the highest 8 bytes of TImode is zero and then set the dest
> to (const_int 0).
>
> The below test cases are fixed by this PATCH.
>
> C:
> FAIL: gcc.dg/graphite/pr111878.c (internal compiler error: in
> extract_insn, at recog.cc:2812)
> FAIL: gcc.dg/graphite/pr111878.c (test for excess errors)
>
> Fortran:
> FAIL: gfortran.dg/graphite/vect-pr40979.f90   -O  (internal compiler
> error: in extract_insn, at recog.cc:2812)
> FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -fomit-frame-pointer
> -funroll-loops -fpeel-loops -ftracer -finline-functions  (internal
> compiler error: in extract_insn, at recog.cc:2812)
> FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -g  (test for excess
> errors)
> FAIL: gfortran.dg/graphite/pr14741.f90   -O  (test for excess errors)
> FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -fomit-frame-pointer
> -funroll-loops -fpeel-loops -ftracer -finline-functions  (test for
> excess errors)
> FAIL: gfortran.dg/graphite/vect-pr40979.f90   -O  (test for excess
> errors)
> FAIL: gfortran.dg/graphite/id-27.f90   -O  (internal compiler error: in
> extract_insn, at recog.cc:2812)
> FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -g  (internal compiler
> error: in extract_insn, at recog.cc:2812)
> FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -g  (test for excess
> errors)
> FAIL: gfortran.dg/graphite/id-27.f90   -O  (test for excess errors)
> FAIL: gfortran.dg/graphite/pr29832.f90   -O3 -fomit-frame-pointer
> -funroll-loops -fpeel-loops -ftracer -finline-functions  (test for
> excess errors)
> FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -fomit-frame-pointer
> -funroll-loops -fpeel-loops -ftracer -finline-functions  (internal
> compiler error: in extract_insn, at recog.cc:2812)
> FAIL: gfortran.dg/graphite/pr14741.f90   -O  (internal compiler error:
> in extract_insn, at recog.cc:2812)
> FAIL: gfortran.dg/graphite/pr29581.f90   -O3 -g  (internal compiler
> error: in extract_insn, at recog.cc:2812)
>
> The below test suites are passed for this patch:
> * The rv64gcv fully regression test.
> * The rv64gc fully regression test.
>
> Try to write some RTL code for test but not works well according to
> existing test cases.  Thus, take above as test cases.  Please note
> graphite require the gcc build with isl.
>
> PR target/114885
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_legitimize_subreg_const_poly_move): New
> func impl to take care of (const_int_poly:TI 8).
> (riscv_legitimize_move): Handle subreg is const_int_poly,
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv.cc | 44 +++
>  1 file changed, 44 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 0519e0679ed..0f62b295b96 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -2786,6 +2786,45 @@ riscv_v_adjust_scalable_frame (rtx target, poly_int64 
> offset, bool epilogue)
>REG_NOTES (insn) = dwarf;
>  }
>
> +/* Take care below subreg const_poly_int move:
> +
> +   1. (set (subreg:DI (reg:TI 237) 8)
> +  (subreg:DI (const_poly_int:TI [4, 2]) 8))
> +  =>
> +  (set (subreg:DI (reg:TI 237) 8)
> +  (const_int 0)) */
> +
> +static bool
> +riscv_legitimize_subreg_const_poly_move (machine_mode mode, rtx dest, rtx 
> src)
> +{
> +  gcc_assert (SUBREG_P (src) && CONST_POLY_INT_P (SUBREG_REG (src)));
> +  gcc_assert (SUBREG_BYTE (src).is_constant ());
> +
> +  int byte_offset = SUBREG_BYTE (src).to_constant ();
> +  rtx const_poly = SUBREG_REG (src);
> +  machine_mode subreg_mode = GET_MODE (const_poly);
> +
> +  if (subreg_mode != TImode) /* Only TImode is needed for now.  */
> +return false;
> +
> +  if (byte_offset == 8)
> +{
> +  /* The const_poly_int cannot exceed int64, just set zero here.  */
> +  emit_move_insn (dest, CONST0_RTX (mode));
> +  return true;
> +}
> +
> +  /* The below transform will be covered in somewhere else.
> + Thus, ignore this here.
> + (set (subreg:DI (reg:TI 237) 0)
> + (subreg:DI (const_poly_int:TI [4, 2]) 0))
> + =>
> + (set (subreg:DI (reg:TI 237) 0)
> + (const_poly_int:DI [4, 2])) */
> +
> +  return false;
> +}
> +
>  /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
> sequence that is valid.  */
>
> @@ -2839,6 +2878,11 @@ riscv_legi

Re: [PATCH v1] RISC-V: Fix ICE for legitimize move on subreg const_poly_move

[Kito Cheng]

> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 0519e0679ed..bad23ea487f 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -2786,6 +2786,44 @@ riscv_v_adjust_scalable_frame (rtx target, poly_int64 
> offset, bool epilogue)
>REG_NOTES (insn) = dwarf;
> }
> +/* Take care below subreg const_poly_int move:
> +
> +   1. (set (subreg:DI (reg:TI 237) 8)
> +(subreg:DI (const_poly_int:TI [4, 2]) 8))
> +  =>
> +  (set (subreg:DI (reg:TI 237) 8)
> +(const_int 0)) */
> +
> +static bool
> +riscv_legitimize_subreg_const_poly_move (machine_mode mode, rtx dest, rtx 
> src)
> +{
> +  gcc_assert (SUBREG_P (src) && CONST_POLY_INT_P (SUBREG_REG (src)));
> +  gcc_assert (SUBREG_BYTE (src).is_constant ());
> +
> +  int byte_offset = SUBREG_BYTE (src).to_constant ();
> +  rtx const_poly = SUBREG_REG (src);
> +  machine_mode subreg_mode = GET_MODE (const_poly);
> +
> +  if (subreg_mode != TImode) /* Only TImode is needed for now.  */
> +return false;
> +
> +  if (byte_offset == 8)
> +{ /* The const_poly_int cannot exceed int64, just set zero here.  */

{
 /* The const_poly_int cannot exceed int64, just set zero here.  */

New line for the comment.

> +  emit_move_insn (dest, CONST0_RTX (mode));
> +  return true;
> +}
> +
> +  /* The below transform will be covered in somewhere else.
> + Thus, ignore this here.
> +   1. (set (subreg:DI (reg:TI 237) 0)
> +(subreg:DI (const_poly_int:TI [4, 2]) 0))
> +  =>
> +  (set (subreg:DI (reg:TI 237) 0)
> +(const_poly_int:DI [4, 2])) */
> +
> +  return false;
> +}
> +
> /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
> sequence that is valid.  */
> @@ -2839,6 +2877,11 @@ riscv_legitimize_move (machine_mode mode, rtx dest, 
> rtx src)
> }
>return true;
>  }
> +
> +  if (SUBREG_P (src) && CONST_POLY_INT_P (SUBREG_REG (src))
> +&& riscv_legitimize_subreg_const_poly_move (mode, dest, src))
> +return true;
> +
>/* Expand
> (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))
>   Expand this data movement instead of simply forbid it since
> --
> 2.34.1
>
>

Re: [PATCH] RISC-V: Fix parsing of Zic* extensions

[Kito Cheng]

OK for trunk, and my understanding is that flag isn't really used in
code gen yet, so it's not necessary to port to GCC 14 branch?

On Mon, Apr 29, 2024 at 7:05 AM Christoph Müllner
 wrote:
>
> The extension parsing table entries for a range of Zic* extensions
> does not match the mask definition in riscv.opt.
> This results in broken TARGET_ZIC* macros, because the values of
> riscv_zi_subext and riscv_zicmo_subext are set wrong.
>
> This patch fixes this by moving Zic64b into riscv_zicmo_subext
> and all other affected Zic* extensions to riscv_zi_subext.
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc: Move ziccamoa, ziccif,
> zicclsm, and ziccrse into riscv_zi_subext.
> * config/riscv/riscv.opt: Define MASK_ZIC64B for
> riscv_ziccmo_subext.
>
> Signed-off-by: Christoph Müllner 
> ---
>  gcc/common/config/riscv/riscv-common.cc | 8 
>  gcc/config/riscv/riscv.opt  | 4 ++--
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 43b7549e3ec..8cc0e727737 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -1638,15 +1638,15 @@ static const riscv_ext_flag_table_t 
> riscv_ext_flag_table[] =
>
>{"zihintntl", &gcc_options::x_riscv_zi_subext, MASK_ZIHINTNTL},
>{"zihintpause", &gcc_options::x_riscv_zi_subext, MASK_ZIHINTPAUSE},
> +  {"ziccamoa", &gcc_options::x_riscv_zi_subext, MASK_ZICCAMOA},
> +  {"ziccif", &gcc_options::x_riscv_zi_subext, MASK_ZICCIF},
> +  {"zicclsm", &gcc_options::x_riscv_zi_subext, MASK_ZICCLSM},
> +  {"ziccrse", &gcc_options::x_riscv_zi_subext, MASK_ZICCRSE},
>
>{"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ},
>{"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM},
>{"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP},
>{"zic64b", &gcc_options::x_riscv_zicmo_subext, MASK_ZIC64B},
> -  {"ziccamoa", &gcc_options::x_riscv_zicmo_subext, MASK_ZICCAMOA},
> -  {"ziccif", &gcc_options::x_riscv_zicmo_subext, MASK_ZICCIF},
> -  {"zicclsm", &gcc_options::x_riscv_zicmo_subext, MASK_ZICCLSM},
> -  {"ziccrse", &gcc_options::x_riscv_zicmo_subext, MASK_ZICCRSE},
>
>{"zve32x",   &gcc_options::x_target_flags, MASK_VECTOR},
>{"zve32f",   &gcc_options::x_target_flags, MASK_VECTOR},
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index b14888e9816..ee824756381 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -237,8 +237,6 @@ Mask(ZIHINTPAUSE) Var(riscv_zi_subext)
>
>  Mask(ZICOND)  Var(riscv_zi_subext)
>
> -Mask(ZIC64B)  Var(riscv_zi_subext)
> -
>  Mask(ZICCAMOA)Var(riscv_zi_subext)
>
>  Mask(ZICCIF)  Var(riscv_zi_subext)
> @@ -390,6 +388,8 @@ Mask(ZICBOM) Var(riscv_zicmo_subext)
>
>  Mask(ZICBOP) Var(riscv_zicmo_subext)
>
> +Mask(ZIC64B) Var(riscv_zicmo_subext)
> +
>  TargetVariable
>  int riscv_zf_subext
>
> --
> 2.44.0
>

Re: [PATCH] RISC-V: Add -X to link spec

[Kito Cheng]

LGTM :)

Fangrui Song  於 2024年4月23日 週二 12:27 寫道：

> From: Fangrui Song 
>
> --discard-locals (-X) instructs the linker to remove local .L* symbols,
> which occur a lot due to label differences for linker relaxation. The
> arm port has a similar need and passes -X to ld.
>
> In contrast, the RISC-V port does not pass -X to ld and rely on the
> default --discard-locals in GNU ld's riscv port. The arm way is more
> conventional (compiler driver instead of the linker customizes the
> default behavior) and works with lld.
> ---
>  gcc/config/riscv/elf.h | 1 +
>  gcc/config/riscv/freebsd.h | 1 +
>  gcc/config/riscv/linux.h   | 1 +
>  3 files changed, 3 insertions(+)
>
> diff --git a/gcc/config/riscv/elf.h b/gcc/config/riscv/elf.h
> index f533764d9f8..c97f13c0cca 100644
> --- a/gcc/config/riscv/elf.h
> +++ b/gcc/config/riscv/elf.h
> @@ -20,6 +20,7 @@ along with GCC; see the file COPYING3.  If not see
>  #define LINK_SPEC "\
>  -melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv \
>  %{mno-relax:--no-relax} \
> +-X \
>  %{mbig-endian:-EB} \
>  %{mlittle-endian:-EL} \
>  %{shared}"
> diff --git a/gcc/config/riscv/freebsd.h b/gcc/config/riscv/freebsd.h
> index bd08a985285..5dd4d51c42b 100644
> --- a/gcc/config/riscv/freebsd.h
> +++ b/gcc/config/riscv/freebsd.h
> @@ -44,6 +44,7 @@ along with GCC; see the file COPYING3.  If not see
>%{p:%nconsider using `-pg' instead of `-p' with gprof (1)}   \
>%{v:-V}  \
>%{assert*} %{R*} %{rpath*} %{defsym*}\
> +  -X   \
>%{mbig-endian:-EB}   \
>%{mlittle-endian:-EL}\
>%{shared:-Bshareable %{h*} %{soname*}}   \
> diff --git a/gcc/config/riscv/linux.h b/gcc/config/riscv/linux.h
> index 15851f653bc..3c356227134 100644
> --- a/gcc/config/riscv/linux.h
> +++ b/gcc/config/riscv/linux.h
> @@ -50,6 +50,7 @@ along with GCC; see the file COPYING3.  If not see
>  #define LINK_SPEC "\
>  -melf" XLEN_SPEC DEFAULT_ENDIAN_SPEC "riscv" LD_EMUL_SUFFIX " \
>  %{mno-relax:--no-relax} \
> +-X \
>  %{mbig-endian:-EB} \
>  %{mlittle-endian:-EL} \
>  %{shared} \
> --
> 2.44.0.769.g3c40516874-goog
>
>

Re: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll

[Kito Cheng]

LGTM, thanks :)

On Thu, Apr 25, 2024 at 9:26 AM juzhe.zh...@rivai.ai
 wrote:
>
> lgtm
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: pan2.li
> Date: 2024-04-25 09:25
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; rdapp.gcc; Pan Li
> Subject: [PATCH v1] RISC-V: Add early clobber to the dest of vwsll
> From: Pan Li 
>
> We missed the existing early clobber for the dest operand of vwsll
> pattern when resolve the conflict of revert register overlap.  Thus
> add it back to the pattern.  Unfortunately, we have no test to cover
> this part and will improve this after GCC-15 open.
>
> The below tests are passed for this patch:
> * The rv64gcv fully regression test with isl build.
>
> gcc/ChangeLog:
>
> * config/riscv/vector-crypto.md: Add early clobber to the
> dest operand of vwsll.
>
> Signed-off-by: Pan Li 
> ---
> gcc/config/riscv/vector-crypto.md | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/vector-crypto.md 
> b/gcc/config/riscv/vector-crypto.md
> index 8a4888a7653..e474ddf5da7 100755
> --- a/gcc/config/riscv/vector-crypto.md
> +++ b/gcc/config/riscv/vector-crypto.md
> @@ -303,7 +303,7 @@ (define_insn "@pred_vwsll"
> (set_attr "mode" "")])
> (define_insn "@pred_vwsll_scalar"
> -  [(set (match_operand:VWEXTI 0 "register_operand"  "=vr, 
> vr")
> +  [(set (match_operand:VWEXTI 0 "register_operand"  "=&vr,
> &vr")
>   (if_then_else:VWEXTI
> (unspec:
>   [(match_operand: 1 "vector_mask_operand"   "vmWc1, 
> vmWc1")
> --
> 2.34.1
>
>

Re: [PATCH v1] RISC-V: Add xfail test case for highpart register overlap of vwcvt

[Kito Cheng]

LGTM

juzhe.zh...@rivai.ai  於 2024年4月25日 週四 09:26 寫道：

> lgtm
>
> --
> juzhe.zh...@rivai.ai
>
>
> *From:* pan2.li 
> *Date:* 2024-04-25 09:25
> *To:* gcc-patches 
> *CC:* juzhe.zhong ; kito.cheng
> ; rdapp.gcc ; Pan Li
> 
> *Subject:* [PATCH v1] RISC-V: Add xfail test case for highpart register
> overlap of vwcvt
> From: Pan Li 
>
> We reverted below patch for register group overlap, add the related
> insn test and mark it as xfail.  And we will remove the xfail
> after we support the register overlap in GCC-15.
>
> bdad036da32 RISC-V: Support highpart register overlap for vwcvt
>
> The below test suites are passed for this patch
> * The rv64gcv fully regression test with isl build.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/pr112431-1.c: New test.
> * gcc.target/riscv/rvv/base/pr112431-2.c: New test.
> * gcc.target/riscv/rvv/base/pr112431-3.c: New test.
>
> Signed-off-by: Pan Li 
> ---
> .../gcc.target/riscv/rvv/base/pr112431-1.c| 104 ++
> .../gcc.target/riscv/rvv/base/pr112431-2.c|  68 
> .../gcc.target/riscv/rvv/base/pr112431-3.c|  51 +
> 3 files changed, 223 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c
>
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c
> new file mode 100644
> index 000..6f9c6f7bd8c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c
> @@ -0,0 +1,104 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
> +
> +#include "riscv_vector.h"
> +
> +size_t __attribute__ ((noinline))
> +sumation (size_t sum0, size_t sum1, size_t sum2, size_t sum3, size_t sum4,
> +   size_t sum5, size_t sum6, size_t sum7, size_t sum8, size_t sum9,
> +   size_t sum10, size_t sum11, size_t sum12, size_t sum13, size_t sum14,
> +   size_t sum15)
> +{
> +  return sum0 + sum1 + sum2 + sum3 + sum4 + sum5 + sum6 + sum7 + sum8 +
> sum9
> + + sum10 + sum11 + sum12 + sum13 + sum14 + sum15;
> +}
> +
> +size_t
> +foo (char const *buf, size_t len)
> +{
> +  size_t sum = 0;
> +  size_t vl = __riscv_vsetvlmax_e8m8 ();
> +  size_t step = vl * 4;
> +  const char *it = buf, *end = buf + len;
> +  for (; it + step <= end;)
> +{
> +  vint8m1_t v0 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v1 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v2 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v3 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v4 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v5 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v6 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v7 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v8 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v9 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v10 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v11 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v12 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v13 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v14 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +  vint8m1_t v15 = __riscv_vle8_v_i8m1 ((void *) it, vl);
> +  it += vl;
> +
> +  asm volatile("nop" ::: "memory");
> +  vint16m2_t vw0 = __riscv_vwcvt_x_x_v_i16m2 (v0, vl);
> +  vint16m2_t vw1 = __riscv_vwcvt_x_x_v_i16m2 (v1, vl);
> +  vint16m2_t vw2 = __riscv_vwcvt_x_x_v_i16m2 (v2, vl);
> +  vint16m2_t vw3 = __riscv_vwcvt_x_x_v_i16m2 (v3, vl);
> +  vint16m2_t vw4 = __riscv_vwcvt_x_x_v_i16m2 (v4, vl);
> +  vint16m2_t vw5 = __riscv_vwcvt_x_x_v_i16m2 (v5, vl);
> +  vint16m2_t vw6 = __riscv_vwcvt_x_x_v_i16m2 (v6, vl);
> +  vint16m2_t vw7 = __riscv_vwcvt_x_x_v_i16m2 (v7, vl);
> +  vint16m2_t vw8 = __riscv_vwcvt_x_x_v_i16m2 (v8, vl);
> +  vint16m2_t vw9 = __riscv_vwcvt_x_x_v_i16m2 (v9, vl);
> +  vint16m2_t vw10 = __riscv_vwcvt_x_x_v_i16m2 (v10, vl);
> +  vint16m2_t vw11 = __riscv_vwcvt_x_x_v_i16m2 (v11, vl);
> +  vint16m2_t vw12 = __riscv_vwcvt_x_x_v_i16m2 (v12, vl);
> +  vint16m2_t vw13 = __riscv_vwcvt_x_x_v_i16m2 (v13, vl);
> +  vint16m2_t vw14 = __riscv_vwcvt_x_x_v_i16m2 (v14, vl);
> +  vint16m2_t vw15 = __riscv_vwcvt_x_x_v_i16m2 (v15, vl);
> +
> +  asm volatile("nop" ::: "memory");
> +  size_t sum0 = __riscv_vmv_x_s_i16m2_i16 (vw0);
> +  size_t sum1 = __riscv_vmv_x_s_i16m2_i16 (vw1);
>

Re: [PATCH][GCC 13] RISC-V: Fix recursive vsetvli checking [PR114172]

[Kito Cheng]

thanks, committed :)

On Wed, Apr 24, 2024 at 6:12 PM juzhe.zh...@rivai.ai
 wrote:
>
> lgtm.
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: Kito Cheng
> Date: 2024-04-24 18:09
> To: gcc-patches; kito.cheng; rdapp; juzhe.zhong
> CC: Kito Cheng
> Subject: [PATCH][GCC 13] RISC-V: Fix recursive vsetvli checking [PR114172]
> extract_single_source will recursive checking the sources to
> make sure if it's single source, however it may cause infinite
> recursive when the source is come from itself, so it should just skip
> first source to prevent that.
>
> NOTE: This logic has existing on trunk/GCC 14, but it included in a big
> vsetvli improvement patch, which is not backport to GCC 13.
>
> ```
>
> void saxpy_rvv_m8(float *y, long vl)
> {
> for (;;)
> {
> vl = __riscv_vsetvl_e32m8(vl); //ICE
> vfloat32m8_t y_vec;
> __riscv_vse32_v_f32m8(y, y_vec, vl);
> }
> }
> ```
>
> gcc/ChangeLog:
>
> PR target/114172
> * gcc/config/riscv/riscv-vsetvl.cc (extract_single_source):
> Skip first set.
>
> gcc/testsuite/ChangeLog:
>
> PR target/114172
> * gcc.target/riscv/rvv/vsetvl/pr114172.c: New.
> ---
> gcc/config/riscv/riscv-vsetvl.cc   |  4 
> .../gcc.target/riscv/rvv/vsetvl/pr114172.c | 14 ++
> 2 files changed, 18 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c
>
> diff --git a/gcc/config/riscv/riscv-vsetvl.cc 
> b/gcc/config/riscv/riscv-vsetvl.cc
> index 9dca2ce709d..36d2e6e6f20 100644
> --- a/gcc/config/riscv/riscv-vsetvl.cc
> +++ b/gcc/config/riscv/riscv-vsetvl.cc
> @@ -1196,6 +1196,10 @@ extract_single_source (set_info *set)
>  return nullptr;
>for (const set_info *set : sets)
>  {
> +  /* Skip first set, this can prevent us run into infinite recursive
> + checking if first set is come from itself.  */
> +  if (set == *sets.begin ())
> + continue;
>/* If there is a head or end insn, we conservative return
> NULL so that VSETVL PASS will insert vsetvl directly.  */
>if (set->insn ()->is_artificial ())
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c 
> b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c
> new file mode 100644
> index 000..ed1494666d6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -fno-tree-vectorize" } */
> +
> +#include "riscv_vector.h"
> +
> +void e(long, vfloat32m4_t);
> +
> +void b(long c) {
> +  for (;;) {
> +c = __riscv_vsetvl_e32m4(c);
> +vfloat32m4_t d;
> +e(c, d);
> +  }
> +}
> --
> 2.34.1
>
>

Re: [PATCH v1] Revert "RISC-V: Support highpart register overlap for vwcvt"

[Kito Cheng]

LGTM, thanks Pan, although the revert patch series look a little bit
scary, but I believe it's the safest way for now since we don't really
fully understand how register filters work, and it's not really good
timing to figure out all the detail around that.

On Wed, Apr 24, 2024 at 9:02 PM Li, Pan2  wrote:
>
> Request review as this revert patch contains some manually resolved conflict 
> changes.
>
> Passed the rv64gcv fully regression test with isl build.
>
> Pan
>
> -Original Message-
> From: Li, Pan2 
> Sent: Wednesday, April 24, 2024 8:59 PM
> To: gcc-patches@gcc.gnu.org
> Cc: juzhe.zh...@rivai.ai; kito.ch...@gmail.com; rdapp@gmail.com; Li, Pan2 
> 
> Subject: [PATCH v1] Revert "RISC-V: Support highpart register overlap for 
> vwcvt"
>
> From: Pan Li 
>
> This reverts commit bdad036da32f72b84a96070518e7d75c21706dc2.
> ---
>  gcc/config/riscv/constraints.md   |  23 
>  gcc/config/riscv/riscv.md |  24 
>  gcc/config/riscv/vector-crypto.md |  21 ++--
>  gcc/config/riscv/vector.md|  19 ++--
>  .../gcc.target/riscv/rvv/base/pr112431-1.c| 104 --
>  .../gcc.target/riscv/rvv/base/pr112431-2.c|  68 
>  .../gcc.target/riscv/rvv/base/pr112431-3.c|  51 -
>  .../gcc.target/riscv/rvv/base/pr112431-39.c   |   2 +-
>  .../gcc.target/riscv/rvv/base/pr112431-40.c   |   2 +-
>  .../gcc.target/riscv/rvv/base/pr112431-41.c   |   2 +-
>  10 files changed, 22 insertions(+), 294 deletions(-)
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-1.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-2.c
>  delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112431-3.c
>
> diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
> index e37c6936bfa..a590df545d7 100644
> --- a/gcc/config/riscv/constraints.md
> +++ b/gcc/config/riscv/constraints.md
> @@ -159,29 +159,6 @@ (define_register_constraint "vd" "TARGET_VECTOR ? 
> VD_REGS : NO_REGS"
>  (define_register_constraint "vm" "TARGET_VECTOR ? VM_REGS : NO_REGS"
>"A vector mask register (if available).")
>
> -;; These following constraints are used by RVV instructions with dest EEW > 
> src EEW.
> -;; RISC-V 'V' Spec 5.2. Vector Operands:
> -;; The destination EEW is greater than the source EEW, the source EMUL is at 
> least 1,
> -;; and the overlap is in the highest-numbered part of the destination 
> register group.
> -;; (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or 
> v4 is not).
> -(define_register_constraint "W21" "TARGET_VECTOR ? V_REGS : NO_REGS"
> -  "A vector register has register number % 2 == 1." "regno % 2 == 1")
> -
> -(define_register_constraint "W42" "TARGET_VECTOR ? V_REGS : NO_REGS"
> -  "A vector register has register number % 4 == 2." "regno % 4 == 2")
> -
> -(define_register_constraint "W84" "TARGET_VECTOR ? V_REGS : NO_REGS"
> -  "A vector register has register number % 8 == 4." "regno % 8 == 4")
> -
> -(define_register_constraint "W41" "TARGET_VECTOR ? V_REGS : NO_REGS"
> -  "A vector register has register number % 4 == 1." "regno % 4 == 1")
> -
> -(define_register_constraint "W81" "TARGET_VECTOR ? V_REGS : NO_REGS"
> -  "A vector register has register number % 8 == 1." "regno % 8 == 1")
> -
> -(define_register_constraint "W82" "TARGET_VECTOR ? V_REGS : NO_REGS"
> -  "A vector register has register number % 8 == 2." "regno % 8 == 2")
> -
>  ;; This constraint is used to match instruction "csrr %0, vlenb" which is 
> generated in "mov".
>  ;; VLENB is a run-time constant which represent the vector register length 
> in bytes.
>  ;; BYTES_PER_RISCV_VECTOR represent runtime invariant of vector register 
> length in bytes.
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 1693d4008c6..455715ab2f7 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -538,27 +538,6 @@ (define_attr "fp_vector_disabled" "no,yes"
>]
>(const_string "no")))
>
> -(define_attr "vconstraint" "no,W21,W42,W84,W41,W81,W82"
> -  (const_string "no"))
> -
> -(define_attr "vconstraint_enabled" "no,yes"
> -  (cond [(eq_attr "vconstraint" "no")
> - (const_string "yes")
> -
> - (and (eq_attr "vconstraint" "W21")
> - (match_test "riscv_get_v_regno_alignment (GET_MODE 
> (operands[0])) != 2"))
> -(const_string "no")
> -
> - (and (eq_attr "vconstraint" "W42,W41")
> - (match_test "riscv_get_v_regno_alignment (GET_MODE 
> (operands[0])) != 4"))
> -(const_string "no")
> -
> - (and (eq_attr "vconstraint" "W84,W81,W82")
> - (match_test "riscv_get_v_regno_alignment (GET_MODE 
> (operands[0])) != 8"))
> -(const_string "no")
> -]
> -   (const_string "yes")))
> -
>  ;; This attribute marks the alternatives not matching the constraints
>  ;; described in spec as disabled.
>  (define_attr "spec_restriction" "none,thv,r

[PATCH][GCC 13] RISC-V: Fix recursive vsetvli checking [PR114172]

[Kito Cheng]

extract_single_source will recursive checking the sources to
make sure if it's single source, however it may cause infinite
recursive when the source is come from itself, so it should just skip
first source to prevent that.

NOTE: This logic has existing on trunk/GCC 14, but it included in a big
vsetvli improvement patch, which is not backport to GCC 13.

```

void saxpy_rvv_m8(float *y, long vl)
{
for (;;)
{
vl = __riscv_vsetvl_e32m8(vl); //ICE
vfloat32m8_t y_vec;
__riscv_vse32_v_f32m8(y, y_vec, vl);
}
}
```

gcc/ChangeLog:

PR target/114172
* gcc/config/riscv/riscv-vsetvl.cc (extract_single_source):
Skip first set.

gcc/testsuite/ChangeLog:

PR target/114172
* gcc.target/riscv/rvv/vsetvl/pr114172.c: New.
---
 gcc/config/riscv/riscv-vsetvl.cc   |  4 
 .../gcc.target/riscv/rvv/vsetvl/pr114172.c | 14 ++
 2 files changed, 18 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 9dca2ce709d..36d2e6e6f20 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1196,6 +1196,10 @@ extract_single_source (set_info *set)
 return nullptr;
   for (const set_info *set : sets)
 {
+  /* Skip first set, this can prevent us run into infinite recursive
+checking if first set is come from itself.  */
+  if (set == *sets.begin ())
+   continue;
   /* If there is a head or end insn, we conservative return
 NULL so that VSETVL PASS will insert vsetvl directly.  */
   if (set->insn ()->is_artificial ())
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c 
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c
new file mode 100644
index 000..ed1494666d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr114172.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -fno-tree-vectorize" } */
+
+#include "riscv_vector.h"
+
+void e(long, vfloat32m4_t);
+
+void b(long c) {
+  for (;;) {
+c = __riscv_vsetvl_e32m4(c);
+vfloat32m4_t d;
+e(c, d);
+  }
+}
-- 
2.34.1

Re: [PATCH] [RISC-V] optimize Zicond conditional select cases.

[Kito Cheng]

It's simple enough, so LGTM for trunk :)

Fei Gao  於 2024年4月15日 週一 14:38 寫道：

> When one of the two input operands is 0, ADD and IOR are functionally
> equivalent.
> ADD is slightly preferred over IOR because ADD has a higher likelihood
> of being implemented as a compressed instruction when compared to IOR.
> C.ADD uses the CR format with any of the 32 RVI registers availble,
> while C.OR uses the CA format with limit to just 8 of them.
>
> Conditional select, if zero case:
> rd = (rc == 0) ? rs1 : rs2
>
> before patch:
>
>   czero.nez rd, rs1, rc
>   czero.eqz rtmp, rs2, rc
>   or rd, rd, rtmp
>
> after patch:
>
>   czero.eqz rd, rs1, rc
>   czero.nez rtmp, rs2, rc
>   add rd, rd, rtmp
>
> Same trick applies for the conditional select, if non-zero case:
> rd = (rc != 0) ? rs1 : rs2
>
> riscv-gnu-toolchain regression tests have been passed with no new failure.
> ---
>  gcc/config/riscv/riscv.cc|  2 +-
>  .../gcc.target/riscv/zicond-prefer-add-to-or.c   | 16 
>  2 files changed, 17 insertions(+), 1 deletion(-)
>  create mode 100644
> gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index e5f00806bb9..93c736549c9 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -4709,7 +4709,7 @@ riscv_expand_conditional_move (rtx dest, rtx op, rtx
> cons, rtx alt)
>   gen_rtx_IF_THEN_ELSE (mode, cond1,
> CONST0_RTX (mode),
> alt)));
> - riscv_emit_binary (IOR, dest, reg1, reg2);
> + riscv_emit_binary (PLUS, dest, reg1, reg2);
>   return true;
> }
>  }
> diff --git a/gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c
> b/gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c
> new file mode 100644
> index 000..f3f7beb0b5e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/zicond-prefer-add-to-or.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gc_zicond -mabi=lp64d -mbranch-cost=4" {
> target { rv64 } } } */
> +/* { dg-options "-march=rv32gc_zicond -mabi=ilp32f -mbranch-cost=4" {
> target { rv32 } } } */
> +/* { dg-skip-if "" { *-*-* } {"-O0" "-Og" "-Os" "-Oz"} } */
> +
> +long cond_select_if_zero(long a, long b, long c) {
> +  return a == 0 ? c : b;
> +}
> +
> +long cond_select_if_non_zero(long a, long b, long c) {
> +  return a != 0 ? c : b;
> +}
> +
> +/* { dg-final { scan-assembler-times {add\t}  2 } } */
> +/* { dg-final { scan-assembler-not {or\t} } } */
> +
> --
> 2.17.1
>
>

Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in TARGET_FUNCTION_VALUE_REGNO_P

[Kito Cheng]

Does FP reg also need gurared with TARGET_HARD_FLOAT? could you try to
compile that case without F?

On Fri, Apr 12, 2024 at 2:19 PM Li, Pan2  wrote:
>
> Committed, thanks Juzhe.
>
>
>
> Pan
>
>
>
> From: juzhe.zh...@rivai.ai 
> Sent: Friday, April 12, 2024 2:11 PM
> To: Li, Pan2 ; gcc-patches 
> Cc: kito.cheng ; Li, Pan2 
> Subject: Re: [PATCH v1] RISC-V: Bugfix ICE non-vector in 
> TARGET_FUNCTION_VALUE_REGNO_P
>
>
>
> LGTM。
>
>
>
> 
>
> juzhe.zh...@rivai.ai
>
>
>
> From: pan2.li
>
> Date: 2024-04-12 14:08
>
> To: gcc-patches
>
> CC: juzhe.zhong; kito.cheng; Pan Li
>
> Subject: [PATCH v1] RISC-V: Bugfix ICE non-vector in 
> TARGET_FUNCTION_VALUE_REGNO_P
>
> From: Pan Li 
>
>
>
> This patch would like to fix one ICE when vector is not enabled
>
> in hook TARGET_FUNCTION_VALUE_REGNO_P implementation.  The vector
>
> regno is available if and only if the TARGET_VECTOR is true.  The
>
> previous implement missed this condition and then result in ICE
>
> when rv64gc build option without vector.
>
>
>
> PR target/114639
>
>
>
> The below test suite is passed for this patch.
>
>
>
> * The rv64gcv fully regression tests.
>
> * The rv64gc fully regression tests.
>
>
>
> gcc/ChangeLog:
>
>
>
> * config/riscv/riscv.cc (riscv_function_value_regno_p): Add
>
> TARGET_VECTOR predicate for V_RETURN regno.
>
>
>
> gcc/testsuite/ChangeLog:
>
>
>
> * gcc.target/riscv/pr114639-1.c: New test.
>
> * gcc.target/riscv/pr114639-2.c: New test.
>
> * gcc.target/riscv/pr114639-3.c: New test.
>
> * gcc.target/riscv/pr114639-4.c: New test.
>
>
>
> Signed-off-by: Pan Li 
>
> ---
>
> gcc/config/riscv/riscv.cc   |  2 +-
>
> gcc/testsuite/gcc.target/riscv/pr114639-1.c | 11 +++
>
> gcc/testsuite/gcc.target/riscv/pr114639-2.c | 11 +++
>
> gcc/testsuite/gcc.target/riscv/pr114639-3.c | 11 +++
>
> gcc/testsuite/gcc.target/riscv/pr114639-4.c | 11 +++
>
> 5 files changed, 45 insertions(+), 1 deletion(-)
>
> create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-1.c
>
> create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-2.c
>
> create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-3.c
>
> create mode 100644 gcc/testsuite/gcc.target/riscv/pr114639-4.c
>
>
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
>
> index 91f017dd52a..e5f00806bb9 100644
>
> --- a/gcc/config/riscv/riscv.cc
>
> +++ b/gcc/config/riscv/riscv.cc
>
> @@ -11008,7 +11008,7 @@ riscv_function_value_regno_p (const unsigned regno)
>
>if (FP_RETURN_FIRST <= regno && regno <= FP_RETURN_LAST)
>
>  return true;
>
> -  if (regno == V_RETURN)
>
> +  if (TARGET_VECTOR && regno == V_RETURN)
>
>  return true;
>
>return false;
>
> diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-1.c 
> b/gcc/testsuite/gcc.target/riscv/pr114639-1.c
>
> new file mode 100644
>
> index 000..f41723193a4
>
> --- /dev/null
>
> +++ b/gcc/testsuite/gcc.target/riscv/pr114639-1.c
>
> @@ -0,0 +1,11 @@
>
> +/* Test that we do not have ice when compile */
>
> +/* { dg-do compile } */
>
> +/* { dg-options "-march=rv64gc -mabi=lp64d -std=gnu89 -O3" } */
>
> +
>
> +g (a, b) {}
>
> +
>
> +f (xx)
>
> + void* xx;
>
> +{
>
> +  __builtin_apply ((void*)g, xx, 200);
>
> +}
>
> diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-2.c 
> b/gcc/testsuite/gcc.target/riscv/pr114639-2.c
>
> new file mode 100644
>
> index 000..0c402c4b254
>
> --- /dev/null
>
> +++ b/gcc/testsuite/gcc.target/riscv/pr114639-2.c
>
> @@ -0,0 +1,11 @@
>
> +/* Test that we do not have ice when compile */
>
> +/* { dg-do compile } */
>
> +/* { dg-options "-march=rv64imac -mabi=lp64 -std=gnu89 -O3" } */
>
> +
>
> +g (a, b) {}
>
> +
>
> +f (xx)
>
> + void* xx;
>
> +{
>
> +  __builtin_apply ((void*)g, xx, 200);
>
> +}
>
> diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-3.c 
> b/gcc/testsuite/gcc.target/riscv/pr114639-3.c
>
> new file mode 100644
>
> index 000..ffb0d6d162d
>
> --- /dev/null
>
> +++ b/gcc/testsuite/gcc.target/riscv/pr114639-3.c
>
> @@ -0,0 +1,11 @@
>
> +/* Test that we do not have ice when compile */
>
> +/* { dg-do compile } */
>
> +/* { dg-options "-march=rv32gc -mabi=ilp32d -std=gnu89 -O3" } */
>
> +
>
> +g (a, b) {}
>
> +
>
> +f (xx)
>
> + void* xx;
>
> +{
>
> +  __builtin_apply ((void*)g, xx, 200);
>
> +}
>
> diff --git a/gcc/testsuite/gcc.target/riscv/pr114639-4.c 
> b/gcc/testsuite/gcc.target/riscv/pr114639-4.c
>
> new file mode 100644
>
> index 000..a6e229101ef
>
> --- /dev/null
>
> +++ b/gcc/testsuite/gcc.target/riscv/pr114639-4.c
>
> @@ -0,0 +1,11 @@
>
> +/* Test that we do not have ice when compile */
>
> +/* { dg-do compile } */
>
> +/* { dg-options "-march=rv32imac -mabi=ilp32 -std=gnu89 -O3" } */
>
> +
>
> +g (a, b) {}
>
> +
>
> +f (xx)
>
> + void* xx;
>
> +{
>
> +  __builtin_apply ((void*)g, xx, 200);
>
> +}
>
> --
>
> 2.34.1
>
>
>
>

Re: [PATCH] wwwdocs: gcc-14: Add RISC-V changes

[Kito Cheng]

Committed with fixes, thanks :)

On Thu, Apr 11, 2024 at 12:18 AM Palmer Dabbelt  wrote:

> On Wed, 10 Apr 2024 00:58:00 PDT (-0700), kito.ch...@sifive.com wrote:
> > ---
> >  htdocs/gcc-14/changes.html | 155 -
> >  1 file changed, 154 insertions(+), 1 deletion(-)
> >
> > diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
> > index 2d8968cf..6cbb2e8f 100644
> > --- a/htdocs/gcc-14/changes.html
> > +++ b/htdocs/gcc-14/changes.html
> > @@ -739,7 +739,160 @@ __asm (".global __flmap_lock"  "\n\t"
> >
> >  
> >
> > -
> > +RISC-V
> > +
> > +  The SLP and loop vectorizer is now enabled for RISC-V when the
> vector
>
> I think "are now enabled"?
>
> > +  extension is enabled, thanks to Ju-Zhe Zhong from
> > +  RiVAI,
> > +  Pan Li from Intel, and
> Robin Dapp
> > +  from Ventana Micro
> for
> > +  contributing most of the implementation!
> > +  The -mrvv-max-lmul= option has been introduced for
> > +  performance tuning of the loop vectorizer. The default value is
> > +  -mrvv-max-lmul=m1, which limits the maximum LMUL to
> 1.
> > +  The -mrvv-max-lmul=dynamic setting can dynamically
> select
> > +  the maximum LMUL value based on register pressure.
> > +  Atomic code generation has been improved and is now in
> conformance with
> > +  the latest psABI specification, thanks to Patrick O'Neill from
> > +  Rivos.
> > +  Support for the vector intrinsics as specified in
> > +  
> > +  version 1.0 of the RISC-V vector intrinsic specification.
> > +  Support for the experimental vector crypto intrinsics as
> specified in
> > +  
> > +  RISC-V vector intrinsic specification, thanks to Feng Wang et
> al.
> > +  from https://eswincomputing.com/";>ESWIN
> Computing
> > +  Support for the T-head vector intrinsics.
> > +  Support for the scalar bitmanip and scalar crypto  intrinsics,
> thanks to
> > +  Liao Shihua from https://plctlab.org/";>PLCT.
> > +  Support for the large code model via option
> -mcmodel=large,
> > +  thanks to Kuan-Lin Chen from
> > +  https://www.andestech.com/";>Andes Technology.
> > +  Support for the standard vector calling convention variant,
> thanks to
> > +  Lehua Ding from RiVAI.
> > +  Supports the target attribute, which allows users to
> compile
> > +  a function with specific extensions.
> > +  -march= option no longer requires the architecture
> string
> > +  to be in canonical order, with only a few constraints remaining:
> the
> > +  architecture string must start with
> rv[32|64][i|g|e], and
> > +  must use an underscore as the separator after a multi-letter
> extension.
> > +  
> > +  -march=help option has been introduced to dump all
> > +  supported extensions.
> > +  Added experimental support for the
> -mrvv-vector-bits=zvl
> > +  option and the riscv_rvv_vector_bits attribute, which
> > +  specify a fixed length for scalable vector types. This option is
> > +  optimized for specific vector core implementations; however, the
> code
> > +  generated with this option is NOT portable,
>
> IIUC the code is just optimized for a specific vector length, not any
> specific core.  It's portable to other cores, just not portable to cores
> with different vector lengths.
>
> So I think we can soften the language a bit there, as it's not like
> we're emitting vendor-specific code on this one.
>
> > +  thanks to Pan Li from https://www.intel.com/";>Intel.
> > +  
> > +  Support for TLS descriptors has been introduced, which can be
> enabled by
> > +  the -mtls-dialect=desc option. The default behavior
> can be
> > +  configured with --with-tls=[trad|desc].
> > +  Support for the TLS descriptors, this can be enabled by
> > +  -mtls-dialect=desc and the default behavior can be
> configure
> > +  by --with-tls=[trad|desc], thanks to Tatsuyuki Ishi from
> > +  https://bluewhale.systems/";>Blue Whale
> Systems
>
> Maybe should call out that this will require the next glibc release to
> function correctly?
>
> > +  
> > +  Support for the following standard extensions has been added:
> > +
> > +  Vector crypto extensions:
> > + 
> > +   Zvbb
> > +   Zvkb
> > +   Zvbc
> > +   Zvkg
> > +   Zvkned
> > +   Zvkhna
> > +   Zvkhnb
> > +   Zvksed
> > +   Zvksh
> > +   Zvkn
> > +   Zvknc
> > +   Zvkng
> > +   Zvks
> > +   Zvksc
> > +   Zvksg
> > +   Zvkt
> > + 
> > +  
> > +  Code size reduction extensions:
> > + 
> > +   Zca
> > +   Zcb
> > +   Zce
> > +   Zcf
> > +   Zcd
> > +   Zcmp
> > +   Zcmt
> > + 
> > +  
> > +  Zicond
> > +  Zfa
> > +  Ztso
> > +  Zvfbfmin
> > +  Zvfhmin
> > +  Zvfh
> > +  Za64rs
> > +  Za128rs
> > +  Ziccif
> > +  Ziccrse
> > +  Ziccamoa
> > +  Zicclsm
> > +  Zic64b
> > +  Smaia
> > +  Smepmp
> > +  Smst

Re: [PATCH v1] RISC-V: Bugfix ICE for the vector return arg in mode switch

[Kito Cheng]

I was thinking we may guarded with TARGET_VECTOR and TARGET_HARD_FLOAT
or checking with ABI in riscv_function_value_regno_p, however I think
it's fine with current implementation (no checking) after checking all
use site of `targetm.calls.function_value_regno_p`, so LGTM :)

Thanks Pan for fixing this issue!

On Thu, Apr 11, 2024 at 10:23 AM juzhe.zh...@rivai.ai
 wrote:
>
> Thanks for fixing it. LGTM from my side.
>
> I prefer wait kito for another ACK.
>
> 
> juzhe.zh...@rivai.ai
>
>
> From: pan2.li
> Date: 2024-04-11 10:16
> To: gcc-patches
> CC: juzhe.zhong; kito.cheng; Pan Li
> Subject: [PATCH v1] RISC-V: Bugfix ICE for the vector return arg in mode 
> switch
> From: Pan Li 
>
> This patch would like to fix a ICE in mode sw for below example code.
>
> during RTL pass: mode_sw
> test.c: In function ‘vbool16_t j(vuint64m4_t)’:
> test.c:15:1: internal compiler error: in create_pre_exit, at
> mode-switching.cc:451
>15 | }
>   | ^
> 0x3978f12 create_pre_exit
> __RISCV_BUILD__/../gcc/mode-switching.cc:451
> 0x3979e9e optimize_mode_switching
> __RISCV_BUILD__/../gcc/mode-switching.cc:849
> 0x397b9bc execute
> __RISCV_BUILD__/../gcc/mode-switching.cc:1324
>
> extern size_t get_vl ();
>
> vbool16_t
> test (vuint64m4_t a)
> {
>   unsigned long b;
>   return __riscv_vmsne_vx_u64m4_b16 (a, b, get_vl ());
> }
>
> The create_pre_exit would like to find a return value copy.  If
> not, there will be a reason in assert but not available for above
> sample code when vector calling convension is enabled by default.
> This patch would like to override the TARGET_FUNCTION_VALUE_REGNO_P
> for vector register and then we will have hard_regno_nregs for copy_num,
> aka there is a return value copy.
>
> As a side-effect of allow vector in TARGET_FUNCTION_VALUE_REGNO_P, the
> TARGET_GET_RAW_RESULT_MODE will have vector mode and which is sizeless
> cannot be converted to fixed_size_mode.  Thus override the hook
> TARGET_GET_RAW_RESULT_MODE and return VOIDmode when the regno is-not-a
> fixed_size_mode.
>
> The below tests are passed for this patch.
> * The fully riscv regression tests.
> * The reproducing test in bugzilla PR114639.
>
> PR target/114639
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_function_value_regno_p): New func
> impl for hook TARGET_FUNCTION_VALUE_REGNO_P.
> (riscv_get_raw_result_mode): New func imple for hook
> TARGET_GET_RAW_RESULT_MODE.
> (TARGET_FUNCTION_VALUE_REGNO_P): Impl the hook.
> (TARGET_GET_RAW_RESULT_MODE): Ditto.
> * config/riscv/riscv.h (V_RETURN): New macro for vector return.
> (GP_RETURN_FIRST): New macro for the first GPR in return.
> (GP_RETURN_LAST): New macro for the last GPR in return.
> (FP_RETURN_FIRST): Diito but for FPR.
> (FP_RETURN_LAST): Ditto.
> (FUNCTION_VALUE_REGNO_P): Remove as deprecated and replace by
> TARGET_FUNCTION_VALUE_REGNO_P.
>
> gcc/testsuite/ChangeLog:
>
> * g++.target/riscv/rvv/base/pr114639-1.C: New test.
> * gcc.target/riscv/rvv/base/pr114639-1.c: New test.
>
> Signed-off-by: Pan Li 
> ---
> gcc/config/riscv/riscv.cc | 34 +++
> gcc/config/riscv/riscv.h  |  8 +++--
> .../g++.target/riscv/rvv/base/pr114639-1.C| 25 ++
> .../gcc.target/riscv/rvv/base/pr114639-1.c| 14 
> 4 files changed, 79 insertions(+), 2 deletions(-)
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/pr114639-1.C
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr114639-1.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 00defa69fd8..91f017dd52a 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -10997,6 +10997,34 @@ riscv_vector_mode_supported_any_target_p 
> (machine_mode)
>return true;
> }
> +/* Implements hook TARGET_FUNCTION_VALUE_REGNO_P.  */
> +
> +static bool
> +riscv_function_value_regno_p (const unsigned regno)
> +{
> +  if (GP_RETURN_FIRST <= regno && regno <= GP_RETURN_LAST)
> +return true;
> +
> +  if (FP_RETURN_FIRST <= regno && regno <= FP_RETURN_LAST)
> +return true;
> +
> +  if (regno == V_RETURN)
> +return true;
> +
> +  return false;
> +}
> +
> +/* Implements hook TARGET_GET_RAW_RESULT_MODE.  */
> +
> +static fixed_size_mode
> +riscv_get_raw_result_mode (int regno)
> +{
> +  if (!is_a  (reg_raw_mode[regno]))
> +return as_a  (VOIDmode);
> +
> +  return default_get_reg_raw_mode (regno);
> +}
> +
> /* Initialize the GCC target structure.  */
> #undef TARGET_ASM_ALIGNED_HI_OP
> #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
> @@ -11343,6 +11371,12 @@ riscv_vector_mode_supported_any_target_p 
> (machine_mode)
> #undef TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P
> #define TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P 
> riscv_vector_mode_supported_any_target_p
> +#undef TARGET_FUNCTION_VALUE_REGNO_P
> +#define TARGET_FUNCTION_VALUE_REGNO_P riscv_function_value_regno_p
> +
> +#undef TARGET_GET_RAW_RESULT_MODE
> +#define TARGET_GET_RAW_RESULT

[PATCH] wwwdocs: gcc-14: Add RISC-V changes

[Kito Cheng]

---
 htdocs/gcc-14/changes.html | 155 -
 1 file changed, 154 insertions(+), 1 deletion(-)

diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 2d8968cf..6cbb2e8f 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -739,7 +739,160 @@ __asm (".global __flmap_lock"  "\n\t"
 
 
 
-
+RISC-V
+
+  The SLP and loop vectorizer is now enabled for RISC-V when the vector
+  extension is enabled, thanks to Ju-Zhe Zhong from
+  RiVAI,
+  Pan Li from Intel, and Robin Dapp
+  from Ventana Micro for
+  contributing most of the implementation!
+  The -mrvv-max-lmul= option has been introduced for
+  performance tuning of the loop vectorizer. The default value is
+  -mrvv-max-lmul=m1, which limits the maximum LMUL to 1.
+  The -mrvv-max-lmul=dynamic setting can dynamically select
+  the maximum LMUL value based on register pressure.
+  Atomic code generation has been improved and is now in conformance with
+  the latest psABI specification, thanks to Patrick O'Neill from
+  Rivos.
+  Support for the vector intrinsics as specified in
+  
+  version 1.0 of the RISC-V vector intrinsic specification.
+  Support for the experimental vector crypto intrinsics as specified in
+  
+  RISC-V vector intrinsic specification, thanks to Feng Wang et al.
+  from https://eswincomputing.com/";>ESWIN Computing
+  Support for the T-head vector intrinsics.
+  Support for the scalar bitmanip and scalar crypto  intrinsics, thanks to
+  Liao Shihua from https://plctlab.org/";>PLCT.
+  Support for the large code model via option -mcmodel=large,
+  thanks to Kuan-Lin Chen from
+  https://www.andestech.com/";>Andes Technology.
+  Support for the standard vector calling convention variant, thanks to
+  Lehua Ding from RiVAI.
+  Supports the target attribute, which allows users to compile
+  a function with specific extensions.
+  -march= option no longer requires the architecture string
+  to be in canonical order, with only a few constraints remaining: the
+  architecture string must start with rv[32|64][i|g|e], and
+  must use an underscore as the separator after a multi-letter extension.
+  
+  -march=help option has been introduced to dump all
+  supported extensions.
+  Added experimental support for the -mrvv-vector-bits=zvl
+  option and the riscv_rvv_vector_bits attribute, which
+  specify a fixed length for scalable vector types. This option is
+  optimized for specific vector core implementations; however, the code
+  generated with this option is NOT portable,
+  thanks to Pan Li from https://www.intel.com/";>Intel.
+  
+  Support for TLS descriptors has been introduced, which can be enabled by
+  the -mtls-dialect=desc option. The default behavior can be
+  configured with --with-tls=[trad|desc].
+  Support for the TLS descriptors, this can be enabled by
+  -mtls-dialect=desc and the default behavior can be configure
+  by --with-tls=[trad|desc], thanks to Tatsuyuki Ishi from
+  https://bluewhale.systems/";>Blue Whale Systems
+  
+  Support for the following standard extensions has been added:
+
+  Vector crypto extensions:
+   
+ Zvbb
+ Zvkb
+ Zvbc
+ Zvkg
+ Zvkned
+ Zvkhna
+ Zvkhnb
+ Zvksed
+ Zvksh
+ Zvkn
+ Zvknc
+ Zvkng
+ Zvks
+ Zvksc
+ Zvksg
+ Zvkt
+   
+  
+  Code size reduction extensions:
+   
+ Zca
+ Zcb
+ Zce
+ Zcf
+ Zcd
+ Zcmp
+ Zcmt
+   
+  
+  Zicond
+  Zfa
+  Ztso
+  Zvfbfmin
+  Zvfhmin
+  Zvfh
+  Za64rs
+  Za128rs
+  Ziccif
+  Ziccrse
+  Ziccamoa
+  Zicclsm
+  Zic64b
+  Smaia
+  Smepmp
+  Smstateen
+  Ssaia
+  Sscofpmf
+  Ssstateen
+  Sstc
+  Svinval
+  Svnapot
+  Svpbmt
+
+  
+  Support for the following vendor extensions has been added:
+
+  T-Head:
+   
+ XTheadVector
+   
+  
+  CORE-V:
+   
+ XCVmac
+ XCValu
+ XCVelw
+ XCVsimd
+ XCVbi
+   
+  
+  Ventana Micro:
+   
+ XVentanaCondops
+   
+  
+
+  
+  The following new CPUs are supported through the -mcpu
+  option (GCC identifiers in parentheses).
+
+  SiFive's X280 (sifive-x280).
+  SiFive's P450 (sifive-p450).
+  SiFive's P670 (sifive-p670).
+
+  
+  The following new CPUs are supported through the -mtune
+  option (GCC identifiers in parentheses).
+
+  Generic out-of-order core (generic-ooo).
+  SiFive's P400 series (sifive-p400-series).
+  SiFive's P600 series (sifive-p600-series).
+  XiangShan's Nanhu microarchitecture 
(xiangshan-nanhu).
+
+  
+
 
 
 
-- 
2.34.1

Re: [PATCH v5] RISC-V: Implement TLS Descriptors.

[Kito Cheng]

Committed to trunk, thanks Tatsuyuki!

On Fri, Mar 29, 2024 at 2:32 PM Kito Cheng  wrote:
>
> Hi Tatsuyuki:
>
> Thanks for your hard work and keep updating, the patch set is LGTM, I
> plan to commit this next week if no further comments :)
>
> Hi MaskRay:
>
> Thanks for your review on the patchset! just put you into the cc list
> in case you have few more comments :)
>
>
> On Fri, Mar 29, 2024 at 1:53 PM Tatsuyuki Ishi  
> wrote:
> >
> > This implements TLS Descriptors (TLSDESC) as specified in [1].
> >
> > The 4-instruction sequence is implemented as a single RTX insn for
> > simplicity, but this can be revisited later if instruction scheduling or
> > more flexible RA is desired.
> >
> > The default remains to be the traditional TLS model, but can be configured
> > with --with-tls={trad,desc}. The choice can be revisited once toolchain
> > and libc support ships.
> >
> > [1]: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/373.
> >
> > gcc/Changelog:
> > * config/riscv/riscv.opt: Add -mtls-dialect to configure TLS flavor.
> > * config.gcc: Add --with-tls configuration option to change the
> > default TLS flavor.
> > * config/riscv/riscv.h: Add TARGET_TLSDESC determined from
> > -mtls-dialect and with_tls defaults.
> > * config/riscv/riscv-opts.h: Define enum riscv_tls_type for the
> > two TLS flavors.
> > * config/riscv/riscv-protos.h: Define SYMBOL_TLSDESC symbol type.
> > * config/riscv/riscv.md: Add instruction sequence for TLSDESC.
> > * config/riscv/riscv.cc (riscv_symbol_insns): Add instruction
> > sequence length data for TLSDESC.
> > (riscv_legitimize_tls_address): Add lowering of TLSDESC.
> > * doc/install.texi: Document --with-tls for RISC-V.
> > * doc/invoke.texi: Document -mtls-dialect for RISC-V.
> > * testsuite/gcc.target/riscv/tls_1.x: Add TLSDESC GD test case.
> > * testsuite/gcc.target/riscv/tlsdesc.c: Same as above.
> > ---
> > No regression in gcc tests for rv32gcv and rv64gcv, tested alongside
> > the binutils and glibc implementation. Tested with --with-tls=desc.
> >
> > v2: Add with_tls configuration option, and a few readability improvements.
> > Added Changelog.
> > v3: Add documentation per Kito's suggestion.
> > Fix minor issues pointed out by Kito and Jeff.
> > Thanks Kito Cheng and Jeff Law for review.
> > v4: Add TLSDESC GD assembly test.
> > Rebase on top of trunk.
> > v5: Trivial rebase on top of trunk.
> >
> > I have recently addressed relaxation concerns on binutils and RVV
> > register save/restore on glibc, so I'm sending out a trivial rebase
> > with the hope that the full set can be merged soon.
> >
> >  gcc/config.gcc   | 15 ++-
> >  gcc/config/riscv/riscv-opts.h|  6 ++
> >  gcc/config/riscv/riscv-protos.h  |  5 +++--
> >  gcc/config/riscv/riscv.cc| 24 
> >  gcc/config/riscv/riscv.h |  9 +++--
> >  gcc/config/riscv/riscv.md| 20 +++-
> >  gcc/config/riscv/riscv.opt   | 14 ++
> >  gcc/doc/install.texi |  3 +++
> >  gcc/doc/invoke.texi  | 13 -
> >  gcc/testsuite/gcc.target/riscv/tls_1.x   |  5 +
> >  gcc/testsuite/gcc.target/riscv/tlsdesc.c | 12 
> >  11 files changed, 115 insertions(+), 11 deletions(-)
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/tls_1.x
> >  create mode 100644 gcc/testsuite/gcc.target/riscv/tlsdesc.c
> >
> > diff --git a/gcc/config.gcc b/gcc/config.gcc
> > index 17873ac2103..1a5870672d2 100644
> > --- a/gcc/config.gcc
> > +++ b/gcc/config.gcc
> > @@ -2492,6 +2492,7 @@ riscv*-*-linux*)
> > # Force .init_array support.  The configure script cannot always
> > # automatically detect that GAS supports it, yet we require it.
> > gcc_cv_initfini_array=yes
> > +   with_tls=${with_tls:-trad}
> > ;;
> >  riscv*-*-elf* | riscv*-*-rtems*)
> > tm_file="elfos.h newlib-stdint.h ${tm_file} riscv/elf.h"
> > @@ -2534,6 +2535,7 @@ riscv*-*-freebsd*)
> > # Force .init_array support.  The configure script cannot always
> > # automatically detect that GAS supports it, yet we require it.
> > gcc_cv_initfini_array=yes
> > +   with_tls=${with_tls:-trad}
> >  

Re: [PATCH] RISC-V: Fix misspelled term builtin in error message

[Kito Cheng]

lgtm

On Sat, Mar 30, 2024 at 8:07 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to fix below misspelled term in error message.
>
> ../../gcc/config/riscv/riscv-vector-builtins.cc:4592:16: error:
> misspelled term 'builtin function' in format; use 'built-in function' instead 
> [-Werror=format-diag]
>  4592 |   "builtin function %qE requires the V ISA extension", 
> exp);
>
> The below tests are passed for this patch.
> * The riscv regression test on rvv.exp and riscv.exp.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins.cc (expand_builtin): Take
> the term built-in over builtin.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c:
> Adjust test dg-error.
> * gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c:
> Ditto.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/config/riscv/riscv-vector-builtins.cc   | 2 +-
>  .../riscv/rvv/base/target_attribute_v_with_intrinsic-7.c| 2 +-
>  .../riscv/rvv/base/target_attribute_v_with_intrinsic-8.c| 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins.cc 
> b/gcc/config/riscv/riscv-vector-builtins.cc
> index e07373d8b57..db9246eed2d 100644
> --- a/gcc/config/riscv/riscv-vector-builtins.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins.cc
> @@ -4589,7 +4589,7 @@ expand_builtin (unsigned int code, tree exp, rtx target)
>
>if (!TARGET_VECTOR)
>  error_at (EXPR_LOCATION (exp),
> - "builtin function %qE requires the V ISA extension", exp);
> + "built-in function %qE requires the V ISA extension", exp);
>
>return function_expander (rfn.instance, rfn.decl, exp, target).expand ();
>  }
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
>  
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> index 520b2e59fae..a4cd67f4f95 100644
> --- 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> +++ 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-7.c
> @@ -5,5 +5,5 @@
>
>  size_t test_1 (size_t vl)
>  {
> -  return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function 
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> +  return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function 
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
>  }
> diff --git 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
>  
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> index 9032d9d0b43..06ed9a9eddc 100644
> --- 
> a/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> +++ 
> b/gcc/testsuite/gcc.target/riscv/rvv/base/target_attribute_v_with_intrinsic-8.c
> @@ -19,5 +19,5 @@ test_2 ()
>  size_t
>  test_3 (size_t vl)
>  {
> -  return __riscv_vsetvl_e8m4 (vl); /* { dg-error {builtin function 
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
> +  return __riscv_vsetvl_e8m4 (vl); /* { dg-error {built-in function 
> '__riscv_vsetvl_e8m4\(vl\)' requires the V ISA extension} } */
>  }
> --
> 2.34.1
>

Re: [PATCH] RISC-V: Fix one unused varable in riscv_subset_list::parse

[Kito Cheng]

LGTM

On Sat, Mar 30, 2024 at 9:35 PM  wrote:
>
> From: Pan Li 
>
> This patch would like to fix one unused variable as below:
>
> ../../gcc/common/config/riscv/riscv-common.cc: In static member function
> 'static riscv_subset_list* riscv_subset_list::parse(const char*, location_t)':
> ../../gcc/common/config/riscv/riscv-common.cc:1501:19: error: unused variable 
> 'itr'
>   [-Werror=unused-variable]
>  1501 |   riscv_subset_t *itr;
>
> The variable consume code was removed but missed the var itself in
> previous.  Thus, we have unused variable here.
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
> Remove unused var decl.
>
> Signed-off-by: Pan Li 
> ---
>  gcc/common/config/riscv/riscv-common.cc | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc 
> b/gcc/common/config/riscv/riscv-common.cc
> index 7095f303cbb..43b7549e3ec 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -1498,7 +1498,6 @@ riscv_subset_list::parse (const char *arch, location_t 
> loc)
>  return NULL;
>
>riscv_subset_list *subset_list = new riscv_subset_list (arch, loc);
> -  riscv_subset_t *itr;
>const char *p = arch;
>p = subset_list->parse_base_ext (p);
>if (p == NULL)
> --
> 2.34.1
>

Re: [PATCH v5] RISC-V: Implement TLS Descriptors.

[Kito Cheng]

Hi Tatsuyuki:

Thanks for your hard work and keep updating, the patch set is LGTM, I
plan to commit this next week if no further comments :)

Hi MaskRay:

Thanks for your review on the patchset! just put you into the cc list
in case you have few more comments :)


On Fri, Mar 29, 2024 at 1:53 PM Tatsuyuki Ishi  wrote:
>
> This implements TLS Descriptors (TLSDESC) as specified in [1].
>
> The 4-instruction sequence is implemented as a single RTX insn for
> simplicity, but this can be revisited later if instruction scheduling or
> more flexible RA is desired.
>
> The default remains to be the traditional TLS model, but can be configured
> with --with-tls={trad,desc}. The choice can be revisited once toolchain
> and libc support ships.
>
> [1]: https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/373.
>
> gcc/Changelog:
> * config/riscv/riscv.opt: Add -mtls-dialect to configure TLS flavor.
> * config.gcc: Add --with-tls configuration option to change the
> default TLS flavor.
> * config/riscv/riscv.h: Add TARGET_TLSDESC determined from
> -mtls-dialect and with_tls defaults.
> * config/riscv/riscv-opts.h: Define enum riscv_tls_type for the
> two TLS flavors.
> * config/riscv/riscv-protos.h: Define SYMBOL_TLSDESC symbol type.
> * config/riscv/riscv.md: Add instruction sequence for TLSDESC.
> * config/riscv/riscv.cc (riscv_symbol_insns): Add instruction
> sequence length data for TLSDESC.
> (riscv_legitimize_tls_address): Add lowering of TLSDESC.
> * doc/install.texi: Document --with-tls for RISC-V.
> * doc/invoke.texi: Document -mtls-dialect for RISC-V.
> * testsuite/gcc.target/riscv/tls_1.x: Add TLSDESC GD test case.
> * testsuite/gcc.target/riscv/tlsdesc.c: Same as above.
> ---
> No regression in gcc tests for rv32gcv and rv64gcv, tested alongside
> the binutils and glibc implementation. Tested with --with-tls=desc.
>
> v2: Add with_tls configuration option, and a few readability improvements.
> Added Changelog.
> v3: Add documentation per Kito's suggestion.
> Fix minor issues pointed out by Kito and Jeff.
> Thanks Kito Cheng and Jeff Law for review.
> v4: Add TLSDESC GD assembly test.
> Rebase on top of trunk.
> v5: Trivial rebase on top of trunk.
>
> I have recently addressed relaxation concerns on binutils and RVV
> register save/restore on glibc, so I'm sending out a trivial rebase
> with the hope that the full set can be merged soon.
>
>  gcc/config.gcc   | 15 ++-
>  gcc/config/riscv/riscv-opts.h|  6 ++
>  gcc/config/riscv/riscv-protos.h  |  5 +++--
>  gcc/config/riscv/riscv.cc| 24 
>  gcc/config/riscv/riscv.h |  9 +++--
>  gcc/config/riscv/riscv.md| 20 +++-
>  gcc/config/riscv/riscv.opt   | 14 ++
>  gcc/doc/install.texi |  3 +++
>  gcc/doc/invoke.texi  | 13 -
>  gcc/testsuite/gcc.target/riscv/tls_1.x   |  5 +
>  gcc/testsuite/gcc.target/riscv/tlsdesc.c | 12 
>  11 files changed, 115 insertions(+), 11 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/tls_1.x
>  create mode 100644 gcc/testsuite/gcc.target/riscv/tlsdesc.c
>
> diff --git a/gcc/config.gcc b/gcc/config.gcc
> index 17873ac2103..1a5870672d2 100644
> --- a/gcc/config.gcc
> +++ b/gcc/config.gcc
> @@ -2492,6 +2492,7 @@ riscv*-*-linux*)
> # Force .init_array support.  The configure script cannot always
> # automatically detect that GAS supports it, yet we require it.
> gcc_cv_initfini_array=yes
> +   with_tls=${with_tls:-trad}
> ;;
>  riscv*-*-elf* | riscv*-*-rtems*)
> tm_file="elfos.h newlib-stdint.h ${tm_file} riscv/elf.h"
> @@ -2534,6 +2535,7 @@ riscv*-*-freebsd*)
> # Force .init_array support.  The configure script cannot always
> # automatically detect that GAS supports it, yet we require it.
> gcc_cv_initfini_array=yes
> +   with_tls=${with_tls:-trad}
> ;;
>
>  loongarch*-*-linux*)
> @@ -4671,7 +4673,7 @@ case "${target}" in
> ;;
>
> riscv*-*-*)
> -   supported_defaults="abi arch tune riscv_attribute isa_spec"
> +   supported_defaults="abi arch tune riscv_attribute isa_spec 
> tls"
>
> case "${target}" in
> riscv-* | riscv32*) xlen=32 ;;
> @@ -4801,6 +4803,17 @@ case "${target}" in
> ;;
&g

Re: [PATCH v1] RISC-V: Allow RVV intrinsic for more function target

[Kito Cheng]

Just tried something interesting:

$ riscv64-unknown-linux-gnu-gcc -march=rv64gc -O
target_attribute_v_with_intrinsic-9.c -S # Work
$ riscv64-unknown-linux-gnu-gcc -march=rv64gc_zve32x -O
target_attribute_v_with_intrinsic-9.c -S # Not work

Also I guess all zvk* and zvbb may also need to be added as well,
but...I suspect it's not scalable way?