[gem5-dev] Change in gem5/gem5[develop]: util: Add missing iostream header to util/m5/src/commands.cc

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30734 )


Change subject: util: Add missing iostream header to util/m5/src/commands.cc
..

util: Add missing iostream header to util/m5/src/commands.cc

Signed-off-by: Hoa Nguyen 
Change-Id: I93f99284ecda22c73572cc0ffa8c3be0160ce560
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30734
Reviewed-by: Jason Lowe-Power 
Reviewed-by: Gabe Black 
Maintainer: Jason Lowe-Power 
Maintainer: Gabe Black 
Tested-by: kokoro 
---
M util/m5/src/commands.cc
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/util/m5/src/commands.cc b/util/m5/src/commands.cc
index 9c103fb..d721899 100644
--- a/util/m5/src/commands.cc
+++ b/util/m5/src/commands.cc
@@ -34,6 +34,7 @@
 #include 
 #include 
 #include 
+#include 

 #include "args.hh"
 #include "commands.hh"

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I93f99284ecda22c73572cc0ffa8c3be0160ce560
Gerrit-Change-Number: 30734
Gerrit-PatchSet: 2
Gerrit-Owner: Hoa Nguyen 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Feedback on gem5-20.1 roadmap

[Jason Lowe-Power via gem5-dev]

Hi all!

After the gem5 workshop and town hall we held a couple of weeks ago, I have
put together a draft of the gem5-20.1 roadmap. You can find the draft on
gerrit: https://gem5-review.googlesource.com/c/public/gem5-website/+/30715.
Please let me know what feedback you have!

One of the main reasons we want to have a roadmap for 20.1 is that we found
during the gem5-20.0 release that we had many changes committed in the last
week before we created the staging branch. This was not ideal, and led to a
lot of effort to stabilize gem5 before we could release it. See
http://www.gem5.org/project/2020/05/21/gem5-20.html for more info.

Thus, for gem5-20.1, we would like to have a firm idea of what we are
trying to commit now, so we know where to focus our efforts. This roadmap
will help us do this.

So, if you're working on some cool new feature for gem5 and would like to
see it in gem5-20.1, let's add it to the roadmap so we can be sure that it
gets in!

Cheers,
Jason

--

Jason Lowe-Power (he/him/his)

Assistant Professor, Computer Science Department
University of California, Davis
3049 Kemper Hall
https://arch.cs.ucdavis.edu/

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[gem5-dev] Change in gem5/gem5[develop]: arm: Add a missing "break" in an ARM miscreg decode function.

[Gabe Black (Gerrit) via gem5-dev]

Gabe Black has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30654 )


Change subject: arm: Add a missing "break" in an ARM miscreg decode  
function.

..

arm: Add a missing "break" in an ARM miscreg decode function.

This change accidentally left out a "break" which gcc found and
complained about.

arch-arm: Implementation of Hardware Breakpoint exception

This change adds in the break based on the assumption that the function
should not fall through that case to the next.

Change-Id: Id728a0c9a504d1b6d231d3fe1e7c5ece05d3ac4d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30654
Reviewed-by: Jordi Vaquero 
Maintainer: Giacomo Travaglini 
Tested-by: kokoro 
---
M src/arch/arm/miscregs.cc
1 file changed, 1 insertion(+), 2 deletions(-)

Approvals:
  Jordi Vaquero: Looks good to me, approved
  Giacomo Travaglini: Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 86b3aaa..2bdbaa4 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -201,8 +201,6 @@
   return MISCREG_DBGBXVR15;
 }
 break;
-}
-switch (opc2) {
   case 4:
 switch (crm) {
   case 0:
@@ -216,6 +214,7 @@
 }
 break;
 }
+break;
   case 6:
 switch (crm) {
   case 0:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Id728a0c9a504d1b6d231d3fe1e7c5ece05d3ac4d
Gerrit-Change-Number: 30654
Gerrit-PatchSet: 3
Gerrit-Owner: Gabe Black 
Gerrit-Reviewer: Andreas Sandberg 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Gabe Black 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: util: Add missing iostream header to util/m5/src/commands.cc

[Hoa Nguyen (Gerrit) via gem5-dev]

Hoa Nguyen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30734 )



Change subject: util: Add missing iostream header to util/m5/src/commands.cc
..

util: Add missing iostream header to util/m5/src/commands.cc

Signed-off-by: Hoa Nguyen 
Change-Id: I93f99284ecda22c73572cc0ffa8c3be0160ce560
---
M util/m5/src/commands.cc
1 file changed, 1 insertion(+), 0 deletions(-)



diff --git a/util/m5/src/commands.cc b/util/m5/src/commands.cc
index 9c103fb..d721899 100644
--- a/util/m5/src/commands.cc
+++ b/util/m5/src/commands.cc
@@ -34,6 +34,7 @@
 #include 
 #include 
 #include 
+#include 

 #include "args.hh"
 #include "commands.hh"

--
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Gerrit-Branch: develop
Gerrit-Change-Id: I93f99284ecda22c73572cc0ffa8c3be0160ce560
Gerrit-Change-Number: 30734
Gerrit-PatchSet: 1
Gerrit-Owner: Hoa Nguyen 
Gerrit-MessageType: newchange
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[gem5-dev] Change in gem5/gem5[develop]: cpu: differentiate snoop DPRINTF messages for AtomicSimpleCPU

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30694 )



Change subject: cpu: differentiate snoop DPRINTF messages for  
AtomicSimpleCPU

..

cpu: differentiate snoop DPRINTF messages for AtomicSimpleCPU

Those three snoop messages were the same, which made interpreting logs
harder.

Change-Id: Ibff092932bc6d2ef0c5f15bf5f7ce031d1f1956b
---
M src/cpu/simple/atomic.cc
1 file changed, 6 insertions(+), 6 deletions(-)



diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 4671402..8c918e6 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -125,8 +125,8 @@
 void
 AtomicSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
 {
-DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n",  
pkt->getAddr(),

-pkt->cmdString());
+DPRINTF(SimpleCPU, "%s received snoop pkt for addr:%#x %s\n",
+__func__, pkt->getAddr(), pkt->cmdString());

 for (ThreadID tid = 0; tid < numThreads; tid++) {
 if (tid != sender) {
@@ -280,8 +280,8 @@
 Tick
 AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
 {
-DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n",  
pkt->getAddr(),

-pkt->cmdString());
+DPRINTF(SimpleCPU, "%s received atomic snoop pkt for addr:%#x %s\n",
+__func__, pkt->getAddr(), pkt->cmdString());

 // X86 ISA: Snooping an invalidation for monitor/mwait
 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)();
@@ -310,8 +310,8 @@
 void
 AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
 {
-DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n",  
pkt->getAddr(),

-pkt->cmdString());
+DPRINTF(SimpleCPU, "%s received functional snoop pkt for  
addr:%#x %s\n",

+__func__, pkt->getAddr(), pkt->cmdString());

 // X86 ISA: Snooping an invalidation for monitor/mwait
 AtomicSimpleCPU *cpu = (AtomicSimpleCPU *)();

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibff092932bc6d2ef0c5f15bf5f7ce031d1f1956b
Gerrit-Change-Number: 30694
Gerrit-PatchSet: 1
Gerrit-Owner: Ciro Santilli 
Gerrit-MessageType: newchange
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[gem5-dev] Re: bug squashing renamed pinned registers in o3?

[Giacomo Travaglini via gem5-dev]

Thanks Gabe,

Please let me know if you can reproduce the problem with the mentioned patch. 
If that’s the case, we should open a JIRA ticket so that I can have a look at 
that

Giacomo

From: Gabe Black 
Sent: 25 June 2020 05:28
To: Giacomo Travaglini 
Cc: gem5 Developer List ; Weiping Liao 
; Earl Ou ; Yu-hsin Wang 

Subject: Re: [gem5-dev] bug squashing renamed pinned registers in o3?

Hi Giacomo, thanks for your reply. To answer your questions, it looks like no 
for 1 (unless my grep was bad), and checkpoint save/restore for 2. I think 
we've been able to reproduce this problem much more easily with older versions 
of gem5, likely missing that fix, although I think we may have also seen it 
with newer versions. I've only been looking at it recently and was looking for 
the easiest way to reproduce, so I've only directly tried the older version.

I've cc-ed some Google folks that can hopefully share more details and confirm 
if they've seen this problem on a branch which does have the CL you mentioned 
in 1.

To Google folks, we should cherry-pick that CL into our branch to at least make 
the problem less common. We should have it already in our rebase branch, since 
it looks like it went in upstream in early March.

Gabe

On Wed, Jun 24, 2020 at 2:18 AM Giacomo Travaglini 
mailto:giacomo.travagl...@arm.com>> wrote:
Hi Gabe,

We are encountering the same problem on top of develop but it’s still worth 
asking:


  1.  Do you have https://gem5-review.googlesource.com/c/public/gem5/+/25743 ?
  2.  Are you encountering this in a simulation which is using a CPU switch or 
checkpoint save/restore

Kind Regards

Giacomo

From: Gabe Black via gem5-dev mailto:gem5-dev@gem5.org>>
Sent: 23 June 2020 06:24
To: gem5 Developer List mailto:gem5-dev@gem5.org>>
Cc: Gabe Black mailto:gabebl...@google.com>>
Subject: [gem5-dev] bug squashing renamed pinned registers in o3?

Hi folks, specifically ARM folks. We've been seeing a problem with O3 where 
when switching vector register renaming modes (full vectors vs vector 
elements), the CPU checks its bookkeeping and finds that a vector register is 
missing, ie with no instructions in flight, the free list has one fewer 
register in it than the difference between the total number of physical vector 
registers, and the number that should be taken up with architectural state.

This problem has been somewhat difficult to reproduce, although we can get it 
to happen, and it does happen often enough that it's been a real pain for us. 
Given that it's not very easy to get it to happen which makes it hard to 
observe, I've been digging around in the code trying to understand what all the 
pieces do and why the bookkeeping might be wrong.

The most promising thing I've found so far is that when squashing, the rename 
stage looks at its history and rolls back renames for squashed instructions. 
Some registers are fixed and not renamed, so rolling back those would be 
pointless. Also those registers should not go on the free list.

The way O3 detects those special registers is that they have the same index 
before and after renaming. If that is the case, O3 ignores those entries, and 
does not roll them back or mark their target as free.

This check is slightly out of date though, since with the recently added pinned 
register writes, a register will be renamed to the same thing several times in 
a row. When these entries are checked, they will not be rolled back (I think 
this part is still fine), but they will also not be marked as free.

This isn't exactly a smoking gun though, since the more I think about it, the 
more I think this may actually be ok. If one of the later writes is squashed, 
the register isn't "free" since it still holds the (partially written) 
architectural state. If everything gets squashed all the way back to the first 
entry which did change what register to use, then the slightly outdated check 
won't trigger and things should be freed up correctly (I think).

This code is mostly new to me though, so I'm not super confident making any 
grand declarations about what's going on. All the pieces seem to be there 
though, which makes me very suspicious.

Maybe something goes wrong if the right number of writes never happens because 
later writers get squashed?

Gabe
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[gem5-dev] Change in gem5/gem5[develop]: ext: Remove dead code from main.py

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30243 )


Change subject: ext: Remove dead code from main.py
..

ext: Remove dead code from main.py

This has been tested with vulture:
https://pypi.org/project/vulture

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: I5f0fbe6c4f5620503c03dfb1b3c8eb1fac31409e
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30243
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M ext/testlib/main.py
1 file changed, 0 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/ext/testlib/main.py b/ext/testlib/main.py
index 198b010..d2ae5a9 100644
--- a/ext/testlib/main.py
+++ b/ext/testlib/main.py
@@ -30,7 +30,6 @@
 import itertools

 import testlib.configuration as configuration
-import testlib.fixture as fixture_mod
 import testlib.handlers as handlers
 import testlib.loader as loader_mod
 import testlib.log as log

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5f0fbe6c4f5620503c03dfb1b3c8eb1fac31409e
Gerrit-Change-Number: 30243
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: ext: Remove dead code from results.py

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30244 )


Change subject: ext: Remove dead code from results.py
..

ext: Remove dead code from results.py

This has been tested with vulture:
https://pypi.org/project/vulture

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: Ib145f8916fdde9f1571eb71ca2fef3501b48804b
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30244
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M ext/testlib/result.py
1 file changed, 0 insertions(+), 1 deletion(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/ext/testlib/result.py b/ext/testlib/result.py
index 38b3322..2d2c506 100644
--- a/ext/testlib/result.py
+++ b/ext/testlib/result.py
@@ -33,7 +33,6 @@
 from testlib.configuration import config
 import testlib.helper as helper
 import testlib.state as state
-import testlib.log as log

 def _create_uid_index(iterable):
 index = {}

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ib145f8916fdde9f1571eb71ca2fef3501b48804b
Gerrit-Change-Number: 30244
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: ext: Remove dead code from configuration.py

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30242 )


Change subject: ext: Remove dead code from configuration.py
..

ext: Remove dead code from configuration.py

This has been tested with vulture:
https://pypi.org/project/vulture

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-533

Change-Id: Ibaf812ace94c2ae0e2115552a87fb506a427bb89
Signed-off-by: Giacomo Travaglini 
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30242
Tested-by: kokoro 
Reviewed-by: Jason Lowe-Power 
Maintainer: Jason Lowe-Power 
---
M ext/testlib/configuration.py
1 file changed, 0 insertions(+), 7 deletions(-)

Approvals:
  Jason Lowe-Power: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/ext/testlib/configuration.py b/ext/testlib/configuration.py
index b7c4697..cebb98f 100644
--- a/ext/testlib/configuration.py
+++ b/ext/testlib/configuration.py
@@ -84,7 +84,6 @@
 import re

 from six import add_metaclass
-from six.moves import configparser as ConfigParser
 from pickle import HIGHEST_PROTOCOL as highest_pickle_protocol

 from testlib.helper import absdirpath, AttrDict, FrozenAttrDict
@@ -132,11 +131,6 @@
 self._run_post_processors()
 self._initialized = True

-def _init_with_dicts(self, config, defaults):
-self._config = config
-self._defaults = defaults
-self._initialized = True
-
 def _add_post_processor(self, attr, post_processor):
 '''
 :param attr: Attribute to pass to and recieve from the
@@ -220,7 +214,6 @@
   os.pardir,
   os.pardir))
 defaults.result_path = os.path.join(os.getcwd(), '.testing-results')
-defaults.list_only_failed = False
 defaults.resource_url = 'http://dist.gem5.org/dist/develop'

 def define_constants(constants):

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ibaf812ace94c2ae0e2115552a87fb506a427bb89
Gerrit-Change-Number: 30242
Gerrit-PatchSet: 5
Gerrit-Owner: Giacomo Travaglini 
Gerrit-Reviewer: Bobby R. Bruce 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Hoa Nguyen 
Gerrit-Reviewer: Jason Lowe-Power 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: stats: add option to disable alignment spaces in stats.txt file

[Ciro Santilli (Gerrit) via gem5-dev]

Ciro Santilli has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/28627 )


Change subject: stats: add option to disable alignment spaces in stats.txt  
file

..

stats: add option to disable alignment spaces in stats.txt file

The alignment spaces in stats.txt takes up a lot of space and increases
simulation time, this commit adds the option to disable them with:

--stats-file stats.txt?spaces=False

Sample old lines with ?desc=False:

system.cpu.op_class::FloatMultAcc   0  0.00% 65.92%
system.cpu.op_class::FloatDiv   0  0.00% 65.92%

Sample new lines with ?desc=False;spaces=False:

system.cpu.op_class::FloatMultAcc 0 0.00% 65.92%
system.cpu.op_class::FloatDiv 0 0.00% 65.92%

On a 1000 dumpstats m5op loop spaces=False reduces:

* size: from 38MB to 20MB
* time: from 4.5s to 3.5s

Change-Id: Ib738b996b5646c329094cf61aaa1d977e844e759
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28627
Reviewed-by: Andreas Sandberg 
Maintainer: Andreas Sandberg 
Tested-by: kokoro 
---
M src/base/stats/text.cc
M src/base/stats/text.hh
M src/python/m5/stats/__init__.py
3 files changed, 71 insertions(+), 28 deletions(-)

Approvals:
  Andreas Sandberg: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/base/stats/text.cc b/src/base/stats/text.cc
index 96cbe34..fa342a2 100644
--- a/src/base/stats/text.cc
+++ b/src/base/stats/text.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2019 Arm Limited
+ * Copyright (c) 2019-2020 Arm Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -95,18 +95,16 @@
 std::list ();

 Text::Text()
-: mystream(false), stream(NULL), descriptions(false)
+: mystream(false), stream(NULL), descriptions(false), spaces(false)
 {
 }

-Text::Text(std::ostream )
-: mystream(false), stream(NULL), descriptions(false)
+Text::Text(std::ostream ) : Text()
 {
 open(stream);
 }

-Text::Text(const std::string )
-: mystream(false), stream(NULL), descriptions(false)
+Text::Text(const std::string ) : Text()
 {
 open(file);
 }
@@ -229,10 +227,28 @@
 string desc;
 Flags flags;
 bool descriptions;
+bool spaces;
 int precision;
 Result pdf;
 Result cdf;
+int nameSpaces;
+int valueSpaces;
+int pdfstrSpaces;
+int cdfstrSpaces;

+ScalarPrint(bool spaces) : spaces(spaces) {
+if (spaces) {
+nameSpaces = 40;
+valueSpaces = 12;
+pdfstrSpaces = 10;
+cdfstrSpaces = 10;
+} else {
+nameSpaces = 0;
+valueSpaces = 0;
+pdfstrSpaces = 0;
+cdfstrSpaces = 0;
+}
+}
 void update(Result val, Result total);
 void operator()(ostream , bool oneLine = false) const;
 };
@@ -263,12 +279,16 @@
 ccprintf(cdfstr, "%.2f%%", cdf * 100.0);

 if (oneLine) {
-ccprintf(stream, " |%12s %10s %10s",
- ValueToString(value, precision), pdfstr.str(),  
cdfstr.str());

+ccprintf(stream, " |");
 } else {
-ccprintf(stream, "%-40s %12s %10s %10s", name,
- ValueToString(value, precision), pdfstr.str(),  
cdfstr.str());

-
+ccprintf(stream, "%-*s ", nameSpaces, name);
+}
+ccprintf(stream, "%*s", valueSpaces, ValueToString(value, precision));
+if (spaces || pdfstr.rdbuf()->in_avail())
+ccprintf(stream, " %*s", pdfstrSpaces, pdfstr.str());
+if (spaces || cdfstr.rdbuf()->in_avail())
+ccprintf(stream, " %*s", cdfstrSpaces, cdfstr.str());
+if (!oneLine) {
 if (descriptions) {
 if (!desc.empty())
 ccprintf(stream, " # %s", desc);
@@ -286,11 +306,21 @@
 vector subdescs;
 Flags flags;
 bool descriptions;
+bool spaces;
 int precision;
 VResult vec;
 Result total;
 bool forceSubnames;
+int nameSpaces;

+VectorPrint() = delete;
+VectorPrint(bool spaces) : spaces(spaces) {
+if (spaces) {
+nameSpaces = 40;
+} else {
+nameSpaces = 0;
+}
+}
 void operator()(ostream ) const;
 };

@@ -308,7 +338,7 @@

 string base = name + separatorString;

-ScalarPrint print;
+ScalarPrint print(spaces);
 print.name = name;
 print.desc = desc;
 print.precision = precision;
@@ -332,7 +362,7 @@

 if ((!flags.isSet(nozero)) || (total != 0)) {
 if (flags.isSet(oneline)) {
-ccprintf(stream, "%-40s", name);
+ccprintf(stream, "%-*s", nameSpaces, name);
 print.flags = print.flags & (~nozero);
 }

@@ -373,7 +403,9 @@
 string desc;
 Flags flags;
 bool descriptions;
+bool spaces;
 int precision;
+int nameSpaces;

 const DistData 

@@ -389,8 +421,8 @@
 init(text, info);
 }

[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix minor bug PAUTH comparision with 0

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30615 )


Change subject: arch-arm: Fix minor bug PAUTH comparision with 0
..

arch-arm: Fix minor bug PAUTH comparision with 0

Change-Id: I887e5fa256a8c9cc24f7b9ef1fc0353dea555e82
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30615
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
---
M src/arch/arm/pauth_helpers.cc
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc
index 1c83d77..c88795f 100644
--- a/src/arch/arm/pauth_helpers.cc
+++ b/src/arch/arm/pauth_helpers.cc
@@ -706,7 +706,7 @@
 {
 case EL0:
 trapEL2 = (EL2Enabled(tc) && hcr.api == 0 &&
-  (hcr.tge == '0' || hcr.e2h == 0));
+  (hcr.tge == 0 || hcr.e2h == 0));
 trapEL3 = have_el3 && sc3.api == 0;
 break;
 case EL1:

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I887e5fa256a8c9cc24f7b9ef1fc0353dea555e82
Gerrit-Change-Number: 30615
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Fix SCR.NS compare to 0

[Jordi Vaquero (Gerrit) via gem5-dev]

Jordi Vaquero has submitted this change. (  
https://gem5-review.googlesource.com/c/public/gem5/+/30614 )


Change subject: arch-arm: Fix SCR.NS compare to 0
..

arch-arm: Fix SCR.NS compare to 0

Change-Id: Iba7628640bb222fd21fd067ff60dbe4d34f4b196
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30614
Tested-by: kokoro 
Reviewed-by: Giacomo Travaglini 
Maintainer: Giacomo Travaglini 
---
M src/arch/arm/insts/static_inst.hh
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
  kokoro: Regressions pass



diff --git a/src/arch/arm/insts/static_inst.hh  
b/src/arch/arm/insts/static_inst.hh

index 82bf61d..8610f99 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -257,7 +257,7 @@
 validModeChange = false;
 // There is no Hyp mode ('11010') in Secure state, so  
that

 // is UNPREDICTABLE
-if (scr.ns == '0' && newMode == MODE_HYP)
+if (scr.ns == 0 && newMode == MODE_HYP)
 validModeChange = false;
 // Cannot move into Hyp mode directly from a Non-secure
 // PL1 mode

--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/30614
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iba7628640bb222fd21fd067ff60dbe4d34f4b196
Gerrit-Change-Number: 30614
Gerrit-PatchSet: 4
Gerrit-Owner: Jordi Vaquero 
Gerrit-Reviewer: Giacomo Travaglini 
Gerrit-Reviewer: Jordi Vaquero 
Gerrit-Reviewer: kokoro 
Gerrit-MessageType: merged
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