[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adlp: Fix TypeC PHY-ready status readout
== Series Details == Series: drm/i915/adlp: Fix TypeC PHY-ready status readout URL : https://patchwork.freedesktop.org/series/99359/ State : success == Summary == CI Bug Log - changes from CI_DRM_11145 -> Patchwork_22111 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/index.html Participating hosts (46 -> 43) -- Additional (1): fi-pnv-d510 Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Known issues Here are the changes found in Patchwork_22111 that come from known issues: ### CI changes ### Possible fixes * boot: - fi-ilk-650: [FAIL][1] -> [PASS][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-ilk-650/boot.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-ilk-650/boot.html ### IGT changes ### Issues hit * igt@amdgpu/amd_cs_nop@nop-compute0: - fi-ilk-650: NOTRUN -> [SKIP][3] ([fdo#109271]) +39 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-ilk-650/igt@amdgpu/amd_cs_...@nop-compute0.html * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [PASS][4] -> [INCOMPLETE][5] ([i915#146]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-bdw-5557u/igt@gem_exec_suspend@basic...@smem.html * igt@gem_huc_copy@huc-copy: - fi-skl-6600u: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@verify-random: - fi-skl-6600u: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@gem_lmem_swapp...@verify-random.html * igt@i915_selftest@live@execlists: - fi-bsw-n3050: [PASS][8] -> [INCOMPLETE][9] ([i915#2940]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html * igt@i915_selftest@live@hangcheck: - fi-snb-2600:[PASS][10] -> [INCOMPLETE][11] ([i915#3921]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html * igt@i915_selftest@live@hugepages: - fi-rkl-guc: [PASS][12] -> [DMESG-WARN][13] ([i915#4993]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/fi-rkl-guc/igt@i915_selftest@l...@hugepages.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-rkl-guc/igt@i915_selftest@l...@hugepages.html * igt@kms_chamelium@dp-hpd-fast: - fi-ilk-650: NOTRUN -> [SKIP][14] ([fdo#109271] / [fdo#111827]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-ilk-650/igt@kms_chamel...@dp-hpd-fast.html * igt@kms_chamelium@vga-edid-read: - fi-skl-6600u: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827]) +8 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@kms_chamel...@vga-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-skl-6600u: NOTRUN -> [SKIP][16] ([fdo#109271]) +2 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-skl-6600u: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#533]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@kms_psr@primary_page_flip: - fi-skl-6600u: NOTRUN -> [FAIL][18] ([i915#4547]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-skl-6600u/igt@kms_psr@primary_page_flip.html * igt@prime_vgem@basic-userptr: - fi-pnv-d510:NOTRUN -> [SKIP][19] ([fdo#109271]) +57 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-pnv-d510/igt@prime_v...@basic-userptr.html * igt@runner@aborted: - fi-bsw-n3050: NOTRUN -> [FAIL][20] ([fdo#109271] / [i915#1436] / [i915#2722] / [i915#3428] / [i915#4312]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22111/fi-bsw-n3050/igt@run...@aborted.html Possible fixes * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [FAIL][21] ([i915#4547]) -> [PASS][22] [21]:
Re: [Intel-gfx] [PATCH 16/19] drm/i915/guc: Use a single pass to calculate regset
Hi Lucas,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[also build test ERROR on next-20220125]
[cannot apply to drm-intel/for-linux-next drm-exynos/exynos-drm-next
drm/drm-next tegra-drm/drm/tegra/for-next linus/master airlied/drm-next
v5.17-rc1]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Lucas-De-Marchi/drm-i915-guc-Refactor-ADS-access-to-use-dma_buf_map/20220127-043912
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-allyesconfig
(https://download.01.org/0day-ci/archive/20220127/202201271208.kelpe3mn-...@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/313757d9ed833acea4ee2bb0e3f3565d6efcf3cc
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Lucas-De-Marchi/drm-i915-guc-Refactor-ADS-access-to-use-dma_buf_map/20220127-043912
git checkout 313757d9ed833acea4ee2bb0e3f3565d6efcf3cc
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
In file included from include/drm/drm_mm.h:51,
from drivers/gpu/drm/i915/i915_vma.h:31,
from drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h:13,
from drivers/gpu/drm/i915/gt/uc/intel_guc.h:20,
from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
from drivers/gpu/drm/i915/gt/intel_gt_types.h:18,
from drivers/gpu/drm/i915/gt/intel_gt.h:10,
from drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:9:
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c: In function
'guc_mmio_reg_state_create':
>> drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:369:38: error: format '%lu'
>> expects argument of type 'long unsigned int', but argument 4 has type 'u32'
>> {aka 'unsigned int'} [-Werror=format=]
369 | drm_dbg(_to_gt(guc)->i915->drm, "Used %lu KB for temporary ADS
regset\n",
|
^~~~
370 | (temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
| ~~
||
|u32 {aka
unsigned int}
include/drm/drm_print.h:461:56: note: in definition of macro 'drm_dbg'
461 | drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRIVER, fmt,
##__VA_ARGS__)
|^~~
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:369:46: note: format string is
defined here
369 | drm_dbg(_to_gt(guc)->i915->drm, "Used %lu KB for temporary ADS
regset\n",
|~~^
| |
| long unsigned int
|%u
cc1: all warnings being treated as errors
vim +369 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
348
349 static long guc_mmio_reg_state_create(struct intel_guc *guc)
350 {
351 struct intel_gt *gt = guc_to_gt(guc);
352 struct intel_engine_cs *engine;
353 enum intel_engine_id id;
354 struct temp_regset temp_set = {};
355 long total = 0;
356
357 for_each_engine(engine, gt, id) {
358 u32 used = temp_set.storage_used;
359
360 if (guc_mmio_regset_init(_set, engine) < 0)
361 return -1;
362
363 guc->ads_regset_count[id] = temp_set.storage_used -
used;
364 total += guc->ads_regset_count[id];
365 }
366
367 guc->ads_regset = temp_set.storage;
368
> 369 drm_dbg(_to_gt(guc)->i915->drm, "Used %lu KB for temporary
> ADS regset\n",
370 (temp_set.storage_max * sizeof(struct guc_mmio_reg)) >>
10);
371
372 return total * sizeof(struct guc_mmio_reg);
373 }
374
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
Re: [Intel-gfx] [PATCH 3/8] drm/dp: add some new DPCD macros from DP 2.0 E11
On Tue, Jan 25, 2022 at 07:03:41PM +0200, Jani Nikula wrote:
> Add some of the new additions from DP 2.0 E11.
>
> Cc: Uma Shankar
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> include/drm/dp/drm_dp_helper.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h
> index c499d735b992..69487bd8ed56 100644
> --- a/include/drm/dp/drm_dp_helper.h
> +++ b/include/drm/dp/drm_dp_helper.h
> @@ -560,6 +560,7 @@ struct drm_panel;
> # define DP_TRAINING_PATTERN_DISABLE 0
> # define DP_TRAINING_PATTERN_1 1
> # define DP_TRAINING_PATTERN_2 2
> +# define DP_TRAINING_PATTERN_2_CDS 3 /* 2.0 E11 */
> # define DP_TRAINING_PATTERN_3 3 /* 1.2 */
> # define DP_TRAINING_PATTERN_4 7 /* 1.4 */
> # define DP_TRAINING_PATTERN_MASK0x3
> @@ -1350,6 +1351,7 @@ struct drm_panel;
> # define DP_PHY_REPEATER_128B132B_SUPPORTED (1 << 0)
> /* See DP_128B132B_SUPPORTED_LINK_RATES for values */
> #define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /*
> 2.0 */
> +#define DP_PHY_REPEATER_EQ_DONE 0xf0008 /* 2.0
> E11 */
Wonder if we should look at that at some point? The spec doesn't really
say so. Or maybe we should just dump it out of the link training failed?
>
> enum drm_dp_phy {
> DP_PHY_DPRX,
> --
> 2.30.2
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 01/19] dma-buf-map: Add read/write helpers
On Thu, Jan 27, 2022 at 08:24:04AM +0100, Christian König wrote:
> Am 26.01.22 um 21:36 schrieb Lucas De Marchi:
> > In certain situations it's useful to be able to read or write to an
> > offset that is calculated by having the memory layout given by a struct
> > declaration. Usually we are going to read/write a u8, u16, u32 or u64.
> >
> > Add a pair of macros dma_buf_map_read_field()/dma_buf_map_write_field()
> > to calculate the offset of a struct member and memcpy the data from/to
> > the dma_buf_map. We could use readb, readw, readl, readq and the write*
> > counterparts, however due to alignment issues this may not work on all
> > architectures. If alignment needs to be checked to call the right
> > function, it's not possible to decide at compile-time which function to
> > call: so just leave the decision to the memcpy function that will do
> > exactly that on IO memory or dereference the pointer.
> >
> > Cc: Sumit Semwal
> > Cc: Christian König
> > Cc: linux-me...@vger.kernel.org
> > Cc: dri-de...@lists.freedesktop.org
> > Cc: linaro-mm-...@lists.linaro.org
> > Cc: linux-ker...@vger.kernel.org
> > Signed-off-by: Lucas De Marchi
> > ---
> > include/linux/dma-buf-map.h | 81 +
> > 1 file changed, 81 insertions(+)
> >
> > diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h
> > index 19fa0b5ae5ec..65e927d9ce33 100644
> > --- a/include/linux/dma-buf-map.h
> > +++ b/include/linux/dma-buf-map.h
> > @@ -6,6 +6,7 @@
> > #ifndef __DMA_BUF_MAP_H__
> > #define __DMA_BUF_MAP_H__
> > +#include
> > #include
> > #include
> > @@ -229,6 +230,46 @@ static inline void dma_buf_map_clear(struct
> > dma_buf_map *map)
> > }
> > }
> > +/**
> > + * dma_buf_map_memcpy_to_offset - Memcpy into offset of dma-buf mapping
> > + * @dst: The dma-buf mapping structure
> > + * @offset:The offset from which to copy
> > + * @src: The source buffer
> > + * @len: The number of byte in src
> > + *
> > + * Copies data into a dma-buf mapping with an offset. The source buffer is
> > in
> > + * system memory. Depending on the buffer's location, the helper picks the
> > + * correct method of accessing the memory.
> > + */
> > +static inline void dma_buf_map_memcpy_to_offset(struct dma_buf_map *dst,
> > size_t offset,
> > + const void *src, size_t len)
> > +{
> > + if (dst->is_iomem)
> > + memcpy_toio(dst->vaddr_iomem + offset, src, len);
> > + else
> > + memcpy(dst->vaddr + offset, src, len);
> > +}
> > +
> > +/**
> > + * dma_buf_map_memcpy_from_offset - Memcpy from offset of dma-buf mapping
> > into system memory
> > + * @dst: Destination in system memory
> > + * @src: The dma-buf mapping structure
> > + * @src: The offset from which to copy
> > + * @len: The number of byte in src
> > + *
> > + * Copies data from a dma-buf mapping with an offset. The dest buffer is in
> > + * system memory. Depending on the mapping location, the helper picks the
> > + * correct method of accessing the memory.
> > + */
> > +static inline void dma_buf_map_memcpy_from_offset(void *dst, const struct
> > dma_buf_map *src,
> > + size_t offset, size_t len)
> > +{
> > + if (src->is_iomem)
> > + memcpy_fromio(dst, src->vaddr_iomem + offset, len);
> > + else
> > + memcpy(dst, src->vaddr + offset, len);
> > +}
> > +
>
> Well that's certainly a valid use case, but I suggest to change the
> implementation of the existing functions to call the new ones with offset=0.
>
> This way we only have one implementation.
>
Trivial - but agree with Christian that is a good cleanup.
> > /**
> >* dma_buf_map_memcpy_to - Memcpy into dma-buf mapping
> >* @dst: The dma-buf mapping structure
> > @@ -263,4 +304,44 @@ static inline void dma_buf_map_incr(struct dma_buf_map
> > *map, size_t incr)
> > map->vaddr += incr;
> > }
> > +/**
> > + * dma_buf_map_read_field - Read struct member from dma-buf mapping with
> > + * arbitrary size and handling un-aligned accesses
> > + *
> > + * @map__: The dma-buf mapping structure
> > + * @type__:The struct to be used containing the field to read
> > + * @field__: Member from struct we want to read
> > + *
> > + * Read a value from dma-buf mapping calculating the offset and size: this
> > assumes
> > + * the dma-buf mapping is aligned with a a struct type__. A single u8,
> > u16, u32
> > + * or u64 can be read, based on the offset and size of type__.field__.
> > + */
> > +#define dma_buf_map_read_field(map__, type__, field__) ({
> > \
> > + type__ *t__;
> > \
> > + typeof(t__->field__) val__;
> > \
> > + dma_buf_map_memcpy_from_offset(__, map__, offsetof(type__,
> > field__),\
> > +
Re: [Intel-gfx] [PATCH 02/19] dma-buf-map: Add helper to initialize second map
On Thu, Jan 27, 2022 at 08:27:11AM +0100, Christian König wrote:
Am 26.01.22 um 21:36 schrieb Lucas De Marchi:
When dma_buf_map struct is passed around, it's useful to be able to
initialize a second map that takes care of reading/writing to an offset
of the original map.
Add a helper that copies the struct and add the offset to the proper
address.
Well what you propose here can lead to all kind of problems and is
rather bad design as far as I can see.
The struct dma_buf_map is only to be filled in by the exporter and
should not be modified in this way by the importer.
humn... not sure if I was clear. There is no importer and exporter here.
There is a role delegation on filling out and reading a buffer when
that buffer represents a struct layout.
struct bla {
int a;
int b;
int c;
struct foo foo;
struct bar bar;
int d;
}
This implementation allows you to have:
fill_foo(struct dma_buf_map *bla_map) { ... }
fill_bar(struct dma_buf_map *bla_map) { ... }
and the first thing these do is to make sure the map it's pointing to
is relative to the struct it's supposed to write/read. Otherwise you're
suggesting everything to be relative to struct bla, or to do the same
I'm doing it, but IMO more prone to error:
struct dma_buf_map map = *bla_map;
dma_buf_map_incr(map, offsetof(...));
IMO this construct is worse because at a point in time in the function
the map was pointing to the wrong thing the function was supposed to
read/write.
It's also useful when the function has double duty, updating a global
part of the struct and a table inside it (see example in patch 6)
thanks
Lucas De Marchi
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/pmu: Fix KMD and GuC race on accessing busyness
== Series Details == Series: series starting with [1/2] drm/i915/pmu: Fix KMD and GuC race on accessing busyness URL : https://patchwork.freedesktop.org/series/99388/ State : success == Summary == CI Bug Log - changes from CI_DRM_11148 -> Patchwork_22119 Summary --- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/index.html Participating hosts (43 -> 42) -- Additional (3): fi-kbl-soraka fi-icl-u2 fi-pnv-d510 Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u Known issues Here are the changes found in Patchwork_22119 that come from known issues: ### IGT changes ### Issues hit * igt@amdgpu/amd_basic@query-info: - fi-bsw-kefka: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-bsw-kefka/igt@amdgpu/amd_ba...@query-info.html * igt@amdgpu/amd_cs_nop@fork-gfx0: - fi-icl-u2: NOTRUN -> [SKIP][2] ([fdo#109315]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html * igt@amdgpu/amd_cs_nop@sync-gfx0: - fi-bsw-n3050: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-bsw-n3050/igt@amdgpu/amd_cs_...@sync-gfx0.html * igt@gem_exec_fence@basic-busy@bcs0: - fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271]) +8 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#2190]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html - fi-icl-u2: NOTRUN -> [SKIP][6] ([i915#2190]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-icl-u2/igt@gem_huc_c...@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#4613]) +3 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random-engines: - fi-icl-u2: NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][9] ([i915#1886] / [i915#2291]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@i915_selftest@live@hangcheck: - bat-dg1-6: [PASS][10] -> [DMESG-FAIL][11] ([i915#4957]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11148/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [fdo#111827]) +8 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-icl-u2: NOTRUN -> [SKIP][13] ([fdo#111827]) +8 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-icl-u2/igt@kms_chamel...@hdmi-hpd-fast.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-icl-u2: NOTRUN -> [SKIP][14] ([fdo#109278]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-icl-u2/igt@kms_cursor_leg...@basic-busy-flip-before-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - fi-icl-u2: NOTRUN -> [SKIP][15] ([fdo#109285]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-icl-u2/igt@kms_force_connector_ba...@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d: - fi-kbl-soraka: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#533]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html * igt@prime_vgem@basic-userptr: - fi-pnv-d510:NOTRUN -> [SKIP][17] ([fdo#109271]) +57 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-pnv-d510/igt@prime_v...@basic-userptr.html - fi-icl-u2: NOTRUN -> [SKIP][18] ([i915#3301]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22119/fi-icl-u2/igt@prime_v...@basic-userptr.html Possible fixes * igt@i915_selftest@live@execlists: - fi-bsw-kefka:
[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Refactor ADS access to use dma_buf_map
== Series Details == Series: drm/i915/guc: Refactor ADS access to use dma_buf_map URL : https://patchwork.freedesktop.org/series/99378/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11147_full -> Patchwork_22116_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22116_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22116_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22116_full: ### IGT changes ### Possible regressions * igt@i915_pm_rpm@modeset-lpsp-stress: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-iclb7/igt@i915_pm_...@modeset-lpsp-stress.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-iclb4/igt@i915_pm_...@modeset-lpsp-stress.html Known issues Here are the changes found in Patchwork_22116_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][3] ([fdo#109271] / [i915#1099]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_eio@unwedge-stress: - shard-iclb: [PASS][4] -> [TIMEOUT][5] ([i915#2481] / [i915#3070]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-iclb2/igt@gem_...@unwedge-stress.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-iclb7/igt@gem_...@unwedge-stress.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-tglb: NOTRUN -> [FAIL][6] ([i915#2842]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-tglb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-kbl6/igt@gem_exec_fair@basic-p...@vcs1.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-kbl7/igt@gem_exec_fair@basic-p...@vcs1.html * igt@gem_exec_suspend@basic-s3@smem: - shard-apl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +1 similar issue [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-apl2/igt@gem_exec_suspend@basic...@smem.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-apl3/igt@gem_exec_suspend@basic...@smem.html * igt@gem_exec_whisper@basic-fds-forked-all: - shard-glk: [PASS][11] -> [DMESG-WARN][12] ([i915#118]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-glk1/igt@gem_exec_whis...@basic-fds-forked-all.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-glk4/igt@gem_exec_whis...@basic-fds-forked-all.html * igt@gem_lmem_swapping@basic: - shard-kbl: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#4613]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-kbl6/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@heavy-random: - shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-glk8/igt@gem_lmem_swapp...@heavy-random.html * igt@gem_lmem_swapping@parallel-multi: - shard-tglb: NOTRUN -> [SKIP][15] ([i915#4613]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-tglb8/igt@gem_lmem_swapp...@parallel-multi.html * igt@gem_pwrite@basic-exhaustion: - shard-snb: NOTRUN -> [WARN][16] ([i915#2658]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-snb6/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@create-regular-context-1: - shard-tglb: NOTRUN -> [SKIP][17] ([i915#4270]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-tglb8/igt@gem_...@create-regular-context-1.html * igt@gem_pxp@verify-pxp-execution-after-suspend-resume: - shard-iclb: NOTRUN -> [SKIP][18] ([i915#4270]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/shard-iclb7/igt@gem_...@verify-pxp-execution-after-suspend-resume.html * igt@gem_softpin@allocator-evict-all-engines: - shard-glk: [PASS][19] -> [FAIL][20] ([i915#4171]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-glk5/igt@gem_soft...@allocator-evict-all-engines.html [20]:
Re: [Intel-gfx] [PATCH v5 06/10] drm/i915/guc: Update GuC's log-buffer-state access for error capture.
As per the rev 5 CI results between this patch and patch7, i have introduced a lockdep splat bug, i shall fix that in the next rev. ...alan On Wed, 2022-01-26 at 02:48 -0800, Alan Previn wrote: > GuC log buffer regions for debug-log-events, crash-dumps and > error-state-capture are all a single bo allocation that includes > the guc_log_buffer_state structures. > > Since the error-capture region is accessed with high priority at non- > deterministic times (as part of gpu coredump) while the debug-log-event > region is populated and accessed with different priorities, timings and > consumers, let's split out separate locks for buffer-state accesses > of each region. > > Also, ensure a global mapping is made up front for the entire bo > throughout GuC operation so that dynamic mapping and unmapping isn't > required for error capture log access if relay-logging isn't running. > > Additionally, while here, make some readibility improvements: > 1. change previous function names with "capture_logs" to >"copy_debug_logs" to help make the distinction clearer. > 2. Update the guc log region mapping comments to order them >according to the enum definition as per the GuC interface. >
Re: [Intel-gfx] [PATCH 2/2] drm/i915/pmu: Use existing uncore helper to read gpm_timestamp
Hi Umesh,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-tip/drm-tip]
[cannot apply to linus/master drm-intel/for-linux-next v5.17-rc1 next-20220125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Umesh-Nerlige-Ramappa/drm-i915-pmu-Fix-KMD-and-GuC-race-on-accessing-busyness/20220127-081651
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-m021-20220124
(https://download.01.org/0day-ci/archive/20220127/202201271109.uuklswk3-...@intel.com/config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
#
https://github.com/0day-ci/linux/commit/2d74f201eae0c9ec06e6dc84b363089c0f190058
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review
Umesh-Nerlige-Ramappa/drm-i915-pmu-Fix-KMD-and-GuC-race-on-accessing-busyness/20220127-081651
git checkout 2d74f201eae0c9ec06e6dc84b363089c0f190058
# save the config file to linux build tree
mkdir build_dir
make W=1 O=build_dir ARCH=i386 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot
All errors (new ones prefixed by >>):
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c: In function
'guc_update_pm_timestamp':
>> drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1217:36: error: 'uncore'
>> undeclared (first use in this function)
1217 | gpm_ts = intel_uncore_read64_2x32(uncore, MISC_STATUS0,
MISC_STATUS1) >>
|^~
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1217:36: note: each
undeclared identifier is reported only once for each function it appears in
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c:1210:19: warning: unused
variable 'gt' [-Wunused-variable]
1210 | struct intel_gt *gt = guc_to_gt(guc);
| ^~
vim +/uncore +1217 drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
1207
1208 static void guc_update_pm_timestamp(struct intel_guc *guc, ktime_t *now)
1209 {
1210 struct intel_gt *gt = guc_to_gt(guc);
1211 u32 gt_stamp_lo, gt_stamp_hi;
1212 u64 gpm_ts;
1213
1214 lockdep_assert_held(>timestamp.lock);
1215
1216 gt_stamp_hi = upper_32_bits(guc->timestamp.gt_stamp);
> 1217 gpm_ts = intel_uncore_read64_2x32(uncore, MISC_STATUS0,
> MISC_STATUS1) >>
1218 guc->timestamp.shift;
1219 gt_stamp_lo = lower_32_bits(gpm_ts);
1220 *now = ktime_get();
1221
1222 if (gt_stamp_lo < lower_32_bits(guc->timestamp.gt_stamp))
1223 gt_stamp_hi++;
1224
1225 guc->timestamp.gt_stamp = ((u64)gt_stamp_hi << 32) |
gt_stamp_lo;
1226 }
1227
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v10,1/5] drm: improve drm_buddy_alloc function
== Series Details == Series: series starting with [v10,1/5] drm: improve drm_buddy_alloc function URL : https://patchwork.freedesktop.org/series/99382/ State : success == Summary == CI Bug Log - changes from CI_DRM_11147_full -> Patchwork_22117_full Summary --- **SUCCESS** No regressions found. Participating hosts (10 -> 10) -- No changes in participating hosts Known issues Here are the changes found in Patchwork_22117_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_create@create-massive: - shard-skl: NOTRUN -> [DMESG-WARN][1] ([i915#4991]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-skl2/igt@gem_cre...@create-massive.html * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#1099]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-snb6/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_eio@in-flight-immediate: - shard-tglb: [PASS][3] -> [TIMEOUT][4] ([i915#3063]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-tglb1/igt@gem_...@in-flight-immediate.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-tglb5/igt@gem_...@in-flight-immediate.html * igt@gem_exec_capture@pi@vcs0: - shard-skl: NOTRUN -> [INCOMPLETE][5] ([i915#4547]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-skl6/igt@gem_exec_capture@p...@vcs0.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-kbl: NOTRUN -> [FAIL][6] ([i915#2842]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-kbl6/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@vecs0: - shard-apl: [PASS][7] -> [FAIL][8] ([i915#2842]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-apl8/igt@gem_exec_fair@basic-n...@vecs0.html - shard-glk: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-glk5/igt@gem_exec_fair@basic-n...@vecs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-glk4/igt@gem_exec_fair@basic-n...@vecs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-kbl: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/shard-kbl1/igt@gem_exec_fair@basic-pace-s...@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-kbl4/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-tglb: NOTRUN -> [FAIL][13] ([i915#2842]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-tglb3/igt@gem_exec_fair@basic-throt...@rcs0.html * igt@gem_lmem_swapping@basic: - shard-kbl: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#4613]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-kbl1/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@heavy-random: - shard-glk: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-glk7/igt@gem_lmem_swapp...@heavy-random.html * igt@gem_lmem_swapping@parallel-multi: - shard-tglb: NOTRUN -> [SKIP][16] ([i915#4613]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-tglb3/igt@gem_lmem_swapp...@parallel-multi.html * igt@gem_lmem_swapping@parallel-random: - shard-apl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-apl8/igt@gem_lmem_swapp...@parallel-random.html * igt@gem_lmem_swapping@parallel-random-engines: - shard-skl: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-skl10/igt@gem_lmem_swapp...@parallel-random-engines.html * igt@gem_pwrite@basic-exhaustion: - shard-snb: NOTRUN -> [WARN][19] ([i915#2658]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-snb6/igt@gem_pwr...@basic-exhaustion.html * igt@gem_pxp@create-regular-context-1: - shard-tglb: NOTRUN -> [SKIP][20] ([i915#4270]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-tglb3/igt@gem_...@create-regular-context-1.html * igt@gem_pxp@verify-pxp-execution-after-suspend-resume: - shard-iclb: NOTRUN -> [SKIP][21] ([i915#4270]) [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22117/shard-iclb7/igt@gem_...@verify-pxp-execution-after-suspend-resume.html *
Re: [Intel-gfx] [PATCH 6/8] drm/i915/dp: add 128b/132b support to link status checks
On Tue, Jan 25, 2022 at 07:03:44PM +0200, Jani Nikula wrote:
> Abstract link status check to a function that takes 128b/132b and 8b/10b
> into account, and use it. Also dump link status on failures.
>
> Cc: Uma Shankar
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 39 ++-
> .../drm/i915/display/intel_dp_link_training.c | 2 +-
> .../drm/i915/display/intel_dp_link_training.h | 4 ++
> 3 files changed, 34 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 4d4579a301f6..80fedd0e6212 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3628,6 +3628,32 @@ static void intel_dp_handle_test_request(struct
> intel_dp *intel_dp)
> "Could not write test response to sink\n");
> }
>
> +static bool intel_dp_link_ok(struct intel_dp *intel_dp,
> + u8 link_status[DP_LINK_STATUS_SIZE])
> +{
> + struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + bool uhbr = intel_dp->link_rate >= 100;
> + bool ok;
> +
> + if (uhbr)
> + ok = drm_dp_128b132b_lane_channel_eq_done(link_status,
> + intel_dp->lane_count);
That will only check the eq done bits. I think we want to keep the
symbol locked checks as well.
> + else
> + ok = drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
> +
> + if (ok)
> + return true;
> +
> + intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);
> + drm_dbg_kms(>drm,
> + "[ENCODER:%d:%s] %s link not ok, retraining\n",
> + encoder->base.base.id, encoder->base.name,
> + uhbr ? "128b/132b" : "8b/10b");
> +
> + return false;
> +}
> +
> static void
> intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, u8 *ack)
> {
> @@ -3658,14 +3684,7 @@ static bool intel_dp_mst_link_status(struct intel_dp
> *intel_dp)
> return false;
> }
>
> - if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
> - drm_dbg_kms(>drm,
> - "[ENCODER:%d:%s] channel EQ not ok, retraining\n",
> - encoder->base.base.id, encoder->base.name);
> - return false;
> - }
> -
> - return true;
> + return intel_dp_link_ok(intel_dp, link_status);
> }
>
> /**
> @@ -3779,8 +3798,8 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
> intel_dp->lane_count))
> return false;
>
> - /* Retrain if Channel EQ or CR not ok */
> - return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
> + /* Retrain if link not ok */
> + return !intel_dp_link_ok(intel_dp, link_status);
> }
>
> static bool intel_dp_has_connector(struct intel_dp *intel_dp,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> index 8bb6a296f421..1e41a560204a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
> @@ -712,7 +712,7 @@ static bool intel_dp_adjust_request_changed(const struct
> intel_crtc_state *crtc_
> return false;
> }
>
> -static void
> +void
> intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
> const u8 link_status[DP_LINK_STATUS_SIZE])
> {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> index dbfb15705aaa..dc1556b46b85 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h
> @@ -29,6 +29,10 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
> void intel_dp_stop_link_train(struct intel_dp *intel_dp,
> const struct intel_crtc_state *crtc_state);
>
> +void
> +intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
> + const u8 link_status[DP_LINK_STATUS_SIZE]);
> +
> /* Get the TPSx symbol type of the value programmed to
> DP_TRAINING_PATTERN_SET */
> static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
> {
> --
> 2.30.2
--
Ville Syrjälä
Intel
Re: [Intel-gfx] [PATCH 5/8] drm/i915/dp: rewrite DP 2.0 128b/132b link training based on errata
On Tue, Jan 25, 2022 at 07:03:43PM +0200, Jani Nikula wrote:
> +static bool
> +intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp,
> +const struct intel_crtc_state *crtc_state,
> +int lttpr_count)
> +{
> + struct intel_encoder *encoder = _to_dig_port(intel_dp)->base;
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + u8 link_status[DP_LINK_STATUS_SIZE];
> + unsigned long deadline;
> +
> + if (drm_dp_dpcd_writeb(_dp->aux, DP_TRAINING_PATTERN_SET,
> +DP_TRAINING_PATTERN_2_CDS) != 1) {
> + drm_err(>drm,
> + "[ENCODER:%d:%s] Failed to start 128b/132b TPS2 CDS\n",
> + encoder->base.base.id, encoder->base.name);
> + return false;
> + }
> +
> + deadline = jiffies + msecs_to_jiffies((lttpr_count + 1) * 20);
> + for (;;) {
> + usleep_range(2000, 3000);
> +
> + if (drm_dp_dpcd_read_link_status(_dp->aux, link_status) <
> 0) {
> + drm_err(>drm,
> + "[ENCODER:%d:%s] Failed to read link status\n",
> + encoder->base.base.id, encoder->base.name);
> + return false;
> + }
> +
> + if (drm_dp_128b132b_cds_interlane_align_done(link_status) &&
> + drm_dp_128b132b_lane_symbol_locked(link_status,
> crtc_state->lane_count)) {
I'm thinkin we want to check for both eq done and symbol locked here,
just like we do with 8b10b.
> + drm_dbg_kms(>drm,
> + "[ENCODER:%d:%s] CDS interlane align
> done\n",
> + encoder->base.base.id, encoder->base.name);
> + break;
> + }
> +
> + if (drm_dp_128b132b_link_training_failed(link_status)) {
> + intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX,
> link_status);
> + drm_err(>drm,
> + "[ENCODER:%d:%s] Downstream link training
> failure\n",
> + encoder->base.base.id, encoder->base.name);
> + return false;
> + }
> +
> + if (time_after(jiffies, deadline)) {
> + intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX,
> link_status);
> + drm_err(>drm,
> + "[ENCODER:%d:%s] CDS timeout\n",
> + encoder->base.base.id, encoder->base.name);
> + return false;
> + }
> + }
> +
> + /* FIXME: Should DP_TRAINING_PATTERN_DISABLE be written first? */
> + if (intel_dp->set_idle_link_train)
> + intel_dp->set_idle_link_train(intel_dp, crtc_state);
> +
> + return true;
> +}
--
Ville Syrjälä
Intel
Re: [Intel-gfx] mmotm 2022-01-26-21-04 uploaded (gpu/drm/i915/i915_gem_evict.h)
On 1/26/22 21:04, a...@linux-foundation.org wrote: > The mm-of-the-moment snapshot 2022-01-26-21-04 has been uploaded to > >https://www.ozlabs.org/~akpm/mmotm/ > > mmotm-readme.txt says > > README for mm-of-the-moment: > > https://www.ozlabs.org/~akpm/mmotm/ > > This is a snapshot of my -mm patch queue. Uploaded at random hopefully > more than once a week. > > You will need quilt to apply these patches to the latest Linus release (5.x > or 5.x-rcY). The series file is in broken-out.tar.gz and is duplicated in > https://ozlabs.org/~akpm/mmotm/series > > The file broken-out.tar.gz contains two datestamp files: .DATE and > .DATE--mm-dd-hh-mm-ss. Both contain the string -mm-dd-hh-mm-ss, > followed by the base kernel version against which this patch series is to > be applied. on x86_64: (from linux-next.patch) HDRTEST drivers/gpu/drm/i915/i915_gem_evict.h In file included from :0:0: ./../drivers/gpu/drm/i915/i915_gem_evict.h:15:15: error: ‘struct i915_gem_ww_ctx’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] struct i915_gem_ww_ctx *ww, ^~~ ./../drivers/gpu/drm/i915/i915_gem_evict.h:21:14: error: ‘struct i915_gem_ww_ctx’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] struct i915_gem_ww_ctx *ww, ^~~ ./../drivers/gpu/drm/i915/i915_gem_evict.h:25:16: error: ‘struct i915_gem_ww_ctx’ declared inside parameter list will not be visible outside of this definition or declaration [-Werror] struct i915_gem_ww_ctx *ww); ^~~ cc1: all warnings being treated as errors -- ~Randy
Re: [Intel-gfx] [PATCH 1/8] drm/dp: add drm_dp_128b132b_read_aux_rd_interval()
On Tue, Jan 25, 2022 at 07:03:39PM +0200, Jani Nikula wrote:
> The DP 2.0 errata changes DP_128B132B_TRAINING_AUX_RD_INTERVAL (DPCD
> 0x2216) completely. Add a new function to read that. Follow-up will need
> to clean up existing functions.
>
> v2: fix reversed interpretation of bit 7 meaning (Uma)
>
> Cc: Uma Shankar
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
Reviewed-by: Ville Syrjälä
> ---
> drivers/gpu/drm/dp/drm_dp.c| 20
> include/drm/dp/drm_dp_helper.h | 3 +++
> 2 files changed, 23 insertions(+)
>
> diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
> index 6d43325acca5..52c6da510142 100644
> --- a/drivers/gpu/drm/dp/drm_dp.c
> +++ b/drivers/gpu/drm/dp/drm_dp.c
> @@ -281,6 +281,26 @@ int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux,
> const u8 dpcd[DP_RECEIV
> }
> EXPORT_SYMBOL(drm_dp_read_channel_eq_delay);
>
> +/* Per DP 2.0 Errata */
> +int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux)
> +{
> + int unit;
> + u8 val;
> +
> + if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, )
> != 1) {
> + drm_err(aux->drm_dev, "%s: failed rd interval read\n",
> + aux->name);
> + /* default to max */
> + val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
> + }
> +
> + unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2;
> + val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
> +
> + return (val + 1) * unit * 1000;
> +}
> +EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval);
> +
> void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
> const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> {
> diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h
> index 98d020835b49..aa73dfc817ff 100644
> --- a/include/drm/dp/drm_dp_helper.h
> +++ b/include/drm/dp/drm_dp_helper.h
> @@ -1112,6 +1112,7 @@ struct drm_panel;
> # define DP_UHBR13_5 (1 << 2)
>
> #define DP_128B132B_TRAINING_AUX_RD_INTERVAL0x2216 /*
> 2.0 */
> +# define DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT (1 << 7)
> # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK 0x7f
> # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US0x00
> # define DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS 0x01
> @@ -1549,6 +1550,8 @@ void drm_dp_link_train_channel_eq_delay(const struct
> drm_dp_aux *aux,
> void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
> const u8
> caps[DP_LTTPR_PHY_CAP_SIZE]);
>
> +int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux);
> +
> u8 drm_dp_link_rate_to_bw_code(int link_rate);
> int drm_dp_bw_code_to_link_rate(u8 link_bw);
>
> --
> 2.30.2
--
Ville Syrjälä
Intel
[Intel-gfx] [PATCH] drm/i915/adlp: Fix TypeC PHY-ready status readout
The TCSS_DDI_STATUS register is indexed by tc_port not by the FIA port
index, fix this up. This only caused an issue on TC#3/4 ports in legacy
mode, as in all other cases the two indices either match (on TC#1/2) or
the TCSS_DDI_STATUS_READY flag is set regardless of something being
connected or not (on TC#1/2/3/4 in dp-alt and tbt-alt modes).
Reported-and-tested-by: Chia-Lin Kao (AceLan)
Fixes: 55ce306c2aa1 ("drm/i915/adl_p: Implement TC sequences")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4698
Cc: José Roberto de Souza
Cc: # v5.14+
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/display/intel_tc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
b/drivers/gpu/drm/i915/display/intel_tc.c
index 4eefe7b0bb263..3291124a99e5a 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -346,10 +346,11 @@ static bool icl_tc_phy_status_complete(struct
intel_digital_port *dig_port)
static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
struct intel_uncore *uncore = >uncore;
u32 val;
- val = intel_uncore_read(uncore,
TCSS_DDI_STATUS(dig_port->tc_phy_fia_idx));
+ val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port));
if (val == 0x) {
drm_dbg_kms(>drm,
"Port %s: PHY in TCCOLD, assuming not complete\n",
--
2.27.0
Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix oops due to missing stack depot
On Wed, Jan 26, 2022 at 10:15:38AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We call __save_depot_stack() unconditionally so the stack depot
> must always be initialized or else we'll oops on platforms without
> runtime pm support.
>
> Presumably we've not seen this in CI due to stack_depot_init()
> already getting called via drm_mm_init()+CONFIG_DRM_DEBUG_MM.
>
> Cc: Vlastimil Babka
> Cc: Dmitry Vyukov
> Cc: Marco Elver # stackdepot
> Cc: Chris Wilson
> Cc: Imre Deak
> Fixes: 2dba5eb1c73b ("lib/stackdepot: allow optional init and stack_table
> allocation by kvmalloc()")
> Signed-off-by: Ville Syrjälä
Reviewed-by: Imre Deak
> ---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 53f1ccb78849..64c2708efc9e 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -68,9 +68,7 @@ static noinline depot_stack_handle_t
> __save_depot_stack(void)
> static void init_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm)
> {
> spin_lock_init(>debug.lock);
> -
> - if (rpm->available)
> - stack_depot_init();
> + stack_depot_init();
> }
>
> static noinline depot_stack_handle_t
> --
> 2.34.1
>
Re: [Intel-gfx] [PATCH] drm/i915: Lock dpt_obj around set_cache_level, v2.
On 1/26/22 9:37 AM, Maarten Lankhorst wrote:
set_cache_level may unbind the object, which will result in the below
lockdep splat:
<6> [184.578145] [IGT] kms_addfb_basic: starting subtest
addfb25-framebuffer-vs-set-tiling
<4> [184.578220] [ cut here ]
<4> [184.578221] WARN_ON(debug_locks &&
!(lock_is_held(&(&((obj)->base.resv)->lock.base)->dep_map) != 0))
<4> [184.578237] WARNING: CPU: 6 PID: 5544 at
drivers/gpu/drm/i915/i915_gem.c:123 i915_gem_object_unbind+0x4a9/0x510 [i915]
<4> [184.578323] Modules linked in: vgem drm_shmem_helper snd_hda_codec_hdmi
i915 mei_hdcp x86_pkg_temp_thermal snd_hda_intel coretemp crct10dif_pclmul
snd_intel_dspcfg crc32_pclmul ttm snd_hda_codec ghash_clmulni_intel snd_hwdep
drm_kms_helper snd_hda_core e1000e mei_me syscopyarea ptp snd_pcm sysfillrect mei
pps_core sysimgblt fb_sys_fops prime_numbers intel_lpss_pci smsc75xx usbnet mii
<4> [184.578349] CPU: 6 PID: 5544 Comm: kms_addfb_basic Not tainted
5.16.0-CI-Patchwork_22006+ #1
<4> [184.578351] Hardware name: Intel Corporation Alder Lake Client
Platform/AlderLake-P DDR4 RVP, BIOS ADLPFWI1.R00.2422.A00.2110131104 10/13/2021
<4> [184.578352] RIP: 0010:i915_gem_object_unbind+0x4a9/0x510 [i915]
<4> [184.578424] Code: 00 be ff ff ff ff 48 8d 78 68 e8 a2 6e 2b e1 85 c0 0f 85 b1 fb
ff ff 48 c7 c6 48 37 9e a0 48 c7 c7 d9 fc a1 a0 e8 a3 54 26 e1 <0f> 0b e9 97 fb ff ff
31 ed 48 8b 5c 24 58 65 48 33 1c 25 28 00 00
<4> [184.578426] RSP: 0018:c900013b3b68 EFLAGS: 00010286
<4> [184.578428] RAX: RBX: c900013b3bb0 RCX:
0001
<4> [184.578429] RDX: 8001 RSI: 8230b42d RDI:
<4> [184.578430] RBP: 888120e1 R08: R09:
c0007fff
<4> [184.578431] R10: 0001 R11: c900013b3980 R12:
8881176ea740
<4> [184.578432] R13: 888120e1 R14: R15:
0001
<4> [184.578433] FS: 7f65074f5e40() GS:8f30()
knlGS:
<4> [184.578435] CS: 0010 DS: ES: CR0: 80050033
<4> [184.578436] CR2: 7fff4420ede8 CR3: 00010c2f2005 CR4:
00770ee0
<4> [184.578437] PKRU: 5554
<4> [184.578438] Call Trace:
<4> [184.578439]
<4> [184.578440] ? dma_resv_iter_first_unlocked+0x78/0xf0
<4> [184.578447] intel_dpt_create+0x88/0x220 [i915]
<4> [184.578530] intel_framebuffer_init+0x5b8/0x620 [i915]
<4> [184.578612] intel_framebuffer_create+0x3d/0x60 [i915]
<4> [184.578691] intel_user_framebuffer_create+0x18f/0x2c0 [i915]
<4> [184.578775] drm_internal_framebuffer_create+0x36d/0x4c0
<4> [184.578779] drm_mode_addfb2+0x2f/0xd0
<4> [184.578781] ? drm_mode_addfb_ioctl+0x10/0x10
<4> [184.578784] drm_ioctl_kernel+0xac/0x140
<4> [184.578787] drm_ioctl+0x201/0x3d0
<4> [184.578789] ? drm_mode_addfb_ioctl+0x10/0x10
<4> [184.578796] __x64_sys_ioctl+0x6a/0xa0
<4> [184.578800] do_syscall_64+0x37/0xb0
<4> [184.578803] entry_SYSCALL_64_after_hwframe+0x44/0xae
<4> [184.578805] RIP: 0033:0x7f6506736317
<4> [184.578807] Code: b3 66 90 48 8b 05 71 4b 2d 00 64 c7 00 26 00 00 00 48 c7 c0 ff
ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73
01 c3 48 8b 0d 41 4b 2d 00 f7 d8 64 89 01 48
<4> [184.578808] RSP: 002b:7fff44211a98 EFLAGS: 0246 ORIG_RAX:
0010
<4> [184.578810] RAX: ffda RBX: 0006 RCX:
7f6506736317
<4> [184.578811] RDX: 7fff44211b30 RSI: c06864b8 RDI:
0006
<4> [184.578812] RBP: 7fff44211b30 R08: 7fff44311170 R09:
<4> [184.578813] R10: 0008 R11: 0246 R12:
c06864b8
<4> [184.578813] R13: 0006 R14: R15:
<4> [184.578819]
<4> [184.578820] irq event stamp: 47931
<4> [184.578821] hardirqs last enabled at (47937): []
__up_console_sem+0x62/0x70
<4> [184.578824] hardirqs last disabled at (47942): []
__up_console_sem+0x47/0x70
<4> [184.578826] softirqs last enabled at (47340): []
__do_softirq+0x32d/0x493
<4> [184.578828] softirqs last disabled at (47335): []
irq_exit_rcu+0xa6/0xe0
<4> [184.578830] ---[ end trace f17ec219f892c7d4 ]---
Changes since v1:
- Fix intel_pin_fb_obj_dpt too.
Fixes: 0f341974cbc2 ("drm/i915: Add i915_vma_unbind_unlocked, and take obj lock for
i915_vma_unbind, v2.")
Signed-off-by: Maarten Lankhorst
Testcase: kms_addfb_basic
---
drivers/gpu/drm/i915/display/intel_dpt.c| 6 +-
drivers/gpu/drm/i915/display/intel_fb_pin.c | 6 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c
b/drivers/gpu/drm/i915/display/intel_dpt.c
index 63a83d5f85a1..c2f8f853db90 100644
--- a/drivers/gpu/drm/i915/display/intel_dpt.c
+++ b/drivers/gpu/drm/i915/display/intel_dpt.c
@@ -253,7 +253,11 @@ intel_dpt_create(struct intel_framebuffer *fb)
if (IS_ERR(dpt_obj))
return ERR_CAST(dpt_obj);
- ret =
Re: [Intel-gfx] [PATCH 6/9] drm/i915: Clean up PIPESRC defines
On Fri, 12 Nov 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_GENMASK() & co. when dealing with PIPESRC.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c| 4 ++--
> drivers/gpu/drm/i915/display/intel_display.c | 7 ---
> drivers/gpu/drm/i915/i915_reg.h | 4
> 3 files changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
> b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 2194f74101ae..f586e39cb378 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -1048,8 +1048,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
> plane_config->base = base;
>
> val = intel_de_read(dev_priv, PIPESRC(pipe));
> - fb->width = ((val >> 16) & 0xfff) + 1;
> - fb->height = ((val >> 0) & 0xfff) + 1;
I guess the mask width change is worth noting in the commit message.
Reviewed-by: Jani Nikula
> + fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1;
> + fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1;
>
> val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));
> fb->pitches[0] = val & 0xffc0;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 4e29032b29d6..e1959a17805c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3236,7 +3236,8 @@ static void intel_set_pipe_src_size(const struct
> intel_crtc_state *crtc_state)
>* always be the user's requested size.
>*/
> intel_de_write(dev_priv, PIPESRC(pipe),
> -((crtc_state->pipe_src_w - 1) << 16) |
> (crtc_state->pipe_src_h - 1));
> +PIPESRC_WIDTH(crtc_state->pipe_src_w - 1) |
> +PIPESRC_HEIGHT(crtc_state->pipe_src_h - 1));
> }
>
> static bool intel_pipe_is_interlaced(const struct intel_crtc_state
> *crtc_state)
> @@ -3307,8 +3308,8 @@ static void intel_get_pipe_src_size(struct intel_crtc
> *crtc,
> u32 tmp;
>
> tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
> - pipe_config->pipe_src_h = (tmp & 0x) + 1;
> - pipe_config->pipe_src_w = ((tmp >> 16) & 0x) + 1;
> + pipe_config->pipe_src_w = REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1;
> + pipe_config->pipe_src_h = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1;
> }
>
> static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index eea009e76e15..211e2b415e50 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4476,6 +4476,10 @@ enum {
> #define _VSYNC_A 0x60014
> #define _EXITLINE_A 0x60018
> #define _PIPEASRC0x6001c
> +#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
> +#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
> +#define PIPESRC_HEIGHT_MASKREG_GENMASK(15, 0)
> +#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
> #define _BCLRPAT_A 0x60020
> #define _VSYNCSHIFT_A0x60028
> #define _PIPE_MULT_A 0x6002c
--
Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH v5 01/10] drm/i915/guc: Update GuC ADS size for error capture lists
Update GuC ADS size allocation to include space for
the lists of error state capture register descriptors.
Also, populate the lists of registers we want GuC to report back to
Host on engine reset events. This list should include global,
engine-class and engine-instance registers for every engine-class
type on the current hardware.
NOTE: Start with a sample table of register lists to layout the
framework before adding real registers in subsequent patch.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 36 ++
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 13 +-
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 11 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 36 +-
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 450 ++
.../gpu/drm/i915/gt/uc/intel_guc_capture.h| 20 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 17 +
8 files changed, 555 insertions(+), 29 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
create mode 100644 drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index a26e6736bebb..236bcd6cd8ea 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -183,6 +183,7 @@ i915-y += gt/uc/intel_uc.o \
gt/uc/intel_uc_fw.o \
gt/uc/intel_guc.o \
gt/uc/intel_guc_ads.o \
+ gt/uc/intel_guc_capture.o \
gt/uc/intel_guc_ct.o \
gt/uc/intel_guc_debugfs.o \
gt/uc/intel_guc_fw.o \
diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
new file mode 100644
index ..15b8c02b8a76
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021-2021 Intel Corporation
+ */
+
+#ifndef _INTEL_GUC_CAPTURE_FWIF_H
+#define _INTEL_GUC_CAPTURE_FWIF_H
+
+#include
+#include "intel_guc_fwif.h"
+
+struct intel_guc;
+
+struct __guc_mmio_reg_descr {
+ i915_reg_t reg;
+ u32 flags;
+ u32 mask;
+ const char *regname;
+};
+
+struct __guc_mmio_reg_descr_group {
+ struct __guc_mmio_reg_descr *list;
+ u32 num_regs;
+ u32 owner; /* see enum guc_capture_owner */
+ u32 type; /* see enum guc_capture_type */
+ u32 engine; /* as per MAX_ENGINE_CLASS */
+};
+
+struct __guc_state_capture_priv {
+ struct __guc_mmio_reg_descr_group *reglists;
+ u16
num_instance_regs[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
+ u16 num_class_regs[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
+ u16 num_global_regs[GUC_CAPTURE_LIST_INDEX_MAX];
+};
+
+#endif /* _INTEL_GUC_CAPTURE_FWIF_H */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index ba2a67f9e500..d035a3ba8700 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -8,8 +8,9 @@
#include "gt/intel_gt_irq.h"
#include "gt/intel_gt_pm_irq.h"
#include "intel_guc.h"
-#include "intel_guc_slpc.h"
#include "intel_guc_ads.h"
+#include "intel_guc_capture.h"
+#include "intel_guc_slpc.h"
#include "intel_guc_submission.h"
#include "i915_drv.h"
#include "i915_irq.h"
@@ -361,9 +362,14 @@ int intel_guc_init(struct intel_guc *guc)
if (ret)
goto err_fw;
- ret = intel_guc_ads_create(guc);
+ ret = intel_guc_capture_init(guc);
if (ret)
goto err_log;
+
+ ret = intel_guc_ads_create(guc);
+ if (ret)
+ goto err_capture;
+
GEM_BUG_ON(!guc->ads_vma);
ret = intel_guc_ct_init(>ct);
@@ -402,6 +408,8 @@ int intel_guc_init(struct intel_guc *guc)
intel_guc_ct_fini(>ct);
err_ads:
intel_guc_ads_destroy(guc);
+err_capture:
+ intel_guc_capture_destroy(guc);
err_log:
intel_guc_log_destroy(>log);
err_fw:
@@ -429,6 +437,7 @@ void intel_guc_fini(struct intel_guc *guc)
intel_guc_ct_fini(>ct);
intel_guc_ads_destroy(guc);
+ intel_guc_capture_destroy(guc);
intel_guc_log_destroy(>log);
intel_uc_fw_fini(>fw);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 697d9d66acef..4e819853ec2e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -9,18 +9,19 @@
#include
#include
-#include "intel_uncore.h"
+#include "intel_guc_ct.h"
#include "intel_guc_fw.h"
#include "intel_guc_fwif.h"
-#include "intel_guc_ct.h"
#include "intel_guc_log.h"
#include "intel_guc_reg.h"
#include "intel_guc_slpc_types.h"
#include "intel_uc_fw.h"
+#include "intel_uncore.h"
#include "i915_utils.h"
#include "i915_vma.h"
struct __guc_ads_blob;
+struct __guc_state_capture_priv;
/**
*
[Intel-gfx] [PATCH v5 02/10] drm/i915/guc: Add XE_LP registers for GuC error state capture.
Add device specific tables and register lists to cover different engines
class types for GuC error state capture for XE_LP products.
Also, add runtime allocation and freeing of extended register lists
for registers that need steering identifiers that depend on
the detected HW config.
Signed-off-by: Alan Previn
---
drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h | 2 +
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 207 +++---
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4 +-
3 files changed, 180 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
index 15b8c02b8a76..a2f97d04ff18 100644
--- a/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
+++ b/drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h
@@ -24,6 +24,8 @@ struct __guc_mmio_reg_descr_group {
u32 owner; /* see enum guc_capture_owner */
u32 type; /* see enum guc_capture_type */
u32 engine; /* as per MAX_ENGINE_CLASS */
+ int num_ext;
+ struct __guc_mmio_reg_descr *ext;
};
struct __guc_state_capture_priv {
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 06873d617b8b..b6882074fc8d 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -19,40 +19,101 @@
* NOTE: For engine-registers, GuC only needs the register offsets
* from the engine-mmio-base
*/
+#define COMMON_GEN12BASE_GLOBAL() \
+ {GEN12_FAULT_TLB_DATA0,0, 0, "GEN12_FAULT_TLB_DATA0"}, \
+ {GEN12_FAULT_TLB_DATA1,0, 0, "GEN12_FAULT_TLB_DATA1"}, \
+ {FORCEWAKE_MT, 0, 0, "FORCEWAKE_MT"}, \
+ {GEN12_AUX_ERR_DBG,0, 0, "GEN12_AUX_ERR_DBG"}, \
+ {GEN12_GAM_DONE, 0, 0, "GEN12_GAM_DONE"}, \
+ {GEN12_RING_FAULT_REG, 0, 0, "GEN12_RING_FAULT_REG"}
+
+#define COMMON_GEN12BASE_ENGINE_INSTANCE() \
+ {RING_PSMI_CTL(0), 0, 0, "RING_PSMI_CTL"}, \
+ {RING_ESR(0), 0, 0, "RING_ESR"}, \
+ {RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LOW32"}, \
+ {RING_DMA_FADD_UDW(0), 0, 0, "RING_DMA_FADD_UP32"}, \
+ {RING_IPEIR(0),0, 0, "RING_IPEIR"}, \
+ {RING_IPEHR(0),0, 0, "RING_IPEHR"}, \
+ {RING_INSTPS(0), 0, 0, "RING_INSTPS"}, \
+ {RING_BBADDR(0), 0, 0, "RING_BBADDR_LOW32"}, \
+ {RING_BBADDR_UDW(0), 0, 0, "RING_BBADDR_UP32"}, \
+ {RING_BBSTATE(0), 0, 0, "RING_BBSTATE"}, \
+ {CCID(0), 0, 0, "CCID"}, \
+ {RING_ACTHD(0),0, 0, "RING_ACTHD_LOW32"}, \
+ {RING_ACTHD_UDW(0),0, 0, "RING_ACTHD_UP32"}, \
+ {RING_INSTPM(0), 0, 0, "RING_INSTPM"}, \
+ {RING_NOPID(0),0, 0, "RING_NOPID"}, \
+ {RING_START(0),0, 0, "RING_START"}, \
+ {RING_HEAD(0), 0, 0, "RING_HEAD"}, \
+ {RING_TAIL(0), 0, 0, "RING_TAIL"}, \
+ {RING_CTL(0), 0, 0, "RING_CTL"}, \
+ {RING_MI_MODE(0), 0, 0, "RING_MI_MODE"}, \
+ {RING_CONTEXT_CONTROL(0), 0, 0, "RING_CONTEXT_CONTROL"}, \
+ {RING_INSTDONE(0), 0, 0, "RING_INSTDONE"}, \
+ {RING_HWS_PGA(0), 0, 0, "RING_HWS_PGA"}, \
+ {RING_MODE_GEN7(0),0, 0, "RING_MODE_GEN7"}, \
+ {GEN8_RING_PDP_LDW(0, 0), 0, 0, "GEN8_RING_PDP0_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 0), 0, 0, "GEN8_RING_PDP0_UDW"}, \
+ {GEN8_RING_PDP_LDW(0, 1), 0, 0, "GEN8_RING_PDP1_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 1), 0, 0, "GEN8_RING_PDP1_UDW"}, \
+ {GEN8_RING_PDP_LDW(0, 2), 0, 0, "GEN8_RING_PDP2_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 2), 0, 0, "GEN8_RING_PDP2_UDW"}, \
+ {GEN8_RING_PDP_LDW(0, 3), 0, 0, "GEN8_RING_PDP3_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 3), 0, 0, "GEN8_RING_PDP3_UDW"}
+
+#define COMMON_GEN12BASE_HAS_EU() \
+ {EIR, 0, 0, "EIR"}
+
+#define COMMON_GEN12BASE_RENDER() \
+ {GEN7_SC_INSTDONE, 0, 0, "GEN7_SC_INSTDONE"}, \
+ {GEN12_SC_INSTDONE_EXTRA, 0, 0, "GEN12_SC_INSTDONE_EXTRA"}, \
+ {GEN12_SC_INSTDONE_EXTRA2, 0, 0, "GEN12_SC_INSTDONE_EXTRA2"}
+
+#define COMMON_GEN12BASE_VEC() \
+ {GEN12_SFC_DONE(0),0, 0, "GEN12_SFC_DONE0"}, \
+ {GEN12_SFC_DONE(1),0, 0, "GEN12_SFC_DONE1"}, \
+ {GEN12_SFC_DONE(2),0, 0, "GEN12_SFC_DONE2"}, \
+ {GEN12_SFC_DONE(3),0, 0, "GEN12_SFC_DONE3"}
+
/* XE_LPD - Global */
static struct __guc_mmio_reg_descr xe_lpd_global_regs[] = {
- {GEN12_RING_FAULT_REG, 0, 0, "GEN12_RING_FAULT_REG"}
+ COMMON_GEN12BASE_GLOBAL(),
};
/*
[Intel-gfx] [PATCH v5 03/10] drm/i915/guc: Add DG2 registers for GuC error state capture.
Add additional DG2 registers for GuC error state capture.
Signed-off-by: Alan Previn
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 64 ++-
1 file changed, 49 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index b6882074fc8d..19719daffed4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -179,19 +179,23 @@ static struct __ext_steer_reg xelpd_extregs[] = {
{"GEN7_ROW_INSTDONE", GEN7_ROW_INSTDONE}
};
+static struct __ext_steer_reg xehpg_extregs[] = {
+ {"XEHPG_INSTDONE_GEOM_SVG", XEHPG_INSTDONE_GEOM_SVG}
+};
+
static void
-guc_capture_alloc_steered_list_xelpd(struct intel_guc *guc,
-struct __guc_mmio_reg_descr_group *lists)
+guc_capture_alloc_steered_list_xe_lpd_hpg(struct intel_guc *guc,
+ struct __guc_mmio_reg_descr_group
*lists,
+ u32 ipver)
{
struct intel_gt *gt = guc_to_gt(guc);
struct drm_i915_private *i915 = guc_to_gt(guc)->i915;
struct sseu_dev_info *sseu;
- int slice, subslice, i, num_tot_regs = 0;
+ int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0;
struct __guc_mmio_reg_descr_group *list;
struct __guc_mmio_reg_descr *extarray;
- int num_steer_regs = ARRAY_SIZE(xelpd_extregs);
- /* In XE_LP we only care about render-class steering registers during
error-capture */
+ /* In XE_LP / HPG we only have render-class steering registers during
error-capture */
list = guc_capture_get_one_list(lists, GUC_CAPTURE_LIST_INDEX_PF,
GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS,
GUC_RENDER_CLASS);
if (!list)
@@ -200,10 +204,21 @@ guc_capture_alloc_steered_list_xelpd(struct intel_guc
*guc,
if (list->ext)
return; /* already populated */
+ num_steer_regs = ARRAY_SIZE(xelpd_extregs);
+ if (ipver >= IP_VER(12, 55))
+ num_steer_regs += ARRAY_SIZE(xehpg_extregs);
+
sseu = >info.sseu;
- for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
- num_tot_regs += num_steer_regs;
+ if (ipver >= IP_VER(12, 50)) {
+ for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice,
subslice) {
+ num_tot_regs += num_steer_regs;
+ }
+ } else {
+ for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
+ num_tot_regs += num_steer_regs;
+ }
}
+
if (!num_tot_regs)
return;
@@ -212,15 +227,31 @@ guc_capture_alloc_steered_list_xelpd(struct intel_guc
*guc,
return;
extarray = list->ext;
- for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
- for (i = 0; i < num_steer_regs; i++) {
- extarray->reg = xelpd_extregs[i].reg;
- extarray->flags = FIELD_PREP(GUC_REGSET_STEERING_GROUP,
slice);
- extarray->flags |=
FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, subslice);
- extarray->regname = xelpd_extregs[i].name;
- ++extarray;
+
+#define POPULATE_NEXT_EXTREG(ext, list, idx, slicenum, subslicenum) \
+ { \
+ (ext)->reg = list[idx].reg; \
+ (ext)->flags = FIELD_PREP(GUC_REGSET_STEERING_GROUP, slicenum);
\
+ (ext)->flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE,
subslicenum); \
+ (ext)->regname = xelpd_extregs[i].name; \
+ ++(ext); \
+ }
+ if (ipver >= IP_VER(12, 50)) {
+ for_each_instdone_gslice_dss_xehp(i915, sseu, iter, slice,
subslice) {
+ for (i = 0; i < ARRAY_SIZE(xelpd_extregs); i++)
+ POPULATE_NEXT_EXTREG(extarray, xelpd_extregs,
i, slice, subslice)
+ for (i = 0; i < ARRAY_SIZE(xehpg_extregs) && ipver >=
IP_VER(12, 55);
+i++)
+ POPULATE_NEXT_EXTREG(extarray, xehpg_extregs,
i, slice, subslice)
+ }
+ } else {
+ for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
+ for (i = 0; i < num_steer_regs; i++)
+ POPULATE_NEXT_EXTREG(extarray, xelpd_extregs,
i, slice, subslice)
}
}
+#undef POPULATE_NEXT_EXTREG
+
list->num_ext = num_tot_regs;
}
@@ -237,7 +268,10 @@ guc_capture_get_device_reglist(struct intel_guc *guc)
* these at init time based on hw config add it as an extension
* list at the end of the pre-populated render list.
*/
- guc_capture_alloc_steered_list_xelpd(guc,
[Intel-gfx] [PATCH v5 09/10] drm/i915/guc: Follow legacy register names
Before we print the GuC provided register dumps, modify the
register tables to use string names as per the legacy error
capture execlist codes.
Signed-off-by: Alan Previn
---
.../gpu/drm/i915/gt/uc/intel_guc_capture.c| 70 +--
1 file changed, 35 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
index 2f5dc413dddc..506496058daf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
@@ -22,7 +22,7 @@
* from the engine-mmio-base
*/
#define COMMON_BASE_GLOBAL() \
- {FORCEWAKE_MT, 0, 0, "FORCEWAKE_MT"}
+ {FORCEWAKE_MT, 0, 0, "FORCEWAKE"}
#define COMMON_GEN9BASE_GLOBAL() \
{GEN8_FAULT_TLB_DATA0, 0, 0, "GEN8_FAULT_TLB_DATA0"}, \
@@ -34,43 +34,43 @@
#define COMMON_GEN12BASE_GLOBAL() \
{GEN12_FAULT_TLB_DATA0,0, 0, "GEN12_FAULT_TLB_DATA0"}, \
{GEN12_FAULT_TLB_DATA1,0, 0, "GEN12_FAULT_TLB_DATA1"}, \
- {GEN12_AUX_ERR_DBG,0, 0, "GEN12_AUX_ERR_DBG"}, \
- {GEN12_GAM_DONE, 0, 0, "GEN12_GAM_DONE"}, \
- {GEN12_RING_FAULT_REG, 0, 0, "GEN12_RING_FAULT_REG"}
+ {GEN12_AUX_ERR_DBG,0, 0, "AUX_ERR_DBG"}, \
+ {GEN12_GAM_DONE, 0, 0, "GAM_DONE"}, \
+ {GEN12_RING_FAULT_REG, 0, 0, "FAULT_REG"}
#define COMMON_BASE_ENGINE_INSTANCE() \
- {RING_PSMI_CTL(0), 0, 0, "RING_PSMI_CTL"}, \
- {RING_ESR(0), 0, 0, "RING_ESR"}, \
- {RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LOW32"}, \
- {RING_DMA_FADD_UDW(0), 0, 0, "RING_DMA_FADD_UP32"}, \
- {RING_IPEIR(0),0, 0, "RING_IPEIR"}, \
- {RING_IPEHR(0),0, 0, "RING_IPEHR"}, \
- {RING_INSTPS(0), 0, 0, "RING_INSTPS"}, \
+ {RING_PSMI_CTL(0), 0, 0, "RC PSMI"}, \
+ {RING_ESR(0), 0, 0, "ESR"}, \
+ {RING_DMA_FADD(0), 0, 0, "RING_DMA_FADD_LDW"}, \
+ {RING_DMA_FADD_UDW(0), 0, 0, "RING_DMA_FADD_UDW"}, \
+ {RING_IPEIR(0),0, 0, "IPEIR"}, \
+ {RING_IPEHR(0),0, 0, "IPEHR"}, \
+ {RING_INSTPS(0), 0, 0, "INSTPS"}, \
{RING_BBADDR(0), 0, 0, "RING_BBADDR_LOW32"}, \
{RING_BBADDR_UDW(0), 0, 0, "RING_BBADDR_UP32"}, \
- {RING_BBSTATE(0), 0, 0, "RING_BBSTATE"}, \
+ {RING_BBSTATE(0), 0, 0, "BB_STATE"}, \
{CCID(0), 0, 0, "CCID"}, \
- {RING_ACTHD(0),0, 0, "RING_ACTHD_LOW32"}, \
- {RING_ACTHD_UDW(0),0, 0, "RING_ACTHD_UP32"}, \
- {RING_INSTPM(0), 0, 0, "RING_INSTPM"}, \
+ {RING_ACTHD(0),0, 0, "ACTHD_LDW"}, \
+ {RING_ACTHD_UDW(0),0, 0, "ACTHD_UDW"}, \
+ {RING_INSTPM(0), 0, 0, "INSTPM"}, \
+ {RING_INSTDONE(0), 0, 0, "INSTDONE"}, \
{RING_NOPID(0),0, 0, "RING_NOPID"}, \
- {RING_START(0),0, 0, "RING_START"}, \
- {RING_HEAD(0), 0, 0, "RING_HEAD"}, \
- {RING_TAIL(0), 0, 0, "RING_TAIL"}, \
- {RING_CTL(0), 0, 0, "RING_CTL"}, \
- {RING_MI_MODE(0), 0, 0, "RING_MI_MODE"}, \
+ {RING_START(0),0, 0, "START"}, \
+ {RING_HEAD(0), 0, 0, "HEAD"}, \
+ {RING_TAIL(0), 0, 0, "TAIL"}, \
+ {RING_CTL(0), 0, 0, "CTL"}, \
+ {RING_MI_MODE(0), 0, 0, "MODE"}, \
{RING_CONTEXT_CONTROL(0), 0, 0, "RING_CONTEXT_CONTROL"}, \
- {RING_INSTDONE(0), 0, 0, "RING_INSTDONE"}, \
- {RING_HWS_PGA(0), 0, 0, "RING_HWS_PGA"}, \
- {RING_MODE_GEN7(0),0, 0, "RING_MODE_GEN7"}, \
- {GEN8_RING_PDP_LDW(0, 0), 0, 0, "GEN8_RING_PDP0_LDW"}, \
- {GEN8_RING_PDP_UDW(0, 0), 0, 0, "GEN8_RING_PDP0_UDW"}, \
- {GEN8_RING_PDP_LDW(0, 1), 0, 0, "GEN8_RING_PDP1_LDW"}, \
- {GEN8_RING_PDP_UDW(0, 1), 0, 0, "GEN8_RING_PDP1_UDW"}, \
- {GEN8_RING_PDP_LDW(0, 2), 0, 0, "GEN8_RING_PDP2_LDW"}, \
- {GEN8_RING_PDP_UDW(0, 2), 0, 0, "GEN8_RING_PDP2_UDW"}, \
- {GEN8_RING_PDP_LDW(0, 3), 0, 0, "GEN8_RING_PDP3_LDW"}, \
- {GEN8_RING_PDP_UDW(0, 3), 0, 0, "GEN8_RING_PDP3_UDW"}
+ {RING_HWS_PGA(0), 0, 0, "HWS"}, \
+ {RING_MODE_GEN7(0),0, 0, "GFX_MODE"}, \
+ {GEN8_RING_PDP_LDW(0, 0), 0, 0, "PDP0_LDW"}, \
+ {GEN8_RING_PDP_UDW(0, 0), 0, 0, "PDP0_UDW"}, \
+ {GEN8_RING_PDP_LDW(0, 1), 0, 0, "PDP1_LDW"}, \
+
[Intel-gfx] [RFC PATCH] drm/i915: Remove all frontbuffer tracking calls from the gem code
We should now rely on userspace doing dirtyfb. There is no
need to have separate frontbuffer tracking hooks in gem code.
This patch is removing all frontbuffer tracking calls from the gem
code.
Cc: Ville Syrjälä
Cc: Jani Nikula
Cc: Daniel Vetter
Signed-off-by: Jouni Högander
---
drivers/gpu/drm/i915/display/intel_overlay.c | 2 --
drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 2 --
drivers/gpu/drm/i915/gem/i915_gem_domain.c | 5
drivers/gpu/drm/i915/gem/i915_gem_object.c | 24
drivers/gpu/drm/i915/gem/i915_gem_object.h | 16 -
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 7 --
drivers/gpu/drm/i915/i915_gem.c | 5
7 files changed, 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c
b/drivers/gpu/drm/i915/display/intel_overlay.c
index 5358f03b52db..fc2691dac278 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -809,8 +809,6 @@ static int intel_overlay_do_put_image(struct intel_overlay
*overlay,
goto out_pin_section;
}
- i915_gem_object_flush_frontbuffer(new_bo, ORIGIN_DIRTYFB);
-
if (!overlay->active) {
const struct intel_crtc_state *crtc_state =
overlay->crtc->config;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
index 8a248003dfae..115e6d877e38 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_clflush.c
@@ -20,8 +20,6 @@ static void __do_clflush(struct drm_i915_gem_object *obj)
{
GEM_BUG_ON(!i915_gem_object_has_pages(obj));
drm_clflush_sg(obj->mm.pages);
-
- i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
}
static void clflush_work(struct dma_fence_work *base)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
index 26532c07d467..ab1fc2d930e1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_domain.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_domain.c
@@ -63,7 +63,6 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned
int flush_domains)
}
spin_unlock(>vma.lock);
- i915_gem_object_flush_frontbuffer(obj, ORIGIN_CPU);
break;
case I915_GEM_DOMAIN_WC:
@@ -615,9 +614,6 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void
*data,
out_unlock:
i915_gem_object_unlock(obj);
- if (!err && write_domain)
- i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
-
out:
i915_gem_object_put(obj);
return err;
@@ -728,7 +724,6 @@ int i915_gem_object_prepare_write(struct
drm_i915_gem_object *obj,
}
out:
- i915_gem_object_invalidate_frontbuffer(obj, ORIGIN_CPU);
obj->mm.dirty = true;
/* return with the pages pinned */
return 0;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
b/drivers/gpu/drm/i915/gem/i915_gem_object.c
index 1a9e1f940a7d..f7ba66deb923 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
@@ -394,30 +394,6 @@ static void i915_gem_free_object(struct drm_gem_object
*gem_obj)
queue_delayed_work(i915->wq, >mm.free_work, 0);
}
-void __i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
-enum fb_op_origin origin)
-{
- struct intel_frontbuffer *front;
-
- front = __intel_frontbuffer_get(obj);
- if (front) {
- intel_frontbuffer_flush(front, origin);
- intel_frontbuffer_put(front);
- }
-}
-
-void __i915_gem_object_invalidate_frontbuffer(struct drm_i915_gem_object *obj,
- enum fb_op_origin origin)
-{
- struct intel_frontbuffer *front;
-
- front = __intel_frontbuffer_get(obj);
- if (front) {
- intel_frontbuffer_invalidate(front, origin);
- intel_frontbuffer_put(front);
- }
-}
-
static void
i915_gem_object_read_from_page_kmap(struct drm_i915_gem_object *obj, u64
offset, void *dst, int size)
{
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
b/drivers/gpu/drm/i915/gem/i915_gem_object.h
index 02c37fe4a535..d7a08172b239 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h
@@ -578,22 +578,6 @@ void __i915_gem_object_flush_frontbuffer(struct
drm_i915_gem_object *obj,
void __i915_gem_object_invalidate_frontbuffer(struct drm_i915_gem_object *obj,
enum fb_op_origin origin);
-static inline void
-i915_gem_object_flush_frontbuffer(struct drm_i915_gem_object *obj,
- enum fb_op_origin origin)
-{
- if (unlikely(rcu_access_pointer(obj->frontbuffer)))
- __i915_gem_object_flush_frontbuffer(obj,
[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Fix oops due to missing stack depot
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix oops due to missing stack depot
URL : https://patchwork.freedesktop.org/series/99353/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11141 -> Patchwork_22109
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/index.html
Participating hosts (44 -> 43)
--
Additional (2): fi-kbl-soraka bat-jsl-2
Missing(3): fi-ctg-p8600 fi-bsw-cyan fi-hsw-4200u
Known issues
Here are the changes found in Patchwork_22109 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@amdgpu/amd_prime@amd-to-i915:
- fi-pnv-d510:NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/fi-pnv-d510/igt@amdgpu/amd_pr...@amd-to-i915.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-soraka: NOTRUN -> [SKIP][3] ([fdo#109271]) +8 similar issues
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/fi-kbl-soraka/igt@gem_exec_fence@basic-b...@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/fi-kbl-soraka/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3
similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/fi-kbl-soraka/igt@gem_lmem_swapp...@basic.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [PASS][6] -> [INCOMPLETE][7] ([i915#2940])
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/fi-bsw-n3050/igt@i915_selftest@l...@execlists.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][8] ([i915#1886] / [i915#2291])
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770:[PASS][9] -> [INCOMPLETE][10] ([i915#3303])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/fi-hsw-4770/igt@i915_selftest@l...@hangcheck.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-kbl-soraka: NOTRUN -> [SKIP][11] ([fdo#109271] / [fdo#111827]) +8
similar issues
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/fi-kbl-soraka/igt@kms_chamel...@common-hpd-after-suspend.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: [PASS][12] -> [DMESG-WARN][13] ([i915#4269])
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/fi-cml-u2/igt@kms_frontbuffer_track...@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-kbl-soraka: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#533])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/fi-kbl-soraka/igt@kms_pipe_crc_ba...@compare-crc-sanitycheck-pipe-d.html
* igt@runner@aborted:
- fi-hsw-4770:NOTRUN -> [FAIL][15] ([fdo#109271] / [i915#1436] /
[i915#4312])
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/fi-hsw-4770/igt@run...@aborted.html
- fi-bsw-n3050: NOTRUN -> [FAIL][16] ([fdo#109271] / [i915#1436] /
[i915#2722] / [i915#3428] / [i915#4312])
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/fi-bsw-n3050/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600:[INCOMPLETE][17] ([i915#3921]) -> [PASS][18]
[17]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[18]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
* igt@i915_selftest@live@requests:
- fi-pnv-d510:[DMESG-FAIL][19] ([i915#2927] / [i915#4528]) ->
[PASS][20]
[19]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11141/fi-pnv-d510/igt@i915_selftest@l...@requests.html
[20]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22109/fi-pnv-d510/igt@i915_selftest@l...@requests.html
{name}: This element is suppressed. This means it is ignored when computing
Re: [Intel-gfx] [PATCH] drm/i915/adlp: Fix TypeC PHY-ready status readout
On Wed, 2022-01-26 at 12:43 +0200, Imre Deak wrote:
> The TCSS_DDI_STATUS register is indexed by tc_port not by the FIA port
> index, fix this up. This only caused an issue on TC#3/4 ports in legacy
> mode, as in all other cases the two indices either match (on TC#1/2) or
> the TCSS_DDI_STATUS_READY flag is set regardless of something being
> connected or not (on TC#1/2/3/4 in dp-alt and tbt-alt modes).
>
Reviewed-by: José Roberto de Souza
> Reported-and-tested-by: Chia-Lin Kao (AceLan)
> Fixes: 55ce306c2aa1 ("drm/i915/adl_p: Implement TC sequences")
> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4698
> Cc: José Roberto de Souza
> Cc: # v5.14+
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> b/drivers/gpu/drm/i915/display/intel_tc.c
> index 4eefe7b0bb263..3291124a99e5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -346,10 +346,11 @@ static bool icl_tc_phy_status_complete(struct
> intel_digital_port *dig_port)
> static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
> struct intel_uncore *uncore = >uncore;
> u32 val;
>
> - val = intel_uncore_read(uncore,
> TCSS_DDI_STATUS(dig_port->tc_phy_fia_idx));
> + val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port));
> if (val == 0x) {
> drm_dbg_kms(>drm,
> "Port %s: PHY in TCCOLD, assuming not complete\n",
Re: [Intel-gfx] [PATCH 1/9] drm/i915: Bump DSL linemask to 20 bits
On Fri, 19 Nov 2021, Ville Syrjälä wrote: > On Mon, Nov 15, 2021 at 02:05:00PM -0500, Rodrigo Vivi wrote: >> On Fri, Nov 12, 2021 at 09:38:05PM +0200, Ville Syrjala wrote: >> > From: Ville Syrjälä >> > >> > Since tgl PIPE_DSL has 20 bits for the scanline. Let's bump our >> > definition to match. And while at it let's also add the define >> > for the current field readback. >> > >> > We can also get rid of the gen2 vs. gen3+ nonsense since none >> > of the extra bits ever did anything and just always read >> > as zero. >> >> You are stepping over reserved bits on older platforms here. >> >> I understand that must probably hw is not using this for anything >> and the reads are only zero. But I'm always afraid of opening >> precedence for this kind of assumptions and end up stepping >> over some reserved bit that hw is using for something else >> but not documented. > > We do this in other places too in order to keep the code > simple. I think it's fine for cases where all old platforms > had a smaller bitfield which is extended in later platforms. > That is, assuming all the bits were unused (and read as zero) > in the old platforms, which is the case here. > > The thing we probably shouldn't do is make the bitfield larger > proactively for future platforms since we can't know if some of > the currently unused bits might end up being used for something > else in the future. > > I really hope we don't have any undocumented bits anywhere since > those can screw us up in a lot more ways than this. If we do find > any undocuemnted bits we really need to file bspec issues for those. I guess I'd record some of this in the commit message while applying, in case this blows up. Other than that, Reviewed-by: Jani Nikula -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 5/9] drm/i915: Clean up PCH_TRANSCONF/TRANS_DP_CTL bit defines
On Fri, 12 Nov 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT & co. for PCH_TRANSCONF/TRANS_DP_CTL bits, and
> adjust the naming a some bits to be more consistent.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> .../gpu/drm/i915/display/intel_pch_display.c | 13 +++--
> drivers/gpu/drm/i915/i915_reg.h | 58 +--
> 2 files changed, 33 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c
> b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index 81ab761251ae..155c2d19a6bb 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -166,11 +166,11 @@ static void ilk_enable_pch_transcoder(const struct
> intel_crtc_state *crtc_state)
> if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) ==
> PIPECONF_INTERLACE_IF_ID_ILK) {
> if (HAS_PCH_IBX(dev_priv) &&
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
> - val |= TRANS_LEGACY_INTERLACED_ILK;
> + val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
> else
> - val |= TRANS_INTERLACED;
> + val |= TRANS_INTERLACE_INTERLACED;
> } else {
> - val |= TRANS_PROGRESSIVE;
> + val |= TRANS_INTERLACE_PROGRESSIVE;
> }
>
> intel_de_write(dev_priv, reg, val | TRANS_ENABLE);
> @@ -279,7 +279,8 @@ void ilk_pch_enable(struct intel_atomic_state *state,
>
> temp = intel_de_read(dev_priv, reg);
> temp &= ~(TRANS_DP_PORT_SEL_MASK |
> - TRANS_DP_SYNC_MASK |
> + TRANS_DP_VSYNC_ACTIVE_HIGH |
> + TRANS_DP_HSYNC_ACTIVE_HIGH |
> TRANS_DP_BPC_MASK);
> temp |= TRANS_DP_OUTPUT_ENABLE;
> temp |= bpc << 9; /* same format but at 11:9 */
> @@ -423,9 +424,9 @@ static void lpt_enable_pch_transcoder(struct
> drm_i915_private *dev_priv,
> pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
>
> if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
> PIPECONF_INTERLACE_IF_ID_ILK)
> - val |= TRANS_INTERLACED;
> + val |= TRANS_INTERLACE_INTERLACED;
> else
> - val |= TRANS_PROGRESSIVE;
> + val |= TRANS_INTERLACE_PROGRESSIVE;
>
> intel_de_write(dev_priv, LPT_TRANSCONF, val);
> if (intel_de_wait_for_set(dev_priv, LPT_TRANSCONF,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d2d5b2fa2a4a..eea009e76e15 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8994,22 +8994,19 @@ enum {
> #define _PCH_TRANSBCONF 0xf1008
> #define PCH_TRANSCONF(pipe) _MMIO_PIPE(pipe, _PCH_TRANSACONF,
> _PCH_TRANSBCONF)
> #define LPT_TRANSCONFPCH_TRANSCONF(PIPE_A) /* lpt has only
> one transcoder */
> -#define TRANS_DISABLE (0 << 31)
> -#define TRANS_ENABLE (1 << 31)
> -#define TRANS_STATE_MASK (1 << 30)
> -#define TRANS_STATE_DISABLE(0 << 30)
> -#define TRANS_STATE_ENABLE (1 << 30)
> -#define TRANS_FRAME_START_DELAY_MASK(3 << 27) /* ibx */
> -#define TRANS_FRAME_START_DELAY(x) ((x) << 27) /* ibx: 0-3 */
> -#define TRANS_INTERLACE_MASK (7 << 21)
> -#define TRANS_PROGRESSIVE (0 << 21)
> -#define TRANS_INTERLACED (3 << 21)
> -#define TRANS_LEGACY_INTERLACED_ILK (2 << 21)
> -#define TRANS_8BPC (0 << 5)
> -#define TRANS_10BPC(1 << 5)
> -#define TRANS_6BPC (2 << 5)
> -#define TRANS_12BPC(3 << 5)
> -
> +#define TRANS_ENABLEREG_BIT(31)
> +#define TRANS_STATE_ENABLE REG_BIT(30)
> +#define TRANS_FRAME_START_DELAY_MASKREG_GENMASK(28, 27) /* ibx */
> +#define TRANS_FRAME_START_DELAY(x)
> REG_FIELD_PREP(TRANS_FRAME_START_DELAY_MASK, (x)) /* ibx: 0-3 */
> +#define TRANS_INTERLACE_MASKREG_GENMASK(23, 21)
> +#define TRANS_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANS_INTERLACE_MASK, 0)
> +#define TRANS_INTERLACE_LEGACY_VSYNC_IBX
> REG_FIELD_PREP(TRANS_INTERLACE_MASK, 2) /* ibx */
> +#define TRANS_INTERLACE_INTERLACED REG_FIELD_PREP(TRANS_INTERLACE_MASK, 3)
> +#define TRANS_BPC_MASK REG_GENMASK(7, 5) /* ibx */
> +#define TRANS_BPC_8 REG_FIELD_PREP(TRANS_BPC_MASK, 0)
> +#define TRANS_BPC_10REG_FIELD_PREP(TRANS_BPC_MASK,
> 1)
> +#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
> +#define TRANS_BPC_12REG_FIELD_PREP(TRANS_BPC_MASK,
> 3)
> #define _TRANSA_CHICKEN1 0xf0060
> #define _TRANSB_CHICKEN1 0xf1060
> #define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1,
> _TRANSB_CHICKEN1)
> @@ -9219,22 +9216,19 @@ enum {
> #define
Re: [Intel-gfx] [PATCH v2 09/11] drm: Convert open-coded yes/no strings to yesno()
On Wed, Jan 26, 2022 at 12:12:50PM +0200, Andy Shevchenko wrote: On Wed, Jan 26, 2022 at 11:39 AM Lucas De Marchi wrote: linux/string_helpers.h provides a helper to return "yes"/"no" strings. Replace the open coded versions with str_yes_no(). The places were oops, I replaced yesno() here but forgot to do so in the title identified with the following semantic patch: @@ expression b; @@ - b ? "yes" : "no" + str_yes_no(b) Then the includes were added, so we include-what-we-use, and parenthesis adjusted in drivers/gpu/drm/v3d/v3d_debugfs.c. After the conversion we still see the same binary sizes: textdata bss dec hex filename 511493295 212 54656d580 virtio/virtio-gpu.ko.old 511493295 212 54656d580 virtio/virtio-gpu.ko 1441491 60340 800 1502631 16eda7 radeon/radeon.ko.old 1441491 60340 800 1502631 16eda7 radeon/radeon.ko 6125369 328538 34000 6487907 62ff63 amd/amdgpu/amdgpu.ko.old 6125369 328538 34000 6487907 62ff63 amd/amdgpu/amdgpu.ko 411986 104906176 428652 68a6c drm.ko.old 411986 104906176 428652 68a6c drm.ko 981291636 264 100029 186bd dp/drm_dp_helper.ko.old 981291636 264 100029 186bd dp/drm_dp_helper.ko 1973432 1096402352 2085424 1fd230 nouveau/nouveau.ko.old 1973432 1096402352 2085424 1fd230 nouveau/nouveau.ko This probably won't change for modules, but if you compile in the linker may try to optimize it. Would be nice to see the old-new for `make allyesconfig` or equivalent. just like it would already do, no? I can try and see what happens, but my feeling is that we won't have any change. ... seq_printf(m, "\tDP branch device present: %s\n", - branch_device ? "yes" : "no"); + str_yes_no(branch_device)); Can it be now on one line? Same Q for all similar cases in the entire series. I saw that question in the previous version. I think those are very subjective is they all go a little bit over 80 chars. Some maintainers may prefer one way or the other. Here we are reducing just 3 chars so I assumed that is the preferred style here. Also keeping it as is helps with the mass conversion since it's easily repeatable if another iteration is needed. thanks Lucas De Marchi
Re: [Intel-gfx] [PATCH 2/2] drm/i915: Enable rpm wakeref tracking whether runtime pm is enabled or not
On Wed, Jan 26, 2022 at 10:15:39AM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Don't see why we should skip the wakeref tracking when the > platform doesn't support runtime pm. We still want all the > code to be 100% leak free so let's track this unconditionally. > > Cc: Vlastimil Babka > Cc: Dmitry Vyukov > Cc: Marco Elver # stackdepot > Cc: Chris Wilson > Cc: Imre Deak > Signed-off-by: Ville Syrjälä Reviewed-by: Imre Deak > --- > drivers/gpu/drm/i915/intel_runtime_pm.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c > b/drivers/gpu/drm/i915/intel_runtime_pm.c > index 64c2708efc9e..3293ac71bcf8 100644 > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c > @@ -77,9 +77,6 @@ track_intel_runtime_pm_wakeref(struct intel_runtime_pm *rpm) > depot_stack_handle_t stack, *stacks; > unsigned long flags; > > - if (!rpm->available) > - return -1; > - > stack = __save_depot_stack(); > if (!stack) > return -1; > -- > 2.34.1 >
Re: [Intel-gfx] [PATCH v5 5/5] drm/i915/uapi: document behaviour for DG2 64K support
On 1/25/22 20:35, Robert Beckett wrote: From: Matthew Auld On discrete platforms like DG2, we need to support a minimum page size of 64K when dealing with device local-memory. This is quite tricky for various reasons, so try to document the new implicit uapi for this. v3: fix typos and less emphasis v2: Fixed suggestions on formatting [Daniel] Signed-off-by: Matthew Auld Signed-off-by: Ramalingam C Signed-off-by: Robert Beckett Acked-by: Jordan Justen Reviewed-by: Ramalingam C cc: Simon Ser cc: Pekka Paalanen Cc: Jordan Justen Cc: Kenneth Graunke Cc: mesa-...@lists.freedesktop.org Cc: Tony Ye Cc: Slawomir Milczarek --- Reviewed-by: Thomas Hellström
Re: [Intel-gfx] [PATCH 3/9] drm/i915: Clean up SKL_BOTTOM_COLOR defines
On Fri, 12 Nov 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() for SKL_BOTTOM_COLOR.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e300a202ce2d..8b227dabb10c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6341,8 +6341,8 @@ enum {
>
> /* Skylake+ pipe bottom (background) color */
> #define _SKL_BOTTOM_COLOR_A 0x70034
> -#define SKL_BOTTOM_COLOR_GAMMA_ENABLE (1 << 31)
> -#define SKL_BOTTOM_COLOR_CSC_ENABLE(1 << 30)
> +#define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31)
> +#define SKL_BOTTOM_COLOR_CSC_ENABLEREG_BIT(30)
> #define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe,
> _SKL_BOTTOM_COLOR_A)
>
> #define _ICL_PIPE_A_STATUS 0x70058
--
Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH 4/9] drm/i915: Clean up PIPECONF bit defines
On Fri, 12 Nov 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. for PIPECONF bits, and adjust the
> naming of various bits to be more consistent.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c| 4 +-
> drivers/gpu/drm/i915/display/intel_display.c | 60 +-
> .../gpu/drm/i915/display/intel_pch_display.c | 7 +-
> drivers/gpu/drm/i915/gvt/display.c| 4 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 4 +-
> drivers/gpu/drm/i915/i915_reg.h | 108 +-
> 6 files changed, 89 insertions(+), 98 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index c05fb861f10c..0f6587bef106 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -1048,7 +1048,7 @@ static void gen11_dsi_enable_transcoder(struct
> intel_encoder *encoder)
>
> /* wait for transcoder to be enabled */
> if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
> - I965_PIPECONF_ACTIVE, 10))
> + PIPECONF_STATE_ENABLE, 10))
> drm_err(_priv->drm,
> "DSI transcoder not enabled\n");
> }
> @@ -1317,7 +1317,7 @@ static void gen11_dsi_disable_transcoder(struct
> intel_encoder *encoder)
>
> /* wait for transcoder to be disabled */
> if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
> - I965_PIPECONF_ACTIVE, 50))
> + PIPECONF_STATE_ENABLE, 50))
> drm_err(_priv->drm,
> "DSI trancoder not disabled\n");
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index e293241450b1..4e29032b29d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -386,13 +386,11 @@ intel_wait_for_pipe_off(const struct intel_crtc_state
> *old_crtc_state)
>
> if (DISPLAY_VER(dev_priv) >= 4) {
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
> - i915_reg_t reg = PIPECONF(cpu_transcoder);
>
> /* Wait for the Pipe State to go off */
> - if (intel_de_wait_for_clear(dev_priv, reg,
> - I965_PIPECONF_ACTIVE, 100))
> - drm_WARN(_priv->drm, 1,
> - "pipe_off wait timed out\n");
> + if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder),
> + PIPECONF_STATE_ENABLE, 100))
> + drm_WARN(_priv->drm, 1, "pipe_off wait timed
> out\n");
> } else {
> intel_wait_for_pipe_scanline_stopped(crtc);
> }
> @@ -3338,13 +3336,13 @@ static void i9xx_set_pipeconf(const struct
> intel_crtc_state *crtc_state)
>
> switch (crtc_state->pipe_bpp) {
> case 18:
> - pipeconf |= PIPECONF_6BPC;
> + pipeconf |= PIPECONF_BPC_6;
> break;
> case 24:
> - pipeconf |= PIPECONF_8BPC;
> + pipeconf |= PIPECONF_BPC_8;
> break;
> case 30:
> - pipeconf |= PIPECONF_10BPC;
> + pipeconf |= PIPECONF_BPC_10;
> break;
> default:
> /* Case prevented by intel_choose_pipe_bpp_dither. */
> @@ -3359,7 +3357,7 @@ static void i9xx_set_pipeconf(const struct
> intel_crtc_state *crtc_state)
> else
> pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
> } else {
> - pipeconf |= PIPECONF_PROGRESSIVE;
> + pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE;
> }
>
> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> @@ -3537,16 +3535,17 @@ static bool i9xx_get_pipe_config(struct intel_crtc
> *crtc,
> if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
> IS_CHERRYVIEW(dev_priv)) {
> switch (tmp & PIPECONF_BPC_MASK) {
> - case PIPECONF_6BPC:
> + case PIPECONF_BPC_6:
> pipe_config->pipe_bpp = 18;
> break;
> - case PIPECONF_8BPC:
> + case PIPECONF_BPC_8:
> pipe_config->pipe_bpp = 24;
> break;
> - case PIPECONF_10BPC:
> + case PIPECONF_BPC_10:
> pipe_config->pipe_bpp = 30;
> break;
> default:
> + MISSING_CASE(tmp);
> break;
>
Re: [Intel-gfx] [PATCH v2 09/11] drm: Convert open-coded yes/no strings to yesno()
On Wed, Jan 26, 2022 at 02:43:45AM -0800, Lucas De Marchi wrote: > On Wed, Jan 26, 2022 at 12:12:50PM +0200, Andy Shevchenko wrote: > > On Wed, Jan 26, 2022 at 11:39 AM Lucas De Marchi > > wrote: ... > > > 411986 104906176 428652 68a6c drm.ko.old > > > 411986 104906176 428652 68a6c drm.ko > > > 981291636 264 100029 186bd dp/drm_dp_helper.ko.old > > > 981291636 264 100029 186bd dp/drm_dp_helper.ko > > > 1973432 1096402352 2085424 1fd230 nouveau/nouveau.ko.old > > > 1973432 1096402352 2085424 1fd230 nouveau/nouveau.ko > > > > This probably won't change for modules, but if you compile in the > > linker may try to optimize it. Would be nice to see the old-new for > > `make allyesconfig` or equivalent. > > just like it would already do, no? I can try and see what happens, but > my feeling is that we won't have any change. Maybe not or maybe a small win. Depends how compiler puts / linker sees that in two cases. (Yeah, likely it should be no differences if all instances are already caught by linker) -- With Best Regards, Andy Shevchenko
Re: [Intel-gfx] [PATCH v5 1/5] drm/i915: add needs_compact_pt flag
On 1/25/22 20:35, Robert Beckett wrote:
From: Ramalingam C
Add a new platform flag, needs_compact_pt, to mark the requirement of
compact pt layout support for the ppGTT when using 64K GTT pages.
With this flag has_64k_pages will only indicate requirement of 64K
GTT page sizes or larger for device local memory access.
Suggested-by: Matthew Auld
Signed-off-by: Ramalingam C
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/i915_drv.h | 10 +++---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 44c1f98144b4..1258b7779705 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1512,12 +1512,16 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
/*
* Set this flag, when platform requires 64K GTT page sizes or larger for
- * device local memory access. Also this flag implies that we require or
- * at least support the compact PT layout for the ppGTT when using the 64K
- * GTT pages.
Why do we remove these comment lines?
+ * device local memory access.
*/
#define HAS_64K_PAGES(dev_priv) (INTEL_INFO(dev_priv)->has_64k_pages)
+/* Set this flag when platform doesn't allow both 64k pages and 4k pages in
First line of multi-line comments should be empty.
+ * the same PT. this flag means we need to support compact PT layout for the
+ * ppGTT when using the 64K GTT pages.
+ */
+#define NEEDS_COMPACT_PT(dev_priv) (INTEL_INFO(dev_priv)->needs_compact_pt)
+
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
#define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 4081fd50ba9d..799b56569ef5 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1028,6 +1028,7 @@ static const struct intel_device_info xehpsdv_info = {
PLATFORM(INTEL_XEHPSDV),
.display = { },
.has_64k_pages = 1,
+ .needs_compact_pt = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
@@ -1045,6 +1046,7 @@ static const struct intel_device_info dg2_info = {
.media.rel = 55,
PLATFORM(INTEL_DG2),
.has_64k_pages = 1,
+ .needs_compact_pt = 1,
.platform_engine_mask =
BIT(RCS0) | BIT(BCS0) |
BIT(VECS0) | BIT(VECS1) |
diff --git a/drivers/gpu/drm/i915/intel_device_info.h
b/drivers/gpu/drm/i915/intel_device_info.h
index 3699b1c539ea..c8aaf646430c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -130,6 +130,7 @@ enum intel_ppgtt_type {
/* Keep has_* in alphabetical order */ \
func(has_64bit_reloc); \
func(has_64k_pages); \
+ func(needs_compact_pt); \
func(gpu_reset_clobbers_display); \
func(has_reset_engine); \
func(has_global_mocs); \
Re: [Intel-gfx] [PATCH v5 4/5] drm/i915: add gtt misalignment test
On 1/25/22 20:35, Robert Beckett wrote:
add test to check handling of misaligned offsets and sizes
v4:
* remove spurious blank lines
* explicitly cast intel_region_id to intel_memory_type in misaligned_pin
Reported-by: kernel test robot
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 128 ++
1 file changed, 128 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
index b80788a2b7f9..f082b5ff3b5e 100644
--- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
@@ -22,10 +22,12 @@
*
*/
+#include "gt/intel_gtt.h"
#include
#include
#include "gem/i915_gem_context.h"
+#include "gem/i915_gem_region.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_context.h"
#include "gt/intel_gpu_commands.h"
@@ -1067,6 +1069,120 @@ static int shrink_boom(struct i915_address_space *vm,
return err;
}
+static int misaligned_case(struct i915_address_space *vm, struct intel_memory_region *mr,
+ u64 addr, u64 size, unsigned long flags)
+{
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ int err = 0;
+ u64 expected_vma_size, expected_node_size;
+
+ obj = i915_gem_object_create_region(mr, size, 0, 0);
+ if (IS_ERR(obj))
+ return PTR_ERR(obj);
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ goto err_put;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, addr | flags);
+ if (err)
+ goto err_put;
+ i915_vma_unpin(vma);
+
+ if (!drm_mm_node_allocated(>node)) {
+ err = -EINVAL;
+ goto err_put;
+ }
+
+ if (i915_vma_misplaced(vma, 0, 0, addr | flags)) {
+ err = -EINVAL;
+ goto err_put;
+ }
+
+ expected_vma_size = round_up(size, 1 <<
(ffs(vma->resource->page_sizes_gtt) - 1));
+ expected_node_size = expected_vma_size;
+
+ if (IS_DG2(vm->i915) && i915_gem_object_is_lmem(obj)) {
+ /* dg2 should expand lmem node to 2MB */
Should this test be NEEDS_COMPACT_PT()?
Otherwise LGTM. Reviewed-by: Thomas Hellström
Re: [Intel-gfx] [PATCH 2/9] drm/i915: Clean up PIPEMISC register defines
On Fri, 12 Nov 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use REG_BIT() & co. for PIPEMISC* bits, and while at it
> fill in the missing dithering bits since we already had some
> of them defined.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 18 +-
> drivers/gpu/drm/i915/i915_reg.h | 35 +++-
> 2 files changed, 28 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 6073f94632ab..e293241450b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3724,18 +3724,18 @@ static void bdw_set_pipemisc(const struct
> intel_crtc_state *crtc_state)
>
> switch (crtc_state->pipe_bpp) {
> case 18:
> - val |= PIPEMISC_6_BPC;
> + val |= PIPEMISC_BPC_6;
> break;
> case 24:
> - val |= PIPEMISC_8_BPC;
> + val |= PIPEMISC_BPC_8;
> break;
> case 30:
> - val |= PIPEMISC_10_BPC;
> + val |= PIPEMISC_BPC_10;
> break;
> case 36:
> /* Port output 12BPC defined for ADLP+ */
> if (DISPLAY_VER(dev_priv) > 12)
> - val |= PIPEMISC_12_BPC_ADLP;
> + val |= PIPEMISC_BPC_12_ADLP;
> break;
> default:
> MISSING_CASE(crtc_state->pipe_bpp);
> @@ -3771,7 +3771,7 @@ static void bdw_set_pipemisc(const struct
> intel_crtc_state *crtc_state)
> }
>
> intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
> - PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
> + PIPE_MISC2_BUBBLE_COUNTER_MASK,
>scaler_in_use ?
> PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
>PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
> }
> @@ -3787,11 +3787,11 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
> tmp = intel_de_read(dev_priv, PIPEMISC(crtc->pipe));
>
> switch (tmp & PIPEMISC_BPC_MASK) {
> - case PIPEMISC_6_BPC:
> + case PIPEMISC_BPC_6:
> return 18;
> - case PIPEMISC_8_BPC:
> + case PIPEMISC_BPC_8:
> return 24;
> - case PIPEMISC_10_BPC:
> + case PIPEMISC_BPC_10:
> return 30;
> /*
>* PORT OUTPUT 12 BPC defined for ADLP+.
> @@ -3803,7 +3803,7 @@ int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
>* on older platforms, need to find a workaround for 12 BPC
>* MIPI DSI HW readout.
>*/
> - case PIPEMISC_12_BPC_ADLP:
> + case PIPEMISC_BPC_12_ADLP:
> if (DISPLAY_VER(dev_priv) > 12)
> return 36;
> fallthrough;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f5d54ed2efc1..e300a202ce2d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6308,32 +6308,35 @@ enum {
>
> #define _PIPE_MISC_A 0x70030
> #define _PIPE_MISC_B 0x71030
> -#define PIPEMISC_YUV420_ENABLE (1 << 27) /* glk+ */
> -#define PIPEMISC_YUV420_MODE_FULL_BLEND (1 << 26) /* glk+ */
> -#define PIPEMISC_HDR_MODE_PRECISION(1 << 23) /* icl+ */
> -#define PIPEMISC_OUTPUT_COLORSPACE_YUV (1 << 11)
> -#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
> +#define PIPEMISC_YUV420_ENABLE REG_BIT(27) /* glk+ */
> +#define PIPEMISC_YUV420_MODE_FULL_BLENDREG_BIT(26) /* glk+ */
> +#define PIPEMISC_HDR_MODE_PRECISIONREG_BIT(23) /* icl+ */
> +#define PIPEMISC_OUTPUT_COLORSPACE_YUV REG_BIT(11)
> +#define PIPEMISC_PIXEL_ROUNDING_TRUNC REG_BIT(8) /* tgl+ */
> /*
> * For Display < 13, Bits 5-7 of PIPE MISC represent DITHER BPC with
> * valid values of: 6, 8, 10 BPC.
> * ADLP+, the bits 5-7 represent PORT OUTPUT BPC with valid values of:
> * 6, 8, 10, 12 BPC.
> */
> -#define PIPEMISC_BPC_MASK (7 << 5)
> -#define PIPEMISC_8_BPC (0 << 5)
> -#define PIPEMISC_10_BPC(1 << 5)
> -#define PIPEMISC_6_BPC (2 << 5)
> -#define PIPEMISC_12_BPC_ADLP (4 << 5) /* adlp+ */
> -#define PIPEMISC_DITHER_ENABLE (1 << 4)
> -#define PIPEMISC_DITHER_TYPE_MASK (3 << 2)
> -#define PIPEMISC_DITHER_TYPE_SP(0 << 2)
> +#define PIPEMISC_BPC_MASK REG_GENMASK(7, 5)
> +#define PIPEMISC_BPC_8
> REG_FIELD_PREP(PIPEMISC_BPC_MASK, 0)
> +#define PIPEMISC_BPC_10
> REG_FIELD_PREP(PIPEMISC_BPC_MASK, 1)
> +#define PIPEMISC_BPC_6
> REG_FIELD_PREP(PIPEMISC_BPC_MASK, 2)
> +#define PIPEMISC_BPC_12_ADLP
> REG_FIELD_PREP(PIPEMISC_BPC_MASK, 4) /* adlp+ */
> +#define
[Intel-gfx] [PATCH 08/19] drm/i915/guc: Convert engine record to dma_buf_map
Use dma_buf_map to read fields from the dma_blob so access to IO and
system memory is abstracted away.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 14 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h| 3 ++-
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 +++
3 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 2ffe5836f95e..fe1e71adfca1 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -698,18 +698,16 @@ void intel_guc_ads_reset(struct intel_guc *guc)
u32 intel_guc_engine_usage_offset(struct intel_guc *guc)
{
- struct __guc_ads_blob *blob = guc->ads_blob;
- u32 base = intel_guc_ggtt_offset(guc, guc->ads_vma);
- u32 offset = base + ptr_offset(blob, engine_usage);
-
- return offset;
+ return intel_guc_ggtt_offset(guc, guc->ads_vma) +
+ offsetof(struct __guc_ads_blob, engine_usage);
}
-struct guc_engine_usage_record *intel_guc_engine_usage(struct intel_engine_cs
*engine)
+struct dma_buf_map intel_guc_engine_usage_record_map(struct intel_engine_cs
*engine)
{
struct intel_guc *guc = >gt->uc.guc;
- struct __guc_ads_blob *blob = guc->ads_blob;
u8 guc_class = engine_class_to_guc_class(engine->class);
+ size_t offset = offsetof(struct __guc_ads_blob,
+
engine_usage.engines[guc_class][ilog2(engine->logical_mask)]);
- return
>engine_usage.engines[guc_class][ilog2(engine->logical_mask)];
+ return DMA_BUF_MAP_INIT_OFFSET(>ads_map, offset);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
index e74c110facff..27f5b1f9ddac 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h
@@ -7,6 +7,7 @@
#define _INTEL_GUC_ADS_H_
#include
+#include
struct intel_guc;
struct drm_printer;
@@ -18,7 +19,7 @@ void intel_guc_ads_init_late(struct intel_guc *guc);
void intel_guc_ads_reset(struct intel_guc *guc);
void intel_guc_ads_print_policy_info(struct intel_guc *guc,
struct drm_printer *p);
-struct guc_engine_usage_record *intel_guc_engine_usage(struct intel_engine_cs
*engine);
+struct dma_buf_map intel_guc_engine_usage_record_map(struct intel_engine_cs
*engine);
u32 intel_guc_engine_usage_offset(struct intel_guc *guc);
#endif
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index db9615dcb0ec..57bfb4ad0ab8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1125,14 +1125,17 @@ __extend_last_switch(struct intel_guc *guc, u64
*prev_start, u32 new_start)
*prev_start = ((u64)gt_stamp_hi << 32) | new_start;
}
+#define record_read(map_, field_) \
+ dma_buf_map_read_field(map_, struct guc_engine_usage_record, field_)
+
static void guc_update_engine_gt_clks(struct intel_engine_cs *engine)
{
- struct guc_engine_usage_record *rec = intel_guc_engine_usage(engine);
+ struct dma_buf_map rec_map = intel_guc_engine_usage_record_map(engine);
struct intel_engine_guc_stats *stats = >stats.guc;
struct intel_guc *guc = >gt->uc.guc;
- u32 last_switch = rec->last_switch_in_stamp;
- u32 ctx_id = rec->current_context_index;
- u32 total = rec->total_runtime;
+ u32 last_switch = record_read(_map, last_switch_in_stamp);
+ u32 ctx_id = record_read(_map, current_context_index);
+ u32 total = record_read(_map, total_runtime);
lockdep_assert_held(>timestamp.lock);
--
2.35.0
[Intel-gfx] [PATCH 15/19] drm/i915/guc: Prepare for error propagation
Currently guc_mmio_reg_add() relies on having enough memory available in
the array to add a new slot. It uses
`GEM_BUG_ON(count >= regset->size);` to protect going above the
threshold.
In order to allow guc_mmio_reg_add() to handle the memory allocation by
itself, it must return an error in case of failures. Adjust return code
so this error can be propagated to the callers of guc_mmio_reg_add() and
guc_mmio_regset_init().
No intended change in behavior.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 31 +-
1 file changed, 18 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index cad1e325656e..73ca34de44f7 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -244,8 +244,8 @@ static int guc_mmio_reg_cmp(const void *a, const void *b)
return (int)ra->offset - (int)rb->offset;
}
-static void guc_mmio_reg_add(struct temp_regset *regset,
-u32 offset, u32 flags)
+static long __must_check guc_mmio_reg_add(struct temp_regset *regset,
+ u32 offset, u32 flags)
{
u32 count = regset->used;
struct guc_mmio_reg reg = {
@@ -264,7 +264,7 @@ static void guc_mmio_reg_add(struct temp_regset *regset,
*/
if (bsearch(, regset->registers, count,
sizeof(reg), guc_mmio_reg_cmp))
- return;
+ return 0;
slot = >registers[count];
regset->used++;
@@ -277,6 +277,8 @@ static void guc_mmio_reg_add(struct temp_regset *regset,
swap(slot[1], slot[0]);
}
+
+ return 0;
}
#define GUC_MMIO_REG_ADD(regset, reg, masked) \
@@ -284,32 +286,35 @@ static void guc_mmio_reg_add(struct temp_regset *regset,
i915_mmio_reg_offset((reg)), \
(masked) ? GUC_REGSET_MASKED : 0)
-static void guc_mmio_regset_init(struct temp_regset *regset,
-struct intel_engine_cs *engine)
+static int guc_mmio_regset_init(struct temp_regset *regset,
+ struct intel_engine_cs *engine)
{
const u32 base = engine->mmio_base;
struct i915_wa_list *wal = >wa_list;
struct i915_wa *wa;
unsigned int i;
+ int ret = 0;
regset->used = 0;
- GUC_MMIO_REG_ADD(regset, RING_MODE_GEN7(base), true);
- GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false);
- GUC_MMIO_REG_ADD(regset, RING_IMR(base), false);
+ ret |= GUC_MMIO_REG_ADD(regset, RING_MODE_GEN7(base), true);
+ ret |= GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false);
+ ret |= GUC_MMIO_REG_ADD(regset, RING_IMR(base), false);
for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
- GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg);
+ ret |= GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg);
/* Be extra paranoid and include all whitelist registers. */
for (i = 0; i < RING_MAX_NONPRIV_SLOTS; i++)
- GUC_MMIO_REG_ADD(regset,
-RING_FORCE_TO_NONPRIV(base, i),
-false);
+ ret |= GUC_MMIO_REG_ADD(regset,
+ RING_FORCE_TO_NONPRIV(base, i),
+ false);
/* add in local MOCS registers */
for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++)
- GUC_MMIO_REG_ADD(regset, GEN9_LNCFCMOCS(i), false);
+ ret |= GUC_MMIO_REG_ADD(regset, GEN9_LNCFCMOCS(i), false);
+
+ return ret ? -1 : 0;
}
static int guc_mmio_reg_state_query(struct intel_guc *guc)
--
2.35.0
[Intel-gfx] [PATCH 14/19] drm/i915/guc: Convert capture list to dma_buf_map
Use dma_buf_map to write the fields ads.capture_*.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index dca7c3db9cdd..cad1e325656e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -544,7 +544,7 @@ static void guc_init_golden_context(struct intel_guc *guc)
GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size);
}
-static void guc_capture_list_init(struct intel_guc *guc, struct __guc_ads_blob
*blob)
+static void guc_capture_list_init(struct intel_guc *guc)
{
int i, j;
u32 addr_ggtt, offset;
@@ -556,11 +556,11 @@ static void guc_capture_list_init(struct intel_guc *guc,
struct __guc_ads_blob *
for (i = 0; i < GUC_CAPTURE_LIST_INDEX_MAX; i++) {
for (j = 0; j < GUC_MAX_ENGINE_CLASSES; j++) {
- blob->ads.capture_instance[i][j] = addr_ggtt;
- blob->ads.capture_class[i][j] = addr_ggtt;
+ ads_blob_write(guc, ads.capture_instance[i][j],
addr_ggtt);
+ ads_blob_write(guc, ads.capture_class[i][j], addr_ggtt);
}
- blob->ads.capture_global[i] = addr_ggtt;
+ ads_blob_write(guc, ads.capture_global[i], addr_ggtt);
}
}
@@ -600,7 +600,7 @@ static void __guc_ads_init(struct intel_guc *guc)
base = intel_guc_ggtt_offset(guc, guc->ads_vma);
/* Capture list for hang debug */
- guc_capture_list_init(guc, blob);
+ guc_capture_list_init(guc);
/* ADS */
blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
--
2.35.0
[Intel-gfx] [PATCH 07/19] drm/i915/guc: Convert policies update to dma_buf_map
Use dma_buf_map to write the policies update so access to IO and system
memory is abstracted away.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 41 --
1 file changed, 23 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index bcf52ac4fe35..2ffe5836f95e 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -130,33 +130,37 @@ static u32 guc_ads_blob_size(struct intel_guc *guc)
guc_ads_private_data_size(guc);
}
-static void guc_policies_init(struct intel_guc *guc, struct guc_policies
*policies)
+static void guc_policies_init(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
struct drm_i915_private *i915 = gt->i915;
+ u32 global_flags = 0;
- policies->dpc_promote_time = GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US;
- policies->max_num_work_items = GLOBAL_POLICY_MAX_NUM_WI;
+ ads_blob_write(guc, policies.dpc_promote_time,
+ GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US);
+ ads_blob_write(guc, policies.max_num_work_items,
+ GLOBAL_POLICY_MAX_NUM_WI);
- policies->global_flags = 0;
if (i915->params.reset < 2)
- policies->global_flags |= GLOBAL_POLICY_DISABLE_ENGINE_RESET;
+ global_flags |= GLOBAL_POLICY_DISABLE_ENGINE_RESET;
- policies->is_valid = 1;
+ ads_blob_write(guc, policies.global_flags, global_flags);
+ ads_blob_write(guc, policies.is_valid, 1);
}
void intel_guc_ads_print_policy_info(struct intel_guc *guc,
struct drm_printer *dp)
{
- struct __guc_ads_blob *blob = guc->ads_blob;
-
- if (unlikely(!blob))
+ if (unlikely(dma_buf_map_is_null(>ads_map)))
return;
drm_printf(dp, "Global scheduling policies:\n");
- drm_printf(dp, " DPC promote time = %u\n",
blob->policies.dpc_promote_time);
- drm_printf(dp, " Max num work items = %u\n",
blob->policies.max_num_work_items);
- drm_printf(dp, " Flags = %u\n",
blob->policies.global_flags);
+ drm_printf(dp, " DPC promote time = %u\n",
+ ads_blob_read(guc, policies.dpc_promote_time));
+ drm_printf(dp, " Max num work items = %u\n",
+ ads_blob_read(guc, policies.max_num_work_items));
+ drm_printf(dp, " Flags = %u\n",
+ ads_blob_read(guc, policies.global_flags));
}
static int guc_action_policies_update(struct intel_guc *guc, u32 policy_offset)
@@ -171,23 +175,24 @@ static int guc_action_policies_update(struct intel_guc
*guc, u32 policy_offset)
int intel_guc_global_policies_update(struct intel_guc *guc)
{
- struct __guc_ads_blob *blob = guc->ads_blob;
struct intel_gt *gt = guc_to_gt(guc);
+ u32 scheduler_policies;
intel_wakeref_t wakeref;
int ret;
- if (!blob)
+ if (dma_buf_map_is_null(>ads_map))
return -EOPNOTSUPP;
- GEM_BUG_ON(!blob->ads.scheduler_policies);
+ scheduler_policies = ads_blob_read(guc, ads.scheduler_policies);
+ GEM_BUG_ON(!scheduler_policies);
- guc_policies_init(guc, >policies);
+ guc_policies_init(guc);
if (!intel_guc_is_ready(guc))
return 0;
with_intel_runtime_pm(>i915->runtime_pm, wakeref)
- ret = guc_action_policies_update(guc,
blob->ads.scheduler_policies);
+ ret = guc_action_policies_update(guc, scheduler_policies);
return ret;
}
@@ -557,7 +562,7 @@ static void __guc_ads_init(struct intel_guc *guc)
u32 base;
/* GuC scheduling policies */
- guc_policies_init(guc, >policies);
+ guc_policies_init(guc);
/* System info */
fill_engine_enable_masks(gt, >system_info);
--
2.35.0
[Intel-gfx] [PATCH 11/19] drm/i915/guc: Convert golden context prep to dma_buf_map
Use the saved ads_map to prepare the golden context. One difference from
the init context is that this function can be called before there is a
gem object (and thus the guc->ads_map) to calculare the size of the
golden context that should be allocated for that object.
So in this case the function needs to be prepared for not having the
system_info with enabled engines filled out. To accomplish that an
info_map is prepared on the side to point either to the gem object
or the local variable on the stack. This allows making
fill_engine_enable_masks() operate always with a dma_buf_map
argument.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 52 +-
1 file changed, 32 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 15990c229b54..dd9ec47eed16 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -67,6 +67,12 @@ struct __guc_ads_blob {
dma_buf_map_write_field(&(guc_)->ads_map, struct __guc_ads_blob,\
field_, val_)
+#define info_map_write(map_, field_, val_) \
+ dma_buf_map_write_field(map_, struct guc_gt_system_info, field_, val_)
+
+#define info_map_read(map_, field_) \
+ dma_buf_map_read_field(map_, struct guc_gt_system_info, field_)
+
static u32 guc_ads_regset_size(struct intel_guc *guc)
{
GEM_BUG_ON(!guc->ads_regset_size);
@@ -378,24 +384,24 @@ static void guc_mmio_reg_state_init(struct intel_guc *guc,
}
static void fill_engine_enable_masks(struct intel_gt *gt,
-struct guc_gt_system_info *info)
+struct dma_buf_map *info_map)
{
- info->engine_enabled_masks[GUC_RENDER_CLASS] = 1;
- info->engine_enabled_masks[GUC_BLITTER_CLASS] = 1;
- info->engine_enabled_masks[GUC_VIDEO_CLASS] = VDBOX_MASK(gt);
- info->engine_enabled_masks[GUC_VIDEOENHANCE_CLASS] = VEBOX_MASK(gt);
+ info_map_write(info_map, engine_enabled_masks[GUC_RENDER_CLASS], 1);
+ info_map_write(info_map, engine_enabled_masks[GUC_BLITTER_CLASS], 1);
+ info_map_write(info_map, engine_enabled_masks[GUC_VIDEO_CLASS],
VDBOX_MASK(gt));
+ info_map_write(info_map, engine_enabled_masks[GUC_VIDEOENHANCE_CLASS],
VEBOX_MASK(gt));
}
#define LR_HW_CONTEXT_SIZE (80 * sizeof(u32))
#define LRC_SKIP_SIZE (LRC_PPHWSP_SZ * PAGE_SIZE + LR_HW_CONTEXT_SIZE)
-static int guc_prep_golden_context(struct intel_guc *guc,
- struct __guc_ads_blob *blob)
+static int guc_prep_golden_context(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
u32 addr_ggtt, offset;
u32 total_size = 0, alloc_size, real_size;
u8 engine_class, guc_class;
- struct guc_gt_system_info *info, local_info;
+ struct guc_gt_system_info local_info;
+ struct dma_buf_map info_map;
/*
* Reserve the memory for the golden contexts and point GuC at it but
@@ -409,14 +415,15 @@ static int guc_prep_golden_context(struct intel_guc *guc,
* GuC will also validate that the LRC base + size fall within the
* allowed GGTT range.
*/
- if (blob) {
+ if (!dma_buf_map_is_null(>ads_map)) {
offset = guc_ads_golden_ctxt_offset(guc);
addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
- info = >system_info;
+ info_map = DMA_BUF_MAP_INIT_OFFSET(>ads_map,
+ offsetof(struct
__guc_ads_blob, system_info));
} else {
memset(_info, 0, sizeof(local_info));
- info = _info;
- fill_engine_enable_masks(gt, info);
+ dma_buf_map_set_vaddr(_map, _info);
+ fill_engine_enable_masks(gt, _map);
}
for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS;
++engine_class) {
@@ -425,14 +432,14 @@ static int guc_prep_golden_context(struct intel_guc *guc,
guc_class = engine_class_to_guc_class(engine_class);
- if (!info->engine_enabled_masks[guc_class])
+ if (!info_map_read(_map, engine_enabled_masks[guc_class]))
continue;
real_size = intel_engine_context_size(gt, engine_class);
alloc_size = PAGE_ALIGN(real_size);
total_size += alloc_size;
- if (!blob)
+ if (dma_buf_map_is_null(>ads_map))
continue;
/*
@@ -446,12 +453,15 @@ static int guc_prep_golden_context(struct intel_guc *guc,
* what comes before it in the context image (which is identical
* on all engines).
[Intel-gfx] [PATCH 17/19] drm/i915/guc: Convert guc_mmio_reg_state_init to dma_buf_map
Now that the regset list is prepared, convert guc_mmio_reg_state_init()
to use dma_buf_map to copy the array to the final location and
initialize additional fields in ads.reg_state_list.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 30 +-
1 file changed, 18 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 390101ee3661..cb0f543b0e86 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -372,40 +372,46 @@ static long guc_mmio_reg_state_create(struct intel_guc
*guc)
return total * sizeof(struct guc_mmio_reg);
}
-static void guc_mmio_reg_state_init(struct intel_guc *guc,
- struct __guc_ads_blob *blob)
+static void guc_mmio_reg_state_init(struct intel_guc *guc)
{
+ struct dma_buf_map ads_regset_map;
struct intel_gt *gt = guc_to_gt(guc);
struct intel_engine_cs *engine;
- struct guc_mmio_reg *ads_registers;
enum intel_engine_id id;
u32 addr_ggtt, offset;
offset = guc_ads_regset_offset(guc);
addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
- ads_registers = (struct guc_mmio_reg *)(((u8 *)blob) + offset);
+ ads_regset_map = DMA_BUF_MAP_INIT_OFFSET(>ads_map, offset);
- memcpy(ads_registers, guc->ads_regset, guc->ads_regset_size);
+ dma_buf_map_memcpy_to(_regset_map, guc->ads_regset,
+ guc->ads_regset_size);
for_each_engine(engine, gt, id) {
u32 count = guc->ads_regset_count[id];
- struct guc_mmio_reg_set *ads_reg_set;
u8 guc_class;
/* Class index is checked in class converter */
GEM_BUG_ON(engine->instance >= GUC_MAX_INSTANCES_PER_CLASS);
guc_class = engine_class_to_guc_class(engine->class);
- ads_reg_set =
>ads.reg_state_list[guc_class][engine->instance];
if (!count) {
- ads_reg_set->address = 0;
- ads_reg_set->count = 0;
+ ads_blob_write(guc,
+
ads.reg_state_list[guc_class][engine->instance].address,
+ 0);
+ ads_blob_write(guc,
+
ads.reg_state_list[guc_class][engine->instance].count,
+ 0);
continue;
}
- ads_reg_set->address = addr_ggtt;
- ads_reg_set->count = count;
+ ads_blob_write(guc,
+
ads.reg_state_list[guc_class][engine->instance].address,
+ addr_ggtt);
+ ads_blob_write(guc,
+
ads.reg_state_list[guc_class][engine->instance].count,
+ count);
addr_ggtt += count * sizeof(struct guc_mmio_reg);
}
@@ -635,7 +641,7 @@ static void __guc_ads_init(struct intel_guc *guc)
blob->ads.gt_system_info = base + ptr_offset(blob, system_info);
/* MMIO save/restore list */
- guc_mmio_reg_state_init(guc, blob);
+ guc_mmio_reg_state_init(guc);
/* Private Data */
blob->ads.private_data = base + guc_ads_private_data_offset(guc);
--
2.35.0
[Intel-gfx] [PATCH 12/19] drm/i915/guc: Replace check for golden context size
In the other places in this function, guc->ads_map is being protected from access when it's not yet set. However the last check is actually about guc->ads_golden_ctxt_size been set before. These checks should always match as the size is initialized on the first call to guc_prep_golden_context(), but it's clearer if we have a single return and check for guc->ads_golden_ctxt_size. This is just a readability improvement, no change in behavior. Cc: Matt Roper Cc: Thomas Hellström Cc: Daniel Vetter Cc: John Harrison Cc: Matthew Brost Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c index dd9ec47eed16..8e4768289792 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c @@ -461,10 +461,10 @@ static int guc_prep_golden_context(struct intel_guc *guc) addr_ggtt += alloc_size; } - if (dma_buf_map_is_null(>ads_map)) - return total_size; + /* Make sure current size matches what we calculated previously */ + if (guc->ads_golden_ctxt_size) + GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size); - GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size); return total_size; } -- 2.35.0
[Intel-gfx] [PATCH 19/19] drm/i915/guc: Remove plain ads_blob pointer
Now we have the access to content of GuC ADS either using dma_buf_map
API or using a temporary buffer. Remove guc->ads_blob as there shouldn't
be updates using the bare pointer anymore.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 3 +--
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 4c852eee3ad8..7349483d0e35 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -147,8 +147,7 @@ struct intel_guc {
/** @ads_vma: object allocated to hold the GuC ADS */
struct i915_vma *ads_vma;
- /** @ads_blob: contents of the GuC ADS */
- struct __guc_ads_blob *ads_blob;
+ /** @ads_map: contents of the GuC ADS */
struct dma_buf_map ads_map;
/** @ads_regset_size: size of the save/restore regsets in the ADS */
u32 ads_regset_size;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 30edac93afbf..b87269081650 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -661,6 +661,7 @@ static void __guc_ads_init(struct intel_guc *guc)
*/
int intel_guc_ads_create(struct intel_guc *guc)
{
+ void *ads_blob;
u32 size;
int ret;
@@ -685,14 +686,14 @@ int intel_guc_ads_create(struct intel_guc *guc)
size = guc_ads_blob_size(guc);
ret = intel_guc_allocate_and_map_vma(guc, size, >ads_vma,
-(void **)>ads_blob);
+_blob);
if (ret)
return ret;
if (i915_gem_object_is_lmem(guc->ads_vma->obj))
- dma_buf_map_set_vaddr_iomem(>ads_map, (void __iomem
*)guc->ads_blob);
+ dma_buf_map_set_vaddr_iomem(>ads_map, (void __iomem
*)ads_blob);
else
- dma_buf_map_set_vaddr(>ads_map, guc->ads_blob);
+ dma_buf_map_set_vaddr(>ads_map, ads_blob);
__guc_ads_init(guc);
@@ -714,7 +715,6 @@ void intel_guc_ads_init_late(struct intel_guc *guc)
void intel_guc_ads_destroy(struct intel_guc *guc)
{
i915_vma_unpin_and_release(>ads_vma, I915_VMA_RELEASE_MAP);
- guc->ads_blob = NULL;
dma_buf_map_clear(>ads_map);
kfree(guc->ads_regset);
}
--
2.35.0
[Intel-gfx] [PATCH 10/19] drm/i915/guc: Convert guc_ads_private_data_reset to dma_buf_map
Use dma_buf_map_memset() to zero the private data as ADS may be either
on system or IO memory.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index fe1e71adfca1..15990c229b54 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -668,14 +668,15 @@ void intel_guc_ads_destroy(struct intel_guc *guc)
static void guc_ads_private_data_reset(struct intel_guc *guc)
{
+ struct dma_buf_map map =
+ DMA_BUF_MAP_INIT_OFFSET(>ads_map,
guc_ads_private_data_offset(guc));
u32 size;
size = guc_ads_private_data_size(guc);
if (!size)
return;
- memset((void *)guc->ads_blob + guc_ads_private_data_offset(guc), 0,
- size);
+ dma_buf_map_memset(, 0, size);
}
/**
--
2.35.0
[Intel-gfx] [PATCH 03/19] drm/i915/gt: Add helper for shmem copy to dma_buf_map
Add a variant of shmem_read() that takes a dma_buf_map pointer rather
than a plain pointer as argument. It's mostly a copy __shmem_rw() but
adapting the api and removing the write support since there's currently
only need to use dma_buf_map as destination.
Reworking __shmem_rw() to share the implementation was tempting, but
finding a good balance between reuse and clarity pushed towards a little
code duplication. Since the function is small, just add the similar
function with a copy/paste/adapt approach.
Cc: Matt Roper
Cc: Joonas Lahtinen
Cc: Tvrtko Ursulin
Cc: David Airlie
Cc: Daniel Vetter
Cc: Matthew Auld
Cc: Thomas Hellström
Cc: Maarten Lankhorst
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/shmem_utils.c | 32 +++
drivers/gpu/drm/i915/gt/shmem_utils.h | 3 +++
2 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.c
b/drivers/gpu/drm/i915/gt/shmem_utils.c
index 0683b27a3890..d7968e68ccfb 100644
--- a/drivers/gpu/drm/i915/gt/shmem_utils.c
+++ b/drivers/gpu/drm/i915/gt/shmem_utils.c
@@ -3,6 +3,7 @@
* Copyright © 2020 Intel Corporation
*/
+#include
#include
#include
#include
@@ -123,6 +124,37 @@ static int __shmem_rw(struct file *file, loff_t off,
return 0;
}
+int shmem_read_to_dma_buf_map(struct file *file, loff_t off,
+ struct dma_buf_map *map, size_t len)
+{
+ struct dma_buf_map map_iter = *map;
+ unsigned long pfn;
+
+ for (pfn = off >> PAGE_SHIFT; len; pfn++) {
+ unsigned int this =
+ min_t(size_t, PAGE_SIZE - offset_in_page(off), len);
+ struct page *page;
+ void *vaddr;
+
+ page = shmem_read_mapping_page_gfp(file->f_mapping, pfn,
+ GFP_KERNEL);
+ if (IS_ERR(page))
+ return PTR_ERR(page);
+
+ vaddr = kmap(page);
+ dma_buf_map_memcpy_to(_iter, vaddr + offset_in_page(off),
this);
+ mark_page_accessed(page);
+ kunmap(page);
+ put_page(page);
+
+ len -= this;
+ dma_buf_map_incr(_iter, this);
+ off = 0;
+ }
+
+ return 0;
+}
+
int shmem_read(struct file *file, loff_t off, void *dst, size_t len)
{
return __shmem_rw(file, off, dst, len, false);
diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.h
b/drivers/gpu/drm/i915/gt/shmem_utils.h
index c1669170c351..a3d4ce966f74 100644
--- a/drivers/gpu/drm/i915/gt/shmem_utils.h
+++ b/drivers/gpu/drm/i915/gt/shmem_utils.h
@@ -8,6 +8,7 @@
#include
+struct dma_buf_map;
struct drm_i915_gem_object;
struct file;
@@ -17,6 +18,8 @@ struct file *shmem_create_from_object(struct
drm_i915_gem_object *obj);
void *shmem_pin_map(struct file *file);
void shmem_unpin_map(struct file *file, void *ptr);
+int shmem_read_to_dma_buf_map(struct file *file, loff_t off,
+ struct dma_buf_map *map, size_t len);
int shmem_read(struct file *file, loff_t off, void *dst, size_t len);
int shmem_write(struct file *file, loff_t off, void *src, size_t len);
--
2.35.0
[Intel-gfx] [PATCH 02/19] dma-buf-map: Add helper to initialize second map
When dma_buf_map struct is passed around, it's useful to be able to
initialize a second map that takes care of reading/writing to an offset
of the original map.
Add a helper that copies the struct and add the offset to the proper
address.
Cc: Sumit Semwal
Cc: Christian König
Cc: linux-me...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: linaro-mm-...@lists.linaro.org
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Lucas De Marchi
---
include/linux/dma-buf-map.h | 29 +
1 file changed, 29 insertions(+)
diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h
index 65e927d9ce33..3514a859f628 100644
--- a/include/linux/dma-buf-map.h
+++ b/include/linux/dma-buf-map.h
@@ -131,6 +131,35 @@ struct dma_buf_map {
.is_iomem = false, \
}
+/**
+ * DMA_BUF_MAP_INIT_OFFSET - Initializes struct dma_buf_map from another
dma_buf_map
+ * @map_: The dma-buf mapping structure to copy from
+ * @offset:Offset to add to the other mapping
+ *
+ * Initializes a new dma_buf_struct based on another. This is the equivalent
of doing:
+ *
+ * .. code-block: c
+ *
+ * dma_buf_map map = other_map;
+ * dma_buf_map_incr(, );
+ *
+ * Example usage:
+ *
+ * .. code-block: c
+ *
+ * void foo(struct device *dev, struct dma_buf_map *base_map)
+ * {
+ * ...
+ * struct dma_buf_map = DMA_BUF_MAP_INIT_OFFSET(base_map,
FIELD_OFFSET);
+ * ...
+ * }
+ */
+#define DMA_BUF_MAP_INIT_OFFSET(map_, offset_) (struct dma_buf_map)\
+ { \
+ .vaddr = (map_)->vaddr + (offset_), \
+ .is_iomem = (map_)->is_iomem, \
+ }
+
/**
* dma_buf_map_set_vaddr - Sets a dma-buf mapping structure to an address in
system memory
* @map: The dma-buf mapping structure
--
2.35.0
[Intel-gfx] [PATCH 13/19] drm/i915/guc: Convert mapping table to dma_buf_map
Use dma_buf_map to write the fields system_info.mapping_table[][].
Since we already have the info_map around where needed, just use it
instead of going through guc->ads_map.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 8e4768289792..dca7c3db9cdd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -204,7 +204,7 @@ int intel_guc_global_policies_update(struct intel_guc *guc)
}
static void guc_mapping_table_init(struct intel_gt *gt,
- struct guc_gt_system_info *system_info)
+ struct dma_buf_map *info_map)
{
unsigned int i, j;
struct intel_engine_cs *engine;
@@ -213,14 +213,14 @@ static void guc_mapping_table_init(struct intel_gt *gt,
/* Table must be set to invalid values for entries not used */
for (i = 0; i < GUC_MAX_ENGINE_CLASSES; ++i)
for (j = 0; j < GUC_MAX_INSTANCES_PER_CLASS; ++j)
- system_info->mapping_table[i][j] =
- GUC_MAX_INSTANCES_PER_CLASS;
+ info_map_write(info_map, mapping_table[i][j],
+ GUC_MAX_INSTANCES_PER_CLASS);
for_each_engine(engine, gt, id) {
u8 guc_class = engine_class_to_guc_class(engine->class);
-
system_info->mapping_table[guc_class][ilog2(engine->logical_mask)] =
- engine->instance;
+ info_map_write(info_map,
mapping_table[guc_class][ilog2(engine->logical_mask)],
+ engine->instance);
}
}
@@ -595,7 +595,7 @@ static void __guc_ads_init(struct intel_guc *guc)
/* Golden contexts for re-initialising after a watchdog reset */
guc_prep_golden_context(guc);
- guc_mapping_table_init(guc_to_gt(guc), >system_info);
+ guc_mapping_table_init(guc_to_gt(guc), _map);
base = intel_guc_ggtt_offset(guc, guc->ads_vma);
--
2.35.0
[Intel-gfx] [PATCH 01/19] dma-buf-map: Add read/write helpers
In certain situations it's useful to be able to read or write to an
offset that is calculated by having the memory layout given by a struct
declaration. Usually we are going to read/write a u8, u16, u32 or u64.
Add a pair of macros dma_buf_map_read_field()/dma_buf_map_write_field()
to calculate the offset of a struct member and memcpy the data from/to
the dma_buf_map. We could use readb, readw, readl, readq and the write*
counterparts, however due to alignment issues this may not work on all
architectures. If alignment needs to be checked to call the right
function, it's not possible to decide at compile-time which function to
call: so just leave the decision to the memcpy function that will do
exactly that on IO memory or dereference the pointer.
Cc: Sumit Semwal
Cc: Christian König
Cc: linux-me...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: linaro-mm-...@lists.linaro.org
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Lucas De Marchi
---
include/linux/dma-buf-map.h | 81 +
1 file changed, 81 insertions(+)
diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h
index 19fa0b5ae5ec..65e927d9ce33 100644
--- a/include/linux/dma-buf-map.h
+++ b/include/linux/dma-buf-map.h
@@ -6,6 +6,7 @@
#ifndef __DMA_BUF_MAP_H__
#define __DMA_BUF_MAP_H__
+#include
#include
#include
@@ -229,6 +230,46 @@ static inline void dma_buf_map_clear(struct dma_buf_map
*map)
}
}
+/**
+ * dma_buf_map_memcpy_to_offset - Memcpy into offset of dma-buf mapping
+ * @dst: The dma-buf mapping structure
+ * @offset:The offset from which to copy
+ * @src: The source buffer
+ * @len: The number of byte in src
+ *
+ * Copies data into a dma-buf mapping with an offset. The source buffer is in
+ * system memory. Depending on the buffer's location, the helper picks the
+ * correct method of accessing the memory.
+ */
+static inline void dma_buf_map_memcpy_to_offset(struct dma_buf_map *dst,
size_t offset,
+ const void *src, size_t len)
+{
+ if (dst->is_iomem)
+ memcpy_toio(dst->vaddr_iomem + offset, src, len);
+ else
+ memcpy(dst->vaddr + offset, src, len);
+}
+
+/**
+ * dma_buf_map_memcpy_from_offset - Memcpy from offset of dma-buf mapping into
system memory
+ * @dst: Destination in system memory
+ * @src: The dma-buf mapping structure
+ * @src: The offset from which to copy
+ * @len: The number of byte in src
+ *
+ * Copies data from a dma-buf mapping with an offset. The dest buffer is in
+ * system memory. Depending on the mapping location, the helper picks the
+ * correct method of accessing the memory.
+ */
+static inline void dma_buf_map_memcpy_from_offset(void *dst, const struct
dma_buf_map *src,
+ size_t offset, size_t len)
+{
+ if (src->is_iomem)
+ memcpy_fromio(dst, src->vaddr_iomem + offset, len);
+ else
+ memcpy(dst, src->vaddr + offset, len);
+}
+
/**
* dma_buf_map_memcpy_to - Memcpy into dma-buf mapping
* @dst: The dma-buf mapping structure
@@ -263,4 +304,44 @@ static inline void dma_buf_map_incr(struct dma_buf_map
*map, size_t incr)
map->vaddr += incr;
}
+/**
+ * dma_buf_map_read_field - Read struct member from dma-buf mapping with
+ * arbitrary size and handling un-aligned accesses
+ *
+ * @map__: The dma-buf mapping structure
+ * @type__:The struct to be used containing the field to read
+ * @field__: Member from struct we want to read
+ *
+ * Read a value from dma-buf mapping calculating the offset and size: this
assumes
+ * the dma-buf mapping is aligned with a a struct type__. A single u8, u16, u32
+ * or u64 can be read, based on the offset and size of type__.field__.
+ */
+#define dma_buf_map_read_field(map__, type__, field__) ({
\
+ type__ *t__;
\
+ typeof(t__->field__) val__;
\
+ dma_buf_map_memcpy_from_offset(__, map__, offsetof(type__,
field__),\
+ sizeof(t__->field__));
\
+ val__;
\
+})
+
+/**
+ * dma_buf_map_write_field - Write struct member to the dma-buf mapping with
+ * arbitrary size and handling un-aligned accesses
+ *
+ * @map__: The dma-buf mapping structure
+ * @type__:The struct to be used containing the field to write
+ * @field__: Member from struct we want to write
+ * @val__: Value to be written
+ *
+ * Write a value to the dma-buf mapping calculating the offset and size.
+ * A single u8, u16, u32 or u64 can be written based on the offset and size of
+ * type__.field__.
+ */
+#define dma_buf_map_write_field(map__, type__, field__,
[Intel-gfx] [PATCH 05/19] drm/i915/guc: Add read/write helpers for ADS blob
Add helpers on top of dma_buf_map_read_field() /
dma_buf_map_write_field() functions so they always use the right
arguments and make code easier to read.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index c012858376f0..01d2c1ead680 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -59,6 +59,14 @@ struct __guc_ads_blob {
struct guc_mmio_reg regset[0];
} __packed;
+#define ads_blob_read(guc_, field_)\
+ dma_buf_map_read_field(&(guc_)->ads_map, struct __guc_ads_blob, \
+ field_)
+
+#define ads_blob_write(guc_, field_, val_) \
+ dma_buf_map_write_field(&(guc_)->ads_map, struct __guc_ads_blob,\
+ field_, val_)
+
static u32 guc_ads_regset_size(struct intel_guc *guc)
{
GEM_BUG_ON(!guc->ads_regset_size);
--
2.35.0
[Intel-gfx] [PATCH 06/19] drm/i915/guc: Convert golden context init to dma_buf_map
Now the map is saved during creation, so use it to initialize the
golden context, reading from shmem and writing to either system or IO
memory.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 25 +++---
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 01d2c1ead680..bcf52ac4fe35 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -473,18 +473,17 @@ static struct intel_engine_cs *find_engine_state(struct
intel_gt *gt, u8 engine_
static void guc_init_golden_context(struct intel_guc *guc)
{
- struct __guc_ads_blob *blob = guc->ads_blob;
struct intel_engine_cs *engine;
struct intel_gt *gt = guc_to_gt(guc);
+ struct dma_buf_map golden_context_map;
u32 addr_ggtt, offset;
u32 total_size = 0, alloc_size, real_size;
u8 engine_class, guc_class;
- u8 *ptr;
if (!intel_uc_uses_guc_submission(>uc))
return;
- GEM_BUG_ON(!blob);
+ GEM_BUG_ON(dma_buf_map_is_null(>ads_map));
/*
* Go back and fill in the golden context data now that it is
@@ -492,15 +491,15 @@ static void guc_init_golden_context(struct intel_guc *guc)
*/
offset = guc_ads_golden_ctxt_offset(guc);
addr_ggtt = intel_guc_ggtt_offset(guc, guc->ads_vma) + offset;
- ptr = ((u8 *)blob) + offset;
+
+ golden_context_map = DMA_BUF_MAP_INIT_OFFSET(>ads_map, offset);
for (engine_class = 0; engine_class <= MAX_ENGINE_CLASS;
++engine_class) {
if (engine_class == OTHER_CLASS)
continue;
guc_class = engine_class_to_guc_class(engine_class);
-
- if (!blob->system_info.engine_enabled_masks[guc_class])
+ if (!ads_blob_read(guc,
system_info.engine_enabled_masks[guc_class]))
continue;
real_size = intel_engine_context_size(gt, engine_class);
@@ -511,18 +510,20 @@ static void guc_init_golden_context(struct intel_guc *guc)
if (!engine) {
drm_err(>i915->drm, "No engine state recorded for
class %d!\n",
engine_class);
- blob->ads.eng_state_size[guc_class] = 0;
- blob->ads.golden_context_lrca[guc_class] = 0;
+ ads_blob_write(guc, ads.eng_state_size[guc_class], 0);
+ ads_blob_write(guc, ads.golden_context_lrca[guc_class],
0);
continue;
}
- GEM_BUG_ON(blob->ads.eng_state_size[guc_class] !=
+ GEM_BUG_ON(ads_blob_read(guc, ads.eng_state_size[guc_class]) !=
real_size - LRC_SKIP_SIZE);
- GEM_BUG_ON(blob->ads.golden_context_lrca[guc_class] !=
addr_ggtt);
+ GEM_BUG_ON(ads_blob_read(guc,
ads.golden_context_lrca[guc_class]) != addr_ggtt);
+
addr_ggtt += alloc_size;
- shmem_read(engine->default_state, 0, ptr, real_size);
- ptr += alloc_size;
+ shmem_read_to_dma_buf_map(engine->default_state, 0,
+ _context_map, real_size);
+ dma_buf_map_incr(_context_map, alloc_size);
}
GEM_BUG_ON(guc->ads_golden_ctxt_size != total_size);
--
2.35.0
[Intel-gfx] [PATCH 00/19] drm/i915/guc: Refactor ADS access to use dma_buf_map
While porting i915 to arm64 we noticed some issues accessing lmem. Some writes were getting corrupted and the final state of the buffer didn't have exactly what we wrote. This became evident when enabling GuC submission: depending on the number of engines the ADS struct was being corrupted and GuC would reject it, refusin to initialize. >From Documentation/core-api/bus-virt-phys-mapping.rst: This memory is called "PCI memory" or "shared memory" or "IO memory" or whatever, and there is only one way to access it: the readb/writeb and related functions. You should never take the address of such memory, because there is really nothing you can do with such an address: it's not conceptually in the same memory space as "real memory" at all, so you cannot just dereference a pointer. (Sadly, on x86 it **is** in the same memory space, so on x86 it actually works to just deference a pointer, but it's not portable). When reading or writing words directly to IO memory, in order to be portable the Linux kernel provides the abstraction detailed in section "Differences between I/O access functions" of Documentation/driver-api/device-io.rst. This limits our ability to simply overlay our structs on top a buffer and directly access it since that buffer may come from IO memory rather than system memory. Hence the approach taken in intel_guc_ads.c needs to be refactored. This is not the only place in i915 that neeed to be changed, but the one causing the most problems, with a real reproducer. This first set of patch focuses on fixing the gem object to pass the ADS After the addition of a few helpers in the dma_buf_map API, most of intel_guc_ads.c can be converted to use it. The exception is the regset initialization: we'd incur into a lot of extra indirection when reading/writting each register. So the regset is converted to use a temporary buffer allocated on probe, which is then copied to its final location when finishing the initialization or on gt reset. Testing on some discrete cards, after this change we can correctly pass the ADS struct to GuC and have it initialized correctly. thanks Lucas De Marchi Cc: linux-me...@vger.kernel.org Cc: dri-de...@lists.freedesktop.org Cc: linaro-mm-...@lists.linaro.org Cc: linux-ker...@vger.kernel.org Cc: Christian König Cc: Daniel Vetter Cc: Daniele Ceraolo Spurio Cc: David Airlie Cc: John Harrison Cc: Joonas Lahtinen Cc: Maarten Lankhorst Cc: Matt Roper Cc: Matthew Auld Cc: Matthew Brost Cc: Sumit Semwal Cc: Thomas Hellström Cc: Tvrtko Ursulin Lucas De Marchi (19): dma-buf-map: Add read/write helpers dma-buf-map: Add helper to initialize second map drm/i915/gt: Add helper for shmem copy to dma_buf_map drm/i915/guc: Keep dma_buf_map of ads_blob around drm/i915/guc: Add read/write helpers for ADS blob drm/i915/guc: Convert golden context init to dma_buf_map drm/i915/guc: Convert policies update to dma_buf_map drm/i915/guc: Convert engine record to dma_buf_map dma-buf-map: Add wrapper over memset drm/i915/guc: Convert guc_ads_private_data_reset to dma_buf_map drm/i915/guc: Convert golden context prep to dma_buf_map drm/i915/guc: Replace check for golden context size drm/i915/guc: Convert mapping table to dma_buf_map drm/i915/guc: Convert capture list to dma_buf_map drm/i915/guc: Prepare for error propagation drm/i915/guc: Use a single pass to calculate regset drm/i915/guc: Convert guc_mmio_reg_state_init to dma_buf_map drm/i915/guc: Convert __guc_ads_init to dma_buf_map drm/i915/guc: Remove plain ads_blob pointer drivers/gpu/drm/i915/gt/shmem_utils.c | 32 ++ drivers/gpu/drm/i915/gt/shmem_utils.h | 3 + drivers/gpu/drm/i915/gt/uc/intel_guc.h| 14 +- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c| 374 +++--- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h| 3 +- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 11 +- include/linux/dma-buf-map.h | 127 ++ 7 files changed, 405 insertions(+), 159 deletions(-) -- 2.35.0
[Intel-gfx] [PATCH 04/19] drm/i915/guc: Keep dma_buf_map of ads_blob around
Convert intel_guc_ads_create() and initialization to use dma_buf_map
rather than plain pointer and save it in the guc struct. This will help
with additional updates to the ads_blob after the
creation/initialization by abstracting the IO vs system memory.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 4 +++-
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 6 ++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 697d9d66acef..e2e0df1c3d91 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -6,8 +6,9 @@
#ifndef _INTEL_GUC_H_
#define _INTEL_GUC_H_
-#include
#include
+#include
+#include
#include "intel_uncore.h"
#include "intel_guc_fw.h"
@@ -148,6 +149,7 @@ struct intel_guc {
struct i915_vma *ads_vma;
/** @ads_blob: contents of the GuC ADS */
struct __guc_ads_blob *ads_blob;
+ struct dma_buf_map ads_map;
/** @ads_regset_size: size of the save/restore regsets in the ADS */
u32 ads_regset_size;
/** @ads_golden_ctxt_size: size of the golden contexts in the ADS */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 668bf4ac9b0c..c012858376f0 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -623,6 +623,11 @@ int intel_guc_ads_create(struct intel_guc *guc)
if (ret)
return ret;
+ if (i915_gem_object_is_lmem(guc->ads_vma->obj))
+ dma_buf_map_set_vaddr_iomem(>ads_map, (void __iomem
*)guc->ads_blob);
+ else
+ dma_buf_map_set_vaddr(>ads_map, guc->ads_blob);
+
__guc_ads_init(guc);
return 0;
@@ -644,6 +649,7 @@ void intel_guc_ads_destroy(struct intel_guc *guc)
{
i915_vma_unpin_and_release(>ads_vma, I915_VMA_RELEASE_MAP);
guc->ads_blob = NULL;
+ dma_buf_map_clear(>ads_map);
}
static void guc_ads_private_data_reset(struct intel_guc *guc)
--
2.35.0
[Intel-gfx] [PATCH 09/19] dma-buf-map: Add wrapper over memset
Just like memcpy_toio(), there is also need to write a direct value to a
memory block. Add dma_buf_map_memset() to abstract memset() vs memset_io()
Cc: Matt Roper
Cc: Sumit Semwal
Cc: Christian König
Cc: linux-me...@vger.kernel.org
Cc: dri-de...@lists.freedesktop.org
Cc: linaro-mm-...@lists.linaro.org
Cc: linux-ker...@vger.kernel.org
Signed-off-by: Lucas De Marchi
---
include/linux/dma-buf-map.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/include/linux/dma-buf-map.h b/include/linux/dma-buf-map.h
index 3514a859f628..c9fb04264cd0 100644
--- a/include/linux/dma-buf-map.h
+++ b/include/linux/dma-buf-map.h
@@ -317,6 +317,23 @@ static inline void dma_buf_map_memcpy_to(struct
dma_buf_map *dst, const void *sr
memcpy(dst->vaddr, src, len);
}
+/**
+ * dma_buf_map_memset - Memset into dma-buf mapping
+ * @dst: The dma-buf mapping structure
+ * @value: The value to set
+ * @len: The number of bytes to set in dst
+ *
+ * Set value in dma-buf mapping. Depending on the buffer's location, the helper
+ * picks the correct method of accessing the memory.
+ */
+static inline void dma_buf_map_memset(struct dma_buf_map *dst, int value,
size_t len)
+{
+ if (dst->is_iomem)
+ memset_io(dst->vaddr_iomem, value, len);
+ else
+ memset(dst->vaddr, value, len);
+}
+
/**
* dma_buf_map_incr - Increments the address stored in a dma-buf mapping
* @map: The dma-buf mapping structure
--
2.35.0
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Initial support for small BAR recovery
== Series Details == Series: Initial support for small BAR recovery URL : https://patchwork.freedesktop.org/series/99370/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Initial support for small BAR recovery
== Series Details ==
Series: Initial support for small BAR recovery
URL : https://patchwork.freedesktop.org/series/99370/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8c8317fbf210 drm: improve drm_buddy_alloc function
-:399: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON &
recovery code rather than BUG() or BUG_ON()
#399: FILE: drivers/gpu/drm/drm_buddy.c:586:
+ BUG_ON(order > mm->max_order);
-:400: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON &
recovery code rather than BUG() or BUG_ON()
#400: FILE: drivers/gpu/drm/drm_buddy.c:587:
+ BUG_ON(order < min_order);
-:527: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#527: FILE: drivers/gpu/drm/i915/i915_ttm_buddy_manager.c:88:
+ err = drm_buddy_alloc_blocks(mm, (u64)place->fpfn << PAGE_SHIFT,
+ (u64)lpfn << PAGE_SHIFT,
total: 0 errors, 2 warnings, 1 checks, 545 lines checked
06e1414d96cc drm: implement top-down allocation method
3bd9f95ffd60 drm: implement a method to free unused pages
106d4bacced1 drm/i915: add io_size plumbing
-:130: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#130: FILE: drivers/gpu/drm/i915/gt/intel_region_lmem.c:238:
+ drm_info(>drm, "Local memory IO size: %pa\n",
+ >io_size);
total: 0 errors, 0 warnings, 1 checks, 187 lines checked
ecf0c57686a0 drm/i915/ttm: require mappable by default
1577ab960e49 drm/i915: add I915_BO_ALLOC_TOPDOWN
fe790c61b74c drm/i915/buddy: track available visible size
b8dc57a8a6f5 drm/i915/buddy: adjust res->start
dfdefb960877 drm/i915/buddy: tweak 2big check
3a1b1417e181 drm/i915/selftests: mock test io_size
-:62: WARNING:LINE_SPACING: Missing a blank line after declarations
#62: FILE: drivers/gpu/drm/i915/selftests/intel_memory_region.c:548:
+ u64 size;
+ I915_RND_STATE(prng);
total: 0 errors, 1 warnings, 0 checks, 161 lines checked
9937084d5576 drm/i915/ttm: tweak priority hint selection
bd1c8f577dbe drm/i915/ttm: make eviction mappable aware
-:9: WARNING:REPEATED_WORD: Possible repeated word: 'some'
#9:
If we need to make room for some some mappable object, then we should
total: 0 errors, 1 warnings, 0 checks, 97 lines checked
5398c571b14c drm/i915/ttm: mappable migration on fault
-:38: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#38: FILE: drivers/gpu/drm/i915/gem/i915_gem_ttm.c:651:
{
+
total: 0 errors, 0 warnings, 1 checks, 104 lines checked
d96b8b24ddab drm/i915/selftests: exercise mmap migration
-:119: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#119: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:1091:
+ pr_info("igt_mmap(%s, %d) @ %lx\n",
+obj->mm.region->name, I915_MMAP_TYPE_FIXED, addr);
-:182: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#182: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:1154:
+#define IGT_MMAP_MIGRATE_TOPDOWN (1<<0)
^
-:183: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#183: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:1155:
+#define IGT_MMAP_MIGRATE_FILL(1<<1)
^
-:184: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#184: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:1156:
+#define IGT_MMAP_MIGRATE_EVICTABLE (1<<2)
^
-:185: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#185: FILE: drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:1157:
+#define IGT_MMAP_MIGRATE_UNFAULTABLE (1<<3)
^
total: 0 errors, 0 warnings, 5 checks, 324 lines checked
4de3a89e9ae6 drm/i915/selftests: handle allocation failures
0187997a140b drm/i915/create: apply ALLOC_TOPDOWN by default
fc67630543c9 drm/i915/uapi: add NEEDS_CPU_ACCESS hint
-:118: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#118: FILE: include/uapi/drm/i915_drm.h:3189:
+#define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1<<0)
^
total: 0 errors, 0 warnings, 1 checks, 89 lines checked
82b5e5021221 drm/i915/uapi: forbid ALLOC_TOPDOWN for error capture
-:17: WARNING:BAD_SIGN_OFF: Duplicate signature
#17:
Reported-by: kernel test robot
total: 0 errors, 1 warnings, 0 checks, 35 lines checked
2ec2549ba3d3 drm/i915/lmem: don't treat small BAR as an error
0e4cc9d13568 HAX: DG1 small BAR
Re: [Intel-gfx] [PATCH 6/9] drm/i915: Clean up PIPESRC defines
On Wed, Jan 26, 2022 at 04:42:52PM +0200, Jani Nikula wrote: > On Fri, 12 Nov 2021, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > Use REG_GENMASK() & co. when dealing with PIPESRC. > > > > Signed-off-by: Ville Syrjälä > > --- > > drivers/gpu/drm/i915/display/i9xx_plane.c| 4 ++-- > > drivers/gpu/drm/i915/display/intel_display.c | 7 --- > > drivers/gpu/drm/i915/i915_reg.h | 4 > > 3 files changed, 10 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c > > b/drivers/gpu/drm/i915/display/i9xx_plane.c > > index 2194f74101ae..f586e39cb378 100644 > > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c > > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c > > @@ -1048,8 +1048,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, > > plane_config->base = base; > > > > val = intel_de_read(dev_priv, PIPESRC(pipe)); > > - fb->width = ((val >> 16) & 0xfff) + 1; > > - fb->height = ((val >> 0) & 0xfff) + 1; > > I guess the mask width change is worth noting in the commit message. Aye. I added a few notes about this and the DSL stuff. > > Reviewed-by: Jani Nikula Thanks. Series pushed to drm-intel-next. -- Ville Syrjälä Intel
[Intel-gfx] ✗ Fi.CI.BAT: failure for Initial support for small BAR recovery
== Series Details ==
Series: Initial support for small BAR recovery
URL : https://patchwork.freedesktop.org/series/99370/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11146 -> Patchwork_22114
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22114 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22114, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/index.html
Participating hosts (40 -> 44)
--
Additional (8): bat-dg1-6 bat-dg1-5 fi-icl-u2 bat-adlp-6 fi-pnv-d510
bat-rpls-1 bat-jsl-2 bat-jsl-1
Missing(4): fi-ctg-p8600 fi-bsw-cyan fi-bdw-samus fi-hsw-4200u
Possible new issues
---
Here are the unknown changes that may have been introduced in Patchwork_22114:
### IGT changes ###
Possible regressions
* igt@i915_selftest@live@gem_contexts:
- bat-dg1-5: NOTRUN -> [INCOMPLETE][1]
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-5/igt@i915_selftest@live@gem_contexts.html
* igt@i915_selftest@live@hugepages:
- bat-dg1-6: NOTRUN -> [INCOMPLETE][2]
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-6/igt@i915_selftest@l...@hugepages.html
* igt@kms_frontbuffer_tracking@basic:
- bat-dg1-5: NOTRUN -> [CRASH][3]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-5/igt@kms_frontbuffer_track...@basic.html
Suppressed
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- {bat-adlp-6}: NOTRUN -> [DMESG-WARN][4]
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-adlp-6/igt@kms_addfb_ba...@addfb25-framebuffer-vs-set-tiling.html
Known issues
Here are the changes found in Patchwork_22114 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][5] ([fdo#109315]) +17 similar issues
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/fi-icl-u2/igt@amdgpu/amd_cs_...@fork-gfx0.html
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][6] ([fdo#109271]) +17 similar issues
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@core_hotunplug@unbind-rebind:
- fi-pnv-d510:NOTRUN -> [FAIL][7] ([i915#3194])
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/fi-pnv-d510/igt@core_hotunp...@unbind-rebind.html
* igt@fbdev@info:
- bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#2582]) +4 similar issues
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-6/igt@fb...@info.html
* igt@gem_exec_gttfill@basic:
- bat-dg1-6: NOTRUN -> [SKIP][9] ([i915#4086])
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-6/igt@gem_exec_gttf...@basic.html
- bat-dg1-5: NOTRUN -> [SKIP][10] ([i915#4086])
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-5/igt@gem_exec_gttf...@basic.html
* igt@gem_huc_copy@huc-copy:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([i915#2190])
[11]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/fi-icl-u2/igt@gem_huc_c...@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][12] ([i915#4613]) +3 similar issues
[12]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/fi-icl-u2/igt@gem_lmem_swapp...@parallel-random-engines.html
* igt@gem_mmap@basic:
- bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#4083])
[13]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-6/igt@gem_m...@basic.html
- bat-dg1-5: NOTRUN -> [SKIP][14] ([i915#4083])
[14]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-5/igt@gem_m...@basic.html
* igt@gem_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#4077]) +2 similar issues
[15]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-6/igt@gem_tiled_bl...@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-dg1-5: NOTRUN -> [SKIP][16] ([i915#4077]) +2 similar issues
[16]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22114/bat-dg1-5/igt@gem_tiled_fence_bl...@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-5: NOTRUN -> [SKIP][17] ([i915#4079]) +1 similar issue
[17]:
Re: [Intel-gfx] [PATCH v2 1/6] drm/i915/perf: Move OA regs to their own header
On Mon, Jan 24, 2022 at 06:08:21PM -0800, Matt Roper wrote: The OA unit registers are only used by the perf code; move them to their own header file. Cc: Jani Nikula Cc: Umesh Nerlige Ramappa Cc: Lionel Landwerlin Signed-off-by: Matt Roper I checked the output from git show --color-moved to help and indeed this is just moving the registers. Also, looking at the register names, they all seem to be OA/perf related. Reviewed-by: Lucas De Marchi Lucas De Marchi
[Intel-gfx] [PATCH 16/19] drm/i915/guc: Use a single pass to calculate regset
The ADS initialitazion was using 2 passes to calculate the regset sent
to GuC to initialize each engine: the first pass to just have the final
object size and the second to set each register in place in the final
gem object.
However in order to maintain an ordered set of registers to pass to guc,
each register needs to be added and moved in the final array. The second
phase may actually happen in IO memory rather than system memory and
accessing IO memory by simply dereferencing the pointer doesn't work on
all architectures. Other places of the ADS initializaition were
converted to use the dma_buf_map API, but here there may be a lot more
accesses to IO memory. So, instead of following that same approach,
convert the regset initialization to calculate the final array in 1
pass and in the second pass that array is just copied to its final
location, updating the pointers for each engine written to the ADS blob.
One important thing is that struct temp_regset now have
different semantics: `registers` continues to track the registers of a
single engine, however the other fields are updated together, according
to the newly added `storage`, which tracks the memory allocated for
all the registers. So rename some of these fields and add a
__mmio_reg_add(): this function (possibly) allocates memory and operates
on the storage pointer while guc_mmio_reg_add() continues to manage the
registers pointer.
On a Tiger Lake system using enable_guc=3, the following log message is
now seen:
[ 187.334310] i915 :00:02.0: [drm:intel_guc_ads_create [i915]]
Used 4 KB for temporary ADS regset
This change has also been tested on an ARM64 host with DG2 and other
discrete graphics cards.
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h | 7 ++
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 117 +
2 files changed, 79 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index e2e0df1c3d91..4c852eee3ad8 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -152,6 +152,13 @@ struct intel_guc {
struct dma_buf_map ads_map;
/** @ads_regset_size: size of the save/restore regsets in the ADS */
u32 ads_regset_size;
+ /**
+* @ads_regset_count: number of save/restore registers in the ADS for
+* each engine
+*/
+ u32 ads_regset_count[I915_NUM_ENGINES];
+ /** @ads_regset: save/restore regsets in the ADS */
+ struct guc_mmio_reg *ads_regset;
/** @ads_golden_ctxt_size: size of the golden contexts in the ADS */
u32 ads_golden_ctxt_size;
/** @ads_engine_usage_size: size of engine usage in the ADS */
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index 73ca34de44f7..390101ee3661 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -226,14 +226,13 @@ static void guc_mapping_table_init(struct intel_gt *gt,
/*
* The save/restore register list must be pre-calculated to a temporary
- * buffer of driver defined size before it can be generated in place
- * inside the ADS.
+ * buffer before it can be copied inside the ADS.
*/
-#define MAX_MMIO_REGS 128 /* Arbitrary size, increase as needed */
struct temp_regset {
struct guc_mmio_reg *registers;
- u32 used;
- u32 size;
+ struct guc_mmio_reg *storage;
+ u32 storage_used;
+ u32 storage_max;
};
static int guc_mmio_reg_cmp(const void *a, const void *b)
@@ -244,18 +243,44 @@ static int guc_mmio_reg_cmp(const void *a, const void *b)
return (int)ra->offset - (int)rb->offset;
}
+static struct guc_mmio_reg * __must_check
+__mmio_reg_add(struct temp_regset *regset, struct guc_mmio_reg *reg)
+{
+ u32 pos = regset->storage_used;
+ struct guc_mmio_reg *slot;
+
+ if (pos >= regset->storage_max) {
+ size_t size = ALIGN((pos + 1) * sizeof(*slot), PAGE_SIZE);
+ struct guc_mmio_reg *r = krealloc(regset->storage,
+ size, GFP_KERNEL);
+ if (!r) {
+ WARN_ONCE(1, "Incomplete regset list: can't add
register (%d)\n",
+ -ENOMEM);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ regset->registers = r + (regset->registers - regset->storage);
+ regset->storage = r;
+ regset->storage_max = size / sizeof(*slot);
+ }
+
+ slot = >storage[pos];
+ regset->storage_used++;
+ *slot = *reg;
+
+ return slot;
+}
+
static long __must_check guc_mmio_reg_add(struct temp_regset *regset,
[Intel-gfx] [PATCH 18/19] drm/i915/guc: Convert __guc_ads_init to dma_buf_map
Now that all the called functions from __guc_ads_init() are converted to
use ads_map, stop using ads_blob in __guc_ads_init().
Cc: Matt Roper
Cc: Thomas Hellström
Cc: Daniel Vetter
Cc: John Harrison
Cc: Matthew Brost
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 25 --
1 file changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
index cb0f543b0e86..30edac93afbf 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c
@@ -602,7 +602,6 @@ static void __guc_ads_init(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
struct drm_i915_private *i915 = gt->i915;
- struct __guc_ads_blob *blob = guc->ads_blob;
struct dma_buf_map info_map = DMA_BUF_MAP_INIT_OFFSET(>ads_map,
offsetof(struct __guc_ads_blob, system_info));
u32 base;
@@ -613,17 +612,18 @@ static void __guc_ads_init(struct intel_guc *guc)
/* System info */
fill_engine_enable_masks(gt, _map);
-
blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED] =
- hweight8(gt->info.sseu.slice_mask);
-
blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK]
=
- gt->info.vdbox_sfc_access;
+ ads_blob_write(guc,
system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED],
+ hweight8(gt->info.sseu.slice_mask));
+ ads_blob_write(guc,
system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK],
+ gt->info.vdbox_sfc_access);
if (GRAPHICS_VER(i915) >= 12 && !IS_DGFX(i915)) {
u32 distdbreg = intel_uncore_read(gt->uncore,
GEN12_DIST_DBS_POPULATED);
-
blob->system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI]
=
- ((distdbreg >> GEN12_DOORBELLS_PER_SQIDI_SHIFT) &
-GEN12_DOORBELLS_PER_SQIDI) + 1;
+ ads_blob_write(guc,
+
system_info.generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI],
+ ((distdbreg >> GEN12_DOORBELLS_PER_SQIDI_SHIFT)
+ & GEN12_DOORBELLS_PER_SQIDI) + 1);
}
/* Golden contexts for re-initialising after a watchdog reset */
@@ -637,14 +637,17 @@ static void __guc_ads_init(struct intel_guc *guc)
guc_capture_list_init(guc);
/* ADS */
- blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
- blob->ads.gt_system_info = base + ptr_offset(blob, system_info);
+ ads_blob_write(guc, ads.scheduler_policies, base +
+ offsetof(struct __guc_ads_blob, policies));
+ ads_blob_write(guc, ads.gt_system_info, base +
+ offsetof(struct __guc_ads_blob, system_info));
/* MMIO save/restore list */
guc_mmio_reg_state_init(guc);
/* Private Data */
- blob->ads.private_data = base + guc_ads_private_data_offset(guc);
+ ads_blob_write(guc, ads.private_data, base +
+ guc_ads_private_data_offset(guc));
i915_gem_object_flush_map(guc->ads_vma->obj);
}
--
2.35.0
Re: [Intel-gfx] [PATCH v5 02/10] drm/i915/guc: Add XE_LP registers for GuC error state capture.
Thanks Jani for taking the time to review...
1. apologies on the const issue, this is my bad, i think it was
one of the comments from earlier rev not sure how i missed it.
Will fix this on next rev.
2. I do have a question below on the const for one of specific types
of tables. Need your thoughts
...alan
On Wed, 2022-01-26 at 20:13 +0200, Jani Nikula wrote:
> On Wed, 26 Jan 2022, Alan Previn wrote:
> > Add device specific tables and register lists to cover different engines
> > class types for GuC error state capture for XE_LP products.
> >
...
> > +static struct __ext_steer_reg xelpd_extregs[] = {
> > + {"GEN7_SAMPLER_INSTDONE", GEN7_SAMPLER_INSTDONE},
> > + {"GEN7_ROW_INSTDONE", GEN7_ROW_INSTDONE}
> > +};
>
> Either this needs to be const or, if it needs to be mutable, moved to
> device specific data.
>
> Ditto for all such things all over the place.
>
> BR,
> Jani.
I had a question though... the list of registers like the one above as well
as below shall be made const... however, the table-of-lists (see farther down),
contains a pointer to "extended_regs"
that shall be allocated at startup - is it okay for that list to remain
non-const
since the others with actual register offsets remain const?
Alan: will add const for this and above tables:
static struct __guc_mmio_reg_descr xe_lpd_global_regs[] = {
COMMON_BASE_GLOBAL(),
COMMON_GEN9BASE_GLOBAL(),
COMMON_GEN12BASE_GLOBAL(),
};
Is this okay to not be const?:
static struct __guc_mmio_reg_descr_group default_lists[] = {
MAKE_REGLIST(default_global_regs, PF, GLOBAL, 0),
MAKE_REGLIST(default_rc_class_regs, PF, ENGINE_CLASS,
GUC_RENDER_CLASS),
MAKE_REGLIST(xe_lpd_rc_inst_regs, PF, ENGINE_INSTANCE,
GUC_RENDER_CLASS),
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS,
GUC_VIDEO_CLASS),
MAKE_REGLIST(xe_lpd_vd_inst_regs, PF, ENGINE_INSTANCE,
GUC_VIDEO_CLASS),
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS,
GUC_VIDEOENHANCE_CLASS),
MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE,
GUC_VIDEOENHANCE_CLASS),
MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS,
GUC_BLITTER_CLASS),
MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE,
GUC_BLITTER_CLASS),
{}
};
Re: [Intel-gfx] [PATCH v2 2/6] drm/i915/perf: Express OA register ranges with i915_range
On Mon, Jan 24, 2022 at 06:08:22PM -0800, Matt Roper wrote: Let's use 'struct i915_range' to express sets of b-counter and mux registers in the perf code. This makes the code more similar to how we handle things like multicast register ranges, forcewake tables, shadow tables, etc. and also lets us avoid needing symbolic register name definitions for the various range end points. With this change, many of the OA register definitions are no longer used in the code, so we can drop their #define's for simplicity. v2: Drop 'inline' from reg_in_range_table(). (Jani) Cc: Jani Nikula Cc: Umesh Nerlige Ramappa Cc: Lionel Landwerlin Signed-off-by: Matt Roper I didn't come up with an idea to review the table ranges, but agree with the change: Acked-by: Lucas De Marchi Lucas De Marchi
Re: [Intel-gfx] [PATCH v2 3/6] drm/i915: Parameterize R_PWR_CLK_STATE register definition
On Mon, Jan 24, 2022 at 06:08:23PM -0800, Matt Roper wrote: At the moment we only use R_PWR_CLK_STATE in the context of the RCS engine, but upcoming support for compute engines will start using instances relative to the CCS engine base offsets. Let's parameterize the register and move it to the engine reg header. Cc: Jani Nikula Signed-off-by: Matt Roper Reviewed-by: Lucas De Marchi Lucas De Marchi
Re: [Intel-gfx] [PATCH v2 4/6] drm/i915: Parameterize MI_PREDICATE registers
On Mon, Jan 24, 2022 at 06:08:24PM -0800, Matt Roper wrote: The various MI_PREDICATE registers have per-engine instances. Today we only utilize the RCS0 instance of each, but that will likely change in the future; switch to parameterized register definitions to make these easier to work with going forward. Of special note is MI_PREDICATE_RESULT_2; we only use it in one place in the driver today in HSW-specific code. It turns out that the bspec (page 94) lists two different offsets for this register on HSW; one is in the standard location shared by all other platforms (base + 0x3bc) and the other is an unusual location (0x2214). We're using the second, non-standard offset in i915 today; that offset doesn't exist on any other platforms (and it's not even 100% clear that it's correct for HSW) so I've renamed the current non-standard definition to HSW_MI_PREDICATE_RESULT_2; the new cross-platform parameterized macro (which is still unused at the moment) uses the standard offset. Cc: Jani Nikula Signed-off-by: Matt Roper Reviewed-by: Lucas De Marchi Lucas De Marchi
Re: [Intel-gfx] [PATCH v2 5/6] drm/i915: Move GT registers to their own header file
On Mon, Jan 24, 2022 at 06:08:25PM -0800, Matt Roper wrote: +#define MEMSWCTL _MMIO(0x11170) /* Ironlake only */ +#define MEMCTL_CMD_MASK 0xe000 +#define MEMCTL_CMD_SHIFT 13 +#define MEMCTL_CMD_RCLK_OFF 0 +#define MEMCTL_CMD_RCLK_ON 1 +#define MEMCTL_CMD_CHFREQ2 +#define MEMCTL_CMD_CHVID 3 +#define MEMCTL_CMD_VMMOFF4 +#define MEMCTL_CMD_VMMON 5 +#define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears +when command complete */ formatting issue here +#define GEN9_SLICE_PGCTL_ACK(slice)_MMIO(0x804c + (slice) * 0x4) +#define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ +((slice) % 3) * 0x4) and here +#define GEN9_PGCTL_SLICE_ACK (1 << 0) +#define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2)) +#define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F) + +#define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) +#define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ +((slice) % 3) * 0x8) and here +#define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) +#define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ +((slice) % 3) * 0x8) and here. Rest looks sane. There's already a conflict in this patch, although following "this should be just code move", it's easy to solve. I wonder what is the strategy going to be for merging this because it will conflict badly between drm-intel-next and drm-intel-gt-next. Reviewed-by: Lucas De Marchi Lucas De Marchi
Re: [Intel-gfx] [PATCH v2 6/6] drm/i915: Only include i915_reg.h from .c files
On Mon, Jan 24, 2022 at 06:08:26PM -0800, Matt Roper wrote: Several of our i915 header files, have been including i915_reg.h. This means that any change to i915_reg.h will trigger a full rebuild of pretty much every file of the driver, even those that don't have any kind of register access. Let's delete the i915_reg.h include from all headers and include an explicit include from the .c files that truly if you're going to respin this or while applying, it may be good to reword this sentence as we have too many "include". Reviewed-by: Lucas De Marchi Lucas De Marchi
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev2)
== Series Details == Series: drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev2) URL : https://patchwork.freedesktop.org/series/98801/ State : warning == Summary == $ dim checkpatch origin/drm-tip 071c4ebbb036 drm/i915/display/vrr: Reset VRR capable property on a long hpd -:7: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line) #7: With some VRR panels, user can turn VRR ON/OFF on the fly from the panel settings. total: 0 errors, 1 warnings, 0 checks, 33 lines checked
Re: [Intel-gfx] [PATCH v5 01/10] drm/i915/guc: Update GuC ADS size for error capture lists
On Wed, Jan 26, 2022 at 02:48:13AM -0800, Alan Previn wrote:
Update GuC ADS size allocation to include space for
the lists of error state capture register descriptors.
Also, populate the lists of registers we want GuC to report back to
Host on engine reset events. This list should include global,
engine-class and engine-instance registers for every engine-class
type on the current hardware.
NOTE: Start with a sample table of register lists to layout the
framework before adding real registers in subsequent patch.
Signed-off-by: Alan Previn
---
...
static void __guc_ads_init(struct intel_guc *guc)
{
struct intel_gt *gt = guc_to_gt(guc);
@@ -573,9 +553,9 @@ static void __guc_ads_init(struct intel_guc *guc)
base = intel_guc_ggtt_offset(guc, guc->ads_vma);
- /* Capture list for hang debug */
- guc_capture_list_init(guc, blob);
-
+ /* Lists for error capture debug */
+ intel_guc_capture_prep_lists(guc, (struct guc_ads *)blob, base,
no, please don't cast/export struct guc_ads like this. We can't really
dereference it since it may be in IO memory.
See https://patchwork.freedesktop.org/series/99378/ with the huge
refactor in this file to make it conform to the rules of accessing IO
memory.
Maybe this list could be appended in the same reglist buffer and we just
copy it once to its final location, like we are doing with the reglist?
Lucas De Marchi
[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev2)
== Series Details ==
Series: drm/i915/display/vrr: Reset VRR capable property on a long hpd (rev2)
URL : https://patchwork.freedesktop.org/series/98801/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11147 -> Patchwork_22115
Summary
---
**FAILURE**
Serious unknown changes coming with Patchwork_22115 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22115, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22115/index.html
Participating hosts (48 -> 16)
--
ERROR: It appears as if the changes made in Patchwork_22115 prevented too
many machines from booting.
Additional (1): bat-adls-5
Missing(33): fi-kbl-soraka fi-bdw-gvtdvm fi-icl-u2 fi-apl-guc
fi-snb-2520m fi-pnv-d510 fi-skl-6600u fi-snb-2600 fi-cml-u2 fi-bxt-dsi
fi-bdw-5557u fi-bsw-n3050 fi-glk-dsi fi-ilk-650 fi-kbl-7500u fi-ctg-p8600
fi-hsw-4770 fi-ivb-3770 fi-elk-e7500 fi-bsw-nick fi-skl-6700k2 fi-kbl-7567u
fi-skl-guc fi-cfl-8700k fi-hsw-4200u fi-bsw-cyan fi-cfl-guc fi-kbl-guc
fi-kbl-x1275 fi-cfl-8109u fi-kbl-8809g fi-bsw-kefka fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22115 that come from known issues:
### IGT changes ###
Issues hit
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: [PASS][1] -> [DMESG-FAIL][2] ([i915#4494])
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22115/bat-dg1-5/igt@i915_selftest@l...@hangcheck.html
Possible fixes
* igt@i915_selftest@live@gt_pm:
- {fi-jsl-1}: [DMESG-FAIL][3] ([i915#1886]) -> [PASS][4]
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22115/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
Build changes
-
* Linux: CI_DRM_11147 -> Patchwork_22115
CI-20190529: 20190529
CI_DRM_11147: ad57bf1ff13e1c4462f947398fbfb861f1b2e345 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6335: 2b30115edd692b60d16cb10375730a87f51f0e37 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22115: 071c4ebbb036b0f740a0a3b497efb2ad50588e54 @
git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
071c4ebbb036 drm/i915/display/vrr: Reset VRR capable property on a long hpd
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22115/index.html
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/guc: Refactor ADS access to use dma_buf_map
== Series Details ==
Series: drm/i915/guc: Refactor ADS access to use dma_buf_map
URL : https://patchwork.freedesktop.org/series/99378/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
65454816ee9c dma-buf-map: Add read/write helpers
-:105: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'type__' may be better as
'(type__)' to avoid precedence issues
#105: FILE: include/linux/dma-buf-map.h:319:
+#define dma_buf_map_read_field(map__, type__, field__) ({
\
+ type__ *t__;
\
+ typeof(t__->field__) val__;
\
+ dma_buf_map_memcpy_from_offset(__, map__, offsetof(type__,
field__),\
+ sizeof(t__->field__));
\
+ val__;
\
+})
-:105: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'field__' - possible
side-effects?
#105: FILE: include/linux/dma-buf-map.h:319:
+#define dma_buf_map_read_field(map__, type__, field__) ({
\
+ type__ *t__;
\
+ typeof(t__->field__) val__;
\
+ dma_buf_map_memcpy_from_offset(__, map__, offsetof(type__,
field__),\
+ sizeof(t__->field__));
\
+ val__;
\
+})
-:105: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'field__' may be better as
'(field__)' to avoid precedence issues
#105: FILE: include/linux/dma-buf-map.h:319:
+#define dma_buf_map_read_field(map__, type__, field__) ({
\
+ type__ *t__;
\
+ typeof(t__->field__) val__;
\
+ dma_buf_map_memcpy_from_offset(__, map__, offsetof(type__,
field__),\
+ sizeof(t__->field__));
\
+ val__;
\
+})
-:126: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'type__' may be better as
'(type__)' to avoid precedence issues
#126: FILE: include/linux/dma-buf-map.h:340:
+#define dma_buf_map_write_field(map__, type__, field__, val__) ({
\
+ type__ *t__;
\
+ typeof(t__->field__) val = val__;
\
+ dma_buf_map_memcpy_to_offset(map__, offsetof(type__, field__),
\
+, sizeof(t__->field__));
\
+})
-:126: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'field__' - possible
side-effects?
#126: FILE: include/linux/dma-buf-map.h:340:
+#define dma_buf_map_write_field(map__, type__, field__, val__) ({
\
+ type__ *t__;
\
+ typeof(t__->field__) val = val__;
\
+ dma_buf_map_memcpy_to_offset(map__, offsetof(type__, field__),
\
+, sizeof(t__->field__));
\
+})
-:126: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'field__' may be better as
'(field__)' to avoid precedence issues
#126: FILE: include/linux/dma-buf-map.h:340:
+#define dma_buf_map_write_field(map__, type__, field__, val__) ({
\
+ type__ *t__;
\
+ typeof(t__->field__) val = val__;
\
+ dma_buf_map_memcpy_to_offset(map__, offsetof(type__, field__),
\
+, sizeof(t__->field__));
\
+})
total: 0 errors, 0 warnings, 6 checks, 97 lines checked
3e1d98022b1e dma-buf-map: Add helper to initialize second map
-:55: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
#55: FILE: include/linux/dma-buf-map.h:157:
+#define DMA_BUF_MAP_INIT_OFFSET(map_, offset_) (struct dma_buf_map)\
+ { \
+ .vaddr = (map_)->vaddr + (offset_), \
+ .is_iomem = (map_)->is_iomem, \
+ }
-:55: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'map_' - possible
side-effects?
#55: FILE: include/linux/dma-buf-map.h:157:
+#define DMA_BUF_MAP_INIT_OFFSET(map_, offset_) (struct dma_buf_map)\
+ {
[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor ADS access to use dma_buf_map
== Series Details == Series: drm/i915/guc: Refactor ADS access to use dma_buf_map URL : https://patchwork.freedesktop.org/series/99378/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately.
Re: [Intel-gfx] [PATCH 4/8] drm/i915: Use preempt_disable/enable_rt() where recommended
On Tue, Dec 14, 2021 at 3:03 PM Sebastian Andrzej Siewior <
bige...@linutronix.de> wrote:
> From: Mike Galbraith
>
> Mario Kleiner suggest in commit
> ad3543ede630f ("drm/intel: Push get_scanout_position() timestamping into
> kms driver.")
>
> a spots where preemption should be disabled on PREEMPT_RT. The
> difference is that on PREEMPT_RT the intel_uncore::lock disables neither
> preemption nor interrupts and so region remains preemptible.
>
>
Hi, first thank you for implementing these preempt disables according to
the markers i left long ago. And sorry for the rather late reply.
I had a look at the code, as of Linux 5.16, and did also a little test run
(of a standard kernel, not with PREEMPT_RT, only
CONFIG_PREEMPT_VOLUNTARY=y) on my Intel Kabylake GT2, so some thoughts:
The area covers only register reads and writes. The part that worries me
> is:
> - __intel_get_crtc_scanline() the worst case is 100us if no match is
> found.
>
This one can be a problem indeed on (maybe all?) modern Intel gpu's since
Haswell, ie. the last ~10 years. I was able to reproduce it on my Kabylake
Intel gpu.
Most of the time that for-loop with up to 100 repetitions (~ 100
udelay(1) + one mmio register read) (cfe.
https://elixir.bootlin.com/linux/v5.17-rc1/source/drivers/gpu/drm/i915/i915_irq.c#L856)
will not execute, because most of the time that function gets called from
the vblank irq handler and then that trigger condition (if
(HAS_DDI(dev_priv) && !position)) is not true. However, it also gets called
as part of power-saving on behalf of userspace context, whenever the
desktop graphics goes idle for two video refresh cycles. If the desktop
shows graphics activity again, and vblank interrupts need to get reenabled,
the probability of hitting that case is then ~1-4% depending on video mode.
How many loops it runs also varies.
On my little Intel(R) Core(TM) i5-8250U CPU machine with a mostly idle
desktop, I observed about one hit every couple of seconds of regular use,
and each hit took between 125 usecs and almost 250 usecs. I guess udelay(1)
can take a bit longer than 1 usec?
So that's too much for preempt-rt. What one could do is the following:
1. In the for-loop in __intel_get_crtc_scanline(), add a preempt_enable()
before the udelay(1); and a preempt_disable() again after it. Or
potentially around the whole for-loop if the overhead of
preempt_en/disable() is significant?
2. In intel_get_crtc_scanline() also wrap the call to
__intel_get_crtc_scanline() into a preempt_disable() and preempt_enable(),
so we can be sure that __intel_get_crtc_scanline() always gets called with
preemption disabled.
Why should this work ok'ish? The point of the original preempt disable
inside i915_get_crtc_scanoutpos
is that those two *stime = ktime_get() and *etime = ktime_get() clock
queries happen as close to the scanout position query as possible to get a
small confidence interval for when exactly the scanoutpos was
read/determined from the display hardware. error = (etime - stime) is the
error margin. If that margin becomes greater than 20 usecs, then the
higher-level code will consider the measurement invalid and repeat the
whole procedure up to 3 times before giving up.
Normally, in my experience with different graphics chips, one would observe
error < 3 usecs, so the measurement almost always succeeds at first try,
only very rarely takes two attempts. The preempt disable is meant to make
sure that this stays the case on a PREEMPT_RT kernel.
The problem here are the relatively rare cases where we hit that up to 100
iterations for-loop. Here even on a regular kernel, due to hardware quirks,
we already exceed the 20 usecs tolerance by a huge amount of more than 100
usecs, leading to a retry of the measurement. And my tests showed that
often the two succeeding retries also fail, because of hardware quirks can
apparently create a blackout situation approaching 1 msec, so we lose
anyway, regardless if we get preempted on a RT kernel or not. That's why
enabling preemption on RT again during that for-loop should not make the
situation worse and at least keep RT as real-time as intended.
In practice I would also expect that this failure case is the one least
likely to impair userspace applications greatly in practice. The cases that
mostly matter are the ones executed during vblank hardware irq, where the
for-loop never executes and error margin and preempt off time is only about
1 usec. My own software which depends on very precise timestamps from the
mechanism never reported >> 20 usecs errors during startup tests or runtime
tests.
> - intel_crtc_scanlines_since_frame_timestamp() not sure how long this
> may take in the worst case.
>
>
intel_crtc_scanlines_since_frame_timestamp() should be harmless. That
do-while loop just tries to make sure that two register reads that should
happen within the same video refresh cycle are happening in the same
[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Refactor ADS access to use dma_buf_map
== Series Details ==
Series: drm/i915/guc: Refactor ADS access to use dma_buf_map
URL : https://patchwork.freedesktop.org/series/99378/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11147 -> Patchwork_22116
Summary
---
**SUCCESS**
No regressions found.
External URL:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/index.html
Participating hosts (48 -> 31)
--
Missing(17): fi-kbl-soraka fi-bxt-dsi fi-bdw-5557u fi-bsw-n3050
fi-hsw-4200u fi-glk-dsi fi-icl-u2 fi-bsw-cyan fi-apl-guc fi-snb-2520m
fi-ctg-p8600 fi-kbl-x1275 fi-kbl-8809g fi-elk-e7500 fi-bsw-kefka fi-bsw-nick
fi-bdw-samus
Known issues
Here are the changes found in Patchwork_22116 that come from known issues:
### IGT changes ###
Issues hit
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600:NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/fi-snb-2600/igt@amdgpu/amd_cs_...@sync-fork-compute0.html
* igt@gem_exec_suspend@basic-s3@smem:
- fi-skl-6600u: NOTRUN -> [INCOMPLETE][2] ([i915#4547])
[2]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/fi-skl-6600u/igt@gem_exec_suspend@basic...@smem.html
* igt@runner@aborted:
- fi-pnv-d510:NOTRUN -> [FAIL][3] ([i915#2403] / [i915#4312])
[3]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/fi-pnv-d510/igt@run...@aborted.html
- fi-skl-6600u: NOTRUN -> [FAIL][4] ([i915#4312])
[4]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/fi-skl-6600u/igt@run...@aborted.html
Possible fixes
* igt@i915_selftest@live@gt_pm:
- {fi-jsl-1}: [DMESG-FAIL][5] ([i915#1886]) -> [PASS][6]
[5]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
[6]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/fi-jsl-1/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-6: [DMESG-FAIL][7] ([i915#4494] / [i915#4957]) ->
[PASS][8]
[7]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
[8]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/bat-dg1-6/igt@i915_selftest@l...@hangcheck.html
- fi-snb-2600:[INCOMPLETE][9] ([i915#3921]) -> [PASS][10]
[9]:
https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11147/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
[10]:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/fi-snb-2600/igt@i915_selftest@l...@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2403]: https://gitlab.freedesktop.org/drm/intel/issues/2403
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3194]: https://gitlab.freedesktop.org/drm/intel/issues/3194
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494
[i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547
[i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
Build changes
-
* Linux: CI_DRM_11147 -> Patchwork_22116
CI-20190529: 20190529
CI_DRM_11147: ad57bf1ff13e1c4462f947398fbfb861f1b2e345 @
git://anongit.freedesktop.org/gfx-ci/linux
IGT_6335: 2b30115edd692b60d16cb10375730a87f51f0e37 @
https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22116: 2788e054f9ce2eff704b9c331c3881bf035ee68f @
git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/Patchwork_22116/build_32bit.log
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o
In file included from ./include/drm/drm_mm.h:51,
from ./drivers/gpu/drm/i915/i915_vma.h:31,
from ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h:13,
from ./drivers/gpu/drm/i915/gt/uc/intel_guc.h:20,
from ./drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
from ./drivers/gpu/drm/i915/gt/intel_gt_types.h:18,
from ./drivers/gpu/drm/i915/gt/intel_gt.h:10,
from drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:9:
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c: In function
‘guc_mmio_reg_state_create’:
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:369:38: error: format ‘%lu’ expects
[Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915/guc: Refactor ADS access to use dma_buf_map
== Series Details ==
Series: drm/i915/guc: Refactor ADS access to use dma_buf_map
URL : https://patchwork.freedesktop.org/series/99378/
State : warning
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o
In file included from ./include/drm/drm_mm.h:51,
from ./drivers/gpu/drm/i915/i915_vma.h:31,
from ./drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h:13,
from ./drivers/gpu/drm/i915/gt/uc/intel_guc.h:20,
from ./drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
from ./drivers/gpu/drm/i915/gt/intel_gt_types.h:18,
from ./drivers/gpu/drm/i915/gt/intel_gt.h:10,
from drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:9:
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c: In function
‘guc_mmio_reg_state_create’:
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c:369:38: error: format ‘%lu’ expects
argument of type ‘long unsigned int’, but argument 4 has type ‘u32’ {aka
‘unsigned int’} [-Werror=format=]
drm_dbg(_to_gt(guc)->i915->drm, "Used %lu KB for temporary ADS regset\n",
^~~~
(temp_set.storage_max * sizeof(struct guc_mmio_reg)) >> 10);
~~
./include/drm/drm_print.h:461:56: note: in definition of macro ‘drm_dbg’
drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRIVER, fmt, ##__VA_ARGS__)
^~~
cc1: all warnings being treated as errors
scripts/Makefile.build:288: recipe for target
'drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o' failed
make[4]: *** [drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o] Error 1
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:550: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1831: recipe for target 'drivers' failed
make: *** [drivers] Error 2
== Logs ==
For more details see:
https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22116/build_32bit.log
[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v10,1/5] drm: improve drm_buddy_alloc function
== Series Details ==
Series: series starting with [v10,1/5] drm: improve drm_buddy_alloc function
URL : https://patchwork.freedesktop.org/series/99382/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c9a375384fb3 drm: improve drm_buddy_alloc function
-:383: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON &
recovery code rather than BUG() or BUG_ON()
#383: FILE: drivers/gpu/drm/drm_buddy.c:585:
+ BUG_ON(order > mm->max_order);
-:384: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON &
recovery code rather than BUG() or BUG_ON()
#384: FILE: drivers/gpu/drm/drm_buddy.c:586:
+ BUG_ON(order < min_order);
-:510: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#510: FILE: drivers/gpu/drm/i915/i915_ttm_buddy_manager.c:88:
+ err = drm_buddy_alloc_blocks(mm, (u64)place->fpfn << PAGE_SHIFT,
+ (u64)lpfn << PAGE_SHIFT,
total: 0 errors, 2 warnings, 1 checks, 506 lines checked
d007f812a25a drm: implement top-down allocation method
d01faa9bdacb drm: implement a method to free unused pages
69c19364e1f2 drm/amdgpu: move vram inline functions into a header
-:12: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does
MAINTAINERS need updating?
#12:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 51 lines checked
9ce76c7fdbd5 drm/amdgpu: add drm buddy support to amdgpu
-:57: CHECK:PREFER_KERNEL_TYPES: Prefer kernel type 'u32' over 'uint32_t'
#57: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_res_cursor.h:41:
+ uint32_tmem_type;
-:338: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#338: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:325:
+ if (rsv->start <= start &&
+ (start < (rsv->start + rsv->size))) {
-:348: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#348: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:333:
+ if (rsv->start <= start &&
+ (start < (rsv->start + rsv->size))) {
-:414: CHECK:BRACES: Unbalanced braces around else statement
#414: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:387:
+ else {
-:447: WARNING:AVOID_BUG: Avoid crashing the kernel - try using WARN_ON &
recovery code rather than BUG() or BUG_ON()
#447: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:416:
+ BUG_ON(min_page_size < mm->chunk_size);
-:490: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#490: FILE: drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c:440:
+ r = drm_buddy_alloc_blocks(mm, (u64)place->fpfn << PAGE_SHIFT,
+ (u64)lpfn << PAGE_SHIFT,
total: 0 errors, 1 warnings, 5 checks, 594 lines checked
[Intel-gfx] ✗ Fi.CI.IGT: failure for lib/string_helpers: Add a few string helpers (rev2)
== Series Details == Series: lib/string_helpers: Add a few string helpers (rev2) URL : https://patchwork.freedesktop.org/series/99030/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11145_full -> Patchwork_22110_full Summary --- **FAILURE** Serious unknown changes coming with Patchwork_22110_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22110_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (10 -> 10) -- No changes in participating hosts Possible new issues --- Here are the unknown changes that may have been introduced in Patchwork_22110_full: ### IGT changes ### Possible regressions * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt: - shard-skl: [PASS][1] -> [DMESG-WARN][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-skl5/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-shrfb-draw-blt.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-skl10/igt@kms_frontbuffer_track...@psr-1p-primscrn-pri-shrfb-draw-blt.html * igt@kms_vblank@pipe-c-query-busy-hang: - shard-tglb: [PASS][3] -> [INCOMPLETE][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-tglb3/igt@kms_vbl...@pipe-c-query-busy-hang.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-tglb7/igt@kms_vbl...@pipe-c-query-busy-hang.html * igt@perf_pmu@busy-idle@rcs0: - shard-skl: [PASS][5] -> [FAIL][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-skl4/igt@perf_pmu@busy-i...@rcs0.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-skl1/igt@perf_pmu@busy-i...@rcs0.html Known issues Here are the changes found in Patchwork_22110_full that come from known issues: ### IGT changes ### Issues hit * igt@gem_ctx_persistence@legacy-engines-queued: - shard-snb: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#1099]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-snb7/igt@gem_ctx_persiste...@legacy-engines-queued.html * igt@gem_exec_balancer@parallel-keep-submit-fence: - shard-iclb: [PASS][8] -> [SKIP][9] ([i915#4525]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-iclb2/igt@gem_exec_balan...@parallel-keep-submit-fence.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-iclb7/igt@gem_exec_balan...@parallel-keep-submit-fence.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [PASS][10] -> [FAIL][11] ([i915#2842]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-apl2/igt@gem_exec_fair@basic-none-s...@rcs0.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-apl1/igt@gem_exec_fair@basic-none-s...@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: NOTRUN -> [FAIL][12] ([i915#2842]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-glk1/igt@gem_exec_fair@basic-n...@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-kbl: [PASS][13] -> [FAIL][14] ([i915#2842]) +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-kbl3/igt@gem_exec_fair@basic-n...@vcs1.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-kbl6/igt@gem_exec_fair@basic-n...@vcs1.html * igt@gem_exec_fair@basic-pace-share@rcs0: - shard-glk: [PASS][15] -> [FAIL][16] ([i915#2842]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11145/shard-glk4/igt@gem_exec_fair@basic-pace-sh...@rcs0.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-glk7/igt@gem_exec_fair@basic-pace-sh...@rcs0.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-iclb: NOTRUN -> [FAIL][17] ([i915#2842]) +1 similar issue [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-iclb4/igt@gem_exec_fair@basic-pace-s...@rcs0.html - shard-tglb: NOTRUN -> [FAIL][18] ([i915#2842]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-tglb2/igt@gem_exec_fair@basic-pace-s...@rcs0.html * igt@gem_lmem_swapping@basic: - shard-skl: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-skl4/igt@gem_lmem_swapp...@basic.html * igt@gem_lmem_swapping@parallel-random: - shard-apl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22110/shard-apl3/igt@gem_lmem_swapp...@parallel-random.html - shard-kbl:
Re: [Intel-gfx] [PATCH 1/3] drm/i915: Fix up pixel_rate vs. clock confusion in wm calculations
On Thu, 09 Dec 2021, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use pixel_rate rather than crtc_clock in the watermark calculations.
> These are actually identical on gmch platforms for now since
> we don't adjust the pixel rate based on pfit downscaling. But
> pixel_rate is the thing we are actually interested here so use
> the proper name for it.
>
> Signed-off-by: Ville Syrjälä
On the series,
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_pm.c | 52 ++---
> 1 file changed, 22 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 434b1f8b7fe3..b5d5b625a321 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -915,15 +915,13 @@ static void pnv_update_wm(struct drm_i915_private
> *dev_priv)
>
> crtc = single_enabled_crtc(dev_priv);
> if (crtc) {
> - const struct drm_display_mode *pipe_mode =
> - >config->hw.pipe_mode;
> const struct drm_framebuffer *fb =
> crtc->base.primary->state->fb;
> + int pixel_rate = crtc->config->pixel_rate;
> int cpp = fb->format->cpp[0];
> - int clock = pipe_mode->crtc_clock;
>
> /* Display SR */
> - wm = intel_calculate_wm(clock, _display_wm,
> + wm = intel_calculate_wm(pixel_rate, _display_wm,
> pnv_display_wm.fifo_size,
> cpp, latency->display_sr);
> reg = intel_uncore_read(_priv->uncore, DSPFW1);
> @@ -933,7 +931,7 @@ static void pnv_update_wm(struct drm_i915_private
> *dev_priv)
> drm_dbg_kms(_priv->drm, "DSPFW1 register is %x\n", reg);
>
> /* cursor SR */
> - wm = intel_calculate_wm(clock, _cursor_wm,
> + wm = intel_calculate_wm(pixel_rate, _cursor_wm,
> pnv_display_wm.fifo_size,
> 4, latency->cursor_sr);
> reg = intel_uncore_read(_priv->uncore, DSPFW3);
> @@ -942,7 +940,7 @@ static void pnv_update_wm(struct drm_i915_private
> *dev_priv)
> intel_uncore_write(_priv->uncore, DSPFW3, reg);
>
> /* Display HPLL off SR */
> - wm = intel_calculate_wm(clock, _display_hplloff_wm,
> + wm = intel_calculate_wm(pixel_rate, _display_hplloff_wm,
> pnv_display_hplloff_wm.fifo_size,
> cpp, latency->display_hpll_disable);
> reg = intel_uncore_read(_priv->uncore, DSPFW3);
> @@ -951,7 +949,7 @@ static void pnv_update_wm(struct drm_i915_private
> *dev_priv)
> intel_uncore_write(_priv->uncore, DSPFW3, reg);
>
> /* cursor HPLL off SR */
> - wm = intel_calculate_wm(clock, _cursor_hplloff_wm,
> + wm = intel_calculate_wm(pixel_rate, _cursor_hplloff_wm,
> pnv_display_hplloff_wm.fifo_size,
> 4, latency->cursor_hpll_disable);
> reg = intel_uncore_read(_priv->uncore, DSPFW3);
> @@ -1154,7 +1152,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state
> *crtc_state,
> const struct drm_display_mode *pipe_mode =
> _state->hw.pipe_mode;
> unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
> - unsigned int clock, htotal, cpp, width, wm;
> + unsigned int pixel_rate, htotal, cpp, width, wm;
>
> if (latency == 0)
> return USHRT_MAX;
> @@ -1175,21 +1173,21 @@ static u16 g4x_compute_wm(const struct
> intel_crtc_state *crtc_state,
> level != G4X_WM_LEVEL_NORMAL)
> cpp = max(cpp, 4u);
>
> - clock = pipe_mode->crtc_clock;
> + pixel_rate = crtc_state->pixel_rate;
> htotal = pipe_mode->crtc_htotal;
>
> width = drm_rect_width(_state->uapi.dst);
>
> if (plane->id == PLANE_CURSOR) {
> - wm = intel_wm_method2(clock, htotal, width, cpp, latency);
> + wm = intel_wm_method2(pixel_rate, htotal, width, cpp, latency);
> } else if (plane->id == PLANE_PRIMARY &&
> level == G4X_WM_LEVEL_NORMAL) {
> - wm = intel_wm_method1(clock, cpp, latency);
> + wm = intel_wm_method1(pixel_rate, cpp, latency);
> } else {
> unsigned int small, large;
>
> - small = intel_wm_method1(clock, cpp, latency);
> - large = intel_wm_method2(clock, htotal, width, cpp, latency);
> + small = intel_wm_method1(pixel_rate, cpp, latency);
> + large = intel_wm_method2(pixel_rate, htotal, width, cpp,
> latency);
>
> wm = min(small, large);
> }
> @@ -1674,7 +1672,7 @@ static u16 vlv_compute_wm_level(const struct
> intel_crtc_state *crtc_state,
>
[Intel-gfx] [PATCH 00/20] Initial support for small BAR recovery
Starting from DG2 we will have resizable BAR support for device local-memory, but in some cases the final BAR size might still be smaller than the total local-memory size. In such cases only part of local-memory will be CPU accessible, while the remainder is only accessible via the GPU. This series adds the basic enablers needed to ensure that the entire local-memory range is usable. Patches 1-3 are taken directly from Arun' in-progress series[1], which reworks part of the allocator, and for example, allows us to allocate memory within a sub-range, and is needed when allocating mappable memory. These patches are only included here for the benefit of CI testing. [1] https://patchwork.freedesktop.org/series/98979/ -- 2.34.1
Re: [Intel-gfx] [PATCH v2 02/11] drm/i915: Fix trailing semicolon
On Wed, 26 Jan 2022, Lucas De Marchi wrote: > Remove the trailing semicolon, as correctly warned by checkpatch: > > -:1189: WARNING:TRAILING_SEMICOLON: macros should not use a trailing > semicolon > #1189: FILE: drivers/gpu/drm/i915/intel_device_info.c:119: > +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, > yesno(info->display.name)); > > Signed-off-by: Lucas De Marchi Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/intel_device_info.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_device_info.c > b/drivers/gpu/drm/i915/intel_device_info.c > index 93b251b25aba..94da5aa37391 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.c > +++ b/drivers/gpu/drm/i915/intel_device_info.c > @@ -114,7 +114,7 @@ void intel_device_info_print_static(const struct > intel_device_info *info, > DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); > #undef PRINT_FLAG > > -#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, > yesno(info->display.name)); > +#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, > yesno(info->display.name)) > DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); > #undef PRINT_FLAG > } -- Jani Nikula, Intel Open Source Graphics Center
Re: [Intel-gfx] [PATCH v2 09/11] drm: Convert open-coded yes/no strings to yesno()
On Wed, 26 Jan 2022, Lucas De Marchi wrote:
> linux/string_helpers.h provides a helper to return "yes"/"no" strings.
> Replace the open coded versions with str_yes_no(). The places were
> identified with the following semantic patch:
>
> @@
> expression b;
> @@
>
> - b ? "yes" : "no"
> + str_yes_no(b)
>
> Then the includes were added, so we include-what-we-use, and parenthesis
> adjusted in drivers/gpu/drm/v3d/v3d_debugfs.c. After the conversion we
> still see the same binary sizes:
>
>textdata bss dec hex filename
> 511493295 212 54656d580 virtio/virtio-gpu.ko.old
> 511493295 212 54656d580 virtio/virtio-gpu.ko
> 1441491 60340 800 1502631 16eda7 radeon/radeon.ko.old
> 1441491 60340 800 1502631 16eda7 radeon/radeon.ko
> 6125369 328538 34000 6487907 62ff63 amd/amdgpu/amdgpu.ko.old
> 6125369 328538 34000 6487907 62ff63 amd/amdgpu/amdgpu.ko
> 411986 104906176 428652 68a6c drm.ko.old
> 411986 104906176 428652 68a6c drm.ko
> 981291636 264 100029 186bd dp/drm_dp_helper.ko.old
> 981291636 264 100029 186bd dp/drm_dp_helper.ko
> 1973432 1096402352 2085424 1fd230 nouveau/nouveau.ko.old
> 1973432 1096402352 2085424 1fd230 nouveau/nouveau.ko
>
> Signed-off-by: Lucas De Marchi
Reviewed-by: Jani Nikula
> ---
> drivers/gpu/drm/amd/amdgpu/atom.c | 4 +++-
> drivers/gpu/drm/dp/drm_dp.c | 3 ++-
> drivers/gpu/drm/drm_client_modeset.c | 3 ++-
> drivers/gpu/drm/drm_gem.c | 3 ++-
> drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.c | 5 -
> drivers/gpu/drm/radeon/atom.c | 3 ++-
> drivers/gpu/drm/v3d/v3d_debugfs.c | 11 ++-
> drivers/gpu/drm/virtio/virtgpu_debugfs.c | 4 +++-
> 8 files changed, 24 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c
> b/drivers/gpu/drm/amd/amdgpu/atom.c
> index 6fa2229b7229..1c5d9388ad0b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/atom.c
> +++ b/drivers/gpu/drm/amd/amdgpu/atom.c
> @@ -25,6 +25,8 @@
> #include
> #include
> #include
> +#include
> +
> #include
>
> #include
> @@ -740,7 +742,7 @@ static void atom_op_jump(atom_exec_context *ctx, int
> *ptr, int arg)
> break;
> }
> if (arg != ATOM_COND_ALWAYS)
> - SDEBUG(" taken: %s\n", execute ? "yes" : "no");
> + SDEBUG(" taken: %s\n", str_yes_no(execute));
> SDEBUG(" target: 0x%04X\n", target);
> if (execute) {
> if (ctx->last_jump == (ctx->start + target)) {
> diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c
> index 6d43325acca5..c43577c8ac4d 100644
> --- a/drivers/gpu/drm/dp/drm_dp.c
> +++ b/drivers/gpu/drm/dp/drm_dp.c
> @@ -28,6 +28,7 @@
> #include
> #include
> #include
> +#include
>
> #include
> #include
> @@ -1239,7 +1240,7 @@ void drm_dp_downstream_debug(struct seq_file *m,
> bool branch_device = drm_dp_is_branch(dpcd);
>
> seq_printf(m, "\tDP branch device present: %s\n",
> -branch_device ? "yes" : "no");
> +str_yes_no(branch_device));
>
> if (!branch_device)
> return;
> diff --git a/drivers/gpu/drm/drm_client_modeset.c
> b/drivers/gpu/drm/drm_client_modeset.c
> index ced09c7c06f9..e6346a67cd98 100644
> --- a/drivers/gpu/drm/drm_client_modeset.c
> +++ b/drivers/gpu/drm/drm_client_modeset.c
> @@ -11,6 +11,7 @@
> #include
> #include
> #include
> +#include
>
> #include
> #include
> @@ -241,7 +242,7 @@ static void drm_client_connectors_enabled(struct
> drm_connector **connectors,
> connector = connectors[i];
> enabled[i] = drm_connector_enabled(connector, true);
> DRM_DEBUG_KMS("connector %d enabled? %s\n", connector->base.id,
> - connector->display_info.non_desktop ? "non
> desktop" : enabled[i] ? "yes" : "no");
> + connector->display_info.non_desktop ? "non
> desktop" : str_yes_no(enabled[i]));
>
> any_enabled |= enabled[i];
> }
> diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c
> index 21631c22b374..3c888db59ea4 100644
> --- a/drivers/gpu/drm/drm_gem.c
> +++ b/drivers/gpu/drm/drm_gem.c
> @@ -37,6 +37,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
>
> @@ -1145,7 +1146,7 @@ void drm_gem_print_info(struct drm_printer *p, unsigned
> int indent,
> drm_vma_node_start(>vma_node));
> drm_printf_indent(p, indent, "size=%zu\n", obj->size);
> drm_printf_indent(p, indent, "imported=%s\n",
> - obj->import_attach ? "yes" : "no");
> + str_yes_no(obj->import_attach));
>
> if (obj->funcs->print_info)
> obj->funcs->print_info(p, indent, obj);
> diff --git
[Intel-gfx] [PATCH 06/20] drm/i915: add I915_BO_ALLOC_TOPDOWN
If the user doesn't require CPU access for the buffer, then
ALLOC_TOPDOWN should be used, in order to prioritise allocating in the
non-mappable portion of LMEM.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 15 +++
drivers/gpu/drm/i915/gem/i915_gem_pages.c| 3 +++
drivers/gpu/drm/i915/gem/i915_gem_region.c | 5 +
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 13 ++---
drivers/gpu/drm/i915/gt/intel_gt.c | 4 +++-
drivers/gpu/drm/i915/i915_vma.c | 3 +++
drivers/gpu/drm/i915/intel_region_ttm.c | 11 ---
drivers/gpu/drm/i915/selftests/mock_region.c | 7 +--
8 files changed, 44 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
index 71e778ecaeb8..29285aaf0477 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_object_types.h
@@ -319,15 +319,22 @@ struct drm_i915_gem_object {
#define I915_BO_ALLOC_PM_VOLATILE BIT(4)
/* Object needs to be restored early using memcpy during resume */
#define I915_BO_ALLOC_PM_EARLYBIT(5)
+/*
+ * Object is likely never accessed by the CPU. This will prioritise the BO to
be
+ * allocated in the non-mappable portion of lmem. This is merely a hint, and if
+ * dealing with userspace objects the CPU fault handler is free to ignore this.
+ */
+#define I915_BO_ALLOC_TOPDOWNBIT(6)
#define I915_BO_ALLOC_FLAGS (I915_BO_ALLOC_CONTIGUOUS | \
I915_BO_ALLOC_VOLATILE | \
I915_BO_ALLOC_CPU_CLEAR | \
I915_BO_ALLOC_USER | \
I915_BO_ALLOC_PM_VOLATILE | \
-I915_BO_ALLOC_PM_EARLY)
-#define I915_BO_READONLY BIT(6)
-#define I915_TILING_QUIRK_BIT 7 /* unknown swizzling; do not release! */
-#define I915_BO_PROTECTED BIT(8)
+I915_BO_ALLOC_PM_EARLY | \
+I915_BO_ALLOC_TOPDOWN)
+#define I915_BO_READONLY BIT(7)
+#define I915_TILING_QUIRK_BIT 8 /* unknown swizzling; do not release! */
+#define I915_BO_PROTECTED BIT(9)
/**
* @mem_flags - Mutable placement-related flags
*
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
index 7d2211fbe548..a95b4d72619f 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
@@ -346,6 +346,9 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj,
!i915_gem_object_has_iomem(obj))
return ERR_PTR(-ENXIO);
+ if (WARN_ON_ONCE(obj->flags & I915_BO_ALLOC_TOPDOWN))
+ return ERR_PTR(-EINVAL);
+
assert_object_held(obj);
pinned = !(type & I915_MAP_OVERRIDE);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_region.c
b/drivers/gpu/drm/i915/gem/i915_gem_region.c
index a4350227e9ae..f91e5a9c759d 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_region.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_region.c
@@ -45,6 +45,11 @@ i915_gem_object_create_region(struct intel_memory_region
*mem,
GEM_BUG_ON(flags & ~I915_BO_ALLOC_FLAGS);
+ if (WARN_ON_ONCE(flags & I915_BO_ALLOC_TOPDOWN &&
+(flags & I915_BO_ALLOC_CPU_CLEAR ||
+ flags & I915_BO_ALLOC_PM_EARLY)))
+ return ERR_PTR(-EINVAL);
+
if (!mem)
return ERR_PTR(-ENODEV);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index d9a04c7d41b1..e60b677ecd54 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -127,10 +127,14 @@ i915_ttm_place_from_region(const struct
intel_memory_region *mr,
place->mem_type = intel_region_to_ttm_type(mr);
if (flags & I915_BO_ALLOC_CONTIGUOUS)
- place->flags = TTM_PL_FLAG_CONTIGUOUS;
+ place->flags |= TTM_PL_FLAG_CONTIGUOUS;
if (mr->io_size && mr->io_size < mr->total) {
- place->fpfn = 0;
- place->lpfn = mr->io_size >> PAGE_SHIFT;
+ if (flags & I915_BO_ALLOC_TOPDOWN) {
+ place->flags |= TTM_PL_FLAG_TOPDOWN;
+ } else {
+ place->fpfn = 0;
+ place->lpfn = mr->io_size >> PAGE_SHIFT;
+ }
}
}
@@ -890,6 +894,9 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
if (!obj)
return VM_FAULT_SIGBUS;
+ if (obj->flags & I915_BO_ALLOC_TOPDOWN)
+ return -EINVAL;
+
/* Sanity check that we allow writing into this object */
if (unlikely(i915_gem_object_is_readonly(obj) &&
area->vm_flags & VM_WRITE))
diff --git
[Intel-gfx] [PATCH 07/20] drm/i915/buddy: track available visible size
Track the total amount of available visible memory, and also track
per-resource the amount of used visible memory. For now this is useful
for our debug output, and deciding if it is even worth calling into the
buddy allocator. In the future tracking the per-resource visible usage
will be useful for when deciding if we should attempt to evict certain
buffers.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 55 ++-
drivers/gpu/drm/i915/i915_ttm_buddy_manager.h | 8 ++-
drivers/gpu/drm/i915/intel_region_ttm.c | 1 +
3 files changed, 62 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index 53eb100688a6..6e5842155898 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -19,6 +19,8 @@ struct i915_ttm_buddy_manager {
struct drm_buddy mm;
struct list_head reserved;
struct mutex lock;
+ unsigned long visible_size;
+ unsigned long visible_avail;
u64 default_page_size;
};
@@ -87,6 +89,13 @@ static int i915_ttm_buddy_man_alloc(struct
ttm_resource_manager *man,
n_pages = size >> ilog2(mm->chunk_size);
mutex_lock(>lock);
+ if (place->lpfn && place->lpfn <= bman->visible_size &&
+ n_pages > bman->visible_avail) {
+ mutex_unlock(>lock);
+ err = -ENOSPC;
+ goto err_free_res;
+ }
+
err = drm_buddy_alloc_blocks(mm, (u64)place->fpfn << PAGE_SHIFT,
(u64)lpfn << PAGE_SHIFT,
(u64)n_pages << PAGE_SHIFT,
@@ -107,6 +116,30 @@ static int i915_ttm_buddy_man_alloc(struct
ttm_resource_manager *man,
mutex_unlock(>lock);
}
+ if (place->lpfn && place->lpfn <= bman->visible_size) {
+ bman_res->used_visible_size = bman_res->base.num_pages;
+ } else {
+ struct drm_buddy_block *block;
+
+ list_for_each_entry(block, _res->blocks, link) {
+ unsigned long start =
+ drm_buddy_block_offset(block) >> PAGE_SHIFT;
+ unsigned long end = start +
+ (drm_buddy_block_size(mm, block) >> PAGE_SHIFT);
+
+ if (start < bman->visible_size) {
+ bman_res->used_visible_size +=
+ min(end, bman->visible_size) - start;
+ }
+ }
+ }
+
+ if (bman_res->used_visible_size) {
+ mutex_lock(>lock);
+ bman->visible_avail -= bman_res->used_visible_size;
+ mutex_unlock(>lock);
+ }
+
*res = _res->base;
return 0;
@@ -127,6 +160,7 @@ static void i915_ttm_buddy_man_free(struct
ttm_resource_manager *man,
mutex_lock(>lock);
drm_buddy_free_list(>mm, _res->blocks);
+ bman->visible_avail += bman_res->used_visible_size;
mutex_unlock(>lock);
kfree(bman_res);
@@ -141,6 +175,10 @@ static void i915_ttm_buddy_man_debug(struct
ttm_resource_manager *man,
mutex_lock(>lock);
drm_printf(printer, "default_page_size: %lluKiB\n",
bman->default_page_size >> 10);
+ drm_printf(printer, "visible_avail: %luMiB\n",
+ bman->visible_avail << PAGE_SHIFT >> 20);
+ drm_printf(printer, "visible_size: %luMiB\n",
+ bman->visible_size << PAGE_SHIFT >> 20);
drm_buddy_print(>mm, printer);
@@ -162,6 +200,7 @@ static const struct ttm_resource_manager_func
i915_ttm_buddy_manager_func = {
* @type: Memory type we want to manage
* @use_tt: Set use_tt for the manager
* @size: The size in bytes to manage
+ * @visible_size: The CPU visible size in bytes to manage
* @default_page_size: The default minimum page size in bytes for allocations,
* this must be at least as large as @chunk_size, and can be overridden by
* setting the BO page_alignment, to be larger or smaller as needed.
@@ -185,7 +224,7 @@ static const struct ttm_resource_manager_func
i915_ttm_buddy_manager_func = {
*/
int i915_ttm_buddy_man_init(struct ttm_device *bdev,
unsigned int type, bool use_tt,
- u64 size, u64 default_page_size,
+ u64 size, u64 visible_size, u64 default_page_size,
u64 chunk_size)
{
struct ttm_resource_manager *man;
@@ -204,6 +243,8 @@ int i915_ttm_buddy_man_init(struct ttm_device *bdev,
INIT_LIST_HEAD(>reserved);
GEM_BUG_ON(default_page_size < chunk_size);
bman->default_page_size = default_page_size;
+ bman->visible_size = visible_size >> PAGE_SHIFT;
+ bman->visible_avail = bman->visible_size;
man = >manager;
[Intel-gfx] [PATCH 02/20] drm: implement top-down allocation method
From: Arunpravin
Implemented a function which walk through the order list,
compares the offset and returns the maximum offset block,
this method is unpredictable in obtaining the high range
address blocks which depends on allocation and deallocation.
for instance, if driver requests address at a low specific
range, allocator traverses from the root block and splits
the larger blocks until it reaches the specific block and
in the process of splitting, lower orders in the freelist
are occupied with low range address blocks and for the
subsequent TOPDOWN memory request we may return the low
range blocks.To overcome this issue, we may go with the
below approach.
The other approach, sorting each order list entries in
ascending order and compares the last entry of each
order list in the freelist and return the max block.
This creates sorting overhead on every drm_buddy_free()
request and split up of larger blocks for a single page
request.
v2:
- Fix alignment issues(Matthew Auld)
- Remove unnecessary list_empty check(Matthew Auld)
- merged the below patch to see the feature in action
- add top-down alloc support to i915 driver
Signed-off-by: Arunpravin
---
drivers/gpu/drm/drm_buddy.c | 36 ---
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 3 ++
include/drm/drm_buddy.h | 1 +
3 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 954e31962c74..6aa5c1ce25bf 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -371,6 +371,26 @@ alloc_range_bias(struct drm_buddy *mm,
return ERR_PTR(err);
}
+static struct drm_buddy_block *
+get_maxblock(struct list_head *head)
+{
+ struct drm_buddy_block *max_block = NULL, *node;
+
+ max_block = list_first_entry_or_null(head,
+struct drm_buddy_block,
+link);
+ if (!max_block)
+ return NULL;
+
+ list_for_each_entry(node, head, link) {
+ if (drm_buddy_block_offset(node) >
+ drm_buddy_block_offset(max_block))
+ max_block = node;
+ }
+
+ return max_block;
+}
+
static struct drm_buddy_block *
alloc_from_freelist(struct drm_buddy *mm,
unsigned int order,
@@ -381,11 +401,17 @@ alloc_from_freelist(struct drm_buddy *mm,
int err;
for (i = order; i <= mm->max_order; ++i) {
- block = list_first_entry_or_null(>free_list[i],
-struct drm_buddy_block,
-link);
- if (block)
- break;
+ if (flags & DRM_BUDDY_TOPDOWN_ALLOCATION) {
+ block = get_maxblock(>free_list[i]);
+ if (block)
+ break;
+ } else {
+ block = list_first_entry_or_null(>free_list[i],
+struct drm_buddy_block,
+link);
+ if (block)
+ break;
+ }
}
if (!block)
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index 1411f4cf1f21..3662434b64bb 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -53,6 +53,9 @@ static int i915_ttm_buddy_man_alloc(struct
ttm_resource_manager *man,
INIT_LIST_HEAD(_res->blocks);
bman_res->mm = mm;
+ if (place->flags & TTM_PL_FLAG_TOPDOWN)
+ bman_res->flags |= DRM_BUDDY_TOPDOWN_ALLOCATION;
+
if (place->fpfn || lpfn != man->size)
bman_res->flags |= DRM_BUDDY_RANGE_ALLOCATION;
diff --git a/include/drm/drm_buddy.h b/include/drm/drm_buddy.h
index 865664b90a8a..424fc443115e 100644
--- a/include/drm/drm_buddy.h
+++ b/include/drm/drm_buddy.h
@@ -28,6 +28,7 @@
})
#define DRM_BUDDY_RANGE_ALLOCATION (1 << 0)
+#define DRM_BUDDY_TOPDOWN_ALLOCATION (1 << 1)
struct drm_buddy_block {
#define DRM_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12)
--
2.34.1
[Intel-gfx] [PATCH 03/20] drm: implement a method to free unused pages
From: Arunpravin
On contiguous allocation, we round up the size
to the *next* power of 2, implement a function
to free the unused pages after the newly allocate block.
v2(Matthew Auld):
- replace function name 'drm_buddy_free_unused_pages' with
drm_buddy_block_trim
- replace input argument name 'actual_size' with 'new_size'
- add more validation checks for input arguments
- add overlaps check to avoid needless searching and splitting
- merged the below patch to see the feature in action
- add free unused pages support to i915 driver
- lock drm_buddy_block_trim() function as it calls mark_free/mark_split
are all globally visible
v3(Matthew Auld):
- remove trim method error handling as we address the failure case
at drm_buddy_block_trim() function
v4:
- in case of trim, at __alloc_range() split_block failure path
marks the block as free and removes it from the original list,
potentially also freeing it, to overcome this problem, we turn
the drm_buddy_block_trim() input node into a temporary node to
prevent recursively freeing itself, but still retain the
un-splitting/freeing of the other nodes(Matthew Auld)
- modify the drm_buddy_block_trim() function return type
v5(Matthew Auld):
- revert drm_buddy_block_trim() function return type changes in v4
- modify drm_buddy_block_trim() passing argument n_pages to original_size
as n_pages has already been rounded up to the next power-of-two and
passing n_pages results noop
v6:
- fix warnings reported by kernel test robot
Signed-off-by: Arunpravin
---
drivers/gpu/drm/drm_buddy.c | 65 +++
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 10 +++
include/drm/drm_buddy.h | 4 ++
3 files changed, 79 insertions(+)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index 6aa5c1ce25bf..c5902a81b8c5 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -546,6 +546,71 @@ static int __drm_buddy_alloc_range(struct drm_buddy *mm,
return __alloc_range(mm, , start, size, blocks);
}
+/**
+ * drm_buddy_block_trim - free unused pages
+ *
+ * @mm: DRM buddy manager
+ * @new_size: original size requested
+ * @blocks: output list head to add allocated blocks
+ *
+ * For contiguous allocation, we round up the size to the nearest
+ * power of two value, drivers consume *actual* size, so remaining
+ * portions are unused and it can be freed.
+ *
+ * Returns:
+ * 0 on success, error code on failure.
+ */
+int drm_buddy_block_trim(struct drm_buddy *mm,
+u64 new_size,
+struct list_head *blocks)
+{
+ struct drm_buddy_block *parent;
+ struct drm_buddy_block *block;
+ LIST_HEAD(dfs);
+ u64 new_start;
+ int err;
+
+ if (!list_is_singular(blocks))
+ return -EINVAL;
+
+ block = list_first_entry(blocks,
+struct drm_buddy_block,
+link);
+
+ if (!drm_buddy_block_is_allocated(block))
+ return -EINVAL;
+
+ if (new_size > drm_buddy_block_size(mm, block))
+ return -EINVAL;
+
+ if (!new_size && !IS_ALIGNED(new_size, mm->chunk_size))
+ return -EINVAL;
+
+ if (new_size == drm_buddy_block_size(mm, block))
+ return 0;
+
+ list_del(>link);
+ mark_free(mm, block);
+ mm->avail += drm_buddy_block_size(mm, block);
+
+ /* Prevent recursively freeing this node */
+ parent = block->parent;
+ block->parent = NULL;
+
+ new_start = drm_buddy_block_offset(block);
+ list_add(>tmp_link, );
+ err = __alloc_range(mm, , new_start, new_size, blocks);
+ if (err) {
+ mark_allocated(block);
+ mm->avail -= drm_buddy_block_size(mm, block);
+ list_add(>link, blocks);
+ }
+
+ block->parent = parent;
+ return err;
+}
+EXPORT_SYMBOL(drm_buddy_block_trim);
+
/**
* drm_buddy_alloc_blocks - allocate power-of-two blocks
*
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index 3662434b64bb..53eb100688a6 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -97,6 +97,16 @@ static int i915_ttm_buddy_man_alloc(struct
ttm_resource_manager *man,
if (unlikely(err))
goto err_free_blocks;
+ if (place->flags & TTM_PL_FLAG_CONTIGUOUS) {
+ u64 original_size = (u64)bman_res->base.num_pages << PAGE_SHIFT;
+
+ mutex_lock(>lock);
+ drm_buddy_block_trim(mm,
+original_size,
+_res->blocks);
+ mutex_unlock(>lock);
+ }
+
*res = _res->base;
return 0;
diff --git a/include/drm/drm_buddy.h
[Intel-gfx] [PATCH 01/20] drm: improve drm_buddy_alloc function
From: Arunpravin
- Make drm_buddy_alloc a single function to handle
range allocation and non-range allocation demands
- Implemented a new function alloc_range() which allocates
the requested power-of-two block comply with range limitations
- Moved order computation and memory alignment logic from
i915 driver to drm buddy
v2:
merged below changes to keep the build unbroken
- drm_buddy_alloc_range() becomes obsolete and may be removed
- enable ttm range allocation (fpfn / lpfn) support in i915 driver
- apply enhanced drm_buddy_alloc() function to i915 driver
v3(Matthew Auld):
- Fix alignment issues and remove unnecessary list_empty check
- add more validation checks for input arguments
- make alloc_range() block allocations as bottom-up
- optimize order computation logic
- replace uint64_t with u64, which is preferred in the kernel
v4(Matthew Auld):
- keep drm_buddy_alloc_range() function implementation for generic
actual range allocations
- keep alloc_range() implementation for end bias allocations
v5(Matthew Auld):
- modify drm_buddy_alloc() passing argument place->lpfn to lpfn
as place->lpfn will currently always be zero for i915
v6(Matthew Auld):
- fixup potential uaf - If we are unlucky and can't allocate
enough memory when splitting blocks, where we temporarily
end up with the given block and its buddy on the respective
free list, then we need to ensure we delete both blocks,
and no just the buddy, before potentially freeing them
- fix warnings reported by kernel test robot
Signed-off-by: Arunpravin
---
drivers/gpu/drm/drm_buddy.c | 326 +-
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 67 ++--
drivers/gpu/drm/i915/i915_ttm_buddy_manager.h | 2 +
include/drm/drm_buddy.h | 22 +-
4 files changed, 293 insertions(+), 124 deletions(-)
diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c
index d60878bc9c20..954e31962c74 100644
--- a/drivers/gpu/drm/drm_buddy.c
+++ b/drivers/gpu/drm/drm_buddy.c
@@ -282,23 +282,99 @@ void drm_buddy_free_list(struct drm_buddy *mm, struct
list_head *objects)
}
EXPORT_SYMBOL(drm_buddy_free_list);
-/**
- * drm_buddy_alloc_blocks - allocate power-of-two blocks
- *
- * @mm: DRM buddy manager to allocate from
- * @order: size of the allocation
- *
- * The order value here translates to:
- *
- * 0 = 2^0 * mm->chunk_size
- * 1 = 2^1 * mm->chunk_size
- * 2 = 2^2 * mm->chunk_size
- *
- * Returns:
- * allocated ptr to the _buddy_block on success
- */
-struct drm_buddy_block *
-drm_buddy_alloc_blocks(struct drm_buddy *mm, unsigned int order)
+static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2)
+{
+ return s1 <= e2 && e1 >= s2;
+}
+
+static inline bool contains(u64 s1, u64 e1, u64 s2, u64 e2)
+{
+ return s1 <= s2 && e1 >= e2;
+}
+
+static struct drm_buddy_block *
+alloc_range_bias(struct drm_buddy *mm,
+u64 start, u64 end,
+unsigned int order)
+{
+ struct drm_buddy_block *block;
+ struct drm_buddy_block *buddy;
+ LIST_HEAD(dfs);
+ int err;
+ int i;
+
+ end = end - 1;
+
+ for (i = 0; i < mm->n_roots; ++i)
+ list_add_tail(>roots[i]->tmp_link, );
+
+ do {
+ u64 block_start;
+ u64 block_end;
+
+ block = list_first_entry_or_null(,
+struct drm_buddy_block,
+tmp_link);
+ if (!block)
+ break;
+
+ list_del(>tmp_link);
+
+ if (drm_buddy_block_order(block) < order)
+ continue;
+
+ block_start = drm_buddy_block_offset(block);
+ block_end = block_start + drm_buddy_block_size(mm, block) - 1;
+
+ if (!overlaps(start, end, block_start, block_end))
+ continue;
+
+ if (drm_buddy_block_is_allocated(block))
+ continue;
+
+ if (contains(start, end, block_start, block_end) &&
+ order == drm_buddy_block_order(block)) {
+ /*
+* Find the free block within the range.
+*/
+ if (drm_buddy_block_is_free(block))
+ return block;
+
+ continue;
+ }
+
+ if (!drm_buddy_block_is_split(block)) {
+ err = split_block(mm, block);
+ if (unlikely(err))
+ goto err_undo;
+ }
+
+ list_add(>right->tmp_link, );
+ list_add(>left->tmp_link, );
+ } while (1);
+
+ return ERR_PTR(-ENOSPC);
+
+err_undo:
+ /*
+* We really don't want to leave around a bunch of split blocks, since
+* bigger is better, so make
[Intel-gfx] [PATCH 10/20] drm/i915/selftests: mock test io_size
Check that mappable vs non-mappable matches our expectations.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
.../drm/i915/selftests/intel_memory_region.c | 143 ++
1 file changed, 143 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 247f65f02bbf..04ae29779206 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -17,6 +17,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_lmem.h"
#include "gem/i915_gem_region.h"
+#include "gem/i915_gem_ttm.h"
#include "gem/selftests/igt_gem_utils.h"
#include "gem/selftests/mock_context.h"
#include "gt/intel_engine_pm.h"
@@ -512,6 +513,147 @@ static int igt_mock_max_segment(void *arg)
return err;
}
+static u64 igt_object_mappable_total(struct drm_i915_gem_object *obj)
+{
+ struct intel_memory_region *mr = obj->mm.region;
+ struct i915_ttm_buddy_resource *bman_res =
+ to_ttm_buddy_resource(obj->mm.res);
+ struct drm_buddy *mm = bman_res->mm;
+ struct drm_buddy_block *block;
+ u64 total;
+
+ total = 0;
+ list_for_each_entry(block, _res->blocks, link) {
+ u64 start = drm_buddy_block_offset(block);
+ u64 end = start + drm_buddy_block_size(mm, block);
+
+ if (start < mr->io_size)
+ total += min_t(u64, end, mr->io_size) - start;
+ }
+
+ return total;
+}
+
+static int igt_mock_io_size(void *arg)
+{
+ struct intel_memory_region *mr = arg;
+ struct drm_i915_private *i915 = mr->i915;
+ struct drm_i915_gem_object *obj;
+ u64 mappable_theft_total;
+ u64 io_size;
+ u64 total;
+ u64 ps;
+ u64 rem;
+ u64 size;
+ I915_RND_STATE(prng);
+ LIST_HEAD(objects);
+ int err = 0;
+
+ ps = SZ_4K;
+ if (i915_prandom_u64_state() & 1)
+ ps = SZ_64K; /* For something like DG2 */
+
+ div64_u64_rem(i915_prandom_u64_state(), SZ_8G, );
+ total = round_down(total, ps);
+ total = max_t(u64, total, SZ_1G);
+
+ div64_u64_rem(i915_prandom_u64_state(), total - ps, _size);
+ io_size = round_down(io_size, ps);
+ io_size = max_t(u64, io_size, SZ_256M); /* 256M seems to be the common
lower limit */
+
+ pr_info("%s with ps=%llx, io_size=%llx, total=%llx\n",
+ __func__, ps, io_size, total);
+
+ mr = mock_region_create(i915, 0, total, ps, 0, io_size);
+ if (IS_ERR(mr)) {
+ err = PTR_ERR(mr);
+ goto out_err;
+ }
+
+ mappable_theft_total = 0;
+ rem = total - io_size;
+ do {
+ div64_u64_rem(i915_prandom_u64_state(), rem, );
+ size = round_down(size, ps);
+ size = max(size, ps);
+
+ obj = igt_object_create(mr, , size,
+ I915_BO_ALLOC_TOPDOWN);
+ if (IS_ERR(obj)) {
+ pr_err("%s TOPDOWN failed with rem=%llx, size=%llx\n",
+ __func__, rem, size);
+ err = PTR_ERR(obj);
+ goto out_close;
+ }
+
+ mappable_theft_total += igt_object_mappable_total(obj);
+ rem -= size;
+ } while (rem);
+
+ pr_info("%s mappable theft=(%lluMiB/%lluMiB), total=%lluMiB\n",
+ __func__,
+ (u64)mappable_theft_total >> 20,
+ (u64)io_size >> 20,
+ (u64)total >> 20);
+
+ /*
+* Even if we allocate all of the non-mappable portion, we should still
+* be able to dip into the mappable portion.
+*/
+ obj = igt_object_create(mr, , io_size,
+ I915_BO_ALLOC_TOPDOWN);
+ if (IS_ERR(obj)) {
+ pr_err("%s allocation unexpectedly failed\n", __func__);
+ err = PTR_ERR(obj);
+ goto out_close;
+ }
+
+ close_objects(mr, );
+
+ rem = io_size;
+ do {
+ div64_u64_rem(i915_prandom_u64_state(), rem, );
+ size = round_down(size, ps);
+ size = max(size, ps);
+
+ obj = igt_object_create(mr, , size, 0);
+ if (IS_ERR(obj)) {
+ pr_err("%s MAPPABLE failed with rem=%llx, size=%llx\n",
+ __func__, rem, size);
+ err = PTR_ERR(obj);
+ goto out_close;
+ }
+
+ if (igt_object_mappable_total(obj) != size) {
+ pr_err("%s allocation is not mappable(size=%llx)\n",
+ __func__, size);
+ err = -EINVAL;
+ goto out_close;
+ }
+ rem -= size;
+ } while (rem);
+
+ /*
+* We
[Intel-gfx] [PATCH 11/20] drm/i915/ttm: tweak priority hint selection
For some reason we are selecting PRIO_HAS_PAGES when we don't have
mm.pages, and vice versa. Perhaps something else is going on here.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index e60b677ecd54..e4cd6ccf5ab1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -848,11 +848,9 @@ void i915_ttm_adjust_lru(struct drm_i915_gem_object *obj)
} else if (obj->mm.madv != I915_MADV_WILLNEED) {
bo->priority = I915_TTM_PRIO_PURGE;
} else if (!i915_gem_object_has_pages(obj)) {
- if (bo->priority < I915_TTM_PRIO_HAS_PAGES)
- bo->priority = I915_TTM_PRIO_HAS_PAGES;
+ bo->priority = I915_TTM_PRIO_NO_PAGES;
} else {
- if (bo->priority > I915_TTM_PRIO_NO_PAGES)
- bo->priority = I915_TTM_PRIO_NO_PAGES;
+ bo->priority = I915_TTM_PRIO_HAS_PAGES;
}
ttm_bo_move_to_lru_tail(bo, bo->resource, NULL);
--
2.34.1
[Intel-gfx] [PATCH 12/20] drm/i915/ttm: make eviction mappable aware
If we need to make room for some some mappable object, then we should
only victimize objects that have one or pages that occupy the visible
portion of LMEM. Let's also create a new priority hint for objects that
are placed in mappable memory, where we know that CPU access was
requested, that way we hopefully victimize these last.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 65 -
1 file changed, 63 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index e4cd6ccf5ab1..8376e4c3d290 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -5,8 +5,10 @@
#include
#include
+#include
#include "i915_drv.h"
+#include "i915_ttm_buddy_manager.h"
#include "intel_memory_region.h"
#include "intel_region_ttm.h"
@@ -20,6 +22,7 @@
#define I915_TTM_PRIO_PURGE 0
#define I915_TTM_PRIO_NO_PAGES 1
#define I915_TTM_PRIO_HAS_PAGES 2
+#define I915_TTM_PRIO_NEEDS_CPU_ACCESS 3
/*
* Size of struct ttm_place vector in on-stack struct ttm_placement allocs
@@ -337,6 +340,7 @@ static bool i915_ttm_eviction_valuable(struct
ttm_buffer_object *bo,
const struct ttm_place *place)
{
struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo);
+ struct ttm_resource *res = bo->resource;
if (!obj)
return false;
@@ -350,7 +354,48 @@ static bool i915_ttm_eviction_valuable(struct
ttm_buffer_object *bo,
return false;
/* Will do for now. Our pinned objects are still on TTM's LRU lists */
- return i915_gem_object_evictable(obj);
+ if (!i915_gem_object_evictable(obj))
+ return false;
+
+ switch (res->mem_type) {
+ case TTM_PL_PRIV: {
+ struct ttm_resource_manager *man =
+ ttm_manager_type(bo->bdev, res->mem_type);
+ struct i915_ttm_buddy_resource *bman_res =
+ to_ttm_buddy_resource(res);
+ struct drm_buddy *mm = bman_res->mm;
+ struct drm_buddy_block *block;
+
+ if (!place->fpfn && !place->lpfn)
+ return true;
+
+ GEM_BUG_ON(!place->lpfn);
+
+ /*
+* If we just want something mappable then we can quickly check
+* if the current victim resource is using any of the CPU
+* visible portion.
+*/
+ if (!place->fpfn &&
+ place->lpfn == i915_ttm_buddy_man_visible_size(man))
+ return bman_res->used_visible_size > 0;
+
+ /* Real range allocation */
+ list_for_each_entry(block, _res->blocks, link) {
+ unsigned long fpfn =
+ drm_buddy_block_offset(block) >> PAGE_SHIFT;
+ unsigned long lpfn = fpfn +
+ (drm_buddy_block_size(mm, block) >> PAGE_SHIFT);
+
+ if (place->fpfn < lpfn && place->lpfn > fpfn)
+ return true;
+ }
+ return false;
+ } default:
+ break;
+ }
+
+ return true;
}
static void i915_ttm_evict_flags(struct ttm_buffer_object *bo,
@@ -850,7 +895,23 @@ void i915_ttm_adjust_lru(struct drm_i915_gem_object *obj)
} else if (!i915_gem_object_has_pages(obj)) {
bo->priority = I915_TTM_PRIO_NO_PAGES;
} else {
- bo->priority = I915_TTM_PRIO_HAS_PAGES;
+ struct ttm_resource_manager *man =
+ ttm_manager_type(bo->bdev, bo->resource->mem_type);
+
+ /*
+* If we need to place an LMEM resource which doesn't need CPU
+* access then we should try not to victimize mappable objects
+* first, since we likely end up stealing more of the mappable
+* portion. And likewise when we try to find space for a mappble
+* object, we know not to ever victimize objects that don't
+* occupy any mappable pages.
+*/
+ if (i915_ttm_cpu_maps_iomem(bo->resource) &&
+ i915_ttm_buddy_man_visible_size(man) < man->size &&
+ !(obj->flags & I915_BO_ALLOC_TOPDOWN))
+ bo->priority = I915_TTM_PRIO_NEEDS_CPU_ACCESS;
+ else
+ bo->priority = I915_TTM_PRIO_HAS_PAGES;
}
ttm_bo_move_to_lru_tail(bo, bo->resource, NULL);
--
2.34.1
[Intel-gfx] [PATCH 08/20] drm/i915/buddy: adjust res->start
Differentiate between mappable vs non-mappable resources, also if this is an actual range allocation ensure we set res->start as the starting pfn. Later when we need to do non-mappable -> mappable moves then we want TTM to see that the current placement is not compatible, which should result in an actual move, instead of being turned into a noop. Signed-off-by: Matthew Auld Cc: Thomas Hellström --- drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c index 6e5842155898..bc725a92fc5c 100644 --- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c +++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c @@ -140,6 +140,13 @@ static int i915_ttm_buddy_man_alloc(struct ttm_resource_manager *man, mutex_unlock(>lock); } + if (place->lpfn - place->fpfn == n_pages) + bman_res->base.start = place->fpfn; + else if (lpfn <= bman->visible_size) + bman_res->base.start = 0; + else + bman_res->base.start = bman->visible_size; + *res = _res->base; return 0; -- 2.34.1
[Intel-gfx] [PATCH 09/20] drm/i915/buddy: tweak 2big check
Otherwise we get -EINVAL, instead of the more useful -E2BIG if the
allocation doesn't fit within the pfn range, like with mappable lmem.
The hugepages selftest, for example, needs this to know if a smaller
size is needed.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/i915_ttm_buddy_manager.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
index bc725a92fc5c..7c24cc6608e3 100644
--- a/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
+++ b/drivers/gpu/drm/i915/i915_ttm_buddy_manager.c
@@ -81,7 +81,7 @@ static int i915_ttm_buddy_man_alloc(struct
ttm_resource_manager *man,
lpfn = pages;
}
- if (size > mm->size) {
+ if (size > lpfn << PAGE_SHIFT) {
err = -E2BIG;
goto err_free_res;
}
--
2.34.1
[Intel-gfx] [PATCH 04/20] drm/i915: add io_size plumbing
With small LMEM-BAR we need to be able to differentiate between the
total size of LMEM, and how much of it is CPU mappable. The end goal is
to be able to utilize the entire range, even if part of is it not CPU
accessible.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_shmem.c| 2 +-
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 8 +---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 2 +-
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 6 +-
drivers/gpu/drm/i915/intel_memory_region.c | 6 +-
drivers/gpu/drm/i915/intel_memory_region.h | 2 ++
drivers/gpu/drm/i915/selftests/intel_memory_region.c | 8
drivers/gpu/drm/i915/selftests/mock_region.c | 6 --
drivers/gpu/drm/i915/selftests/mock_region.h | 3 ++-
10 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
index 6c57b0a79c8a..a9aca11cedbb 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_shmem.c
@@ -696,7 +696,7 @@ struct intel_memory_region *i915_gem_shmem_setup(struct
drm_i915_private *i915,
{
return intel_memory_region_create(i915, 0,
totalram_pages() << PAGE_SHIFT,
- PAGE_SIZE, 0,
+ PAGE_SIZE, 0, 0,
type, instance,
_region_ops);
}
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
index 26975d857776..387b48686851 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c
@@ -490,6 +490,7 @@ static int i915_gem_init_stolen(struct intel_memory_region
*mem)
/* Exclude the reserved region from driver use */
mem->region.end = reserved_base - 1;
+ mem->io_size = resource_size(>region);
/* It is possible for the reserved area to end before the end of stolen
* memory, so just consider the start. */
@@ -746,7 +747,7 @@ static int init_stolen_lmem(struct intel_memory_region *mem)
if (!io_mapping_init_wc(>iomap,
mem->io_start,
- resource_size(>region)))
+ mem->io_size))
return -EIO;
/*
@@ -801,7 +802,8 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915,
u16 type,
I915_GTT_PAGE_SIZE_4K;
mem = intel_memory_region_create(i915, lmem_base, lmem_size,
-min_page_size, io_start,
+min_page_size,
+io_start, lmem_size,
type, instance,
_region_stolen_lmem_ops);
if (IS_ERR(mem))
@@ -832,7 +834,7 @@ i915_gem_stolen_smem_setup(struct drm_i915_private *i915,
u16 type,
mem = intel_memory_region_create(i915,
intel_graphics_stolen_res.start,
resource_size(_graphics_stolen_res),
-PAGE_SIZE, 0, type, instance,
+PAGE_SIZE, 0, 0, type, instance,
_region_stolen_smem_ops);
if (IS_ERR(mem))
return mem;
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 84cae740b4a5..e1140ca3d9a0 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -1103,7 +1103,7 @@ i915_gem_ttm_system_setup(struct drm_i915_private *i915,
mr = intel_memory_region_create(i915, 0,
totalram_pages() << PAGE_SHIFT,
- PAGE_SIZE, 0,
+ PAGE_SIZE, 0, 0,
type, instance,
_system_region_ops);
if (IS_ERR(mr))
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index f36191ebf964..42db9cd30978 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -499,7 +499,7 @@ static int igt_mock_memory_region_huge_pages(void *arg)
int bit;
int err = 0;
- mem = mock_region_create(i915, 0, SZ_2G, I915_GTT_PAGE_SIZE_4K, 0);
+ mem = mock_region_create(i915, 0, SZ_2G, I915_GTT_PAGE_SIZE_4K, 0, 0);
if (IS_ERR(mem)) {
pr_err("%s failed to create memory
[Intel-gfx] [PATCH 05/20] drm/i915/ttm: require mappable by default
On devices with non-mappable LMEM ensure we always allocate the pages
within the mappable portion. For now we assume that all LMEM buffers
will require CPU access, which is also inline with pretty much all
current kernel internal users. In the next patch we will introduce a new
flag to override this behaviour.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 4
drivers/gpu/drm/i915/intel_region_ttm.c | 5 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index e1140ca3d9a0..d9a04c7d41b1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -128,6 +128,10 @@ i915_ttm_place_from_region(const struct
intel_memory_region *mr,
if (flags & I915_BO_ALLOC_CONTIGUOUS)
place->flags = TTM_PL_FLAG_CONTIGUOUS;
+ if (mr->io_size && mr->io_size < mr->total) {
+ place->fpfn = 0;
+ place->lpfn = mr->io_size >> PAGE_SHIFT;
+ }
}
static void
diff --git a/drivers/gpu/drm/i915/intel_region_ttm.c
b/drivers/gpu/drm/i915/intel_region_ttm.c
index f2b888c16958..4689192d5e8d 100644
--- a/drivers/gpu/drm/i915/intel_region_ttm.c
+++ b/drivers/gpu/drm/i915/intel_region_ttm.c
@@ -199,6 +199,11 @@ intel_region_ttm_resource_alloc(struct intel_memory_region
*mem,
struct ttm_resource *res;
int ret;
+ if (mem->io_size && mem->io_size < mem->total) {
+ place.fpfn = 0;
+ place.lpfn = mem->io_size >> PAGE_SHIFT;
+ }
+
mock_bo.base.size = size;
place.flags = flags;
--
2.34.1
[Intel-gfx] [PATCH 14/20] drm/i915/selftests: exercise mmap migration
Exercise each of the migration scenarios, verifying that the final
placement and buffer contents match our expectations.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
.../drm/i915/gem/selftests/i915_gem_mman.c| 306 ++
1 file changed, 306 insertions(+)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
index ba29767348be..d2c1071df98a 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c
@@ -10,6 +10,7 @@
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_pm.h"
+#include "gt/intel_migrate.h"
#include "gem/i915_gem_region.h"
#include "huge_gem_object.h"
#include "i915_selftest.h"
@@ -999,6 +1000,310 @@ static int igt_mmap(void *arg)
return 0;
}
+static void igt_close_objects(struct drm_i915_private *i915,
+ struct list_head *objects)
+{
+ struct drm_i915_gem_object *obj, *on;
+
+ list_for_each_entry_safe(obj, on, objects, st_link) {
+ i915_gem_object_lock(obj, NULL);
+ if (i915_gem_object_has_pinned_pages(obj))
+ i915_gem_object_unpin_pages(obj);
+ /* No polluting the memory region between tests */
+ __i915_gem_object_put_pages(obj);
+ i915_gem_object_unlock(obj);
+ list_del(>st_link);
+ i915_gem_object_put(obj);
+ }
+
+ cond_resched();
+
+ i915_gem_drain_freed_objects(i915);
+}
+
+static void igt_make_evictable(struct list_head *objects)
+{
+ struct drm_i915_gem_object *obj;
+
+ list_for_each_entry(obj, objects, st_link) {
+ i915_gem_object_lock(obj, NULL);
+ if (i915_gem_object_has_pinned_pages(obj))
+ i915_gem_object_unpin_pages(obj);
+ i915_gem_object_unlock(obj);
+ }
+
+ cond_resched();
+}
+
+static int igt_fill_mappable(struct intel_memory_region *mr,
+struct list_head *objects)
+{
+ u64 size, total;
+ int err;
+
+ total = 0;
+ size = mr->io_size;
+ do {
+ struct drm_i915_gem_object *obj;
+
+ obj = i915_gem_object_create_region(mr, size, 0, 0);
+ if (IS_ERR(obj)) {
+ err = PTR_ERR(obj);
+ goto err_close;
+ }
+
+ list_add(>st_link, objects);
+
+ err = i915_gem_object_pin_pages_unlocked(obj);
+ if (err) {
+ if (err != -ENXIO && err != -ENOMEM)
+ goto err_close;
+
+ if (size == mr->min_page_size) {
+ err = 0;
+ break;
+ }
+
+ size >>= 1;
+ continue;
+ }
+
+ total += obj->base.size;
+ } while (1);
+
+ pr_info("%s filled=%lluMiB\n", __func__, total >> 20);
+ return 0;
+
+err_close:
+ igt_close_objects(mr->i915, objects);
+ return err;
+}
+
+static int ___igt_mmap_migrate(struct drm_i915_private *i915,
+ struct drm_i915_gem_object *obj,
+ unsigned long addr,
+ bool unfaultable)
+{
+ struct vm_area_struct *area;
+ int err = 0, i;
+
+ pr_info("igt_mmap(%s, %d) @ %lx\n",
+obj->mm.region->name, I915_MMAP_TYPE_FIXED, addr);
+
+ mmap_read_lock(current->mm);
+ area = vma_lookup(current->mm, addr);
+ mmap_read_unlock(current->mm);
+ if (!area) {
+ pr_err("%s: Did not create a vm_area_struct for the mmap\n",
+ obj->mm.region->name);
+ err = -EINVAL;
+ goto out_unmap;
+ }
+
+ for (i = 0; i < obj->base.size / sizeof(u32); i++) {
+ u32 __user *ux = u64_to_user_ptr((u64)(addr + i * sizeof(*ux)));
+ u32 x;
+
+ if (get_user(x, ux)) {
+ err = -EFAULT;
+ if (!unfaultable) {
+ pr_err("%s: Unable to read from mmap,
offset:%zd\n",
+ obj->mm.region->name, i * sizeof(x));
+ goto out_unmap;
+ }
+
+ continue;
+ }
+
+ if (unfaultable) {
+ pr_err("%s: Faulted unmappable memory\n",
+ obj->mm.region->name);
+ err = -EINVAL;
+ goto out_unmap;
+ }
+
+ if (x != expand32(POISON_INUSE)) {
+ pr_err("%s: Read incorrect value from mmap, offset:%zd,
found:%x, expected:%x\n",
+
Re: [Intel-gfx] [PATCH v2 08/11] drm/gem: Sort includes alphabetically
On Wed, 26 Jan 2022, Lucas De Marchi wrote: > Sort includes alphabetically so it's easier to add/remove includes and > know when that is needed. > > Signed-off-by: Lucas De Marchi Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/drm_gem.c | 20 ++-- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c > index 4dcdec6487bb..21631c22b374 100644 > --- a/drivers/gpu/drm/drm_gem.c > +++ b/drivers/gpu/drm/drm_gem.c > @@ -25,20 +25,20 @@ > * > */ > > -#include > -#include > -#include > -#include > -#include > +#include > +#include > #include > -#include > +#include > +#include > +#include > #include > +#include > #include > -#include > -#include > -#include > -#include > #include > +#include > +#include > +#include > +#include > > #include > #include -- Jani Nikula, Intel Open Source Graphics Center
[Intel-gfx] [PATCH 15/20] drm/i915/selftests: handle allocation failures
If we have to contend with non-mappable LMEM, then we need to ensure the
object fits within the mappable portion, like in the selftests, where we
later try to CPU access the pages. However if it can't then we need to
gracefully handle this, without throwing an error.
Also it looks like TTM will return -ENOMEM if the object can't be
placed.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 2 +-
drivers/gpu/drm/i915/selftests/intel_memory_region.c | 8 +++-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
index 42db9cd30978..3caa178bbd07 100644
--- a/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
+++ b/drivers/gpu/drm/i915/gem/selftests/huge_pages.c
@@ -1344,7 +1344,7 @@ static int igt_ppgtt_smoke_huge(void *arg)
err = i915_gem_object_pin_pages_unlocked(obj);
if (err) {
- if (err == -ENXIO || err == -E2BIG) {
+ if (err == -ENXIO || err == -E2BIG || err == -ENOMEM) {
i915_gem_object_put(obj);
size >>= 1;
goto try_again;
diff --git a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
index 04ae29779206..87bff7f83554 100644
--- a/drivers/gpu/drm/i915/selftests/intel_memory_region.c
+++ b/drivers/gpu/drm/i915/selftests/intel_memory_region.c
@@ -822,8 +822,14 @@ static int igt_lmem_create_with_ps(void *arg)
i915_gem_object_lock(obj, NULL);
err = i915_gem_object_pin_pages(obj);
- if (err)
+ if (err) {
+ if (err == -ENXIO || err == -E2BIG || err == -ENOMEM) {
+ pr_info("%s not enough lmem for ps(%u)
err=%d\n",
+ __func__, ps, err);
+ err = 0;
+ }
goto out_put;
+ }
daddr = i915_gem_object_get_dma_address(obj, 0);
if (!IS_ALIGNED(daddr, ps)) {
--
2.34.1
[Intel-gfx] [PATCH 18/20] drm/i915/uapi: forbid ALLOC_TOPDOWN for error capture
On platforms where there might be non-mappable LMEM, force userspace to
mark the buffers with the correct hint. When dumping the BO contents
during capture we need CPU access. Note this only applies to buffers
that can be placed in LMEM, and also doesn't impact DG1.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 498b458fd784..3c8083852620 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -1965,7 +1965,7 @@ eb_find_first_request_added(struct i915_execbuffer *eb)
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
/* Stage with GFP_KERNEL allocations before we enter the signaling critical
path */
-static void eb_capture_stage(struct i915_execbuffer *eb)
+static int eb_capture_stage(struct i915_execbuffer *eb)
{
const unsigned int count = eb->buffer_count;
unsigned int i = count, j;
@@ -1978,6 +1978,9 @@ static void eb_capture_stage(struct i915_execbuffer *eb)
if (!(flags & EXEC_OBJECT_CAPTURE))
continue;
+ if (vma->obj->flags & I915_BO_ALLOC_TOPDOWN)
+ return -EINVAL;
+
for_each_batch_create_order(eb, j) {
struct i915_capture_list *capture;
@@ -1990,6 +1993,8 @@ static void eb_capture_stage(struct i915_execbuffer *eb)
eb->capture_lists[j] = capture;
}
}
+
+ return 0;
}
/* Commit once we're in the critical path */
@@ -3418,7 +3423,9 @@ i915_gem_do_execbuffer(struct drm_device *dev,
}
ww_acquire_done();
- eb_capture_stage();
+ err = eb_capture_stage();
+ if (err)
+ goto err_vma;
out_fence = eb_requests_create(, in_fence, out_fence_fd);
if (IS_ERR(out_fence)) {
--
2.34.1
[Intel-gfx] [PATCH 19/20] drm/i915/lmem: don't treat small BAR as an error
Just pass along the probed io_size. The backend should be able to utilize the entire range here, even if some of it is non-mappable. It does leave open with what to do with stolen local-memory. Signed-off-by: Matthew Auld Cc: Thomas Hellström --- drivers/gpu/drm/i915/gt/intel_region_lmem.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c index 2c7ec7ff79fd..b788fc2b3df8 100644 --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c @@ -200,6 +200,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) struct intel_memory_region *mem; resource_size_t min_page_size; resource_size_t io_start; + resource_size_t io_size; resource_size_t lmem_size; int err; @@ -210,7 +211,8 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) lmem_size = intel_uncore_read64(uncore, GEN12_GSMBASE); io_start = pci_resource_start(pdev, 2); - if (GEM_WARN_ON(lmem_size > pci_resource_len(pdev, 2))) + io_size = min(pci_resource_len(pdev, 2), lmem_size); + if (!io_size) return ERR_PTR(-ENODEV); min_page_size = HAS_64K_PAGES(i915) ? I915_GTT_PAGE_SIZE_64K : @@ -220,7 +222,7 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt) lmem_size, min_page_size, io_start, -lmem_size, +io_size, INTEL_MEMORY_LOCAL, 0, _region_lmem_ops); -- 2.34.1
[Intel-gfx] [PATCH 16/20] drm/i915/create: apply ALLOC_TOPDOWN by default
Starting from DG2+, when dealing with LMEM, we assume that by default all userspace allocations should be placed in the non-mappable portion of LMEM. Note that dumb buffers are not included here, since these are not "GPU accelerated" and likely need CPU access. In a later patch userspace will be able to provide a hint if CPU access to the buffer is needed. Signed-off-by: Matthew Auld Cc: Thomas Hellström --- drivers/gpu/drm/i915/gem/i915_gem_create.c | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_create.c b/drivers/gpu/drm/i915/gem/i915_gem_create.c index 9402d4bf4ffc..e7456443f163 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_create.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_create.c @@ -424,6 +424,15 @@ i915_gem_create_ext_ioctl(struct drm_device *dev, void *data, ext_data.n_placements = 1; } + /* +* TODO: add a userspace hint to force CPU_ACCESS for the object, which +* can override this. +*/ + if (!IS_DG1(i915) && (ext_data.n_placements > 1 || + ext_data.placements[0]->type != + INTEL_MEMORY_SYSTEM)) + ext_data.flags |= I915_BO_ALLOC_TOPDOWN; + obj = __i915_gem_object_create_user_ext(i915, args->size, ext_data.placements, ext_data.n_placements, -- 2.34.1
[Intel-gfx] [PATCH 13/20] drm/i915/ttm: mappable migration on fault
The end goal is to have userspace tell the kernel what buffers will
require CPU access, however if we ever reach the CPU fault handler, and
the current resource is not mappable, then we should attempt to migrate
the buffer to the mappable portion of LMEM, or even system memory, if the
allowable placements permit it.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 58 ++---
1 file changed, 52 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
index 8376e4c3d290..7299053fb1ec 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c
@@ -636,11 +636,25 @@ static void i915_ttm_swap_notify(struct ttm_buffer_object
*bo)
i915_ttm_purge(obj);
}
+static bool i915_ttm_resource_mappable(struct ttm_resource *res)
+{
+ struct i915_ttm_buddy_resource *bman_res = to_ttm_buddy_resource(res);
+
+ if (!i915_ttm_cpu_maps_iomem(res))
+ return true;
+
+ return bman_res->used_visible_size == bman_res->base.num_pages;
+}
+
static int i915_ttm_io_mem_reserve(struct ttm_device *bdev, struct
ttm_resource *mem)
{
+
if (!i915_ttm_cpu_maps_iomem(mem))
return 0;
+ if (!i915_ttm_resource_mappable(mem))
+ return -EINVAL;
+
mem->bus.caching = ttm_write_combined;
mem->bus.is_iomem = true;
@@ -779,14 +793,15 @@ static int i915_ttm_get_pages(struct drm_i915_gem_object
*obj)
* Gem forced migration using the i915_ttm_migrate() op, is allowed even
* to regions that are not in the object's list of allowable placements.
*/
-static int i915_ttm_migrate(struct drm_i915_gem_object *obj,
- struct intel_memory_region *mr)
+static int __i915_ttm_migrate(struct drm_i915_gem_object *obj,
+ struct intel_memory_region *mr,
+ unsigned int flags)
{
struct ttm_place requested;
struct ttm_placement placement;
int ret;
- i915_ttm_place_from_region(mr, , obj->flags);
+ i915_ttm_place_from_region(mr, , flags);
placement.num_placement = 1;
placement.num_busy_placement = 1;
placement.placement =
@@ -809,6 +824,12 @@ static int i915_ttm_migrate(struct drm_i915_gem_object
*obj,
return 0;
}
+static int i915_ttm_migrate(struct drm_i915_gem_object *obj,
+ struct intel_memory_region *mr)
+{
+ return __i915_ttm_migrate(obj, mr, obj->flags);
+}
+
static void i915_ttm_put_pages(struct drm_i915_gem_object *obj,
struct sg_table *st)
{
@@ -940,6 +961,10 @@ static void i915_ttm_delayed_free(struct
drm_i915_gem_object *obj)
ttm_bo_put(i915_gem_to_ttm(obj));
}
+static int __i915_ttm_migrate(struct drm_i915_gem_object *obj,
+ struct intel_memory_region *mr,
+ unsigned int flags);
+
static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
{
struct vm_area_struct *area = vmf->vma;
@@ -953,9 +978,6 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
if (!obj)
return VM_FAULT_SIGBUS;
- if (obj->flags & I915_BO_ALLOC_TOPDOWN)
- return -EINVAL;
-
/* Sanity check that we allow writing into this object */
if (unlikely(i915_gem_object_is_readonly(obj) &&
area->vm_flags & VM_WRITE))
@@ -970,6 +992,30 @@ static vm_fault_t vm_fault_ttm(struct vm_fault *vmf)
return VM_FAULT_SIGBUS;
}
+ if (!i915_ttm_resource_mappable(bo->resource)) {
+ int err = -ENODEV;
+ int i;
+
+ for (i = 0; i < obj->mm.n_placements; i++) {
+ struct intel_memory_region *mr = obj->mm.placements[i];
+ unsigned int flags;
+
+ if (!mr->io_size && mr->type != INTEL_MEMORY_SYSTEM)
+ continue;
+
+ flags = obj->flags;
+ flags &= ~I915_BO_ALLOC_TOPDOWN;
+ err = __i915_ttm_migrate(obj, mr, flags);
+ if (!err)
+ break;
+ }
+
+ if (err) {
+ dma_resv_unlock(bo->base.resv);
+ return VM_FAULT_SIGBUS;
+ }
+ }
+
if (drm_dev_enter(dev, )) {
ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
TTM_BO_VM_NUM_PREFAULT);
--
2.34.1
