Re: [PATCH 01/15] iommu/arm-smmu: Convert GR0 registers to bitfields
On 14/08/2019 18:20, Will Deacon wrote: On Fri, Aug 09, 2019 at 06:07:38PM +0100, Robin Murphy wrote: FIELD_PREP remains a terrible name, but the overall simplification will make further work on this stuff that much more manageable. This also serves as an audit of the header, wherein we can impose a consistent grouping and ordering of the offset and field definitions Signed-off-by: Robin Murphy --- drivers/iommu/arm-smmu-regs.h | 126 -- drivers/iommu/arm-smmu.c | 51 +++--- 2 files changed, 84 insertions(+), 93 deletions(-) diff --git a/drivers/iommu/arm-smmu-regs.h b/drivers/iommu/arm-smmu-regs.h index 1c278f7ae888..d189f025537a 100644 --- a/drivers/iommu/arm-smmu-regs.h +++ b/drivers/iommu/arm-smmu-regs.h @@ -10,111 +10,101 @@ #ifndef _ARM_SMMU_REGS_H #define _ARM_SMMU_REGS_H +#include + /* Configuration registers */ #define ARM_SMMU_GR0_sCR0 0x0 -#define sCR0_CLIENTPD (1 << 0) -#define sCR0_GFRE (1 << 1) -#define sCR0_GFIE (1 << 2) -#define sCR0_EXIDENABLE(1 << 3) -#define sCR0_GCFGFRE (1 << 4) -#define sCR0_GCFGFIE (1 << 5) -#define sCR0_USFCFG(1 << 10) -#define sCR0_VMIDPNE (1 << 11) -#define sCR0_PTM (1 << 12) -#define sCR0_FB(1 << 13) -#define sCR0_VMID16EN (1 << 31) -#define sCR0_BSU_SHIFT 14 -#define sCR0_BSU_MASK 0x3 +#define sCR0_VMID16EN BIT(31) +#define sCR0_BSU GENMASK(15, 14) +#define sCR0_FBBIT(13) +#define sCR0_PTM BIT(12) +#define sCR0_VMIDPNE BIT(11) +#define sCR0_USFCFGBIT(10) +#define sCR0_GCFGFIE BIT(5) +#define sCR0_GCFGFRE BIT(4) +#define sCR0_EXIDENABLEBIT(3) +#define sCR0_GFIE BIT(2) +#define sCR0_GFRE BIT(1) +#define sCR0_CLIENTPD BIT(0) /* Auxiliary Configuration register */ #define ARM_SMMU_GR0_sACR 0x10 /* Identification registers */ #define ARM_SMMU_GR0_ID0 0x20 +#define ID0_S1TS BIT(30) +#define ID0_S2TS BIT(29) +#define ID0_NTSBIT(28) +#define ID0_SMSBIT(27) +#define ID0_ATOSNS BIT(26) +#define ID0_PTFS_NO_AARCH32BIT(25) +#define ID0_PTFS_NO_AARCH32S BIT(24) +#define ID0_CTTW BIT(14) +#define ID0_NUMIRPTGENMASK(23, 16) nit: assuming this should be above ID0_CTTW so things are in descending bit order? Bah, indeed it should. Fixed now. Other than that, looks good to me. Thanks! Robin. ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH 01/15] iommu/arm-smmu: Convert GR0 registers to bitfields
On Fri, Aug 09, 2019 at 06:07:38PM +0100, Robin Murphy wrote: > FIELD_PREP remains a terrible name, but the overall simplification will > make further work on this stuff that much more manageable. This also > serves as an audit of the header, wherein we can impose a consistent > grouping and ordering of the offset and field definitions > > Signed-off-by: Robin Murphy > --- > drivers/iommu/arm-smmu-regs.h | 126 -- > drivers/iommu/arm-smmu.c | 51 +++--- > 2 files changed, 84 insertions(+), 93 deletions(-) > > diff --git a/drivers/iommu/arm-smmu-regs.h b/drivers/iommu/arm-smmu-regs.h > index 1c278f7ae888..d189f025537a 100644 > --- a/drivers/iommu/arm-smmu-regs.h > +++ b/drivers/iommu/arm-smmu-regs.h > @@ -10,111 +10,101 @@ > #ifndef _ARM_SMMU_REGS_H > #define _ARM_SMMU_REGS_H > > +#include > + > /* Configuration registers */ > #define ARM_SMMU_GR0_sCR00x0 > -#define sCR0_CLIENTPD(1 << 0) > -#define sCR0_GFRE(1 << 1) > -#define sCR0_GFIE(1 << 2) > -#define sCR0_EXIDENABLE (1 << 3) > -#define sCR0_GCFGFRE (1 << 4) > -#define sCR0_GCFGFIE (1 << 5) > -#define sCR0_USFCFG (1 << 10) > -#define sCR0_VMIDPNE (1 << 11) > -#define sCR0_PTM (1 << 12) > -#define sCR0_FB (1 << 13) > -#define sCR0_VMID16EN(1 << 31) > -#define sCR0_BSU_SHIFT 14 > -#define sCR0_BSU_MASK0x3 > +#define sCR0_VMID16ENBIT(31) > +#define sCR0_BSU GENMASK(15, 14) > +#define sCR0_FB BIT(13) > +#define sCR0_PTM BIT(12) > +#define sCR0_VMIDPNE BIT(11) > +#define sCR0_USFCFG BIT(10) > +#define sCR0_GCFGFIE BIT(5) > +#define sCR0_GCFGFRE BIT(4) > +#define sCR0_EXIDENABLE BIT(3) > +#define sCR0_GFIEBIT(2) > +#define sCR0_GFREBIT(1) > +#define sCR0_CLIENTPDBIT(0) > > /* Auxiliary Configuration register */ > #define ARM_SMMU_GR0_sACR0x10 > > /* Identification registers */ > #define ARM_SMMU_GR0_ID0 0x20 > +#define ID0_S1TS BIT(30) > +#define ID0_S2TS BIT(29) > +#define ID0_NTS BIT(28) > +#define ID0_SMS BIT(27) > +#define ID0_ATOSNS BIT(26) > +#define ID0_PTFS_NO_AARCH32 BIT(25) > +#define ID0_PTFS_NO_AARCH32S BIT(24) > +#define ID0_CTTW BIT(14) > +#define ID0_NUMIRPT GENMASK(23, 16) nit: assuming this should be above ID0_CTTW so things are in descending bit order? Other than that, looks good to me. Will ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
[PATCH 01/15] iommu/arm-smmu: Convert GR0 registers to bitfields
FIELD_PREP remains a terrible name, but the overall simplification will make further work on this stuff that much more manageable. This also serves as an audit of the header, wherein we can impose a consistent grouping and ordering of the offset and field definitions Signed-off-by: Robin Murphy --- drivers/iommu/arm-smmu-regs.h | 126 -- drivers/iommu/arm-smmu.c | 51 +++--- 2 files changed, 84 insertions(+), 93 deletions(-) diff --git a/drivers/iommu/arm-smmu-regs.h b/drivers/iommu/arm-smmu-regs.h index 1c278f7ae888..d189f025537a 100644 --- a/drivers/iommu/arm-smmu-regs.h +++ b/drivers/iommu/arm-smmu-regs.h @@ -10,111 +10,101 @@ #ifndef _ARM_SMMU_REGS_H #define _ARM_SMMU_REGS_H +#include + /* Configuration registers */ #define ARM_SMMU_GR0_sCR0 0x0 -#define sCR0_CLIENTPD (1 << 0) -#define sCR0_GFRE (1 << 1) -#define sCR0_GFIE (1 << 2) -#define sCR0_EXIDENABLE(1 << 3) -#define sCR0_GCFGFRE (1 << 4) -#define sCR0_GCFGFIE (1 << 5) -#define sCR0_USFCFG(1 << 10) -#define sCR0_VMIDPNE (1 << 11) -#define sCR0_PTM (1 << 12) -#define sCR0_FB(1 << 13) -#define sCR0_VMID16EN (1 << 31) -#define sCR0_BSU_SHIFT 14 -#define sCR0_BSU_MASK 0x3 +#define sCR0_VMID16EN BIT(31) +#define sCR0_BSU GENMASK(15, 14) +#define sCR0_FBBIT(13) +#define sCR0_PTM BIT(12) +#define sCR0_VMIDPNE BIT(11) +#define sCR0_USFCFGBIT(10) +#define sCR0_GCFGFIE BIT(5) +#define sCR0_GCFGFRE BIT(4) +#define sCR0_EXIDENABLEBIT(3) +#define sCR0_GFIE BIT(2) +#define sCR0_GFRE BIT(1) +#define sCR0_CLIENTPD BIT(0) /* Auxiliary Configuration register */ #define ARM_SMMU_GR0_sACR 0x10 /* Identification registers */ #define ARM_SMMU_GR0_ID0 0x20 +#define ID0_S1TS BIT(30) +#define ID0_S2TS BIT(29) +#define ID0_NTSBIT(28) +#define ID0_SMSBIT(27) +#define ID0_ATOSNS BIT(26) +#define ID0_PTFS_NO_AARCH32BIT(25) +#define ID0_PTFS_NO_AARCH32S BIT(24) +#define ID0_CTTW BIT(14) +#define ID0_NUMIRPTGENMASK(23, 16) +#define ID0_NUMSIDBGENMASK(12, 9) +#define ID0_EXIDS BIT(8) +#define ID0_NUMSMRGGENMASK(7, 0) + #define ARM_SMMU_GR0_ID1 0x24 +#define ID1_PAGESIZE BIT(31) +#define ID1_NUMPAGENDXBGENMASK(30, 28) +#define ID1_NUMS2CBGENMASK(23, 16) +#define ID1_NUMCB GENMASK(7, 0) + #define ARM_SMMU_GR0_ID2 0x28 +#define ID2_VMID16 BIT(15) +#define ID2_PTFS_64K BIT(14) +#define ID2_PTFS_16K BIT(13) +#define ID2_PTFS_4KBIT(12) +#define ID2_UBSGENMASK(11, 8) +#define ID2_OASGENMASK(7, 4) +#define ID2_IASGENMASK(3, 0) + #define ARM_SMMU_GR0_ID3 0x2c #define ARM_SMMU_GR0_ID4 0x30 #define ARM_SMMU_GR0_ID5 0x34 #define ARM_SMMU_GR0_ID6 0x38 + #define ARM_SMMU_GR0_ID7 0x3c +#define ID7_MAJOR GENMASK(7, 4) +#define ID7_MINOR GENMASK(3, 0) + #define ARM_SMMU_GR0_sGFSR 0x48 #define ARM_SMMU_GR0_sGFSYNR0 0x50 #define ARM_SMMU_GR0_sGFSYNR1 0x54 #define ARM_SMMU_GR0_sGFSYNR2 0x58 -#define ID0_S1TS (1 << 30) -#define ID0_S2TS (1 << 29) -#define ID0_NTS(1 << 28) -#define ID0_SMS(1 << 27) -#define ID0_ATOSNS (1 << 26) -#define ID0_PTFS_NO_AARCH32(1 << 25) -#define ID0_PTFS_NO_AARCH32S (1 << 24) -#define ID0_CTTW (1 << 14) -#define ID0_NUMIRPT_SHIFT 16 -#define ID0_NUMIRPT_MASK 0xff -#define ID0_NUMSIDB_SHIFT 9 -#define ID0_NUMSIDB_MASK 0xf -#define ID0_EXIDS (1 << 8) -#define ID0_NUMSMRG_SHIFT 0 -#define ID0_NUMSMRG_MASK 0xff - -#define ID1_PAGESIZE (1 << 31) -#define ID1_NUMPAGENDXB_SHIFT 28 -#define ID1_NUMPAGENDXB_MASK 7 -#define ID1_NUMS2CB_SHIFT 16 -#define ID1_NUMS2CB_MASK
