Re: [PATCH V3 1/3] clk: mvebu: add armada-370-xp specific clocks
On 10/15/2012 02:18 PM, Gregory CLEMENT wrote:
Add Armada 370/XP specific clocks: core clocks and CPU clocks.
The CPU clocks are only for Armada XP for the SMP mode.
...
+static struct core_clk_fn armada_370_clk_fn = {
+ .get_tclk_freq = armada_370_get_tclk_freq,
+ .get_pck_freq = armada_370_get_pck_freq,
+ .get_fab_freq_opt = armada_370_get_fab_freq_opt,
+};
+
+static struct core_clk_fn armada_xp_clk_fn = {
+ .get_tclk_freq = armada_xp_get_tclk_freq,
+ .get_pck_freq = armada_xp_get_pck_freq,
+ .get_fab_freq_opt = armada_xp_get_fab_freq_opt,
+};
+
+static const __initconst struct of_device_id clk_match[] = {
+ {
+.compatible = "marvell,armada-370-core-clockctrl",
+.data =_370_clk_fn,
+},
+
+ {
+.compatible = "marvell,armada-xp-core-clockctrl",
+.data =_xp_clk_fn,
+},
+ {
+/* sentinel */
+}
+};
Gregory,
armada_370_clk_fn and armada_xp_clk_fn cause section mismatches
as they are referenced within __initconst.
You should either rename them to armada_xp_clk_ops or annotate them
with the appropriate attribute.
Sebastian
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH V3 1/3] clk: mvebu: add armada-370-xp specific clocks
On 10/15/2012 02:18 PM, Gregory CLEMENT wrote:
Add Armada 370/XP specific clocks: core clocks and CPU clocks.
The CPU clocks are only for Armada XP for the SMP mode.
...
+static struct core_clk_fn armada_370_clk_fn = {
+ .get_tclk_freq = armada_370_get_tclk_freq,
+ .get_pck_freq = armada_370_get_pck_freq,
+ .get_fab_freq_opt = armada_370_get_fab_freq_opt,
+};
+
+static struct core_clk_fn armada_xp_clk_fn = {
+ .get_tclk_freq = armada_xp_get_tclk_freq,
+ .get_pck_freq = armada_xp_get_pck_freq,
+ .get_fab_freq_opt = armada_xp_get_fab_freq_opt,
+};
+
+static const __initconst struct of_device_id clk_match[] = {
+ {
+.compatible = marvell,armada-370-core-clockctrl,
+.data =armada_370_clk_fn,
+},
+
+ {
+.compatible = marvell,armada-xp-core-clockctrl,
+.data =armada_xp_clk_fn,
+},
+ {
+/* sentinel */
+}
+};
Gregory,
armada_370_clk_fn and armada_xp_clk_fn cause section mismatches
as they are referenced within __initconst.
You should either rename them to armada_xp_clk_ops or annotate them
with the appropriate attribute.
Sebastian
--
To unsubscribe from this list: send the line unsubscribe linux-kernel in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
[PATCH V3 1/3] clk: mvebu: add armada-370-xp specific clocks
Add Armada 370/XP specific clocks: core clocks and CPU clocks.
The CPU clocks are only for Armada XP for the SMP mode.
The core clocks are clocks which have their rate set during reset. The
code was written with the other SoCs of the mvebu family in
mind. Adding them should be pretty straight forward. For a new
SoC, only 3 binding have to be added:
- one to provide the tclk frequency
- one to provde the pclk frequency
- and one to provide the ratio between the pclk and the children
clocks
Signed-off-by: Gregory CLEMENT
---
.../devicetree/bindings/clock/mvebu-core-clock.txt | 40 +++
.../devicetree/bindings/clock/mvebu-cpu-clock.txt | 21 ++
drivers/clk/Makefile |1 +
drivers/clk/mvebu/Makefile |2 +
drivers/clk/mvebu/clk-core.c | 312
drivers/clk/mvebu/clk-core.h | 19 ++
drivers/clk/mvebu/clk-cpu.c| 155 ++
drivers/clk/mvebu/clk-cpu.h| 19 ++
drivers/clk/mvebu/clk.c| 36 +++
9 files changed, 605 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
create mode 100644 drivers/clk/mvebu/Makefile
create mode 100644 drivers/clk/mvebu/clk-core.c
create mode 100644 drivers/clk/mvebu/clk-core.h
create mode 100644 drivers/clk/mvebu/clk-cpu.c
create mode 100644 drivers/clk/mvebu/clk-cpu.h
create mode 100644 drivers/clk/mvebu/clk.c
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
new file mode 100644
index 000..d2e0965
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -0,0 +1,40 @@
+Device Tree Clock bindings for core clock of Marvell EBU platforms
+
+This is the binding for the "core" clock of the mvebu SoCs, the rate
+of this clocks are fixed during reset. Their value or ratio are taken
+from the Sample at Reset(SAR) register.
+
+Required properties:
+- compatible : shall be one of the following:
+ "marvell,armada-370-core-clockctrl" - core clock for Armada 370
+ "marvell,armada-xp-core-clockctrl" - core clock for Armada XP
+- reg : Address and length of the SAR register set
+- #clock-cells : should be set to 1.
+- clock-output-names: A list of clock output names that mvebu core
+ clocks provides. The full list of all valid clock names, IDs and
+ description are below.
+ NameID Description
+ tclk0 Peripheral clock
+ pclk1 CPU clock
+ nbclk 2 L2 clock
+ hclk3 DRAM control clock
+ dramclk 4 DDR clock
+
+coreclk: mvebu-sar@d0018230 {
+ #clock-cells = <1>;
+ reg = <0xd0018230 0x08>;
+ compatible = "marvell,armada-370-core-clockctrl";
+ clock-output-names =
+ "tclk", /* 0 */
+ "pclk", /* 1 */
+ "nbclk",/* 2 */
+ "hclk", /* 3 */
+ "dramclk", /* 4 */
+};
+
+timer@d0020300 {
+ compatible = "marvell,armada-370-xp-timer";
+ reg = <0xd0020300 0x30>;
+ interrupts = <37>, <38>, <39>, <40>;
+ clocks = < 0>;
+};
diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
new file mode 100644
index 000..c524618
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
@@ -0,0 +1,21 @@
+Device Tree Clock bindings for cpu clock of Marvell EBU platforms
+
+Required properties:
+- compatible : shall be one of the following:
+ "marvell,armada-xp-cpu-clockctrl" - cpu clocks for Armada XP
+- reg : Address and length of the clock complex register set
+- #clock-cells : should be set to 1.
+- clocks : shall be the input parent clock phandle for the clock.
+
+cpuclk: clock-complex@d0018700 {
+ #clock-cells = <1>;
+ compatible = "marvell,armada-xp-cpu-clockctrl";
+ reg = <0xd0018700 0xA0>;
+ clocks = < 1>;
+}
+
+cpu@0 {
+ compatible = "marvell,sheeva-v7";
+ reg = <0>;
+ clocks = < 0>;
+};
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 71a25b9..9c91d6c 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PLAT_SPEAR) += spear/
obj-$(CONFIG_ARCH_U300)+= clk-u300.o
obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
obj-$(CONFIG_ARCH_PRIMA2) += clk-prima2.o
+obj-$(CONFIG_ARCH_MVEBU) += mvebu/
ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_ARCH_MMP) += mmp/
endif
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
new file mode 100644
index 000..de94a87
--- /dev/null
+++ b/drivers/clk/mvebu/Makefile
@@ -0,0 +1,2 @@
[PATCH V3 1/3] clk: mvebu: add armada-370-xp specific clocks
Add Armada 370/XP specific clocks: core clocks and CPU clocks.
The CPU clocks are only for Armada XP for the SMP mode.
The core clocks are clocks which have their rate set during reset. The
code was written with the other SoCs of the mvebu family in
mind. Adding them should be pretty straight forward. For a new
SoC, only 3 binding have to be added:
- one to provide the tclk frequency
- one to provde the pclk frequency
- and one to provide the ratio between the pclk and the children
clocks
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
.../devicetree/bindings/clock/mvebu-core-clock.txt | 40 +++
.../devicetree/bindings/clock/mvebu-cpu-clock.txt | 21 ++
drivers/clk/Makefile |1 +
drivers/clk/mvebu/Makefile |2 +
drivers/clk/mvebu/clk-core.c | 312
drivers/clk/mvebu/clk-core.h | 19 ++
drivers/clk/mvebu/clk-cpu.c| 155 ++
drivers/clk/mvebu/clk-cpu.h| 19 ++
drivers/clk/mvebu/clk.c| 36 +++
9 files changed, 605 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
create mode 100644 Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
create mode 100644 drivers/clk/mvebu/Makefile
create mode 100644 drivers/clk/mvebu/clk-core.c
create mode 100644 drivers/clk/mvebu/clk-core.h
create mode 100644 drivers/clk/mvebu/clk-cpu.c
create mode 100644 drivers/clk/mvebu/clk-cpu.h
create mode 100644 drivers/clk/mvebu/clk.c
diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
new file mode 100644
index 000..d2e0965
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -0,0 +1,40 @@
+Device Tree Clock bindings for core clock of Marvell EBU platforms
+
+This is the binding for the core clock of the mvebu SoCs, the rate
+of this clocks are fixed during reset. Their value or ratio are taken
+from the Sample at Reset(SAR) register.
+
+Required properties:
+- compatible : shall be one of the following:
+ marvell,armada-370-core-clockctrl - core clock for Armada 370
+ marvell,armada-xp-core-clockctrl - core clock for Armada XP
+- reg : Address and length of the SAR register set
+- #clock-cells : should be set to 1.
+- clock-output-names: A list of clock output names that mvebu core
+ clocks provides. The full list of all valid clock names, IDs and
+ description are below.
+ NameID Description
+ tclk0 Peripheral clock
+ pclk1 CPU clock
+ nbclk 2 L2 clock
+ hclk3 DRAM control clock
+ dramclk 4 DDR clock
+
+coreclk: mvebu-sar@d0018230 {
+ #clock-cells = 1;
+ reg = 0xd0018230 0x08;
+ compatible = marvell,armada-370-core-clockctrl;
+ clock-output-names =
+ tclk, /* 0 */
+ pclk, /* 1 */
+ nbclk,/* 2 */
+ hclk, /* 3 */
+ dramclk, /* 4 */
+};
+
+timer@d0020300 {
+ compatible = marvell,armada-370-xp-timer;
+ reg = 0xd0020300 0x30;
+ interrupts = 37, 38, 39, 40;
+ clocks = coreclk 0;
+};
diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
new file mode 100644
index 000..c524618
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
@@ -0,0 +1,21 @@
+Device Tree Clock bindings for cpu clock of Marvell EBU platforms
+
+Required properties:
+- compatible : shall be one of the following:
+ marvell,armada-xp-cpu-clockctrl - cpu clocks for Armada XP
+- reg : Address and length of the clock complex register set
+- #clock-cells : should be set to 1.
+- clocks : shall be the input parent clock phandle for the clock.
+
+cpuclk: clock-complex@d0018700 {
+ #clock-cells = 1;
+ compatible = marvell,armada-xp-cpu-clockctrl;
+ reg = 0xd0018700 0xA0;
+ clocks = coreclk 1;
+}
+
+cpu@0 {
+ compatible = marvell,sheeva-v7;
+ reg = 0;
+ clocks = cpuclk 0;
+};
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 71a25b9..9c91d6c 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PLAT_SPEAR) += spear/
obj-$(CONFIG_ARCH_U300)+= clk-u300.o
obj-$(CONFIG_COMMON_CLK_VERSATILE) += versatile/
obj-$(CONFIG_ARCH_PRIMA2) += clk-prima2.o
+obj-$(CONFIG_ARCH_MVEBU) += mvebu/
ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_ARCH_MMP) += mmp/
endif
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
new file mode 100644
index 000..de94a87
--- /dev/null
+++ b/drivers/clk/mvebu/Makefile
@@ -0,0 +1,2 @@
