[linux-sunxi] Re: [PATCH 2/4] ARM: sun8i: h3/h5: add DE2 CCU device node for H3

2017-10-27 Thread icenowy 

在 2017-09-11 23:55，Icenowy Zheng 写道：

The DE2 in H3/H5 has a clock control unit in it, and the behavior is
slightly different between H3 and H5.

Add the common parts in H3/H5 DTSI, and add the compatible string in H3
DTSI.

The compatible string of H5 DE2 CCU will be added in a separated patch.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/boot/dts/sun8i-h3.dtsi|  4 
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 14 ++
 2 files changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi 
b/arch/arm/boot/dts/sun8i-h3.dtsi

index b36f9f423c39..a8a1db79f362 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -85,6 +85,10 @@
compatible = "allwinner,sun8i-h3-ccu";
 };

+_clocks {
+   compatible = "allwinner,sun8i-a83t-de2-clk";


Sorry, this compatible is wrong.

Please wait for my new version of this patchset to add a
allwinner,sun8i-h3-de2-clk and use it.

(A83T doesn't have DE mod clk, but H3 has)


+};
+
  {
compatible = "allwinner,sun7i-a20-mmc";
clocks = < CLK_BUS_MMC0>,
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 11240a8313c2..76a4cbc99bdb 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -40,9 +40,11 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */

+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 

@@ -85,6 +87,18 @@
#size-cells = <1>;
ranges;

+   display_clocks: clock@100 {
+   /* compatible is in per SoC .dtsi file */
+   reg = <0x0100 0x10>;
+   clocks = < CLK_DE>,
+< CLK_BUS_DE>;
+   clock-names = "mod",
+ "bus";
+   resets = < RST_BUS_DE>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-h3-system-controller",
"syscon";


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[linux-sunxi] Re: [Buildroot] [PATCH v3 02/11] support/scripts: Add sunxi64-post-build.sh

2017-10-27 Thread Jagan Teki 
On Fri, Oct 27, 2017 at 2:02 AM, André Przywara  wrote:
> On 26/10/17 19:13, Jagan Teki wrote:
>> On Thu, Oct 26, 2017 at 4:50 PM, Jagan Teki  
>> wrote:
>>> On Sun, Oct 22, 2017 at 5:59 PM, Thomas Petazzoni
>>>  wrote:
 Hello,

 On Sun, 22 Oct 2017 12:05:52 +0100, André Przywara wrote:

>> This wasn't only the case with sunxi it's been the U-Boot FIT
>> behaviour..even rockchip do follow same build process.
>>
>> Ideally FIT need input files to produce blob like dtb.
>>
>> Added Andre he will give some more insight.
>
> So yes, ATF supports *multiple* ways of integration:
> - On the Juno it has the capability of loading images - from NOR flash,
> so not a big deal. This means the BL1 and BL2 stages read the BL31
> (containing the PSCI runtime) and BL33 (U-Boot or EDK2), also this uses
> the ATF defined FIP image format.
> - For other platforms (like rockchip or sunxi) we usually load from MMC
> or SPI flash. So using the traditional ATF approach would mean to have
> MMC and SPI drivers in the early ATF stages, also do the DRAM
> initialization there. Since ATF is BSD licensed, it's more involved than
> just copying some code from U-Boot.
> So the pragmatic approach - which ATF actually embraces - is to just use
> a subset of the whole ATF (BL31) and do the rest via some platform
> specific firmware: which is U-Boot's SPL in our case, since it already
> has support for this hardware. Other platform (most ARM64 servers) tend
> to have their proprietary early-init firmware there.

 Thanks for summarizing the context.

> So I virtually know nothing about buildroot, but it might not be a good
> idea to shoehorn the second approach into the Juno ATF build scheme.
> As I believe that in fact more platforms use the second approach, it
> might be worthwhile to introduce some extra code in buildroot to support
> that specifically instead of working around the Juno ATF way.
> Maybe it can be modelled as some U-Boot FIT build process with an
> additional requirement, similar to a binary blob?

 And this is exactly what I was suggesting Jagan to do: extend Buildroot
 so that it covers the U-Boot-bundles-ATF scenario (sunxi/rockchip,
 etc.) in addition to the already supported ATF-bundles-U-Boot scenario
 (Juno).
>>>
>>> Based on the ATF build this look not an exact U-Boot-bundles-ATF
>>> scenario. Whether for Juno(ATF-bundles-U-Boot scenario) or for SUNXI,
>>> ATF want a dependence to build U-Boot first atleast for FIP point.
>>>
>>> ARM_TRUSTED_FIRMWARE_MAKE_OPTS += \
>>> CROSS_COMPILE="$(TARGET_CROSS)" \
>>> BL33=$(BINARIES_DIR)/u-boot.bin \
>>>
>>> Here BL33 need u-boot.bin to export for building FIP in default that
>>> could be the reason of making ARM_TRUSTED_FIRMWARE_DEPENDENCIES +=
>>> uboot
>>> in atf.
>>>
>>> I tried to build for U-Boot-bundles-ATF scenario by not to dependent
>>> U-Boot so that U-boot build later. Since at this movement there is no
>>> U-Boot build, ATF is unable to get the BL33, I don't know whether this
>>> BL33 is needed for all because I'm trying for BL31.
>>>
>>> Build Log:
>>> -
>>> un50iw1p1 all fip
>>> make[1]: Entering directory
>>> `/mnt/jagan/buildroot/buildroot-sun32/output/build/arm-trusted-firmware-aa75c8da415158a94b82a430b2b4778e851f'
>>> make[1]: Nothing to be done for `bl31'.
>>> make[1]: *** No rule to make target
>>> `/mnt/jagan/buildroot/buildroot-sun32/output/images/u-boot.bin',
>>> needed by `build/sun50iw1p1/release/fip.bin'.  Stop.
>>> make[1]: *** Waiting for unfinished jobs
>>> Building sun50iw1p1
>
> Why do build a fip then?
> Please read board/sunxi/README.sunxi in the U-Boot sources, it tells you
> how to build ATF: namely using the "bl31" target, and not "all fip" as
> for the Juno, for instance.

Yes, ie what I founded out. Currently buildroot is doing 'all fip',
I've fixed and patches in ML.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.

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[linux-sunxi] [PATCH v2 00/10] Allwinner H3/H5/A64(DE2) SimpleFB support

2017-10-27 Thread Icenowy Zheng 
This patchset adds support for the SimpleFB on Allwinner SoCs with
"Display Engine 2.0".

PATCH 1 to PATCH 3 are DE2 CCU fixes for H3/H5 SoCs.

PATCH 4 adds the pipeline strings for DE2 SimpleFB.

PATCH 5 to 7 adds necessary device tree nodes (DE2 CCU and SimpleFB)
for H3/H5 SoCs.

PATCH 8 to 10 are for Allwinner A64 SoC to enable SimpleFB.

Icenowy Zheng (10):
  dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
  clk: sunxi-ng: add support for Allwinner H3 DE2 CCU
  clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU
  dt-bindings: simplefb-sunxi: add pipelines for DE2
  ARM: sun8i: h3/h5: add DE2 CCU device node for H3
  arm64: allwinner: h5: add compatible string for DE2 CCU
  ARM: sunxi: h3/h5: add simplefb nodes
  dt-bindings: add binding for A64 DE2 CCU SRAM
  arm64: allwinner: a64: add DE2 CCU for A64 SoC
  arm64: allwinner: a64: add simplefb for A64 SoC

 .../devicetree/bindings/clock/sun8i-de2.txt| 10 +++-
 .../bindings/display/simple-framebuffer-sunxi.txt  |  4 ++
 arch/arm/boot/dts/sun8i-h3.dtsi|  4 ++
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 43 ++
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi  | 65 ++
 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi   |  4 ++
 drivers/clk/sunxi-ng/ccu-sun8i-de2.c   | 53 +-
 7 files changed, 178 insertions(+), 5 deletions(-)

-- 
2.13.6

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[linux-sunxi] Re: [PATCH 1/2] dt-bindings: add binding for A64 DE2 CCU with SRAM section

2017-10-27 Thread icenowy 

在 2017-10-16 20:09，Maxime Ripard 写道：

On Mon, Oct 16, 2017 at 05:41:10PM +0800, icen...@aosc.io wrote:

在 2017-10-16 17:11，Maxime Ripard 写道：
> On Sat, Oct 14, 2017 at 08:29:24PM +0800, Icenowy Zheng wrote:
> > A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be
> > claimed.
>
> Why?

Allwinner didn't document this, but if the SRAM is not claimed, the
DE2 MMIO zone is totally not accessible.


Not accessible how? It generates an abort when you access it? It
returns 0?


It seems that Allwinner uses the SRAM C in the DE2 internally.


Then shouldn't it be tied to all the DE2 devices then? So mixers
too. Either way, this should be mentionned in your commit logs. How
you're fixing things is much less interesting than why you're doing
them. You can tell how you're doing them from your code already.


Yes I checked and when the SRAM is not claimed any part in DE2 memory
zone can't be accessed.

Should I also add the code that claims the SRAM in the mixer code? Or
just place the device tree property is enough? (As the mixers depend
on the DE2 CCU) Or just ignore this?



Maxime

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[linux-sunxi] [PATCH v2 10/10] arm64: allwinner: a64: add simplefb for A64 SoC

2017-10-27 Thread Icenowy Zheng 
The A64 SoC features two display pipelines, one has a LCD output, the
other has a HDMI output.

Add support for simplefb for these pipelines on A64 SoC.

Signed-off-by: Icenowy Zheng 
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi 
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 03a46da0f0fa..65ffd94441a1 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -42,9 +42,11 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 
 / {
@@ -52,6 +54,35 @@
#address-cells = <1>;
#size-cells = <1>;
 
+   chosen {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   framebuffer-lcd {
+   compatible = "allwinner,simple-framebuffer",
+"simple-framebuffer";
+   allwinner,pipeline = "mixer0-lcd0";
+   clocks = <_clocks CLK_BUS_MIXER0>,
+< CLK_BUS_TCON0>, < CLK_BUS_TCON0>,
+<_clocks CLK_MIXER0>,
+< CLK_TCON0>;
+   status = "disabled";
+   };
+
+   framebuffer-hdmi {
+   compatible = "allwinner,simple-framebuffer",
+"simple-framebuffer";
+   allwinner,pipeline = "mixer1-lcd1-hdmi";
+   clocks = <_clocks CLK_BUS_MIXER1>,
+< CLK_BUS_TCON1>, < CLK_BUS_HDMI>,
+<_clocks CLK_MIXER1>,
+< CLK_TCON1>, < CLK_HDMI>,
+< CLK_HDMI_DDC>;
+   status = "disabled";
+   };
+   };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
-- 
2.13.6

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[linux-sunxi] [PATCH v2 09/10] arm64: allwinner: a64: add DE2 CCU for A64 SoC

2017-10-27 Thread Icenowy Zheng 
The A64 SoC features a DE2 CCU like the one in H5, but needs to claim a
section of SRAM (SRAM C) to be accessed.

Adds the device tree nodes for the SRAM controller and the DE2 CCU.

Signed-off-by: Icenowy Zheng 
---
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 34 +++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi 
b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 062040ec2fed..03a46da0f0fa 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -130,6 +130,40 @@
#size-cells = <1>;
ranges;
 
+   display_clocks: clock@100 {
+   compatible = "allwinner,sun50i-a64-de2-clk";
+   reg = <0x0100 0x10>;
+   clocks = < CLK_DE>,
+< CLK_BUS_DE>;
+   clock-names = "mod",
+ "bus";
+   resets = < RST_BUS_DE>;
+   allwinner,sram = <_sram>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
+   sram-controller@1c0 {
+   compatible = "allwinner,sun50i-a64-sram-controller";
+   reg = <0x01c0 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   sram_c: sram@18000 {
+   compatible = "mmio-sram";
+   reg = <0x00018000 0x28000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0x00018000 0x28000>;
+
+   de2_sram: sram-section@0 {
+   compatible = 
"allwinner,sun50i-a64-sram-c";
+   reg = <0x 0x28000>;
+   };
+   };
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun50i-a64-system-controller",
"syscon";
-- 
2.13.6

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[linux-sunxi] [PATCH v2 01/10] dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3

2017-10-27 Thread Icenowy Zheng 
The DE2 CCU is different on A83T and H3 -- the parent of the clocks on
A83T is PLL_DE but on H3 it's the DE module clock. This is not noticed
when I develop the DE2 CCU driver.

Fix the binding by using different compatibles for A83T and H3, adding
notes for the PLL_DE usage on A83T, and change the binding example's
compatible from A83T to H3 (as it specifies the DE module clock).

Fixes: ed74f8a8a679 ("dt-bindings: add binding for the Allwinner DE2 CCU")
Signed-off-by: Icenowy Zheng 
---
 Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt 
b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
index 631d27cd89d6..f2fa87c4765c 100644
--- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
@@ -4,13 +4,14 @@ Allwinner Display Engine 2.0 Clock Control Binding
 Required properties :
 - compatible: must contain one of the following compatibles:
- "allwinner,sun8i-a83t-de2-clk"
+   - "allwinner,sun8i-h3-de2-clk"
- "allwinner,sun8i-v3s-de2-clk"
- "allwinner,sun50i-h5-de2-clk"
 
 - reg: Must contain the registers base address and length
 - clocks: phandle to the clocks feeding the display engine subsystem.
  Three are needed:
-  - "mod": the display engine module clock
+  - "mod": the display engine module clock (on A83T it's the DE PLL)
   - "bus": the bus clock for the whole display engine subsystem
 - clock-names: Must contain the clock names described just above
 - resets: phandle to the reset control for the display engine subsystem.
@@ -19,7 +20,7 @@ Required properties :
 
 Example:
 de2_clocks: clock@100 {
-   compatible = "allwinner,sun8i-a83t-de2-clk";
+   compatible = "allwinner,sun8i-h3-de2-clk";
reg = <0x0100 0x10>;
clocks = < CLK_BUS_DE>,
 < CLK_DE>;
-- 
2.13.6

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[linux-sunxi] [PATCH v2 02/10] clk: sunxi-ng: add support for Allwinner H3 DE2 CCU

2017-10-27 Thread Icenowy Zheng 
Allwinner H3 features a DE2 CCU like the one on A83T, however the
parent of the clocks is the DE module clock, not the PLL_DE clock.

Add support for it.

Signed-off-by: Icenowy Zheng 
---
 drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 47 
 1 file changed, 47 insertions(+)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 5cc9d9952121..2db5d4e00ea7 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -41,6 +41,8 @@ static SUNXI_CCU_GATE(wb_clk, "wb",   
"wb-div",
 
 static SUNXI_CCU_M(mixer0_div_clk, "mixer0-div", "de", 0x0c, 0, 4,
   CLK_SET_RATE_PARENT);
+static SUNXI_CCU_M(mixer1_div_clk, "mixer1-div", "de", 0x0c, 4, 4,
+  CLK_SET_RATE_PARENT);
 static SUNXI_CCU_M(wb_div_clk, "wb-div", "de", 0x0c, 8, 4,
   CLK_SET_RATE_PARENT);
 
@@ -65,6 +67,20 @@ static struct ccu_common *sun8i_a83t_de2_clks[] = {
_div_a83_clk.common,
 };
 
+static struct ccu_common *sun8i_h3_de2_clks[] = {
+   _clk.common,
+   _clk.common,
+   _clk.common,
+
+   _mixer0_clk.common,
+   _mixer1_clk.common,
+   _wb_clk.common,
+
+   _div_clk.common,
+   _div_clk.common,
+   _div_clk.common,
+};
+
 static struct ccu_common *sun8i_v3s_de2_clks[] = {
_clk.common,
_clk.common,
@@ -93,6 +109,23 @@ static struct clk_hw_onecell_data sun8i_a83t_de2_hw_clks = {
.num= CLK_NUMBER,
 };
 
+static struct clk_hw_onecell_data sun8i_h3_de2_hw_clks = {
+   .hws= {
+   [CLK_MIXER0]= _clk.common.hw,
+   [CLK_MIXER1]= _clk.common.hw,
+   [CLK_WB]= _clk.common.hw,
+
+   [CLK_BUS_MIXER0]= _mixer0_clk.common.hw,
+   [CLK_BUS_MIXER1]= _mixer1_clk.common.hw,
+   [CLK_BUS_WB]= _wb_clk.common.hw,
+
+   [CLK_MIXER0_DIV]= _div_clk.common.hw,
+   [CLK_MIXER1_DIV]= _div_clk.common.hw,
+   [CLK_WB_DIV]= _div_clk.common.hw,
+   },
+   .num= CLK_NUMBER,
+};
+
 static struct clk_hw_onecell_data sun8i_v3s_de2_hw_clks = {
.hws= {
[CLK_MIXER0]= _clk.common.hw,
@@ -133,6 +166,16 @@ static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc 
= {
.num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
 };
 
+static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
+   .ccu_clks   = sun8i_h3_de2_clks,
+   .num_ccu_clks   = ARRAY_SIZE(sun8i_h3_de2_clks),
+
+   .hw_clks= _h3_de2_hw_clks,
+
+   .resets = sun8i_a83t_de2_resets,
+   .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+};
+
 static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
.ccu_clks   = sun8i_a83t_de2_clks,
.num_ccu_clks   = ARRAY_SIZE(sun8i_a83t_de2_clks),
@@ -238,6 +281,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
.data = _a83t_de2_clk_desc,
},
{
+   .compatible = "allwinner,sun8i-h3-de2-clk",
+   .data = _h3_de2_clk_desc,
+   },
+   {
.compatible = "allwinner,sun8i-v3s-de2-clk",
.data = _v3s_de2_clk_desc,
},
-- 
2.13.6

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[linux-sunxi] [PATCH v2 03/10] clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU

2017-10-27 Thread Icenowy Zheng 
The clocks of A64/H5 SoCs in the DE2 CCU is the same as the clocks in H3
DE2 CCU rather than the A83T DE2 CCU (the parent of them is the DE
module clock).

Fix this by change the clock descriptions to use the clocks of H3.

Fixes: 763c5bd045b1 ("clk: sunxi-ng: add support for DE2 CCU")
Signed-off-by: Icenowy Zheng 
---
 drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c 
b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 2db5d4e00ea7..468d1abaf0ee 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -177,10 +177,10 @@ static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc 
= {
 };
 
 static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
-   .ccu_clks   = sun8i_a83t_de2_clks,
-   .num_ccu_clks   = ARRAY_SIZE(sun8i_a83t_de2_clks),
+   .ccu_clks   = sun8i_h3_de2_clks,
+   .num_ccu_clks   = ARRAY_SIZE(sun8i_h3_de2_clks),
 
-   .hw_clks= _a83t_de2_hw_clks,
+   .hw_clks= _h3_de2_hw_clks,
 
.resets = sun50i_a64_de2_resets,
.num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
-- 
2.13.6

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[linux-sunxi] Re: [PATCH 1/2] dt-bindings: add binding for A64 DE2 CCU with SRAM section

2017-10-27 Thread Maxime Ripard 
On Fri, Oct 27, 2017 at 10:33:29PM +0800, icen...@aosc.io wrote:
> 在 2017-10-16 20:09，Maxime Ripard 写道：
> > On Mon, Oct 16, 2017 at 05:41:10PM +0800, icen...@aosc.io wrote:
> > > 在 2017-10-16 17:11，Maxime Ripard 写道：
> > > > On Sat, Oct 14, 2017 at 08:29:24PM +0800, Icenowy Zheng wrote:
> > > > > A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be
> > > > > claimed.
> > > >
> > > > Why?
> > > 
> > > Allwinner didn't document this, but if the SRAM is not claimed, the
> > > DE2 MMIO zone is totally not accessible.
> > 
> > Not accessible how? It generates an abort when you access it? It
> > returns 0?
> > 
> > > It seems that Allwinner uses the SRAM C in the DE2 internally.
> > 
> > Then shouldn't it be tied to all the DE2 devices then? So mixers
> > too. Either way, this should be mentionned in your commit logs. How
> > you're fixing things is much less interesting than why you're doing
> > them. You can tell how you're doing them from your code already.
> 
> Yes I checked and when the SRAM is not claimed any part in DE2 memory
> zone can't be accessed.

Then all the nodes that depend on it should have it, and the bindings
should be modified appropriately.

Maxime

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[linux-sunxi] [PATCH v2 05/10] ARM: sun8i: h3/h5: add DE2 CCU device node for H3

2017-10-27 Thread Icenowy Zheng 
The DE2 in H3/H5 has a clock control unit in it, and the behavior is
slightly different between H3 and H5.

Add the common parts in H3/H5 DTSI, and add the compatible string in H3
DTSI.

The compatible string of H5 DE2 CCU will be added in a separated patch.

Signed-off-by: Icenowy Zheng 
---
Changes in v2:
- Use H3 DE2 CCU compatible as it's discovered that H3 and A83T DE2 CCU are
  not equal.

 arch/arm/boot/dts/sun8i-h3.dtsi|  4 
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 14 ++
 2 files changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b36f9f423c39..8495deecedad 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -85,6 +85,10 @@
compatible = "allwinner,sun8i-h3-ccu";
 };
 
+_clocks {
+   compatible = "allwinner,sun8i-h3-de2-clk";
+};
+
  {
compatible = "allwinner,sun7i-a20-mmc";
clocks = < CLK_BUS_MMC0>,
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi 
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index d7a71e726a9f..367319d22116 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -40,9 +40,11 @@
  * OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -85,6 +87,18 @@
#size-cells = <1>;
ranges;
 
+   display_clocks: clock@100 {
+   /* compatible is in per SoC .dtsi file */
+   reg = <0x0100 0x10>;
+   clocks = < CLK_DE>,
+< CLK_BUS_DE>;
+   clock-names = "mod",
+ "bus";
+   resets = < RST_BUS_DE>;
+   #clock-cells = <1>;
+   #reset-cells = <1>;
+   };
+
syscon: syscon@1c0 {
compatible = "allwinner,sun8i-h3-system-controller",
"syscon";
-- 
2.13.6

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[linux-sunxi] [PATCH v2 06/10] arm64: allwinner: h5: add compatible string for DE2 CCU

2017-10-27 Thread Icenowy Zheng 
The DE2 CCU on Allwinner H5 SoC has a slightly different behavior than
the one on H3, so the compatible string is not set in the common DTSI
file.

Add the compatible string of H5 DE2 CCU in H5 DTSI file.

Signed-off-by: Icenowy Zheng 
---
 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi 
b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
index d9a720bff05d..e237c05cfdb4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
@@ -98,6 +98,10 @@
compatible = "allwinner,sun50i-h5-ccu";
 };
 
+_clocks {
+   compatible = "allwinner,sun50i-h5-de2-clk";
+};
+
  {
compatible = "allwinner,sun50i-h5-mmc",
 "allwinner,sun50i-a64-mmc";
-- 
2.13.6

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[linux-sunxi] [PATCH v2 08/10] dt-bindings: add binding for A64 DE2 CCU SRAM

2017-10-27 Thread Icenowy Zheng 
A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed,
otherwise the whole DE2 memory zone cannot be accessed (kept to all 0).

Add binding for this, in order to make the DE2 CCU able to claim the
SRAM and enable access to the DE2 clock and reset registers.

Signed-off-by: Icenowy Zheng 
---
Changes in v2:
- Adds description of the situation when the SRAM is not claimed.

 Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt 
b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
index f2fa87c4765c..a7d558a2b9b2 100644
--- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
@@ -6,6 +6,7 @@ Required properties :
- "allwinner,sun8i-a83t-de2-clk"
- "allwinner,sun8i-h3-de2-clk"
- "allwinner,sun8i-v3s-de2-clk"
+   - "allwinner,sun50i-a64-de2-clk"
- "allwinner,sun50i-h5-de2-clk"
 
 - reg: Must contain the registers base address and length
@@ -18,6 +19,10 @@ Required properties :
 - #clock-cells : must contain 1
 - #reset-cells : must contain 1
 
+Additional required properties for "allwinner,sun50i-a64-de2-clk" :
+- allwinner,sram: See Documentation/devicetree/bindings/sram/sunxi-sram.txt,
+ should be the SRAM C section on A64 SoC.
+
 Example:
 de2_clocks: clock@100 {
compatible = "allwinner,sun8i-h3-de2-clk";
-- 
2.13.6

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[linux-sunxi] [PATCH v2 07/10] ARM: sunxi: h3/h5: add simplefb nodes

2017-10-27 Thread Icenowy Zheng 
The H3/H5 SoCs have a HDMI output and a TV Composite output.

Add simplefb nodes for these outputs.

Signed-off-by: Icenowy Zheng 
---
 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 29 +
 1 file changed, 29 insertions(+)

diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi 
b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 367319d22116..2ce0c3bb9896 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -53,6 +53,35 @@
#address-cells = <1>;
#size-cells = <1>;
 
+   chosen {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   framebuffer-hdmi {
+   compatible = "allwinner,simple-framebuffer",
+"simple-framebuffer";
+   allwinner,pipeline = "mixer0-lcd0-hdmi";
+   clocks = <_clocks CLK_BUS_MIXER0>,
+< CLK_BUS_TCON0>, < CLK_BUS_HDMI>,
+<_clocks CLK_MIXER0>,
+< CLK_TCON0>, < CLK_HDMI>,
+< CLK_HDMI_DDC>;
+   status = "disabled";
+   };
+
+   framebuffer-tve {
+   compatible = "allwinner,simple-framebuffer",
+"simple-framebuffer";
+   allwinner,pipeline = "mixer1-lcd1-tve";
+   clocks = <_clocks CLK_BUS_MIXER1>,
+< CLK_BUS_TCON1>, < CLK_BUS_TVE>,
+<_clocks CLK_MIXER1>,
+< CLK_TVE>;
+   status = "disabled";
+   };
+   };
+
clocks {
#address-cells = <1>;
#size-cells = <1>;
-- 
2.13.6

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[linux-sunxi] Re: [PATCH 1/2] ARM: dts: sun8i: h3-h5: Move pinctrl of mmc0 from dts to dtsi

2017-10-27 Thread Maxime Ripard 
Hi,

On Thu, Oct 26, 2017 at 02:57:00PM +, Joonas Kylmälä wrote:
> Maxime Ripard:
> > On Sun, Oct 22, 2017 at 12:19:56PM +0300, Joonas Kylmälä wrote:
> >> Most of the boards use the mmc0 pins and their attributes defined in
> >> mmc0_pins_a and mmc0_cd_pin. Let's default to those by moving the
> >> pinctrl attributes to the dtsi file. This makes it easier to modify
> >> device trees in the future as there is only one place to change the
> >> pinctrl attributes.
> >>
> >> As a side effect this patch also adds the detect pin of Orange Pi
> >> Zero's mmc0 under pinctrl as it should have been there right from the
> >> beginning.
> > 
> > We're actually in the process of removing those gpio pinctrl
> > nodes. Could you make that while you're at it?
> 
> Sure. We are assuming that the bootloader will do the pin
> configuration?

No, Linux will actually do it as part of the gpio(d)_request call, so
the pinctrl node is actually redundant. And it prevents us from
enabling stricter checks to make sure that someone isn't going to
"steal" our pin by requesting a GPIO on a !GPIO line (or the other way
around). This is something that is allowed at the moment, and it
really shouldn't be.

Thanks!
Maxime

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