Re: [PATCH net-next 0/3] sctp: add support for sk_reuseport
On Sun, Oct 21, 2018 at 12:43:35PM +0800, Xin Long wrote: > sctp sk_reuseport allows multiple socks to listen on the same port and > addresses, as long as these socks have the same uid. This works pretty > much as TCP/UDP does, the only difference is that sctp is multi-homing > and all the bind_addrs in these socks will have to completely matched, > otherwise listen() will return err. > > The below is when 5 sockets are listening on 172.16.254.254:6400 on a > server, 26 sockets on a client connect to 172.16.254.254:6400 and each > may be processed by a different socket on the server which is selected > by hash(lport, pport, paddr) in reuseport_select_sock(): > > # ss --sctp -nn >State Recv-Q Send-QLocal Address:Port Peer Address:Port >LISTEN 0 10 172.16.254.254:6400*:* >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.2.1:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.2.4:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.3.3:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.3.4:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.5.2:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.5.3:1234 >LISTEN 0 10 172.16.254.254:6400*:* >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.1.3:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.1.4:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.3.2:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.4.1:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.4.2:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.4.3:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.4.4:1234 >LISTEN 0 10 172.16.254.254:6400*:* >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.1.2:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.3.5:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.4.5:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.253.253:1234 >LISTEN 0 10 172.16.254.254:6400*:* >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.2.2:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.2.3:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.5.4:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.5.5:1234 >LISTEN 0 10 172.16.254.254:6400*:* >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.1.1:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.1.5:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.2.5:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.3.1:1234 >`- ESTAB 0 0 172.16.254.254%eth1:6400 172.16.5.1:1234 > > Xin Long (3): > sctp: do reuseport_select_sock in __sctp_rcv_lookup_endpoint > sctp: add sock_reuseport for the sock in __sctp_hash_endpoint > sctp: process sk_reuseport in sctp_get_port_local > > include/net/sctp/sctp.h| 2 +- > include/net/sctp/structs.h | 6 ++- > net/core/sock_reuseport.c | 1 + > net/sctp/bind_addr.c | 28 ++ > net/sctp/input.c | 129 > - > net/sctp/socket.c | 49 +++-- > 6 files changed, 162 insertions(+), 53 deletions(-) > > -- > 2.1.0 > > Series Acked-by: Neil Horman
Re: [PATCH net-next 2/4] net: phy-c45: Populate autoneg_done callback
On Mon, Oct 22, 2018 at 11:32:47AM +0100, Jose Abreu wrote:
> We already have this callback implemented. Use it in driver structure.
>
> Signed-off-by: Jose Abreu
> Cc: Andrew Lunn
> Cc: Florian Fainelli
> Cc: "David S. Miller"
> Cc: Joao Pinto
> ---
> drivers/net/phy/phy-c45.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/net/phy/phy-c45.c b/drivers/net/phy/phy-c45.c
> index e1225545362d..c0135217b81f 100644
> --- a/drivers/net/phy/phy-c45.c
> +++ b/drivers/net/phy/phy-c45.c
> @@ -330,6 +330,7 @@ struct phy_driver genphy_10g_driver = {
> .soft_reset = gen10g_no_soft_reset,
> .config_init= gen10g_config_init,
> .features = 0,
> + .aneg_done = genphy_c45_aneg_done,
> .config_aneg= gen10g_config_aneg,
> .read_status= gen10g_read_status,
> .suspend= gen10g_suspend,
We should probably do something about the naming. I need to look at
the history to understand why we have gen10g_ and genphy_c45_.
Andrew
Re: [PATCH net-next 3/4] net: phy-c45: Implement reset/suspend/resume callbacks
Hello,
On 22-10-2018 13:28, Andrew Lunn wrote:
>> EXPORT_SYMBOL_GPL(gen10g_resume);
>> @@ -327,7 +381,7 @@ struct phy_driver genphy_10g_driver = {
>> .phy_id = 0x,
>> .phy_id_mask= 0x,
>> .name = "Generic 10G PHY",
>> -.soft_reset = gen10g_no_soft_reset,
>> +.soft_reset = gen10g_soft_reset,
>> .config_init= gen10g_config_init,
>> .features = 0,
>> .aneg_done = genphy_c45_aneg_done,
> Hi Jose
>
> You need to be careful here. There is a reason this is called
> gen10g_no_soft_reset, rather than having an empty
> gen10g_soft_reset. Some PHYs break when you do a reset. So adding a
> gen10g_soft_reset is fine, but don't change this here, without first
> understanding the history, and talking to Russell King.
Hmm, the reset function only interacts with standard PCS
registers, which should always be available ...
>From my tests I need to do at least 1 reset during power-up so in
ultimate case I can add a feature quirk or similar.
Russell, can you please comment ?
Thanks and Best Regards,
Jose Miguel Abreu
>
> Andrew
[PATCH net-next] tls: Add maintainers
Add John and Daniel as additional tls co-maintainers to help review patches and fix syzbot reports. Acked-by: John Fastabend Acked-by: Daniel Borkmann Signed-off-by: Dave Watson --- MAINTAINERS | 2 ++ 1 file changed, 2 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7f1399ac028e..4265dacab7d7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10223,6 +10223,8 @@ NETWORKING [TLS] M: Boris Pismenny M: Aviad Yehezkel M: Dave Watson +M: John Fastabend +M: Daniel Borkmann L: netdev@vger.kernel.org S: Maintained F: net/tls/* -- 2.17.1
RE: [Intel-wired-lan] [PATCH] ixgbe: allow IPsec Tx offload in VEPA mode
> -Original Message-
> From: Intel-wired-lan [mailto:intel-wired-lan-boun...@osuosl.org] On
> Behalf Of Shannon Nelson
> Sent: Thursday, October 4, 2018 4:29 PM
> To: intel-wired-...@lists.osuosl.org; Kirsher, Jeffrey T
>
> Cc: netdev@vger.kernel.org
> Subject: [Intel-wired-lan] [PATCH] ixgbe: allow IPsec Tx offload in VEPA
> mode
>
> When it's possible that the PF might end up trying to send a packet to one of
> its own VFs, we have to forbid IPsec offload because the device drops the
> packets into a black hole.
> See commit 47b6f50077e6 ("ixgbe: disallow IPsec Tx offload when in SR-IOV
> mode") for more info.
>
> This really is only necessary when the device is in the default VEB mode. If
> instead the device is running in VEPA mode, the packets will go through the
> encryption engine and out the MAC/PHY as normal, and get "hairpinned" as
> needed by the switch.
>
> So let's not block IPsec offload when in VEPA mode. To get there with the
> ixgbe device, use the handy 'bridge' command:
> bridge link set dev eth1 hwmode vepa
>
> Signed-off-by: Shannon Nelson
> ---
> drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
Tested-by: Andrew Bowers
Re: [iproute PATCH] tc: htb: Print default value in hex
On Fri, 19 Oct 2018 17:42:55 +0200
Phil Sutter wrote:
> Value of 'default' is assumed to be hexadecimal when parsing, so
> consequently it should be printed in hex as well. This is a regression
> introduced when adding JSON output.
>
> Fixes: f354fa6aa5ff0 ("tc: jsonify htb qdisc")
> Signed-off-by: Phil Sutter
> ---
> tc/q_htb.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/tc/q_htb.c b/tc/q_htb.c
> index c8b2941d945b7..c69485db8ef7d 100644
> --- a/tc/q_htb.c
> +++ b/tc/q_htb.c
> @@ -332,7 +332,7 @@ static int htb_print_opt(struct qdisc_util *qu, FILE *f,
> struct rtattr *opt)
> if (RTA_PAYLOAD(tb[TCA_HTB_INIT]) < sizeof(*gopt)) return -1;
>
> print_int(PRINT_ANY, "r2q", "r2q %d", gopt->rate2quantum);
> - print_uint(PRINT_ANY, "default", " default %u", gopt->defcls);
> + print_uint(PRINT_ANY, "default", " default %x", gopt->defcls);
> print_uint(PRINT_ANY, "direct_packets_stat",
> " direct_packets_stat %u", gopt->direct_pkts);
> if (show_details) {
The output should be in hex. Because you used print_uint it will still be in
decimal
in the JSON output. The correct fix here is to use print_0xhex instead.
Please fix that, test it, and resubmit.
Re: [iproute PATCH] ip-route: Fix parse_encap_seg6() srh parsing
On Thu, 18 Oct 2018 15:44:14 +0200
Phil Sutter wrote:
> In case caller did not specify 'segs' parameter, parse_srh() would read
> garbage while iterating over 'segbuf'. Avoid this by initializing
> 'segbuf' to an empty string.
>
> Fixes: e8493916a8ede ("iproute: add support for SR-IPv6 lwtunnel
> encapsulation")
> Signed-off-by: Phil Sutter
Applied
Re: [PATCH v2 1/2] dt-bindings: net: add MDIO bus multiplexer driven by a regmap device
On 10/21/18 9:22 PM, Pankaj Bansal wrote: > >> -Original Message- >> From: Pankaj Bansal >> Sent: Thursday, October 18, 2018 10:00 AM >> To: Florian Fainelli ; Andrew Lunn >> Cc: netdev@vger.kernel.org >> Subject: RE: [PATCH v2 1/2] dt-bindings: net: add MDIO bus multiplexer >> driven by >> a regmap device >> >> Hi Florian >> >>> -Original Message- >>> From: Florian Fainelli [mailto:f.faine...@gmail.com] >>> Sent: Sunday, October 7, 2018 11:32 PM >>> To: Pankaj Bansal ; Andrew Lunn >>> >>> Cc: netdev@vger.kernel.org >>> Subject: Re: [PATCH v2 1/2] dt-bindings: net: add MDIO bus multiplexer >>> driven by a regmap device >>> >>> >>> >>> On 10/07/18 11:24, Pankaj Bansal wrote: Add support for an MDIO bus multiplexer controlled by a regmap device, like an FPGA. Tested on a NXP LX2160AQDS board which uses the "QIXIS" FPGA attached to the i2c bus. Signed-off-by: Pankaj Bansal --- Notes: V2: - Fixed formatting error caused by using space instead of tab - Add newline between property list and subnode - Add newline between two subnodes .../bindings/net/mdio-mux-regmap.txt | 95 ++ 1 file changed, 95 insertions(+) diff --git a/Documentation/devicetree/bindings/net/mdio-mux-regmap.txt b/Documentation/devicetree/bindings/net/mdio-mux-regmap.txt new file mode 100644 index ..88ebac26c1c5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/mdio-mux-regmap.txt @@ -0,0 +1,95 @@ +Properties for an MDIO bus multiplexer controlled by a regmap + +This is a special case of a MDIO bus multiplexer. A regmap device, +like an FPGA, is used to control which child bus is connected. The +mdio-mux node must be a child of the device that is controlled by a >> regmap. +The driver currently only supports devices with upto 32-bit registers. >>> >>> I would omit any sort of details about Linux constructs designed to >>> support specific needs (e.g: regmap) as well as putting driver >>> limitations into a binding document because it really ought to be >>> restricted to >> describing hardware. >>> >> >> Actually the platform driver mdio-mux-regmap.c, is generalization of >> mdio-mux- >> mmioreg.c As such, it doesn't describe any new hardware, so no new properties >> are described by it. >> The only new property is compatible field. >> I don't know how to describe this driver otherwise. Can you please help? > > I further thought about it. mdio-mux-regmap.c is not meant to control a > specific device. > It is meant to control some registers of parent device. Therefore, IMO this > should not be a > Platform driver and there should not be any "compatible" property to which > this driver is associated. > > Rather this driver should expose the APIs, which should be called by parent > devices' driver. Which one is "this driver" in that context? If you already have a driver that FPGA bus/piece of hardware, then that driver itself could be offering the MDIO muxing capabilities directly. You might still want to have some Device Tree representation to properly parent the PHY devices to the branches of the mux. > > What is your thought on this ? > >> + +Required properties in addition to the generic multiplexer properties: + +- compatible : string, must contain "mdio-mux-regmap" + +- reg : integer, contains the offset of the register that controls the bus + multiplexer. it can be 32 bit number. >>> >>> Technically it could be any "reg" property size, the only requirement >>> is that it must be of the appropriate size with respect to what the >>> parent node of this "mdio-mux-regmap" node has, determined by #address- >> cells/#size-cells width. >> >> We are reading only single cell of this property using "of_propert_read_u32". >> That is why I put the size in this. >> >>> + +- mux-mask : integer, contains an 32 bit mask that specifies which + bits in the register control the actual bus multiplexer. The + 'reg' property of each child mdio-mux node must be constrained by + this mask. >>> >>> Same thing here. >> >> We are reading only single cell of this property using "of_propert_read_u32". >> That is why I put the size in this. >> >>> >>> Since this is a MDIO mux, I would invite you to specify what the >>> correct #address-cells/#size-cells values should be (1, and 0 >>> respectively as your example correctly shows). >>> >> >> I will mention #address-cells/#size-cells values >> + +Example: + +The FPGA node defines a i2c connected FPGA with a register space of +0x30 >>> bytes. +For the "EMI2" MDIO bus, register 0x54 (BRDCFG4) controls the mux +on that >>> bus. +A bitmask of 0x07 means that bits 0, 1 and 2 (bit 0 is lsb) are the +bits on +BRDCFG4 that control the actual mux. +
Re: [iproute PATCH] tc: Remove pointless assignments in batch()
On Thu, 18 Oct 2018 15:48:48 +0200
Phil Sutter wrote:
> All these assignments are later overwritten without reading in between,
> so just drop them.
>
> Fixes: 485d0c6001c4a ("tc: Add batchsize feature for filter and actions")
> Signed-off-by: Phil Sutter
Applied
Re: [iproute PATCH] tipc: Drop unused variable 'genl'
On Thu, 18 Oct 2018 15:48:09 +0200
Phil Sutter wrote:
> Although initialized by call to libmnl, the variable is used only in a
> call to sizeof(). Drop it and call sizeof with its type instead.
>
> Fixes: f043759dd4928 ("tipc: add new TIPC configuration tool")
> Signed-off-by: Phil Sutter
Applied
Re: [iproute PATCH] tc: htb: Print default value in hex
On Mon, Oct 22, 2018 at 09:56:23AM -0700, Stephen Hemminger wrote:
> On Fri, 19 Oct 2018 17:42:55 +0200
> Phil Sutter wrote:
>
> > Value of 'default' is assumed to be hexadecimal when parsing, so
> > consequently it should be printed in hex as well. This is a regression
> > introduced when adding JSON output.
> >
> > Fixes: f354fa6aa5ff0 ("tc: jsonify htb qdisc")
> > Signed-off-by: Phil Sutter
> > ---
> > tc/q_htb.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/tc/q_htb.c b/tc/q_htb.c
> > index c8b2941d945b7..c69485db8ef7d 100644
> > --- a/tc/q_htb.c
> > +++ b/tc/q_htb.c
> > @@ -332,7 +332,7 @@ static int htb_print_opt(struct qdisc_util *qu, FILE
> > *f, struct rtattr *opt)
> > if (RTA_PAYLOAD(tb[TCA_HTB_INIT]) < sizeof(*gopt)) return -1;
> >
> > print_int(PRINT_ANY, "r2q", "r2q %d", gopt->rate2quantum);
> > - print_uint(PRINT_ANY, "default", " default %u", gopt->defcls);
> > + print_uint(PRINT_ANY, "default", " default %x", gopt->defcls);
> > print_uint(PRINT_ANY, "direct_packets_stat",
> >" direct_packets_stat %u", gopt->direct_pkts);
> > if (show_details) {
>
> The output should be in hex. Because you used print_uint it will still be in
> decimal
> in the JSON output. The correct fix here is to use print_0xhex instead.
>
> Please fix that, test it, and resubmit.
I did test, but not JSON output. It is not a regression in the latter
because it has been like this since JSON output was added to HTB.
Assuming the output is programmatically parsed, it shouldn't matter too
much as well.
Grepping through the code I found three more cases where print_uint()
was used for data printed in %x. Should I fix those as well?
Thanks, Phil
[PATCH v2 09/17] octeontx2-af: Support for VTAG strip and capture
From: Vamsi Attunuru
Added support for PF/VF drivers to configure NIX to
capture and/or strip VLAN tag from ingress packets.
Signed-off-by: Vamsi Attunuru
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 35 -
drivers/net/ethernet/marvell/octeontx2/af/rvu.h| 3 ++
.../net/ethernet/marvell/octeontx2/af/rvu_nix.c| 59 ++
.../net/ethernet/marvell/octeontx2/af/rvu_struct.h | 5 ++
4 files changed, 101 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index f8efeaa..b60ac9d 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -156,7 +156,8 @@ M(NIX_HWCTX_DISABLE,0x8003, hwctx_disable_req,
msg_rsp) \
M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free_req, msg_rsp)\
M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_config, msg_rsp) \
-M(NIX_STATS_RST, 0x8007, msg_req, msg_rsp)
+M(NIX_STATS_RST, 0x8007, msg_req, msg_rsp) \
+M(NIX_VTAG_CFG,0x8008, nix_vtag_config, msg_rsp)
/* Messages initiated by AF (range 0xC00 - 0xDFF) */
#define MBOX_UP_CGX_MESSAGES \
@@ -462,4 +463,36 @@ struct nix_txschq_config {
u64 regval[MAX_REGS_PER_MBOX_MSG];
};
+struct nix_vtag_config {
+ struct mbox_msghdr hdr;
+ u8 vtag_size;
+ /* cfg_type is '0' for tx vlan cfg
+* cfg_type is '1' for rx vlan cfg
+*/
+ u8 cfg_type;
+ union {
+ /* valid when cfg_type is '0' */
+ struct {
+ /* tx vlan0 tag(C-VLAN) */
+ u64 vlan0;
+ /* tx vlan1 tag(S-VLAN) */
+ u64 vlan1;
+ /* insert tx vlan tag */
+ u8 insert_vlan :1;
+ /* insert tx double vlan tag */
+ u8 double_vlan :1;
+ } tx;
+
+ /* valid when cfg_type is '1' */
+ struct {
+ /* rx vtag type index */
+ u8 vtag_type;
+ /* rx vtag strip */
+ u8 strip_vtag :1;
+ /* rx vtag capture */
+ u8 capture_vtag :1;
+ } rx;
+ };
+};
+
#endif /* MBOX_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index b39400d..1e85e80 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -319,6 +319,9 @@ int rvu_mbox_handler_NIX_TXSCHQ_CFG(struct rvu *rvu,
struct msg_rsp *rsp);
int rvu_mbox_handler_NIX_STATS_RST(struct rvu *rvu, struct msg_req *req,
struct msg_rsp *rsp);
+int rvu_mbox_handler_NIX_VTAG_CFG(struct rvu *rvu,
+ struct nix_vtag_config *req,
+ struct msg_rsp *rsp);
/* NPC APIs */
int rvu_npc_init(struct rvu *rvu);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 8333283..7de5417 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -1143,6 +1143,65 @@ int rvu_mbox_handler_NIX_TXSCHQ_CFG(struct rvu *rvu,
return 0;
}
+static int nix_rx_vtag_cfg(struct rvu *rvu, int nixlf, int blkaddr,
+ struct nix_vtag_config *req)
+{
+ u64 regval = 0;
+
+#define NIX_VTAGTYPE_MAX 0x8ull
+#define NIX_VTAGSIZE_MASK 0x7ull
+#define NIX_VTAGSTRIP_CAP_MASK 0x30ull
+
+ if (req->rx.vtag_type >= NIX_VTAGTYPE_MAX ||
+ req->vtag_size > VTAGSIZE_T8)
+ return -EINVAL;
+
+ regval = rvu_read64(rvu, blkaddr,
+ NIX_AF_LFX_RX_VTAG_TYPEX(nixlf, req->rx.vtag_type));
+
+ if (req->rx.strip_vtag && req->rx.capture_vtag)
+ regval |= BIT_ULL(4) | BIT_ULL(5);
+ else if (req->rx.strip_vtag)
+ regval |= BIT_ULL(4);
+ else
+ regval &= ~(BIT_ULL(4) | BIT_ULL(5));
+
+ regval &= ~NIX_VTAGSIZE_MASK;
+ regval |= req->vtag_size & NIX_VTAGSIZE_MASK;
+
+ rvu_write64(rvu, blkaddr,
+ NIX_AF_LFX_RX_VTAG_TYPEX(nixlf, req->rx.vtag_type), regval);
+ return 0;
+}
+
+int rvu_mbox_handler_NIX_VTAG_CFG(struct rvu *rvu,
+ struct nix_vtag_config *req,
+ struct msg_rsp *rsp)
+{
+ struct rvu_hwinfo *hw = rvu->hw;
+ u16 pcifunc = req->hdr.pcifunc;
+ int blkaddr, nixlf, err;
+
+ blkaddr =
[PATCH v2 07/17] octeontx2-af: Broadcast packet replication support
From: Sunil Goutham
Allocate memory for mcast/bcast/mirror replication entry
contexts, replication buffers (used by HW) and config HW
with corresponding memory bases. Added support for installing
MCEs via NIX AQ mbox.
For now support is restricted to broadcast pkt replication,
hence MCE table size and number of replication buffers
allocated are less. Each CGX LMAC mapped RVU PF is assigned
a MCE table of size 'num VFs of that PF + PF'.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/af/rvu.h| 19 ++
.../net/ethernet/marvell/octeontx2/af/rvu_nix.c| 201 +
2 files changed, 220 insertions(+)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index b3dbbd6..b39400d 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -59,6 +59,20 @@ struct rvu_block {
unsigned char name[NAME_SIZE];
};
+struct nix_mcast {
+ struct qmem *mce_ctx;
+ struct qmem *mcast_buf;
+ int replay_pkind;
+ int next_free_mce;
+ spinlock_t mce_lock; /* Serialize MCE updates */
+};
+
+struct nix_mce_list {
+ struct hlist_head head;
+ int count;
+ int max;
+};
+
/* Structure for per RVU func info ie PF/VF */
struct rvu_pfvf {
boolnpalf; /* Only one NPALF per RVU_FUNC */
@@ -93,6 +107,10 @@ struct rvu_pfvf {
unsigned long *cq_bmap;
u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
+
+ /* Broadcast pkt replication info */
+ u16 bcast_mce_idx;
+ struct nix_mce_list bcast_mce_list;
};
struct nix_txsch {
@@ -108,6 +126,7 @@ struct npc_pkind {
struct nix_hw {
struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
+ struct nix_mcast mcast;
};
struct rvu_hwinfo {
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 4f2528e..947424a 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -16,6 +16,61 @@
#include "rvu.h"
#include "cgx.h"
+enum mc_tbl_sz {
+ MC_TBL_SZ_256,
+ MC_TBL_SZ_512,
+ MC_TBL_SZ_1K,
+ MC_TBL_SZ_2K,
+ MC_TBL_SZ_4K,
+ MC_TBL_SZ_8K,
+ MC_TBL_SZ_16K,
+ MC_TBL_SZ_32K,
+ MC_TBL_SZ_64K,
+};
+
+enum mc_buf_cnt {
+ MC_BUF_CNT_8,
+ MC_BUF_CNT_16,
+ MC_BUF_CNT_32,
+ MC_BUF_CNT_64,
+ MC_BUF_CNT_128,
+ MC_BUF_CNT_256,
+ MC_BUF_CNT_512,
+ MC_BUF_CNT_1024,
+ MC_BUF_CNT_2048,
+};
+
+/* For now considering MC resources needed for broadcast
+ * pkt replication only. i.e 256 HWVFs + 12 PFs.
+ */
+#define MC_TBL_SIZEMC_TBL_SZ_512
+#define MC_BUF_CNT MC_BUF_CNT_128
+
+struct mce {
+ struct hlist_node node;
+ u16 idx;
+ u16 pcifunc;
+};
+
+static void nix_mce_list_init(struct nix_mce_list *list, int max)
+{
+ INIT_HLIST_HEAD(>head);
+ list->count = 0;
+ list->max = max;
+}
+
+static u16 nix_alloc_mce_list(struct nix_mcast *mcast, int count)
+{
+ int idx;
+
+ if (!mcast)
+ return 0;
+
+ idx = mcast->next_free_mce;
+ mcast->next_free_mce += count;
+ return idx;
+}
+
static inline struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr)
{
if (blkaddr == BLKADDR_NIX0 && hw->nix0)
@@ -315,6 +370,19 @@ static int rvu_nix_aq_enq_inst(struct rvu *rvu, struct
nix_aq_enq_req *req,
(req->qidx >= (256UL << (cfg & 0xF
rc = NIX_AF_ERR_AQ_ENQUEUE;
break;
+ case NIX_AQ_CTYPE_MCE:
+ cfg = rvu_read64(rvu, blkaddr, NIX_AF_RX_MCAST_CFG);
+ /* Check if index exceeds MCE list length */
+ if (!hw->nix0->mcast.mce_ctx ||
+ (req->qidx >= (256UL << (cfg & 0xF
+ rc = NIX_AF_ERR_AQ_ENQUEUE;
+
+ /* Adding multicast lists for requests from PF/VFs is not
+* yet supported, so ignore this.
+*/
+ if (rsp)
+ rc = NIX_AF_ERR_AQ_ENQUEUE;
+ break;
default:
rc = NIX_AF_ERR_AQ_ENQUEUE;
}
@@ -361,6 +429,9 @@ static int rvu_nix_aq_enq_inst(struct rvu *rvu, struct
nix_aq_enq_req *req,
else if (req->ctype == NIX_AQ_CTYPE_RSS)
memcpy(mask, >rss_mask,
sizeof(struct nix_rsse_s));
+ else if (req->ctype == NIX_AQ_CTYPE_MCE)
+ memcpy(mask, >mce_mask,
+ sizeof(struct nix_rx_mce_s));
/* Fall through */
case
[PATCH v2 04/17] octeontx2-af: Add NPC KPU profile
From: Hao Zheng
NPC block is responsible for parsing and forwarding
packets to different NIXLFs. NPC has 16 KPU engines
(Kangaroo parse engine) and one iKPU which represents
pkinds. Each physical port either CGX/LBK is assigned
a pkind and upon receiving a packet HW takes that port's
pkind and starts parsing as per the KPU engines config.
This patch adds header files which contain configuration
profile/array for each of the iKPU and 16 KPU engines.
Signed-off-by: Hao Zheng
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/af/npc.h| 143 +
.../ethernet/marvell/octeontx2/af/npc_profile.h| 5709
2 files changed, 5852 insertions(+)
create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/npc.h
create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/npc_profile.h
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/npc.h
b/drivers/net/ethernet/marvell/octeontx2/af/npc.h
new file mode 100644
index 000..3e7ec10
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/af/npc.h
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: GPL-2.0
+ * Marvell OcteonTx2 RVU Admin Function driver
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef NPC_H
+#define NPC_H
+
+enum NPC_LID_E {
+ NPC_LID_LA = 0,
+ NPC_LID_LB,
+ NPC_LID_LC,
+ NPC_LID_LD,
+ NPC_LID_LE,
+ NPC_LID_LF,
+ NPC_LID_LG,
+ NPC_LID_LH,
+};
+
+#define NPC_LT_NA 0
+
+enum npc_kpu_la_ltype {
+ NPC_LT_LA_8023 = 1,
+ NPC_LT_LA_ETHER,
+};
+
+enum npc_kpu_lb_ltype {
+ NPC_LT_LB_ETAG = 1,
+ NPC_LT_LB_CTAG,
+ NPC_LT_LB_STAG,
+ NPC_LT_LB_BTAG,
+ NPC_LT_LB_QINQ,
+ NPC_LT_LB_ITAG,
+};
+
+enum npc_kpu_lc_ltype {
+ NPC_LT_LC_IP = 1,
+ NPC_LT_LC_IP6,
+ NPC_LT_LC_ARP,
+ NPC_LT_LC_RARP,
+ NPC_LT_LC_MPLS,
+ NPC_LT_LC_NSH,
+ NPC_LT_LC_PTP,
+ NPC_LT_LC_FCOE,
+};
+
+/* Don't modify Ltypes upto SCTP, otherwise it will
+ * effect flow tag calculation and thus RSS.
+ */
+enum npc_kpu_ld_ltype {
+ NPC_LT_LD_TCP = 1,
+ NPC_LT_LD_UDP,
+ NPC_LT_LD_ICMP,
+ NPC_LT_LD_SCTP,
+ NPC_LT_LD_IGMP,
+ NPC_LT_LD_ICMP6,
+ NPC_LT_LD_ESP,
+ NPC_LT_LD_AH,
+ NPC_LT_LD_GRE,
+ NPC_LT_LD_GRE_MPLS,
+ NPC_LT_LD_GRE_NSH,
+ NPC_LT_LD_TU_MPLS,
+};
+
+enum npc_kpu_le_ltype {
+ NPC_LT_LE_TU_ETHER = 1,
+ NPC_LT_LE_TU_PPP,
+ NPC_LT_LE_TU_MPLS_IN_NSH,
+ NPC_LT_LE_TU_3RD_NSH,
+};
+
+enum npc_kpu_lf_ltype {
+ NPC_LT_LF_TU_IP = 1,
+ NPC_LT_LF_TU_IP6,
+ NPC_LT_LF_TU_ARP,
+ NPC_LT_LF_TU_MPLS_IP,
+ NPC_LT_LF_TU_MPLS_IP6,
+ NPC_LT_LF_TU_MPLS_ETHER,
+};
+
+enum npc_kpu_lg_ltype {
+ NPC_LT_LG_TU_TCP = 1,
+ NPC_LT_LG_TU_UDP,
+ NPC_LT_LG_TU_SCTP,
+ NPC_LT_LG_TU_ICMP,
+ NPC_LT_LG_TU_IGMP,
+ NPC_LT_LG_TU_ICMP6,
+ NPC_LT_LG_TU_ESP,
+ NPC_LT_LG_TU_AH,
+};
+
+enum npc_kpu_lh_ltype {
+ NPC_LT_LH_TCP_DATA = 1,
+ NPC_LT_LH_HTTP_DATA,
+ NPC_LT_LH_HTTPS_DATA,
+ NPC_LT_LH_PPTP_DATA,
+ NPC_LT_LH_UDP_DATA,
+};
+
+struct npc_kpu_profile_cam {
+ u8 state;
+ u8 state_mask;
+ u16 dp0;
+ u16 dp0_mask;
+ u16 dp1;
+ u16 dp1_mask;
+ u16 dp2;
+ u16 dp2_mask;
+};
+
+struct npc_kpu_profile_action {
+ u8 errlev;
+ u8 errcode;
+ u8 dp0_offset;
+ u8 dp1_offset;
+ u8 dp2_offset;
+ u8 bypass_count;
+ u8 parse_done;
+ u8 next_state;
+ u8 ptr_advance;
+ u8 cap_ena;
+ u8 lid;
+ u8 ltype;
+ u8 flags;
+ u8 offset;
+ u8 mask;
+ u8 right;
+ u8 shift;
+};
+
+struct npc_kpu_profile {
+ int cam_entries;
+ int action_entries;
+ struct npc_kpu_profile_cam *cam;
+ struct npc_kpu_profile_action *action;
+};
+
+#endif /* NPC_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/npc_profile.h
b/drivers/net/ethernet/marvell/octeontx2/af/npc_profile.h
new file mode 100644
index 000..b2ce957
--- /dev/null
+++ b/drivers/net/ethernet/marvell/octeontx2/af/npc_profile.h
@@ -0,0 +1,5709 @@
+/* SPDX-License-Identifier: GPL-2.0
+ * Marvell OcteonTx2 RVU Admin Function driver
+ *
+ * Copyright (C) 2018 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef NPC_PROFILE_H
+#define NPC_PROFILE_H
+
+#define NPC_ETYPE_IP 0x0800
+#define NPC_ETYPE_IP6 0x86dd
+#define NPC_ETYPE_ARP 0x0806
+#define NPC_ETYPE_RARP 0x8035
+#define NPC_ETYPE_MPLSU0x8847
[PATCH v2 14/17] octeontx2-af: NIX Rx flowkey configuration for RSS
From: Sunil Goutham
Configure NIX RX flowkey algorithm configuration to support
RSS (receive side scaling). Currently support for only L3/L4
2-tuple and 4-tuple hash of IPv4/v6/TCP/UDP/SCTP is added.
HW supports upto 32 different flowkey algorithms which SW
can define, this patch defines 9. NPC RX ACTION has to point
to one of these flowkey indices for RSS to work.
The configuration is dependent on NPC parse result's layer
info. So if NPC KPU profile changes suchthat LID/LTYPE values
of above said protocols change then this configuration will
most likely be effected.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/af/common.h | 22
.../net/ethernet/marvell/octeontx2/af/rvu_nix.c| 135 +
.../net/ethernet/marvell/octeontx2/af/rvu_struct.h | 30 +
3 files changed, 187 insertions(+)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/common.h
b/drivers/net/ethernet/marvell/octeontx2/af/common.h
index 6c8150d..d39ada4 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/common.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/common.h
@@ -186,4 +186,26 @@ enum nix_scheduler {
#define DEFAULT_RSS_CONTEXT_GROUP 0
#define MAX_RSS_INDIR_TBL_SIZE 256 /* 1 << Max adder bits */
+/* NIX flow tag, key type flags */
+#define FLOW_KEY_TYPE_PORT BIT(0)
+#define FLOW_KEY_TYPE_IPV4 BIT(1)
+#define FLOW_KEY_TYPE_IPV6 BIT(2)
+#define FLOW_KEY_TYPE_TCP BIT(3)
+#define FLOW_KEY_TYPE_UDP BIT(4)
+#define FLOW_KEY_TYPE_SCTP BIT(5)
+
+/* NIX flow tag algorithm indices, max is 31 */
+enum {
+ FLOW_KEY_ALG_PORT,
+ FLOW_KEY_ALG_IP,
+ FLOW_KEY_ALG_TCP,
+ FLOW_KEY_ALG_UDP,
+ FLOW_KEY_ALG_SCTP,
+ FLOW_KEY_ALG_TCP_UDP,
+ FLOW_KEY_ALG_TCP_SCTP,
+ FLOW_KEY_ALG_UDP_SCTP,
+ FLOW_KEY_ALG_TCP_UDP_SCTP,
+ FLOW_KEY_ALG_MAX,
+};
+
#endif /* COMMON_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index fbe4ff0..e4c2c52 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -1536,6 +1536,139 @@ int rvu_mbox_handler_NIX_STATS_RST(struct rvu *rvu,
struct msg_req *req,
return 0;
}
+static void set_flowkey_fields(struct nix_rx_flowkey_alg *alg, u32 flow_cfg)
+{
+ struct nix_rx_flowkey_alg *field = NULL;
+ int idx, key_type;
+
+ if (!alg)
+ return;
+
+ /* FIELD0: IPv4
+* FIELD1: IPv6
+* FIELD2: TCP/UDP/SCTP/ALL
+* FIELD3: Unused
+* FIELD4: Unused
+*
+* Each of the 32 possible flow key algorithm definitions should
+* fall into above incremental config (except ALG0). Otherwise a
+* single NPC MCAM entry is not sufficient for supporting RSS.
+*
+* If a different definition or combination needed then NPC MCAM
+* has to be programmed to filter such pkts and it's action should
+* point to this definition to calculate flowtag or hash.
+*/
+ for (idx = 0; idx < 32; idx++) {
+ key_type = flow_cfg & BIT_ULL(idx);
+ if (!key_type)
+ continue;
+ switch (key_type) {
+ case FLOW_KEY_TYPE_PORT:
+ field = [0];
+ field->sel_chan = true;
+ /* This should be set to 1, when SEL_CHAN is set */
+ field->bytesm1 = 1;
+ break;
+ case FLOW_KEY_TYPE_IPV4:
+ field = [0];
+ field->lid = NPC_LID_LC;
+ field->ltype_match = NPC_LT_LC_IP;
+ field->hdr_offset = 12; /* SIP offset */
+ field->bytesm1 = 7; /* SIP + DIP, 8 bytes */
+ field->ltype_mask = 0xF; /* Match only IPv4 */
+ break;
+ case FLOW_KEY_TYPE_IPV6:
+ field = [1];
+ field->lid = NPC_LID_LC;
+ field->ltype_match = NPC_LT_LC_IP6;
+ field->hdr_offset = 8; /* SIP offset */
+ field->bytesm1 = 31; /* SIP + DIP, 32 bytes */
+ field->ltype_mask = 0xF; /* Match only IPv6 */
+ break;
+ case FLOW_KEY_TYPE_TCP:
+ case FLOW_KEY_TYPE_UDP:
+ case FLOW_KEY_TYPE_SCTP:
+ field = [2];
+ field->lid = NPC_LID_LD;
+ field->bytesm1 = 3; /* Sport + Dport, 4 bytes */
+ if (key_type == FLOW_KEY_TYPE_TCP)
+ field->ltype_match |= NPC_LT_LD_TCP;
+ else if (key_type == FLOW_KEY_TYPE_UDP)
+ field->ltype_match |= NPC_LT_LD_UDP;
+ else if
[PATCH v2 15/17] octeontx2-af: Support for changing RSS algorithm
From: Sunil Goutham
This patch adds support for a RVU PF/VF to change
NIX Rx flowkey algorithm index in NPC RX RSS_ACTION.
eg: a ethtool command changing RSS algorithm for a netdev
interface would trigger this change in NPC.
If PF/VF doesn't specify any MCAM entry index then default
UCAST entry of the NIXLF attached to PF/VF will be updated
with RSS_ACTION and flowkey index.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 10 -
drivers/net/ethernet/marvell/octeontx2/af/rvu.h| 5 +++
.../net/ethernet/marvell/octeontx2/af/rvu_nix.c| 51 ++
.../net/ethernet/marvell/octeontx2/af/rvu_npc.c| 43 ++
4 files changed, 108 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index 0e2552c..32d70bf 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -157,7 +157,8 @@ M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc_req,
nix_txsch_alloc_rsp) \
M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free_req, msg_rsp)\
M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_config, msg_rsp) \
M(NIX_STATS_RST, 0x8007, msg_req, msg_rsp) \
-M(NIX_VTAG_CFG,0x8008, nix_vtag_config, msg_rsp)
+M(NIX_VTAG_CFG,0x8008, nix_vtag_config, msg_rsp) \
+M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, msg_rsp)
/* Messages initiated by AF (range 0xC00 - 0xDFF) */
#define MBOX_UP_CGX_MESSAGES \
@@ -499,4 +500,11 @@ struct nix_vtag_config {
};
};
+struct nix_rss_flowkey_cfg {
+ struct mbox_msghdr hdr;
+ int mcam_index; /* MCAM entry index to modify */
+ u32 flowkey_cfg; /* Flowkey types selected */
+ u8 group; /* RSS context or group */
+};
+
#endif /* MBOX_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index e83d324..b169657 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -341,6 +341,9 @@ int rvu_mbox_handler_NIX_STATS_RST(struct rvu *rvu, struct
msg_req *req,
int rvu_mbox_handler_NIX_VTAG_CFG(struct rvu *rvu,
struct nix_vtag_config *req,
struct msg_rsp *rsp);
+int rvu_mbox_handler_NIX_RSS_FLOWKEY_CFG(struct rvu *rvu,
+struct nix_rss_flowkey_cfg *req,
+struct msg_rsp *rsp);
/* NPC APIs */
int rvu_npc_init(struct rvu *rvu);
@@ -352,4 +355,6 @@ void rvu_npc_install_ucast_entry(struct rvu *rvu, u16
pcifunc,
void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
int nixlf, u64 chan);
void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
+void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
+ int group, int alg_idx, int mcam_index);
#endif /* RVU_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index e4c2c52..d4dcdbb 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -1536,6 +1536,57 @@ int rvu_mbox_handler_NIX_STATS_RST(struct rvu *rvu,
struct msg_req *req,
return 0;
}
+/* Returns the ALG index to be set into NPC_RX_ACTION */
+static int get_flowkey_alg_idx(u32 flow_cfg)
+{
+ u32 ip_cfg;
+
+ flow_cfg &= ~FLOW_KEY_TYPE_PORT;
+ ip_cfg = FLOW_KEY_TYPE_IPV4 | FLOW_KEY_TYPE_IPV6;
+ if (flow_cfg == ip_cfg)
+ return FLOW_KEY_ALG_IP;
+ else if (flow_cfg == (ip_cfg | FLOW_KEY_TYPE_TCP))
+ return FLOW_KEY_ALG_TCP;
+ else if (flow_cfg == (ip_cfg | FLOW_KEY_TYPE_UDP))
+ return FLOW_KEY_ALG_UDP;
+ else if (flow_cfg == (ip_cfg | FLOW_KEY_TYPE_SCTP))
+ return FLOW_KEY_ALG_SCTP;
+ else if (flow_cfg == (ip_cfg | FLOW_KEY_TYPE_TCP | FLOW_KEY_TYPE_UDP))
+ return FLOW_KEY_ALG_TCP_UDP;
+ else if (flow_cfg == (ip_cfg | FLOW_KEY_TYPE_TCP | FLOW_KEY_TYPE_SCTP))
+ return FLOW_KEY_ALG_TCP_SCTP;
+ else if (flow_cfg == (ip_cfg | FLOW_KEY_TYPE_UDP | FLOW_KEY_TYPE_SCTP))
+ return FLOW_KEY_ALG_UDP_SCTP;
+ else if (flow_cfg == (ip_cfg | FLOW_KEY_TYPE_TCP |
+ FLOW_KEY_TYPE_UDP | FLOW_KEY_TYPE_SCTP))
+ return FLOW_KEY_ALG_TCP_UDP_SCTP;
+
+ return FLOW_KEY_ALG_PORT;
+}
+
+int rvu_mbox_handler_NIX_RSS_FLOWKEY_CFG(struct rvu *rvu,
+struct nix_rss_flowkey_cfg *req,
+struct msg_rsp *rsp)
+{
+
[PATCH v2 16/17] octeontx2-af: Support for setting MAC address
From: Sunil Goutham
Added a new mailbox message for a PF/VF to set/update
it's NIXLF's MAC address. Also updates unicast NPC
MCAM entry with this address as matching DMAC.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 8 ++-
drivers/net/ethernet/marvell/octeontx2/af/rvu.h| 3 +++
.../net/ethernet/marvell/octeontx2/af/rvu_nix.c| 25 ++
3 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index 32d70bf..afa2ead 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -158,7 +158,8 @@ M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free_req, msg_rsp)
\
M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_config, msg_rsp) \
M(NIX_STATS_RST, 0x8007, msg_req, msg_rsp) \
M(NIX_VTAG_CFG,0x8008, nix_vtag_config, msg_rsp) \
-M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, msg_rsp)
+M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, msg_rsp) \
+M(NIX_SET_MAC_ADDR,0x800a, nix_set_mac_addr, msg_rsp)
/* Messages initiated by AF (range 0xC00 - 0xDFF) */
#define MBOX_UP_CGX_MESSAGES \
@@ -507,4 +508,9 @@ struct nix_rss_flowkey_cfg {
u8 group; /* RSS context or group */
};
+struct nix_set_mac_addr {
+ struct mbox_msghdr hdr;
+ u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
+};
+
#endif /* MBOX_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index b169657..93e6891 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -344,6 +344,9 @@ int rvu_mbox_handler_NIX_VTAG_CFG(struct rvu *rvu,
int rvu_mbox_handler_NIX_RSS_FLOWKEY_CFG(struct rvu *rvu,
struct nix_rss_flowkey_cfg *req,
struct msg_rsp *rsp);
+int rvu_mbox_handler_NIX_SET_MAC_ADDR(struct rvu *rvu,
+ struct nix_set_mac_addr *req,
+ struct msg_rsp *rsp);
/* NPC APIs */
int rvu_npc_init(struct rvu *rvu);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index d4dcdbb..3caf81b 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -1720,6 +1720,31 @@ static void nix_rx_flowkey_alg_cfg(struct rvu *rvu, int
blkaddr)
}
}
+int rvu_mbox_handler_NIX_SET_MAC_ADDR(struct rvu *rvu,
+ struct nix_set_mac_addr *req,
+ struct msg_rsp *rsp)
+{
+ struct rvu_hwinfo *hw = rvu->hw;
+ u16 pcifunc = req->hdr.pcifunc;
+ struct rvu_pfvf *pfvf;
+ int blkaddr, nixlf;
+
+ pfvf = rvu_get_pfvf(rvu, pcifunc);
+ blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
+ if (!pfvf->nixlf || blkaddr < 0)
+ return NIX_AF_ERR_AF_LF_INVALID;
+
+ nixlf = rvu_get_lf(rvu, >block[blkaddr], pcifunc, 0);
+ if (nixlf < 0)
+ return NIX_AF_ERR_AF_LF_INVALID;
+
+ ether_addr_copy(pfvf->mac_addr, req->mac_addr);
+
+ rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf,
+ pfvf->rx_chan_base, req->mac_addr);
+ return 0;
+}
+
static int nix_calibrate_x2p(struct rvu *rvu, int blkaddr)
{
int idx, err;
--
2.7.4
[PATCH v2 12/17] octeontx2-af: Add LMAC channel info to NIXLF_ALLOC response
From: Stanislaw Kardach
Add LMAC channel info like Rx/Tx channel base and count to
NIXLF_ALLOC mailbox message response. This info is used by
NIXLF attached RVU PF/VF to configure SQ's default channel,
TL3_TL2_LINKX_CFG and to install MCAM rules in NPC based
on matching ingress channel number.
Signed-off-by: Stanislaw Kardach
Signed-off-by: Tomasz Duszynski
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/af/common.h | 1 +
drivers/net/ethernet/marvell/octeontx2/af/mbox.h| 4
drivers/net/ethernet/marvell/octeontx2/af/rvu.h | 5 +
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 8
4 files changed, 18 insertions(+)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/common.h
b/drivers/net/ethernet/marvell/octeontx2/af/common.h
index e438f92..6c8150d 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/common.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/common.h
@@ -169,6 +169,7 @@ enum nix_scheduler {
#define MAX_LMAC_PKIND 12
#define NIX_LINK_CGX_LMAC(a, b)(0 + 4 * (a) + (b))
+#define NIX_CHAN_CGX_LMAC_CHX(a, b, c) (0x800 + 0x100 * (a) + 0x10 * (b) + (c))
/* NIX LSO format indices.
* As of now TSO is the only one using, so statically assigning indices.
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index b60ac9d..0e2552c 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -382,6 +382,10 @@ struct nix_lf_alloc_req {
struct nix_lf_alloc_rsp {
struct mbox_msghdr hdr;
u16 sqb_size;
+ u16 rx_chan_base;
+ u16 tx_chan_base;
+ u8 rx_chan_cnt; /* total number of RX channels */
+ u8 tx_chan_cnt; /* total number of TX channels */
u8 lso_tsov4_idx;
u8 lso_tsov6_idx;
u8 mac_addr[ETH_ALEN];
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index 9fa5183..12391d2 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -118,6 +118,11 @@ struct rvu_pfvf {
unsigned long *rq_bmap;
unsigned long *cq_bmap;
+ u16 rx_chan_base;
+ u16 tx_chan_base;
+ u8 rx_chan_cnt; /* total number of RX channels */
+ u8 tx_chan_cnt; /* total number of TX channels */
+
u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
/* Broadcast pkt replication info */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 55075e7..86b1e9b 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -140,6 +140,10 @@ static int nix_interface_init(struct rvu *rvu, u16
pcifunc, int type, int nixlf)
"PF_Func 0x%x: Invalid pkind\n", pcifunc);
return -EINVAL;
}
+ pfvf->rx_chan_base = NIX_CHAN_CGX_LMAC_CHX(cgx_id, lmac_id, 0);
+ pfvf->tx_chan_base = pfvf->rx_chan_base;
+ pfvf->rx_chan_cnt = 1;
+ pfvf->tx_chan_cnt = 1;
cgx_set_pkind(rvu_cgx_pdata(cgx_id, rvu), lmac_id, pkind);
rvu_npc_set_pkind(rvu, pkind, pfvf);
break;
@@ -799,6 +803,10 @@ int rvu_mbox_handler_NIX_LF_ALLOC(struct rvu *rvu,
/* set SQB size info */
cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQ_CONST);
rsp->sqb_size = (cfg >> 34) & 0x;
+ rsp->rx_chan_base = pfvf->rx_chan_base;
+ rsp->tx_chan_base = pfvf->tx_chan_base;
+ rsp->rx_chan_cnt = pfvf->rx_chan_cnt;
+ rsp->tx_chan_cnt = pfvf->tx_chan_cnt;
rsp->lso_tsov4_idx = NIX_LSO_FORMAT_IDX_TSOV4;
rsp->lso_tsov6_idx = NIX_LSO_FORMAT_IDX_TSOV6;
return rc;
--
2.7.4
[PATCH v2 13/17] octeontx2-af: Install ucast and bcast pkt forwarding rules
From: Sunil Goutham
Upon NIXLF_ALLOC install a unicast forwarding rule in NPC MCAM
like below
- Match pkt DMAC with NIXLF attached PF/VF's MAC address.
- Ingress channel
- Action is UCAST
- Forward to PF_FUNC of this NIXLF
And broadcast pkt forwarding rule as
- Match L2B bit in MCAM search key
- Ingress channel
- Action is UCAST, for now, later it will be changed to MCAST.
Only PFs can install this rule
Upon NIXLF_FREE disable all MCAM entries in use by that NIXLF.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/af/npc.h| 19 ++
drivers/net/ethernet/marvell/octeontx2/af/rvu.h| 5 +
.../net/ethernet/marvell/octeontx2/af/rvu_nix.c| 14 +
.../net/ethernet/marvell/octeontx2/af/rvu_npc.c| 337 +
4 files changed, 375 insertions(+)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/npc.h
b/drivers/net/ethernet/marvell/octeontx2/af/npc.h
index 58d8f0b..f98b011 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/npc.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/npc.h
@@ -240,4 +240,23 @@ struct npc_kpu_pkind_cpi_def {
u64 ena: 1;
#endif
};
+
+struct nix_rx_action {
+#if defined(__BIG_ENDIAN_BITFIELD)
+ u64 rsvd_63_61 :3;
+ u64 flow_key_alg:5;
+ u64 match_id:16;
+ u64 index :20;
+ u64 pf_func :16;
+ u64 op :4;
+#else
+ u64 op :4;
+ u64 pf_func :16;
+ u64 index :20;
+ u64 match_id:16;
+ u64 flow_key_alg:5;
+ u64 rsvd_63_61 :3;
+#endif
+};
+
#endif /* NPC_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index 12391d2..e83d324 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -347,4 +347,9 @@ int rvu_npc_init(struct rvu *rvu);
void rvu_npc_freemem(struct rvu *rvu);
int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
+void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
+int nixlf, u64 chan, u8 *mac_addr);
+void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
+ int nixlf, u64 chan);
+void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
#endif /* RVU_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 86b1e9b..fbe4ff0 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -151,13 +151,24 @@ static int nix_interface_init(struct rvu *rvu, u16
pcifunc, int type, int nixlf)
break;
}
+ /* Add a UCAST forwarding rule in MCAM with this NIXLF attached
+* RVU PF/VF's MAC address.
+*/
+ rvu_npc_install_ucast_entry(rvu, pcifunc, nixlf,
+ pfvf->rx_chan_base, pfvf->mac_addr);
+
/* Add this PF_FUNC to bcast pkt replication list */
err = nix_update_bcast_mce_list(rvu, pcifunc, true);
if (err) {
dev_err(rvu->dev,
"Bcast list, failed to enable PF_FUNC 0x%x\n",
pcifunc);
+ return err;
}
+
+ rvu_npc_install_bcast_match_entry(rvu, pcifunc,
+ nixlf, pfvf->rx_chan_base);
+
return 0;
}
@@ -172,6 +183,9 @@ static void nix_interface_deinit(struct rvu *rvu, u16
pcifunc, u8 nixlf)
"Bcast list, failed to disable PF_FUNC 0x%x\n",
pcifunc);
}
+
+ /* Free and disable any MCAM entries used by this NIX LF */
+ rvu_npc_disable_mcam_entries(rvu, pcifunc, nixlf);
}
static void nix_setup_lso_tso_l3(struct rvu *rvu, int blkaddr,
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
index 1c29436..845ea98 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
@@ -26,6 +26,14 @@
#define NPC_PARSE_RESULT_DMAC_OFFSET 8
+struct mcam_entry {
+#define NPC_MAX_KWS_IN_KEY 7 /* Number of keywords in max keywidth */
+ u64 kw[NPC_MAX_KWS_IN_KEY];
+ u64 kw_mask[NPC_MAX_KWS_IN_KEY];
+ u64 action;
+ u64 vtag_action;
+};
+
void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf)
{
int blkaddr;
@@ -54,6 +62,335 @@ int rvu_npc_get_pkind(struct rvu *rvu, u16 pf)
return -1;
}
+static int npc_get_nixlf_mcam_index(struct npc_mcam *mcam,
+ u16 pcifunc, int nixlf, int type)
+{
+ int pf = rvu_get_pf(pcifunc);
[PATCH v2 11/17] octeontx2-af: NPC MCAM and LDATA extract minimal configuration
From: Sunil Goutham
This patch adds some minimal configuration for NPC MCAM and
LDATA extraction which is sufficient enough to install
ucast/bcast/promiscuous forwarding rules. Below is the
config done
- LDATA extraction config to extract DMAC from pkt
to offset 64bit in MCAM search key.
- Set MCAM lookup keysize to 224bits
- Set MCAM TX miss action to UCAST_DEFAULT
- Set MCAM RX miss action to DROP
Also inorder to have guaranteed space in MCAM to install
ucast forwarding rule for each of RVU PF/VF, reserved
one MCAM entry for each of NIXLF for ucast rule. And two
entries for each of RVU PF. One for bcast pkt replication
and other for promiscuous mode which allows all pkts
received on a HW CGX/LBK channel.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/af/common.h | 21
drivers/net/ethernet/marvell/octeontx2/af/rvu.h| 14 +++
.../net/ethernet/marvell/octeontx2/af/rvu_nix.c| 12 ++
.../net/ethernet/marvell/octeontx2/af/rvu_npc.c| 134 +
4 files changed, 181 insertions(+)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/common.h
b/drivers/net/ethernet/marvell/octeontx2/af/common.h
index 7c53ba3..e438f92 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/common.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/common.h
@@ -143,6 +143,27 @@ enum nix_scheduler {
NIX_TXSCH_LVL_CNT = 0x5,
};
+/* NIX RX action operation*/
+#define NIX_RX_ACTIONOP_DROP (0x0ull)
+#define NIX_RX_ACTIONOP_UCAST (0x1ull)
+#define NIX_RX_ACTIONOP_UCAST_IPSEC(0x2ull)
+#define NIX_RX_ACTIONOP_MCAST (0x3ull)
+#define NIX_RX_ACTIONOP_RSS(0x4ull)
+
+/* NIX TX action operation*/
+#define NIX_TX_ACTIONOP_DROP (0x0ull)
+#define NIX_TX_ACTIONOP_UCAST_DEFAULT (0x1ull)
+#define NIX_TX_ACTIONOP_UCAST_CHAN (0x2ull)
+#define NIX_TX_ACTIONOP_MCAST (0x3ull)
+#define NIX_TX_ACTIONOP_DROP_VIOL (0x5ull)
+
+#define NPC_MCAM_KEY_X10
+#define NPC_MCAM_KEY_X21
+#define NPC_MCAM_KEY_X42
+
+#define NIX_INTF_RX0
+#define NIX_INTF_TX1
+
#define NIX_INTF_TYPE_CGX 0
#define NIX_INTF_TYPE_LBK 1
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index 1e85e80..9fa5183 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -73,6 +73,18 @@ struct nix_mce_list {
int max;
};
+struct npc_mcam {
+ spinlock_t lock; /* MCAM entries and counters update lock */
+ u8 keysize;/* MCAM keysize 112/224/448 bits */
+ u8 banks; /* Number of MCAM banks */
+ u8 banks_per_entry;/* Number of keywords in key */
+ u16 banksize; /* Number of MCAM entries in each bank */
+ u16 total_entries; /* Total number of MCAM entries */
+ u16 entries;/* Total minus reserved for NIX LFs */
+ u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */
+ u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */
+};
+
/* Structure for per RVU func info ie PF/VF */
struct rvu_pfvf {
boolnpalf; /* Only one NPALF per RVU_FUNC */
@@ -144,6 +156,7 @@ struct rvu_hwinfo {
struct rvu_block block[BLK_COUNT]; /* Block info */
struct nix_hw*nix0;
struct npc_pkind pkind;
+ struct npc_mcam mcam;
};
struct rvu {
@@ -297,6 +310,7 @@ int rvu_mbox_handler_NPA_LF_FREE(struct rvu *rvu, struct
msg_req *req,
/* NIX APIs */
int rvu_nix_init(struct rvu *rvu);
void rvu_nix_freemem(struct rvu *rvu);
+int rvu_get_nixlf_count(struct rvu *rvu);
int rvu_mbox_handler_NIX_LF_ALLOC(struct rvu *rvu,
struct nix_lf_alloc_req *req,
struct nix_lf_alloc_rsp *rsp);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 02e1d16..55075e7 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -55,6 +55,18 @@ struct mce {
u16 pcifunc;
};
+int rvu_get_nixlf_count(struct rvu *rvu)
+{
+ struct rvu_block *block;
+ int blkaddr;
+
+ blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0);
+ if (blkaddr < 0)
+ return 0;
+ block = >hw->block[blkaddr];
+ return block->lf.max;
+}
+
static void nix_mce_list_init(struct nix_mce_list *list, int max)
{
INIT_HLIST_HEAD(>head);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
index cc1d8c9..1c29436 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
+++
Re: Kernel oops with mlx5 and dual XDP redirect programs
On Thu, 2018-10-18 at 23:53 +0200, Toke Høiland-Jørgensen wrote:
> Saeed Mahameed writes:
>
> > I think that the mlx5 driver doesn't know how to tell the other
> > device
> > to stop transmitting to it while it is resetting.. Maybe tariq or
> > Jesper know more about this ?
> > I will look at this tomorrow after noon and will try to repro...
>
> Hi Saeed
>
> Did you have a chance to poke at this? :)
HI Toke, yes i have been planing to respond but also i wanted to dig
more,
so the root cause is very clear.
1. core 1 is doing tx_dev->ndo_xdp_xmit()
2. core 2 is doing tx_dev->xdp_set() //remove xdp program.
in mlx5 you must have xdp porgram on tx_dev in order to be able to use
dev_map and ndo_xdp_xmit, due to the simple reason that we create
unique TX resources (Send Queues/SQs) for xdp redirect/tx use case.
so if you are removing xdp program on core2, driver will start
destroying xdp redirect SQs, this safe for xdp rx and fwd since we use
napi_synchronize. But for xdp redirect, we don't have the means to
synchronize with a different napi device and yet on a different cpu !
so if core 1 got past the below check in mlx5/core/en/xdp.c @
mlx5e_xdp_xmit
if (unlikely(!test_bit(MLX5E_SQ_STATE_ENABLED, >state)))
return -ENETDOWN;
and at the same moment core 2 destroyed that SQ:
@mlx5e_xdp_set -> mlx5e_close_locked
This SQ is no longer available and core 1 will be writing descriptors
on a freed dma buffer.
and the problem is beyond mlx5, since we don't have a way to tell a
different core/different netdev to stop xmitting, or at least
synchronize with it.
Assuming napi is polled under rcu read lock, then synchronize_net might
help ass suggested in the attached temporary fix.
the idea is to set a flag for mlx5e_xdp_tx ndo to check if tx resources
are valid, and to set it on and of on xdp_set ndo with synchronize_net
to synchronize with ongoing xdp redirection.
I am still not sure if napi is polled under rcu read lock, if it's not
and synchronize_net() didn't help then replace it with msleep(200),
should be enough for now.
I've managed to reproduce and verify the fix with even one direction of
xdp_redirect and by just removing the xdp program on the tx side while
xdp redirection was ongoing.
#run xdp redirect
RX_IF=p6p1
TX_IF=p5p1
./samples/bpf/xdp_redirect_map $(
Date: Fri, 19 Oct 2018 14:59:00 -0700
Subject: [PATCH] net/mlx5e: XDP redirect bug fix
Signed-off-by: Saeed Mahameed
---
drivers/net/ethernet/mellanox/mlx5/core/en.h | 1 +
drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c | 3 +++
drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 15 +--
3 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h
b/drivers/net/ethernet/mellanox/mlx5/core/en.h
index aea74856c702..4228aafc0165 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h
@@ -620,6 +620,7 @@ struct mlx5e_channels {
struct mlx5e_channel **c;
unsigned int num;
struct mlx5e_paramsparams;
+ bool xdp_disabled;
};
struct mlx5e_channel_stats {
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c
b/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c
index ad6d471d00dd..c338b7b8f838 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/xdp.c
@@ -268,6 +268,9 @@ int mlx5e_xdp_xmit(struct net_device *dev, int n,
struct xdp_frame **frames,
if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
return -EINVAL;
+ if (unlikely(READ_ONCE(priv->channels.xdp_disabled)))
+ return -ENETDOWN;
+
sq_num = smp_processor_id();
if (unlikely(sq_num >= priv->channels.num))
diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
index 0d495a6b3949..a2d8a52ae469 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c
@@ -4237,8 +4237,17 @@ static int mlx5e_xdp_set(struct net_device
*netdev, struct bpf_prog *prog)
/* no need for full reset when exchanging programs */
reset = (!priv->channels.params.xdp_prog || !prog);
- if (was_opened && reset)
+ if (was_opened && reset) {
+ for (i = 0; i < priv->channels.num; i++)
+ clear_bit(MLX5E_SQ_STATE_ENABLED,
>channels.c[i]->xdpsq.state);
+ priv->channels.xdp_disabled = true;
+
+ synchronize_net();
+ //msleep(200);
+
mlx5e_close_locked(netdev);
+ }
+
if (was_opened && !reset) {
/* num_channels is invariant here, so we can take the
* batched reference right upfront.
@@ -4260,8 +4269,10 @@ static int mlx5e_xdp_set(struct net_device
*netdev, struct bpf_prog *prog)
if (reset) /* change RQ type according to priv->xdp_prog */
[PATCH v2 03/17] octeontx2-af: Reset NIXLF's Rx/Tx stats
From: Vamsi Attunuru
This patch adds a new mailbox message to reset
a NIXLF's receive and transmit HW stats.
Signed-off-by: Vamsi Attunuru
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 3 ++-
drivers/net/ethernet/marvell/octeontx2/af/rvu.h| 2 ++
.../net/ethernet/marvell/octeontx2/af/rvu_nix.c| 30 ++
3 files changed, 34 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index f2e0743..f8efeaa 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -155,7 +155,8 @@ M(NIX_AQ_ENQ, 0x8002, nix_aq_enq_req,
nix_aq_enq_rsp) \
M(NIX_HWCTX_DISABLE, 0x8003, hwctx_disable_req, msg_rsp) \
M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free_req, msg_rsp)\
-M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_config, msg_rsp)
+M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_config, msg_rsp) \
+M(NIX_STATS_RST, 0x8007, msg_req, msg_rsp)
/* Messages initiated by AF (range 0xC00 - 0xDFF) */
#define MBOX_UP_CGX_MESSAGES \
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index 4b15552..f041d0a 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -288,4 +288,6 @@ int rvu_mbox_handler_NIX_TXSCH_FREE(struct rvu *rvu,
int rvu_mbox_handler_NIX_TXSCHQ_CFG(struct rvu *rvu,
struct nix_txschq_config *req,
struct msg_rsp *rsp);
+int rvu_mbox_handler_NIX_STATS_RST(struct rvu *rvu, struct msg_req *req,
+ struct msg_rsp *rsp);
#endif /* RVU_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 56f242d..62d8913 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -1053,6 +1053,36 @@ static int nix_setup_txschq(struct rvu *rvu, struct
nix_hw *nix_hw, int blkaddr)
return 0;
}
+int rvu_mbox_handler_NIX_STATS_RST(struct rvu *rvu, struct msg_req *req,
+ struct msg_rsp *rsp)
+{
+ struct rvu_hwinfo *hw = rvu->hw;
+ u16 pcifunc = req->hdr.pcifunc;
+ int i, nixlf, blkaddr;
+ u64 stats;
+
+ blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
+ if (blkaddr < 0)
+ return NIX_AF_ERR_AF_LF_INVALID;
+
+ nixlf = rvu_get_lf(rvu, >block[blkaddr], pcifunc, 0);
+ if (nixlf < 0)
+ return NIX_AF_ERR_AF_LF_INVALID;
+
+ /* Get stats count supported by HW */
+ stats = rvu_read64(rvu, blkaddr, NIX_AF_CONST1);
+
+ /* Reset tx stats */
+ for (i = 0; i < ((stats >> 24) & 0xFF); i++)
+ rvu_write64(rvu, blkaddr, NIX_AF_LFX_TX_STATX(nixlf, i), 0);
+
+ /* Reset rx stats */
+ for (i = 0; i < ((stats >> 32) & 0xFF); i++)
+ rvu_write64(rvu, blkaddr, NIX_AF_LFX_RX_STATX(nixlf, i), 0);
+
+ return 0;
+}
+
static int nix_calibrate_x2p(struct rvu *rvu, int blkaddr)
{
int idx, err;
--
2.7.4
[PATCH v2 06/17] octeontx2-af: Config pkind for CGX mapped PFs
From: Geetha sowjanya
For each CGX LMAC that is mapped to a RVU PF, allocate
a pkind and config the same in CGX. For a received packet
at CGX LMAC interface this pkind is used by NPC block
to start parsing of packet.
Signed-off-by: Geetha sowjanya
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/af/cgx.c| 12
drivers/net/ethernet/marvell/octeontx2/af/cgx.h| 1 +
drivers/net/ethernet/marvell/octeontx2/af/common.h | 6
drivers/net/ethernet/marvell/octeontx2/af/rvu.h| 4 +++
.../net/ethernet/marvell/octeontx2/af/rvu_cgx.c| 7 +++--
.../net/ethernet/marvell/octeontx2/af/rvu_nix.c| 34 ++
.../net/ethernet/marvell/octeontx2/af/rvu_npc.c| 28 ++
7 files changed, 90 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
index 352501b..12db256 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.c
@@ -186,6 +186,18 @@ u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id)
}
EXPORT_SYMBOL(cgx_lmac_addr_get);
+int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind)
+{
+ struct cgx *cgx = cgxd;
+
+ if (!cgx || lmac_id >= cgx->lmac_count)
+ return -ENODEV;
+
+ cgx_write(cgx, lmac_id, CGXX_CMRX_RX_ID_MAP, (pkind & 0x3F));
+ return 0;
+}
+EXPORT_SYMBOL(cgx_set_pkind);
+
static inline u8 cgx_get_lmac_type(struct cgx *cgx, int lmac_id)
{
u64 cfg;
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
index ada25ed..0a66d27 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/cgx.h
@@ -97,6 +97,7 @@ extern struct pci_driver cgx_driver;
int cgx_get_cgx_cnt(void);
int cgx_get_lmac_cnt(void *cgxd);
void *cgx_get_pdata(int cgx_id);
+int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);
int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);
int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/common.h
b/drivers/net/ethernet/marvell/octeontx2/af/common.h
index 28eb691..7c53ba3 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/common.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/common.h
@@ -143,6 +143,12 @@ enum nix_scheduler {
NIX_TXSCH_LVL_CNT = 0x5,
};
+#define NIX_INTF_TYPE_CGX 0
+#define NIX_INTF_TYPE_LBK 1
+
+#define MAX_LMAC_PKIND 12
+#define NIX_LINK_CGX_LMAC(a, b)(0 + 4 * (a) + (b))
+
/* NIX LSO format indices.
* As of now TSO is the only one using, so statically assigning indices.
*/
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index e8e16a7..b3dbbd6 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -67,6 +67,7 @@ struct rvu_pfvf {
u16 ssow;
u16 cptlfs;
u16 timlfs;
+ u8 cgx_lmac;
/* Block LF's MSIX vector info */
struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
@@ -230,6 +231,7 @@ static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id,
u8 *lmac_id)
int rvu_cgx_probe(struct rvu *rvu);
void rvu_cgx_wq_destroy(struct rvu *rvu);
+void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
int rvu_mbox_handler_CGX_START_RXTX(struct rvu *rvu, struct msg_req *req,
struct msg_rsp *rsp);
@@ -302,4 +304,6 @@ int rvu_mbox_handler_NIX_STATS_RST(struct rvu *rvu, struct
msg_req *req,
/* NPC APIs */
int rvu_npc_init(struct rvu *rvu);
void rvu_npc_freemem(struct rvu *rvu);
+int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
+void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
#endif /* RVU_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
index e0aee21..188185c 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
@@ -50,7 +50,7 @@ static inline u8 cgxlmac_id_to_bmap(u8 cgx_id, u8 lmac_id)
return ((cgx_id & 0xF) << 4) | (lmac_id & 0xF);
}
-static void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu)
+void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu)
{
if (cgx_id >= rvu->cgx_cnt)
return NULL;
@@ -60,10 +60,11 @@ static void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu)
static int rvu_map_cgx_lmac_pf(struct rvu *rvu)
{
+ struct npc_pkind *pkind = >hw->pkind;
int cgx_cnt = rvu->cgx_cnt;
int cgx, lmac_cnt, lmac;
int pf =
[PATCH v2 10/17] octeontx2-af: Enable packet length and csum validation
From: Sunil Goutham Config NPC layer info from KPU profile into protocol checker to identify outer L2/IPv4/TCP/UDP headers in a packet. And enable IPv4 checksum validation. L3/L4 and L4 CSUM validation will be enabled by PF/VF drivers by configuring NIX_AF_LF(0..127)_RX_CFG via mbox i.e 'nix_lf_alloc_req->rx_cfg' Also enable setting of NPC_RESULT_S[L2B] when an outer L2 broadcast address is detected. This will help in installing NPC MCAM rules for broadcast packets. Signed-off-by: Sunil Goutham --- drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 14 ++ drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c | 14 ++ 2 files changed, 28 insertions(+) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c index 7de5417..02e1d16 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -14,6 +14,7 @@ #include "rvu_struct.h" #include "rvu_reg.h" #include "rvu.h" +#include "npc.h" #include "cgx.h" static int nix_update_bcast_mce_list(struct rvu *rvu, u16 pcifunc, bool add); @@ -1630,6 +1631,19 @@ int rvu_nix_init(struct rvu *rvu) err = nix_setup_mcast(rvu, hw->nix0, blkaddr); if (err) return err; + + /* Config Outer L2, IP, TCP and UDP's NPC layer info. +* This helps HW protocol checker to identify headers +* and validate length and checksums. +*/ + rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OL2, + (NPC_LID_LA << 8) | (NPC_LT_LA_ETHER << 4) | 0x0F); + rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OUDP, + (NPC_LID_LD << 8) | (NPC_LT_LD_UDP << 4) | 0x0F); + rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OTCP, + (NPC_LID_LD << 8) | (NPC_LT_LD_TCP << 4) | 0x0F); + rvu_write64(rvu, blkaddr, NIX_AF_RX_DEF_OIP4, + (NPC_LID_LC << 8) | (NPC_LT_LC_IP << 4) | 0x0F); } return 0; } diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c index a973895..cc1d8c9 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c @@ -220,6 +220,20 @@ int rvu_npc_init(struct rvu *rvu) /* Configure KPU profile */ npc_parser_profile_init(rvu, blkaddr); + /* Config Outer L2, IPv4's NPC layer info */ + rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OL2, + (NPC_LID_LA << 8) | (NPC_LT_LA_ETHER << 4) | 0x0F); + rvu_write64(rvu, blkaddr, NPC_AF_PCK_DEF_OIP4, + (NPC_LID_LC << 8) | (NPC_LT_LC_IP << 4) | 0x0F); + + /* Enable below for Rx pkts. +* - Outer IPv4 header checksum validation. +* - Detect outer L2 broadcast address and set NPC_RESULT_S[L2M]. +*/ + rvu_write64(rvu, blkaddr, NPC_AF_PCK_CFG, + rvu_read64(rvu, blkaddr, NPC_AF_PCK_CFG) | + BIT_ULL(6) | BIT_ULL(2)); + return 0; } -- 2.7.4
[PATCH v2 02/17] octeontx2-af: NIX Tx scheduler queue config support
From: Sunil Goutham
This patch adds support for a PF/VF driver to configure
NIX transmit scheduler queues via mbox. Since PF/VF doesn't
know the absolute HW index of the NIXLF attached to it, AF
traps the register config and overwrites with the correct
NIXLF index.
HW supports shaping, colouring and policing of packets with
these multilevel traffic scheduler queues. Instead of
introducing different mbox message formats for different
configurations and making both AF & PF/VF driver implementation
cumbersome, access to the scheduler queue's CSRs is provided
via mbox. AF checks whether the sender PF/VF has the
corresponding queue allocated or not and dumps the config
to HW. With a single mbox msg 20 registers can be configured.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/af/Makefile | 3 +-
drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 15 ++-
drivers/net/ethernet/marvell/octeontx2/af/rvu.h| 11 +++
.../net/ethernet/marvell/octeontx2/af/rvu_nix.c| 104 -
.../net/ethernet/marvell/octeontx2/af/rvu_reg.c| 71 ++
5 files changed, 199 insertions(+), 5 deletions(-)
create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/Makefile
b/drivers/net/ethernet/marvell/octeontx2/af/Makefile
index 45b108f..264cbd7 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/Makefile
+++ b/drivers/net/ethernet/marvell/octeontx2/af/Makefile
@@ -7,4 +7,5 @@ obj-$(CONFIG_OCTEONTX2_MBOX) += octeontx2_mbox.o
obj-$(CONFIG_OCTEONTX2_AF) += octeontx2_af.o
octeontx2_mbox-y := mbox.o
-octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o
+octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \
+ rvu_reg.o
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index 282e556..f2e0743 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -154,7 +154,8 @@ M(NIX_LF_FREE, 0x8001, msg_req, msg_rsp)
\
M(NIX_AQ_ENQ, 0x8002, nix_aq_enq_req, nix_aq_enq_rsp) \
M(NIX_HWCTX_DISABLE, 0x8003, hwctx_disable_req, msg_rsp) \
M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
-M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free_req, msg_rsp)
+M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free_req, msg_rsp)\
+M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_config, msg_rsp)
/* Messages initiated by AF (range 0xC00 - 0xDFF) */
#define MBOX_UP_CGX_MESSAGES \
@@ -448,4 +449,16 @@ struct nix_txsch_free_req {
u16 schq;
};
+struct nix_txschq_config {
+ struct mbox_msghdr hdr;
+ u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
+#define TXSCHQ_IDX_SHIFT 16
+#define TXSCHQ_IDX_MASK(BIT_ULL(10) - 1)
+#define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
+ u8 num_regs;
+#define MAX_REGS_PER_MBOX_MSG 20
+ u64 reg[MAX_REGS_PER_MBOX_MSG];
+ u64 regval[MAX_REGS_PER_MBOX_MSG];
+};
+
#endif /* MBOX_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index c402eba..4b15552 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -195,6 +195,14 @@ int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block,
int lf);
int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
+/* RVU HW reg validation */
+enum regmap_block {
+ TXSCHQ_HWREGMAP = 0,
+ MAX_HWREGMAP,
+};
+
+bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
+
/* NPA/NIX AQ APIs */
int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
int qsize, int inst_size, int res_size);
@@ -277,4 +285,7 @@ int rvu_mbox_handler_NIX_TXSCH_ALLOC(struct rvu *rvu,
int rvu_mbox_handler_NIX_TXSCH_FREE(struct rvu *rvu,
struct nix_txsch_free_req *req,
struct msg_rsp *rsp);
+int rvu_mbox_handler_NIX_TXSCHQ_CFG(struct rvu *rvu,
+ struct nix_txschq_config *req,
+ struct msg_rsp *rsp);
#endif /* RVU_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index e8374d9..56f242d 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -738,10 +738,10 @@ static void nix_reset_tx_linkcfg(struct rvu *rvu, int
blkaddr,
if (lvl == NIX_TXSCH_LVL_TL4)
rvu_write64(rvu, blkaddr, NIX_AF_TL4X_SDP_LINK_CFG(schq), 0x00);
- if (lvl != NIX_TXSCH_LVL_TL3)
+ if (lvl !=
[PATCH v2 01/17] octeontx2-af: NIX Tx scheduler queues alloc/free
From: Sunil Goutham
Added support for a PF/VF to allocate or free NIX transmit
scheduler queues via mbox. For setting up pkt transmission
priorities between queues, the scheduler queues have to be
contiguous w.r.t their HW indices. So both contiguous and
non-contiguous allocations are supported.
Upon receiving NIX_TXSCH_FREE mbox msg all scheduler queues
allocated to sending PFFUNC (PF/VF) will be freed. Selective
free is not supported.
Signed-off-by: Sunil Goutham
Signed-off-by: Nithin Dabilpuram
---
drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 36 +++-
drivers/net/ethernet/marvell/octeontx2/af/rvu.c| 4 +-
drivers/net/ethernet/marvell/octeontx2/af/rvu.h| 9 +-
.../net/ethernet/marvell/octeontx2/af/rvu_nix.c| 220 +
4 files changed, 265 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index c339024..282e556 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -15,6 +15,7 @@
#include
#include "rvu_struct.h"
+#include "common.h"
#define MBOX_SIZE SZ_64K
@@ -151,7 +152,9 @@ M(NPA_HWCTX_DISABLE,0x403, hwctx_disable_req,
msg_rsp) \
M(NIX_LF_ALLOC,0x8000, nix_lf_alloc_req, nix_lf_alloc_rsp)
\
M(NIX_LF_FREE, 0x8001, msg_req, msg_rsp) \
M(NIX_AQ_ENQ, 0x8002, nix_aq_enq_req, nix_aq_enq_rsp) \
-M(NIX_HWCTX_DISABLE, 0x8003, hwctx_disable_req, msg_rsp)
+M(NIX_HWCTX_DISABLE, 0x8003, hwctx_disable_req, msg_rsp) \
+M(NIX_TXSCH_ALLOC, 0x8004, nix_txsch_alloc_req, nix_txsch_alloc_rsp) \
+M(NIX_TXSCH_FREE, 0x8005, nix_txsch_free_req, msg_rsp)
/* Messages initiated by AF (range 0xC00 - 0xDFF) */
#define MBOX_UP_CGX_MESSAGES \
@@ -414,4 +417,35 @@ struct nix_aq_enq_rsp {
};
};
+/* Tx scheduler/shaper mailbox messages */
+
+#define MAX_TXSCHQ_PER_FUNC128
+
+struct nix_txsch_alloc_req {
+ struct mbox_msghdr hdr;
+ /* Scheduler queue count request at each level */
+ u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
+ u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
+};
+
+struct nix_txsch_alloc_rsp {
+ struct mbox_msghdr hdr;
+ /* Scheduler queue count allocated at each level */
+ u16 schq_contig[NIX_TXSCH_LVL_CNT];
+ u16 schq[NIX_TXSCH_LVL_CNT];
+ /* Scheduler queue list allocated at each level */
+ u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
+ u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
+};
+
+struct nix_txsch_free_req {
+ struct mbox_msghdr hdr;
+#define TXSCHQ_FREE_ALL BIT_ULL(0)
+ u16 flags;
+ /* Scheduler queue level to be freed */
+ u16 schq_lvl;
+ /* List of scheduler queues to be freed */
+ u16 schq;
+};
+
#endif /* MBOX_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
index c06cca9..9594432 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
@@ -80,7 +80,7 @@ int rvu_alloc_rsrc(struct rsrc_bmap *rsrc)
return id;
}
-static int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc)
+int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc)
{
int start;
@@ -105,7 +105,7 @@ static void rvu_free_rsrc_contig(struct rsrc_bmap *rsrc,
int nrsrc, int start)
bitmap_clear(rsrc->bmap, start, nrsrc);
}
-static bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc)
+bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc)
{
int start;
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index b48b5af..c402eba 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -180,11 +180,12 @@ static inline u64 rvupf_read64(struct rvu *rvu, u64
offset)
/* Function Prototypes
* RVU
*/
-
int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
+int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
+bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
int rvu_get_pf(u16 pcifunc);
struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
@@ -270,4 +271,10 @@ int rvu_mbox_handler_NIX_AQ_ENQ(struct rvu *rvu,
int rvu_mbox_handler_NIX_HWCTX_DISABLE(struct rvu *rvu,
struct hwctx_disable_req *req,
struct msg_rsp *rsp);
+int
[PATCH v2 05/17] octeontx2-af: Config NPC KPU engines with parser profile
From: Sunil Goutham
This patch configures all 16 KPUs and iKPU (pkinds) with
the KPU parser profile defined in npc_profile.h. Each KPU
engine has a 128 entry CAM, only CAM entries which are listed
in the profile are enabled and rest are left disabled.
Also
- Memory is allocated for pkind's bitmap and PFFUNC, interface
channel mapping.
- Added all CSR offsets of NPC HW block.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/af/Makefile | 2 +-
drivers/net/ethernet/marvell/octeontx2/af/npc.h| 100 ++
drivers/net/ethernet/marvell/octeontx2/af/rvu.c| 8 +
drivers/net/ethernet/marvell/octeontx2/af/rvu.h| 12 ++
.../net/ethernet/marvell/octeontx2/af/rvu_npc.c| 203 +
.../net/ethernet/marvell/octeontx2/af/rvu_reg.h| 61 +++
6 files changed, 385 insertions(+), 1 deletion(-)
create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/Makefile
b/drivers/net/ethernet/marvell/octeontx2/af/Makefile
index 264cbd7..06329ac 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/Makefile
+++ b/drivers/net/ethernet/marvell/octeontx2/af/Makefile
@@ -8,4 +8,4 @@ obj-$(CONFIG_OCTEONTX2_AF) += octeontx2_af.o
octeontx2_mbox-y := mbox.o
octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \
- rvu_reg.o
+ rvu_reg.o rvu_npc.o
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/npc.h
b/drivers/net/ethernet/marvell/octeontx2/af/npc.h
index 3e7ec10..58d8f0b 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/npc.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/npc.h
@@ -140,4 +140,104 @@ struct npc_kpu_profile {
struct npc_kpu_profile_action *action;
};
+/* NPC KPU register formats */
+struct npc_kpu_cam {
+#if defined(__BIG_ENDIAN_BITFIELD)
+ u64 rsvd_63_56 : 8;
+ u64 state : 8;
+ u64 dp2_data : 16;
+ u64 dp1_data : 16;
+ u64 dp0_data : 16;
+#else
+ u64 dp0_data : 16;
+ u64 dp1_data : 16;
+ u64 dp2_data : 16;
+ u64 state : 8;
+ u64 rsvd_63_56 : 8;
+#endif
+};
+
+struct npc_kpu_action0 {
+#if defined(__BIG_ENDIAN_BITFIELD)
+ u64 rsvd_63_57 : 7;
+ u64 byp_count : 3;
+ u64 capture_ena: 1;
+ u64 parse_done : 1;
+ u64 next_state : 8;
+ u64 rsvd_43: 1;
+ u64 capture_lid: 3;
+ u64 capture_ltype : 4;
+ u64 capture_flags : 8;
+ u64 ptr_advance: 8;
+ u64 var_len_offset : 8;
+ u64 var_len_mask : 8;
+ u64 var_len_right : 1;
+ u64 var_len_shift : 3;
+#else
+ u64 var_len_shift : 3;
+ u64 var_len_right : 1;
+ u64 var_len_mask : 8;
+ u64 var_len_offset : 8;
+ u64 ptr_advance: 8;
+ u64 capture_flags : 8;
+ u64 capture_ltype : 4;
+ u64 capture_lid: 3;
+ u64 rsvd_43: 1;
+ u64 next_state : 8;
+ u64 parse_done : 1;
+ u64 capture_ena: 1;
+ u64 byp_count : 3;
+ u64 rsvd_63_57 : 7;
+#endif
+};
+
+struct npc_kpu_action1 {
+#if defined(__BIG_ENDIAN_BITFIELD)
+ u64 rsvd_63_36 : 28;
+ u64 errlev : 4;
+ u64 errcode: 8;
+ u64 dp2_offset : 8;
+ u64 dp1_offset : 8;
+ u64 dp0_offset : 8;
+#else
+ u64 dp0_offset : 8;
+ u64 dp1_offset : 8;
+ u64 dp2_offset : 8;
+ u64 errcode: 8;
+ u64 errlev : 4;
+ u64 rsvd_63_36 : 28;
+#endif
+};
+
+struct npc_kpu_pkind_cpi_def {
+#if defined(__BIG_ENDIAN_BITFIELD)
+ u64 ena: 1;
+ u64 rsvd_62_59 : 4;
+ u64 lid: 3;
+ u64 ltype_match: 4;
+ u64 ltype_mask : 4;
+ u64 flags_match: 8;
+ u64 flags_mask : 8;
+ u64 add_offset : 8;
+ u64 add_mask : 8;
+ u64 rsvd_15: 1;
+ u64 add_shift : 3;
+ u64 rsvd_11_10 : 2;
+ u64 cpi_base : 10;
+#else
+ u64 cpi_base : 10;
+ u64 rsvd_11_10 : 2;
+ u64 add_shift : 3;
+ u64 rsvd_15: 1;
+ u64 add_mask : 8;
+ u64 add_offset : 8;
+ u64 flags_mask : 8;
+ u64 flags_match: 8;
+ u64 ltype_mask : 4;
+ u64 ltype_match: 4;
+ u64 lid: 3;
+ u64 rsvd_62_59 : 4;
+ u64 ena: 1;
+#endif
+};
#endif /* NPC_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
index 9594432..3cb7f76 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c
@@ -180,6 +180,9 @@ int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16
pcifunc)
bool is_pf;
switch (blktype) {
+ case
[PATCH v2 17/17] octeontx2-af: Support for NIXLF's UCAST/PROMISC/ALLMULTI modes
From: Sunil Goutham
By default NIXLF is set in UCAST mode. This patch adds a new
mailbox message which when sent by a RVU PF changes this default
mode. When promiscuous mode is needed, the reserved promisc entry
for each of RVU PF is setup to match against ingress channel number
only, so that all pkts on that channel are accepted and forwarded
to the mode change requesting PF_FUNC's NIXLF.
PROMISC and ALLMULTI modes are supported only for PFs, for VFs only
UCAST mode is supported.
Signed-off-by: Sunil Goutham
---
drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 11 -
drivers/net/ethernet/marvell/octeontx2/af/rvu.h| 5 ++
.../net/ethernet/marvell/octeontx2/af/rvu_nix.c| 33 +
.../net/ethernet/marvell/octeontx2/af/rvu_npc.c| 57 ++
4 files changed, 105 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index afa2ead..a15a59c 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -159,7 +159,8 @@ M(NIX_TXSCHQ_CFG, 0x8006, nix_txschq_config, msg_rsp)
\
M(NIX_STATS_RST, 0x8007, msg_req, msg_rsp) \
M(NIX_VTAG_CFG,0x8008, nix_vtag_config, msg_rsp) \
M(NIX_RSS_FLOWKEY_CFG, 0x8009, nix_rss_flowkey_cfg, msg_rsp) \
-M(NIX_SET_MAC_ADDR,0x800a, nix_set_mac_addr, msg_rsp)
+M(NIX_SET_MAC_ADDR,0x800a, nix_set_mac_addr, msg_rsp) \
+M(NIX_SET_RX_MODE, 0x800b, nix_rx_mode, msg_rsp)
/* Messages initiated by AF (range 0xC00 - 0xDFF) */
#define MBOX_UP_CGX_MESSAGES \
@@ -513,4 +514,12 @@ struct nix_set_mac_addr {
u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
};
+struct nix_rx_mode {
+ struct mbox_msghdr hdr;
+#define NIX_RX_MODE_UCAST BIT(0)
+#define NIX_RX_MODE_PROMISCBIT(1)
+#define NIX_RX_MODE_ALLMULTI BIT(2)
+ u16 mode;
+};
+
#endif /* MBOX_H */
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
index 93e6891..2c0580c 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
@@ -347,6 +347,8 @@ int rvu_mbox_handler_NIX_RSS_FLOWKEY_CFG(struct rvu *rvu,
int rvu_mbox_handler_NIX_SET_MAC_ADDR(struct rvu *rvu,
struct nix_set_mac_addr *req,
struct msg_rsp *rsp);
+int rvu_mbox_handler_NIX_SET_RX_MODE(struct rvu *rvu, struct nix_rx_mode *req,
+struct msg_rsp *rsp);
/* NPC APIs */
int rvu_npc_init(struct rvu *rvu);
@@ -355,6 +357,9 @@ int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
int nixlf, u64 chan, u8 *mac_addr);
+void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
+ int nixlf, u64 chan, bool allmulti);
+void rvu_npc_disable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf);
void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
int nixlf, u64 chan);
void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 3caf81b..8890c95 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -1745,6 +1745,39 @@ int rvu_mbox_handler_NIX_SET_MAC_ADDR(struct rvu *rvu,
return 0;
}
+int rvu_mbox_handler_NIX_SET_RX_MODE(struct rvu *rvu, struct nix_rx_mode *req,
+struct msg_rsp *rsp)
+{
+ bool allmulti = false, disable_promisc = false;
+ struct rvu_hwinfo *hw = rvu->hw;
+ u16 pcifunc = req->hdr.pcifunc;
+ struct rvu_pfvf *pfvf;
+ int blkaddr, nixlf;
+
+ pfvf = rvu_get_pfvf(rvu, pcifunc);
+ blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
+ if (!pfvf->nixlf || blkaddr < 0)
+ return NIX_AF_ERR_AF_LF_INVALID;
+
+ nixlf = rvu_get_lf(rvu, >block[blkaddr], pcifunc, 0);
+ if (nixlf < 0)
+ return NIX_AF_ERR_AF_LF_INVALID;
+
+ if (req->mode & NIX_RX_MODE_PROMISC)
+ allmulti = false;
+ else if (req->mode & NIX_RX_MODE_ALLMULTI)
+ allmulti = true;
+ else
+ disable_promisc = true;
+
+ if (disable_promisc)
+ rvu_npc_disable_promisc_entry(rvu, pcifunc, nixlf);
+ else
+ rvu_npc_install_promisc_entry(rvu, pcifunc, nixlf,
+ pfvf->rx_chan_base,
[PATCH v2 08/17] octeontx2-af: Update bcast list upon NIXLF alloc/free
From: Sunil Goutham
Upon NIXLF ALLOC/FREE, add or remove corresponding PF_FUNC from
the broadcast packet replication list of the CGX LMAC mapped
RVU PF.
Signed-off-by: Sunil Goutham
---
.../net/ethernet/marvell/octeontx2/af/rvu_nix.c| 133 +
1 file changed, 133 insertions(+)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 947424a..8333283 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -16,6 +16,8 @@
#include "rvu.h"
#include "cgx.h"
+static int nix_update_bcast_mce_list(struct rvu *rvu, u16 pcifunc, bool add);
+
enum mc_tbl_sz {
MC_TBL_SZ_256,
MC_TBL_SZ_512,
@@ -108,6 +110,7 @@ static int nix_interface_init(struct rvu *rvu, u16 pcifunc,
int type, int nixlf)
struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);
u8 cgx_id, lmac_id;
int pkind, pf;
+ int err;
pf = rvu_get_pf(pcifunc);
if (!is_pf_cgxmapped(rvu, pf) && type != NIX_INTF_TYPE_LBK)
@@ -130,9 +133,30 @@ static int nix_interface_init(struct rvu *rvu, u16
pcifunc, int type, int nixlf)
case NIX_INTF_TYPE_LBK:
break;
}
+
+ /* Add this PF_FUNC to bcast pkt replication list */
+ err = nix_update_bcast_mce_list(rvu, pcifunc, true);
+ if (err) {
+ dev_err(rvu->dev,
+ "Bcast list, failed to enable PF_FUNC 0x%x\n",
+ pcifunc);
+ }
return 0;
}
+static void nix_interface_deinit(struct rvu *rvu, u16 pcifunc, u8 nixlf)
+{
+ int err;
+
+ /* Remove this PF_FUNC from bcast pkt replication list */
+ err = nix_update_bcast_mce_list(rvu, pcifunc, false);
+ if (err) {
+ dev_err(rvu->dev,
+ "Bcast list, failed to disable PF_FUNC 0x%x\n",
+ pcifunc);
+ }
+}
+
static void nix_setup_lso_tso_l3(struct rvu *rvu, int blkaddr,
u64 format, bool v4, u64 *fidx)
{
@@ -786,6 +810,8 @@ int rvu_mbox_handler_NIX_LF_FREE(struct rvu *rvu, struct
msg_req *req,
if (nixlf < 0)
return NIX_AF_ERR_AF_LF_INVALID;
+ nix_interface_deinit(rvu, pcifunc, nixlf);
+
/* Reset this NIX LF */
err = rvu_lf_reset(rvu, block, nixlf);
if (err) {
@@ -1147,6 +1173,113 @@ static int nix_setup_mce(struct rvu *rvu, int mce, u8
op,
return 0;
}
+static int nix_update_mce_list(struct nix_mce_list *mce_list,
+ u16 pcifunc, int idx, bool add)
+{
+ struct mce *mce, *tail = NULL;
+ bool delete = false;
+
+ /* Scan through the current list */
+ hlist_for_each_entry(mce, _list->head, node) {
+ /* If already exists, then delete */
+ if (mce->pcifunc == pcifunc && !add) {
+ delete = true;
+ break;
+ }
+ tail = mce;
+ }
+
+ if (delete) {
+ hlist_del(>node);
+ kfree(mce);
+ mce_list->count--;
+ return 0;
+ }
+
+ if (!add)
+ return 0;
+
+ /* Add a new one to the list, at the tail */
+ mce = kzalloc(sizeof(*mce), GFP_KERNEL);
+ if (!mce)
+ return -ENOMEM;
+ mce->idx = idx;
+ mce->pcifunc = pcifunc;
+ if (!tail)
+ hlist_add_head(>node, _list->head);
+ else
+ hlist_add_behind(>node, >node);
+ mce_list->count++;
+ return 0;
+}
+
+static int nix_update_bcast_mce_list(struct rvu *rvu, u16 pcifunc, bool add)
+{
+ int err = 0, idx, next_idx, count;
+ struct nix_mce_list *mce_list;
+ struct mce *mce, *next_mce;
+ struct nix_mcast *mcast;
+ struct nix_hw *nix_hw;
+ struct rvu_pfvf *pfvf;
+ int blkaddr;
+
+ blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
+ if (blkaddr < 0)
+ return 0;
+
+ nix_hw = get_nix_hw(rvu->hw, blkaddr);
+ if (!nix_hw)
+ return 0;
+
+ mcast = _hw->mcast;
+
+ /* Get this PF/VF func's MCE index */
+ pfvf = rvu_get_pfvf(rvu, pcifunc & ~RVU_PFVF_FUNC_MASK);
+ idx = pfvf->bcast_mce_idx + (pcifunc & RVU_PFVF_FUNC_MASK);
+
+ mce_list = >bcast_mce_list;
+ if (idx > (pfvf->bcast_mce_idx + mce_list->max)) {
+ dev_err(rvu->dev,
+ "%s: Idx %d > max MCE idx %d, for PF%d bcast list\n",
+ __func__, idx, mce_list->max,
+ pcifunc >> RVU_PFVF_PF_SHIFT);
+ return -EINVAL;
+ }
+
+ spin_lock(>mce_lock);
+
+ err = nix_update_mce_list(mce_list, pcifunc, idx, add);
+ if (err)
+ goto end;
+
+ /* Disable MCAM entry in NPC */
+
+ if (!mce_list->count)
+
Re: [RFC PATCH v2 06/10] udp: cope with UDP GRO packet misdirection
On 2018-10-19 08:25, Paolo Abeni wrote:
In some scenarios, the GRO engine can assemble an UDP GRO packet
that ultimately lands on a non GRO-enabled socket.
This patch tries to address the issue explicitly checking for the UDP
socket features before enqueuing the packet, and eventually segmenting
the unexpected GRO packet, as needed.
We must also cope with re-insertion requests: after segmentation the
UDP code calls the helper introduced by the previous patches, as
needed.
Signed-off-by: Paolo Abeni
---
+static inline bool udp_unexpected_gso(struct sock *sk, struct sk_buff
*skb)
+{
+ return !udp_sk(sk)->gro_enabled && skb_is_gso(skb) &&
+ skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4;
+}
+
+static inline struct sk_buff *udp_rcv_segment(struct sock *sk,
+ struct sk_buff *skb)
+{
+ struct sk_buff *segs;
+
+ /* the GSO CB lays after the UDP one, no need to save and restore
any
+* CB fragment, just initialize it
+*/
+ segs = __skb_gso_segment(skb, NETIF_F_SG, false);
+ if (unlikely(IS_ERR(segs)))
+ kfree_skb(skb);
+ else if (segs)
+ consume_skb(skb);
+ return segs;
+}
+
+
Hi Paolo
Do we need to check for IS_ERR_OR_NULL(segs)
+void ip_protocol_deliver_rcu(struct net *net, struct sk_buff *skb, int
proto);
+
+static int udp_queue_rcv_skb(struct sock *sk, struct sk_buff *skb)
+{
+ struct sk_buff *next, *segs;
+ int ret;
+
+ if (likely(!udp_unexpected_gso(sk, skb)))
+ return udp_queue_rcv_one_skb(sk, skb);
+static int udpv6_queue_rcv_skb(struct sock *sk, struct sk_buff *skb)
+{
+ struct sk_buff *next, *segs;
+ int ret;
+
+ if (likely(!udp_unexpected_gso(sk, skb)))
+ return udpv6_queue_rcv_one_skb(sk, skb);
+
Is the "likely" required here?
HW can coalesce all incoming streams of UDP and may not know the socket
state.
In that case, a socket not having UDP GRO option might see a penalty
here.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
Re: Some suggestions for tc-tests
Hi Cong, > > 1. Create veth pair devices by its own. The most important thing for > tc-tests is to automate everything, it is not friendly for users to > create their own veth pair named v0p0 to just run the tests. tc-tests > should be able to create a veth pair with random names and clean up > them once it is finished. You can actually do this automatically in two steps: first, create a symlink to plugin-lib/nsPlugin.py in the plugins/ directory. Then, when running tdc, always invoke the '-n' option. This will execute all the commands inside a namespace *and* automatically create the veth pair that get used in the testing. It's referenced in the readme, but if you think it's useful to make it a default setup I could add an installation/setup script to tdc to create the symlink. > 2. Test iproute2 version or capability. Apparently my iproute2 doesn't > support tc filter chain yet, this makes many tests failed. Ideally, > each test should be able to check if the iproute2 supports the thing > it wants to test, if not just skip it, at least by default. So is this a version you compile yourself, or is it just the default /sbin/tc? Because you can specify the tc executable you want to use in tdc_config.py... But yes, we're looking at ways to make sure the support is there before running tests. We're hoping to send some patches soon. > 3. Is there anything in the tests that can be done only with Python3? > If we could lower the requirement to Python2, then it would be easier > to setup and run these tests. I'd have to go back and re-check to see what python 3-specific features I'm using, but there *are* some. Do you maybe have the ability to run a VM or Docker container on your system to run python 3? Thanks!
Re: [PATCH net 1/4] net/sched: act_gact: disallow 'goto chain' on fallback control action
Sat, Oct 20, 2018 at 11:33:07PM CEST, dcara...@redhat.com wrote:
>in the following command:
>
> # tc action add action random
>
>'goto chain x' is allowed only for c1: setting it for c2 makes the kernel
>crash with NULL pointer dereference, since TC core doesn't initialize the
>chain handle.
>
>Signed-off-by: Davide Caratti
>---
> net/sched/act_gact.c | 5 +
> 1 file changed, 5 insertions(+)
>
>diff --git a/net/sched/act_gact.c b/net/sched/act_gact.c
>index cd1d9bd32ef9..505138047e5c 100644
>--- a/net/sched/act_gact.c
>+++ b/net/sched/act_gact.c
>@@ -88,6 +88,11 @@ static int tcf_gact_init(struct net *net, struct nlattr
>*nla,
> p_parm = nla_data(tb[TCA_GACT_PROB]);
> if (p_parm->ptype >= MAX_RAND)
> return -EINVAL;
>+ if (TC_ACT_EXT_CMP(p_parm->paction, TC_ACT_GOTO_CHAIN)) {
>+ NL_SET_ERR_MSG(extack,
>+ "goto chain not allowed on fallback");
No need for a line-wrap. Otherwise
Acked-by: Jiri Pirko
[net-next:master 451/481] drivers/net/ethernet/amazon/ena/ena_com.h:1104:2: error: implicit declaration of function 'prefetchw'
Hi Netanel,
FYI, the error/warning still remains.
tree: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git
master
head: 21ea1d36f6dfcb1d59184937c672022d5d01902a
commit: 8c590f9776386b8f697fd0b7ed6142ae6e3de79e [451/481] net: ena: Fix
Kconfig dependency on X86
config: microblaze-allmodconfig (attached as .config)
compiler: microblaze-linux-gcc (GCC) 8.1.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 8c590f9776386b8f697fd0b7ed6142ae6e3de79e
# save the attached .config to linux build tree
GCC_VERSION=8.1.0 make.cross ARCH=microblaze
All errors (new ones prefixed by >>):
In file included from drivers/net/ethernet/amazon/ena/ena_com.c:33:
drivers/net/ethernet/amazon/ena/ena_com.h: In function
'ena_com_get_next_bounce_buffer':
>> drivers/net/ethernet/amazon/ena/ena_com.h:1104:2: error: implicit
>> declaration of function 'prefetchw' [-Werror=implicit-function-declaration]
prefetchw(bounce_buf_ctrl->base_buffer +
^
cc1: some warnings being treated as errors
vim +/prefetchw +1104 drivers/net/ethernet/amazon/ena/ena_com.h
1738cd3e Netanel Belgazal 2016-08-10 1092
689b2bda Arthur Kiyanovski 2018-10-11 1093 static inline u8
*ena_com_get_next_bounce_buffer(struct ena_com_io_bounce_buffer_control
*bounce_buf_ctrl)
689b2bda Arthur Kiyanovski 2018-10-11 1094 {
689b2bda Arthur Kiyanovski 2018-10-11 1095 u16 size, buffers_num;
689b2bda Arthur Kiyanovski 2018-10-11 1096 u8 *buf;
689b2bda Arthur Kiyanovski 2018-10-11 1097
689b2bda Arthur Kiyanovski 2018-10-11 1098 size =
bounce_buf_ctrl->buffer_size;
689b2bda Arthur Kiyanovski 2018-10-11 1099 buffers_num =
bounce_buf_ctrl->buffers_num;
689b2bda Arthur Kiyanovski 2018-10-11 1100
689b2bda Arthur Kiyanovski 2018-10-11 1101 buf =
bounce_buf_ctrl->base_buffer +
689b2bda Arthur Kiyanovski 2018-10-11 1102
(bounce_buf_ctrl->next_to_use++ & (buffers_num - 1)) * size;
689b2bda Arthur Kiyanovski 2018-10-11 1103
689b2bda Arthur Kiyanovski 2018-10-11 @1104
prefetchw(bounce_buf_ctrl->base_buffer +
689b2bda Arthur Kiyanovski 2018-10-11 1105
(bounce_buf_ctrl->next_to_use & (buffers_num - 1)) * size);
689b2bda Arthur Kiyanovski 2018-10-11 1106
689b2bda Arthur Kiyanovski 2018-10-11 1107 return buf;
689b2bda Arthur Kiyanovski 2018-10-11 1108 }
689b2bda Arthur Kiyanovski 2018-10-11 1109
:: The code at line 1104 was first introduced by commit
:: 689b2bdaaa1480ad2c14bdc4c6eaf38284549022 net: ena: add functions for
handling Low Latency Queues in ena_com
:: TO: Arthur Kiyanovski
:: CC: David S. Miller
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
Re: Improving accuracy of PHC readings
On Fri, Oct 19, 2018 at 11:51:37AM +0200, Miroslav Lichvar wrote: > A solution to this would be a new driver function that wraps the > latching register read with readings of the system clock and return > three timestamps instead of one. For example: > > ktime_get_real_ts64(_ts1); > IXGBE_READ_REG(hw, IXGBE_SYSTIMR); > ktime_get_real_ts64(_ts2); > phc_ts.tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML); > phc_ts.tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH); Makes sense... > The extra timestamp doesn't fit the API of the PTP_SYS_OFFSET ioctl, > so it would need to shift the timestamp it returns by the missing > intervals (assuming the frequency offset between the PHC and system > clock is small), or a new ioctl could be introduced that would return > all timestamps in an array looking like this: > > [sys, phc, sys, sys, phc, sys, ...] How about a new ioctl with number of trials as input and single offset as output? Then it would be up to the driver to implement the device-specific loop. Thanks, Richard
Re: Improving accuracy of PHC readings
On Fri, Oct 19, 2018 at 04:52:13PM +, Keller, Jacob E wrote: > Nice! I think this is good. I'd love to see some data to back it up, but it > makes sense to me. +1
Re: [PATCH net 2/4] net/sched: act_police: disallow 'goto chain' on fallback control action
Sat, Oct 20, 2018 at 11:33:08PM CEST, dcara...@redhat.com wrote:
>in the following command:
>
> # tc action add action police rate burst conform-exceed /
>
>'goto chain x' is allowed only for c1: setting it for c2 makes the kernel
>crash with NULL pointer dereference, since TC core doesn't initialize the
>chain handle.
>
>Signed-off-by: Davide Caratti
>---
> net/sched/act_police.c | 12 ++--
> 1 file changed, 10 insertions(+), 2 deletions(-)
>
>diff --git a/net/sched/act_police.c b/net/sched/act_police.c
>index 5d8bfa878477..3b793393efd1 100644
>--- a/net/sched/act_police.c
>+++ b/net/sched/act_police.c
>@@ -150,6 +150,16 @@ static int tcf_police_init(struct net *net, struct nlattr
>*nla,
> goto failure;
> }
>
>+ if (tb[TCA_POLICE_RESULT]) {
>+ police->tcfp_result = nla_get_u32(tb[TCA_POLICE_RESULT]);
>+ if (TC_ACT_EXT_CMP(police->tcfp_result, TC_ACT_GOTO_CHAIN)) {
>+ NL_SET_ERR_MSG(extack,
>+ "goto chain not allowed on fallback");
Also, no need for line-wrap
Acked-by: Jiri Pirko
>+ err = -EINVAL;
>+ goto failure;
>+ }
>+ }
>+
> spin_lock_bh(>tcf_lock);
> /* No failure allowed after this point */
> police->tcfp_mtu = parm->mtu;
>@@ -173,8 +183,6 @@ static int tcf_police_init(struct net *net, struct nlattr
>*nla,
> police->peak_present = false;
> }
>
>- if (tb[TCA_POLICE_RESULT])
>- police->tcfp_result = nla_get_u32(tb[TCA_POLICE_RESULT]);
> police->tcfp_burst = PSCHED_TICKS2NS(parm->burst);
> police->tcfp_toks = police->tcfp_burst;
> if (police->peak_present) {
>--
>2.17.1
>
Re: [PATCH net-next 3/4] net: phy-c45: Implement reset/suspend/resume callbacks
On 10/22/18 8:48 AM, Russell King - ARM Linux wrote:
> On Mon, Oct 22, 2018 at 01:47:48PM +0100, Jose Abreu wrote:
>> Hello,
>>
>> On 22-10-2018 13:28, Andrew Lunn wrote:
EXPORT_SYMBOL_GPL(gen10g_resume);
@@ -327,7 +381,7 @@ struct phy_driver genphy_10g_driver = {
.phy_id = 0x,
.phy_id_mask= 0x,
.name = "Generic 10G PHY",
- .soft_reset = gen10g_no_soft_reset,
+ .soft_reset = gen10g_soft_reset,
.config_init= gen10g_config_init,
.features = 0,
.aneg_done = genphy_c45_aneg_done,
>>> Hi Jose
>>>
>>> You need to be careful here. There is a reason this is called
>>> gen10g_no_soft_reset, rather than having an empty
>>> gen10g_soft_reset. Some PHYs break when you do a reset. So adding a
>>> gen10g_soft_reset is fine, but don't change this here, without first
>>> understanding the history, and talking to Russell King.
>>
>> Hmm, the reset function only interacts with standard PCS
>> registers, which should always be available ...
>>
>> >From my tests I need to do at least 1 reset during power-up so in
>> ultimate case I can add a feature quirk or similar.
>>
>> Russell, can you please comment ?
>
> Setting the reset bit on 88x3310 causes the entire device to become
> completely inaccessible until hardware reset. Therefore, this bit
> must _never_ be set for these devices. That said, we have a separate
> driver for these PHYs, but that will only be used for them if it's
> present in the kernel. If we accidentally fall back to the generic
> driver, then we'll screw the 88x3310 until a full hardware reset.
>
> We also have a bunch of net devices that make use of this crippled
> "generic" 10G support - we don't know whether resetting the PHY
> for those systems will cause a regression - maybe board firmware
> already configured the PHY? I can't say either way on that, except
> that we've had crippled 10G support in PHYLIB for a number of years
> now _with_ users, and adding reset support drastically changes the
> subsystem's behaviour for these users.
>
> I would recommend not touching the generic 10G driver, but instead
> implement your own driver for your PHY to avoid causing regressions.
>
Agreed.
--
Florian
Re: [iproute2 PATCH] bridge: fix vlan show stats formatting
On Sat, 20 Oct 2018 15:42:33 +0200 Tobias Jungel wrote: > The output of -statistics vlan show was broken previous change for json > output. This aligns the format to vlan show. > > Signed-off-by: Tobias Jungel This patch causes new warning: CC vlan.o vlan.c: In function ‘print_vlan_stats_attr’: vlan.c:492:2: warning: ‘ifname’ may be used uninitialized in this function [-Wmaybe-uninitialized] print_color_string(PRINT_FP, COLOR_IFNAME, ^~ NULL, "%-16s", ifname); ~~ Reverting the patch, please fix and resubmit.
Re: [PATCH iproute2 1/1] DEBUG: Fix make check when need build generate_nlmsg
Hi Stephen, > Applied, it seem to have gotten lost somewhere between my laptop and the repo. Thanks a lot for merging :). There is a patchset "Minor shell code cleanup", which has state Accepted, but not in git https://patchwork.ozlabs.org/project/netdev/list/?series=67063=* Did they got lost as well, or you don't agree with it? Kind regards, Petr
Re: [PATCH net-next 1/4] net: phy: Use C45 Helpers when forcing PHY
On 10/22/18 3:32 AM, Jose Abreu wrote:
> If PHY is in force state and we have a C45 phy we need to use the
> standard C45 helpers and not the C22 ones.
>
> Signed-off-by: Jose Abreu
> Cc: Andrew Lunn
> Cc: Florian Fainelli
> Cc: "David S. Miller"
> Cc: Joao Pinto
> ---
> drivers/net/phy/phy.c | 2 +-
> include/linux/phy.h | 8
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> index 1d73ac3309ce..0ff4946e208e 100644
> --- a/drivers/net/phy/phy.c
> +++ b/drivers/net/phy/phy.c
> @@ -995,7 +995,7 @@ void phy_state_machine(struct work_struct *work)
> }
> break;
> case PHY_FORCING:
> - err = genphy_update_link(phydev);
> + err = phy_update_link(phydev);
> if (err)
> break;
>
> diff --git a/include/linux/phy.h b/include/linux/phy.h
> index 3ea87f774a76..02c2ee8bc05b 100644
> --- a/include/linux/phy.h
> +++ b/include/linux/phy.h
> @@ -1044,6 +1044,14 @@ static inline int phy_read_status(struct phy_device
> *phydev)
> return genphy_read_status(phydev);
> }
>
> +static inline int phy_update_link(struct phy_device *phydev)
> +{
> + if (phydev->is_c45)
> + return gen10g_read_status(phydev);
Should not this be genphy_c45_read_link() for symmetry with
genphy_update_link() which only updates phydev->link?
--
Florian
Re: [PATCH net 0/4] net/sched: forbid 'goto_chain' on fallback actions
On 2018-10-20 5:33 p.m., Davide Caratti wrote: the following command: # tc actions add action police rate 1mbit burst 1k conform-exceed \ > pass / goto chain 42 generates a NULL pointer dereference when packets exceed the configured rate. Similarly, the following command: # tc actions add action pass random determ goto chain 42 2 makes the kernel crash with NULL dereference when the first packet does not match the 'pass' action. gact and police allow users to specify a fallback control action, that is stored in the action private data. 'goto chain x' never worked for these cases, since a->goto_chain handle was never initialized. There is only one goto_chain handle per TC action, and it is designed to be non-NULL only if tcf_action contains a 'goto chain' command. So, let's forbid 'goto chain' on fallback actions. Patch 1/4 and 2/4 change the .init() functions of police and gact, to let them return an error when users try to set 'goto chain x' in the fallback action. Patch 3/4 and 4/4 add TDC selftest coverage to this new behavior. For the series, Acked-by: Jamal Hadi Salim cheers, jamal
Re: [iproute PATCH] ip-route: Fix for memleak in error path
On Thu, 18 Oct 2018 14:30:31 +0200
Phil Sutter wrote:
> If call to rta_addattr_l() failed, parse_encap_seg6() would leak memory.
> Fix this by making sure calls to free() are not skipped.
>
> Fixes: bd59e5b1517b0 ("ip-route: Fix segfault with many nexthops")
> Signed-off-by: Phil Sutter
Applied, thanks.
Re: [iproute PATCH] rdma: Fix for ineffective check in add_filter()
On Thu, 18 Oct 2018 13:41:54 +0200
Phil Sutter wrote:
> With 'name' field defined as array in struct filters, it will always
> contain a value irrespective of whether a name was assigned or not.
>
> Fix this by turning the field into a const char pointer.
>
> Fixes: 8cd644095842a ("devlink: Add support for devlink resource abstraction")
> Signed-off-by: Phil Sutter
Applied, and fixed fixes
Re: [PATCH 0/9] net: simplify getting .driver_data
On 10/21/18 1:00 PM, Wolfram Sang wrote: > I got tired of fixing this in Renesas drivers manually, so I took the big > hammer. Remove this cumbersome code pattern which got copy-pasted too much > already: > > - struct platform_device *pdev = to_platform_device(dev); > - struct ep93xx_keypad *keypad = platform_get_drvdata(pdev); > + struct ep93xx_keypad *keypad = dev_get_drvdata(dev); > > A branch, tested by buildbot, can be found here: > > git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git > coccinelle/get_drvdata > > I have been asked if it couldn't be done for dev_set_drvdata as well. I > checked > it and did not find one occasion where it could be simplified like this. Not > much of a surprise because driver_data is usually set in probe() functions > which access struct platform_device in many other ways. > > I am open for other comments, suggestions, too, of course. Would it make sense to annotate platform_get_drvdata() with __deprecated or something like that to prevent further uses by driver authors? Do you mind submitting the cocci-script to the maintainers of the coccinelle scripts that way it can be included and run by automated tools? Thanks! > > Here is the cocci-script I created: > > @@ > struct device* d; > identifier pdev; > expression *ptr; > @@ > ( > - struct platform_device *pdev = to_platform_device(d); > | > - struct platform_device *pdev; > ... > - pdev = to_platform_device(d); > ) > <... when != pdev > - >dev > + d > ...> > > ptr = > - platform_get_drvdata(pdev) > + dev_get_drvdata(d) > > <... when != pdev > - >dev > + d > ...> > > Kind regards, > >Wolfram > > > Wolfram Sang (9): > net: dsa: bcm_sf2: simplify getting .driver_data > net: dsa: qca8k: simplify getting .driver_data > net: ethernet: cadence: macb_main: simplify getting .driver_data > net: ethernet: davicom: dm9000: simplify getting .driver_data > net: ethernet: smsc: smc91x: simplify getting .driver_data > net: ethernet: ti: cpsw: simplify getting .driver_data > net: ethernet: ti: davinci_emac: simplify getting .driver_data > net: ethernet: wiznet: w5300: simplify getting .driver_data > net: phy: mdio-mux-bcm-iproc: simplify getting .driver_data > > drivers/net/dsa/bcm_sf2.c| 6 ++ > drivers/net/dsa/qca8k.c | 6 ++ > drivers/net/ethernet/cadence/macb_main.c | 6 ++ > drivers/net/ethernet/davicom/dm9000.c| 6 ++ > drivers/net/ethernet/smsc/smc91x.c | 3 +-- > drivers/net/ethernet/ti/cpsw.c | 6 ++ > drivers/net/ethernet/ti/davinci_emac.c | 6 ++ > drivers/net/ethernet/wiznet/w5300.c | 6 ++ > drivers/net/phy/mdio-mux-bcm-iproc.c | 6 ++ > 9 files changed, 17 insertions(+), 34 deletions(-) > -- Florian
Re: [iproute PATCH] rdma: Don't pass garbage to rd_check_is_filtered()
On Thu, 18 Oct 2018 14:35:50 +0200
Phil Sutter wrote:
> Variables 'src_port' and 'dst_port' are initialized only if attributes
> RDMA_NLDEV_ATTR_RES_SRC_ADDR or RDMA_NLDEV_ATTR_RES_DST_ADDR are
> present. Make sure to pass them over to rd_check_is_filtered() only if
> that is the case.
>
> Fixes: 9a362cc71a455 ("rdma: Add CM_ID resource tracking information")
> Signed-off-by: Phil Sutter
Applied, thanks.
Re: [PATCH bpf-next] selftests/bpf: enable (uncomment) all tests in test_libbpf.sh
On Mon, 22 Oct 2018 11:00:27 +0100 Quentin Monnet wrote: > 2018-10-21 23:04 UTC+0200 ~ Jesper Dangaard Brouer > > On Sun, 21 Oct 2018 16:37:08 +0100 > > Quentin Monnet wrote: > > > >> 2018-10-21 11:57 UTC+0200 ~ Jesper Dangaard Brouer > >>> On Sat, 20 Oct 2018 23:00:24 +0100 > >>> Quentin Monnet wrote: > >>> > >> > >> [...] > >> > --- a/tools/testing/selftests/bpf/test_libbpf.sh > +++ b/tools/testing/selftests/bpf/test_libbpf.sh > @@ -33,17 +33,11 @@ trap exit_handler 0 2 3 6 9 > > libbpf_open_file test_l4lb.o > > -# TODO: fix libbpf to load noinline functions > -# [warning] libbpf: incorrect bpf_call opcode > -#libbpf_open_file test_l4lb_noinline.o > +libbpf_open_file test_l4lb_noinline.o > > -# TODO: fix test_xdp_meta.c to load with libbpf > -# [warning] libbpf: test_xdp_meta.o doesn't provide kernel version > -#libbpf_open_file test_xdp_meta.o > +libbpf_open_file test_xdp_meta.o > > -# TODO: fix libbpf to handle .eh_frame > -# [warning] libbpf: relocation failed: no section(10) > -#libbpf_open_file ../../../../samples/bpf/tracex3_kern.o > +libbpf_open_file ../../../../samples/bpf/tracex3_kern.o > >>> > >>> I don't like the ../../../../samples/bpf/ reference (even-through I > >>> added this TODO), as the kselftests AFAIK support installing the > >>> selftests and then this tests will fail. > >>> Maybe we can find another example kern.o file? > >>> (which isn't compiled with -target bpf) > >> > >> Hi Jesper, yeah maybe making the test rely on something from samples/bpf > >> instead of just the selftests/bpf directory is not a good idea. But > >> there is no program compiled without the "-target-bpf" in that > >> directory. What we could do is explicitly compile one without the flag > >> in the Makefile, as in the patch below, but I am not sure that doing so > >> is acceptable? > > > > I think it makes sense to have a test program compiled without the > > "-target-bpf", as that will happen for users. And I guess we can add > > some more specific test that are related to "-target-bpf". > > Alright, I can repost my second version that takes a test out of the > default target for building BPF programs, after the merge window. > Okay, guess there is no rush in getting this in now, and we can wait for after the merge window. > >> Or should tests for libbpf have a directory of their own, > >> with another Makefile? > > > > Hmm, I'm not sure about that idea. > > > > I did plan by naming the test "libbpf_open_file", what we add more > > libbpf_ prefixed tests to the test_libbpf.sh script, which should > > cover more aspects of the _base_ libbpf functionality. > > > >> Another question regarding the test with test_xdp_meta.o: does the fix I > >> suggested (setting a version in the .C file) makes sense, or did you > >> leave this test for testing someday that libbpf would be able to open > >> even programs that do not set a version (in which case this is still not > >> the case if program type is not provided, and in fact my fix ruins > >> everything? :s). > > > > Well, yes. I was hinting if we should relax the version requirement > > for e.g. XDP BPF progs. > > This is already the case. What happens for this test is that we never > tell libbpf that this program is XDP, we just ask it to open the ELF > file and the whole time libbpf treats it as a program of type > BPF_PROG_TYPE_UNSPEC. So we can fix the BPF source (by adding a version) > or we can fix test_libbpf_open.c (to tell libbpf this is XDP), but I > don't believe there is anything to add to libbpf in that regard. I think > we could simply remove the test on test_xdp_meta.o from test_libbpf.h, > actually. What is you opinion? Yes, we should likely just drop the test then. -- Best regards, Jesper Dangaard Brouer MSc.CS, Principal Kernel Engineer at Red Hat LinkedIn: http://www.linkedin.com/in/brouer
Re: [PATCH iproute2 1/1] DEBUG: Fix make check when need build generate_nlmsg
On Mon, 22 Oct 2018 19:03:41 +0200 Petr Vorel wrote: > Hi Stephen, > > > Applied, it seem to have gotten lost somewhere between my laptop and the > > repo. > Thanks a lot for merging :). > > There is a patchset "Minor shell code cleanup", which has state Accepted, but > not in git > https://patchwork.ozlabs.org/project/netdev/list/?series=67063=* > Did they got lost as well, or you don't agree with it? > > > Kind regards, > Petr Let me go hunting.
[PATCH v2 00/17] octeontx2-af: NPC parser and NIX blocks initialization
From: Sunil Goutham This patchset is a continuation to earlier submitted two patch series to add a new driver for Marvell's OcteonTX2 SOC's Resource virtualization unit (RVU) admin function driver. 1. octeontx2-af: Add RVU Admin Function driver https://www.spinics.net/lists/netdev/msg528272.html 2. octeontx2-af: NPA and NIX blocks initialization https://www.spinics.net/lists/netdev/msg529163.html This patch series adds more NIX block configuration logic and additionally adds NPC block parser profile configuration. In brief below is what this series adds. NIX block: - Support for PF/VF to allocate/free transmit scheduler queues, maintenance and their configuration. - Adds support for packet replication lists, only broadcast packets is covered for now. - Defines few RSS flow algorithms for HW to distribute packets. This is not the hash algorithsm (i.e toeplitz or crc32), here SW defines what fields in packet should HW take and calculate the hash. - Support for PF/VF to configure VTAG strip and capture capabilities. - Reset NIXLF statastics. NPC block: This block has multiple parser engines which support packet parsing at multiple layers and generates a parse result which is further used to generate a key. Based on packet field offsets in the key, SW can install packet forwarding rules. This patch series adds - Initial parser profile to be programmed into parser engines. - Default forwarding rules to forward packets to different logical interfaces having a NIXLF attached. - Support for promiscuous and multicast modes. Changes from v1: 1 Fixed kernel build failure when compiled with BIG_ENDIAN enabled. - Reported by Kbuild test robot 2 Fixed a warning observed when kernel is built with -Wunused-but-set-variable Geetha sowjanya (1): octeontx2-af: Config pkind for CGX mapped PFs Hao Zheng (1): octeontx2-af: Add NPC KPU profile Stanislaw Kardach (1): octeontx2-af: Add LMAC channel info to NIXLF_ALLOC response Sunil Goutham (12): octeontx2-af: NIX Tx scheduler queues alloc/free octeontx2-af: NIX Tx scheduler queue config support octeontx2-af: Config NPC KPU engines with parser profile octeontx2-af: Broadcast packet replication support octeontx2-af: Update bcast list upon NIXLF alloc/free octeontx2-af: Enable packet length and csum validation octeontx2-af: NPC MCAM and LDATA extract minimal configuration octeontx2-af: Install ucast and bcast pkt forwarding rules octeontx2-af: NIX Rx flowkey configuration for RSS octeontx2-af: Support for changing RSS algorithm octeontx2-af: Support for setting MAC address octeontx2-af: Support for NIXLF's UCAST/PROMISC/ALLMULTI modes Vamsi Attunuru (2): octeontx2-af: Reset NIXLF's Rx/Tx stats octeontx2-af: Support for VTAG strip and capture drivers/net/ethernet/marvell/octeontx2/af/Makefile |3 +- drivers/net/ethernet/marvell/octeontx2/af/cgx.c| 12 + drivers/net/ethernet/marvell/octeontx2/af/cgx.h|1 + drivers/net/ethernet/marvell/octeontx2/af/common.h | 50 + drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 110 +- drivers/net/ethernet/marvell/octeontx2/af/npc.h| 262 + .../ethernet/marvell/octeontx2/af/npc_profile.h| 5709 drivers/net/ethernet/marvell/octeontx2/af/rvu.c| 12 +- drivers/net/ethernet/marvell/octeontx2/af/rvu.h| 97 +- .../net/ethernet/marvell/octeontx2/af/rvu_cgx.c|7 +- .../net/ethernet/marvell/octeontx2/af/rvu_nix.c| 1067 .../net/ethernet/marvell/octeontx2/af/rvu_npc.c| 816 +++ .../net/ethernet/marvell/octeontx2/af/rvu_reg.c| 71 + .../net/ethernet/marvell/octeontx2/af/rvu_reg.h| 61 + .../net/ethernet/marvell/octeontx2/af/rvu_struct.h | 35 + 15 files changed, 8306 insertions(+), 7 deletions(-) create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/npc.h create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/npc_profile.h create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/rvu_npc.c create mode 100644 drivers/net/ethernet/marvell/octeontx2/af/rvu_reg.c -- 2.7.4
Re: [PATCH net-next 0/6 v2] qed*: Doorbell overflow recovery
From: Ariel Elior Date: Tue, 23 Oct 2018 08:35:43 +0300 > Please consider applying to net-next. Sorry, net-next is closed.
