Re: [Qemu-devel] [RFC v1 06/23] riscv: Add the tcg target registers

[Richard Henderson]

On 11/15/18 11:34 PM, Alistair Francis wrote:
> +
> +#define TCG_CT_CONST_ZERO  0x100
> +#define TCG_CT_CONST_S12   0x200
> +#define TCG_CT_CONST_N12   0x400

Logically this would go with patch 8.  But,

Reviewed-by: Richard Henderson 

r~

Re: [Qemu-devel] [RFC v1 03/23] linux-user: Add host dependency for RISC-V 64-bit

[Richard Henderson]

On 11/15/18 11:34 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis 
> Signed-off-by: Michael Clark 
> ---
>  linux-user/host/riscv64/hostdep.h | 11 +++
>  1 file changed, 11 insertions(+)
>  create mode 100644 linux-user/host/riscv64/hostdep.h


Reviewed-by: Richard Henderson 

r~

Re: [Qemu-devel] [RFC v1 05/23] riscv: Add the tcg-target header file

[Richard Henderson]

On 11/15/18 11:34 PM, Alistair Francis wrote:
> +#define TCG_TARGET_HAS_add2_i32 0
> +#define TCG_TARGET_HAS_sub2_i32 0

You're not allowed to not implement this for riscv-32,
along with brcond2 and setcond2.

> +#define TCG_TARGET_HAS_movcond_i32  0

The architecture manual suggests that implementations recognize short
branch-over and convert internally to predication.  Do any do that?

Even if they don't, you might implement it that way anyway, as the code size
savings are large vs the inline fallback (6 insns).  But you can definitely put
that off for a later patch.

> +#define TCG_TARGET_HAS_ext16u_i32   1

Really?  I thought this required two insns...  Or do you expand to shifts while
the default is x & 0x, which would take 3 insns?  I guess I'll find out as
I keep reading.  ;-)


r~

Re: [Qemu-devel] [PULL V2 24/26] net: ignore packet size greater than INT_MAX

[Dima Stepanov]

On Thu, Nov 15, 2018 at 10:47:04AM +0800, Jason Wang wrote:
> 
> On 2018/11/15 上午12:23, Dima Stepanov wrote:
> >On Wed, Nov 14, 2018 at 10:59:32AM +0800, Jason Wang wrote:
> >>On 2018/11/13 下午11:41, Dima Stepanov wrote:
> >>>Hi Jason,
> >>>
> >>>I know that this patch has been already merged to stable, but i have a
> >>>question:
> >>>
> >>>On Fri, Oct 19, 2018 at 11:22:23AM +0800, Jason Wang wrote:
> There should not be a reason for passing a packet size greater than
> INT_MAX. It's usually a hint of bug somewhere, so ignore packet size
> greater than INT_MAX in qemu_deliver_packet_iov()
> 
> CC:qemu-sta...@nongnu.org
> Reported-by: Daniel Shapira
> Reviewed-by: Michael S. Tsirkin
> Signed-off-by: Jason Wang
> ---
>   net/net.c | 7 ++-
>   1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/net/net.c b/net/net.c
> index c66847e..07c194a 100644
> --- a/net/net.c
> +++ b/net/net.c
> @@ -712,10 +712,15 @@ ssize_t qemu_deliver_packet_iov(NetClientState 
> *sender,
>   void *opaque)
>   {
>   NetClientState *nc = opaque;
> +size_t size = iov_size(iov, iovcnt);
>   int ret;
> +if (size > INT_MAX) {
> +return size;
> >>>Is it okay that the function returns ssize_t (signed), but the type of the
> >>>size variable is size_t (unsigned)? For now the top level routine checks
> >>>the return value only for 0, but anyway we can return negative value
> >>>here instead of positive. What do you think?
> >>>
> >>>Regards, Dima.
> >>>
> >>Any non zero value should be ok here. Actually I think because of the
> >>conversion from size_t to ssize_t, caller actually see negative value?
> >I believe it depends. If long (ssize_t and size_t type) is 8 bytes, then
> >the routine can sometimes return positive values and sometimes negative.
> >I fully agree that in the current case any non zero value should be
> >okay. I just wanted to point on the inconsistency in types and as a
> >result a return value.
> 
> 
> I see, want to post a patch for this?
> 
> Thanks

Yes, will take a look into it and prepare a patch.

Thanks, Dima.
> 
> 
> >Dima.
> >>Thanks
> >>

Re: [Qemu-devel] [RFC v1 04/23] exec: Add RISC-V GCC poison macro

[Richard Henderson]

On 11/15/18 11:34 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis 
> Signed-off-by: Michael Clark 
> ---
>  include/exec/poison.h | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Richard Henderson 

r~

Re: [Qemu-devel] KVM Forum block no[td]es

[Denis V . Lunev]

On 11/12/18 1:25 AM, Max Reitz wrote:
> This is what I’ve taken from two or three BoF-like get-togethers on
> blocky things.  Amendments are more than welcome, of course.
>
>
>
> Permission system
> =
>
> GRAPH_MOD
> -
>
> We need some way for the commit job to prevent graph changes on its
> chain while it is running.  Our current blocker doesn’t do the job,
> however.  What to do?
>
> - We have no idea how to make a *permission* work.  Maybe the biggest
>   problem is that it just doesn’t work as a permission, because the
>   commit job doesn’t own the BdrvChildren that would need to be
>   blocked (namely the @backing BdrvChild).
>
> - A property of BdrvChild that can be set by a non-parent seems more
>   feasible, e.g. a counter where changing the child is possible only
>   if the counter is 0.  This also actually makes sense in what it
>   means.
>   (We never quite knew what “taking the GRAPH_PERMISSION” or
>   “unsharing the GRPAH_MOD permission” was supposed to mean.  Figuring
>   that out always took like half an our in any face-to-face meeting,
>   and then we decided it was pretty much useless for any case we had
>   at hand.)
>
>
> Reopen
> --
>
> How should permissions be handled while the reopen is under way?
> Maybe we should take the union of @perm before and after, and the
> intersection of @shared before and after?
>
> - Taking permissions is a transaction that can fail.  Reopen, too, is
>   a transaction, and we want to go from the intermediate to the final
>   permissions in reopen’s commit part, so that transition is not
>   allowed to fail.
>   Since with the above model we would only relax things during that
>   transition (relinquishing bits from @perm and adding bits to
>   @shared), this transition should in theory be possible without any
>   failure.  However, in practice things are different, as permission
>   changes with file-posix nodes imply lock changes on the filesystem
>   -- which may always fail.  Arguably failures from changing the
>   file-posix locks can be ignored, because that just means that the
>   file claims more permissions to be taken and less to be shared than
>   is actually the case.  Which means you may not be able to open the
>   file in some other application, while you should be, but that’s the
>   benign kind of error.  You won’t be able to access data in a way
>   you shouldn’t be able to.
>   - Note that we have this issue already, so in general dropping
> permissions sometimes aborts because code assumes that dropping
> permissions is always safe and can never result in an error.  It
> seems best to ignore such protocol layer errors in the generic
> block layer rather than handling this in every protocol driver
> itself.
> (The block layer should discard errors from dropping permissions
> on the protocol layer.)
>
> - Is it possible that changing an option may require taking an
>   intermediate permission that is required neither before nor after
>   the reopen process?
>   Changing a child link comes to mind (like changing a child from one
>   BDS to another, where the visible data changes, which would mean we
>   may want to e.g. unshare CONSISTENT_READ during the reopen).
>   However:
>   1. It is unfeasible to unshare that for all child changes.
>  Effectively everything requires CONSISTENT_READ, and for good
>  reason.
>   2. Why would a user even change a BDS to something of a different
>  content?
>   3. Anything that currently allows you to change a child node assumes
>  that the user always changes it to something of the same content
>  (some take extra care to verify this, like mirror, which makes
>  sure that @replaces and the target are connected, and there are
>  only filter nodes in between).
>   Always using the same enforcing model as mirror does (no. 3 above)
>   does not really work, though, because one use case is to copy a
>   backing file offline to some different storage and then replace the
>   files via QMP.  To qemu, both files are completely unrelated.
>
>
> Block jobs, including blockdev-copy
> ===
>
> Example for use of the fleecing filter:
> - The real target is on slow storage.  Put an overlay on fast storage
>   on top of it.  Then use that overlay as the target of the fleecing
>   filter (and commit the data later or on the side), so that the
>   backup job does not slow down the guest.
>
> For a unified copy job, having a backup/fleecing filter is not a
> problem on the way.  One thing we definitely have to and can do is to
> copy common functionality into a shared file so that the different
> jobs can at least share that.
>
> COR/Stream:
> - There should be a way to discard ranges that have been copied into
>   the overlay from the backing files to save space
> - Also, the COR filter should integrated with the stream job (at some
>   point, as always)
>
> Hole punching with active commit:
> - Putting 

Re: [Qemu-devel] [RFC v1 02/23] linux-user: Add host dependency for RISC-V 32-bit

[Richard Henderson]

On 11/15/18 11:34 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis 
> Signed-off-by: Michael Clark 
> ---
>  linux-user/host/riscv32/hostdep.h | 11 +++
>  1 file changed, 11 insertions(+)
>  create mode 100644 linux-user/host/riscv32/hostdep.h

Reviewed-by: Richard Henderson 

r~

Re: [Qemu-devel] [RFC v1 02/23] linux-user: Add host dependency for RISC-V 32-bit

[Richard Henderson]

On 11/15/18 11:34 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis 
> Signed-off-by: Michael Clark 
> ---
>  linux-user/host/riscv32/hostdep.h | 11 +++
>  1 file changed, 11 insertions(+)
>  create mode 100644 linux-user/host/riscv32/hostdep.h

Reviewed-by: Richard Henderson 

r~

Re: [Qemu-devel] [RFC v1 01/23] elf.h: Add the RISCV ELF magic numbers

[Richard Henderson]

On 11/15/18 11:34 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis 
> Signed-off-by: Michael Clark 
> ---
>  include/elf.h | 55 +++
>  1 file changed, 55 insertions(+)

Reviewed-by: Richard Henderson 

r~

Re: [Qemu-devel] [PATCH for-3.2 00/41] RFC: slirp: make it again a standalone project

[Akihiro Suda]

> One change I am aware of in the forked version is the possibility
to tweak the MTU and AFAIK this is the only blocker from adopting
libslirp immediately.
> Akihiro, is there anything more that could block slirp4netns from
just using libslirp once it is available?

No, the only blocker is MTU (which significantly improves the bandwidth
from 1.07 Gbps to 9.21 Gbps :
https://github.com/rootless-containers/slirp4netns/tree/19ec5cf6b8f562ebaed6d4004c8b172907ea6adb#benchmarks
)

In future I think we want to support checksum offloading and
multiqueue/multithread, but these can be experimented and discussed after
we get support for the standalone libslirp.
https://github.com/rootless-containers/slirp4netns/issues/16
https://github.com/rootless-containers/slirp4netns/issues/17


2018年11月16日(金) 0:49 Giuseppe Scrivano :

> Daniel P. Berrangé  writes:
>
> > On Wed, Nov 14, 2018 at 04:36:02PM +0400, Marc-André Lureau wrote:
> >> Hi,
> >>
> >> Based-on: https://people.debian.org/~sthibault/qemu.git/ slirp branch
> >>
> >> This series goal is to allow building libslirp as an independent
> library.
>
> Marc-André, thanks for working on this!
>
>
> > At least half of the patches in this series are deleting unused or
> > unreachable code. I'd suggest you send all of those as a non-RFC
> > series, as they are things we could merge straight away regardless
> > of whether/when slirp becomes a separate library.
> >
> >> While looking at making SLIRP a seperate running process, I thought
> >> that having an independent library from QEMU would be a first step.
> >>
> >> There has been some attempts to make slirp a seperate project in the
> past.
> >> (https://lists.gnu.org/archive/html/qemu-devel/2017-02/msg01092.html)
> >> Unfortunately, they forked from QEMU and didn't provide enough
> >> compatibility for QEMU to make use of it (in particular, vmstate
> >> handling was removed, they lost git history etc). Furthermore, they
> >> are not maintained as far as I can see.
> >
> > More recently there is this fun project which just pulled in the
> > QEMU code and chopped out everything todo with slirp:
> >
> >   https://github.com/rootless-containers/slirp4netns
>
> to give a little bit of background on slirp4netns:
>
> slirp4netns is used for setting up the network in a network namespace
> without requiring root privileges.
>
> It is already used by Podman and Buildah to set up the network for
> rootless containers, so they won't be limited to run in the host network
> namespace or require a suid helper.
>
> Coincidentally just today I was working on a slirp4netns change for
> spawning a QEMU process instead of using the forked version.
> I'd prefer to not rely on the slirp forked version, but this costs the
> access to the underlying knobs.  With a separate libslirp project, this
> is not needed anymore.
>
> One change I am aware of in the forked version is the possibility to
> tweak the MTU and AFAIK this is the only blocker from adopting libslirp
> immediately.
> Akihiro, is there anything more that could block slirp4netns from just
> using libslirp once it is available?
>
> Regards,
> Giuseppe
>

Re: [Qemu-devel] [PATCH 0/4] keymaps: drop support for include files

[Thomas Huth]

On 2018-11-15 13:32, Gerd Hoffmann wrote:
> Gerd Hoffmann (4):
>   keymaps: remove modifiers include
>   keymaps: drop nl-be map
>   keymaps: remove common include
>   keymaps: drop support for include files

Please give some rationale in the cover letter... why do you want to
drop support for this?

 Thomas

Re: [Qemu-devel] [PATCH for-3.1 2/2] hw/block/onenand: use qemu_log_mask() for reporting

[Thomas Huth]

On 2018-11-15 15:35, Peter Maydell wrote:
> Update the onenand device to use qemu_log_mask() for reporting
> guest errors and unimplemented features, rather than plain
> fprintf() and hw_error().
> 
> (We leave the hw_error() in onenand_reset(), as that is
> triggered by a failure to read the underlying block device
> for the bootRAM, not by guest action.)
> 
> Signed-off-by: Peter Maydell 
> ---
>  hw/block/onenand.c | 22 +-
>  1 file changed, 13 insertions(+), 9 deletions(-)
Reviewed-by: Thomas Huth 

Re: [Qemu-devel] [PATCH for-4.0 00/17] tcg: Move softmmu out-of-line

[Emilio G. Cota]

On Thu, Nov 15, 2018 at 20:13:38 -0500, Emilio G. Cota wrote:
> I'll generate now some more perf numbers that we could include in the
> commit logs.

SPEC numbers are a net perf decrease, unfortunately:

 Softmmu speedup for SPEC06int (test set)
   1.1 +-+--+++++++---++++++--+-+
   ||
   |  aft+++|
  1.05 +-+|...+-+
   |   +++| |
   |   +++  | | |
   |   +++  |   | | |
 1 +-***+++-+
   || |  *  *    *|*|
   |   ***  +++   |  *  * * |*   +++   *| *  *|*|
  0.95 +-+.*|*..***...|..*..*.*.|*..+++...|*|.*.+++..*|*..+++.+-+
   |   *|*  *+*  *** *  * * |*   ||  +++   *| * ***  *|*  ***   |
   |   *+*  * *  *|* *  * *++*   |    |*| * *+*  *|*  *+*   |
   |   * *  * *  *|* *  * *  *  * |*   *++* * *  *+*  * *   |
   0.9 +-+.*.*..*.*..*+*.*..*.*..*.*.|*.*.|*.*|.*..*..*.*.*..*.*..*.*.+-+
   |   * *  * *  * * *  * *  * *++* *++* *++* +++  *  * * *  * *  * *   |
   |   * *  * *  * * *  * *  * *  * *  * *  *  |   *  * * *  * *  * *   |
  0.85 +-+.*.*..*.*..*.*.*..*.*..*.*..*.*..*.*..*..|...*..*.*.*..*.*..*.*.+-+
   |   * *  * *  * * *  * *  * *  * *  * *  *  |   *  * * *  * *  * *   |
   |   * *  * *  * * *  * *  * *  * *  * *  *  *  * * *  * *  * *   |
   |   * *  * *  * * *  * *  * *  * *  * *  * *| * *  * * *  * *  * *   |
   0.8 +-+.*.*..*.*..*.*.*..*.*..*.*..*.*..*.*..*.*|.*.*..*.*.*..*.*..*.*.+-+
   |   * *  * *  * * *  * *  * *  * *  * *  * *| * *  * * *  * *  * *   |
   |   * *  * *  * * *  * *  * *  * *  * *  * *++* *  * * *  * *  * *   |
  0.75 +-+-***--***--***--------***--***--***-+-+
401.bzi403.g429445.g456.462.libq464.h471.omn4483.xalancbgeomean
  png: https://imgur.com/aO39gyP

Turns out that the additional instructions are the problem,
despite the much lower icache miss rate. For instance, here
are some numbers for h264ref running on the not-so-recent
Xeon E5-2643 (i.e. Sandy Bridge):

- Before:
 1,137,737,512,668  instructions  #2.02  insns per cycle
   563,574,505,040  cycles
 5,663,616,681  L1-icache-load-misses
 164.091239774 seconds time elapsed

- After:
 1,216,600,582,476  instructions  #2.06  insns per cycle

   591,888,969,223  cycles  

 3,082,426,508  L1-icache-load-misses   


 172.232292897 seconds time elapsed

It's possible that newer machines with larger reorder buffers
will be able to take better advantage of the higher instruction
locality, hiding the latency of having to execute more instructions.
I'll test on Skylake tomorrow.

Thanks,

E.

Re: [Qemu-devel] Are FreeBSD guest images working?

[Peter Xu]

On Thu, Nov 15, 2018 at 08:24:23PM -0700, Warner Losh wrote:
> On Thu, Nov 15, 2018 at 7:54 PM Peter Xu  wrote:
> 
> > On Thu, Nov 15, 2018 at 11:05:33AM +0100, Philippe Mathieu-Daudé wrote:
> > > On 15/11/18 9:58, Peter Xu wrote:
> > > > Hi, the list,
> > > >
> > > > I am trying to boot a FreeBSD guest but failed.  It hangs at the
> > > > kernel booting phase:
> > > >
> > > > /boot/ker]el/kernel text=0x14ed860 data=0x132538+0x4baa68
> > syms=[0x8+0x159ee8+0x8
> > > > Booting...
> > > > (nothing more)
> > > >
> > > > It's just as simple as downloading the image and boot so I can't think
> > > > of anything strange within my procedures so far:
> > > >
> > > > https://wiki.qemu.org/Hosts/BSD#FreeBSD
> > > >
> > > > I also tried the latest image here:
> > > >
> > > >
> > https://download.freebsd.org/ftp/releases/VM-IMAGES/11.2-RELEASE/amd64/Latest/FreeBSD-11.2-RELEASE-amd64.qcow2.xz
> > > >
> > > > but it's having the same problem as 11.0.
> > > >
> > > > Am downloading an fresh ISO, but before I continue I'm just curious on
> > > > whether anyone is using these images and whether there's quick answers
> > > > to what I have encountered.
> > > >
> > > > Thanks in advance,
> > >
> > > I use 'make vm-build-freebsd' which works, but the image comes
> > > pre-installed.
> >
> > It's because I'm always with no-gui mode and FreeBSD images has no
> > serial enabled by default.  I was possibly spoiled by the nice
> > virt-builder before with consoles setup already for all Linux guest
> > images.  Thanks for answering!
> >
> 
> I'm coming to the game late...
> 
> I run FreeBSD in qemu all the time, but I build images from source to test
> the boot loader and it's all serial and my test scripts are tuned to that.
> I rarely use the pre-built images, however.
> 
> If there's ways that we can build images that work better than we're doing
> right now to make the experience better, like making sure we enable the
> dual console support for them... We're late in our release cycle, but if
> what we need to change is what I think we need to change, we still have
> time for it.
> 
> In the mean time I'll read through wiki and see if there's anything
> obviously wrong...

I would guess there aren't many people like me to prefer booting a VM
using console, though I agree that it'll be nice if we put something
into the prebuilt images like what's suggested by Ilya (and so far I
don't see anything bad with that):

[root@freebsd ~]# cat /boot/loader.conf
boot_multicons="YES"
boot_serial="YES"
comconsole_speed="115200"
console="comconsole,vidconsole"

Anyway, thanks for your work on either the wiki or the images, they
are really helpful to people like me.

Regards,

-- 
Peter Xu

Re: [Qemu-devel] [Qemu-arm] [PATCH V7 4/6] hw/arm/virt: Use the pvpanic device

[peng.hao2]

>Hi,
>
>On 2018/11/16 18:50, Peng Hao wrote:
>>   Add pvpanic device in arm virt machine.
[...]
>>
>> +create_pvpanic_device(vms);
>> +
>It should not create pvpanic by default. It should be configurable via
>-device pvpanic.
yeah ,it is a problem. I will resolve it.
Thanks.
>Thanks,
>Shannon

Re: [Qemu-devel] [PATCH for-4.0 v2] virtio: Provide version-specific variants of virtio PCI devices

[Eduardo Habkost]

On Thu, Nov 15, 2018 at 05:29:24PM +0100, Andrea Bolognani wrote:
> On Wed, 2018-11-14 at 21:38 -0200, Eduardo Habkost wrote:
> > Many of the current virtio-*-pci device types actually represent
> > 3 different types of devices:
> > * virtio 1.0 non-transitional devices
> > * virtio 1.0 transitional devices
> > * virtio 0.9 ("legacy device" in virtio 1.0 terminology)
> > 
> > That would be just an annoyance if it didn't break our device/bus
> > compatibility QMP interfaces.  With this multi-purpose device
> > type, there's no way to tell management software that
> > transitional devices and legacy devices require a Conventional
> > PCI bus.
> > 
> > The multi-purpose device types would also prevent us from telling
> > management software what's the PCI vendor/device ID for them,
> > because their PCI IDs change at runtime depending on the bus
> > where they were plugged.
> > 
> > This patch adds separate device types for each of those virtio
> > device flavors:
> > 
> > - virtio-*-pci: the existing multi-purpose device types
> >   - Configurable using `disable-legacy` and `disable-modern`
> > properties
> >   - Legacy driver support is automatically enabled/disabled
> > depending on the bus where it is plugged
> >   - Supports Conventional PCI and PCI Express buses
> > (but Conventional PCI is incompatible with
> > disable-legacy=off)
> >   - Changes PCI vendor/device IDs at runtime
> > - virtio-*-pci-transitional: virtio-1.0 device supporting legacy drivers
> >   - Supports Conventional PCI buses only, because
> > it has a PIO BAR
> > - virtio-*-pci-non-transitional: modern-only
> >   - Supports both Conventional PCI and PCI Express buses
> 
> So, my understanding was that transitional devices would be suitable
> for both PCI and PCIe slots and non-transitional devices could only
> work in PCIe slots, but based on the above it looks like I got it
> pretty much completely wrong? I'm not too surprised that would be
> the case, to be honest: keeping this stuff straight in my head has
> always been a bit of a challenge, so I can't possibly not welcome a
> proposal like this, which will spell it out a bit more :)

That's possibly my fault.  I described it completely wrong in one
message in the v1 thread.


> 
> Let me try to map the interactions out:
> 
>   * virtio-*-pci-transitional
> + plugged into PCI slot
>   - shows up as vendor1/device1
> + plugged into PCIe slot
>   - doesn't work
> 
>   * virtio-*-pci-non-transitional
> + plugged into PCI slot
>   - shows up as vendor2/device2
> + plugged into PCIe slot
>   - shows up as vendor2/device2
> 
>   * virtio-*-pci
> + plugged into PCI slot
>   - shows up as vendor1/device1
> (same as virtio-*-pci-transitional)
> + plugged into PCIe slot
>   - shows up as vendor2/device2
> (same as virtio-*-pci-non-transitional)
> 
> Does that look about right?

Exactly.

> 
> Once all the various pieces have fallen into place, when adding a
> device to a guest running a modern OS we would find out through
> libosinfo that it supports vendor2/device2 (and vendor1/device1
> too, I guess?) so we would choose the non-transitional variant and
> plug it into PCIe when possible (q35) or PCI otherwise (pc); on
> the other hand, an older guest OS like CentOS 6 will only advertise
> support for vendor1/device1, so we'd have to use the transitional
> variant instead and plug it into a PCI slot regardless of the
> machine type, which more specifically means building a
> pcie.0 <- pcie-root-port <- pcie-pci-bridge topology for q35
> guests.
> 
> If all of the above is correct, then it sounds like a feasible
> enough plan to me, though of course it be a long time before users
> and management applications can rely on these new device types
> being available in downstream distributions...
> 
> One thing that I'm very much not convinced about is the naming,
> specifically leaving the virtio revision out: I get it that we
> Should Never Need™ another major version of the spec, but I'm
> afraid discounting the possibility outright might prove to be
> shortsighted and come back to bite us later, so I'd much rather
> keep it.
> 
> And once that's done, "non-transitional" (while matching the
> language of the spec) starts to look a bit unnecessary when you
> could simply have
> 
>   virtio-*-pci
>   virtio-*-pci-1
>   virtio-*-pci-1-transitional
> 
> instead. But I don't feel as strongly about this as I do about
> keeping the virtio revision in the device name :)

I like that suggestion.  Makes the device names more explicit
_and_ shorter.  I'll do that in v3.

-- 
Eduardo

[Qemu-devel] [PULL] net/filter-rewriter.c: Fix coverity static analysis issue

[Jason Wang]

From: Zhang Chen 

The original code just follow the TCP state diagram,
but in this case, we can skip the TCPS_TIME_WAIT state to simplify
the implementation.

Signed-off-by: Zhang Chen 
Signed-off-by: Jason Wang 
---
 net/filter-rewriter.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/net/filter-rewriter.c b/net/filter-rewriter.c
index bb8f4d9..2e26839 100644
--- a/net/filter-rewriter.c
+++ b/net/filter-rewriter.c
@@ -155,12 +155,13 @@ static int handle_primary_tcp_pkt(RewriterState *rf,
  * Active close step 2.
  */
 if (conn->tcp_state == TCPS_FIN_WAIT_1) {
-conn->tcp_state = TCPS_TIME_WAIT;
 /*
  * For simplify implementation, we needn't wait 2MSL time
  * in filter rewriter. Because guest kernel will track the
  * TCP status and wait 2MSL time, if client resend the FIN
  * packet, guest will apply the last ACK too.
+ * So, we skip the TCPS_TIME_WAIT state here and go straight
+ * to TCPS_CLOSED state.
  */
 conn->tcp_state = TCPS_CLOSED;
 g_hash_table_remove(rf->connection_track_table, key);
-- 
2.5.0

[Qemu-devel] [PULL] Net patches

[Jason Wang]

The following changes since commit d835c6192495dc5b2c3a15a0761eb57d8d310828:

  Merge remote-tracking branch 
'remotes/stefanberger/tags/pull-tpm-2018-11-15-1' into staging (2018-11-15 
14:18:25 +)

are available in the git repository at:

  https://github.com/jasowang/qemu.git tags/net-pull-request

for you to fetch changes up to 013a62020a92f371555c67342424f2f944b62be4:

  net/filter-rewriter.c: Fix coverity static analysis issue (2018-11-16 
11:08:26 +0800)




Zhang Chen (1):
  net/filter-rewriter.c: Fix coverity static analysis issue

 net/filter-rewriter.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Re: [Qemu-devel] [Qemu-arm] [PATCH V7 4/6] hw/arm/virt: Use the pvpanic device

[Shannon Zhao]

Hi,

On 2018/11/16 18:50, Peng Hao wrote:

  Add pvpanic device in arm virt machine.

Signed-off-by: Peng Hao
Signed-off-by: Philippe Mathieu-Daudé
---
  default-configs/arm-softmmu.mak |  1 +
  hw/arm/virt.c   | 21 +
  include/hw/arm/virt.h   |  1 +
  3 files changed, 23 insertions(+)

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 2420491..50345df 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -159,3 +159,4 @@ CONFIG_PCI_DESIGNWARE=y
  CONFIG_STRONGARM=y
  CONFIG_HIGHBANK=y
  CONFIG_MUSICPAL=y
+CONFIG_PVPANIC=y
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 9f67782..c4f29c8 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -59,6 +59,7 @@
  #include "qapi/visitor.h"
  #include "standard-headers/linux/input.h"
  #include "hw/arm/smmuv3.h"
+#include "hw/misc/pvpanic.h"
  
  #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \

  static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
@@ -143,6 +144,7 @@ static const MemMapEntry a15memmap[] = {
  [VIRT_GPIO] =   { 0x0903, 0x1000 },
  [VIRT_SECURE_UART] ={ 0x0904, 0x1000 },
  [VIRT_SMMU] =   { 0x0905, 0x0002 },
+[VIRT_PVPANIC] ={ 0x0907, 0x0002 },
  [VIRT_MMIO] =   { 0x0a00, 0x0200 },
  /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
  [VIRT_PLATFORM_BUS] =   { 0x0c00, 0x0200 },
@@ -190,6 +192,23 @@ static bool cpu_type_valid(const char *cpu)
  return false;
  }
  
+static void create_pvpanic_device(const VirtMachineState *vms)

+{
+char *nodename;
+hwaddr base = vms->memmap[VIRT_PVPANIC].base;
+hwaddr size = vms->memmap[VIRT_PVPANIC].size;
+
+sysbus_create_simple(TYPE_PVPANIC_MMIO, base, NULL);
+
+nodename = g_strdup_printf("/pvpanic-mmio@%" PRIx64, base);
+qemu_fdt_add_subnode(vms->fdt, nodename);
+qemu_fdt_setprop_string(vms->fdt, nodename,
+"compatible", "qemu,pvpanic-mmio");
+qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
+ 2, base, 2, size);
+g_free(nodename);
+}
+
  static void create_fdt(VirtMachineState *vms)
  {
  void *fdt = create_device_tree(>fdt_size);
@@ -1531,6 +1550,8 @@ static void machvirt_init(MachineState *machine)
  
  create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem);
  
+create_pvpanic_device(vms);

+
It should not create pvpanic by default. It should be configurable via 
-device pvpanic.


Thanks,
Shannon

Re: [Qemu-devel] [Qemu-block] [PATCH] migration/block-dirty-bitmap: fix Coverity CID1390625

[John Snow]

On 11/15/18 6:48 AM, Peter Maydell wrote:
> On 17 October 2018 at 10:51, Stefan Hajnoczi  wrote:
>> On Tue, Oct 16, 2018 at 04:20:18PM +0300, Vladimir Sementsov-Ogievskiy wrote:
>>> Theoretically possible that we finish the skipping loop with bs = NULL
>>> and the following code will crash trying to dereference it. Fix that.
>>>
>>> Signed-off-by: Vladimir Sementsov-Ogievskiy 
>>> ---
>>>  migration/block-dirty-bitmap.c | 4 
>>>  1 file changed, 4 insertions(+)
>>>
>>> diff --git a/migration/block-dirty-bitmap.c b/migration/block-dirty-bitmap.c
>>> index 477826330c..6de808f95f 100644
>>> --- a/migration/block-dirty-bitmap.c
>>> +++ b/migration/block-dirty-bitmap.c
>>> @@ -288,6 +288,10 @@ static int init_dirty_bitmap_migration(void)
>>>  bs = backing_bs(bs);
>>>  }
>>>
>>> +if (!bs || bs->implicit) {
>>> +continue;
>>> +}
>>> +
>>>  for (bitmap = bdrv_dirty_bitmap_next(bs, NULL); bitmap;
>>>   bitmap = bdrv_dirty_bitmap_next(bs, bitmap))
>>>  {
>>
>> Previous discussion:
>> http://qemu.11.n7.nabble.com/PATCH-migration-Appease-coverity-skip-empty-block-trees-td582504.html
>>
>> I've CCed John so he can take a look.
> 
> So have you block-layer folks figured out how you want to address
> this Coverity issue yet?
> 
> thanks
> -- PMM
> 

I looked again. I think Vladimir's patch will shut up Coverity for sure,
feel free to apply it if you want this out of your hair.

Stefan suggests the following, however;


diff --git a/migration/block-dirty-bitmap.c b/migration/block-dirty-bitmap.c
index 5e90f44c2f..00c068fda3 100644
--- a/migration/block-dirty-bitmap.c
+++ b/migration/block-dirty-bitmap.c
@@ -284,7 +284,7 @@ static int init_dirty_bitmap_migration(void)
 const char *drive_name = bdrv_get_device_or_node_name(bs);

 /* skip automatically inserted nodes */
-while (bs && bs->drv && bs->implicit) {
+while (bs->drv && bs->implicit) {
 bs = backing_bs(bs);
 }


that by removing the assumption that bs could ever be null here (it
shouldn't), that we'll coax coverity into not warning anymore. I don't
know if that will work, because backing_bs can theoretically return NULL
and might convince coverity there's a problem. In practice it won't be.

I don't know how to check this to see if Stefan's suggestion is appropriate.

For such a small, trivial issue though, just merge this and be done with
it, in my opinion. If you want to take this fix directly as a "build
fix" I wouldn't object.

I'm sorry for the fuss.

Re: [Qemu-devel] Are FreeBSD guest images working?

[Warner Losh]

On Thu, Nov 15, 2018 at 7:54 PM Peter Xu  wrote:

> On Thu, Nov 15, 2018 at 11:05:33AM +0100, Philippe Mathieu-Daudé wrote:
> > On 15/11/18 9:58, Peter Xu wrote:
> > > Hi, the list,
> > >
> > > I am trying to boot a FreeBSD guest but failed.  It hangs at the
> > > kernel booting phase:
> > >
> > > /boot/ker]el/kernel text=0x14ed860 data=0x132538+0x4baa68
> syms=[0x8+0x159ee8+0x8
> > > Booting...
> > > (nothing more)
> > >
> > > It's just as simple as downloading the image and boot so I can't think
> > > of anything strange within my procedures so far:
> > >
> > > https://wiki.qemu.org/Hosts/BSD#FreeBSD
> > >
> > > I also tried the latest image here:
> > >
> > >
> https://download.freebsd.org/ftp/releases/VM-IMAGES/11.2-RELEASE/amd64/Latest/FreeBSD-11.2-RELEASE-amd64.qcow2.xz
> > >
> > > but it's having the same problem as 11.0.
> > >
> > > Am downloading an fresh ISO, but before I continue I'm just curious on
> > > whether anyone is using these images and whether there's quick answers
> > > to what I have encountered.
> > >
> > > Thanks in advance,
> >
> > I use 'make vm-build-freebsd' which works, but the image comes
> > pre-installed.
>
> It's because I'm always with no-gui mode and FreeBSD images has no
> serial enabled by default.  I was possibly spoiled by the nice
> virt-builder before with consoles setup already for all Linux guest
> images.  Thanks for answering!
>

I'm coming to the game late...

I run FreeBSD in qemu all the time, but I build images from source to test
the boot loader and it's all serial and my test scripts are tuned to that.
I rarely use the pre-built images, however.

If there's ways that we can build images that work better than we're doing
right now to make the experience better, like making sure we enable the
dual console support for them... We're late in our release cycle, but if
what we need to change is what I think we need to change, we still have
time for it.

In the mean time I'll read through wiki and see if there's anything
obviously wrong...

Warner

Re: [Qemu-devel] [PATCH] keymaps: detect recursive keyboard layout file

[Li Qiang]

Markus Armbruster  于2018年11月15日周四 下午9:29写道：

> Li Qiang  writes:
>
> > When the parse_keyboard_layout() find a "include " line
> > in the keyboard layout file, it will call parse_keyboard_layout()
> > to perform a recursive parse. If the keyboard layout is malformed
> > by adding a line include itself, this can cause an infinite parse.
> > Thus cause qemu a segv. This patch avoid this.
> >
> > Signed-off-by: Li Qiang 
> > ---
> >  ui/keymaps.c | 17 -
> >  1 file changed, 16 insertions(+), 1 deletion(-)
> >
> > diff --git a/ui/keymaps.c b/ui/keymaps.c
> > index 085889b555..564893a9f3 100644
> > --- a/ui/keymaps.c
> > +++ b/ui/keymaps.c
> > @@ -38,6 +38,8 @@ struct kbd_layout_t {
> >  GHashTable *hash;
> >  };
> >
> > +GList *keyboard_files;
> > +
> >  static int get_keysym(const name2keysym_t *table,
> >const char *name)
> >  {
> > @@ -80,6 +82,11 @@ static void add_keysym(char *line, int keysym, int
> keycode, kbd_layout_t *k)
> >  trace_keymap_add(keysym, keycode, line);
> >  }
> >
> > +static gint compare_string(gconstpointer a, gconstpointer b)
> > +{
> > +return g_strcmp0(a, b);
> > +}
> > +
> >  static int parse_keyboard_layout(kbd_layout_t *k,
> >   const name2keysym_t *table,
> >   const char *language, Error **errp)
> > @@ -94,12 +101,18 @@ static int parse_keyboard_layout(kbd_layout_t *k,
> >  filename = qemu_find_file(QEMU_FILE_TYPE_KEYMAP, language);
> >  trace_keymap_parse(filename);
> >  f = filename ? fopen(filename, "r") : NULL;
> > -g_free(filename);
> >  if (!f) {
> > +g_free(filename);
> >  error_setg(errp, "could not read keymap file: '%s'", language);
> >  return -1;
> >  }
> >
> > +if (g_list_find_custom(keyboard_files, filename, compare_string)) {
> > +error_setg(errp, "find recursive keyboard layout: %s'",
> filename);
>
> Suggest something like "Inclusion loop for %s".
>
> > +g_free(filename);
> > +return -1;
> > +}
> > +keyboard_files = g_list_append(keyboard_files, filename);
> >  for(;;) {
> >  if (fgets(line, 1024, f) == NULL) {
> >  break;
> > @@ -168,6 +181,8 @@ static int parse_keyboard_layout(kbd_layout_t *k,
> >  ret = 0;
> >  out:
> >  fclose(f);
> > +keyboard_files = g_list_remove(keyboard_files, filename);
> > +g_free(filename);
> >  return ret;
> >  }
>
> There's no real need to make @keyboard_files global.  I'd make it local
> to init_keyboard_layout(), and pass it as argument to
> parse_keyboard_layout().



Thanks Markus,
Finally, Gerd decide remove the support of "include" in keymaps.

Thanks,
Li Qiang


> Matter of taste.  Gerd is the maintainer, not
> me.
>

Re: [Qemu-devel] Are FreeBSD guest images working?

[Peter Xu]

On Thu, Nov 15, 2018 at 11:05:33AM +0100, Philippe Mathieu-Daudé wrote:
> On 15/11/18 9:58, Peter Xu wrote:
> > Hi, the list,
> > 
> > I am trying to boot a FreeBSD guest but failed.  It hangs at the
> > kernel booting phase:
> > 
> > /boot/ker]el/kernel text=0x14ed860 data=0x132538+0x4baa68 
> > syms=[0x8+0x159ee8+0x8
> > Booting...
> > (nothing more)
> > 
> > It's just as simple as downloading the image and boot so I can't think
> > of anything strange within my procedures so far:
> > 
> > https://wiki.qemu.org/Hosts/BSD#FreeBSD
> > 
> > I also tried the latest image here:
> > 
> > https://download.freebsd.org/ftp/releases/VM-IMAGES/11.2-RELEASE/amd64/Latest/FreeBSD-11.2-RELEASE-amd64.qcow2.xz
> > 
> > but it's having the same problem as 11.0.
> > 
> > Am downloading an fresh ISO, but before I continue I'm just curious on
> > whether anyone is using these images and whether there's quick answers
> > to what I have encountered.
> > 
> > Thanks in advance,
> 
> I use 'make vm-build-freebsd' which works, but the image comes
> pre-installed.

It's because I'm always with no-gui mode and FreeBSD images has no
serial enabled by default.  I was possibly spoiled by the nice
virt-builder before with consoles setup already for all Linux guest
images.  Thanks for answering!

Regards,

-- 
Peter Xu

Re: [Qemu-devel] Are FreeBSD guest images working?

[Peter Xu]

On Thu, Nov 15, 2018 at 02:06:36PM +0300, Ilya Maximets wrote:
> > Hi, the list,
> > 
> > I am trying to boot a FreeBSD guest but failed.  It hangs at the
> > kernel booting phase:
> > 
> > /boot/ker]el/kernel text=0x14ed860 data=0x132538+0x4baa68 
> > syms=[0x8+0x159ee8+0x8
> > Booting...
> > (nothing more)
> > 
> > It's just as simple as downloading the image and boot so I can't think
> > of anything strange within my procedures so far:
> > 
> > https://wiki.qemu.org/Hosts/BSD#FreeBSD
> > 
> > I also tried the latest image here:
> > 
> > https://download.freebsd.org/ftp/releases/VM-IMAGES/11.2-RELEASE/amd64/Latest/FreeBSD-11.2-RELEASE-amd64.qcow2.xz
> > 
> > but it's having the same problem as 11.0.
> > 
> > Am downloading an fresh ISO, but before I continue I'm just curious on
> > whether anyone is using these images and whether there's quick answers
> > to what I have encountered.
> > 
> > Thanks in advance,
> > 
> > -- 
> > Peter Xu
> 
> Hi,
> I have one VM with FreeBSD-11.2-RELEASE-amd64.qcow2 image and it works
> fine under qemu 2.12.1. But it's controlled by libvirt + virt-manager,
> so it has a bit more cmdline arguments than in wiki.
> 
> In general, those images has serial console disabled by default.

Well...  I never expected this. :)

> 
> Creating the following file in VM fs:
> [root@freebsd ~]# cat /boot/loader.conf 
> boot_multicons="YES"
> boot_serial="YES"
> comconsole_speed="115200"
> console="comconsole,vidconsole"
> 
> allows me to successfully boot with:
> # qemu-system-x86_64 -machine accel=kvm -m 2048  \
>   -cpu host -enable-kvm -nographic -smp 2 \
>   -drive if=virtio,file=./FreeBSD-11.2-RELEASE-amd64.qcow2,format=qcow2
> 
> Best regards, Ilya Maximets.

SPICE worked for me now, and I tested your serial configuration, it
works as well! (though there'll be some display issue with the boot
logo before the kernel starts, but it's not a big problem)

Thanks!

-- 
Peter Xu

[Qemu-devel] [PATCH V7 6/6] pvpanic : update pvpanic document

[Peng Hao]

Add mmio support info in docs/specs/pvpanic.txt.

Signed-off-by: Peng Hao 
---
 docs/specs/pvpanic.txt | 16 +++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/docs/specs/pvpanic.txt b/docs/specs/pvpanic.txt
index c7bbacc..4e1f69d 100644
--- a/docs/specs/pvpanic.txt
+++ b/docs/specs/pvpanic.txt
@@ -1,7 +1,7 @@
 PVPANIC DEVICE
 ==
 
-pvpanic device is a simulated ISA device, through which a guest panic
+pvpanic device is a simulated device, through which a guest panic
 event is sent to qemu, and a QMP event is generated. This allows
 management apps (e.g. libvirt) to be notified and respond to the event.
 
@@ -9,6 +9,13 @@ The management app has the option of waiting for 
GUEST_PANICKED events,
 and/or polling for guest-panicked RunState, to learn when the pvpanic
 device has fired a panic event.
 
+Some architectures do not support ioport, just like arm. So add mmio
+support.
+
+When pvpanic device is implemented as a ISA device, it supports IOPORT
+mode. If pvpanic device supports MMIO mode, it will be implemented as
+a SYSBUS device.
+
 ISA Interface
 -
 
@@ -19,6 +26,13 @@ Software should set only bits both itself and the device 
recognize.
 Currently, only bit 0 is recognized, setting it indicates a guest panic
 has happened.
 
+SYSBUS Interface
+--
+
+The SYSBUS interface is similar to the ISA interface except that it uses
+MMIO. Pvpanic exposes a address space region 0x0907--0x09070001 in 
+arm virt machine. Currently only the first byte is used.
+
 ACPI Interface
 --
 
-- 
1.8.3.1

[Qemu-devel] [PATCH V7 4/6] hw/arm/virt: Use the pvpanic device

[Peng Hao]

 Add pvpanic device in arm virt machine.

Signed-off-by: Peng Hao 
Signed-off-by: Philippe Mathieu-Daudé 
---
 default-configs/arm-softmmu.mak |  1 +
 hw/arm/virt.c   | 21 +
 include/hw/arm/virt.h   |  1 +
 3 files changed, 23 insertions(+)

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index 2420491..50345df 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -159,3 +159,4 @@ CONFIG_PCI_DESIGNWARE=y
 CONFIG_STRONGARM=y
 CONFIG_HIGHBANK=y
 CONFIG_MUSICPAL=y
+CONFIG_PVPANIC=y
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 9f67782..c4f29c8 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -59,6 +59,7 @@
 #include "qapi/visitor.h"
 #include "standard-headers/linux/input.h"
 #include "hw/arm/smmuv3.h"
+#include "hw/misc/pvpanic.h"
 
 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
@@ -143,6 +144,7 @@ static const MemMapEntry a15memmap[] = {
 [VIRT_GPIO] =   { 0x0903, 0x1000 },
 [VIRT_SECURE_UART] ={ 0x0904, 0x1000 },
 [VIRT_SMMU] =   { 0x0905, 0x0002 },
+[VIRT_PVPANIC] ={ 0x0907, 0x0002 },
 [VIRT_MMIO] =   { 0x0a00, 0x0200 },
 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
 [VIRT_PLATFORM_BUS] =   { 0x0c00, 0x0200 },
@@ -190,6 +192,23 @@ static bool cpu_type_valid(const char *cpu)
 return false;
 }
 
+static void create_pvpanic_device(const VirtMachineState *vms)
+{
+char *nodename;
+hwaddr base = vms->memmap[VIRT_PVPANIC].base;
+hwaddr size = vms->memmap[VIRT_PVPANIC].size;
+
+sysbus_create_simple(TYPE_PVPANIC_MMIO, base, NULL);
+
+nodename = g_strdup_printf("/pvpanic-mmio@%" PRIx64, base);
+qemu_fdt_add_subnode(vms->fdt, nodename);
+qemu_fdt_setprop_string(vms->fdt, nodename,
+"compatible", "qemu,pvpanic-mmio");
+qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
+ 2, base, 2, size);
+g_free(nodename);
+}
+
 static void create_fdt(VirtMachineState *vms)
 {
 void *fdt = create_device_tree(>fdt_size);
@@ -1531,6 +1550,8 @@ static void machvirt_init(MachineState *machine)
 
 create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem);
 
+create_pvpanic_device(vms);
+
 create_gic(vms, pic);
 
 fdt_add_pmu_nodes(vms);
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 4cc57a7..937c124 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -66,6 +66,7 @@ enum {
 VIRT_GIC_REDIST,
 VIRT_GIC_REDIST2,
 VIRT_SMMU,
+VIRT_PVPANIC,
 VIRT_UART,
 VIRT_MMIO,
 VIRT_RTC,
-- 
1.8.3.1

[Qemu-devel] [PATCH V7 1/6] hw/misc/pvpanic: Build the pvpanic device in $(common-obj)

[Peng Hao]

From: Philippe Mathieu-Daudé 

The 'pvpanic' ISA device can be use by any machine with an ISA bus.

Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/misc/Makefile.objs | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 6d50b03..24997d6 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -8,6 +8,7 @@ common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
 common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o
 common-obj-$(CONFIG_EDU) += edu.o
 common-obj-$(CONFIG_PCA9552) += pca9552.o
+common-obj-$(CONFIG_PVPANIC) += pvpanic.o
 
 common-obj-y += unimp.o
 common-obj-$(CONFIG_FW_CFG_DMA) += vmcoreinfo.o
@@ -70,7 +71,6 @@ obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o
 obj-$(CONFIG_IOTKIT_SYSCTL) += iotkit-sysctl.o
 obj-$(CONFIG_IOTKIT_SYSINFO) += iotkit-sysinfo.o
 
-obj-$(CONFIG_PVPANIC) += pvpanic.o
 obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
 obj-$(CONFIG_AUX) += auxbus.o
 obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o
-- 
1.8.3.1

[Qemu-devel] [PATCH V7 5/6] hw/arm/virt: add pvpanic device in virt acpi table

[Peng Hao]

add pvpanic device in virt acpi table, so when kenrel command line uses
acpi=force, kernel can get info from acpi table in aarch64.

Signed-off-by: Peng Hao 
---
 hw/arm/virt-acpi-build.c | 16 
 1 file changed, 16 insertions(+)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 5785fb6..d126cee 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -61,6 +61,21 @@ static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
 }
 }
 
+static void acpi_dsdt_add_pvpanic(Aml *scope, const MemMapEntry 
*pvpanic_memmap)
+{
+Aml *dev = aml_device("PEVT");
+aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
+aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+Aml *crs = aml_resource_template();
+aml_append(crs, aml_memory32_fixed(pvpanic_memmap->base,
+   pvpanic_memmap->size, AML_READ_WRITE));
+
+aml_append(dev, aml_name_decl("_CRS", crs));
+
+aml_append(scope, dev);
+}
+
 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
uint32_t uart_irq)
 {
@@ -770,6 +785,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, 
VirtMachineState *vms)
 acpi_dsdt_add_cpus(scope, vms->smp_cpus);
 acpi_dsdt_add_uart(scope, [VIRT_UART],
(irqmap[VIRT_UART] + ARM_SPI_BASE));
+acpi_dsdt_add_pvpanic(scope, [VIRT_PVPANIC]);
 acpi_dsdt_add_flash(scope, [VIRT_FLASH]);
 acpi_dsdt_add_fw_cfg(scope, [VIRT_FW_CFG]);
 acpi_dsdt_add_virtio(scope, [VIRT_MMIO],
-- 
1.8.3.1

[Qemu-devel] [PATCH V7 3/6] hw/misc/pvpanic: Add the MMIO interface

[Peng Hao]

Add pvpanic new type "TYPE_PVPANIC_MMIO"

Signed-off-by: Peng Hao 
Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/misc/pvpanic.c | 81 +--
 include/hw/misc/pvpanic.h |  1 +
 2 files changed, 65 insertions(+), 17 deletions(-)

diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c
index dd3aef2..5d0fbc6 100644
--- a/hw/misc/pvpanic.c
+++ b/hw/misc/pvpanic.c
@@ -2,10 +2,12 @@
  * QEMU simulated pvpanic device.
  *
  * Copyright Fujitsu, Corp. 2013
+ * Copyright (c) 2018 ZTE Ltd.
  *
  * Authors:
  * Wen Congyang 
  * Hu Tao 
+ * Peng Hao 
  *
  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  * See the COPYING file in the top-level directory.
@@ -25,9 +27,6 @@
 /* The pv event value */
 #define PVPANIC_PANICKED(1 << PVPANIC_F_PANICKED)
 
-#define PVPANIC(obj)\
-OBJECT_CHECK(PVPanicState, (obj), TYPE_PVPANIC)
-
 static void handle_event(int event)
 {
 static bool logged;
@@ -45,30 +44,50 @@ static void handle_event(int event)
 
 #include "hw/isa/isa.h"
 
-typedef struct PVPanicState {
-/* private */
-ISADevice isadev;
+/* PVPanicISAState for ISA device and
+ * use ioport.
+ */
+typedef struct PVPanicISAState {
+ /* private */
+ ISADevice isadev;
+ uint16_t ioport;
 
 /* public */
 MemoryRegion mr;
-uint16_t ioport;
-} PVPanicState;
+} PVPanicISAState;
+
+/* PVPanicMMIOState for sysbus device and
+ * use mmio.
+ */
+typedef struct PVPanicMMIOState {
+/* private */
+SysBusDevice busdev;
+
+ /* public */
+MemoryRegion mr;
+} PVPanicMMIOState;
+
+#define PVPANIC_ISA(obj)\
+OBJECT_CHECK(PVPanicISAState, (obj), TYPE_PVPANIC)
+
+#define PVPANIC_MMIO(obj)\
+OBJECT_CHECK(PVPanicMMIOState, (obj), TYPE_PVPANIC_MMIO)
 
 /* return supported events on read */
-static uint64_t pvpanic_ioport_read(void *opaque, hwaddr addr, unsigned size)
+static uint64_t pvpanic_read(void *opaque, hwaddr addr, unsigned size)
 {
 return PVPANIC_PANICKED;
 }
 
-static void pvpanic_ioport_write(void *opaque, hwaddr addr, uint64_t val,
+static void pvpanic_write(void *opaque, hwaddr addr, uint64_t val,
  unsigned size)
 {
 handle_event(val);
 }
 
 static const MemoryRegionOps pvpanic_ops = {
-.read = pvpanic_ioport_read,
-.write = pvpanic_ioport_write,
+.read = pvpanic_read,
+.write = pvpanic_write,
 .impl = {
 .min_access_size = 1,
 .max_access_size = 1,
@@ -77,15 +96,16 @@ static const MemoryRegionOps pvpanic_ops = {
 
 static void pvpanic_isa_initfn(Object *obj)
 {
-PVPanicState *s = PVPANIC(obj);
+PVPanicISAState *s = PVPANIC_ISA(obj);
 
-memory_region_init_io(>mr, OBJECT(s), _ops, s, "pvpanic", 1);
+memory_region_init_io(>mr, OBJECT(s), _ops, s,
+  TYPE_PVPANIC, 1);
 }
 
 static void pvpanic_isa_realizefn(DeviceState *dev, Error **errp)
 {
 ISADevice *d = ISA_DEVICE(dev);
-PVPanicState *s = PVPANIC(dev);
+PVPanicISAState *s = PVPANIC_ISA(dev);
 FWCfgState *fw_cfg = fw_cfg_find();
 uint16_t *pvpanic_port;
 
@@ -102,7 +122,7 @@ static void pvpanic_isa_realizefn(DeviceState *dev, Error 
**errp)
 }
 
 static Property pvpanic_isa_properties[] = {
-DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicState, ioport, 0x505),
+DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicISAState, ioport, 0x505),
 DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -118,14 +138,41 @@ static void pvpanic_isa_class_init(ObjectClass *klass, 
void *data)
 static TypeInfo pvpanic_isa_info = {
 .name  = TYPE_PVPANIC,
 .parent= TYPE_ISA_DEVICE,
-.instance_size = sizeof(PVPanicState),
+.instance_size = sizeof(PVPanicISAState),
 .instance_init = pvpanic_isa_initfn,
 .class_init= pvpanic_isa_class_init,
 };
 
+
+static void pvpanic_mmio_initfn(Object *obj)
+{
+PVPanicMMIOState *s = PVPANIC_MMIO(obj);
+SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+
+memory_region_init_io(>mr, OBJECT(s), _ops, s,
+  TYPE_PVPANIC_MMIO, 2);
+sysbus_init_mmio(sbd, >mr);
+}
+
+static void pvpanic_mmio_class_init(ObjectClass *klass, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(klass);
+
+set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+}
+
+static TypeInfo pvpanic_mmio_info = {
+.name  = TYPE_PVPANIC_MMIO,
+.parent= TYPE_SYS_BUS_DEVICE,
+.instance_size = sizeof(PVPanicMMIOState),
+.instance_init = pvpanic_mmio_initfn,
+.class_init= pvpanic_mmio_class_init,
+};
+
 static void pvpanic_register_types(void)
 {
 type_register_static(_isa_info);
+type_register_static(_mmio_info);
 }
 
 type_init(pvpanic_register_types)
diff --git a/include/hw/misc/pvpanic.h b/include/hw/misc/pvpanic.h
index 1ee071a..19c0fbb 100644
--- a/include/hw/misc/pvpanic.h
+++ b/include/hw/misc/pvpanic.h
@@ -17,6 +17,7 @@
 #define TYPE_PVPANIC "pvpanic"
 
 #define PVPANIC_IOPORT_PROP "ioport"
+#define 

[Qemu-devel] [PATCH V7 0/5] add pvpanic mmio support

[Peng Hao]

The first patches are simple cleanups:
- patch 1 move the pvpanic device with the 'ocmmon objects' so we compile
  it once for the x86/arm/aarch64 archs,
- patch 2 simply renames ISA fields/definitions to generic ones.

Then instead of add/use the MMIO pvpanic device in the virt machine in an
unique patch, I split it in two distinct patches:
- patch 3 uses Peng Hao's work, but add the MMIO interface to the existing
  device (no logical change).
- patch 4 is Peng Hao's work in the virt machine (no logical change).
- patch 5 add pvpanic device in acpi table in virt machine
v2 from Peng Hao is:
https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg03433.html

v3 --> v4
  patch 1,2 no modification.
  patch 3, add TYPE_PANIC_MMIO for distinguishing different bus device,
   virt + isa_pvpanic will abnormally terminate virtual machine. 
  patch 4, "pvpanic,mmio" --> "qemu,pvpanic-mmio".
  patch 5, newly added.

v4 --> v5
  patch 1,2 no modification.
  patch 3 delete PvpanicCommonState structure.
  patch 4 VIRT_PVPANIC_MMIO --> VIRT_PVPANIC
  correct VIRT_PVPANIC's overlap start address
  patch 5 no modification.

v5 --> v6
  add document.

v6 --> v7
  patch 5 modify device name from "PANC" to "PEVT".
  patch 6 modify document description.
  
the kernel part of the series:
https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git/log/?h=char-misc-testing
misc/pvpanic: remove a redundant comma 
misc/pvpanic: convert to SPDX license tags 
misc/pvpanic: change header file sort style 
misc/pvpanic: remove unnecessary header file  
misc/pvpanic : break dependency on ACPI 
misc/pvpanic : grouping ACPI related stuff  
misc/pvpanic: add support to get pvpanic device info FDT  
dt-bindings: misc/pvpanic: add document for pvpanic-mmio  
misc/pvpanic: add MMIO support  
misc/pvpanic: simplify the code using acpi_dev_resource_io  
pvpanic: move pvpanic to misc as common driver 

Philippe Mathieu-Daudé (2):
  hw/misc/pvpanic: Build the pvpanic device in $(common-obj)
  hw/misc/pvpanic: Cosmetic renaming

Peng Hao (3):
  hw/misc/pvpanic: Add the MMIO interface
  hw/arm/virt: Use the pvpanic device
  hw/arm/virt: add pvpanic device in virt acpi table
  pvpanic : update pvpanic document

 default-configs/aarch64-softmmu.mak |  1 +
 hw/arm/virt-acpi-build.c| 16 
 hw/arm/virt.c   | 21 ++
 hw/misc/Makefile.objs   |  2 +-
 hw/misc/pvpanic.c   | 78 ++---
 include/hw/arm/virt.h   |  1 +
 include/hw/misc/pvpanic.h   |  2 +
 docs/specs/pvpanic.txt  | 13 -
 8 files changed, 118 insertions(+), 17 deletions(-)

-- 
1.8.3.1

[Qemu-devel] [PATCH V7 2/6] hw/misc/pvpanic: Cosmetic renaming

[Peng Hao]

From: Philippe Mathieu-Daudé 

To ease the MMIO device addition in the next patch, rename:
- ISA_PVPANIC_DEVICE -> PVPANIC (this just returns a generic Object),
- ISADevice parent_obj -> isadev,
- MemoryRegion io -> mr.

Signed-off-by: Philippe Mathieu-Daudé 
---
 hw/misc/pvpanic.c | 16 +---
 1 file changed, 9 insertions(+), 7 deletions(-)

diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c
index 9d8961b..dd3aef2 100644
--- a/hw/misc/pvpanic.c
+++ b/hw/misc/pvpanic.c
@@ -25,7 +25,7 @@
 /* The pv event value */
 #define PVPANIC_PANICKED(1 << PVPANIC_F_PANICKED)
 
-#define ISA_PVPANIC_DEVICE(obj)\
+#define PVPANIC(obj)\
 OBJECT_CHECK(PVPanicState, (obj), TYPE_PVPANIC)
 
 static void handle_event(int event)
@@ -46,9 +46,11 @@ static void handle_event(int event)
 #include "hw/isa/isa.h"
 
 typedef struct PVPanicState {
-ISADevice parent_obj;
+/* private */
+ISADevice isadev;
 
-MemoryRegion io;
+/* public */
+MemoryRegion mr;
 uint16_t ioport;
 } PVPanicState;
 
@@ -75,15 +77,15 @@ static const MemoryRegionOps pvpanic_ops = {
 
 static void pvpanic_isa_initfn(Object *obj)
 {
-PVPanicState *s = ISA_PVPANIC_DEVICE(obj);
+PVPanicState *s = PVPANIC(obj);
 
-memory_region_init_io(>io, OBJECT(s), _ops, s, "pvpanic", 1);
+memory_region_init_io(>mr, OBJECT(s), _ops, s, "pvpanic", 1);
 }
 
 static void pvpanic_isa_realizefn(DeviceState *dev, Error **errp)
 {
 ISADevice *d = ISA_DEVICE(dev);
-PVPanicState *s = ISA_PVPANIC_DEVICE(dev);
+PVPanicState *s = PVPANIC(dev);
 FWCfgState *fw_cfg = fw_cfg_find();
 uint16_t *pvpanic_port;
 
@@ -96,7 +98,7 @@ static void pvpanic_isa_realizefn(DeviceState *dev, Error 
**errp)
 fw_cfg_add_file(fw_cfg, "etc/pvpanic-port", pvpanic_port,
 sizeof(*pvpanic_port));
 
-isa_register_ioport(d, >io, s->ioport);
+isa_register_ioport(d, >mr, s->ioport);
 }
 
 static Property pvpanic_isa_properties[] = {
-- 
1.8.3.1

Re: [Qemu-devel] [PATCH V2] net/filter-rewriter.c: Fix coverity static analysis issue

[Jason Wang]

On 2018/11/15 下午6:32, Peter Maydell wrote:

On 2 November 2018 at 02:21, Jason Wang  wrote:

On 2018/10/31 上午8:50, Zhang Chen wrote:

The original code just follow the TCP state diagram,
but in this case, we can skip the TCPS_TIME_WAIT state to simplify
the implementation.

Signed-off-by: Zhang Chen 
---
   net/filter-rewriter.c | 3 ++-
   1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/net/filter-rewriter.c b/net/filter-rewriter.c
index bb8f4d93b1..2e26839bc2 100644
--- a/net/filter-rewriter.c
+++ b/net/filter-rewriter.c
@@ -155,12 +155,13 @@ static int handle_primary_tcp_pkt(RewriterState *rf,
* Active close step 2.
*/
   if (conn->tcp_state == TCPS_FIN_WAIT_1) {
-conn->tcp_state = TCPS_TIME_WAIT;
   /*
* For simplify implementation, we needn't wait 2MSL time
* in filter rewriter. Because guest kernel will track the
* TCP status and wait 2MSL time, if client resend the FIN
* packet, guest will apply the last ACK too.
+ * So, we skip the TCPS_TIME_WAIT state here and go straight
+ * to TCPS_CLOSED state.
*/
   conn->tcp_state = TCPS_CLOSED;
   g_hash_table_remove(rf->connection_track_table, key);



Applied.

Ping -- this doesn't seem to have made it into master?

thanks
-- PMM



Will send a pull request soon.

Thanks

Re: [Qemu-devel] [PATCH V6 6/6] pvpanic : update pvpanic document

[peng.hao2]

> Add mmio support info in docs/specs/pvpanic.txt.
>>
>> Signed-off-by: Peng Hao 
>> ---
>>  docs/specs/pvpanic.txt | 13 -
>>  1 file changed, 12 insertions(+), 1 deletion(-)
>>
>> diff --git a/docs/specs/pvpanic.txt b/docs/specs/pvpanic.txt
>> index c7bbacc..5d8e9dc 100644
>> --- a/docs/specs/pvpanic.txt
>> +++ b/docs/specs/pvpanic.txt
>> @@ -1,7 +1,7 @@
>>  PVPANIC DEVICE
>>  ==
>>
>> -pvpanic device is a simulated ISA device, through which a guest panic
>> +pvpanic device is a simulated device, through which a guest panic
>>  event is sent to qemu, and a QMP event is generated. This allows
>>  management apps (e.g. libvirt) to be notified and respond to the event.
>>
>> @@ -9,6 +9,10 @@ The management app has the option of waiting for 
>> GUEST_PANICKED events,
>>  and/or polling for guest-panicked RunState, to learn when the pvpanic
>>  device has fired a panic event.
>>
>> +When pvpanic device is implemented as a ISA device, it supports IOPORT
>^the  ^an
>> +mode. If pvpanic device supports MMIO mode, it will be implemented as
>
>When the pvpanic device needs to use MMIO mode, ...
>
I will add "Some architectures do not support ioport, just like arm."
>> +a SYSBUS device.
>> +
>>  ISA Interface
>>  -
>>
>> @@ -19,6 +23,13 @@ Software should set only bits both itself and the device 
>> recognize.
>>  Currently, only bit 0 is recognized, setting it indicates a guest panic
>>  has happened.
>>
>> +SYSBUS Interface
>> +--
>> +
>> +It is basically the same as ISA interface except that it uses MMIO.
>
>The SYSBUS interface is similar to the ISA interface...
>
I will change it.
>> Pvpanic exposes
>> +a address space region 0x0906--0x09060001 in arm virt machine.
>> +Currently only the first byte is used.
>> +
>
>I would drop the above lines. They're not correct anyway. The region is
>907-9070001 (inclusive).
sorry,I wrote a  wrong address span.
>
>>  ACPI Interface
>>  --
>>
>> --
>> 1.8.3.1
>>
>>
>
>Thanks,
>drew

Re: [Qemu-devel] [PATCH V6 5/6] hw/arm/virt: add pvpanic device invirt acpi table

[peng.hao2]

>> add pvpanic device in virt acpi table, so when kenrel command line uses
>> acpi=force, kernel can get info from acpi table in aarch64.

[...]

>>
>> +static void acpi_dsdt_add_pvpanic(Aml *scope, const MemMapEntry 
>> *pvpanic_memmap)
>> +{
>> +Aml *dev = aml_device("PANC");
>
>Shouldn't this be "PEVT" ("panic event"), like it is for x86?
>
yeah, I will change it.
>> +aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
>> +aml_append(dev, aml_name_decl("_UID", aml_int(0)));
>
>Why add _UID? Also, I see x86 had some issues with not having _STA and
>then having a _STA without the UI flag. It now has _STA=0xf
>(PRESENT|ENABLED|UI|FUNCTIONING). I'm not saying we need to do that to,
>but I'd like to know if it was considered and decided we don't need to.
>
The way the kernel code processes _STA is that if _STA is not found, the 
default 
setting is (PRESENT|ENABLED|UI|FUNCTIONING). So I think it is not necessary
 to add it. It is only parsed in the pvpanic driver. 
for _UID, I think it is used for device index. I just fill it with 0 because 
there is 
only one pvpanic device.

by the way, How to get the value of ACPI conveniently? how dou you get the 
value of _STA?

Thanks.
>> +
>> +Aml *crs = aml_resource_template();
>> +aml_append(crs, aml_memory32_fixed(pvpanic_memmap->base,
>> +   pvpanic_memmap->size, 
>> AML_READ_WRITE));
>> +
>> +aml_append(dev, aml_name_decl("_CRS", crs));
>> +
>> +aml_append(scope, dev);
>> +}
>> +
>>  static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
>> uint32_t uart_irq)
>>  {
>> @@ -770,6 +785,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, 
>> VirtMachineState *vms)
>>  acpi_dsdt_add_cpus(scope, vms->smp_cpus);
>>  acpi_dsdt_add_uart(scope, [VIRT_UART],
>> (irqmap[VIRT_UART] + ARM_SPI_BASE));
>> +acpi_dsdt_add_pvpanic(scope, [VIRT_PVPANIC]);
>>  acpi_dsdt_add_flash(scope, [VIRT_FLASH]);
>>  acpi_dsdt_add_fw_cfg(scope, [VIRT_FW_CFG]);
>>  acpi_dsdt_add_virtio(scope, [VIRT_MMIO],
>> --
>> 1.8.3.1
>>
>>
>
>Thanks,
>drew

Re: [Qemu-devel] [PATCH v9 0/8] virtio-balloon: free page hint support

[Wei Wang]

On 11/16/2018 02:50 AM, no-re...@patchew.org wrote:

Hi,

This series failed docker-quick@centos7 build test. Please find the testing 
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

   CC  net/filter.o
   CC  net/filter-buffer.o
   CC  net/filter-mirror.o
   CC  net/colo-compare.o
/tmp/qemu-test/src/migration/rdma.c: In function 'qemu_rdma_accept':
/tmp/qemu-test/src/migration/rdma.c:3353:5: error: implicit declaration of 
function 'migrate_postcopy' [-Werror=implicit-function-declaration]
  if (migrate_postcopy() && !rdma->is_return_path) {
  ^
/tmp/qemu-test/src/migration/rdma.c:3353:5: error: nested extern declaration of 
'migrate_postcopy' [-Werror=nested-externs]
cc1: all warnings being treated as errors
make: *** [migration/rdma.o] Error 1
make: *** Waiting for unfinished jobs


This is caused by missing "migration/misc.h" in rdma.c, since we moved 
the migrate_postcopy() declaration there. I'll add it.


Best,
Wei

Re: [Qemu-devel] [PATCH for-4.0 00/17] tcg: Move softmmu out-of-line

[Emilio G. Cota]

On Thu, Nov 15, 2018 at 23:04:50 +0100, Richard Henderson wrote:
> On 11/15/18 7:48 PM, Emilio G. Cota wrote:
> > - Segfault in code_gen_buffer. This one I don't have a fix for,
> >   but it's *much* easier to reproduce when -tb-size is very small,
> >   e.g. "-tb-size 5 -smp 2" (BTW it crashes with x86_64 guests too.)
> >   So at first I thought the code cache flushing was the problem,
> >   but I don't see how that could be, at least from a TCGContext
> >   viewpoint -- I agree that clearing the hash table in
> >   tcg_region_assign is a good place to do so.
> 
> Ho hum.
> 
> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
> index 639f0b2728..115ea186e5 100644
> --- a/accel/tcg/translate-all.c
> +++ b/accel/tcg/translate-all.c
> @@ -1831,10 +1831,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
>  existing_tb = tb_link_page(tb, phys_pc, phys_page2);
>  /* if the TB already exists, discard what we just translated */
>  if (unlikely(existing_tb != tb)) {
> -uintptr_t orig_aligned = (uintptr_t)gen_code_buf;
> -
> -orig_aligned -= ROUND_UP(sizeof(*tb), qemu_icache_linesize);
> -atomic_set(_ctx->code_gen_ptr, (void *)orig_aligned);
>  return existing_tb;
>  }
>  tcg_tb_insert(tb);
> 
> We can't easily undo the hash table insert, and for a relatively rare
> occurrence it's not worth the effort.

Nice catch! Everything works now =D

In the bootup+shutdown aarch64 test with -smp 12, we end up
discarding ~2500 TB's--that's ~439K of space for code that we
do not waste; note that I'm assuming 180 host bytes per TB,
which is the average reported by info jit.

We can still discard most of these by increasing a counter every
time we insert a new element into the OOL table, and checking
this counter before/after tcg_gen_code. (Note that checking
g_hash_table_size before/after is not enough, because we might
have replaced an existing item from the table.)
Then, we discard a TB iff an OOL thunk was generated. (Diff below.)

This allows us to discard most TBs; in the example above,
we end up *not* discarding only ~70 TBs, that is we end up keeping
only 70/2500 = 2.8% of the TBs that we'd discard without OOL.

Performance-wise it doesn't make a difference for -smp 1:

Host: Intel(R) Xeon(R) CPU E5-2643 0 @ 3.30GHz
Performance counter stats for 'taskset -c 0 ../img/aarch64/die.sh' (5 runs):

- Before (3.1.0-rc1):

  14351.436177  task-clock (msec) #0.998 CPUs utilized  
  ( +-  0.24% )
49,963,260,126  cycles#3.481 GHz
  ( +-  0.22% )  (83.32%)
26,047,650,654  stalled-cycles-frontend   #   52.13% frontend cycles 
idle ( +-  0.29% )  (83.34%)
19,717,480,482  stalled-cycles-backend#   39.46% backend  cycles 
idle ( +-  0.27% )  (66.67%)
59,278,011,067  instructions  #1.19  insns per cycle

  #0.44  stalled cycles per 
insn  ( +-  0.17% )  (83.34%)
10,632,601,608  branches  #  740.874 M/sec  
  ( +-  0.17% )  (83.34%)
   236,153,469  branch-misses #2.22% of all branches
  ( +-  0.16% )  (83.35%)

  14.382847823 seconds time elapsed 
 ( +-  0.25% )

- After this series (with the fixes we've discussed):

  13256.198927  task-clock (msec) #0.998 CPUs utilized  
  ( +-  0.04% )
46,146,457,353  cycles#3.481 GHz
  ( +-  0.08% )  (83.34%)
22,632,342,565  stalled-cycles-frontend   #   49.04% frontend cycles 
idle ( +-  0.12% )  (83.35%)
16,534,690,741  stalled-cycles-backend#   35.83% backend  cycles 
idle ( +-  0.15% )  (66.67%)
58,047,832,548  instructions  #1.26  insns per cycle

  #0.39  stalled cycles per 
insn  ( +-  0.18% )  (83.34%)
11,031,634,880  branches  #  832.187 M/sec  
  ( +-  0.12% )  (83.33%)
   210,593,929  branch-misses #1.91% of all branches
  ( +-  0.30% )  (83.33%)

  13.285023783 seconds time elapsed 
 ( +-  0.05% )

- After the fixup below:

  13240.889734  task-clock (msec) #0.998 CPUs utilized  
  ( +-  0.19% )
46,074,292,775  cycles#3.480 GHz
  ( +-  0.12% )  (83.35%)
22,670,132,770  stalled-cycles-frontend   #   49.20% frontend cycles 
idle ( +-  0.17% )  (83.35%)
16,598,822,504  stalled-cycles-backend#   36.03% backend  cycles 
idle ( +-  0.26% )  (66.66%)
57,796,083,344  instructions  #1.25  insns per cycle

  #0.39  stalled cycles per 
insn 

Re: [Qemu-devel] [PATCH for-3.2 00/10] vhost: preparation for qgraph conversion of vhost-user-test

[no-reply]

Hi,

This series seems to have some coding style problems. See output below for
more information:

Message-id: 20181115143124.19234-1-pbonz...@redhat.com
Type: series
Subject: [Qemu-devel] [PATCH for-3.2 00/10] vhost: preparation for qgraph 
conversion of vhost-user-test

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
d7a4ddd vhost-user-test: create a temporary directory per TestServer
0671cab vhost-user-test: small changes to init_hugepagefs
2afa43f vhost-user-test: create a main loop per TestServer
49ae390 vhost-user-test: reduce usage of global_qtest
2732f0b vhost-user-test: skip if there is no memory at address 0
b792e50 vhost-user-test: support VHOST_USER_PROTOCOL_F_CROSS_ENDIAN
b82ba2f vhost-user: support cross-endian vnet headers
48b61f6 vhost-net: compile it for all targets
8e327b5 vhost-user-test: signal data_cond when s->rings changes
4e3260e vhost-user-test: use g_cond_broadcast

=== OUTPUT BEGIN ===
Checking PATCH 1/10: vhost-user-test: use g_cond_broadcast...
Checking PATCH 2/10: vhost-user-test: signal data_cond when s->rings changes...
Checking PATCH 3/10: vhost-net: compile it for all targets...
Checking PATCH 4/10: vhost-user: support cross-endian vnet headers...
Checking PATCH 5/10: vhost-user-test: support 
VHOST_USER_PROTOCOL_F_CROSS_ENDIAN...
Checking PATCH 6/10: vhost-user-test: skip if there is no memory at address 0...
Checking PATCH 7/10: vhost-user-test: reduce usage of global_qtest...
WARNING: line over 80 characters
#21: FILE: tests/vhost-user-test.c:190:
+static void init_virtio_dev(QTestState *qts, TestServer *s, uint32_t 
features_mask)

WARNING: line over 80 characters
#54: FILE: tests/vhost-user-test.c:296:
+uint32_t a = qtest_readb(qts, s->memory.regions[i].guest_phys_addr 
+ j);

total: 0 errors, 2 warnings, 132 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 8/10: vhost-user-test: create a main loop per TestServer...
ERROR: space prohibited between function name and open parenthesis '('
#50: FILE: tests/vhost-user-test.c:551:
+g_main_context_iteration (NULL, TRUE);

total: 1 errors, 0 warnings, 82 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 9/10: vhost-user-test: small changes to init_hugepagefs...
Checking PATCH 10/10: vhost-user-test: create a temporary directory per 
TestServer...
=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

Re: [Qemu-devel] [PATCH] cpus: run work items for all vCPUs if single-threaded

[Emilio G. Cota]

On Fri, Nov 16, 2018 at 00:15:53 +0100, Paolo Bonzini wrote:
> On 14/11/2018 20:42, Emilio G. Cota wrote:
> > On Wed, Nov 14, 2018 at 12:44:00 +0100, Paolo Bonzini wrote:
> >> This avoids the following deadlock:
> >>
> >> 1) a thread calls run_on_cpu for CPU 2 from a timer, and 
> >> single_tcg_halt_cond
> >> is signaled
> >>
> >> 2) CPU 1 is running and exits.  It finds no work item and enters CPU 2
> >>
> >> 3) because the I/O thread is stuck in run_on_cpu, the round-robin kick
> >> timer never triggers, and CPU 2 never runs the work item
> >>
> >> 4) run_on_cpu never completes
(snip)
> > I can see though how with an additional CPU the deadlock
> > could happen. For example, the I/O thread does run_on_cpu(cpu3),
> > which kicks cpu1 (i.e. the tcg_current_rr_cpu) and cpu3, but not cpu2.
> > Then cpu1 exits, and cpu2 starts executing; unless cpu2 exits on its
> > own volition, it will run forever.
> 
> Yes, the thread must call run_on_cpu for CPU *3* from a timer.

Thanks! Please add my

Reviewed-by: Emilio G. Cota 

tag when fixing up the commit message.

E.

Re: [Qemu-devel] [PATCH] cpus: run work items for all vCPUs if single-threaded

[Paolo Bonzini]

On 14/11/2018 20:42, Emilio G. Cota wrote:
> On Wed, Nov 14, 2018 at 12:44:00 +0100, Paolo Bonzini wrote:
>> This avoids the following deadlock:
>>
>> 1) a thread calls run_on_cpu for CPU 2 from a timer, and single_tcg_halt_cond
>> is signaled
>>
>> 2) CPU 1 is running and exits.  It finds no work item and enters CPU 2
>>
>> 3) because the I/O thread is stuck in run_on_cpu, the round-robin kick
>> timer never triggers, and CPU 2 never runs the work item
>>
>> 4) run_on_cpu never completes
> 
> I'm having trouble understanding (2)->(3).
> 
> When the vCPU thread enters CPU 2, shouldn't it detect that work is
> pending? As in:
> 
>   /* assume cpu == cpu2 in the example above */
>   while (cpu && !cpu->queued_work_first && !cpu->exit_request) {
> 
> Both cpu->queued_work_first and cpu->exit_request will be set for cpu2.
> 
> I can see though how with an additional CPU the deadlock
> could happen. For example, the I/O thread does run_on_cpu(cpu3),
> which kicks cpu1 (i.e. the tcg_current_rr_cpu) and cpu3, but not cpu2.
> Then cpu1 exits, and cpu2 starts executing; unless cpu2 exits on its
> own volition, it will run forever.

Yes, the thread must call run_on_cpu for CPU *3* from a timer.

Paolo

[Qemu-devel] [PATCH] hw/i2c/smbus_eeprom: Create at most SMBUS_EEPROM_MAX EEPROMs on a SMBus

[Philippe Mathieu-Daudé]

Calling smbus_eeprom_init() with more than 8 EEPROMs would lead to a
heap overflow.
Replace the '8' magic number by a definition, and check no more than
this number are created.

Signed-off-by: Philippe Mathieu-Daudé 
---
Based-on: 20181115192446.17187-1-miny...@acm.org
"RFC v2: Fix/add vmstate handling in some I2C code"
---
 hw/i2c/smbus_eeprom.c | 13 +++--
 include/hw/i2c/smbus_eeprom.h |  4 +++-
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
index d0a8d63869..de3a492df4 100644
--- a/hw/i2c/smbus_eeprom.c
+++ b/hw/i2c/smbus_eeprom.c
@@ -23,6 +23,7 @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/error-report.h"
 #include "hw/hw.h"
 #include "hw/boards.h"
 #include "hw/i2c/i2c.h"
@@ -163,12 +164,20 @@ void smbus_eeprom_init_one(I2CBus *smbus, uint8_t 
address, uint8_t *eeprom_buf)
 qdev_init_nofail(dev);
 }
 
-void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,
+void smbus_eeprom_init(I2CBus *smbus, unsigned int nb_eeprom,
const uint8_t *eeprom_spd, int eeprom_spd_size)
 {
 int i;
+uint8_t *eeprom_buf;
+
+if (nb_eeprom > SMBUS_EEPROM_MAX) {
+error_report("At most %u EEPROM are supported on a SMBus.",
+ SMBUS_EEPROM_MAX);
+exit(1);
+}
+
  /* XXX: make this persistent */
-uint8_t *eeprom_buf = g_malloc0(8 * SMBUS_EEPROM_SIZE);
+eeprom_buf = g_malloc0(nb_eeprom * SMBUS_EEPROM_SIZE);
 if (eeprom_spd_size > 0) {
 memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size);
 }
diff --git a/include/hw/i2c/smbus_eeprom.h b/include/hw/i2c/smbus_eeprom.h
index 2f56e5dc4e..cc9d1cdba9 100644
--- a/include/hw/i2c/smbus_eeprom.h
+++ b/include/hw/i2c/smbus_eeprom.h
@@ -4,8 +4,10 @@
 
 #include "hw/i2c/i2c.h"
 
+#define SMBUS_EEPROM_MAX 8
+
 void smbus_eeprom_init_one(I2CBus *bus, uint8_t address, uint8_t *eeprom_buf);
-void smbus_eeprom_init(I2CBus *bus, int nb_eeprom,
+void smbus_eeprom_init(I2CBus *bus, unsigned int nb_eeprom,
const uint8_t *eeprom_spd, int size);
 
 #endif
-- 
2.17.2

Re: [Qemu-devel] [PATCH v2 00/12] RFC: Fix/add vmstate handling in some I2C code

[Philippe Mathieu-Daudé]

Hi Corey,

On 15/11/18 20:24, miny...@acm.org wrote:

These changes allow SMBus access while doing a state transfer.
Seems like a good idea to me in general.

I have these queued for the SMBus IPMI driver work, of course.

I had submitted this before and then lost track of the work since I
started finding all kinds of broken things in the I2C code.  I
have fixed the broken things I found first, and then added the
previous patches.

I have tested this in q35 and it works without issue.  On piix4 the
pm_smbus code is broken on a migration, however. The device disappears
from the PCI bus on a migration, from what I can tell.  It's not the
fault of this code, something more fundamental is going on.  The
following comment in piix4.c may have something to do with it:

/* qemu-kvm 1.2 uses version 3 but advertised as 2
  * To support incoming qemu-kvm 1.2 migration, change version_id
  * and minimum_version_id to 2 below (which breaks migration from
  * qemu 1.2).

Anyway, I need to chase that down.

I'm primarily submitting this to make sure I'm doing the backwards
compatability with .needed correctly.  I'm adding a new field in
the machine class and setting it in the initialization code for
older versions.  David, is this what you wanted?  It will have to
be adjusted for the proper version if/when it really goes in, of
course.  You can see those in the following commits:
   boards.h: Ignore migration for SMBus devices on
   i2c:pm_smbus: Fix state transfer
   i2c: Add vmstate handling to the smbus eeprom
I thought about adding a field to the pm_smbus code to only transfer
if it was accessed, but I'm assuming that most modern OSes will
at least initialized the device based on its presence on the PCI
bus.  So that didn't seem like it would add any value.

I'm also submitting to see if all the fixes and cleanups look ok.
That's the first 5 commits.


$ git diff origin/master --summary
 delete mode 100644 hw/i2c/smbus.c
 create mode 100644 hw/i2c/smbus_master.c
 create mode 100644 hw/i2c/smbus_slave.c
 create mode 100644 include/hw/i2c/smbus_eeprom.h
 rename include/hw/i2c/{smbus.h => smbus_master.h} (56%)
 create mode 100644 include/hw/i2c/smbus_slave.h

Can you add the following files in the MAINTAINERS file:
- hw/i2c/smbus_master.c
- hw/i2c/smbus_slave.c
- include/hw/i2c/smbus_eeprom.h
- include/hw/i2c/smbus_master.h
- include/hw/i2c/smbus_slave.h

Thanks,

Phil.

Re: [Qemu-devel] [PATCH v2] qapi: Reduce Makefile boilerplate

[Paolo Bonzini]

On 15/11/2018 23:50, Eric Blake wrote:
> Adding a new qapi module requires some rather tedious repetition to
> wire it into Makefile and Makefile.objs. Add some indirection by
> taking advantage of GNU Make string processing to expand a list
> of module names into all the required artifacts, so that future
> additions of a new module need only touch the list of module names.
> 
> The list has to live in Makefile.objs, due to the way that
> unnest-vars slirps in that file without remembering any definition
> of $(QAPI_MODULES) from Makefile.

I don't see offhand why that would happen; Makefile.objs is simply
included from Makefile.  Anyway, if this works it's okay as well.

Feel free to send me the non-working patch offlist.

Paolo

Re: [Qemu-devel] [PATCH] qapi: Reduce Makefile boilerplate

[Eric Blake]

On 11/15/18 4:37 PM, Eric Blake wrote:

I'm trying to do the same thing to Makefile.objs, but when I use:

common-obj-y += $(QAPI_MODULES:%=qapi/qapi-commands-%.o)

or the longer $(patsubst %,qapi,qapi-commands-%.o,$(QAPI_MODULES))

both before and after the change, 'make print-common-obj-y | grep qapi' 
returns identical content, but after the change, the linker fails with:






So something about variable expansions is NOT playing nicely with our

dummy := $(call unnest-vars,, \
     stub-obj-y \
     chardev-obj-y \
...
     common-obj-y \


Aha - the problem is that $(QAPI_MODULES) is empty at the time 
unnest-vars tries to slurp in Makefile.objs, while it was non-empty at 
the time that Makefile directly includes it. Moving the definition of 
QAPI_MODULES into Makefile.objs solves that. v2 coming up.


--
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

[Qemu-devel] [PATCH v2] qapi: Reduce Makefile boilerplate

[Eric Blake]

Adding a new qapi module requires some rather tedious repetition to
wire it into Makefile and Makefile.objs. Add some indirection by
taking advantage of GNU Make string processing to expand a list
of module names into all the required artifacts, so that future
additions of a new module need only touch the list of module names.

The list has to live in Makefile.objs, due to the way that
unnest-vars slirps in that file without remembering any definition
of $(QAPI_MODULES) from Makefile.

Signed-off-by: Eric Blake 

---
v2: also condense Makefile.objs, prefer $(FOO:%=a%b) over
%(patsubst %,a%b,$(foo))
---
 Makefile  | 192 ++
 Makefile.objs |  75 ++--
 2 files changed, 30 insertions(+), 237 deletions(-)

diff --git a/Makefile b/Makefile
index f2947186a4c..c8b9efdad4b 100644
--- a/Makefile
+++ b/Makefile
@@ -88,82 +88,26 @@ endif
 include $(SRC_PATH)/rules.mak

 GENERATED_FILES = qemu-version.h config-host.h qemu-options.def
-GENERATED_FILES += qapi/qapi-builtin-types.h qapi/qapi-builtin-types.c
-GENERATED_FILES += qapi/qapi-types.h qapi/qapi-types.c
-GENERATED_FILES += qapi/qapi-types-block-core.h qapi/qapi-types-block-core.c
-GENERATED_FILES += qapi/qapi-types-block.h qapi/qapi-types-block.c
-GENERATED_FILES += qapi/qapi-types-char.h qapi/qapi-types-char.c
-GENERATED_FILES += qapi/qapi-types-common.h qapi/qapi-types-common.c
-GENERATED_FILES += qapi/qapi-types-crypto.h qapi/qapi-types-crypto.c
-GENERATED_FILES += qapi/qapi-types-introspect.h qapi/qapi-types-introspect.c
-GENERATED_FILES += qapi/qapi-types-job.h qapi/qapi-types-job.c
-GENERATED_FILES += qapi/qapi-types-migration.h qapi/qapi-types-migration.c
-GENERATED_FILES += qapi/qapi-types-misc.h qapi/qapi-types-misc.c
-GENERATED_FILES += qapi/qapi-types-net.h qapi/qapi-types-net.c
-GENERATED_FILES += qapi/qapi-types-rocker.h qapi/qapi-types-rocker.c
-GENERATED_FILES += qapi/qapi-types-run-state.h qapi/qapi-types-run-state.c
-GENERATED_FILES += qapi/qapi-types-sockets.h qapi/qapi-types-sockets.c
-GENERATED_FILES += qapi/qapi-types-tpm.h qapi/qapi-types-tpm.c
-GENERATED_FILES += qapi/qapi-types-trace.h qapi/qapi-types-trace.c
-GENERATED_FILES += qapi/qapi-types-transaction.h qapi/qapi-types-transaction.c
-GENERATED_FILES += qapi/qapi-types-ui.h qapi/qapi-types-ui.c
-GENERATED_FILES += qapi/qapi-builtin-visit.h qapi/qapi-builtin-visit.c
-GENERATED_FILES += qapi/qapi-visit.h qapi/qapi-visit.c
-GENERATED_FILES += qapi/qapi-visit-block-core.h qapi/qapi-visit-block-core.c
-GENERATED_FILES += qapi/qapi-visit-block.h qapi/qapi-visit-block.c
-GENERATED_FILES += qapi/qapi-visit-char.h qapi/qapi-visit-char.c
-GENERATED_FILES += qapi/qapi-visit-common.h qapi/qapi-visit-common.c
-GENERATED_FILES += qapi/qapi-visit-crypto.h qapi/qapi-visit-crypto.c
-GENERATED_FILES += qapi/qapi-visit-introspect.h qapi/qapi-visit-introspect.c
-GENERATED_FILES += qapi/qapi-visit-job.h qapi/qapi-visit-job.c
-GENERATED_FILES += qapi/qapi-visit-migration.h qapi/qapi-visit-migration.c
-GENERATED_FILES += qapi/qapi-visit-misc.h qapi/qapi-visit-misc.c
-GENERATED_FILES += qapi/qapi-visit-net.h qapi/qapi-visit-net.c
-GENERATED_FILES += qapi/qapi-visit-rocker.h qapi/qapi-visit-rocker.c
-GENERATED_FILES += qapi/qapi-visit-run-state.h qapi/qapi-visit-run-state.c
-GENERATED_FILES += qapi/qapi-visit-sockets.h qapi/qapi-visit-sockets.c
-GENERATED_FILES += qapi/qapi-visit-tpm.h qapi/qapi-visit-tpm.c
-GENERATED_FILES += qapi/qapi-visit-trace.h qapi/qapi-visit-trace.c
-GENERATED_FILES += qapi/qapi-visit-transaction.h qapi/qapi-visit-transaction.c
-GENERATED_FILES += qapi/qapi-visit-ui.h qapi/qapi-visit-ui.c
-GENERATED_FILES += qapi/qapi-commands.h qapi/qapi-commands.c
-GENERATED_FILES += qapi/qapi-commands-block-core.h 
qapi/qapi-commands-block-core.c
-GENERATED_FILES += qapi/qapi-commands-block.h qapi/qapi-commands-block.c
-GENERATED_FILES += qapi/qapi-commands-char.h qapi/qapi-commands-char.c
-GENERATED_FILES += qapi/qapi-commands-common.h qapi/qapi-commands-common.c
-GENERATED_FILES += qapi/qapi-commands-crypto.h qapi/qapi-commands-crypto.c
-GENERATED_FILES += qapi/qapi-commands-introspect.h 
qapi/qapi-commands-introspect.c
-GENERATED_FILES += qapi/qapi-commands-job.h qapi/qapi-commands-job.c
-GENERATED_FILES += qapi/qapi-commands-migration.h 
qapi/qapi-commands-migration.c
-GENERATED_FILES += qapi/qapi-commands-misc.h qapi/qapi-commands-misc.c
-GENERATED_FILES += qapi/qapi-commands-net.h qapi/qapi-commands-net.c
-GENERATED_FILES += qapi/qapi-commands-rocker.h qapi/qapi-commands-rocker.c
-GENERATED_FILES += qapi/qapi-commands-run-state.h 
qapi/qapi-commands-run-state.c
-GENERATED_FILES += qapi/qapi-commands-sockets.h qapi/qapi-commands-sockets.c
-GENERATED_FILES += qapi/qapi-commands-tpm.h qapi/qapi-commands-tpm.c
-GENERATED_FILES += qapi/qapi-commands-trace.h qapi/qapi-commands-trace.c
-GENERATED_FILES += qapi/qapi-commands-transaction.h 
qapi/qapi-commands-transaction.c
-GENERATED_FILES += qapi/qapi-commands-ui.h 

[Qemu-devel] [RFC v1 23/23] configure: Add support for building RISC-V host

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 configure | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/configure b/configure
index 74e313a810..8a7b9fc933 100755
--- a/configure
+++ b/configure
@@ -700,6 +700,12 @@ elif check_define __s390__ ; then
   else
 cpu="s390"
   fi
+elif check_define __riscv ; then
+  if check_define _LP64 ; then
+cpu="riscv64"
+  elif check_define _ILP32 ; then
+cpu="riscv32"
+  fi
 elif check_define __arm__ ; then
   cpu="arm"
 elif check_define __aarch64__ ; then
@@ -712,7 +718,7 @@ ARCH=
 # Normalise host CPU name and set ARCH.
 # Note that this case should only have supported host CPUs, not guests.
 case "$cpu" in
-  ppc|ppc64|s390|s390x|sparc64|x32)
+  ppc|ppc64|s390|s390x|sparc64|x32|riscv32|riscv64)
 cpu="$cpu"
 supported_cpu="yes"
 eval "cross_cc_${cpu}=\$host_cc"
@@ -6809,6 +6815,8 @@ elif test "$ARCH" = "x86_64" -o "$ARCH" = "x32" ; then
   QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/i386 $QEMU_INCLUDES"
 elif test "$ARCH" = "ppc64" ; then
   QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/ppc $QEMU_INCLUDES"
+elif test "$ARCH" = "riscv32" -o "$ARCH" = "riscv64" ; then
+  QEMU_INCLUDES="-I\$(SRC_PATH)/tcg/riscv $QEMU_INCLUDES"
 else
   QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/\$(ARCH) $QEMU_INCLUDES"
 fi
@@ -7306,7 +7314,7 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
   ppc*)
 disas_config "PPC"
   ;;
-  riscv)
+  riscv*)
 disas_config "RISCV"
   ;;
   s390*)
-- 
2.19.1

Re: [Qemu-devel] [PATCH] qapi: Reduce Makefile boilerplate

[Eric Blake]

On 11/15/18 3:54 PM, Eric Blake wrote:

Adding a new qapi module had some rather tedious repetition to
wire it into Makefile. Add some indirection by taking advantage
of GNU Make string processing to expand a list of module names
into all the required artifacts, so that future additions of a
new module need only touch the list of module names.

Signed-off-by: Eric Blake 
---

I finally found time to follow through with my threats to make it
MUCH easier to add a new qapi/FOO.json file.

Should be no semantic change, but as it is not fixing an actual
bug, I don't care if it goes in 3.1 or 4.0.

  Makefile | 194 +++
  1 file changed, 25 insertions(+), 169 deletions(-)


I'm trying to do the same thing to Makefile.objs, but when I use:

common-obj-y += $(QAPI_MODULES:%=qapi/qapi-commands-%.o)

or the longer $(patsubst %,qapi,qapi-commands-%.o,$(QAPI_MODULES))

both before and after the change, 'make print-common-obj-y | grep qapi' 
returns identical content, but after the change, the linker fails with:


  LINKx86_64-softmmu/qemu-system-x86_64
monitor.o: In function `monitor_init_qmp_commands':
/home/eblake/qemu/monitor.c:1200: undefined reference to 
`qmp_marshal_qmp_capabilities'

monitor.o: In function `qmp_greeting':
/home/eblake/qemu/monitor.c:4342: undefined reference to 
`qmp_marshal_query_version'

../qapi/qapi-commands.o: In function `qmp_init_marshal':
/home/eblake/qemu/qapi/qapi-commands.c:30: undefined reference to 
`qmp_marshal_query_status'

...

So something about variable expansions is NOT playing nicely with our

dummy := $(call unnest-vars,, \
stub-obj-y \
chardev-obj-y \
...
common-obj-y \

that builds up the set of files the linker needs to see.  But I have 
_no_ idea what is going wrong that makes unnest-vars unable to see 
through a variable expansion of .o files.  Ideas on how to compress 
Makefile.objs to avoid the redundancy would be appreciated.


--
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

[Qemu-devel] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 accel/tcg/user-exec.c | 48 +++
 1 file changed, 48 insertions(+)

diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index cd75829cf2..bb693484ed 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -571,6 +571,54 @@ int cpu_signal_handler(int host_signum, void *pinfo,
 return handle_cpu_signal(pc, info, is_write, >uc_sigmask);
 }
 
+#elif defined(__riscv)
+
+int cpu_signal_handler(int host_signum, void *pinfo,
+   void *puc)
+{
+siginfo_t *info = pinfo;
+ucontext_t *uc = puc;
+greg_t pc = uc->uc_mcontext.__gregs[REG_PC];
+
+/* Detect store by reading the instruction at the program
+   counter. Note: we currently only generate 32-bit
+   instructions so we thus only detect 32-bit stores */
+uint32_t insn = *(uint32_t *)pc;
+int is_write = 0;
+switch (((insn >> 0) & 0b11)) {
+case 3:
+switch (((insn >> 2) & 0b1)) {
+case 8:
+switch (((insn >> 12) & 0b111)) {
+case 0: /* sb */
+case 1: /* sh */
+case 2: /* sw */
+case 3: /* sd */
+case 4: /* sq */
+is_write = 1;
+break;
+default:
+break;
+}
+break;
+case 9:
+switch (((insn >> 12) & 0b111)) {
+case 2: /* fsw */
+case 3: /* fsd */
+case 4: /* fsq */
+is_write = 1;
+break;
+default:
+break;
+}
+break;
+default:
+break;
+}
+}
+return handle_cpu_signal(pc, info, is_write, >uc_sigmask);
+}
+
 #else
 
 #error host CPU specific signal handler needed
-- 
2.19.1

[Qemu-devel] [RFC v1 16/23] riscv: tcg-target: Add slowpath load and store instructions

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.inc.c | 240 +
 1 file changed, 240 insertions(+)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index b449e17295..5fe6935e24 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -718,6 +718,246 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit 
*arg)
 tcg_out_call_int(s, arg, false);
 }
 
+static void tcg_out_mb(TCGContext *s, TCGArg a0)
+{
+static const RISCVInsn fence[] = {
+[0 ... TCG_MO_ALL] = OPC_FENCE_RW_RW,
+[TCG_MO_LD_LD] = OPC_FENCE_R_R,
+[TCG_MO_ST_LD] = OPC_FENCE_W_R,
+[TCG_MO_LD_ST] = OPC_FENCE_R_W,
+[TCG_MO_ST_ST] = OPC_FENCE_W_W,
+[TCG_BAR_LDAQ] = OPC_FENCE_R_RW,
+[TCG_BAR_STRL] = OPC_FENCE_RW_W,
+[TCG_BAR_SC]   = OPC_FENCE_RW_RW,
+};
+tcg_out32(s, fence[a0 & TCG_MO_ALL]);
+}
+
+/*
+ * Load/store and TLB
+ */
+
+#if defined(CONFIG_SOFTMMU)
+#include "tcg-ldst.inc.c"
+
+/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
+ * TCGMemOpIdx oi, uintptr_t ra)
+ */
+static void * const qemu_ld_helpers[16] = {
+[MO_UB]   = helper_ret_ldub_mmu,
+[MO_SB]   = helper_ret_ldsb_mmu,
+[MO_LEUW] = helper_le_lduw_mmu,
+[MO_LESW] = helper_le_ldsw_mmu,
+[MO_LEUL] = helper_le_ldul_mmu,
+[MO_LESL] = helper_le_ldsl_mmu,
+[MO_LEQ]  = helper_le_ldq_mmu,
+[MO_BEUW] = helper_be_lduw_mmu,
+[MO_BESW] = helper_be_ldsw_mmu,
+[MO_BEUL] = helper_be_ldul_mmu,
+[MO_BESL] = helper_be_ldsl_mmu,
+[MO_BEQ]  = helper_be_ldq_mmu,
+};
+
+/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
+ * uintxx_t val, TCGMemOpIdx oi,
+ * uintptr_t ra)
+ */
+static void * const qemu_st_helpers[16] = {
+[MO_UB]   = helper_ret_stb_mmu,
+[MO_LEUW] = helper_le_stw_mmu,
+[MO_LEUL] = helper_le_stl_mmu,
+[MO_LEQ]  = helper_le_stq_mmu,
+[MO_BEUW] = helper_be_stw_mmu,
+[MO_BEUL] = helper_be_stl_mmu,
+[MO_BEQ]  = helper_be_stq_mmu,
+};
+
+static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
+ TCGReg addrh, TCGMemOpIdx oi,
+ tcg_insn_unit **label_ptr, bool is_load)
+{
+TCGMemOp opc = get_memop(oi);
+unsigned s_bits = opc & MO_SIZE;
+unsigned a_bits = get_alignment_bits(opc);
+target_ulong mask;
+int mem_index = get_mmuidx(oi);
+int cmp_off
+= (is_load
+   ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
+   : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
+int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
+int addend_offset = (offsetof(CPUTLBEntry, addend)) -
+(is_load ? offsetof(CPUTLBEntry, addr_read)
+ : offsetof(CPUTLBEntry, addr_write));
+RISCVInsn load_cmp_op = (TARGET_LONG_BITS == 64 ? OPC_LD :
+ TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW);
+RISCVInsn load_add_op = TCG_TARGET_REG_BITS == 64 ? OPC_LD : OPC_LW;
+TCGReg base = TCG_AREG0;
+TCGReg cmpr;
+
+/* We don't support oversize guests */
+if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
+g_assert_not_reached();
+}
+
+/* We don't support unaligned accesses. */
+if (a_bits < s_bits) {
+a_bits = s_bits;
+}
+mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1);
+
+
+/* Compensate for very large offsets.  */
+if (add_off >= 0x1000) {
+int adj;
+base = TCG_REG_TMP2;
+if (cmp_off <= 2 * 0xfff) {
+adj = 0xfff;
+tcg_out_opc_imm(s, OPC_ADDI, base, TCG_AREG0, adj);
+} else {
+adj = cmp_off - sextract32(cmp_off, 0, 12);
+tcg_debug_assert(add_off - adj >= -0x1000
+ && add_off - adj < 0x1000);
+
+tcg_out_opc_upper(s, OPC_LUI, base, adj);
+tcg_out_opc_reg(s, OPC_ADD, base, TCG_REG_ZERO, TCG_AREG0);
+}
+add_off -= adj;
+cmp_off -= adj;
+}
+
+/* Extract the page index.  */
+if (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS < 12) {
+tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP0, addrl,
+TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
+tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP0, TCG_REG_TMP0,
+MAKE_64BIT_MASK(CPU_TLB_ENTRY_BITS, CPU_TLB_BITS));
+} else {
+tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP0, addrl, TARGET_PAGE_BITS);
+tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP0, TCG_REG_TMP0,
+MAKE_64BIT_MASK(0, CPU_TLB_BITS));
+tcg_out_opc_imm(s, OPC_SLLI, TCG_REG_TMP0, TCG_REG_TMP0,
+CPU_TLB_ENTRY_BITS);
+}
+
+/* Add 

[Qemu-devel] [RFC v1 14/23] riscv: tcg-target: Add the out load and store instructions

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.inc.c | 56 ++
 1 file changed, 56 insertions(+)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 646a4d3ebd..bc433170c4 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -518,6 +518,62 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, 
TCGReg arg)
 tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
 }
 
+static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
+ TCGReg addr, intptr_t offset)
+{
+int32_t imm12 = sextract32(offset, 0, 12);
+if (offset != imm12) {
+tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
+if (addr != TCG_REG_ZERO) {
+tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr);
+}
+addr = TCG_REG_TMP2;
+}
+switch (opc) {
+case OPC_SB:
+case OPC_SH:
+case OPC_SW:
+case OPC_SD:
+tcg_out_opc_store(s, opc, addr, data, imm12);
+break;
+case OPC_LB:
+case OPC_LBU:
+case OPC_LH:
+case OPC_LHU:
+case OPC_LW:
+case OPC_LWU:
+case OPC_LD:
+tcg_out_opc_imm(s, opc, data, addr, imm12);
+break;
+default:
+g_assert_not_reached();
+}
+}
+
+static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
+   TCGReg arg1, intptr_t arg2)
+{
+bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
+tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2);
+}
+
+static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
+   TCGReg arg1, intptr_t arg2)
+{
+bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32);
+tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2);
+}
+
+static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
+TCGReg base, intptr_t ofs)
+{
+if (val == 0) {
+tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
+return true;
+}
+return false;
+}
+
 void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
   uintptr_t addr)
 {
-- 
2.19.1

[Qemu-devel] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.inc.c | 144 +
 1 file changed, 144 insertions(+)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index bc433170c4..b449e17295 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -574,6 +574,150 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, 
TCGArg val,
 return false;
 }
 
+static const struct {
+RISCVInsn op;
+bool swap;
+} tcg_brcond_to_riscv[] = {
+[TCG_COND_EQ] =  { OPC_BEQ,  false },
+[TCG_COND_NE] =  { OPC_BNE,  false },
+[TCG_COND_LT] =  { OPC_BLT,  false },
+[TCG_COND_GE] =  { OPC_BGE,  false },
+[TCG_COND_LE] =  { OPC_BGE,  true  },
+[TCG_COND_GT] =  { OPC_BLT,  true  },
+[TCG_COND_LTU] = { OPC_BLTU, false },
+[TCG_COND_GEU] = { OPC_BGEU, false },
+[TCG_COND_LEU] = { OPC_BGEU, true  },
+[TCG_COND_GTU] = { OPC_BLTU, true  }
+};
+
+static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
+   TCGReg arg2, TCGLabel *l)
+{
+RISCVInsn op = tcg_brcond_to_riscv[cond].op;
+bool swap = tcg_brcond_to_riscv[cond].swap;
+
+tcg_out_opc_branch(s, op, swap ? arg2 : arg1, swap ? arg1 : arg2, 0);
+
+if (l->has_value) {
+reloc_sbimm12(s->code_ptr - 1, l->u.value_ptr);
+} else {
+tcg_out_reloc(s, s->code_ptr - 1, R_RISCV_BRANCH, l, 0);
+}
+}
+
+static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
+TCGReg arg1, TCGReg arg2)
+{
+switch (cond) {
+case TCG_COND_EQ:
+tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
+tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1);
+break;
+case TCG_COND_NE:
+tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2);
+tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret);
+break;
+case TCG_COND_LT:
+tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
+break;
+case TCG_COND_GE:
+tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2);
+tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
+break;
+case TCG_COND_LE:
+tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
+tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
+break;
+case TCG_COND_GT:
+tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1);
+break;
+case TCG_COND_LTU:
+tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
+break;
+case TCG_COND_GEU:
+tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2);
+tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
+break;
+case TCG_COND_LEU:
+tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
+tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1);
+break;
+case TCG_COND_GTU:
+tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1);
+break;
+default:
+ g_assert_not_reached();
+ break;
+ }
+}
+
+static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
+TCGReg bl, TCGReg bh, TCGLabel *l)
+{
+/* todo */
+g_assert_not_reached();
+}
+
+static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
+ TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
+{
+/* todo */
+g_assert_not_reached();
+}
+
+static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target)
+{
+ptrdiff_t offset = tcg_pcrel_diff(s, target);
+tcg_debug_assert(offset == sextract64(offset, 0, 26));
+tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset);
+}
+
+static inline void tcg_out_goto_long(TCGContext *s, tcg_insn_unit *target)
+{
+ptrdiff_t offset = tcg_pcrel_diff(s, target);
+
+if (offset == sextract64(offset, 0, 26)) {
+tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset);
+} else {
+tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, (intptr_t)target);
+tcg_out_opc_jump(s, OPC_JAL, TCG_REG_TMP0, 0);
+}
+}
+
+static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail)
+{
+TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
+ptrdiff_t offset = tcg_pcrel_diff(s, arg);
+if (offset == sextract32(offset, 1, 20) << 1) {
+/* short jump: -2097150 to 2097152 */
+tcg_out_opc_jump(s, OPC_JAL, link, offset);
+} else if (TCG_TARGET_REG_BITS == 32 ||
+offset == sextract32(offset, 1, 31) << 1) {
+/* long jump: -2147483646 to 2147483648 */
+tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0);
+tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0);
+reloc_call(s->code_ptr - 2, arg);
+} else if (TCG_TARGET_REG_BITS == 64) {
+/* far jump: 64-bit */
+tcg_target_long imm = sextract32((tcg_target_long)arg, 0, 12);
+tcg_target_long base = (tcg_target_long)arg - imm;
+tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base);
+tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm);
+} else {
+

[Qemu-devel] [RFC v1 19/23] riscv: tcg-target: Add the prologue generation

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.inc.c | 66 ++
 1 file changed, 66 insertions(+)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index bf3b04f7dc..4b8f65f367 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -1575,6 +1575,72 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode 
op)
 }
 }
 
+static const int tcg_target_callee_save_regs[] = {
+TCG_REG_S0,   /* used for the global env (TCG_AREG0) */
+TCG_REG_S1,
+TCG_REG_S2,
+TCG_REG_S3,
+TCG_REG_S4,
+TCG_REG_S5,
+TCG_REG_S6,
+TCG_REG_S7,
+TCG_REG_S8,
+TCG_REG_S9,
+TCG_REG_S10,
+TCG_REG_S11,
+TCG_REG_RA,   /* should be last for ABI compliance */
+};
+
+/* Stack frame parameters.  */
+#define REG_SIZE   (TCG_TARGET_REG_BITS / 8)
+#define SAVE_SIZE  ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
+#define TEMP_SIZE  (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
+#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
+ + TCG_TARGET_STACK_ALIGN - 1) \
+& -TCG_TARGET_STACK_ALIGN)
+#define SAVE_OFS   (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
+
+/* We're expecting to be able to use an immediate for frame allocation.  */
+QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff);
+
+/* Generate global QEMU prologue and epilogue code */
+static void tcg_target_qemu_prologue(TCGContext *s)
+{
+int i;
+
+tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
+
+/* TB prologue */
+tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
+for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
+tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
+   TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
+}
+
+#if !defined(CONFIG_SOFTMMU)
+tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
+tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+#endif
+
+/* Call generated code */
+tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
+tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 
0);
+
+/* Return path for goto_ptr. Set return value to 0 */
+s->code_gen_epilogue = s->code_ptr;
+tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO);
+
+/* TB epilogue */
+tb_ret_addr = s->code_ptr;
+for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
+tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
+   TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
+}
+
+tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
+tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
+}
+
 void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
   uintptr_t addr)
 {
-- 
2.19.1

[Qemu-devel] [RFC v1 13/23] riscv: tcg-target: Add the extract instructions

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.inc.c | 34 ++
 1 file changed, 34 insertions(+)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 0e891e24c9..646a4d3ebd 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -484,6 +484,40 @@ static void tcg_out_movi(TCGContext *s, TCGType type, 
TCGReg rd,
 }
 }
 
+static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff);
+}
+
+static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+tcg_out_opc_imm(s, OPC_SLLI, ret, arg, TCG_TARGET_REG_BITS - 16);
+tcg_out_opc_imm(s, OPC_SRLI, ret, ret, TCG_TARGET_REG_BITS - 16);
+}
+
+static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32);
+tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32);
+}
+
+static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+tcg_out_opc_imm(s, OPC_SLLI, ret, arg, TCG_TARGET_REG_BITS - 8);
+tcg_out_opc_imm(s, OPC_SRAI, ret, ret, TCG_TARGET_REG_BITS - 8);
+}
+
+static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+tcg_out_opc_imm(s, OPC_SLLI, ret, arg, TCG_TARGET_REG_BITS - 16);
+tcg_out_opc_imm(s, OPC_SRAI, ret, ret, TCG_TARGET_REG_BITS - 16);
+}
+
+static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
+{
+tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
+}
+
 void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
   uintptr_t addr)
 {
-- 
2.19.1

[Qemu-devel] [RFC v1 22/23] dias: Add RISC-V support

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 disas.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/disas.c b/disas.c
index 5325b7e6be..82a408f272 100644
--- a/disas.c
+++ b/disas.c
@@ -522,8 +522,14 @@ void disas(FILE *out, void *code, unsigned long size)
 # ifdef _ARCH_PPC64
 s.info.cap_mode = CS_MODE_64;
 # endif
-#elif defined(__riscv__)
-print_insn = print_insn_riscv;
+#elif defined(__riscv) && defined(CONFIG_RISCV_DIS)
+#if defined(_ILP32)
+print_insn = print_insn_riscv32;
+#elif defined(_LP64)
+print_insn = print_insn_riscv64;
+#else
+#error unsupported RISC-V ABI
+#endif
 #elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS)
 print_insn = print_insn_arm_a64;
 s.info.cap_arch = CS_ARCH_ARM64;
-- 
2.19.1

[Qemu-devel] [RFC v1 08/23] riscv: tcg-target: Add support for the constraints

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.inc.c | 139 +
 1 file changed, 139 insertions(+)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index a9c57493a0..e585740870 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -119,6 +119,145 @@ static const int tcg_target_call_oarg_regs[] = {
 #define TCG_CT_CONST_S12   0x200
 #define TCG_CT_CONST_N12   0x400
 
+/* parse target specific constraints */
+static const char *target_parse_constraint(TCGArgConstraint *ct,
+   const char *ct_str, TCGType type)
+{
+switch (*ct_str++) {
+case 'r':
+ct->ct |= TCG_CT_REG;
+ct->u.regs = 0x;
+break;
+case 'L':
+/* qemu_ld/qemu_st constraint */
+ct->ct |= TCG_CT_REG;
+ct->u.regs = 0x;
+/* qemu_ld/qemu_st uses TCG_REG_TMP0 */
+#if defined(CONFIG_SOFTMMU)
+/* tcg_out_tlb_load uses TCG_REG_TMP0/TMP1 and TCG_REG_L0/L1 */
+/* tcg_regset_reset_reg(ct->u.regs, TCG_REG_TMP0); */
+/* tcg_regset_reset_reg(ct->u.regs, TCG_REG_TMP1); */
+tcg_regset_reset_reg(ct->u.regs, TCG_REG_TMP2);
+
+tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]);
+tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]);
+tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]);
+tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]);
+tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]);
+#endif
+break;
+case 'I':
+ct->ct |= TCG_CT_CONST_S12;
+break;
+case 'N':
+ct->ct |= TCG_CT_CONST_N12;
+break;
+case 'Z':
+/* we can use a zero immediate as a zero register argument. */
+ct->ct |= TCG_CT_CONST_ZERO;
+break;
+default:
+return NULL;
+}
+return ct_str;
+}
+
+/* test if a constant matches the constraint */
+static int tcg_target_const_match(tcg_target_long val, TCGType type,
+  const TCGArgConstraint *arg_ct)
+{
+int ct = arg_ct->ct;
+if (ct & TCG_CT_CONST) {
+return 1;
+}
+if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
+return 1;
+}
+if ((ct & TCG_CT_CONST_S12) && val >= -2048 && val <= 2047) {
+return 1;
+}
+if ((ct & TCG_CT_CONST_N12) && val >= -2047 && val <= 2048) {
+return 1;
+}
+return 0;
+}
+
+/*
+ * RISC-V Base ISA opcodes (IM)
+ */
+
+typedef enum {
+OPC_ADD = 0x33,
+OPC_ADDI = 0x13,
+OPC_ADDIW = 0x1b,
+OPC_ADDW = 0x3b,
+OPC_AND = 0x7033,
+OPC_ANDI = 0x7013,
+OPC_AUIPC = 0x17,
+OPC_BEQ = 0x63,
+OPC_BGE = 0x5063,
+OPC_BGEU = 0x7063,
+OPC_BLT = 0x4063,
+OPC_BLTU = 0x6063,
+OPC_BNE = 0x1063,
+OPC_DIV = 0x2004033,
+OPC_DIVU = 0x2005033,
+OPC_DIVUW = 0x200503b,
+OPC_DIVW = 0x200403b,
+OPC_JAL = 0x6f,
+OPC_JALR = 0x67,
+OPC_LB = 0x3,
+OPC_LBU = 0x4003,
+OPC_LD = 0x3003,
+OPC_LH = 0x1003,
+OPC_LHU = 0x5003,
+OPC_LUI = 0x37,
+OPC_LW = 0x2003,
+OPC_LWU = 0x6003,
+OPC_MUL = 0x233,
+OPC_MULH = 0x2001033,
+OPC_MULHSU = 0x2002033,
+OPC_MULHU = 0x2003033,
+OPC_MULW = 0x23b,
+OPC_OR = 0x6033,
+OPC_ORI = 0x6013,
+OPC_REM = 0x2006033,
+OPC_REMU = 0x2007033,
+OPC_REMUW = 0x200703b,
+OPC_REMW = 0x200603b,
+OPC_SB = 0x23,
+OPC_SD = 0x3023,
+OPC_SH = 0x1023,
+OPC_SLL = 0x1033,
+OPC_SLLI = 0x1013,
+OPC_SLLIW = 0x101b,
+OPC_SLLW = 0x103b,
+OPC_SLT = 0x2033,
+OPC_SLTI = 0x2013,
+OPC_SLTIU = 0x3013,
+OPC_SLTU = 0x3033,
+OPC_SRA = 0x40005033,
+OPC_SRAI = 0x40005013,
+OPC_SRAIW = 0x4000501b,
+OPC_SRAW = 0x4000503b,
+OPC_SRL = 0x5033,
+OPC_SRLI = 0x5013,
+OPC_SRLIW = 0x501b,
+OPC_SRLW = 0x503b,
+OPC_SUB = 0x4033,
+OPC_SUBW = 0x403b,
+OPC_SW = 0x2023,
+OPC_XOR = 0x4033,
+OPC_XORI = 0x4013,
+OPC_FENCE_RW_RW = 0x033f,
+OPC_FENCE_R_R = 0x022f,
+OPC_FENCE_W_R = 0x012f,
+OPC_FENCE_R_W = 0x021f,
+OPC_FENCE_W_W = 0x011f,
+OPC_FENCE_R_RW = 0x023f,
+OPC_FENCE_RW_W = 0x031f,
+} RISCVInsn;
+
 typedef struct {
 DebugFrameHeader h;
 uint8_t fde_def_cfa[4];
-- 
2.19.1

[Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init code

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.inc.c | 33 +
 1 file changed, 33 insertions(+)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 4b8f65f367..dfc4e8b44c 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -1641,6 +1641,39 @@ static void tcg_target_qemu_prologue(TCGContext *s)
 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0);
 }
 
+static void tcg_target_init(TCGContext *s)
+{
+tcg_target_available_regs[TCG_TYPE_I32] = 0x;
+if (TCG_TARGET_REG_BITS == 64) {
+tcg_target_available_regs[TCG_TYPE_I64] = 0x;
+}
+
+tcg_target_call_clobber_regs = -1u;
+tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
+tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
+tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
+tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3);
+tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4);
+tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5);
+tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6);
+tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7);
+tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
+tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
+tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10);
+tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11);
+
+s->reserved_regs = 0;
+tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
+tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
+tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
+tcg_regset_set_reg(s->reserved_regs, TCG_REG_L0);
+tcg_regset_set_reg(s->reserved_regs, TCG_REG_L1);
+tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA);
+tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
+tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP);
+tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
+}
+
 void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
   uintptr_t addr)
 {
-- 
2.19.1

[Qemu-devel] [RFC v1 12/23] riscv: tcg-target: Add the mov and movi instruction

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.inc.c | 62 ++
 1 file changed, 62 insertions(+)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 475feca906..0e891e24c9 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -422,6 +422,68 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type,
 }
 }
 
+/*
+ * TCG intrinsics
+ */
+
+static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+{
+if (ret == arg) {
+return;
+}
+switch (type) {
+case TCG_TYPE_I32:
+case TCG_TYPE_I64:
+tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);
+break;
+default:
+g_assert_not_reached();
+}
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
+ tcg_target_long val)
+{
+tcg_target_long lo = sextract32(val, 0, 12);
+tcg_target_long hi = val - lo;
+
+RISCVInsn add32_op = TCG_TARGET_REG_BITS == 64 ? OPC_ADDIW : OPC_ADDI;
+
+#if TCG_TARGET_REG_BITS == 64
+ptrdiff_t offset = tcg_pcrel_diff(s, (void *)val);
+#endif
+
+if (val == lo) {
+tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, val);
+} else if (val && !(val & (val - 1))) {
+/* power of 2 */
+tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, 1);
+tcg_out_opc_imm(s, OPC_SLLI, rd, rd, ctz64(val));
+} else if (TCG_TARGET_REG_BITS == 64 &&
+   !(val >> 31 == 0 || val >> 31 == -1)) {
+int shift = 12 + ctz64(hi >> 12);
+hi >>= shift;
+tcg_out_movi(s, type, rd, hi);
+tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift);
+if (lo != 0) {
+tcg_out_opc_imm(s, OPC_ADDI, rd, rd, lo);
+}
+#if TCG_TARGET_REG_BITS == 64
+} else if (offset == sextract32(offset, 1, 31) << 1) {
+tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
+tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0);
+reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val);
+#endif
+} else {
+if (hi != 0) {
+tcg_out_opc_upper(s, OPC_LUI, rd, hi);
+}
+if (lo != 0) {
+tcg_out_opc_imm(s, add32_op, rd, hi == 0 ? TCG_REG_ZERO : rd, lo);
+}
+}
+}
+
 void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
   uintptr_t addr)
 {
-- 
2.19.1

[Qemu-devel] [RFC v1 06/23] riscv: Add the tcg target registers

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.inc.c | 120 +
 1 file changed, 120 insertions(+)
 create mode 100644 tcg/riscv/tcg-target.inc.c

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
new file mode 100644
index 00..e5eca4bbbe
--- /dev/null
+++ b/tcg/riscv/tcg-target.inc.c
@@ -0,0 +1,120 @@
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2018 SiFive, Inc
+ * Copyright (c) 2008-2009 Arnaud Patard 
+ * Copyright (c) 2009 Aurelien Jarno 
+ * Copyright (c) 2008 Fabrice Bellard
+ *
+ * Based on i386/tcg-target.c and mips/tcg-target.c
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifdef CONFIG_DEBUG_TCG
+static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
+"zero",
+"ra",
+"sp",
+"gp",
+"tp",
+"t0",
+"t1",
+"t2",
+"s0",
+"s1",
+"a0",
+"a1",
+"a2",
+"a3",
+"a4",
+"a5",
+"a6",
+"a7",
+"s2",
+"s3",
+"s4",
+"s5",
+"s6",
+"s7",
+"s8",
+"s9",
+"s10",
+"s11",
+"t3",
+"t4",
+"t5",
+"t6"
+};
+#endif
+
+static const int tcg_target_reg_alloc_order[] = {
+/* Call saved registers */
+/* TCG_REG_S0 reservered for TCG_AREG0 */
+TCG_REG_S1,
+TCG_REG_S2,
+TCG_REG_S3,
+TCG_REG_S4,
+TCG_REG_S5,
+TCG_REG_S6,
+TCG_REG_S7,
+TCG_REG_S8,
+TCG_REG_S9,
+TCG_REG_S10,
+TCG_REG_S11,
+
+/* Call clobbered registers */
+TCG_REG_T0,
+TCG_REG_T1,
+TCG_REG_T2,
+TCG_REG_T3,
+TCG_REG_T4,
+TCG_REG_T5,
+TCG_REG_T6,
+
+/* Argument registers */
+TCG_REG_A0,
+TCG_REG_A1,
+TCG_REG_A2,
+TCG_REG_A3,
+TCG_REG_A4,
+TCG_REG_A5,
+TCG_REG_A6,
+TCG_REG_A7,
+};
+
+static const int tcg_target_call_iarg_regs[] = {
+TCG_REG_A0,
+TCG_REG_A1,
+TCG_REG_A2,
+TCG_REG_A3,
+TCG_REG_A4,
+TCG_REG_A5,
+TCG_REG_A6,
+TCG_REG_A7,
+};
+
+static const int tcg_target_call_oarg_regs[] = {
+TCG_REG_A0,
+TCG_REG_A1,
+};
+
+#define TCG_CT_CONST_ZERO  0x100
+#define TCG_CT_CONST_S12   0x200
+#define TCG_CT_CONST_N12   0x400
-- 
2.19.1

[Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct load and store instructions

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.inc.c | 145 +
 1 file changed, 145 insertions(+)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 5fe6935e24..c4a013a962 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -958,6 +958,151 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, 
TCGLabelQemuLdst *l)
 }
 #endif /* CONFIG_SOFTMMU */
 
+static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
+   TCGReg base, TCGMemOp opc, bool is_64)
+{
+const TCGMemOp bswap = opc & MO_BSWAP;
+
+/* TODO: Handle byte swapping */
+
+switch (opc & (MO_SSIZE)) {
+case MO_UB:
+tcg_out_opc_imm(s, OPC_LBU, lo, base, 0);
+break;
+case MO_SB:
+tcg_out_opc_imm(s, OPC_LB, lo, base, 0);
+break;
+case MO_UW:
+tcg_out_opc_imm(s, OPC_LHU, lo, base, 0);
+break;
+case MO_SW:
+tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
+break;
+case MO_UL:
+if (TCG_TARGET_REG_BITS == 64 && is_64) {
+tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
+break;
+}
+/* FALLTHRU */
+case MO_SL:
+tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
+break;
+case MO_Q:
+/* Prefer to load from offset 0 first, but allow for overlap.  */
+if (TCG_TARGET_REG_BITS == 64) {
+tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
+} else {
+tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
+tcg_out_opc_imm(s, OPC_LW, hi, base, 4);
+}
+break;
+default:
+g_assert_not_reached();
+}
+}
+
+static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
+{
+TCGReg addr_regl, addr_regh __attribute__((unused));
+TCGReg data_regl, data_regh;
+TCGMemOpIdx oi;
+TCGMemOp opc;
+#if defined(CONFIG_SOFTMMU)
+tcg_insn_unit *label_ptr[1];
+#endif
+TCGReg base = TCG_REG_TMP0;
+
+data_regl = *args++;
+data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
+addr_regl = *args++;
+addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
+oi = *args++;
+opc = get_memop(oi);
+
+#if defined(CONFIG_SOFTMMU)
+tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1);
+tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
+add_qemu_ldst_label(s, 1, oi,
+(is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
+data_regl, data_regh, addr_regl, addr_regh,
+s->code_ptr, label_ptr);
+#else
+if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+tcg_out_ext32u(s, base, addr_regl);
+addr_regl = base;
+}
+tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl);
+tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64);
+#endif
+}
+
+static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
+   TCGReg base, TCGMemOp opc)
+{
+const TCGMemOp bswap = opc & MO_BSWAP;
+
+/* TODO: Handle byte swapping */
+
+switch (opc & (MO_SSIZE)) {
+case MO_8:
+tcg_out_opc_store(s, OPC_SB, base, lo, 0);
+break;
+case MO_16:
+tcg_out_opc_store(s, OPC_SH, base, lo, 0);
+break;
+case MO_32:
+tcg_out_opc_store(s, OPC_SW, base, lo, 0);
+break;
+case MO_64:
+if (TCG_TARGET_REG_BITS == 64) {
+tcg_out_opc_store(s, OPC_SD, base, lo, 0);
+} else {
+tcg_out_opc_store(s, OPC_SW, base, lo, 0);
+tcg_out_opc_store(s, OPC_SW, base, hi, 4);
+}
+break;
+default:
+g_assert_not_reached();
+}
+}
+
+static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
+{
+TCGReg addr_regl, addr_regh __attribute__((unused));
+TCGReg data_regl, data_regh;
+TCGMemOpIdx oi;
+TCGMemOp opc;
+#if defined(CONFIG_SOFTMMU)
+tcg_insn_unit *label_ptr[1];
+TCGReg base = TCG_REG_L0;
+#else
+TCGReg base = TCG_REG_TMP0;
+#endif
+
+data_regl = *args++;
+data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
+addr_regl = *args++;
+addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
+oi = *args++;
+opc = get_memop(oi);
+
+#if defined(CONFIG_SOFTMMU)
+tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0);
+tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc);
+add_qemu_ldst_label(s, 0, oi,
+(is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32),
+data_regl, data_regh, addr_regl, addr_regh,
+s->code_ptr, label_ptr);
+#else
+if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+tcg_out_ext32u(s, base, addr_regl);
+addr_regl = base;
+}
+tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, 

[Qemu-devel] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.inc.c | 51 ++
 1 file changed, 51 insertions(+)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index d402e48cbf..475feca906 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -371,6 +371,57 @@ static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc,
 tcg_out32(s, encode_uj(opc, rd, imm));
 }
 
+/*
+ * Relocations
+ */
+
+static void reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
+tcg_debug_assert(offset == sextract32(offset, 1, 12) << 1);
+
+code_ptr[0] |= encode_sbimm12(offset);
+}
+
+static void reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
+tcg_debug_assert(offset == sextract32(offset, 1, 20) << 1);
+
+code_ptr[0] |= encode_ujimm12(offset);
+}
+
+static void reloc_call(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
+{
+intptr_t offset = (intptr_t)target - (intptr_t)code_ptr;
+tcg_debug_assert(offset == (int32_t)offset);
+
+int32_t hi20 = ((offset + 0x800) >> 12) << 12;
+int32_t lo12 = offset - hi20;
+
+code_ptr[0] |= encode_uimm20(hi20);
+code_ptr[1] |= encode_imm12(lo12);
+}
+
+static void patch_reloc(tcg_insn_unit *code_ptr, int type,
+intptr_t value, intptr_t addend)
+{
+tcg_debug_assert(addend == 0);
+switch (type) {
+case R_RISCV_BRANCH:
+reloc_sbimm12(code_ptr, (tcg_insn_unit *)value);
+break;
+case R_RISCV_JAL:
+reloc_jimm20(code_ptr, (tcg_insn_unit *)value);
+break;
+case R_RISCV_CALL:
+reloc_call(code_ptr, (tcg_insn_unit *)value);
+break;
+default:
+tcg_abort();
+}
+}
+
 void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
   uintptr_t addr)
 {
-- 
2.19.1

[Qemu-devel] [RFC v1 18/23] riscv: tcg-target: Add the out op decoder

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.inc.c | 472 +
 1 file changed, 472 insertions(+)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index c4a013a962..bf3b04f7dc 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -1103,6 +1103,478 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg 
*args, bool is_64)
 #endif
 }
 
+static tcg_insn_unit *tb_ret_addr;
+
+static void tcg_out_op(TCGContext *s, TCGOpcode opc,
+   const TCGArg *args, const int *const_args)
+{
+TCGArg a0 = args[0];
+TCGArg a1 = args[1];
+TCGArg a2 = args[2];
+int c2 = const_args[2];
+const bool is32bit = TCG_TARGET_REG_BITS == 32;
+
+switch (opc) {
+case INDEX_op_exit_tb:
+/* Reuse the zeroing that exists for goto_ptr.  */
+if (a0 == 0) {
+tcg_out_goto_long(s, s->code_gen_epilogue);
+} else {
+tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0);
+tcg_out_goto_long(s, tb_ret_addr);
+}
+break;
+
+case INDEX_op_goto_tb:
+if (s->tb_jmp_insn_offset) {
+/* direct jump method */
+s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s);
+/* should align on 64-bit boundary for atomic patching */
+tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0);
+tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0);
+} else {
+/* indirect jump method */
+tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO,
+   (uintptr_t)(s->tb_jmp_target_addr + a0));
+tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0);
+}
+s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s);
+break;
+
+case INDEX_op_goto_ptr:
+tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0);
+break;
+
+case INDEX_op_br:
+tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0);
+tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0);
+break;
+
+case INDEX_op_ld8u_i32:
+case INDEX_op_ld8u_i64:
+tcg_out_ldst(s, OPC_LBU, a0, a1, a2);
+break;
+case INDEX_op_ld8s_i32:
+case INDEX_op_ld8s_i64:
+tcg_out_ldst(s, OPC_LB, a0, a1, a2);
+break;
+case INDEX_op_ld16u_i32:
+case INDEX_op_ld16u_i64:
+tcg_out_ldst(s, OPC_LHU, a0, a1, a2);
+break;
+case INDEX_op_ld16s_i32:
+case INDEX_op_ld16s_i64:
+tcg_out_ldst(s, OPC_LH, a0, a1, a2);
+break;
+case INDEX_op_ld32u_i64:
+tcg_out_ldst(s, OPC_LWU, a0, a1, a2);
+break;
+case INDEX_op_ld_i32:
+case INDEX_op_ld32s_i64:
+tcg_out_ldst(s, OPC_LW, a0, a1, a2);
+break;
+case INDEX_op_ld_i64:
+tcg_out_ldst(s, OPC_LD, a0, a1, a2);
+break;
+
+case INDEX_op_st8_i32:
+case INDEX_op_st8_i64:
+tcg_out_ldst(s, OPC_SB, a0, a1, a2);
+break;
+case INDEX_op_st16_i32:
+case INDEX_op_st16_i64:
+tcg_out_ldst(s, OPC_SH, a0, a1, a2);
+break;
+case INDEX_op_st_i32:
+case INDEX_op_st32_i64:
+tcg_out_ldst(s, OPC_SW, a0, a1, a2);
+break;
+case INDEX_op_st_i64:
+tcg_out_ldst(s, OPC_SD, a0, a1, a2);
+break;
+
+case INDEX_op_add_i32:
+if (c2) {
+tcg_out_opc_imm(s, is32bit ? OPC_ADDI : OPC_ADDIW, a0, a1, a2);
+} else {
+tcg_out_opc_reg(s, is32bit ? OPC_ADD : OPC_ADDW, a0, a1, a2);
+}
+break;
+case INDEX_op_add_i64:
+if (c2) {
+tcg_out_opc_imm(s, OPC_ADDI, a0, a1, a2);
+} else {
+tcg_out_opc_reg(s, OPC_ADD, a0, a1, a2);
+}
+break;
+
+case INDEX_op_sub_i32:
+if (c2) {
+tcg_out_opc_imm(s, is32bit ? OPC_ADDI : OPC_ADDIW, a0, a1, -a2);
+} else {
+tcg_out_opc_reg(s, is32bit ? OPC_SUB : OPC_SUBW, a0, a1, a2);
+}
+break;
+case INDEX_op_sub_i64:
+if (c2) {
+tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2);
+} else {
+tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2);
+}
+break;
+
+case INDEX_op_and_i32:
+case INDEX_op_and_i64:
+if (c2) {
+tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2);
+} else {
+tcg_out_opc_reg(s, OPC_AND, a0, a1, a2);
+}
+break;
+
+case INDEX_op_or_i32:
+case INDEX_op_or_i64:
+if (c2) {
+tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2);
+} else {
+tcg_out_opc_reg(s, OPC_OR, a0, a1, a2);
+}
+break;
+
+case INDEX_op_xor_i32:
+case INDEX_op_xor_i64:
+if (c2) {
+tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2);
+} else {
+tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2);
+}
+break;
+
+case INDEX_op_not_i32:
+

[Qemu-devel] [RFC v1 05/23] riscv: Add the tcg-target header file

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.h | 173 +
 1 file changed, 173 insertions(+)
 create mode 100644 tcg/riscv/tcg-target.h

diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
new file mode 100644
index 00..53ab485983
--- /dev/null
+++ b/tcg/riscv/tcg-target.h
@@ -0,0 +1,173 @@
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2018 SiFive, Inc
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to 
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef RISCV_TCG_TARGET_H
+#define RISCV_TCG_TARGET_H
+
+#if __riscv_xlen == 32
+# define TCG_TARGET_REG_BITS 32
+#elif __riscv_xlen == 64
+# define TCG_TARGET_REG_BITS 64
+#endif
+
+#define TCG_TARGET_INSN_UNIT_SIZE 4
+#define TCG_TARGET_TLB_DISPLACEMENT_BITS 20
+#define TCG_TARGET_NB_REGS 32
+
+typedef enum {
+TCG_REG_ZERO,
+TCG_REG_RA,
+TCG_REG_SP,
+TCG_REG_GP,
+TCG_REG_TP,
+TCG_REG_T0,
+TCG_REG_T1,
+TCG_REG_T2,
+TCG_REG_S0,
+TCG_REG_S1,
+TCG_REG_A0,
+TCG_REG_A1,
+TCG_REG_A2,
+TCG_REG_A3,
+TCG_REG_A4,
+TCG_REG_A5,
+TCG_REG_A6,
+TCG_REG_A7,
+TCG_REG_S2,
+TCG_REG_S3,
+TCG_REG_S4,
+TCG_REG_S5,
+TCG_REG_S6,
+TCG_REG_S7,
+TCG_REG_S8,
+TCG_REG_S9,
+TCG_REG_S10,
+TCG_REG_S11,
+TCG_REG_T3,
+TCG_REG_T4,
+TCG_REG_T5,
+TCG_REG_T6,
+
+/* aliases */
+TCG_AREG0  = TCG_REG_S0,
+TCG_GUEST_BASE_REG = TCG_REG_S1,
+TCG_REG_TMP0   = TCG_REG_T6,
+TCG_REG_TMP1   = TCG_REG_T5,
+TCG_REG_TMP2   = TCG_REG_T4,
+TCG_REG_L0 = TCG_REG_A6,
+TCG_REG_L1 = TCG_REG_A7,
+} TCGReg;
+
+/* used for function call generation */
+#define TCG_REG_CALL_STACK  TCG_REG_SP
+#define TCG_TARGET_STACK_ALIGN  16
+#define TCG_TARGET_CALL_ALIGN_ARGS  1
+#define TCG_TARGET_CALL_STACK_OFFSET0
+
+/* optional instructions */
+#define TCG_TARGET_HAS_goto_ptr 1
+#define TCG_TARGET_HAS_movcond_i32  0
+#define TCG_TARGET_HAS_div_i32  1
+#define TCG_TARGET_HAS_rem_i32  1
+#define TCG_TARGET_HAS_div2_i32 0
+#define TCG_TARGET_HAS_rot_i32  0
+#define TCG_TARGET_HAS_deposit_i32  0
+#define TCG_TARGET_HAS_extract_i32  0
+#define TCG_TARGET_HAS_sextract_i32 0
+#define TCG_TARGET_HAS_add2_i32 0
+#define TCG_TARGET_HAS_sub2_i32 0
+#define TCG_TARGET_HAS_mulu2_i320
+#define TCG_TARGET_HAS_muls2_i320
+#define TCG_TARGET_HAS_muluh_i32(TCG_TARGET_REG_BITS == 32)
+#define TCG_TARGET_HAS_mulsh_i32(TCG_TARGET_REG_BITS == 32)
+#define TCG_TARGET_HAS_ext8s_i321
+#define TCG_TARGET_HAS_ext16s_i32   1
+#define TCG_TARGET_HAS_ext8u_i321
+#define TCG_TARGET_HAS_ext16u_i32   1
+#define TCG_TARGET_HAS_bswap16_i32  0
+#define TCG_TARGET_HAS_bswap32_i32  0
+#define TCG_TARGET_HAS_not_i32  1
+#define TCG_TARGET_HAS_neg_i32  1
+#define TCG_TARGET_HAS_andc_i32 0
+#define TCG_TARGET_HAS_orc_i32  0
+#define TCG_TARGET_HAS_eqv_i32  0
+#define TCG_TARGET_HAS_nand_i32 0
+#define TCG_TARGET_HAS_nor_i32  0
+#define TCG_TARGET_HAS_clz_i32  0
+#define TCG_TARGET_HAS_ctz_i32  0
+#define TCG_TARGET_HAS_ctpop_i320
+#define TCG_TARGET_HAS_direct_jump  1
+
+#if TCG_TARGET_REG_BITS == 64
+#define TCG_TARGET_HAS_movcond_i64  0
+#define TCG_TARGET_HAS_div_i64  1
+#define TCG_TARGET_HAS_rem_i64  1
+#define TCG_TARGET_HAS_div2_i64 0
+#define TCG_TARGET_HAS_rot_i64  0
+#define TCG_TARGET_HAS_deposit_i64  0
+#define TCG_TARGET_HAS_extract_i64  0
+#define TCG_TARGET_HAS_sextract_i64 0
+#define TCG_TARGET_HAS_extrl_i64_i320
+#define TCG_TARGET_HAS_extrh_i64_i320
+#define TCG_TARGET_HAS_ext8s_i641
+#define TCG_TARGET_HAS_ext16s_i64   1
+#define TCG_TARGET_HAS_ext32s_i64   

[Qemu-devel] [RFC v1 10/23] riscv: tcg-target: Add the instruction emitters

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.inc.c | 40 ++
 1 file changed, 40 insertions(+)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 5319f7ade5..d402e48cbf 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -331,6 +331,46 @@ static int32_t encode_uj(RISCVInsn opc, TCGReg rd, 
uint32_t imm)
 return opc | (rd & 0x1f) << 7 | encode_ujimm12(imm);
 }
 
+/*
+ * RISC-V instruction emitters
+ */
+
+static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc,
+TCGReg rd, TCGReg rs1, TCGReg rs2)
+{
+tcg_out32(s, encode_r(opc, rd, rs1, rs2));
+}
+
+static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc,
+TCGReg rd, TCGReg rs1, TCGArg imm)
+{
+tcg_out32(s, encode_i(opc, rd, rs1, imm));
+}
+
+static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc,
+  TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+tcg_out32(s, encode_s(opc, rs1, rs2, imm));
+}
+
+static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc,
+   TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+tcg_out32(s, encode_sb(opc, rs1, rs2, imm));
+}
+
+static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc,
+  TCGReg rd, uint32_t imm)
+{
+tcg_out32(s, encode_u(opc, rd, imm));
+}
+
+static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc,
+ TCGReg rd, uint32_t imm)
+{
+tcg_out32(s, encode_uj(opc, rd, imm));
+}
+
 void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
   uintptr_t addr)
 {
-- 
2.19.1

[Qemu-devel] [RFC v1 04/23] exec: Add RISC-V GCC poison macro

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 include/exec/poison.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/exec/poison.h b/include/exec/poison.h
index 32d53789f8..ecdc83c147 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -79,6 +79,7 @@
 #pragma GCC poison CONFIG_MOXIE_DIS
 #pragma GCC poison CONFIG_NIOS2_DIS
 #pragma GCC poison CONFIG_PPC_DIS
+#pragma GCC poison CONFIG_RISCV_DIS
 #pragma GCC poison CONFIG_S390_DIS
 #pragma GCC poison CONFIG_SH4_DIS
 #pragma GCC poison CONFIG_SPARC_DIS
-- 
2.19.1

[Qemu-devel] [RFC v1 09/23] riscv: tcg-target: Add the immediate encoders

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.inc.c | 81 ++
 1 file changed, 81 insertions(+)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index e585740870..5319f7ade5 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -258,6 +258,87 @@ typedef enum {
 OPC_FENCE_RW_W = 0x031f,
 } RISCVInsn;
 
+/*
+ * RISC-V immediate and instruction encoders (excludes 16-bit RVC)
+ */
+
+/* Type-R */
+
+static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2)
+{
+return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20;
+}
+
+/* Type-I */
+
+static int32_t encode_imm12(uint32_t imm)
+{
+return (imm & 0xfff) << 20;
+}
+
+static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm)
+{
+return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm);
+}
+
+/* Type-S */
+
+static int32_t encode_simm12(uint32_t imm)
+{
+return ((imm << 20) >> 25) << 25 | ((imm << 27) >> 27) << 7;
+}
+
+static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm);
+}
+
+/* Type-SB */
+
+static int32_t encode_sbimm12(uint32_t imm)
+{
+return ((imm << 19) >> 31) << 31 | ((imm << 21) >> 26) << 25 |
+   ((imm << 27) >> 28) << 8 | ((imm << 20) >> 31) << 7;
+}
+
+static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm)
+{
+return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm);
+}
+
+/* Type-U */
+
+static int32_t encode_uimm20(uint32_t imm)
+{
+return (imm >> 12) << 12;
+}
+
+static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm)
+{
+return opc | (rd & 0x1f) << 7 | encode_uimm20(imm);
+}
+
+/* Type-UJ */
+
+static int32_t encode_ujimm12(uint32_t imm)
+{
+return ((imm << 11) >> 31) << 31 | ((imm << 21) >> 22) << 21 |
+   ((imm << 20) >> 31) << 20 | ((imm << 12) >> 24) << 12;
+}
+
+static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm)
+{
+return opc | (rd & 0x1f) << 7 | encode_ujimm12(imm);
+}
+
+void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
+  uintptr_t addr)
+{
+/* Note: jump target patching should be atomic */
+reloc_call((tcg_insn_unit *)jmp_addr, (tcg_insn_unit*)addr);
+flush_icache_range(jmp_addr, jmp_addr + 8);
+}
+
 typedef struct {
 DebugFrameHeader h;
 uint8_t fde_def_cfa[4];
-- 
2.19.1

[Qemu-devel] [RFC v1 03/23] linux-user: Add host dependency for RISC-V 64-bit

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 linux-user/host/riscv64/hostdep.h | 11 +++
 1 file changed, 11 insertions(+)
 create mode 100644 linux-user/host/riscv64/hostdep.h

diff --git a/linux-user/host/riscv64/hostdep.h 
b/linux-user/host/riscv64/hostdep.h
new file mode 100644
index 00..28467ba00b
--- /dev/null
+++ b/linux-user/host/riscv64/hostdep.h
@@ -0,0 +1,11 @@
+/*
+ * hostdep.h : things which are dependent on the host architecture
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef RISCV64_HOSTDEP_H
+#define RISCV64_HOSTDEP_H
+
+#endif
-- 
2.19.1

[Qemu-devel] [RFC v1 02/23] linux-user: Add host dependency for RISC-V 32-bit

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 linux-user/host/riscv32/hostdep.h | 11 +++
 1 file changed, 11 insertions(+)
 create mode 100644 linux-user/host/riscv32/hostdep.h

diff --git a/linux-user/host/riscv32/hostdep.h 
b/linux-user/host/riscv32/hostdep.h
new file mode 100644
index 00..adf9edbf2d
--- /dev/null
+++ b/linux-user/host/riscv32/hostdep.h
@@ -0,0 +1,11 @@
+/*
+ * hostdep.h : things which are dependent on the host architecture
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef RISCV32_HOSTDEP_H
+#define RISCV32_HOSTDEP_H
+
+#endif
-- 
2.19.1

[Qemu-devel] [RFC v1 07/23] riscv: tcg-target: Regiser the JIT

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 tcg/riscv/tcg-target.inc.c | 45 ++
 1 file changed, 45 insertions(+)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index e5eca4bbbe..a9c57493a0 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -118,3 +118,48 @@ static const int tcg_target_call_oarg_regs[] = {
 #define TCG_CT_CONST_ZERO  0x100
 #define TCG_CT_CONST_S12   0x200
 #define TCG_CT_CONST_N12   0x400
+
+typedef struct {
+DebugFrameHeader h;
+uint8_t fde_def_cfa[4];
+uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
+} DebugFrame;
+
+#define ELF_HOST_MACHINE EM_RISCV
+
+static const DebugFrame debug_frame = {
+.h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
+.h.cie.id = -1,
+.h.cie.version = 1,
+.h.cie.code_align = 1,
+.h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
+.h.cie.return_column = TCG_REG_RA,
+
+/* Total FDE size does not include the "len" member.  */
+.h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
+
+.fde_def_cfa = {
+12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */
+(FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
+(FRAME_SIZE >> 7)
+},
+.fde_reg_ofs = {
+0x80 + 9,  12,  /* DW_CFA_offset, s1,  -96 */
+0x80 + 18, 11,  /* DW_CFA_offset, s2,  -88 */
+0x80 + 19, 10,  /* DW_CFA_offset, s3,  -80 */
+0x80 + 20, 9,   /* DW_CFA_offset, s4,  -72 */
+0x80 + 21, 8,   /* DW_CFA_offset, s5,  -64 */
+0x80 + 22, 7,   /* DW_CFA_offset, s6,  -56 */
+0x80 + 23, 6,   /* DW_CFA_offset, s7,  -48 */
+0x80 + 24, 5,   /* DW_CFA_offset, s8,  -40 */
+0x80 + 25, 4,   /* DW_CFA_offset, s9,  -32 */
+0x80 + 26, 3,   /* DW_CFA_offset, s10, -24 */
+0x80 + 27, 2,   /* DW_CFA_offset, s11, -16 */
+0x80 + 1 , 1,   /* DW_CFA_offset, ra,  -8 */
+}
+};
+
+void tcg_register_jit(void *buf, size_t buf_size)
+{
+tcg_register_jit_int(buf, buf_size, _frame, sizeof(debug_frame));
+}
-- 
2.19.1

[Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support

[Alistair Francis]

This patch set adds RISC-V backend support to QEMU. This is based on
Michael Clark's original work with some patches ontop.

This has been slightly tested and can run other architecture softmmu
code for a number of instructions but eventually QEMU will either
seg fault or generate an illigal instruction (depending on the guest
architecture).

I haven't tested linux user support at all yet. I think Michael had that
working reliably though and hopefully my changes haven't broken it. I'll
test both a lot more before I send a full patchset.

My hope of submitting an RFC is that some extra eyes on the code might
help catch what is wrong. Comparing the guest CPU state to a working
version hasn't given any hints as the states match, even up until the
generated code segfaults.

This branch can be found here:
https://github.com/alistair23/qemu/tree/mainline/alistair/tcg-backend-upstream.next

The working version with Michael's orignal patch and work ontop can be
found here:
https://github.com/alistair23/qemu/tree/mainline/alistair/tcg-backend.next


Alistair Francis (23):
  elf.h: Add the RISCV ELF magic numbers
  linux-user: Add host dependency for RISC-V 32-bit
  linux-user: Add host dependency for RISC-V 64-bit
  exec: Add RISC-V GCC poison macro
  riscv: Add the tcg-target header file
  riscv: Add the tcg target registers
  riscv: tcg-target: Regiser the JIT
  riscv: tcg-target: Add support for the constraints
  riscv: tcg-target: Add the immediate encoders
  riscv: tcg-target: Add the instruction emitters
  riscv: tcg-target: Add the relocation functions
  riscv: tcg-target: Add the mov and movi instruction
  riscv: tcg-target: Add the extract instructions
  riscv: tcg-target: Add the out load and store instructions
  riscv: tcg-target: Add branch and jump instructions
  riscv: tcg-target: Add slowpath load and store instructions
  riscv: tcg-target: Add direct load and store instructions
  riscv: tcg-target: Add the out op decoder
  riscv: tcg-target: Add the prologue generation
  riscv: tcg-target: Add the target init code
  tcg: Add RISC-V cpu signal handler
  dias: Add RISC-V support
  configure: Add support for building RISC-V host

 accel/tcg/user-exec.c |   48 +
 configure |   12 +-
 disas.c   |   10 +-
 include/elf.h |   55 +
 include/exec/poison.h |1 +
 linux-user/host/riscv32/hostdep.h |   11 +
 linux-user/host/riscv64/hostdep.h |   11 +
 tcg/riscv/tcg-target.h|  173 +++
 tcg/riscv/tcg-target.inc.c| 1728 +
 9 files changed, 2045 insertions(+), 4 deletions(-)
 create mode 100644 linux-user/host/riscv32/hostdep.h
 create mode 100644 linux-user/host/riscv64/hostdep.h
 create mode 100644 tcg/riscv/tcg-target.h
 create mode 100644 tcg/riscv/tcg-target.inc.c

-- 
2.19.1

[Qemu-devel] [RFC v1 01/23] elf.h: Add the RISCV ELF magic numbers

[Alistair Francis]

Signed-off-by: Alistair Francis 
Signed-off-by: Michael Clark 
---
 include/elf.h | 55 +++
 1 file changed, 55 insertions(+)

diff --git a/include/elf.h b/include/elf.h
index c151164b63..0ac7911b7b 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -1338,6 +1338,61 @@ typedef struct {
 #define R_IA64_DTPREL64LSB 0xb7/* @dtprel(sym + add), data8 LSB */
 #define R_IA64_LTOFF_DTPREL22  0xba/* @ltoff(@dtprel(s+a)), imm22 */
 
+/* RISC-V relocations.  */
+#define R_RISCV_NONE  0
+#define R_RISCV_321
+#define R_RISCV_642
+#define R_RISCV_RELATIVE  3
+#define R_RISCV_COPY  4
+#define R_RISCV_JUMP_SLOT 5
+#define R_RISCV_TLS_DTPMOD32  6
+#define R_RISCV_TLS_DTPMOD64  7
+#define R_RISCV_TLS_DTPREL32  8
+#define R_RISCV_TLS_DTPREL64  9
+#define R_RISCV_TLS_TPREL32   10
+#define R_RISCV_TLS_TPREL64   11
+#define R_RISCV_BRANCH16
+#define R_RISCV_JAL   17
+#define R_RISCV_CALL  18
+#define R_RISCV_CALL_PLT  19
+#define R_RISCV_GOT_HI20  20
+#define R_RISCV_TLS_GOT_HI20  21
+#define R_RISCV_TLS_GD_HI20   22
+#define R_RISCV_PCREL_HI2023
+#define R_RISCV_PCREL_LO12_I  24
+#define R_RISCV_PCREL_LO12_S  25
+#define R_RISCV_HI20  26
+#define R_RISCV_LO12_I27
+#define R_RISCV_LO12_S28
+#define R_RISCV_TPREL_HI2029
+#define R_RISCV_TPREL_LO12_I  30
+#define R_RISCV_TPREL_LO12_S  31
+#define R_RISCV_TPREL_ADD 32
+#define R_RISCV_ADD8  33
+#define R_RISCV_ADD16 34
+#define R_RISCV_ADD32 35
+#define R_RISCV_ADD64 36
+#define R_RISCV_SUB8  37
+#define R_RISCV_SUB16 38
+#define R_RISCV_SUB32 39
+#define R_RISCV_SUB64 40
+#define R_RISCV_GNU_VTINHERIT 41
+#define R_RISCV_GNU_VTENTRY   42
+#define R_RISCV_ALIGN 43
+#define R_RISCV_RVC_BRANCH44
+#define R_RISCV_RVC_JUMP  45
+#define R_RISCV_RVC_LUI   46
+#define R_RISCV_GPREL_I   47
+#define R_RISCV_GPREL_S   48
+#define R_RISCV_TPREL_I   49
+#define R_RISCV_TPREL_S   50
+#define R_RISCV_RELAX 51
+#define R_RISCV_SUB6  52
+#define R_RISCV_SET6  53
+#define R_RISCV_SET8  54
+#define R_RISCV_SET16 55
+#define R_RISCV_SET32 56
+
 typedef struct elf32_rel {
   Elf32_Addr   r_offset;
   Elf32_Word   r_info;
-- 
2.19.1

Re: [Qemu-devel] [PATCH v2 10/12] i2c: Add a size constant for the smbus_eeprom size

[Philippe Mathieu-Daudé]

On 15/11/18 20:24, miny...@acm.org wrote:

From: Corey Minyard 

It was hard-coded to 256 in a number of places, create a constant
for that.

Signed-off-by: Corey Minyard 
---
  hw/i2c/smbus_eeprom.c | 10 +++---
  1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
index 8d4eed129f..8e9b734c09 100644
--- a/hw/i2c/smbus_eeprom.c
+++ b/hw/i2c/smbus_eeprom.c
@@ -35,6 +35,8 @@
  #define SMBUS_EEPROM(obj) \
  OBJECT_CHECK(SMBusEEPROMDevice, (obj), TYPE_SMBUS_EEPROM)
  
+#define SMBUS_EEPROM_SIZE 256

+
  typedef struct SMBusEEPROMDevice {
  SMBusDevice smbusdev;
  void *data;
@@ -70,7 +72,7 @@ static int eeprom_write_data(SMBusDevice *dev, uint8_t *buf, 
uint8_t len)
  
  for (; len > 0; len--) {

  data[eeprom->offset] = *buf++;
-eeprom->offset = (eeprom->offset + 1) % 256;
+eeprom->offset = (eeprom->offset + 1) % SMBUS_EEPROM_SIZE;
  }
  
  return 0;

@@ -129,12 +131,14 @@ void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,
 const uint8_t *eeprom_spd, int eeprom_spd_size)
  {
  int i;
-uint8_t *eeprom_buf = g_malloc0(8 * 256); /* XXX: make this persistent */
+ /* XXX: make this persistent */
+uint8_t *eeprom_buf = g_malloc0(8 * SMBUS_EEPROM_SIZE);


Ideally this requires a previous patch replacing 8 -> nb_eeprom, fixing 
a long standing bug.


Reviewed-by: Philippe Mathieu-Daudé 


  if (eeprom_spd_size > 0) {
  memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size);
  }
  
  for (i = 0; i < nb_eeprom; i++) {

-smbus_eeprom_init_one(smbus, 0x50 + i, eeprom_buf + (i * 256));
+smbus_eeprom_init_one(smbus, 0x50 + i,
+  eeprom_buf + (i * SMBUS_EEPROM_SIZE));
  }
  }

Re: [Qemu-devel] [Qemu-block] Change in qemu 2.12 causes qemu-img convert to NBD to write more data

[Nir Soffer]

On Sun, Nov 11, 2018 at 6:11 PM Nir Soffer  wrote:

> On Wed, Nov 7, 2018 at 7:55 PM Nir Soffer  wrote:
>
>> On Wed, Nov 7, 2018 at 7:27 PM Kevin Wolf  wrote:
>>
>>> Am 07.11.2018 um 15:56 hat Nir Soffer geschrieben:
>>> > Wed, Nov 7, 2018 at 4:36 PM Richard W.M. Jones 
>>> wrote:
>>> >
>>> > > Another thing I tried was to change the NBD server (nbdkit) so that
>>> it
>>> > > doesn't advertise zero support to the client:
>>> > >
>>> > >   $ nbdkit --filter=log --filter=nozero memory size=6G
>>> logfile=/tmp/log \
>>> > >   --run './qemu-img convert ./fedora-28.img -n $nbd'
>>> > >   $ grep '\.\.\.$' /tmp/log | sed 's/.*\([A-Z][a-z]*\).*/\1/' | uniq
>>> -c
>>> > >2154 Write
>>> > >
>>> > > Not surprisingly no zero commands are issued.  The size of the write
>>> > > commands is very uneven -- it appears to be send one command per
>>> block
>>> > > of zeroes or data.
>>> > >
>>> > > Nir: If we could get information from imageio about whether zeroing
>>> is
>>> > > implemented efficiently or not by the backend, we could change
>>> > > virt-v2v / nbdkit to advertise this back to qemu.
>>> >
>>> > There is no way to detect the capability, ioctl(BLKZEROOUT) always
>>> > succeeds, falling back to manual zeroing in the kernel silently
>>> >
>>> > Even if we could, sending zero on the wire from qemu may be even
>>> > slower, and it looks like qemu send even more requests in this case
>>> > (2154 vs ~1300).
>>> >
>>> > Looks like this optimization in qemu side leads to worse performance,
>>> > so it should not be enabled by default.
>>>
>>> Well, that's overgeneralising your case a bit. If the backend does
>>> support efficient zero writes (which file systems, the most common case,
>>> generally do), doing one big write_zeroes request at the start can
>>> improve performance quite a bit.
>>>
>>> It seems the problem is that we can't really know whether the operation
>>> will be efficient because the backends generally don't tell us. Maybe
>>> NBD could introduce a flag for this, but in the general case it appears
>>> to me that we'll have to have a command line option.
>>>
>>> However, I'm curious what your exact use case and the backend used in it
>>> is? Can something be improved there to actually get efficient zero
>>> writes and get even better performance than by just disabling the big
>>> zero write?
>>
>>
>> The backend is some NetApp storage connected via FC. I don't have
>> more info on this. We get zero rate of about 1G/s on this storage, which
>> is quite slow compared with other storage we tested.
>>
>> One option we check now is if this is the kernel silent fallback to manual
>> zeroing when the server advertise wrong value of write_same_max_bytes.
>>
>
> We eliminated this using blkdiscard. This is what we get on with this
> storage
> zeroing 100G LV:
>
> for i in 1 2 4 8 16 32; do time blkdiscard -z -p ${i}m
> /dev/6e1d84f9-f939-46e9-b108-0427a08c280c/2d5c06ce-6536-4b3c-a7b6-13c6d8e55ade;
> done
>
> real 4m50.851s
> user 0m0.065s
> sys 0m1.482s
>
> real 4m30.504s
> user 0m0.047s
> sys 0m0.870s
>
> real 4m19.443s
> user 0m0.029s
> sys 0m0.508s
>
> real 4m13.016s
> user 0m0.020s
> sys 0m0.284s
>
> real 2m45.888s
> user 0m0.011s
> sys 0m0.162s
>
> real 2m10.153s
> user 0m0.003s
> sys 0m0.100s
>
> We are investigating why we get low throughput on this server, and also
> will check
> several other servers.
>
> Having a command line option to control this behavior sounds good. I don't
>> have enough data to tell what should be the default, but I think the safe
>> way would be to keep old behavior.
>>
>
> We file this bug:
> https://bugzilla.redhat.com/1648622
>

More data from even slower storage - zeroing 10G lv on Kaminario K2

# time blkdiscard -z -p 32m /dev/test_vg/test_lv2

real50m12.425s
user0m0.018s
sys 2m6.785s

Maybe something is wrong with this storage, since we see this:

# grep -s "" /sys/block/dm-29/queue/* | grep write_same_max_bytes
/sys/block/dm-29/queue/write_same_max_bytes:512

Since BLKZEROOUT always fallback to manual slow zeroing silently,
maybe we can disable the aggressive pre-zero of the entire device
for block devices, and keep this optimization for files when fallocate()
is supported?

Nir

Re: [Qemu-devel] [PATCH v2 01/12] i2c: Split smbus into parts

[Philippe Mathieu-Daudé]

On 15/11/18 20:24, miny...@acm.org wrote:

From: Corey Minyard 

smbus.c and smbus.h had device side code, master side code, and
smbus.h has some smbus_eeprom.c definitions.  Split them into
separate files.


Lovely cleanup!



Signed-off-by: Corey Minyard 
---
  hw/arm/aspeed.c   |   2 +-
  hw/i2c/Makefile.objs  |   2 +-
  hw/i2c/pm_smbus.c |   2 +-
  hw/i2c/smbus_eeprom.c |   3 +-
  hw/i2c/smbus_ich9.c   |   2 -
  hw/i2c/smbus_master.c | 165 ++
  hw/i2c/{smbus.c => smbus_slave.c} | 153 +---
  hw/i386/pc_piix.c |   2 +-
  hw/i386/pc_q35.c  |   2 +-
  hw/isa/vt82c686.c |   1 -
  hw/mips/mips_fulong2e.c   |   2 +-
  hw/mips/mips_malta.c  |   2 +-
  hw/ppc/sam460ex.c |   2 +-
  include/hw/i2c/pm_smbus.h |   2 +
  include/hw/i2c/smbus_eeprom.h |  11 ++
  include/hw/i2c/smbus_master.h |  55 
  include/hw/i2c/{smbus.h => smbus_slave.h} |  35 +
  17 files changed, 251 insertions(+), 192 deletions(-)
  create mode 100644 hw/i2c/smbus_master.c
  rename hw/i2c/{smbus.c => smbus_slave.c} (64%)
  create mode 100644 include/hw/i2c/smbus_eeprom.h
  create mode 100644 include/hw/i2c/smbus_master.h
  rename include/hw/i2c/{smbus.h => smbus_slave.h} (65%)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 6b33ecd5aa..69a19df00d 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -18,7 +18,7 @@
  #include "hw/arm/aspeed.h"
  #include "hw/arm/aspeed_soc.h"
  #include "hw/boards.h"
-#include "hw/i2c/smbus.h"
+#include "hw/i2c/smbus_eeprom.h"
  #include "qemu/log.h"
  #include "sysemu/block-backend.h"
  #include "hw/loader.h"
diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs
index 37cacde978..8973edfa22 100644
--- a/hw/i2c/Makefile.objs
+++ b/hw/i2c/Makefile.objs
@@ -1,4 +1,4 @@
-common-obj-$(CONFIG_I2C) += core.o smbus.o smbus_eeprom.o
+common-obj-$(CONFIG_I2C) += core.o smbus_slave.o smbus_master.o smbus_eeprom.o
  common-obj-$(CONFIG_DDC) += i2c-ddc.o
  common-obj-$(CONFIG_VERSATILE_I2C) += versatile_i2c.o
  common-obj-$(CONFIG_ACPI_X86) += smbus_ich9.o
diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c
index 685a2378ed..f3c6cc46f9 100644
--- a/hw/i2c/pm_smbus.c
+++ b/hw/i2c/pm_smbus.c
@@ -20,7 +20,7 @@
  #include "qemu/osdep.h"
  #include "hw/hw.h"
  #include "hw/i2c/pm_smbus.h"
-#include "hw/i2c/smbus.h"
+#include "hw/i2c/smbus_master.h"
  
  #define SMBHSTSTS   0x00

  #define SMBHSTCNT   0x02
diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
index f18aa3de35..d82423aa7e 100644
--- a/hw/i2c/smbus_eeprom.c
+++ b/hw/i2c/smbus_eeprom.c
@@ -25,7 +25,8 @@
  #include "qemu/osdep.h"
  #include "hw/hw.h"
  #include "hw/i2c/i2c.h"
-#include "hw/i2c/smbus.h"
+#include "hw/i2c/smbus_slave.h"
+#include "hw/i2c/smbus_eeprom.h"
  
  //#define DEBUG
  
diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c

index 2a8b49e02f..e6d8d28194 100644
--- a/hw/i2c/smbus_ich9.c
+++ b/hw/i2c/smbus_ich9.c
@@ -29,8 +29,6 @@
  #include "hw/i2c/pm_smbus.h"
  #include "hw/pci/pci.h"
  #include "sysemu/sysemu.h"
-#include "hw/i2c/i2c.h"
-#include "hw/i2c/smbus.h"
  
  #include "hw/i386/ich9.h"
  
diff --git a/hw/i2c/smbus_master.c b/hw/i2c/smbus_master.c

new file mode 100644
index 00..0a6223744c
--- /dev/null
+++ b/hw/i2c/smbus_master.c
@@ -0,0 +1,165 @@
+/*
+ * QEMU SMBus host (master) emulation.
+ *
+ * This code emulates SMBus transactions from the master point of view,
+ * it runs the individual I2C transaction to do the SMBus protocol
+ * over I2C.
+ *
+ * Copyright (c) 2007 CodeSourcery.
+ * Written by Paul Brook
+ *
+ * This code is licensed under the LGPL.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "hw/i2c/i2c.h"
+#include "hw/i2c/smbus_master.h"
+
+/* Master device commands.  */
+int smbus_quick_command(I2CBus *bus, uint8_t addr, int read)
+{
+if (i2c_start_transfer(bus, addr, read)) {
+return -1;
+}
+i2c_end_transfer(bus);
+return 0;
+}
+
+int smbus_receive_byte(I2CBus *bus, uint8_t addr)
+{
+uint8_t data;
+
+if (i2c_start_transfer(bus, addr, 1)) {
+return -1;
+}
+data = i2c_recv(bus);
+i2c_nack(bus);
+i2c_end_transfer(bus);
+return data;
+}
+
+int smbus_send_byte(I2CBus *bus, uint8_t addr, uint8_t data)
+{
+if (i2c_start_transfer(bus, addr, 0)) {
+return -1;
+}
+i2c_send(bus, data);
+i2c_end_transfer(bus);
+return 0;
+}
+
+int smbus_read_byte(I2CBus *bus, uint8_t addr, uint8_t command)
+{
+uint8_t data;
+if (i2c_start_transfer(bus, addr, 0)) {
+return -1;
+}
+i2c_send(bus, command);
+if (i2c_start_transfer(bus, addr, 1)) {
+i2c_end_transfer(bus);
+return -1;
+}
+data = i2c_recv(bus);
+

Re: [Qemu-devel] [PATCH for-4.0 00/17] tcg: Move softmmu out-of-line

[Richard Henderson]

On 11/15/18 7:48 PM, Emilio G. Cota wrote:
> - Segfault in code_gen_buffer. This one I don't have a fix for,
>   but it's *much* easier to reproduce when -tb-size is very small,
>   e.g. "-tb-size 5 -smp 2" (BTW it crashes with x86_64 guests too.)
>   So at first I thought the code cache flushing was the problem,
>   but I don't see how that could be, at least from a TCGContext
>   viewpoint -- I agree that clearing the hash table in
>   tcg_region_assign is a good place to do so.

Ho hum.

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 639f0b2728..115ea186e5 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1831,10 +1831,6 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
 existing_tb = tb_link_page(tb, phys_pc, phys_page2);
 /* if the TB already exists, discard what we just translated */
 if (unlikely(existing_tb != tb)) {
-uintptr_t orig_aligned = (uintptr_t)gen_code_buf;
-
-orig_aligned -= ROUND_UP(sizeof(*tb), qemu_icache_linesize);
-atomic_set(_ctx->code_gen_ptr, (void *)orig_aligned);
 return existing_tb;
 }
 tcg_tb_insert(tb);

We can't easily undo the hash table insert, and for a relatively rare
occurrence it's not worth the effort.


r~

Re: [Qemu-devel] [PATCH v4 2/4] fsdev-throttle-qmp: move struct ThrottleLimits to new file

[Eric Blake]

On 11/15/18 3:41 PM, Eric Blake wrote:

On 11/15/18 2:55 AM, xiezhide wrote:

this patch move ThrottleLimits to new file and rename struct
field with common format


As written, you need s/move/moves/ and s/rename/renames/ to match the 
singular actor 'this patch'.  Or, if you stick with my preference for 
imperative sense, s/this patch move/Move/


s/to new/to a new/



Signed-off-by: xiezhide 
---



+++ b/Makefile
@@ -106,6 +106,7 @@ GENERATED_FILES += qapi/qapi-types-sockets.h 
qapi/qapi-types-sockets.c

  GENERATED_FILES += qapi/qapi-types-tpm.h qapi/qapi-types-tpm.c
  GENERATED_FILES += qapi/qapi-types-trace.h qapi/qapi-types-trace.c
  GENERATED_FILES += qapi/qapi-types-transaction.h 
qapi/qapi-types-transaction.c

+GENERATED_FILES += qapi/qapi-types-tlimits.h qapi/qapi-types-tlimits.c


tlimits comes before tpm, not after transaction.  (Multiple times in 
this file)


Or, just apply your patch after mine[1], for a much simpler task of 
inserting 'tlimits' in the right place within QAPI_MODULES.


[1] https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg03070.html

--
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

[Qemu-devel] [PATCH 1/2] usb-mtp: Reallocate buffer in multiples of MTP_WRITE_BUF_SZ

[Bandan Das]

This is a "pre-patch" to breaking up the write buffer for
MTP writes. Instead of allocating a mtp buffer equal to size
sent by the initiator, we start with a small size and reallocate
multiples (of that small size) as needed.

Signed-off-by: Bandan Das 
---
 hw/usb/dev-mtp.c | 26 --
 1 file changed, 12 insertions(+), 14 deletions(-)

diff --git a/hw/usb/dev-mtp.c b/hw/usb/dev-mtp.c
index 00a3691bae..de941d649c 100644
--- a/hw/usb/dev-mtp.c
+++ b/hw/usb/dev-mtp.c
@@ -152,7 +152,6 @@ struct MTPData {
 bool first;
 /* Used for >4G file sizes */
 bool pending;
-uint64_t cached_length;
 int  fd;
 };
 
@@ -244,6 +243,7 @@ typedef struct {
 
 #define MTP_MANUFACTURER  "QEMU"
 #define MTP_PRODUCT   "QEMU filesharing"
+#define MTP_WRITE_BUF_SZ  512000
 
 enum {
 STR_MANUFACTURER = 1,
@@ -1647,7 +1647,7 @@ static void usb_mtp_write_data(MTPState *s)
 d->fd = mkdir(path, mask);
 goto free;
 }
-if ((s->dataset.size != 0x) && (s->dataset.size < d->length)) {
+if ((s->dataset.size != 0x) && (s->dataset.size != d->offset)) 
{
 usb_mtp_queue_result(s, RES_STORE_FULL, d->trans,
  0, 0, 0, 0);
 goto done;
@@ -1757,17 +1757,21 @@ static void usb_mtp_get_data(MTPState *s, mtp_container 
*container,
 total_len = cpu_to_le32(container->length) - sizeof(mtp_container);
 /* Length of data in this packet */
 data_len -= sizeof(mtp_container);
-usb_mtp_realloc(d, total_len);
-d->length += total_len;
+if (total_len < MTP_WRITE_BUF_SZ) {
+usb_mtp_realloc(d, total_len);
+d->length += total_len;
+} else {
+usb_mtp_realloc(d, MTP_WRITE_BUF_SZ - sizeof(mtp_container));
+d->length += MTP_WRITE_BUF_SZ - sizeof(mtp_container);
+}
 d->offset = 0;
-d->cached_length = total_len;
 d->first = false;
 d->pending = false;
 }
 
 if (d->pending) {
-usb_mtp_realloc(d, d->cached_length);
-d->length += d->cached_length;
+usb_mtp_realloc(d, MTP_WRITE_BUF_SZ);
+d->length += MTP_WRITE_BUF_SZ;
 d->pending = false;
 }
 
@@ -1775,12 +1779,6 @@ static void usb_mtp_get_data(MTPState *s, mtp_container 
*container,
 dlen = data_len;
 } else {
 dlen = d->length - d->offset;
-/* Check for cached data for large files */
-if ((s->dataset.size == 0x) && (dlen < p->iov.size)) {
-usb_mtp_realloc(d, p->iov.size - dlen);
-d->length += p->iov.size - dlen;
-dlen = p->iov.size;
-}
 }
 
 switch (d->code) {
@@ -1802,7 +1800,7 @@ static void usb_mtp_get_data(MTPState *s, mtp_container 
*container,
 d->offset += dlen;
 if ((p->iov.size % 64) || !p->iov.size) {
 assert((s->dataset.size == 0x) ||
-   (s->dataset.size == d->length));
+   (s->dataset.size == d->offset));
 
 usb_mtp_write_data(s);
 usb_mtp_data_free(s->data_out);
-- 
2.14.4

[Qemu-devel] [PATCH 2/2] usb-mtp: breakup MTP write into smaller chunks

[Bandan Das]

For every MTP_WRITE_BUF_SZ copied, this patch writes it to file before
getting the next block of data. The file is kept opened for the
duration of the operation but the sanity checks on the write operation
are performed only once when the write operation starts. Additionally,
we also update the file size in the object metadata once the file has
completely been written.

Suggested-by: Gerd Hoffman 
Signed-off-by: Bandan Das 
---
 hw/usb/dev-mtp.c | 133 +--
 1 file changed, 90 insertions(+), 43 deletions(-)

diff --git a/hw/usb/dev-mtp.c b/hw/usb/dev-mtp.c
index de941d649c..fce6029df0 100644
--- a/hw/usb/dev-mtp.c
+++ b/hw/usb/dev-mtp.c
@@ -35,6 +35,13 @@ enum mtp_container_type {
 TYPE_EVENT= 4,
 };
 
+/* MTP write stage, for internal use only */
+enum mtp_write_status {
+WRITE_START= 1,
+WRITE_CONTINUE = 2,
+WRITE_END  = 3,
+};
+
 enum mtp_code {
 /* command codes */
 CMD_GET_DEVICE_INFO= 0x1001,
@@ -153,6 +160,9 @@ struct MTPData {
 /* Used for >4G file sizes */
 bool pending;
 int  fd;
+uint8_t  write_status;
+/* Internal pointer per every MTP_WRITE_BUF_SZ */
+uint64_t data_offset;
 };
 
 struct MTPObject {
@@ -1607,10 +1617,14 @@ static void utf16_to_str(uint8_t len, uint16_t *arr, 
char *name)
 }
 
 /* Wrapper around write, returns 0 on failure */
-static uint64_t write_retry(int fd, void *buf, uint64_t size)
+static uint64_t write_retry(int fd, void *buf, uint64_t size, off_t offset)
 {
 uint64_t bytes_left = size, ret;
 
+if (lseek(fd, offset, SEEK_SET) < 0) {
+goto done;
+}
+
 while (bytes_left > 0) {
 ret = write(fd, buf, bytes_left);
 if ((ret == -1) && (errno != EINTR || errno != EAGAIN ||
@@ -1621,9 +1635,20 @@ static uint64_t write_retry(int fd, void *buf, uint64_t 
size)
 buf += ret;
 }
 
+done:
 return size - bytes_left;
 }
 
+static void usb_mtp_update_object(MTPObject *parent, char *name)
+{
+MTPObject *o =
+usb_mtp_object_lookup_name(parent, name, strlen(name));
+
+if (o) {
+lstat(o->path, >stat);
+}
+}
+
 static void usb_mtp_write_data(MTPState *s)
 {
 MTPData *d = s->data_out;
@@ -1635,48 +1660,55 @@ static void usb_mtp_write_data(MTPState *s)
 
 assert(d != NULL);
 
-if (parent == NULL || !s->write_pending) {
-usb_mtp_queue_result(s, RES_INVALID_OBJECTINFO, d->trans,
- 0, 0, 0, 0);
+switch (d->write_status) {
+case WRITE_START:
+if (!parent || !s->write_pending) {
+usb_mtp_queue_result(s, RES_INVALID_OBJECTINFO, d->trans,
+0, 0, 0, 0);
 return;
-}
-
-if (s->dataset.filename) {
-path = g_strdup_printf("%s/%s", parent->path, s->dataset.filename);
-if (s->dataset.format == FMT_ASSOCIATION) {
-d->fd = mkdir(path, mask);
-goto free;
-}
-if ((s->dataset.size != 0x) && (s->dataset.size != d->offset)) 
{
-usb_mtp_queue_result(s, RES_STORE_FULL, d->trans,
- 0, 0, 0, 0);
-goto done;
-}
-d->fd = open(path, O_CREAT | O_WRONLY, mask);
-if (d->fd == -1) {
-usb_mtp_queue_result(s, RES_STORE_FULL, d->trans,
- 0, 0, 0, 0);
-goto done;
 }
 
-/*
- * Return success if initiator sent 0 sized data
- */
-if (!s->dataset.size) {
-goto success;
-}
+if (s->dataset.filename) {
+path = g_strdup_printf("%s/%s", parent->path, s->dataset.filename);
+if (s->dataset.format == FMT_ASSOCIATION) {
+d->fd = mkdir(path, mask);
+goto free;
+}
+d->fd = open(path, O_CREAT | O_WRONLY, mask);
+if (d->fd == -1) {
+usb_mtp_queue_result(s, RES_STORE_FULL, d->trans,
+ 0, 0, 0, 0);
+goto done;
+}
 
-rc = write_retry(d->fd, d->data, d->offset);
-if (rc != d->offset) {
+/* Return success if initiator sent 0 sized data */
+if (!s->dataset.size) {
+goto success;
+}
+if (d->length != MTP_WRITE_BUF_SZ && !d->pending) {
+d->write_status = WRITE_END;
+}
+}
+/* fall through */
+case WRITE_CONTINUE:
+case WRITE_END:
+rc = write_retry(d->fd, d->data, d->data_offset,
+ d->offset - d->data_offset);
+if (rc != d->data_offset) {
 usb_mtp_queue_result(s, RES_STORE_FULL, d->trans,
  0, 0, 0, 0);
 goto done;
+}
+if (d->write_status != WRITE_END) {
+return;
+} else {
+ 

[Qemu-devel] [PATCH 0/2] Break down the MTP write operation

[Bandan Das]

For larger files, not only do we keep reallocating to increase the mtp buffer
size, the write also happens in one go. This does two things:

Write to file upto a certain data size we have received so far and second,
reuse the buffer again instead of reallocating to a larger buffer size.

Tested with different file sizes on a Linux guest.

Bandan Das (2):
  usb-mtp: Reallocate buffer in multiples of MTP_WRITE_BUF_SZ
  usb-mtp: breakup MTP write into smaller chunks

 hw/usb/dev-mtp.c | 153 +++
 1 file changed, 99 insertions(+), 54 deletions(-)

-- 
2.14.4

Re: [Qemu-devel] [PATCH v1 1/9] cutils: add qemu_strtod() and qemu_strtod_finite()

[David Hildenbrand]

On 15.11.18 19:02, Eric Blake wrote:
> If the conversion underflows, store ±0.0 in @result, depending on the 
> sign, and return -ERANGE.

Will do! Thanks!

-- 

Thanks,

David / dhildenb

[Qemu-devel] [PATCH] qapi: Reduce Makefile boilerplate

[Eric Blake]

Adding a new qapi module had some rather tedious repetition to
wire it into Makefile. Add some indirection by taking advantage
of GNU Make string processing to expand a list of module names
into all the required artifacts, so that future additions of a
new module need only touch the list of module names.

Signed-off-by: Eric Blake 
---

I finally found time to follow through with my threats to make it
MUCH easier to add a new qapi/FOO.json file.

Should be no semantic change, but as it is not fixing an actual
bug, I don't care if it goes in 3.1 or 4.0.

 Makefile | 194 +++
 1 file changed, 25 insertions(+), 169 deletions(-)

diff --git a/Makefile b/Makefile
index f2947186a4c..e343722c71d 100644
--- a/Makefile
+++ b/Makefile
@@ -88,82 +88,28 @@ endif
 include $(SRC_PATH)/rules.mak

 GENERATED_FILES = qemu-version.h config-host.h qemu-options.def
-GENERATED_FILES += qapi/qapi-builtin-types.h qapi/qapi-builtin-types.c
-GENERATED_FILES += qapi/qapi-types.h qapi/qapi-types.c
-GENERATED_FILES += qapi/qapi-types-block-core.h qapi/qapi-types-block-core.c
-GENERATED_FILES += qapi/qapi-types-block.h qapi/qapi-types-block.c
-GENERATED_FILES += qapi/qapi-types-char.h qapi/qapi-types-char.c
-GENERATED_FILES += qapi/qapi-types-common.h qapi/qapi-types-common.c
-GENERATED_FILES += qapi/qapi-types-crypto.h qapi/qapi-types-crypto.c
-GENERATED_FILES += qapi/qapi-types-introspect.h qapi/qapi-types-introspect.c
-GENERATED_FILES += qapi/qapi-types-job.h qapi/qapi-types-job.c
-GENERATED_FILES += qapi/qapi-types-migration.h qapi/qapi-types-migration.c
-GENERATED_FILES += qapi/qapi-types-misc.h qapi/qapi-types-misc.c
-GENERATED_FILES += qapi/qapi-types-net.h qapi/qapi-types-net.c
-GENERATED_FILES += qapi/qapi-types-rocker.h qapi/qapi-types-rocker.c
-GENERATED_FILES += qapi/qapi-types-run-state.h qapi/qapi-types-run-state.c
-GENERATED_FILES += qapi/qapi-types-sockets.h qapi/qapi-types-sockets.c
-GENERATED_FILES += qapi/qapi-types-tpm.h qapi/qapi-types-tpm.c
-GENERATED_FILES += qapi/qapi-types-trace.h qapi/qapi-types-trace.c
-GENERATED_FILES += qapi/qapi-types-transaction.h qapi/qapi-types-transaction.c
-GENERATED_FILES += qapi/qapi-types-ui.h qapi/qapi-types-ui.c
-GENERATED_FILES += qapi/qapi-builtin-visit.h qapi/qapi-builtin-visit.c
-GENERATED_FILES += qapi/qapi-visit.h qapi/qapi-visit.c
-GENERATED_FILES += qapi/qapi-visit-block-core.h qapi/qapi-visit-block-core.c
-GENERATED_FILES += qapi/qapi-visit-block.h qapi/qapi-visit-block.c
-GENERATED_FILES += qapi/qapi-visit-char.h qapi/qapi-visit-char.c
-GENERATED_FILES += qapi/qapi-visit-common.h qapi/qapi-visit-common.c
-GENERATED_FILES += qapi/qapi-visit-crypto.h qapi/qapi-visit-crypto.c
-GENERATED_FILES += qapi/qapi-visit-introspect.h qapi/qapi-visit-introspect.c
-GENERATED_FILES += qapi/qapi-visit-job.h qapi/qapi-visit-job.c
-GENERATED_FILES += qapi/qapi-visit-migration.h qapi/qapi-visit-migration.c
-GENERATED_FILES += qapi/qapi-visit-misc.h qapi/qapi-visit-misc.c
-GENERATED_FILES += qapi/qapi-visit-net.h qapi/qapi-visit-net.c
-GENERATED_FILES += qapi/qapi-visit-rocker.h qapi/qapi-visit-rocker.c
-GENERATED_FILES += qapi/qapi-visit-run-state.h qapi/qapi-visit-run-state.c
-GENERATED_FILES += qapi/qapi-visit-sockets.h qapi/qapi-visit-sockets.c
-GENERATED_FILES += qapi/qapi-visit-tpm.h qapi/qapi-visit-tpm.c
-GENERATED_FILES += qapi/qapi-visit-trace.h qapi/qapi-visit-trace.c
-GENERATED_FILES += qapi/qapi-visit-transaction.h qapi/qapi-visit-transaction.c
-GENERATED_FILES += qapi/qapi-visit-ui.h qapi/qapi-visit-ui.c
-GENERATED_FILES += qapi/qapi-commands.h qapi/qapi-commands.c
-GENERATED_FILES += qapi/qapi-commands-block-core.h 
qapi/qapi-commands-block-core.c
-GENERATED_FILES += qapi/qapi-commands-block.h qapi/qapi-commands-block.c
-GENERATED_FILES += qapi/qapi-commands-char.h qapi/qapi-commands-char.c
-GENERATED_FILES += qapi/qapi-commands-common.h qapi/qapi-commands-common.c
-GENERATED_FILES += qapi/qapi-commands-crypto.h qapi/qapi-commands-crypto.c
-GENERATED_FILES += qapi/qapi-commands-introspect.h 
qapi/qapi-commands-introspect.c
-GENERATED_FILES += qapi/qapi-commands-job.h qapi/qapi-commands-job.c
-GENERATED_FILES += qapi/qapi-commands-migration.h 
qapi/qapi-commands-migration.c
-GENERATED_FILES += qapi/qapi-commands-misc.h qapi/qapi-commands-misc.c
-GENERATED_FILES += qapi/qapi-commands-net.h qapi/qapi-commands-net.c
-GENERATED_FILES += qapi/qapi-commands-rocker.h qapi/qapi-commands-rocker.c
-GENERATED_FILES += qapi/qapi-commands-run-state.h 
qapi/qapi-commands-run-state.c
-GENERATED_FILES += qapi/qapi-commands-sockets.h qapi/qapi-commands-sockets.c
-GENERATED_FILES += qapi/qapi-commands-tpm.h qapi/qapi-commands-tpm.c
-GENERATED_FILES += qapi/qapi-commands-trace.h qapi/qapi-commands-trace.c
-GENERATED_FILES += qapi/qapi-commands-transaction.h 
qapi/qapi-commands-transaction.c
-GENERATED_FILES += qapi/qapi-commands-ui.h qapi/qapi-commands-ui.c
-GENERATED_FILES += qapi/qapi-events.h qapi/qapi-events.c
-GENERATED_FILES += 

Re: [Qemu-devel] [PATCH v1 3/9] qapi: use qemu_strtod_finite() in string-input-visitor

[David Hildenbrand]

On 15.11.18 17:48, Markus Armbruster wrote:
> David Hildenbrand  writes:
> 
>> Let's use the new function. "NaN" and "inf" are now properly rejected.
>>
>> Signed-off-by: David Hildenbrand 
> 
> Whether this is a bug fix or just a change is debatable.  But the commit
> message's title should highlight the change.  Perhaps you want to steal
> from the one I suggested for the previous patch.

Yes, will copy+modify that one.

> 
> We need to assess backward compatibility impact.  I can do that.
Thanks! I assume this shouldn't be an issue.

-- 

Thanks,

David / dhildenb

Re: [Qemu-devel] [PATCH v4 2/4] fsdev-throttle-qmp: move struct ThrottleLimits to new file

[Eric Blake]

On 11/15/18 2:55 AM, xiezhide wrote:

this patch move ThrottleLimits to new file and rename struct
field with common format


As written, you need s/move/moves/ and s/rename/renames/ to match the 
singular actor 'this patch'.  Or, if you stick with my preference for 
imperative sense, s/this patch move/Move/


s/to new/to a new/



Signed-off-by: xiezhide 
---



+++ b/Makefile
@@ -106,6 +106,7 @@ GENERATED_FILES += qapi/qapi-types-sockets.h 
qapi/qapi-types-sockets.c
  GENERATED_FILES += qapi/qapi-types-tpm.h qapi/qapi-types-tpm.c
  GENERATED_FILES += qapi/qapi-types-trace.h qapi/qapi-types-trace.c
  GENERATED_FILES += qapi/qapi-types-transaction.h qapi/qapi-types-transaction.c
+GENERATED_FILES += qapi/qapi-types-tlimits.h qapi/qapi-types-tlimits.c


tlimits comes before tpm, not after transaction.  (Multiple times in 
this file)



+++ b/Makefile.objs
@@ -20,6 +20,7 @@ util-obj-y += qapi/qapi-types-sockets.o
  util-obj-y += qapi/qapi-types-tpm.o
  util-obj-y += qapi/qapi-types-trace.o
  util-obj-y += qapi/qapi-types-transaction.o
+util-obj-y += qapi/qapi-types-tlimits.o


Here too.



  { 'struct': 'BlockIOThrottle',
-  'data': { '*device': 'str', '*id': 'str', 'bps': 'int', 'bps_rd': 'int',
-'bps_wr': 'int', 'iops': 'int', 'iops_rd': 'int', 'iops_wr': 'int',
-'*bps_max': 'int', '*bps_rd_max': 'int',
-'*bps_wr_max': 'int', '*iops_max': 'int',
-'*iops_rd_max': 'int', '*iops_wr_max': 'int',
-'*bps_max_length': 'int', '*bps_rd_max_length': 'int',
-'*bps_wr_max_length': 'int', '*iops_max_length': 'int',
-'*iops_rd_max_length': 'int', '*iops_wr_max_length': 'int',
-'*iops_size': 'int', '*group': 'str' } }
-



-{ 'struct': 'ThrottleLimits',
-  'data': { '*iops-total' : 'int', '*iops-total-max' : 'int',
-'*iops-total-max-length' : 'int', '*iops-read' : 'int',
-'*iops-read-max' : 'int', '*iops-read-max-length' : 'int',
-'*iops-write' : 'int', '*iops-write-max' : 'int',
-'*iops-write-max-length' : 'int', '*bps-total' : 'int',
-'*bps-total-max' : 'int', '*bps-total-max-length' : 'int',
-'*bps-read' : 'int', '*bps-read-max' : 'int',
-'*bps-read-max-length' : 'int', '*bps-write' : 'int',
-'*bps-write-max' : 'int', '*bps-write-max-length' : 'int',
-'*iops-size' : 'int' } }
+  'base': 'ThrottleLimits',
+  'data': { '*device': 'str', '*id': 'str', '*group': 'str' } }


The old code has QMP using 'bps_wr' for BlockIOThrottle, but 'bps-write' 
for ThrottleLimits. The new code...



+++ b/qapi/tlimits.json



+{ 'struct': 'ThrottleLimits',
+  'data': { '*bps': 'int', '*bps_rd': 'int',
+'*bps_wr': 'int', '*iops': 'int', '*iops_rd': 'int', '*iops_wr': 
'int',
+'*bps_max': 'int', '*bps_rd_max': 'int',
+'*bps_wr_max': 'int', '*iops_max': 'int',
+'*iops_rd_max': 'int', '*iops_wr_max': 'int',
+'*bps_max_length': 'int', '*bps_rd_max_length': 'int',
+'*bps_wr_max_length': 'int', '*iops_max_length': 'int',
+'*iops_rd_max_length': 'int', '*iops_wr_max_length': 'int',
+'*iops_size': 'int' } }


...is sticking with the BlockIOThrottle naming.  I don't see any use of 
ThrottleLimits in QAPI code (quick check: grep bps-wr 
qapi/qapi-introspect.c comes up empty), so we SHOULD be okay with 
regards to back-compat.  But I'd still split this patch into multiple 
pieces: 1. Rename the ThrottleLimits member names (and give 
justification why such rename doesn't break back-compat). 2. Rewrite 
BlockIOThrottle with ThrottleLimits as its base class. 3. Move 
ThrottleLimits into a new file for future reuse.  (Maybe 2 and 3 can be 
squashed into a single patch)



diff --git a/util/throttle.c b/util/throttle.c
index e7db2ad..b421e33 100644
--- a/util/throttle.c
+++ b/util/throttle.c
@@ -496,98 +496,97 @@ void throttle_account(ThrottleState *ts, bool is_write, 
uint64_t size)
  void throttle_limits_to_config(ThrottleLimits *arg, ThrottleConfig *cfg,
 Error **errp)
  {
-if (arg->has_bps_total) {
-cfg->buckets[THROTTLE_BPS_TOTAL].avg = arg->bps_total;
+if (arg->has_bps) {
+cfg->buckets[THROTTLE_BPS_TOTAL].avg = arg->bps;


Otherwise, the churn from renaming members (part 1) makes it hard to see 
if the code was properly moved into a new file.


--
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

Re: [Qemu-devel] [PATCH 0/2] typedefs.h cleanup

[Philippe Mathieu-Daudé]

On 15/11/18 22:17, Eric Blake wrote:

Prompted by my review of xiezhide's work.  No semantic change, but
not technically a bug fix, so I don't care if it goes in 3.1 or
waits for 4.0.

Eric Blake (2):
   typedefs: (Re-)sort entries alphabetically
   numa: Match struct to typedef name


Series:
Reviewed-by: Philippe Mathieu-Daudé 

[Qemu-devel] [PATCH 1/2] typedefs: (Re-)sort entries alphabetically

[Eric Blake]

Since the last time we sorted things (2988cbeaf), we've had a
few relapses that were inserted out of order.  Also, we had more
entries that were sorted case-insensitively than not, so let's
document that convention and stick to it.

Signed-off-by: Eric Blake 
---
 include/qemu/typedefs.h | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index 3ec0e13a967..45eab4078eb 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -4,7 +4,7 @@
 /* A load of opaque types so that device init declarations don't have to
pull in all the real definitions.  */

-/* Please keep this list in alphabetical order */
+/* Please keep this list in case-insensitive alphabetical order */
 typedef struct AdapterInfo AdapterInfo;
 typedef struct AddressSpace AddressSpace;
 typedef struct AioContext AioContext;
@@ -40,6 +40,7 @@ typedef struct HCIInfo HCIInfo;
 typedef struct HVFX86EmulatorState HVFX86EmulatorState;
 typedef struct I2CBus I2CBus;
 typedef struct I2SCodec I2SCodec;
+typedef struct IOMMUMemoryRegion IOMMUMemoryRegion;
 typedef struct ISABus ISABus;
 typedef struct ISADevice ISADevice;
 typedef struct IsaDma IsaDma;
@@ -49,7 +50,6 @@ typedef struct MachineState MachineState;
 typedef struct MemoryListener MemoryListener;
 typedef struct MemoryMappingList MemoryMappingList;
 typedef struct MemoryRegion MemoryRegion;
-typedef struct IOMMUMemoryRegion IOMMUMemoryRegion;
 typedef struct MemoryRegionCache MemoryRegionCache;
 typedef struct MemoryRegionSection MemoryRegionSection;
 typedef struct MigrationIncomingState MigrationIncomingState;
@@ -82,6 +82,8 @@ typedef struct PostcopyDiscardState PostcopyDiscardState;
 typedef struct Property Property;
 typedef struct PropertyInfo PropertyInfo;
 typedef struct PS2State PS2State;
+typedef struct QBool QBool;
+typedef struct QDict QDict;
 typedef struct QEMUBH QEMUBH;
 typedef struct QemuConsole QemuConsole;
 typedef struct QemuDmaBuf QemuDmaBuf;
@@ -91,12 +93,10 @@ typedef struct QemuMutex QemuMutex;
 typedef struct QemuOpt QemuOpt;
 typedef struct QemuOpts QemuOpts;
 typedef struct QemuOptsList QemuOptsList;
-typedef struct QemuSpin QemuSpin;
 typedef struct QEMUSGList QEMUSGList;
+typedef struct QemuSpin QemuSpin;
 typedef struct QEMUTimer QEMUTimer;
 typedef struct QEMUTimerListGroup QEMUTimerListGroup;
-typedef struct QBool QBool;
-typedef struct QDict QDict;
 typedef struct QJSON QJSON;
 typedef struct QList QList;
 typedef struct QNull QNull;
-- 
2.17.2

[Qemu-devel] [PATCH 2/2] numa: Match struct to typedef name

[Eric Blake]

There's no reason to violate our naming conventions by having a
struct with a different name than its typedef.  Messed up since
its introduction in commit 8c85901e, but made more obvious when
commit 3bfe5716 promoted it to typedefs.h.

Signed-off-by: Eric Blake 
---
 include/qemu/typedefs.h | 2 +-
 include/sysemu/numa.h   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
index 45eab4078eb..a9cfe1b2c2e 100644
--- a/include/qemu/typedefs.h
+++ b/include/qemu/typedefs.h
@@ -61,6 +61,7 @@ typedef struct MSIMessage MSIMessage;
 typedef struct NetClientState NetClientState;
 typedef struct NetFilterState NetFilterState;
 typedef struct NICInfo NICInfo;
+typedef struct NodeInfo NodeInfo;
 typedef struct NumaNodeMem NumaNodeMem;
 typedef struct PCIBridge PCIBridge;
 typedef struct PCIBus PCIBus;
@@ -112,7 +113,6 @@ typedef struct SSIBus SSIBus;
 typedef struct uWireSlave uWireSlave;
 typedef struct VirtIODevice VirtIODevice;
 typedef struct Visitor Visitor;
-typedef struct node_info NodeInfo;
 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);

diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
index 21713b7e2f6..b6ac7de43ed 100644
--- a/include/sysemu/numa.h
+++ b/include/sysemu/numa.h
@@ -9,7 +9,7 @@
 extern int nb_numa_nodes;   /* Number of NUMA nodes */
 extern bool have_numa_distance;

-struct node_info {
+struct NodeInfo {
 uint64_t node_mem;
 struct HostMemoryBackend *node_memdev;
 bool present;
-- 
2.17.2

[Qemu-devel] [PATCH 0/2] typedefs.h cleanup

[Eric Blake]

Prompted by my review of xiezhide's work.  No semantic change, but
not technically a bug fix, so I don't care if it goes in 3.1 or
waits for 4.0.

Eric Blake (2):
  typedefs: (Re-)sort entries alphabetically
  numa: Match struct to typedef name

 include/qemu/typedefs.h | 12 ++--
 include/sysemu/numa.h   |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

-- 
2.17.2

Re: [Qemu-devel] [PATCH 0/4] keymaps: drop support for include files

[no-reply]

Hi,

This series failed docker-quick@centos7 build test. Please find the testing 
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

Message-id: 20181115123218.25387-1-kra...@redhat.com
Type: series
Subject: [Qemu-devel] [PATCH 0/4] keymaps: drop support for include files

=== TEST SCRIPT BEGIN ===
#!/bin/bash
time make docker-test-quick@centos7 SHOW_ENV=1 J=8
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
ed5fa6b keymaps: drop support for include files
96f504b keymaps: remove common include
b2833f8 keymaps: drop nl-be map
73dd69e keymaps: remove modifiers include

=== OUTPUT BEGIN ===
  BUILD   centos7
make[1]: Entering directory `/var/tmp/patchew-tester-tmp-d6ntaqin/src'
  GEN 
/var/tmp/patchew-tester-tmp-d6ntaqin/src/docker-src.2018-11-15-15.50.49.15293/qemu.tar
Cloning into 
'/var/tmp/patchew-tester-tmp-d6ntaqin/src/docker-src.2018-11-15-15.50.49.15293/qemu.tar.vroot'...
done.
Checking out files:  45% (2948/6452)   
Checking out files:  46% (2968/6452)   
Checking out files:  47% (3033/6452)   
Checking out files:  48% (3097/6452)   
Checking out files:  49% (3162/6452)   
Checking out files:  50% (3226/6452)   
Checking out files:  51% (3291/6452)   
Checking out files:  52% (3356/6452)   
Checking out files:  53% (3420/6452)   
Checking out files:  54% (3485/6452)   
Checking out files:  55% (3549/6452)   
Checking out files:  56% (3614/6452)   
Checking out files:  57% (3678/6452)   
Checking out files:  58% (3743/6452)   
Checking out files:  59% (3807/6452)   
Checking out files:  60% (3872/6452)   
Checking out files:  61% (3936/6452)   
Checking out files:  62% (4001/6452)   
Checking out files:  63% (4065/6452)   
Checking out files:  64% (4130/6452)   
Checking out files:  65% (4194/6452)   
Checking out files:  66% (4259/6452)   
Checking out files:  67% (4323/6452)   
Checking out files:  68% (4388/6452)   
Checking out files:  69% (4452/6452)   
Checking out files:  70% (4517/6452)   
Checking out files:  71% (4581/6452)   
Checking out files:  72% (4646/6452)   
Checking out files:  73% (4710/6452)   
Checking out files:  74% (4775/6452)   
Checking out files:  75% (4839/6452)   
Checking out files:  76% (4904/6452)   
Checking out files:  77% (4969/6452)   
Checking out files:  78% (5033/6452)   
Checking out files:  79% (5098/6452)   
Checking out files:  80% (5162/6452)   
Checking out files:  81% (5227/6452)   
Checking out files:  82% (5291/6452)   
Checking out files:  83% (5356/6452)   
Checking out files:  84% (5420/6452)   
Checking out files:  85% (5485/6452)   
Checking out files:  86% (5549/6452)   
Checking out files:  87% (5614/6452)   
Checking out files:  88% (5678/6452)   
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Checking out files:  90% (5807/6452)   
Checking out files:  91% (5872/6452)   
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Checking out files:  95% (6130/6452)   
Checking out files:  96% (6194/6452)   
Checking out files:  97% (6259/6452)   
Checking out files:  98% (6323/6452)   
Checking out files:  99% (6388/6452)   
Checking out files: 100% (6452/6452)   
Checking out files: 100% (6452/6452), done.
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) 
registered for path 'ui/keycodemapdb'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out 
'6b3d716e2b6472eb7189d3220552280ef3d832ce'
  COPYRUNNER
RUN test-quick in qemu:centos7 
Packages installed:
SDL-devel-1.2.15-14.el7.x86_64
bison-3.0.4-1.el7.x86_64
bzip2-1.0.6-13.el7.x86_64
bzip2-devel-1.0.6-13.el7.x86_64
ccache-3.3.4-1.el7.x86_64
csnappy-devel-0-6.20150729gitd7bc683.el7.x86_64
flex-2.5.37-3.el7.x86_64
gcc-4.8.5-28.el7_5.1.x86_64
gettext-0.19.8.1-2.el7.x86_64
git-1.8.3.1-14.el7_5.x86_64
glib2-devel-2.54.2-2.el7.x86_64
libaio-devel-0.3.109-13.el7.x86_64
libepoxy-devel-1.3.1-2.el7_5.x86_64
libfdt-devel-1.4.6-1.el7.x86_64
lzo-devel-2.06-8.el7.x86_64
make-3.82-23.el7.x86_64
mesa-libEGL-devel-17.2.3-8.20171019.el7.x86_64
mesa-libgbm-devel-17.2.3-8.20171019.el7.x86_64
nettle-devel-2.7.1-8.el7.x86_64
package g++ is not installed
package librdmacm-devel is not installed
pixman-devel-0.34.0-1.el7.x86_64
spice-glib-devel-0.34-3.el7_5.2.x86_64
spice-server-devel-0.14.0-2.el7_5.5.x86_64
tar-1.26-34.el7.x86_64
vte-devel-0.28.2-10.el7.x86_64
xen-devel-4.8.4.43.ge52ec4b787-1.el7.x86_64
zlib-devel-1.2.7-17.el7.x86_64

Environment variables:
PACKAGES=bison bzip2 bzip2-devel ccache csnappy-devel flex  
   g++ gcc gettext git glib2-devel libaio-devel 
libepoxy-devel libfdt-devel librdmacm-devel lzo-devel make 
mesa-libEGL-devel 

Re: [Qemu-devel] [PATCH v4 1/4] fsdev-throttle-qmp: factor out throttle code to reuse code

[Eric Blake]

On 11/15/18 2:54 AM, xiezhide wrote:

This patch factor out throttle parameter parse code to common function


s/factor/factors/

Actually, when I write commit messages, I like to use the imperative 
mood, with an implicit "Apply this patch in order to" unspoken prefix. 
Starting with an explicit "This patch does" is more of a descriptive 
mood. So I might have written:


Factor out the throttle parameter parsing code to a new common function 
which will be used by block and fsdev.



which will be used by block and fsdev.
rename function throttle_parse_options to throttle_parse_group to resolve
function name conflict

Signed-off-by: xiezhide 
---
  block/throttle.c|  6 ++--
  blockdev.c  | 43 +-
  fsdev/qemu-fsdev-throttle.c | 44 ++
  include/qemu/throttle-options.h |  2 ++
  include/qemu/throttle.h |  4 +--
  include/qemu/typedefs.h |  1 +
  util/throttle.c | 68 +
  7 files changed, 79 insertions(+), 89 deletions(-)

+++ b/include/qemu/throttle-options.h
@@ -111,4 +111,6 @@
  .help = "when limiting by iops max size of an I/O in bytes",\
  }
  
+void throttle_parse_options(ThrottleConfig *, QemuOpts *);


It's okay to use parameter names in function declarations.


+++ b/include/qemu/typedefs.h
@@ -113,6 +113,7 @@ typedef struct uWireSlave uWireSlave;
  typedef struct VirtIODevice VirtIODevice;
  typedef struct Visitor Visitor;
  typedef struct node_info NodeInfo;
+typedef struct ThrottleConfig ThrottleConfig;


Please keep this in the right sorted location, right after SSIBus.

[Hmm, we already have an inconsistency on whether we are sorting by 
en_US rules, which are case-insensitive and therefore has 'struct 
node_info' in the wrong location, or by C rules which sort lowercase 
later and therefore has 'struct uWireSlave' in the wrong position. For 
that matter, why are we renaming 'struct node_info NodeInfo', and why 
does uWireSlave violate our naming conventions?  But those are 
independent cleanups, and not necessarily something for you to worry about]


With the sorting fixed,

Reviewed-by: Eric Blake 

--
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

Re: [Qemu-devel] [PATCH 0/4] keymaps: drop support for include files

[no-reply]

Hi,

This series failed docker-mingw@fedora build test. Please find the testing 
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

Message-id: 20181115123218.25387-1-kra...@redhat.com
Type: series
Subject: [Qemu-devel] [PATCH 0/4] keymaps: drop support for include files

=== TEST SCRIPT BEGIN ===
#!/bin/bash
time make docker-test-mingw@fedora SHOW_ENV=1 J=8
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
ed5fa6b keymaps: drop support for include files
96f504b keymaps: remove common include
b2833f8 keymaps: drop nl-be map
73dd69e keymaps: remove modifiers include

=== OUTPUT BEGIN ===
  BUILD   fedora
make[1]: Entering directory `/var/tmp/patchew-tester-tmp-yjbkfxnp/src'
  GEN 
/var/tmp/patchew-tester-tmp-yjbkfxnp/src/docker-src.2018-11-15-15.48.24.6093/qemu.tar
Cloning into 
'/var/tmp/patchew-tester-tmp-yjbkfxnp/src/docker-src.2018-11-15-15.48.24.6093/qemu.tar.vroot'...
done.
Checking out files:  46% (3003/6452)   
Checking out files:  47% (3033/6452)   
Checking out files:  48% (3097/6452)   
Checking out files:  49% (3162/6452)   
Checking out files:  50% (3226/6452)   
Checking out files:  51% (3291/6452)   
Checking out files:  52% (3356/6452)   
Checking out files:  53% (3420/6452)   
Checking out files:  54% (3485/6452)   
Checking out files:  55% (3549/6452)   
Checking out files:  56% (3614/6452)   
Checking out files:  57% (3678/6452)   
Checking out files:  58% (3743/6452)   
Checking out files:  59% (3807/6452)   
Checking out files:  60% (3872/6452)   
Checking out files:  61% (3936/6452)   
Checking out files:  62% (4001/6452)   
Checking out files:  63% (4065/6452)   
Checking out files:  64% (4130/6452)   
Checking out files:  65% (4194/6452)   
Checking out files:  66% (4259/6452)   
Checking out files:  67% (4323/6452)   
Checking out files:  68% (4388/6452)   
Checking out files:  69% (4452/6452)   
Checking out files:  70% (4517/6452)   
Checking out files:  71% (4581/6452)   
Checking out files:  72% (4646/6452)   
Checking out files:  73% (4710/6452)   
Checking out files:  74% (4775/6452)   
Checking out files:  75% (4839/6452)   
Checking out files:  76% (4904/6452)   
Checking out files:  77% (4969/6452)   
Checking out files:  78% (5033/6452)   
Checking out files:  79% (5098/6452)   
Checking out files:  80% (5162/6452)   
Checking out files:  81% (5227/6452)   
Checking out files:  82% (5291/6452)   
Checking out files:  83% (5356/6452)   
Checking out files:  84% (5420/6452)   
Checking out files:  85% (5485/6452)   
Checking out files:  86% (5549/6452)   
Checking out files:  87% (5614/6452)   
Checking out files:  88% (5678/6452)   
Checking out files:  89% (5743/6452)   
Checking out files:  90% (5807/6452)   
Checking out files:  91% (5872/6452)   
Checking out files:  92% (5936/6452)   
Checking out files:  93% (6001/6452)   
Checking out files:  94% (6065/6452)   
Checking out files:  95% (6130/6452)   
Checking out files:  96% (6194/6452)   
Checking out files:  97% (6259/6452)   
Checking out files:  98% (6323/6452)   
Checking out files:  99% (6388/6452)   
Checking out files: 100% (6452/6452)   
Checking out files: 100% (6452/6452), done.
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) 
registered for path 'ui/keycodemapdb'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out 
'6b3d716e2b6472eb7189d3220552280ef3d832ce'
  COPYRUNNER
RUN test-mingw in qemu:fedora 
Packages installed:
SDL2-devel-2.0.9-1.fc28.x86_64
bc-1.07.1-5.fc28.x86_64
bison-3.0.4-9.fc28.x86_64
bluez-libs-devel-5.50-1.fc28.x86_64
brlapi-devel-0.6.7-19.fc28.x86_64
bzip2-1.0.6-26.fc28.x86_64
bzip2-devel-1.0.6-26.fc28.x86_64
ccache-3.4.2-2.fc28.x86_64
clang-6.0.1-2.fc28.x86_64
device-mapper-multipath-devel-0.7.4-3.git07e7bd5.fc28.x86_64
findutils-4.6.0-19.fc28.x86_64
flex-2.6.1-7.fc28.x86_64
gcc-8.2.1-5.fc28.x86_64
gcc-c++-8.2.1-5.fc28.x86_64
gettext-0.19.8.1-14.fc28.x86_64
git-2.17.2-1.fc28.x86_64
glib2-devel-2.56.3-2.fc28.x86_64
glusterfs-api-devel-4.1.5-1.fc28.x86_64
gnutls-devel-3.6.4-1.fc28.x86_64
gtk3-devel-3.22.30-1.fc28.x86_64
hostname-3.20-3.fc28.x86_64
libaio-devel-0.3.110-11.fc28.x86_64
libasan-8.2.1-5.fc28.x86_64
libattr-devel-2.4.48-3.fc28.x86_64
libcap-devel-2.25-9.fc28.x86_64
libcap-ng-devel-0.7.9-4.fc28.x86_64
libcurl-devel-7.59.0-8.fc28.x86_64
libfdt-devel-1.4.7-1.fc28.x86_64
libpng-devel-1.6.34-6.fc28.x86_64
librbd-devel-12.2.8-1.fc28.x86_64
libssh2-devel-1.8.0-7.fc28.x86_64
libubsan-8.2.1-5.fc28.x86_64
libusbx-devel-1.0.22-1.fc28.x86_64
libxml2-devel-2.9.8-4.fc28.x86_64
llvm-6.0.1-8.fc28.x86_64
lzo-devel-2.08-12.fc28.x86_64
make-4.2.1-6.fc28.x86_64
mingw32-SDL2-2.0.9-1.fc28.noarch
mingw32-bzip2-1.0.6-9.fc27.noarch

Re: [Qemu-devel] [PULL 29/36] qemu-iotests: Test auto-read-only with -drive and -blockdev

[Eric Blake]

On 11/5/18 10:37 AM, Kevin Wolf wrote:

Signed-off-by: Kevin Wolf 
Reviewed-by: Eric Blake 
---
  tests/qemu-iotests/232 | 147 +
  tests/qemu-iotests/232.out |  59 +++
  tests/qemu-iotests/group   |   1 +
  3 files changed, 207 insertions(+)
  create mode 100755 tests/qemu-iotests/232
  create mode 100644 tests/qemu-iotests/232.out

diff --git a/tests/qemu-iotests/232 b/tests/qemu-iotests/232
new file mode 100755
index 00..bc2972d124
--- /dev/null
+++ b/tests/qemu-iotests/232
@@ -0,0 +1,147 @@
+#!/bin/bash
+#
+# Test for auto-read-only


This breaks './check -luks 232':

@@ -3,57 +3,60 @@

 === -drive with read-write image: read-only/auto-read-only 
combinations ===


-NODE_NAME: TEST_DIR/t.IMGFMT (file, read-only)
-NODE_NAME: TEST_DIR/t.IMGFMT (file, read-only)
-NODE_NAME: TEST_DIR/t.IMGFMT (file, read-only)
-
-NODE_NAME: TEST_DIR/t.IMGFMT (file)
-NODE_NAME: TEST_DIR/t.IMGFMT (file)
-NODE_NAME: TEST_DIR/t.IMGFMT (file)
-
-NODE_NAME: TEST_DIR/t.IMGFMT (file)
-NODE_NAME: TEST_DIR/t.IMGFMT (file)
-NODE_NAME: TEST_DIR/t.IMGFMT (file)
+QEMU_PROG: -drive 
driver=file,file=driver=IMGFMT,key-secret=keysec0,file.filename=TEST_DIR/t.IMGFMT,if=none,read-only=on,auto-read-only=off: 
Could not open 'driver=IMGFMT': No such file or directory
+QEMU_PROG: -drive 
driver=file,file=driver=IMGFMT,key-secret=keysec0,file.filename=TEST_DIR/t.IMGFMT,if=none,read-only=on,auto-read-only=on: 
Could not open 'driver=IMGFMT': No such file or directory


...

I know that for LUKS, you have to use --image-opts, which would require 
some rewrites of the commands you are testing; so maybe the best thing 
is to just blacklist this test from running on LUKS?


--
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

Re: [Qemu-devel] [PATCH for 3.1] x86: Add 3.1 machine types

[Dr. David Alan Gilbert]

* Marc-André Lureau (marcandre.lur...@gmail.com) wrote:
> On Thu, Nov 15, 2018 at 7:47 PM Dr. David Alan Gilbert (git)
>  wrote:
> >
> > From: "Dr. David Alan Gilbert" 
> >
> > x86 doesn't need a 3.1 machine type, because there's no incompatibility,
> > but it looks odd not having one, especially since s390, ppc and ARM have
> > it.  Join the party.
> >
> > Signed-off-by: Dr. David Alan Gilbert 
> > Suggested-by: Peter Maydell 
> 
> I sent same patch already reviewed by Michael a few weeks ago:
> https://lists.nongnu.org/archive/html/qemu-devel/2018-10/msg06574.html

OK, the problem is it's buried in the middle of a big series; can we
just take either this version or your version for 3.1?

> > ---
> >  hw/i386/pc_piix.c| 15 ---
> >  hw/i386/pc_q35.c | 13 +++--
> >  include/hw/i386/pc.h |  3 +++
> >  3 files changed, 26 insertions(+), 5 deletions(-)
> >
> > diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> > index dc09466b3e..7092d6d13f 100644
> > --- a/hw/i386/pc_piix.c
> > +++ b/hw/i386/pc_piix.c
> > @@ -428,21 +428,30 @@ static void pc_i440fx_machine_options(MachineClass *m)
> >  machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
> >  }
> >
> > -static void pc_i440fx_3_0_machine_options(MachineClass *m)
> > +static void pc_i440fx_3_1_machine_options(MachineClass *m)
> >  {
> >  pc_i440fx_machine_options(m);
> >  m->alias = "pc";
> >  m->is_default = 1;
> >  }
> >
> > +DEFINE_I440FX_MACHINE(v3_1, "pc-i440fx-3.1", NULL,
> > +  pc_i440fx_3_1_machine_options);
> > +
> > +static void pc_i440fx_3_0_machine_options(MachineClass *m)
> > +{
> > +pc_i440fx_3_1_machine_options(m);
> > +m->is_default = 0;
> > +m->alias = NULL;
> > +SET_MACHINE_COMPAT(m, PC_COMPAT_3_0);
> > +}
> > +
> >  DEFINE_I440FX_MACHINE(v3_0, "pc-i440fx-3.0", NULL,
> >pc_i440fx_3_0_machine_options);
> >
> >  static void pc_i440fx_2_12_machine_options(MachineClass *m)
> >  {
> >  pc_i440fx_3_0_machine_options(m);
> > -m->is_default = 0;
> > -m->alias = NULL;
> >  SET_MACHINE_COMPAT(m, PC_COMPAT_2_12);
> >  }
> >
> > diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> > index 532241e3f8..6799b3e553 100644
> > --- a/hw/i386/pc_q35.c
> > +++ b/hw/i386/pc_q35.c
> > @@ -311,19 +311,28 @@ static void pc_q35_machine_options(MachineClass *m)
> >  m->max_cpus = 288;
> >  }
> >
> > -static void pc_q35_3_0_machine_options(MachineClass *m)
> > +static void pc_q35_3_1_machine_options(MachineClass *m)
> >  {
> >  pc_q35_machine_options(m);
> >  m->alias = "q35";
> >  }
> >
> > +DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL,
> > +pc_q35_3_1_machine_options);
> > +
> > +static void pc_q35_3_0_machine_options(MachineClass *m)
> > +{
> > +pc_q35_3_1_machine_options(m);
> > +m->alias = NULL;
> > +SET_MACHINE_COMPAT(m, PC_COMPAT_3_0);
> > +}
> > +
> >  DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
> >  pc_q35_3_0_machine_options);
> >
> >  static void pc_q35_2_12_machine_options(MachineClass *m)
> >  {
> >  pc_q35_3_0_machine_options(m);
> > -m->alias = NULL;
> >  SET_MACHINE_COMPAT(m, PC_COMPAT_2_12);
> >  }
> >
> > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> > index 136fe497b6..c37d4333a0 100644
> > --- a/include/hw/i386/pc.h
> > +++ b/include/hw/i386/pc.h
> > @@ -294,6 +294,9 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t);
> >  int e820_get_num_entries(void);
> >  bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
> >
> > +#define PC_COMPAT_3_1 \
> > +HW_COMPAT_3_1
> 
> you shouldn't need that, right?

Oops, true, that's for next time around.

Dave

> > +
> >  #define PC_COMPAT_3_0 \
> >  HW_COMPAT_3_0 \
> >  {\
> > --
> > 2.19.1
> >
> >
> 
> 
> -- 
> Marc-André Lureau
--
Dr. David Alan Gilbert / dgilb...@redhat.com / Manchester, UK

Re: [Qemu-devel] [PATCH for-3.1?] file-posix: Better checks of 64-bit copy_range

[Eric Blake]

On 11/14/18 3:05 PM, Eric Blake wrote:

file-posix.c was taking a 64-bit bytes in raw_co_copy_range_to(),
passing it through a 32-bit parameter of paio_submit_co_full(),
then widening it back to size_t when assigning into acb->aio_nbytes.

Looking at io.c, I can't quickly tell if bdrv_co_copy_range_internal()
is fragmenting things to honor bs->bl.max_transfer, or if it can
accidentally send requests larger than 2G down to the driver. If
the former, then this is a no-op; if the latter, then someone needs
to find a way to trigger this assertion and patch the block layer
to properly fragment copy_range requests.  Either way, we're better
off with an assertion than the risk of silent data corruption.

Signed-off-by: Eric Blake 
---
  block/file-posix.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)


This patch is not needed after Kevin's file-posix cleanups for post-release:
https://lists.gnu.org/archive/html/qemu-devel/2018-11/msg02985.html

The question remains, though, if we still want this in 3.1.



diff --git a/block/file-posix.c b/block/file-posix.c
index 58c86a01eaa..48ad3bb372a 100644
--- a/block/file-posix.c
+++ b/block/file-posix.c
@@ -1821,7 +1821,7 @@ static int aio_worker(void *arg)
  static int paio_submit_co_full(BlockDriverState *bs, int fd,
 int64_t offset, int fd2, int64_t offset2,
 QEMUIOVector *qiov,
-   int bytes, int type)
+   uint64_t bytes, int type)
  {
  RawPosixAIOData *acb = g_new(RawPosixAIOData, 1);
  ThreadPool *pool;
@@ -1832,6 +1832,7 @@ static int paio_submit_co_full(BlockDriverState *bs, int 
fd,
  acb->aio_fd2 = fd2;
  acb->aio_offset2 = offset2;

+assert(bytes <= SIZE_MAX);
  acb->aio_nbytes = bytes;
  acb->aio_offset = offset;

@@ -1848,7 +1849,7 @@ static int paio_submit_co_full(BlockDriverState *bs, int 
fd,

  static inline int paio_submit_co(BlockDriverState *bs, int fd,
   int64_t offset, QEMUIOVector *qiov,
- int bytes, int type)
+ uint64_t bytes, int type)
  {
  return paio_submit_co_full(bs, fd, offset, -1, 0, qiov, bytes, type);
  }



--
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

Re: [Qemu-devel] [PATCH for 3.1] x86: Add 3.1 machine types

[Marc-André Lureau]

On Thu, Nov 15, 2018 at 7:47 PM Dr. David Alan Gilbert (git)
 wrote:
>
> From: "Dr. David Alan Gilbert" 
>
> x86 doesn't need a 3.1 machine type, because there's no incompatibility,
> but it looks odd not having one, especially since s390, ppc and ARM have
> it.  Join the party.
>
> Signed-off-by: Dr. David Alan Gilbert 
> Suggested-by: Peter Maydell 

I sent same patch already reviewed by Michael a few weeks ago:
https://lists.nongnu.org/archive/html/qemu-devel/2018-10/msg06574.html

> ---
>  hw/i386/pc_piix.c| 15 ---
>  hw/i386/pc_q35.c | 13 +++--
>  include/hw/i386/pc.h |  3 +++
>  3 files changed, 26 insertions(+), 5 deletions(-)
>
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index dc09466b3e..7092d6d13f 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -428,21 +428,30 @@ static void pc_i440fx_machine_options(MachineClass *m)
>  machine_class_allow_dynamic_sysbus_dev(m, TYPE_RAMFB_DEVICE);
>  }
>
> -static void pc_i440fx_3_0_machine_options(MachineClass *m)
> +static void pc_i440fx_3_1_machine_options(MachineClass *m)
>  {
>  pc_i440fx_machine_options(m);
>  m->alias = "pc";
>  m->is_default = 1;
>  }
>
> +DEFINE_I440FX_MACHINE(v3_1, "pc-i440fx-3.1", NULL,
> +  pc_i440fx_3_1_machine_options);
> +
> +static void pc_i440fx_3_0_machine_options(MachineClass *m)
> +{
> +pc_i440fx_3_1_machine_options(m);
> +m->is_default = 0;
> +m->alias = NULL;
> +SET_MACHINE_COMPAT(m, PC_COMPAT_3_0);
> +}
> +
>  DEFINE_I440FX_MACHINE(v3_0, "pc-i440fx-3.0", NULL,
>pc_i440fx_3_0_machine_options);
>
>  static void pc_i440fx_2_12_machine_options(MachineClass *m)
>  {
>  pc_i440fx_3_0_machine_options(m);
> -m->is_default = 0;
> -m->alias = NULL;
>  SET_MACHINE_COMPAT(m, PC_COMPAT_2_12);
>  }
>
> diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
> index 532241e3f8..6799b3e553 100644
> --- a/hw/i386/pc_q35.c
> +++ b/hw/i386/pc_q35.c
> @@ -311,19 +311,28 @@ static void pc_q35_machine_options(MachineClass *m)
>  m->max_cpus = 288;
>  }
>
> -static void pc_q35_3_0_machine_options(MachineClass *m)
> +static void pc_q35_3_1_machine_options(MachineClass *m)
>  {
>  pc_q35_machine_options(m);
>  m->alias = "q35";
>  }
>
> +DEFINE_Q35_MACHINE(v3_1, "pc-q35-3.1", NULL,
> +pc_q35_3_1_machine_options);
> +
> +static void pc_q35_3_0_machine_options(MachineClass *m)
> +{
> +pc_q35_3_1_machine_options(m);
> +m->alias = NULL;
> +SET_MACHINE_COMPAT(m, PC_COMPAT_3_0);
> +}
> +
>  DEFINE_Q35_MACHINE(v3_0, "pc-q35-3.0", NULL,
>  pc_q35_3_0_machine_options);
>
>  static void pc_q35_2_12_machine_options(MachineClass *m)
>  {
>  pc_q35_3_0_machine_options(m);
> -m->alias = NULL;
>  SET_MACHINE_COMPAT(m, PC_COMPAT_2_12);
>  }
>
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 136fe497b6..c37d4333a0 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -294,6 +294,9 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t);
>  int e820_get_num_entries(void);
>  bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
>
> +#define PC_COMPAT_3_1 \
> +HW_COMPAT_3_1

you shouldn't need that, right?

> +
>  #define PC_COMPAT_3_0 \
>  HW_COMPAT_3_0 \
>  {\
> --
> 2.19.1
>
>


-- 
Marc-André Lureau

[Qemu-devel] [PATCH v2 12/12] i2c: Add a reset function to smbus_eeprom

[minyard]

From: Corey Minyard 

Reset the contents to init data and reset the offset on a machine
reset.

Signed-off-by: Corey Minyard 
---
 hw/i2c/smbus_eeprom.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
index 942057dc10..d0a8d63869 100644
--- a/hw/i2c/smbus_eeprom.c
+++ b/hw/i2c/smbus_eeprom.c
@@ -106,7 +106,7 @@ static const VMStateDescription vmstate_smbus_eeprom = {
 }
 };
 
-static void smbus_eeprom_realize(DeviceState *dev, Error **errp)
+static void smbus_eeprom_reset(DeviceState *dev)
 {
 SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
 
@@ -114,6 +114,11 @@ static void smbus_eeprom_realize(DeviceState *dev, Error 
**errp)
 eeprom->offset = 0;
 }
 
+static void smbus_eeprom_realize(DeviceState *dev, Error **errp)
+{
+smbus_eeprom_reset(dev);
+}
+
 static Property smbus_eeprom_properties[] = {
 DEFINE_PROP_PTR("data", SMBusEEPROMDevice, init_data),
 DEFINE_PROP_END_OF_LIST(),
@@ -125,6 +130,7 @@ static void smbus_eeprom_class_initfn(ObjectClass *klass, 
void *data)
 SMBusDeviceClass *sc = SMBUS_DEVICE_CLASS(klass);
 
 dc->realize = smbus_eeprom_realize;
+dc->reset = smbus_eeprom_reset;
 sc->receive_byte = eeprom_receive_byte;
 sc->write_data = eeprom_write_data;
 dc->props = smbus_eeprom_properties;
-- 
2.17.1

[Qemu-devel] [PATCH v2 06/12] boards.h: Ignore migration for SMBus devices on older machines

[minyard]

From: Corey Minyard 

Migration capability is being added for pm_smbus and SMBus devices.
This change will allow backwards compatibility to be kept when
migrating back to an old qemu version.  Add a bool to the machine
class tho keep smbus migration from happening.  Future changes
will use this.

Signed-off-by: Corey Minyard 
Cc: Eduardo Habkost 
Cc: Marcel Apfelbaum 
---
 hw/i386/pc_piix.c   | 1 +
 hw/i386/pc_q35.c| 1 +
 include/hw/boards.h | 1 +
 3 files changed, 3 insertions(+)

diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index cb28227cc3..3d1ccb1af1 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -443,6 +443,7 @@ static void pc_i440fx_2_12_machine_options(MachineClass *m)
 pc_i440fx_3_0_machine_options(m);
 m->is_default = 0;
 m->alias = NULL;
+m->smbus_no_migration_support = true;
 SET_MACHINE_COMPAT(m, PC_COMPAT_2_12);
 }
 
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 90e88c9b28..0c6fca6a40 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -324,6 +324,7 @@ static void pc_q35_2_12_machine_options(MachineClass *m)
 {
 pc_q35_3_0_machine_options(m);
 m->alias = NULL;
+m->smbus_no_migration_support = true;
 SET_MACHINE_COMPAT(m, PC_COMPAT_2_12);
 }
 
diff --git a/include/hw/boards.h b/include/hw/boards.h
index f82f28468b..65314fbe2a 100644
--- a/include/hw/boards.h
+++ b/include/hw/boards.h
@@ -207,6 +207,7 @@ struct MachineClass {
 void (*numa_auto_assign_ram)(MachineClass *mc, NodeInfo *nodes,
  int nb_nodes, ram_addr_t size);
 bool ignore_boot_device_suffixes;
+bool smbus_no_migration_support;
 
 HotplugHandler *(*get_hotplug_handler)(MachineState *machine,
DeviceState *dev);
-- 
2.17.1

[Qemu-devel] [PATCH v2 09/12] i2c: Add normal type name and cast to smbus_eeprom.c

[minyard]

From: Corey Minyard 

Create a type name and a cast macro and use those through the
code.

Signed-off-by: Corey Minyard 
---
 hw/i2c/smbus_eeprom.c | 15 ++-
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
index 4d25222e23..8d4eed129f 100644
--- a/hw/i2c/smbus_eeprom.c
+++ b/hw/i2c/smbus_eeprom.c
@@ -30,6 +30,11 @@
 
 //#define DEBUG
 
+#define TYPE_SMBUS_EEPROM "smbus-eeprom"
+
+#define SMBUS_EEPROM(obj) \
+OBJECT_CHECK(SMBusEEPROMDevice, (obj), TYPE_SMBUS_EEPROM)
+
 typedef struct SMBusEEPROMDevice {
 SMBusDevice smbusdev;
 void *data;
@@ -38,7 +43,7 @@ typedef struct SMBusEEPROMDevice {
 
 static uint8_t eeprom_receive_byte(SMBusDevice *dev)
 {
-SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
+SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
 uint8_t *data = eeprom->data;
 uint8_t val = data[eeprom->offset++];
 
@@ -51,7 +56,7 @@ static uint8_t eeprom_receive_byte(SMBusDevice *dev)
 
 static int eeprom_write_data(SMBusDevice *dev, uint8_t *buf, uint8_t len)
 {
-SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
+SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
 uint8_t *data = eeprom->data;
 
 #ifdef DEBUG
@@ -73,7 +78,7 @@ static int eeprom_write_data(SMBusDevice *dev, uint8_t *buf, 
uint8_t len)
 
 static void smbus_eeprom_realize(DeviceState *dev, Error **errp)
 {
-SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *)dev;
+SMBusEEPROMDevice *eeprom = SMBUS_EEPROM(dev);
 
 eeprom->offset = 0;
 }
@@ -97,7 +102,7 @@ static void smbus_eeprom_class_initfn(ObjectClass *klass, 
void *data)
 }
 
 static const TypeInfo smbus_eeprom_info = {
-.name  = "smbus-eeprom",
+.name  = TYPE_SMBUS_EEPROM,
 .parent= TYPE_SMBUS_DEVICE,
 .instance_size = sizeof(SMBusEEPROMDevice),
 .class_init= smbus_eeprom_class_initfn,
@@ -114,7 +119,7 @@ void smbus_eeprom_init_one(I2CBus *smbus, uint8_t address, 
uint8_t *eeprom_buf)
 {
 DeviceState *dev;
 
-dev = qdev_create((BusState *) smbus, "smbus-eeprom");
+dev = qdev_create((BusState *) smbus, TYPE_SMBUS_EEPROM);
 qdev_prop_set_uint8(dev, "address", address);
 qdev_prop_set_ptr(dev, "data", eeprom_buf);
 qdev_init_nofail(dev);
-- 
2.17.1

[Qemu-devel] [PATCH v2 07/12] i2c:pm_smbus: Fix state transfer

[minyard]

From: Corey Minyard 

Transfer the state information for the SMBus registers and
internal data so it will work on a VM transfer.

Signed-off-by: Corey Minyard 
Cc: Michael S. Tsirkin 
Cc: Paolo Bonzini 
Cc: Dr. David Alan Gilbert 
---
 hw/acpi/piix4.c   |  3 ++-
 hw/i2c/pm_smbus.c | 31 +++
 hw/i2c/smbus_ich9.c   |  6 --
 include/hw/i2c/pm_smbus.h |  2 ++
 4 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index e330f24c71..313305f5a0 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -309,7 +309,7 @@ static const VMStateDescription vmstate_cpuhp_state = {
  */
 static const VMStateDescription vmstate_acpi = {
 .name = "piix4_pm",
-.version_id = 3,
+.version_id = 4,
 .minimum_version_id = 3,
 .minimum_version_id_old = 1,
 .load_state_old = acpi_load_old,
@@ -320,6 +320,7 @@ static const VMStateDescription vmstate_acpi = {
 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
+VMSTATE_STRUCT(smb, PIIX4PMState, 4, pmsmb_vmstate, PMSMBus),
 VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c
index 8793113c25..75907e1c22 100644
--- a/hw/i2c/pm_smbus.c
+++ b/hw/i2c/pm_smbus.c
@@ -19,6 +19,7 @@
  */
 #include "qemu/osdep.h"
 #include "hw/hw.h"
+#include "hw/boards.h"
 #include "hw/i2c/pm_smbus.h"
 #include "hw/i2c/smbus_master.h"
 
@@ -450,6 +451,36 @@ static const MemoryRegionOps pm_smbus_ops = {
 .endianness = DEVICE_LITTLE_ENDIAN,
 };
 
+static bool pm_smbus_vmstate_needed(void *opaque)
+{
+MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
+
+return !mc->smbus_no_migration_support;
+}
+
+const VMStateDescription pmsmb_vmstate = {
+.name = "pmsmb",
+.version_id = 1,
+.minimum_version_id = 1,
+.needed = pm_smbus_vmstate_needed,
+.fields = (VMStateField[]) {
+VMSTATE_UINT8(smb_stat, PMSMBus),
+VMSTATE_UINT8(smb_ctl, PMSMBus),
+VMSTATE_UINT8(smb_cmd, PMSMBus),
+VMSTATE_UINT8(smb_addr, PMSMBus),
+VMSTATE_UINT8(smb_data0, PMSMBus),
+VMSTATE_UINT8(smb_data1, PMSMBus),
+VMSTATE_UINT32(smb_index, PMSMBus),
+VMSTATE_UINT8_ARRAY(smb_data, PMSMBus, PM_SMBUS_MAX_MSG_SIZE),
+VMSTATE_UINT8(smb_auxctl, PMSMBus),
+VMSTATE_BOOL(i2c_enable, PMSMBus),
+VMSTATE_BOOL(op_done, PMSMBus),
+VMSTATE_BOOL(in_i2c_block_read, PMSMBus),
+VMSTATE_BOOL(start_transaction_on_status_read, PMSMBus),
+VMSTATE_END_OF_LIST()
+}
+};
+
 void pm_smbus_init(DeviceState *parent, PMSMBus *smb, bool force_aux_blk)
 {
 smb->op_done = true;
diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c
index e6d8d28194..c9b7482a54 100644
--- a/hw/i2c/smbus_ich9.c
+++ b/hw/i2c/smbus_ich9.c
@@ -45,10 +45,12 @@ typedef struct ICH9SMBState {
 
 static const VMStateDescription vmstate_ich9_smbus = {
 .name = "ich9_smb",
-.version_id = 1,
+.version_id = 2,
 .minimum_version_id = 1,
 .fields = (VMStateField[]) {
-VMSTATE_PCI_DEVICE(dev, struct ICH9SMBState),
+VMSTATE_PCI_DEVICE(dev, ICH9SMBState),
+VMSTATE_BOOL_V(irq_enabled, ICH9SMBState, 2),
+VMSTATE_STRUCT(smb, ICH9SMBState, 2, pmsmb_vmstate, PMSMBus),
 VMSTATE_END_OF_LIST()
 }
 };
diff --git a/include/hw/i2c/pm_smbus.h b/include/hw/i2c/pm_smbus.h
index 7bcca97672..5075fc64fa 100644
--- a/include/hw/i2c/pm_smbus.h
+++ b/include/hw/i2c/pm_smbus.h
@@ -43,4 +43,6 @@ typedef struct PMSMBus {
 
 void pm_smbus_init(DeviceState *parent, PMSMBus *smb, bool force_aux_blk);
 
+extern const VMStateDescription pmsmb_vmstate;
+
 #endif /* PM_SMBUS_H */
-- 
2.17.1

[Qemu-devel] [PATCH v2 10/12] i2c: Add a size constant for the smbus_eeprom size

[minyard]

From: Corey Minyard 

It was hard-coded to 256 in a number of places, create a constant
for that.

Signed-off-by: Corey Minyard 
---
 hw/i2c/smbus_eeprom.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
index 8d4eed129f..8e9b734c09 100644
--- a/hw/i2c/smbus_eeprom.c
+++ b/hw/i2c/smbus_eeprom.c
@@ -35,6 +35,8 @@
 #define SMBUS_EEPROM(obj) \
 OBJECT_CHECK(SMBusEEPROMDevice, (obj), TYPE_SMBUS_EEPROM)
 
+#define SMBUS_EEPROM_SIZE 256
+
 typedef struct SMBusEEPROMDevice {
 SMBusDevice smbusdev;
 void *data;
@@ -70,7 +72,7 @@ static int eeprom_write_data(SMBusDevice *dev, uint8_t *buf, 
uint8_t len)
 
 for (; len > 0; len--) {
 data[eeprom->offset] = *buf++;
-eeprom->offset = (eeprom->offset + 1) % 256;
+eeprom->offset = (eeprom->offset + 1) % SMBUS_EEPROM_SIZE;
 }
 
 return 0;
@@ -129,12 +131,14 @@ void smbus_eeprom_init(I2CBus *smbus, int nb_eeprom,
const uint8_t *eeprom_spd, int eeprom_spd_size)
 {
 int i;
-uint8_t *eeprom_buf = g_malloc0(8 * 256); /* XXX: make this persistent */
+ /* XXX: make this persistent */
+uint8_t *eeprom_buf = g_malloc0(8 * SMBUS_EEPROM_SIZE);
 if (eeprom_spd_size > 0) {
 memcpy(eeprom_buf, eeprom_spd, eeprom_spd_size);
 }
 
 for (i = 0; i < nb_eeprom; i++) {
-smbus_eeprom_init_one(smbus, 0x50 + i, eeprom_buf + (i * 256));
+smbus_eeprom_init_one(smbus, 0x50 + i,
+  eeprom_buf + (i * SMBUS_EEPROM_SIZE));
 }
 }
-- 
2.17.1

[Qemu-devel] [PATCH v2 02/12] i2c: have I2C receive operation return uint8_t

[minyard]

From: Corey Minyard 

It is never supposed to fail and cannot return an error, so just
have it return the proper type.  Have it return 0xff on nothing
available, since that's what would happen on a real bus.

Signed-off-by: Corey Minyard 
---
 hw/arm/pxa2xx.c |  2 +-
 hw/arm/tosa.c   |  4 ++--
 hw/arm/z2.c |  2 +-
 hw/audio/wm8750.c   |  2 +-
 hw/display/sii9022.c|  2 +-
 hw/display/ssd0303.c|  4 ++--
 hw/gpio/max7310.c   |  2 +-
 hw/i2c/core.c   | 32 +---
 hw/i2c/i2c-ddc.c|  2 +-
 hw/i2c/smbus_slave.c|  4 ++--
 hw/input/lm832x.c   |  2 +-
 hw/misc/pca9552.c   |  2 +-
 hw/misc/tmp105.c|  2 +-
 hw/misc/tmp421.c|  2 +-
 hw/nvram/eeprom_at24c.c |  4 ++--
 hw/timer/ds1338.c   |  2 +-
 hw/timer/m41t80.c   |  2 +-
 hw/timer/twl92230.c |  2 +-
 include/hw/i2c/i2c.h|  7 +++
 19 files changed, 37 insertions(+), 44 deletions(-)

diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c
index f598a1c053..3d7c88910e 100644
--- a/hw/arm/pxa2xx.c
+++ b/hw/arm/pxa2xx.c
@@ -1286,7 +1286,7 @@ static int pxa2xx_i2c_event(I2CSlave *i2c, enum i2c_event 
event)
 return 0;
 }
 
-static int pxa2xx_i2c_rx(I2CSlave *i2c)
+static uint8_t pxa2xx_i2c_rx(I2CSlave *i2c)
 {
 PXA2xxI2CSlaveState *slave = PXA2XX_I2C_SLAVE(i2c);
 PXA2xxI2CState *s = slave->host;
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index 7a925fa5e6..eef9d427e7 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -197,10 +197,10 @@ static int tosa_dac_event(I2CSlave *i2c, enum i2c_event 
event)
 return 0;
 }
 
-static int tosa_dac_recv(I2CSlave *s)
+static uint8_t tosa_dac_recv(I2CSlave *s)
 {
 printf("%s: recv not supported!!!\n", __func__);
-return -1;
+return 0xff;
 }
 
 static void tosa_tg_init(PXA2xxState *cpu)
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index 697a822f1e..6f18d924df 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -243,7 +243,7 @@ static int aer915_event(I2CSlave *i2c, enum i2c_event event)
 return 0;
 }
 
-static int aer915_recv(I2CSlave *slave)
+static uint8_t aer915_recv(I2CSlave *slave)
 {
 AER915State *s = AER915(slave);
 int retval = 0x00;
diff --git a/hw/audio/wm8750.c b/hw/audio/wm8750.c
index f4aa838f62..169b006ade 100644
--- a/hw/audio/wm8750.c
+++ b/hw/audio/wm8750.c
@@ -561,7 +561,7 @@ static int wm8750_tx(I2CSlave *i2c, uint8_t data)
 return 0;
 }
 
-static int wm8750_rx(I2CSlave *i2c)
+static uint8_t wm8750_rx(I2CSlave *i2c)
 {
 return 0x00;
 }
diff --git a/hw/display/sii9022.c b/hw/display/sii9022.c
index eaf11a6e7b..9994385c35 100644
--- a/hw/display/sii9022.c
+++ b/hw/display/sii9022.c
@@ -79,7 +79,7 @@ static int sii9022_event(I2CSlave *i2c, enum i2c_event event)
 return 0;
 }
 
-static int sii9022_rx(I2CSlave *i2c)
+static uint8_t sii9022_rx(I2CSlave *i2c)
 {
 sii9022_state *s = SII9022(i2c);
 uint8_t res = 0x00;
diff --git a/hw/display/ssd0303.c b/hw/display/ssd0303.c
index eb90ba26be..8edf34986c 100644
--- a/hw/display/ssd0303.c
+++ b/hw/display/ssd0303.c
@@ -62,10 +62,10 @@ typedef struct {
 uint8_t framebuffer[132*8];
 } ssd0303_state;
 
-static int ssd0303_recv(I2CSlave *i2c)
+static uint8_t ssd0303_recv(I2CSlave *i2c)
 {
 BADF("Reads not implemented\n");
-return -1;
+return 0xff;
 }
 
 static int ssd0303_send(I2CSlave *i2c, uint8_t data)
diff --git a/hw/gpio/max7310.c b/hw/gpio/max7310.c
index a560e3afd2..f35a930276 100644
--- a/hw/gpio/max7310.c
+++ b/hw/gpio/max7310.c
@@ -39,7 +39,7 @@ static void max7310_reset(DeviceState *dev)
 s->command = 0x00;
 }
 
-static int max7310_rx(I2CSlave *i2c)
+static uint8_t max7310_rx(I2CSlave *i2c)
 {
 MAX7310State *s = MAX7310(i2c);
 
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index b54725985a..15237ad073 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -191,23 +191,17 @@ int i2c_send_recv(I2CBus *bus, uint8_t *data, bool send)
 }
 return ret ? -1 : 0;
 } else {
-if ((QLIST_EMPTY(>current_devs)) || (bus->broadcast)) {
-return -1;
-}
-
-sc = I2C_SLAVE_GET_CLASS(QLIST_FIRST(>current_devs)->elt);
-if (sc->recv) {
-s = QLIST_FIRST(>current_devs)->elt;
-ret = sc->recv(s);
-trace_i2c_recv(s->address, ret);
-if (ret < 0) {
-return ret;
-} else {
-*data = ret;
-return 0;
+ret = 0xff;
+if (!QLIST_EMPTY(>current_devs) && !bus->broadcast) {
+sc = I2C_SLAVE_GET_CLASS(QLIST_FIRST(>current_devs)->elt);
+if (sc->recv) {
+s = QLIST_FIRST(>current_devs)->elt;
+ret = sc->recv(s);
+trace_i2c_recv(s->address, ret);
 }
 }
-return -1;
+*data = ret;
+return 0;
 }
 }
 
@@ -216,12 +210,12 @@ int i2c_send(I2CBus *bus, uint8_t data)
 return i2c_send_recv(bus, , true);
 }
 
-int i2c_recv(I2CBus *bus)
+uint8_t 

[Qemu-devel] [PATCH v2 08/12] i2c: Add an SMBus vmstate structure

[minyard]

From: Corey Minyard 

There is no vmstate handling for SMBus, so no device sitting on SMBus
can have a state transfer that works reliably.  So add it.

Signed-off-by: Corey Minyard 
Cc: Paolo Bonzini 
Cc: Michael S. Tsirkin 
Cc: Dr. David Alan Gilbert 
---
 hw/i2c/smbus_slave.c | 18 ++
 include/hw/i2c/smbus_slave.h | 24 +---
 2 files changed, 39 insertions(+), 3 deletions(-)

diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c
index fa988919d8..b8a2d521f4 100644
--- a/hw/i2c/smbus_slave.c
+++ b/hw/i2c/smbus_slave.c
@@ -206,6 +206,24 @@ static void smbus_device_class_init(ObjectClass *klass, 
void *data)
 sc->send = smbus_i2c_send;
 }
 
+bool smbus_vmstate_needed(SMBusDevice *dev)
+{
+return dev->mode != SMBUS_IDLE;
+}
+
+const VMStateDescription vmstate_smbus_device = {
+.name = TYPE_SMBUS_DEVICE,
+.version_id = 1,
+.minimum_version_id = 1,
+.fields  = (VMStateField[]) {
+VMSTATE_I2C_SLAVE(i2c, SMBusDevice),
+VMSTATE_INT32(mode, SMBusDevice),
+VMSTATE_INT32(data_len, SMBusDevice),
+VMSTATE_UINT8_ARRAY(data_buf, SMBusDevice, SMBUS_DATA_MAX_LEN),
+VMSTATE_END_OF_LIST()
+}
+};
+
 static const TypeInfo smbus_device_type_info = {
 .name = TYPE_SMBUS_DEVICE,
 .parent = TYPE_I2C_SLAVE,
diff --git a/include/hw/i2c/smbus_slave.h b/include/hw/i2c/smbus_slave.h
index eabac1dd73..d53d691bf6 100644
--- a/include/hw/i2c/smbus_slave.h
+++ b/include/hw/i2c/smbus_slave.h
@@ -75,14 +75,32 @@ typedef struct SMBusDeviceClass
 void (*transaction_complete)(SMBusDevice *dev);
 } SMBusDeviceClass;
 
+#define SMBUS_DATA_MAX_LEN 34  /* command + len + 32 bytes of data.  */
+
 struct SMBusDevice {
 /* The SMBus protocol is implemented on top of I2C.  */
 I2CSlave i2c;
 
 /* Remaining fields for internal use only.  */
-int mode;
-int data_len;
-uint8_t data_buf[34]; /* command + len + 32 bytes of data.  */
+int32_t mode;
+int32_t data_len;
+uint8_t data_buf[SMBUS_DATA_MAX_LEN];
 };
 
+extern const VMStateDescription vmstate_smbus_device;
+
+#define VMSTATE_SMBUS_DEVICE(_field, _state) {   \
+.name   = (stringify(_field)),   \
+.size   = sizeof(SMBusDevice),   \
+.vmsd   = _smbus_device, \
+.flags  = VMS_STRUCT,\
+.offset = vmstate_offset_value(_state, _field, SMBusDevice), \
+}
+
+/*
+ * Users should call this in their .needed functions to know if the
+ * SMBus slave data needs to be transferred.
+ */
+bool smbus_vmstate_needed(SMBusDevice *dev);
+
 #endif
-- 
2.17.1

[Qemu-devel] [PATCH v2 01/12] i2c: Split smbus into parts

[minyard]

From: Corey Minyard 

smbus.c and smbus.h had device side code, master side code, and
smbus.h has some smbus_eeprom.c definitions.  Split them into
separate files.

Signed-off-by: Corey Minyard 
---
 hw/arm/aspeed.c   |   2 +-
 hw/i2c/Makefile.objs  |   2 +-
 hw/i2c/pm_smbus.c |   2 +-
 hw/i2c/smbus_eeprom.c |   3 +-
 hw/i2c/smbus_ich9.c   |   2 -
 hw/i2c/smbus_master.c | 165 ++
 hw/i2c/{smbus.c => smbus_slave.c} | 153 +---
 hw/i386/pc_piix.c |   2 +-
 hw/i386/pc_q35.c  |   2 +-
 hw/isa/vt82c686.c |   1 -
 hw/mips/mips_fulong2e.c   |   2 +-
 hw/mips/mips_malta.c  |   2 +-
 hw/ppc/sam460ex.c |   2 +-
 include/hw/i2c/pm_smbus.h |   2 +
 include/hw/i2c/smbus_eeprom.h |  11 ++
 include/hw/i2c/smbus_master.h |  55 
 include/hw/i2c/{smbus.h => smbus_slave.h} |  35 +
 17 files changed, 251 insertions(+), 192 deletions(-)
 create mode 100644 hw/i2c/smbus_master.c
 rename hw/i2c/{smbus.c => smbus_slave.c} (64%)
 create mode 100644 include/hw/i2c/smbus_eeprom.h
 create mode 100644 include/hw/i2c/smbus_master.h
 rename include/hw/i2c/{smbus.h => smbus_slave.h} (65%)

diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 6b33ecd5aa..69a19df00d 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -18,7 +18,7 @@
 #include "hw/arm/aspeed.h"
 #include "hw/arm/aspeed_soc.h"
 #include "hw/boards.h"
-#include "hw/i2c/smbus.h"
+#include "hw/i2c/smbus_eeprom.h"
 #include "qemu/log.h"
 #include "sysemu/block-backend.h"
 #include "hw/loader.h"
diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs
index 37cacde978..8973edfa22 100644
--- a/hw/i2c/Makefile.objs
+++ b/hw/i2c/Makefile.objs
@@ -1,4 +1,4 @@
-common-obj-$(CONFIG_I2C) += core.o smbus.o smbus_eeprom.o
+common-obj-$(CONFIG_I2C) += core.o smbus_slave.o smbus_master.o smbus_eeprom.o
 common-obj-$(CONFIG_DDC) += i2c-ddc.o
 common-obj-$(CONFIG_VERSATILE_I2C) += versatile_i2c.o
 common-obj-$(CONFIG_ACPI_X86) += smbus_ich9.o
diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c
index 685a2378ed..f3c6cc46f9 100644
--- a/hw/i2c/pm_smbus.c
+++ b/hw/i2c/pm_smbus.c
@@ -20,7 +20,7 @@
 #include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/i2c/pm_smbus.h"
-#include "hw/i2c/smbus.h"
+#include "hw/i2c/smbus_master.h"
 
 #define SMBHSTSTS   0x00
 #define SMBHSTCNT   0x02
diff --git a/hw/i2c/smbus_eeprom.c b/hw/i2c/smbus_eeprom.c
index f18aa3de35..d82423aa7e 100644
--- a/hw/i2c/smbus_eeprom.c
+++ b/hw/i2c/smbus_eeprom.c
@@ -25,7 +25,8 @@
 #include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/i2c/i2c.h"
-#include "hw/i2c/smbus.h"
+#include "hw/i2c/smbus_slave.h"
+#include "hw/i2c/smbus_eeprom.h"
 
 //#define DEBUG
 
diff --git a/hw/i2c/smbus_ich9.c b/hw/i2c/smbus_ich9.c
index 2a8b49e02f..e6d8d28194 100644
--- a/hw/i2c/smbus_ich9.c
+++ b/hw/i2c/smbus_ich9.c
@@ -29,8 +29,6 @@
 #include "hw/i2c/pm_smbus.h"
 #include "hw/pci/pci.h"
 #include "sysemu/sysemu.h"
-#include "hw/i2c/i2c.h"
-#include "hw/i2c/smbus.h"
 
 #include "hw/i386/ich9.h"
 
diff --git a/hw/i2c/smbus_master.c b/hw/i2c/smbus_master.c
new file mode 100644
index 00..0a6223744c
--- /dev/null
+++ b/hw/i2c/smbus_master.c
@@ -0,0 +1,165 @@
+/*
+ * QEMU SMBus host (master) emulation.
+ *
+ * This code emulates SMBus transactions from the master point of view,
+ * it runs the individual I2C transaction to do the SMBus protocol
+ * over I2C.
+ *
+ * Copyright (c) 2007 CodeSourcery.
+ * Written by Paul Brook
+ *
+ * This code is licensed under the LGPL.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "hw/i2c/i2c.h"
+#include "hw/i2c/smbus_master.h"
+
+/* Master device commands.  */
+int smbus_quick_command(I2CBus *bus, uint8_t addr, int read)
+{
+if (i2c_start_transfer(bus, addr, read)) {
+return -1;
+}
+i2c_end_transfer(bus);
+return 0;
+}
+
+int smbus_receive_byte(I2CBus *bus, uint8_t addr)
+{
+uint8_t data;
+
+if (i2c_start_transfer(bus, addr, 1)) {
+return -1;
+}
+data = i2c_recv(bus);
+i2c_nack(bus);
+i2c_end_transfer(bus);
+return data;
+}
+
+int smbus_send_byte(I2CBus *bus, uint8_t addr, uint8_t data)
+{
+if (i2c_start_transfer(bus, addr, 0)) {
+return -1;
+}
+i2c_send(bus, data);
+i2c_end_transfer(bus);
+return 0;
+}
+
+int smbus_read_byte(I2CBus *bus, uint8_t addr, uint8_t command)
+{
+uint8_t data;
+if (i2c_start_transfer(bus, addr, 0)) {
+return -1;
+}
+i2c_send(bus, command);
+if (i2c_start_transfer(bus, addr, 1)) {
+i2c_end_transfer(bus);
+return -1;
+}
+data = i2c_recv(bus);
+i2c_nack(bus);
+i2c_end_transfer(bus);
+return data;
+}
+
+int smbus_write_byte(I2CBus *bus, uint8_t addr, uint8_t