From: Leo Li
[Why]
display_mode_vba is for DCN2 and up. When building for upstream (DCN1
enabled only), there will be a build error, since display_mode_vba.c/h
is stripped out.
Note that building DCN1 only with internal dal-dev is still fine, since
display_mode_vba.h is not stripped out
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/Kconfig
b/drivers/gpu/drm/amd/display/Kconfig
index 9cb2211edf4c..33e7efbb4ef4
From: hersen wu
Signed-off-by: hersen wu
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
From: Aidan Wood
[Why]
u clk set request was being sent in units of mts, when it needed to be
in units of Mhz
[How]
add a division by 16 to convert from mts to Mhz
Signed-off-by: Aidan Wood
Reviewed-by: Jun Lei
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
From: Wenjing Liu
[why]
Global optic double buffer lock is currently disabled due to
incorrect programming sequence that affects non global lock.
[how]
Isolate global lock programming sequence out of non global lock
programming sequence, so it can be enabled without affecting
non global lock.
From: Eric Yang
[Why]
Some HW specific implementations can be pulled out into clk_mgr.c.
[How]
- Pull get_active_display_cnt out to clk_mgr.
- Pull out shared logic in set_dispclk and set_dprefclk
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Leo Li
Signed-off-by: Alex Deucher
From: Nikola Cornij
[why]
Currently link bandwidth is calculated in various places using the same
multi-step formula. Doing this in one common place makes sure the same
formula will indeed be applied to all link bandwidth calculations.
It also makes it possible to apply link-setting-specific
From: Nikola Cornij
[why] DSC spec requires this
Signed-off-by: Nikola Cornij
Reviewed-by: Wenjing Liu
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git
From: Wenjing Liu
[why]
Clean up some dsc legacy functions that are
no longer needed.
[how]
remove two dsc functions in dc_dsc, use dc_bandwidth_in_kbps_from_timing
instead of calc_required_bandwidth_for_timing.
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Acked-by: Leo Li
From: Aidan Wood
[Why]
If num_states == 0 we did update_bound_box which doesn't updated any max
clocks if num_states == 0, therefore we need to do cap_soc_clocks
instead, also SMU cannot set DCF clock to a higher than or equal to freq
than SOC clock
[How]
Add a num_states != 0 check for
From: Joshua Aberback
[Why]
dcn20_apply_ctx_for_surface can be called with 0 planes, which means we
should blank the display. In this case when we get down to
dcn20_setup_gsl_group_as_lock, pipe_ctx->plane_state is NULL, but we don't
check for it. However, this function is only called by
From: Ilya Bakoulin
[Why]
If voltage level > 0, DCFCLK and SOCCLK could be 0 during DML
calculations, which ended up causing an assert.
[How]
Initialize dcfclk_mhz and socclk_mhz values according to the
voltage level.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Dmytro Laktyushkin
Acked-by:
From: Tony Cheng
Signed-off-by: Tony Cheng
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 5 ++---
2 files changed, 3
From: Leo Li
A previous fix was done for DCN1 that needed to be ported to DCN2:
60c677534e73 ("drm/amd/display: Disconnect mpcc when changing tg")
Signed-off-by: Leo Li
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 7 ---
1
From: hersen wu
[why] we meet a bug when program dsc register even dsc mode is not
enabled. disable dsc config for now. we will re-visit this issue.
Signed-off-by: hersen wu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 9 +
From: Jun Lei
[why]
pstate allow/block is not being handled properly on DCN2
[how]
DML needs to be updated to calculate pstate support at both min and max
mpc combine rather than just min
clock manager needs to update current to new pstate support before
sending to pplib/smu
Signed-off-by: Jun
From: Joshua Aberback
[Why]
VTG has a parameter FP2, which is defined as:
if VSTARTUP is before VSYNC:
FP2 = number of lines in between VSTARTUP and VSYNC
else
FP2 = 0
Currently, FP2 is only programmed during "program_timing". However, the
position of VSTARTUP is affected
From: hersen wu
[todo] need find caller bug. tempooariy fix
Signed-off-by: hersen wu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git
From: Anthony Koo
[Why]
Modern Standby may toggle display adapter state between D0
and D3 state unpredictably.
But events that cause transition to D0 are not always resulting
in a display light up scenario.
Modern eDP panels should be able to power on panel logic
quickly upon VDD going high.
From: Jun Lei
[why]
Current calculation of bounding box will cause DML to increase voltage
state due to DPP or DISPCLK, this is unnecessary since from DML perspective
we can max DPP/DISP can be supported at DPM0. This is because
increasing voltage for DPP/DISP is done separately via actual
From: hersen wu
[WHY] dcn20 enable usb-c dp ALT mode in dmcu. There is bug
when enable abm feature which cause system crash. dal team
will debug this bug later.
[HOW] disable dcn abm feature for dcn20.
Signed-off-by: hersen wu
Signed-off-by: Alex Deucher
---
From: Chris Park
[Why]
link-specific functions should reside in dc_link.c
[How]
Move them there.
Signed-off-by: Chris Park
Reviewed-by: Charlene Liu
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 27 +++
1 file changed, 27
From: Paul Hsieh
[Why]
1. DMCU is not running on some platform but driver still send ABM
command. It may cause assert due to DMCU is not alive.
2. To make sure PSR disable when driver disable
[How]
1. Add dmcu_is_running in ABM struct, driver can check this flag to
determine driver should
From: Eryk Brol
[Why]
In the previous implementation DRR event sometimes came
in during FP2 region which is a keep-out zone. This
would cause the frame not to latch until the next frame
which resulted in heavy flicker. To fix this we need
to make sure that it triggers in the BP.
[How]
1. Remove
From: hersen wu
dc needs get uclk dpm table for bandwidth calculation
Signed-off-by: hersen wu
Acked-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4
1 file changed, 4 insertions(+)
diff --git
From: Harry Wentland
Handle BIOS parsing for DCN2
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 4
drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c | 6 ++
2 files changed, 10 insertions(+)
Pass extra parameter to validate_bandwidth() callback.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
From: Harry Wentland
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/Makefile | 6 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 141 -
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +-
To deal with rebasing the code.
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 21 ---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
From: hersen wu
during bring up time, before window dc-ppplib interface
design, linux dc use raven dc-pplib interface.
now nvai10 dc-pplib-smu interface is changed and verified
under window, navi10 need its specific dc-pplib-smu
interface. todo: hook set_hard_min_uclk_by_freq,
To deal with changes from rebasing.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 +++-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git
From: Harry Wentland
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++
drivers/gpu/drm/amd/amdgpu/nv.c| 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
From: Harry Wentland
Enable DCN2 support in DM (Display Manager).
v2: fix spurious raven change (Alex)
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/Kconfig| 9 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14
From: Harry Wentland
Add support to program the DCN2 OPP (Output Plane Processing)
HW Blocks:
+---+
| OPP |
+---+
|
v
++
| OPTC |
++
|
v
++ ++
| DIO | | DCCG |
From: Harry Wentland
Adding support to program GPIO HW block of DCN2
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
.../display/dc/gpio/dcn20/hw_factory_dcn20.c | 212 ++
From: hersen wu
dc (display component) needs maximum clock values of uclock,
socclk, dcefclk, to calculate display bandwidth.
Signed-off-by: hersen wu
Acked-by: Alex Deucher
Reviewed-by: Huang Rui
---
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 4 +++
From: Harry Wentland
Add support for programming the DCN2 OPTC (Output Timing Controller)
HW Blocks:
++
| OPTC |
++
|
v
++ ++
| DIO | | DCCG |
++ ++
Signed-off-by: Harry Wentland
From: Harry Wentland
Add support to program DCN2 cursor (IPP)
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 24 +++
.../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 43 +++
2 files changed, 67
From: Harry Wentland
Add support to program DCN2 IRQ handling
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +
.../display/dc/irq/dcn20/irq_service_dcn20.c | 361 ++
From: Harry Wentland
DCN2.0 (Display Core Next) is the display block in Navi10.
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/include/dal_asic_id.h | 25 +++
.../gpu/drm/amd/display/include/dal_types.h | 3 +++
2 files changed, 28
Fix UTCL1_CGTT_CLK_CTRL
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index ae3d868de308..779597a6f33a 100644
---
From: Harry Wentland
Add support to program the DCN2 MPC (Multiple pipe and plane combine)
HW Blocks:
++
| MPC |
++
|
v
+---+
| OPP |
+---+
|
v
++
| OPTC |
++
|
v
From: Leo Liu
This is default mode for VCN2.x now
Signed-off-by: Leo Liu
Reviewed-by: James Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
From: Harry Wentland
Adding support to program DCN2 AUX and I2C HW.
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 10 ++
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 32 +++
From: Harry Wentland
Adds support for handling of clocking relevant to the DCN2 block,
including programming of the DCCG (Display Controller Clock Generator)
block:
HW Blocks:
++ ++
| DIO | | DCCG |
++ ++
Signed-off-by: Harry
From: Xiaojie Yuan
Signed-off-by: Xiaojie Yuan
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h | 30 +++
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h
From: Kevin Wang
the uclk dpm feature is not work well on all navi10 asic,
use pp feature mask module parameter to control it.
Signed-off-by: Kevin Wang
Reviewed-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 8 +---
1 file changed, 5
From: Harry Wentland
Add support to program the DCN2 DWB (Display Writeback)
HW Blocks:
+++--+ +--+
| HUBBUB || HUBP | <-- | MMHUBBUB |
+++--+ +--+
| ^
v |
++
From: Harry Wentland
Add support to program the DCN2 MMHUBBUB (Multimedia HUB interface)
HW Blocks:
+++--+ +--+
| HUBBUB || HUBP | <-- | MMHUBBUB |
+++--+ +--+
|
v
++
| DPP |
++
|
From: Harry Wentland
Add support to program the DCN2 HUBP (Display to data fabric interface
pipe) and HUBBUB (DCN memory HUB interface)
HW Blocks:
+++--+
| HUBBUB || HUBP |
+++--+
|
v
++
| DPP |
++
|
v
From: Harry Wentland
Add support for the DIO (Display IO) block of DCN2, which entails our
stream and link encoders.
HW Blocks:
++
| DIO |
++
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 174
From: hersen wu
when dc update clocks via smu, smu needs to know how many
displays active. this interface is for dc notify number
of active displays to smu.
Signed-off-by: hersen wu
Reviewed-by: Huang Rui
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
---
From: Harry Wentland
Add support to program the DCN2 DPP (Multiple pipe and plane combine)
HW Blocks:
++
| DPP |
++
|
v
++
| MPC |
++
|
v
+---+
| OPP |
+---+
|
v
From: Harry Wentland
[WHY]
We don't want to expose sensitive ASIC information before ASIC release.
[HOW]
Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it
at driver load.
v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex)
Signed-off-by: Harry Wentland
From: Jack Xiao
It would hit SMU fw bug without BACO enablement when audio
driver put audio device to D3 state. Before the bug in SMU fw
get fixed, enable BACO feature as WAR.
Signed-off-by: Jack Xiao
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
From: hersen wu
when dc set mode or color format in frame buffer
change, it may request clock changes, like dispclk,
dcfclk, uclk. after smu get clock requests, smu
will make decision.
Signed-off-by: hersen wu
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
From: Harry Wentland
Add support to program DCN2 VMID (Virtual Memory Support)
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c | 62 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h | 91 +++
2 files
From: Leo Li
DC needs to include the soc bounding box when initializing HW resources.
Including amdgpu_ucode.h directly will cause warnings, since amdgpu.h is
required to define amdgpu_device. The solution here is to split the
bounding box structs into a different header, then include it in
From: Marek Olšák
Signed-off-by: Marek Olšák
Reviewed-by: Xiaojie Yuan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
From: tiancyin
Reviewed-by: Jack Xiao
Signed-off-by: tiancyin
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
b/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c
index
From: Kevin Wang
the PPSMC_MSG_SetFanTemperatureTarget is not support on navi10
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 13 -
1 file changed, 13 deletions(-)
diff
Use the SMU_* variant so we look up the correct index.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
From: tiancyin
Signed-off-by: tiancyin
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index
From: Leo Liu
SRAM will be programmed by PSP
Signed-off-by: Leo Liu
Reviewed-by: James Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 3 ++
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 69 ++---
2 files changed, 53 insertions(+), 19
From: Jack Xiao
PSP leverages the existing fw loading function for vcn updating sram.
Signed-off-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 3 +++
2 files changed, 16 insertions(+)
diff
From: Jack Xiao
update the smu11_driver_if_navi10.h since navi10 smu fw
update to 42.23
Signed-off-by: Jack Xiao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
.../powerplay/inc/smu11_driver_if_navi10.h| 24 +++
1 file changed, 14 insertions(+), 10
From: Jack Xiao
SMU FW has bug that it would cause hung when both fw dstate and
gfxoff are enabled at the same time.
Signed-off-by: Jack Xiao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 -
1 file changed, 4 insertions(+), 1
From: Leo Liu
This will be used later for indirect SRAM mode
Signed-off-by: Leo Liu
Reviewed-by: James Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 16
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 6 ++
2 files changed, 22 insertions(+)
Looks like my mail relay has blocked the rest of this series for
sending too many emails. Please see the git link.
Alex
On Mon, Jun 17, 2019 at 3:26 PM Alex Deucher wrote:
>
> Hi,
>
> This patch set adds support for Navi10 asics to amdgpu. This includes
> support for:
> - Core driver support
From: Jack Xiao
PSP leverages the existing fw loading function for vcn updating sram.
Signed-off-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 3 +++
2 files changed, 16 insertions(+)
diff
From: Jack Xiao
PSP supports to program vcn sram by ucode loading interface.
Signed-off-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
From: Jack Xiao
Convert ucode id to the corresponding psp ucode id.
Signed-off-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
From: Jack Xiao
Add VCN RAM ucode id in corresponding to psp ucode id.
Signed-off-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
From: Kevin Wang
the fcuntion thermal_get_temperature will be access SmuMetrics_t data,
the data structure is asic related, so move vega20_ppt to implement.
Signed-off-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 7
From: Tao Zhou
Signed-off-by: Tao Zhou
Acked-by: Alex Deucher
Reviewed-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
From: Kenneth Feng
update the vcn pg function in navi10.
Signed-off-by: Kenneth Feng
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 6 ++
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 14 ++
2 files changed, 16
From: Kevin Wang
the od_settings is asic related data, so move it to asic file.
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 12 --
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 7 +-
From: Kevin Wang
add callback function get_current_activity_percent for navi10 asic
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 20
1 file changed, 20 insertions(+)
diff --git
From: hersen wu
dc needs get uclk dpm table for bandwidth calculation
Signed-off-by: hersen wu
Acked-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 ++
drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 30
From: hersen wu
when dc update clocks via smu, smu needs to know how many
displays active. this interface is for dc notify number
of active displays to smu.
Signed-off-by: hersen wu
Reviewed-by: Huang Rui
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
---
From: Kevin Wang
remove smu callback: get_mclk, get_sclk.
because the function smu_get_dpm_freq_range has the same function.
Signed-off-by: Kevin Wang
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 32 +--
From: Kevin Wang
the function upload_dpm_level is an internal function,
so remove public interface.
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 5
From: Kenneth Feng
enable ac/dc feature on navi10. currently we don't have
the case to verify it.
Signed-off-by: Kenneth Feng
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
From: Kevin Wang
add callback function get_profiling_clk_mask for navi10 asic
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 42 ++
1 file changed, 42 insertions(+)
diff --git
From: Leo Liu
Just for cleanup
Signed-off-by: Leo Liu
Reviewed-by: Alex Deucher
Reviewed-by: James Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 57 +-
1 file changed, 11 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
From: Hawking Zhang
The thermal policy could be ASIC specific ones and depends on structures
in pptable. As a result, get_thermal_temperature_range should be implemented
as ppt funcs instead of smu funcs
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
From: Kevin Wang
enable uclk (mclk) dpm by default on navi10
Signed-off-by: Kevin Wang
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
From: Leo Liu
This is for using SRAM directly
v2: rebase (Alex)
Signed-off-by: Leo Liu
Reviewed-by: Alex Deucher
Reviewed-by: James Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 299 +-
1 file changed, 296 insertions(+), 3 deletions(-)
From: Leo Liu
It will be the default for VCN2.x family
Signed-off-by: Leo Liu
Reviewed-by: Alex Deucher
Reviewed-by: James Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
On 2019-06-17 3:28 p.m., Christian König wrote:
> Am 17.06.19 um 21:15 schrieb Kuehling, Felix:
>> Looks good to me. One cosmetic comment inline. With that fixed this
>> patch is Reviewed-by: Felix Kuehling
>>
>> On 2019-06-14 12:51 p.m., StDenis, Tom wrote:
>>> On 32-bit hosts mem->num_pages is
From: Kevin Wang
the SmuMetrics_t table is asic related data structure.
so move vega20_ppt file to implement.
Signed-off-by: Kevin Wang
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 6 +--
drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 2 +-
From: Kenneth Feng
on navi10, by default the below four features are enabled.
gfxclk deep sleep: enabled and verified
fw dstate: enabled and then soc ulv is verified
dcefclk deep sleep: enabled and verified. notice that on different boards,
due to the minimum dcefclk deep sleep setting in VBIOS,
From: Kevin Wang
the smu mutex lock is unnecessary in smu hw init.
Signed-off-by: Kevin Wang
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
From: Kevin Wang
1.add callback function to support navi10 asic.
2.Remove unnecessary logical code.
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 25 ++
From: Leo Liu
Pause the DPG when not doing decode
Signed-off-by: Leo Liu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 70 +++
1 file changed, 70 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
From: Kevin Wang
add callback function get_gpu_power for navi10 asic
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 19 +++
1 file changed, 19 insertions(+)
diff --git
From: Kevin Wang
use sw-smu clk type name to replace legacy clk type name
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++--
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 16
2 files
From: Kevin Wang
the smu->mutex is internal lock resource in sw-smu, some functions will use
it at the same time, so it maybe will cause deadlock issue.
this patch fix this issue in smu_force_performance_level function.
Signed-off-by: Kevin Wang
Signed-off-by: Alex Deucher
---
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