..@redhat.com>
>> Cc: Ni, Ruiyu <ruiyu...@intel.com>; Tian, Feng <feng.t...@intel.com>;
>> edk2-devel@lists.01.org <edk2-de...@ml01.01.org>;
>> Zeng, Star <star.z...@intel.com>; Ard Biesheuvel <ard.biesheu...@linaro.org>
>> Subject: Re: [
u...@intel.com>; Tian, Feng <feng.t...@intel.com>;
>>> edk2-devel@lists.01.org
><edk2-de...@ml01.01.org>;
>>> Zeng, Star <star.z...@intel.com>; Ard Biesheuvel <ard.biesheu...@linaro.org>
>>> Subject: Re: [edk2] [PATCH v2 2/3] MdeModulePkg/Ser
om>; Tian, Feng <feng.t...@intel.com>;
edk2-devel@lists.01.org <edk2-de...@ml01.01.org>;
Zeng, Star <star.z...@intel.com>; Ard Biesheuvel <ard.biesheu...@linaro.org>
Subject: Re: [edk2] [PATCH v2 2/3] MdeModulePkg/SerialDxe: Set FIFO depth with
PCD
Hi folks,
Please see
..@intel.com>;
>edk2-devel@lists.01.org <edk2-de...@ml01.01.org>;
>Zeng, Star <star.z...@intel.com>; Ard Biesheuvel <ard.biesheu...@linaro.org>
>Subject: Re: [edk2] [PATCH v2 2/3] MdeModulePkg/SerialDxe: Set FIFO depth with
>PCD
>
>Hi folks,
>
>Ple
<ard.biesheu...@linaro.org>; edk2-devel@lists.01.org
><edk2-de...@ml01.01.org>; Heyi Guo <heyi@linaro.org>; Ryan Harkin
><ryan.har...@linaro.org>; Zeng, Star
><star.z...@intel.com>
>Subject: Re: [edk2] [PATCH v2 2/3] MdeModulePkg/SerialDxe: Set FIFO
01.org
Cc: Heyi Guo <heyi@linaro.org>; Tian, Feng <feng.t...@intel.com>; Zeng, Star
<star.z...@intel.com>
Subject: [edk2] [PATCH v2 2/3] MdeModulePkg/SerialDxe: Set FIFO depth with PCD
Set UART receive FIFO depth with PCD instead of fixed number "1".
The default value of P
O setting problem we discussed a few weeks ago.
>>
>>
>>> Thanks
>>> Laszlo
>>>
>>>>
>>>> Regards,
>>>> Ray
>>>>
>>>>
>>>>> -----Original Message-
>>>>> From: edk2-
>>>
>>>
>>>> -Original Message-
>>>> From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of
>>>> Heyi Guo
>>>> Sent: Thursday, March 17, 2016 10:37 PM
>>>> To: edk2-devel@lists.01.org
>>>&g
un...@lists.01.org] On Behalf Of Heyi
>>> Guo
>>> Sent: Thursday, March 17, 2016 10:37 PM
>>> To: edk2-devel@lists.01.org
>>> Cc: Heyi Guo <heyi@linaro.org>; Tian, Feng <feng.t...@intel.com>; Zeng,
>>> Star <star.z...@intel.com>
>&g
m>
>Cc: Tian, Feng <feng.t...@intel.com>; Ard Biesheuvel
><ard.biesheu...@linaro.org>; edk2-devel@lists.01.org
><edk2-de...@ml01.01.org>; Heyi Guo <heyi@linaro.org>; Ryan Harkin
><ryan.har...@linaro.org>; Zeng, Star
><star.z...@intel.com&
devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Heyi
>> Guo
>> Sent: Thursday, March 17, 2016 10:37 PM
>> To: edk2-devel@lists.01.org
>> Cc: Heyi Guo <heyi@linaro.org>; Tian, Feng <feng.t...@intel.com>; Zeng,
>> Star <star.z...@intel.
.com>
>Subject: [edk2] [PATCH v2 2/3] MdeModulePkg/SerialDxe: Set FIFO depth with PCD
>
>Set UART receive FIFO depth with PCD instead of fixed number "1".
>The default value of PCD is also 1, so it makes no difference for
>platforms which do not explicitly set this PCD.
>
&
Set UART receive FIFO depth with PCD instead of fixed number "1".
The default value of PCD is also 1, so it makes no difference for
platforms which do not explicitly set this PCD.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Heyi Guo
Cc: Feng Tian
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