* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED!
*
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
FAILED!
*
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
Hello Alec Roelke,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19828
to look at the new patch set (#2).
Change subject: arch-riscv: Create system file for RISCV FS
Although something here still needs to be virtual...
Gabe
On Wed, Aug 7, 2019 at 6:49 PM Gabe Black wrote:
> Oh, never mind! I'd misunderstood the difference between members and
> children in the clock code. I think things are fine as is! I guess I'm
> still not all the way back from my trip
Oh, never mind! I'd misunderstood the difference between members and
children in the clock code. I think things are fine as is! I guess I'm
still not all the way back from my trip :-).
Gabe
On Wed, Aug 7, 2019 at 6:33 PM Gabe Black wrote:
> You know, after writing that all out, I think maybe
You know, after writing that all out, I think maybe it would be better to
have a generic ClockWatcher interface where something (anything) could
watch a clock source and be notified of period updates. The
DerivedClockDomain would implement that interface, but then so could my
CPU. That would avoid
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19892 )
Change subject: arch-x86: Updating fault condition for write to cr4
..
arch-x86: Updating fault condition for
Hi folks. I'm working on making a CPU model out of a black box CPU
implementation which doesn't explicitly schedule each of its clock ticks (I
assume it does that internally), but does respect a clock which I can
adjust.
The existing clock domain mechanism lets a client call into it to see when
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19891 )
Change subject: mem-ruby: Use check_on_cache_probe on MOESI hammer
..
mem-ruby: Use check_on_cache_probe on
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19908 )
Change subject: mem-ruby: Use check_on_cache_probe on MOESI CMP
..
mem-ruby: Use check_on_cache_probe on MOESI
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19890 )
Change subject: mem-ruby: Use check_on_cache_probe on MOESI
..
mem-ruby: Use check_on_cache_probe on MOESI
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19889 )
Change subject: cpu: Pull more arch specialization to the top of BaseCPU.py.
..
cpu: Pull more arch
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19888 )
Change subject: mem-ruby: Use check_on_cache_probe on MI
..
mem-ruby: Use check_on_cache_probe on MI
This
Pouya Fotouhi has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19868 )
Change subject: mem-ruby: Use check_on_cache_probe to protect locked lines
from eviction
..
mem-ruby: Use
Brandon Potter has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/17112 )
Change subject: sim-se, tests: add a new sim-se test
..
sim-se, tests: add a new sim-se test
This changeset adds a test
Hello kokoro, Ciro Santilli, Giacomo Travaglini, Jason Lowe-Power,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19251
to look at the new patch set (#10).
Change subject: tests: Refactor the Gem5Fixture to derive from UniqueFixture
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19815 )
Change subject: cpu-o3: fix atomic instructions non-speculative
..
cpu-o3: fix atomic instructions non-speculative
Fix
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19814 )
Change subject: cpu-o3: added _amo_op parameter in o3 LSQ
..
cpu-o3: added _amo_op parameter in o3 LSQ
Fix bug with AMO
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19810 )
Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic
instructions
..
arch-arm: Add TypeAtomicOp
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED!
*
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
FAILED!
*
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
Hello kokoro, Ciro Santilli, Giacomo Travaglini, Jason Lowe-Power,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19251
to look at the new patch set (#9).
Change subject: tests: Refactor the Gem5Fixture to derive from UniqueFixture
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19809 )
Change subject: arch-arm: adding register control flags enabling LSE
implementation
..
arch-arm: adding register
Hello Andreas Sandberg, kokoro, Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19810
to look at the new patch set (#4).
Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic
instructions
Hello Andreas Sandberg, Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19811
to look at the new patch set (#6).
Change subject: arch-arm: Adding CAS/CASP AMO instr including new
TypedAtomic func
Hello Andreas Sandberg, kokoro, Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19810
to look at the new patch set (#3).
Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic
instructions
Hello Andreas Sandberg, Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19812
to look at the new patch set (#5).
Change subject: arch-arm: Added LD/ST atomic instruction family and SWP
instrs
Hello Andreas Sandberg, kokoro, Giacomo Travaglini, Anthony Gutierrez,
Jason Lowe-Power,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19814
to look at the new patch set (#7).
Change subject: cpu-o3: added _amo_op parameter in o3
Hello Andreas Sandberg, kokoro,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19809
to look at the new patch set (#3).
Change subject: arch-arm: adding register control flags enabling LSE
implementation
Jordi Vaquero has uploaded a new patch set (#2). (
https://gem5-review.googlesource.com/c/public/gem5/+/19849 )
Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic
instructions
..
arch-arm: Add
Hello Andreas Sandberg, Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19812
to look at the new patch set (#4).
Change subject: arch-arm: Added LD/ST atomic instruction family and SWP
instrs
Hello Andreas Sandberg, Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19811
to look at the new patch set (#4).
Change subject: arch-arm: Adding CAS/CASP AMO instr including new
TypedAtomic func
Jordi Vaquero has uploaded a new patch set (#2). (
https://gem5-review.googlesource.com/c/public/gem5/+/19848 )
Change subject: arch-arm: adding register control flags enabling LSE
implementation
..
arch-arm: adding
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19848 )
Change subject: arch-arm: adding register control flags enabling LSE
implementation
..
arch-arm: adding
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19850 )
Change subject: cpu-o3: fix atomic instructions non-speculative
..
cpu-o3: fix atomic instructions
Jordi Vaquero has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/19849 )
Change subject: arch-arm: Add TypeAtomicOp class to be used by new atomic
instructions
..
arch-arm: Add
Hello Andreas Sandberg, Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19812
to look at the new patch set (#3).
Change subject: arch-arm: Added LD/ST atomic instruction family and SWP
instrs
Hello kokoro, Ciro Santilli, Giacomo Travaglini, Jason Lowe-Power,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19250
to look at the new patch set (#8).
Change subject: tests: Add base class for fixtures that generate a target
Hello kokoro, Ciro Santilli, Giacomo Travaglini, Jason Lowe-Power,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19251
to look at the new patch set (#8).
Change subject: tests: Refactor the Gem5Fixture to derive from UniqueFixture
Hello Andreas Sandberg, Rahul Thakur, kokoro, Giacomo Travaglini, Jason
Lowe-Power,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/18989
to look at the new patch set (#13).
Change subject: tests: Add Arm full system regressions to
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19813 )
Change subject: dev-arm: Perform SMMUv3 CFG Invalidation at device interface
..
dev-arm: Perform SMMUv3 CFG
Daniel Carvalho has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19808 )
Change subject: mem-cache: Fix non-virtual base destructor of Repl Entry
..
mem-cache: Fix non-virtual base destructor
* build/NULL/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby: FAILED!
*
build/NULL_MOESI_hammer/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MOESI_hammer:
FAILED!
*
build/NULL_MESI_Two_Level/tests/opt/quick/se/60.rubytest/null/none/rubytest-ruby-MESI_Two_Level:
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