Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/20088 )
Change subject: sim: Clean up some mild style bugs in clocked_object.hh.
..
sim: Clean up some mild style bugs in clocked_obj
Hello kokoro, Gabe Black, Jason Lowe-Power,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19892
to look at the new patch set (#3).
Change subject: arch-x86: Updating fault condition for write to cr4
...
Hello kokoro, Gabe Black, Jason Lowe-Power,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19892
to look at the new patch set (#2).
Change subject: arch-x86: Updating fault condition for write to cr4
...
Pouya Fotouhi has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19888 )
Change subject: mem-ruby: Use check_on_cache_probe on MI
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mem-ruby: Use check_on_cache_probe on MI
This change uses che
Pouya Fotouhi has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19890 )
Change subject: mem-ruby: Use check_on_cache_probe on MOESI
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mem-ruby: Use check_on_cache_probe on MOESI
This change us
Pouya Fotouhi has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19891 )
Change subject: mem-ruby: Use check_on_cache_probe on MOESI hammer
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mem-ruby: Use check_on_cache_probe on MOESI hammer
Pouya Fotouhi has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19908 )
Change subject: mem-ruby: Use check_on_cache_probe on MOESI CMP
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mem-ruby: Use check_on_cache_probe on MOESI CMP
This c
YIFEI LIU has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/20108 )
Change subject: arch-riscv: Update Page Table Entry
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arch-riscv: Update Page Table Entry
This patch updates the
In x86, a software breakpoint is generally only one byte, the
int3 instruction which is defined for that purpose. It's put at the start
of whatever instruction you want to catch. In other ISAs like ARM which
have different instruction sizes, I'm assuming gdb either figures out what
the size of the
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/20088 )
Change subject: sim: Clean up some mild style bugs in clocked_object.hh.
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sim: Clean up some mild style bugs in
Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/20089 )
Change subject: sim: Add a hook Clocked objects can implement for frequency
changes.
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sim: Add a hook Clocked
Daniel Carvalho has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/20068 )
Change subject: mem-cache: Fix invalid whenReady
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mem-cache: Fix invalid whenReady
When a writeback needs
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19812 )
Change subject: arch-arm: Added LD/ST atomic instruction family and SWP
instrs
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arch-arm: Added LD/ST atomic instruct
Pouya Fotouhi has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19868 )
Change subject: mem-ruby: Use check_on_cache_probe to protect locked lines
from eviction
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mem-ruby: Use check_on_cach
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/20050 )
Change subject: python: FdtState using interrupt-cells
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python: FdtState using interrupt-cells
Change-Id: I3781374
Pouya Fotouhi has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/16809 )
Change subject: mem-ruby: Use check_on_cache_probe to protect locked lines
from eviction
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mem-ruby: Use check_on_cach
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/20053 )
Change subject: dev-arm: Enable DTB autogeneration in GICv3
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dev-arm: Enable DTB autogeneration in GICv3
Change-Id
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/20052 )
Change subject: dev-arm: Fix PCI node's interrupt-map property
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dev-arm: Fix PCI node's interrupt-map property
The
Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/20051 )
Change subject: dev-arm: Use FdtState to generate GIC properites
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dev-arm: Use FdtState to generate GIC properites
Jordi Vaquero has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19811 )
Change subject: arch-arm: Adding CAS/CASP AMO instr including new
TypedAtomic func
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arch-arm: Adding CAS/CASP AMO ins
Brandon Potter has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/20008 )
Change subject: sim-se: rename Process::setpgid member
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sim-se: rename Process::setpgid member
The getter methods to a
Hello Andreas Sandberg, Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/19812
to look at the new patch set (#13).
Change subject: arch-arm: Added LD/ST atomic instruction family and SWP
instrs
Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/20050
to review the following change.
Change subject: python: FdtState using interrupt-cells
..
Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/20053
to review the following change.
Change subject: dev-arm: Enable DTB autogeneration in GICv3
...
Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/20052
to review the following change.
Change subject: dev-arm: Fix PCI node's interrupt-map property
Hello Andreas Sandberg,
I'd like you to do a code review. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/20051
to review the following change.
Change subject: dev-arm: Use FdtState to generate GIC properites
..
Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/20049 )
Change subject: base: assert that stats bucket size is greater than 0
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base: assert that stats bucket size is
Hello Andreas Sandberg, Giacomo Travaglini,
I'd like you to reexamine a change. Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/20048
to look at the new patch set (#2).
Change subject: arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0
...
Ciro Santilli has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/20048 )
Change subject: arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0
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arch-arm, cpu: fix ARM ubsan build on GCC 7.
Andreas Sandberg has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/19931 )
Change subject: misc: Update MAINTAINERS with a system tag
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misc: Update MAINTAINERS with a system tag
The code in s
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