[Intel-gfx] [PATCH v7 4/4] drm/dp: Track MST link bandwidth

From: "Pandiyan, Dhinakaran" Use the added helpers to track MST link bandwidth for atomic modesets. Link bw is acquired in the ->atomic_check() phase when CRTCs are being enabled with drm_atomic_find_vcpi_slots() instead of drm_find_vcpi_slots(). Similarly, link bw

[Intel-gfx] [PATCH v7 1/4] drm: Add driver-private objects to atomic state

From: "Pandiyan, Dhinakaran" It is necessary to track states for objects other than connector, crtc and plane for atomic modesets. But adding objects like DP MST link bandwidth to drm_atomic_state would mean that a non-core object will be modified by the core

[Intel-gfx] [PATCH v7 3/4] drm/dp: Add DP MST helpers to atomically find and release vcpi slots

From: "Pandiyan, Dhinakaran" drm_dp_atomic_find_vcpi_slots() should be called from ->atomic_check() to check there are sufficient vcpi slots for a mode and to add that to the state. This should be followed by a call to drm_dp_mst_allocate_vcpi() in

[Intel-gfx] [PATCH v7 0/4] Adding driver-private objects to atomic state

Changes in this version: Used connector->atomic_check() to release vcpi slots instead of the atomic_release() callback. This series introduces void * type driver-private objects in core and adds helper functions that operate on these private objects. Drivers need to implement object-specific

[Intel-gfx] [PATCH v7 2/4] drm/dp: Introduce MST topology state to track available link bandwidth

From: "Pandiyan, Dhinakaran" Link bandwidth is shared between multiple display streams in DP MST configurations. The DP MST topology manager structure maintains the shared link bandwidth for a primary link directly connected to the GPU. For atomic modesetting

Re: [Intel-gfx] linux-next: build failure after merge of the drm-misc tree

Thanks Stephen. Looks good to me. Logan On 20/04/17 08:10 PM, Stephen Rothwell wrote: > Hi all, > > After merging the drm-misc tree, today's linux-next build (x86_64 > allmodconfig) failed like this: > > drivers/tee/tee_shm.c:87:2: error: unknown field 'kmap_atomic' specified in > initializer

[Intel-gfx] linux-next: build failure after merge of the drm-misc tree

Hi all, After merging the drm-misc tree, today's linux-next build (x86_64 allmodconfig) failed like this: drivers/tee/tee_shm.c:87:2: error: unknown field 'kmap_atomic' specified in initializer .kmap_atomic = tee_shm_op_kmap_atomic, ^ drivers/tee/tee_shm.c:87:17: error: initialization from

[Intel-gfx] ✓ Fi.CI.BAT: success for drm: i915: Don't try detecting sinks on ports already in use

== Series Details == Series: drm: i915: Don't try detecting sinks on ports already in use URL : https://patchwork.freedesktop.org/series/23299/ State : success == Summary == Series 23299v1 drm: i915: Don't try detecting sinks on ports already in use

[Intel-gfx] [PATCH RFC] drm: i915: Don't try detecting sinks on ports already in use

On systems where more than one connector is attached to the same port, the HPD pin is also shared, and attaching one connector will trigger a hotplug on every other connector on that port. But, according to the documentation, connectors sharing the port cannot be enabled simultaneously, such that

Re: [Intel-gfx] [PATCH v6 05/20] drm/i915/tdr: Add support for per engine reset recovery

On 19/04/17 03:49, Chris Wilson wrote: On Tue, Apr 18, 2017 at 01:23:20PM -0700, Michel Thierry wrote: From: Arun Siluvery This change implements support for per-engine reset as an initial, less intrusive hang recovery option to be attempted before falling back

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix pipe/transcoder enum mismatches

== Series Details == Series: drm/i915: Fix pipe/transcoder enum mismatches URL : https://patchwork.freedesktop.org/series/23296/ State : success == Summary == Series 23296v1 drm/i915: Fix pipe/transcoder enum mismatches https://patchwork.freedesktop.org/api/1.0/series/23296/revisions/1/mbox/

[Intel-gfx] [PATCH RESEND] drm/i915: Fix pipe/transcoder enum mismatches

In several instances the driver passes an 'enum pipe' value to a function expecting an 'enum transcoder' and viceversa. Since PIPE_x and TRANSCODER_x have the same values this doesn't cause functional problems. Still it is incorrect and causes clang to generate warnings like this:

Re: [Intel-gfx] [PULL] drm-misc-next-fixes

On Thu, Apr 20, 2017 at 10:11 PM, Sean Paul wrote: > Hi Dave, > A few fixes for you to pick up. The driver changes are trivial, and the > maintainer change was necessitated by the sti fix. The headliner here is the > dma_buf_ops rename, since it touches so many drivers.

[Intel-gfx] [PULL] drm-misc-next-fixes

Hi Dave, A few fixes for you to pick up. The driver changes are trivial, and the maintainer change was necessitated by the sti fix. The headliner here is the dma_buf_ops rename, since it touches so many drivers. Everything looks sane and builds with that change, so it shouldn't cause problems.

Re: [Intel-gfx] freedesktop bug id: 100548, bisected to sched/clock commit

On Thu, Apr 20, 2017 at 07:19:50PM +0200, Peter Zijlstra wrote: > Just for my sanity, could you confirm "tsc=unstable" (which requires the > patch) actually works for you? Also, could you get me the dmesg of a 'broken' boot? ___ Intel-gfx mailing list

Re: [Intel-gfx] [PATCH v6 13/20] drm/i915/guc: Provide register list to be saved/restored during engine reset

On 20/04/17 09:39, Daniele Ceraolo Spurio wrote: On 20/04/17 04:33, Joonas Lahtinen wrote: On ke, 2017-04-19 at 11:35 -0700, Michel Thierry wrote: From: Arun Siluvery GuC expects a list of registers from the driver which are saved/restored during engine

Re: [Intel-gfx] freedesktop bug id: 100548, bisected to sched/clock commit

On Tue, Apr 18, 2017 at 05:53:56PM +0200, Peter Zijlstra wrote: > On Tue, Apr 18, 2017 at 02:10:07PM +, Lofstedt, Marta wrote: > > Sorry Peter, I still see regression on the Core2 machine, with your patch. > > > > Blergh, ok. I'll see if I can dig out an actual Core2 machine somewhere. > I

Re: [Intel-gfx] [PATCH v6 18/20] drm/i915: Watchdog timeout: DRM kernel interface to set the timeout

On 20/04/17 01:52, Chris Wilson wrote: On Wed, Apr 19, 2017 at 06:09:00PM -0700, Michel Thierry wrote: This patch is missing: diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index c1013af0b910..a8bdea43a217 100644 ---

Re: [Intel-gfx] [PATCH v6 13/20] drm/i915/guc: Provide register list to be saved/restored during engine reset

On 20/04/17 04:33, Joonas Lahtinen wrote: On ke, 2017-04-19 at 11:35 -0700, Michel Thierry wrote: From: Arun Siluvery GuC expects a list of registers from the driver which are saved/restored during engine reset. The type of value to be saved is controlled by

Re: [Intel-gfx] [PATCH i-g-t v4] benchmarks/gem_wsim: Command submission workload simulator

On Thu, Apr 20, 2017 at 01:29:11PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > +static void > +run_workload(unsigned int id, struct workload *wrk, unsigned int repeat, > + enum intel_engine_id (*balance)(struct workload *wrk, > +

Re: [Intel-gfx] [PATCH i-g-t v4] benchmarks/gem_wsim: Command submission workload simulator

On Thu, Apr 20, 2017 at 03:34:56PM +0100, Tvrtko Ursulin wrote: > > On 20/04/2017 15:23, Chris Wilson wrote: > >On Thu, Apr 20, 2017 at 01:29:11PM +0100, Tvrtko Ursulin wrote: > >>+static void > >>+alloc_step_batch(struct workload *wrk, struct w_step *w, struct w_step_eb > >>*b, > >>+

Re: [Intel-gfx] [PATCH i-g-t v4] benchmarks/gem_wsim: Command submission workload simulator

On 20/04/2017 15:52, Chris Wilson wrote: On Thu, Apr 20, 2017 at 01:29:11PM +0100, Tvrtko Ursulin wrote: + wrk->nr_bb[engine]++; + + if (engine == VCS && balance) { + engine = balance(wrk, w); +

Re: [Intel-gfx] [PATCH 13/27] drm/i915/execlists: Pack the count into the low bits of the port.request

On 19/04/2017 10:41, Chris Wilson wrote: add/remove: 1/1 grow/shrink: 5/4 up/down: 391/-578 (-187) function old new delta execlists_submit_ports 262 471+209 port_assign.isra - 136+136

Re: [Intel-gfx] [PATCH i-g-t v4] benchmarks/gem_wsim: Command submission workload simulator

On Thu, Apr 20, 2017 at 01:29:11PM +0100, Tvrtko Ursulin wrote: > + wrk->nr_bb[engine]++; > + > + if (engine == VCS && balance) { > + engine = balance(wrk, w); > + wrk->nr_bb[engine]++; > +

Re: [Intel-gfx] [PATCH v4] drm: Add DPCD definitions for DP 1.4 DSC feature

On Tue, 04 Apr 2017, Manasi Navare wrote: > From: "Navare, Manasi D" > > Display stream compression is supported on DP 1.4 DP > devices. This patch adds the corersponding DPCD > register definitions for DSC. > > v4: > * Add DSC Enable DPCD

Re: [Intel-gfx] [PATCH i-g-t v4] benchmarks/gem_wsim: Command submission workload simulator

On 20/04/2017 15:33, Chris Wilson wrote: On Thu, Apr 20, 2017 at 03:23:27PM +0100, Chris Wilson wrote: You either want to reset presumed_offset=-1 each time, or better for all concerned write the correct address alongside the seqno (which also enables NORELOC). Delta incoming. See attached.

Re: [Intel-gfx] [PATCH i-g-t v4] benchmarks/gem_wsim: Command submission workload simulator

On 20/04/2017 15:23, Chris Wilson wrote: On Thu, Apr 20, 2017 at 01:29:11PM +0100, Tvrtko Ursulin wrote: +static void +alloc_step_batch(struct workload *wrk, struct w_step *w, struct w_step_eb *b, +enum intel_engine_id engine, unsigned int flags) +{ + unsigned int bb_i, j

Re: [Intel-gfx] [PATCH i-g-t v4] benchmarks/gem_wsim: Command submission workload simulator

On Thu, Apr 20, 2017 at 03:23:27PM +0100, Chris Wilson wrote: > You either want to reset presumed_offset=-1 each time, or better for all > concerned write the correct address alongside the seqno (which also > enables NORELOC). > > Delta incoming. See attached. Next concern is that I have full

Re: [Intel-gfx] [PATCH i-g-t v4] benchmarks/gem_wsim: Command submission workload simulator

On Thu, Apr 20, 2017 at 01:29:11PM +0100, Tvrtko Ursulin wrote: > +static void > +alloc_step_batch(struct workload *wrk, struct w_step *w, struct w_step_eb *b, > + enum intel_engine_id engine, unsigned int flags) > +{ > + unsigned int bb_i, j = 0; > + > + b->obj[j].handle =

Re: [Intel-gfx] [PATCH 12/27] drm/i915: Only report a wakeup if the waiter was truly asleep

On Thu, Apr 20, 2017 at 02:30:21PM +0100, Tvrtko Ursulin wrote: > > On 19/04/2017 10:41, Chris Wilson wrote: > >If we attempt to wake up a waiter, who is currently checking the seqno > >it will be in the TASK_INTERRUPTIBLE state and ttwu will report success. > >However, it is actually awake and

Re: [Intel-gfx] [PATCH 12/27] drm/i915: Only report a wakeup if the waiter was truly asleep

On 19/04/2017 10:41, Chris Wilson wrote: If we attempt to wake up a waiter, who is currently checking the seqno it will be in the TASK_INTERRUPTIBLE state and ttwu will report success. However, it is actually awake and functioning -- so delay reporting the actual wake up until it sleeps. v2:

[Intel-gfx] [PATCH i-g-t v4] benchmarks/gem_wsim: Command submission workload simulator

From: Tvrtko Ursulin Tool which emits batch buffers to engines with configurable sequences, durations, contexts, dependencies and userspace waits. Unfinished but shows promise so sending out for early feedback. v2: * Load workload descriptors from files. (also -w) *

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Use discardable buffers for rings

On Thu, Apr 20, 2017 at 10:49:37AM -, Patchwork wrote: > == Series Details == > > Series: drm/i915: Use discardable buffers for rings > URL : https://patchwork.freedesktop.org/series/23274/ > State : failure > > == Summary == > > Series 23274v1 drm/i915: Use discardable buffers for rings

Re: [Intel-gfx] [PATCH v6 13/20] drm/i915/guc: Provide register list to be saved/restored during engine reset

On ke, 2017-04-19 at 11:35 -0700, Michel Thierry wrote: > From: Arun Siluvery > > GuC expects a list of registers from the driver which are saved/restored > during engine reset. The type of value to be saved is controlled by > flags. We provide a minimal set of

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Use discardable buffers for rings

== Series Details == Series: drm/i915: Use discardable buffers for rings URL : https://patchwork.freedesktop.org/series/23274/ State : failure == Summary == Series 23274v1 drm/i915: Use discardable buffers for rings https://patchwork.freedesktop.org/api/1.0/series/23274/revisions/1/mbox/

Re: [Intel-gfx] [PATCH i-g-t 03/13] lib/igt_aux: Include unistd.h for gettid() on Android

On Wed, Apr 19, 2017 at 05:23:46PM +0300, Jani Nikula wrote: > On Wed, 19 Apr 2017, Arkadiusz Hiler wrote: > > On Wed, Apr 19, 2017 at 03:22:19PM +0300, Jani Nikula wrote: > >> On Wed, 19 Apr 2017, Arkadiusz Hiler wrote: > >> > We define

Re: [Intel-gfx] [PATCH] drm/i915: Use discardable buffers for rings

On to, 2017-04-20 at 11:17 +0100, Chris Wilson wrote: > The contents of a ring are only valid between HEAD and TAIL, when the > ring is idle (HEAD == TAIL) we can simply let the pages go under memory > pressue if they are not pinned by an active context. And new content > will be written and so

Re: [Intel-gfx] [PATCH i-g-t 08/13] benchmarks/Android.mk: Add gem_latency to skip list

On Wed, Apr 19, 2017 at 05:58:28PM +0100, Chris Wilson wrote: > On Wed, Apr 19, 2017 at 01:01:50PM +0200, Arkadiusz Hiler wrote: > > AOSP, as of this commit, does not include libdrm with fence defines. > > Pushed local defines that should keep the benchmark happy. > > Please do reset the

[Intel-gfx] [PATCH] drm/i915: Use discardable buffers for rings

The contents of a ring are only valid between HEAD and TAIL, when the ring is idle (HEAD == TAIL) we can simply let the pages go under memory pressue if they are not pinned by an active context. And new content will be written and so the ring will again be valid between HEAD and TAIL, everything

Re: [Intel-gfx] [i-g-t PATCH v4 1/2] lib/igt_kms: Add support for 4K and audio HDMI EDID injection.

On 19.04.2017 11:13, Petri Latvala wrote: > > The only Intel-specific part I can spot is that one chunk where you > check for at-least-hsw. Is that so you can properly report skip > instead of fail? It would be good to make this all suitable for > non-Intel hw. > That is meant to report skip

Re: [Intel-gfx] [PATCH v6 14/20] drm/i915/guc: Add support for reset engine using GuC commands

On Wed, Apr 19, 2017 at 04:22:43PM -0700, Michel Thierry wrote: > On 19/04/17 03:27, Chris Wilson wrote: > >On Tue, Apr 18, 2017 at 01:23:29PM -0700, Michel Thierry wrote: > >>This patch adds per engine reset and recovery (TDR) support when GuC is > >>used to submit workloads to GPU. > >> > >>In

Re: [Intel-gfx] [PATCH 14/27] drm/i915: Don't mark an execlists context-switch when idle

On ke, 2017-04-19 at 10:41 +0100, Chris Wilson wrote: > If we *know* that the engine is idle, i.e. we have not more contexts in > lift, we can skip any spurious CSB idle interrupts. These spurious in flight? > interrupts seem to arrive long after we assert that the engines are > completely idle,

Re: [Intel-gfx] [PATCH v6 18/20] drm/i915: Watchdog timeout: DRM kernel interface to set the timeout

On Wed, Apr 19, 2017 at 06:09:00PM -0700, Michel Thierry wrote: > This patch is missing: > > diff --git a/drivers/gpu/drm/i915/i915_gem_context.c > b/drivers/gpu/drm/i915/i915_gem_context.c > index c1013af0b910..a8bdea43a217 100644 > --- a/drivers/gpu/drm/i915/i915_gem_context.c > +++

Re: [Intel-gfx] [PATCH 22/27] drm/i915: Eliminate lots of iterations over the execobjects array

On ke, 2017-04-19 at 10:41 +0100, Chris Wilson wrote: > The major scaling bottleneck in execbuffer is the processing of the > execobjects. Creating an auxiliary list is inefficient when compared to > using the execobject array we already have allocated. > > Reservation is then split into phases.

Re: [Intel-gfx] [PATCH v4 6/9] drm/i915: Convert intel_dp properties to atomic.

On 19-04-17 17:53, Daniel Vetter wrote: > On Wed, Apr 12, 2017 at 12:50:04PM +0200, Maarten Lankhorst wrote: >> intel_dp supports 3 properties, scaling mode, broadcast rgb and >> force_audio. intel_digital_connector handles the plumbing, >> so we only have to hook this up in compute_config and

Re: [Intel-gfx] [PATCH v2] dma-buf: Rename dma-ops to prevent conflict with kunmap_atomic macro

Hi All, On 2017-04-20 09:51, Daniel Vetter wrote: On Wed, Apr 19, 2017 at 01:36:10PM -0600, Logan Gunthorpe wrote: Seeing the kunmap_atomic dma_buf_ops share the same name with a macro in highmem.h, the former can be aliased if any dma-buf user includes that header. I'm personally trying to

[Intel-gfx] [i-g-t PATCH 2/4] igt/igt_core: Provide an option to check for the log buffer contents

Signed-off-by: Abdiel Janulgue --- lib/igt_core.c | 24 lib/igt_core.h | 3 +++ 2 files changed, 27 insertions(+) diff --git a/lib/igt_core.c b/lib/igt_core.c index 8a7ba0d..e80a32a 100644 --- a/lib/igt_core.c +++ b/lib/igt_core.c @@

[Intel-gfx] [i-g-t PATCH 3/4] lib/igt_debugfs: Add helper to return path to device.

Signed-off-by: Abdiel Janulgue --- lib/igt_debugfs.c | 26 ++ lib/igt_debugfs.h | 1 + 2 files changed, 27 insertions(+) diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c index 7584be5..b019c3b 100644 --- a/lib/igt_debugfs.c +++

[Intel-gfx] [i-g-t PATCH 1/4] lib/igt_core: Add igt_exec helpers

Support executing external processes with the goal of capturing its standard streams to the igt logging infrastructure in addition to its exit status. Cc: Daniel Vetter Cc: Petri Latvala Signed-off-by: Abdiel Janulgue

[Intel-gfx] [i-g-t PATCH 4/4] Convert shell script tests to C version

Converted: - check_drm_clients (ensures no other clients are running. functionality provided by drm_open_driver_master). - debugfs_emon_crash - debugfs_wedged - drv_debugfs_reader - sysfs_l3_parity - test_rte_check (same as check_drm_clients) - tools_test - ZZ_check_dmesg Cc: Daniel

Re: [Intel-gfx] [PATCH v2] dma-buf: Rename dma-ops to prevent conflict with kunmap_atomic macro

Hi Marek, Thanks! On 20 April 2017 at 13:36, Marek Szyprowski wrote: > Hi All, > > On 2017-04-20 09:51, Daniel Vetter wrote: >> >> On Wed, Apr 19, 2017 at 01:36:10PM -0600, Logan Gunthorpe wrote: >>> >>> Seeing the kunmap_atomic dma_buf_ops share the same name with a

Re: [Intel-gfx] [PATCH v2] dma-buf: Rename dma-ops to prevent conflict with kunmap_atomic macro

Hi Logan, Thanks for the patch. On 20 April 2017 at 13:21, Daniel Vetter wrote: > On Wed, Apr 19, 2017 at 01:36:10PM -0600, Logan Gunthorpe wrote: >> Seeing the kunmap_atomic dma_buf_ops share the same name with a macro >> in highmem.h, the former can be aliased if any dma-buf

Re: [Intel-gfx] [PATCH v2] dma-buf: Rename dma-ops to prevent conflict with kunmap_atomic macro

On Wed, Apr 19, 2017 at 01:36:10PM -0600, Logan Gunthorpe wrote: > Seeing the kunmap_atomic dma_buf_ops share the same name with a macro > in highmem.h, the former can be aliased if any dma-buf user includes > that header. > > I'm personally trying to include highmem.h inside scatterlist.h and

Re: [Intel-gfx] [PATCH 01/27] drm/i915/selftests: Allocate inode/file dynamically

On ke, 2017-04-19 at 10:41 +0100, Chris Wilson wrote: > Avoid having too large a stack by creating the fake struct inode/file on > the heap instead. > > drivers/gpu/drm/i915/selftests/mock_drm.c: In function 'mock_file': > drivers/gpu/drm/i915/selftests/mock_drm.c:46:1: error: the frame size of

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/scheduler: add gvt force-single-submission and notification for guc (rev4)

== Series Details == Series: drm/i915/scheduler: add gvt force-single-submission and notification for guc (rev4) URL : https://patchwork.freedesktop.org/series/21972/ State : success == Summary == Series 21972v4 drm/i915/scheduler: add gvt force-single-submission and notification for guc

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/scheduler: add gvt force-single-submission and notification for guc (rev4)

Hi, > == Series Details == > > Series: drm/i915/scheduler: add gvt force-single-submission and notification > for guc (rev4) > URL : https://patchwork.freedesktop.org/series/21972/ > State : failure > > == Summary == > > Series 21972v4 drm/i915/scheduler: add gvt force-single-submission and

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/scheduler: add gvt force-single-submission and notification for guc (rev4)

== Series Details == Series: drm/i915/scheduler: add gvt force-single-submission and notification for guc (rev4) URL : https://patchwork.freedesktop.org/series/21972/ State : failure == Summary == Series 21972v4 drm/i915/scheduler: add gvt force-single-submission and notification for guc

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/scheduler: add gvt force-single-submission and notification for guc (rev4)

Hi, > == Series Details == > > Series: drm/i915/scheduler: add gvt force-single-submission and notification > for guc (rev4) > URL : https://patchwork.freedesktop.org/series/21972/ > State : failure > > == Summary == > > Series 21972v4 drm/i915/scheduler: add gvt force-single-submission and

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/scheduler: add gvt force-single-submission and notification for guc (rev4)

> -Original Message- > From: Saarinen, Jani > Sent: Thursday, April 20, 2017 2:30 PM > To: intel-gfx@lists.freedesktop.org; Dong, Chuanxiao > > Subject: RE: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/scheduler: add gvt > force-single-submission and

Re: [Intel-gfx] [PATCH v4 2/9] drm/i915: Add plumbing for digital connector state, v2.

On 19-04-17 17:48, Daniel Vetter wrote: > On Wed, Apr 12, 2017 at 12:50:00PM +0200, Maarten Lankhorst wrote: >> Some atomic properties are common between the various kinds of >> connectors, for example a lot of them use panel fitting mode. >> It makes sense to put a lot of it in a common place, so

[Intel-gfx] [RESEND][GIT PULL] GVT-g next fixes for 4.12

Hi, Please pull gvt next fixes for 4.12. (resend with subscribed mail address.) Thanks. -- The following changes since commit b35f34d1da4e77637869c8041a355da810f69fb6: drm/i915/gvt: control the scheduler by timeslice usage (2017-03-30 13:34:10 +0800) are available in the git repository