Since writing the comment that the scheduler is entirely passive, we've
added minimal timeslicing which adds the most primitive of active
elements (a timeout and reschedule).
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Ramalingam C
---
drivers/gpu/drm/i915/i915_scheduler_types.h | 9 +++
Sometimes we want to emit a terminator request, a request that flushes
the pipeline and allows no request to come after it. This can be used
for a "preempt-to-idle" to ensure that upon processing the
context-switch to that request, all other active contexts have been
flushed.
Signed-off-by: Chris
To flush idle barriers, and even inflight requests, we want to send a
preemptive 'pulse' along an engine. We use a no-op request along the
pinned kernel_context at high priority so that it should run or else
kick off the stuck requests. We can use this to ensure idle barriers are
immediately flushe
Replace sampling the engine state every so often with a periodic
heartbeat request to measure the health of an engine. This is coupled
with the forced-preemption to allow long running requests to survive so
long as they do not block other users.
The heartbeat interval can be adjusted per-engine us
On completion of a banned context, scrub the context image so that we do
not replay the active payload. The intent is that we skip banned
payloads on request submission so that the timeline advancement
continues on in the background. However, if we are returning to a
preempted request, i915_request
If the preempted context takes too long to relinquish control, e.g. it
is stuck inside a shader with arbitration disabled, evict that context
with an engine reset. This ensures that preemptions are reasonably
responsive, providing a tighter QoS for the more important context at
the cost of flagging
Normally, we rely on our hangcheck to prevent persistent batches from
hogging the GPU. However, if the user disables hangcheck, this mechanism
breaks down. Despite our insistence that this is unsafe, the users are
equally insistent that they want to use endless batches and will disable
the hangchec
Preliminary stub to add engines underneath /sys/class/drm/cardN/, so
that we can expose properties on each engine to the sysadmin.
To start with we have basic analogues of the i915_query ioctl so that we
can pretty print engine discovery from the shell, and flesh out the
directory structure. Later
Before we BUG out with bad pending state, leave a telltale as to which
test failed.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 30 -
drivers/gpu/drm/i915/i915_gem.h | 8
2 files changed, 2
If we do find ourselves with an idle barrier inside our active while
waiting, attempt to flush it by emitting a pulse using the kernel
context.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_engine_heartbeat.c | 14 +
.../gpu/drm/i915/gt/intel_engine_heartbeat.h | 1 +
From: Lionel Landwerlin
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine. For now, we want to
pull the knowledge of which engine we use into a central property.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_p
Now that we have the engine stored in i915_perf, we have a means of
accessing intel_gt should we require it. However, we are currently only
using the intel_gt to find the right intel_uncore, so replace our
i915_perf.gt pointer with the more useful i915_perf.uncore.
Signed-off-by: Chris Wilson
Cc:
Sanity test existing persistence and new exciting non-persistent context
behaviour.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Michał Winiarski
Cc: Jon Bloomfield
Cc: Tvrtko Ursulin
Cc: Andi Shyti
---
lib/i915/gem_context.c | 37 +++
lib/i915/gem_context.h |
Update to commit fef476f3ab47527a00818ddaf4b46b8c0936 (not upstream!)
Author: Chris Wilson
Date: Mon Aug 5 22:55:44 2019 +0100
drm/i915: Cancel non-persistent contexts on close
for I915_CONTEXT_PARAM_PERSISTENCE
---
include/drm-uapi/i915_drm.h | 22 --
1 file chang
On 10/10/2019 04:02, Daniele Ceraolo Spurio wrote:
> Add a short description of what we expect from GuC and some minor
> improvements to existing documentation. Also remove a comment about a
> difference between GuC and HuC that is not true anymore.
>
> v2: add that the GuC is not mandatory (Marti
== Series Details ==
Series: series starting with [01/10] drm/i915: Note the addition of timeslicing
to the pretend scheduler
URL : https://patchwork.freedesktop.org/series/67827/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cdd8a8ed5e08 drm/i915: Note the addition of timesli
Move the BUG_ON around slightly and add some explanations for each to
try and capture the expected state more carefully. We want to compare
the expected active state of our bookkeeping as compared to the tracked
HW state.
References: https://bugs.freedesktop.org/show_bug.cgi?id=111937
Signed-off-b
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Move SAGV block time to
dev_priv (rev2)
URL : https://patchwork.freedesktop.org/series/67799/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14733_full
=
== Series Details ==
Series: series starting with [01/10] drm/i915: Note the addition of timeslicing
to the pretend scheduler
URL : https://patchwork.freedesktop.org/series/67827/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7047 -> Patchwork_14742
==
Quoting Daniele Ceraolo Spurio (2019-10-10 00:04:23)
> The specs don't mention any specific HW limitation on the blitter and
> manual inspection shows that the HW does set the relative MMIO bit in
> the LRI of the blitter context image, so we can remove our limitations.
I concur, the HW itself set
Quoting Daniele Ceraolo Spurio (2019-10-10 00:04:24)
> There are small differences between the blitter and the video engines in
> the xcs context image (e.g. registers 0x200 and 0x204 only exist on the
> blitter). Since we never explicitly set a value for those register and
> given that we don't ne
== Series Details ==
Series: series starting with [1/2] drm/i915/perf: store the associated engine
of a stream
URL : https://patchwork.freedesktop.org/series/67828/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7047 -> Patchwork_14743
=
Quoting Patchwork (2019-10-10 03:08:10)
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915/tgl: the BCS engine supports
> relative MMIO
> URL : https://patchwork.freedesktop.org/series/67809/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7046 ->
On 2019/9/25 上午7:06, Alex Williamson wrote:
On Tue, 24 Sep 2019 21:53:30 +0800
Jason Wang wrote:
This patch implements basic support for mdev driver that supports
virtio transport for kernel virtio driver.
Signed-off-by: Jason Wang
---
include/linux/mdev.h| 2 +
include/linux/vi
== Series Details ==
Series: drm/i915/execlists: Leave tell-tales as to why pending[] is bad (rev2)
URL : https://patchwork.freedesktop.org/series/67786/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14734_full
===
On Wed, 09 Oct 2019, "Ruhl, Michael J" wrote:
>>-Original Message-
>>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>>Jani Nikula
>>+/* Helper for struct drm_device based logging. */
>>+#define __drm_printk(drm, level, type, fmt, ...) \
>
Hi Chris,
On Wednesday, October 2, 2019 6:00:34 PM CEST Chris Wilson wrote:
> If we have a wedged GPU that we need to recover, but fail, add a taint
> for CI to pickup and schedule a reboot.
As your approach has been chosen by CI, FWIW:
Reviewed-by: Janusz Krzysztofik
Thanks,
Janusz
>
> Sign
On 10/10/2019 04:02, Daniele Ceraolo Spurio wrote:
> Better explain the usage of the microcontroller and what i915 is
> responsible of. While at it, fix the documentation for the auth
> function, which doesn't do any pinning anymore.
>
> v2: add a comment on HuC being optional and descrive how HuC
== Series Details ==
Series: Gen12 E2E compression (rev3)
URL : https://patchwork.freedesktop.org/series/67078/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a2306a44f000 drm/framebuffer: Format modifier for Intel Gen-12 render
compression
7fceadb0dd8f drm/i915: Use intel_tile
== Series Details ==
Series: series starting with [1/9] drm/i915/perf: store the associated engine
of a stream
URL : https://patchwork.freedesktop.org/series/67804/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14736_full
===
Make sure that we copy across the registers from one engine to the next,
as we hop around a virtual engine.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 176 +
1 file changed, 176 insertions(+)
diff --git a/drivers/gpu/drm/
== Series Details ==
Series: Gen12 E2E compression (rev3)
URL : https://patchwork.freedesktop.org/series/67078/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7049 -> Patchwork_14744
Summary
---
**FAILURE**
Serious
On 09-Oct-19 7:46 PM, Ville Syrjälä wrote:
On Wed, Oct 09, 2019 at 12:25:41PM +0530, Swati Sharma wrote:
For icl+, have hw read out to create hw blob of gamma
lut values. icl+ platforms supports multi segmented gamma
mode by default, add hw lut creation for this mode.
This will be used to valid
Quoting Chris Wilson (2019-10-10 11:36:57)
> Make sure that we copy across the registers from one engine to the next,
> as we hop around a virtual engine.
Looking at Broadwell's HW context image, there are no GPR registers for
xcs. Weird.
-Chris
___
Inte
Make sure that we copy across the registers from one engine to the next,
as we hop around a virtual engine.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
Skip the test on gen8 as the context image is devoid of CS_GPR.
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 180 +++
Hi Dave, Daniel,
Here's this week drm-misc-fixes PR, dealing mostly with SPI probing
related issues.
Maxime
drm-misc-fixes-2019-10-10:
Short summary of fixes pull (less than what git shortlog provides):
- SPI Aliases fixes for panels
- One fix for the tc358767 bridge dealing with visual artifact
== Series Details ==
Series: drm/dp-mst: Drop connection_mutex check
URL : https://patchwork.freedesktop.org/series/67807/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14738_full
Summary
---
*
== Series Details ==
Series: drm/i915/execlists: Mark up expected state during reset
URL : https://patchwork.freedesktop.org/series/67830/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7050 -> Patchwork_14745
Summary
--
Op 08-10-2019 om 19:03 schreef Ville Syrjälä:
> On Fri, Oct 04, 2019 at 01:34:57PM +0200, Maarten Lankhorst wrote:
>> Use this in all the places where we try to acquire planes after the planes
>> atomic_check().
>>
>> In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
>>
== Series Details ==
Series: series starting with [1/2] drm/i915/tgl: the BCS engine supports
relative MMIO
URL : https://patchwork.freedesktop.org/series/67809/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14739_full
==
== Series Details ==
Series: drm/i915/selftests: Check that registers are preserved between virtual
engines (rev2)
URL : https://patchwork.freedesktop.org/series/67837/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7050 -> Patchwork_14746
=
Make sure that we copy across the registers from one engine to the next,
as we hop around a virtual engine.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 180 +
1 file changed, 180 insertions(+)
diff --git a/drivers/gpu/drm/
Check the logical ring context by asserting that the registers hold
expected start during execution. (It's a bit chicken-and-egg for how
could we manage to execute our request if the registers were not being
updated. Still, it's nice to verify that the HW is working as expected.)
Signed-off-by: Ch
Op 07-10-2019 om 21:37 schreef Matt Roper:
> On Fri, Oct 04, 2019 at 01:34:54PM +0200, Maarten Lankhorst wrote:
>> We have a src and dect rectangle, use it instead of relying on
>> the core drm properties.
>>
>> This removes the special case in the watermark code for cursor w/h.
>>
>> Signed-off-by
On 10/10/2019 12:02, Chris Wilson wrote:
Make sure that we copy across the registers from one engine to the next,
as we hop around a virtual engine.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
Skip the test on gen8 as the context image is devoid of CS_GPR.
---
drivers/gpu/drm/i915/gt
Hi guys,
Any feedback on the below?
On 06/09/2019 16:47, Tvrtko Ursulin wrote:
Peter, Thomas,
If you could spare a moment for some brainstorming on the topic of
uncore PMU and multiple providers it would be appreciated.
So from i915 we export some metrics as uncore PMU, which shows up und
On Thu, Oct 10, 2019 at 01:56:42PM +0200, Maarten Lankhorst wrote:
> Op 08-10-2019 om 19:03 schreef Ville Syrjälä:
> > On Fri, Oct 04, 2019 at 01:34:57PM +0200, Maarten Lankhorst wrote:
> >> Use this in all the places where we try to acquire planes after the planes
> >> atomic_check().
> >>
> >> In
Op 08-10-2019 om 21:40 schreef Ville Syrjälä:
> On Fri, Oct 04, 2019 at 01:35:05PM +0200, Maarten Lankhorst wrote:
>> When the clock is higher than the dotclock, try with 2 pipes enabled.
>> If we can enable 2, then we will go into big joiner mode, and steal
>> the adjacent crtc.
>>
>> This only li
Chris Wilson writes:
> Move the BUG_ON around slightly and add some explanations for each to
> try and capture the expected state more carefully. We want to compare
> the expected active state of our bookkeeping as compared to the tracked
> HW state.
>
> References: https://bugs.freedesktop.org/s
Hi Jani,
During plumbers I had some discussions with Daniel about supporting
OLED screens. Userspace may need to know that a panel is OLED for 2
reasons:
1) To avoid screen burn-in
2) OLED screens do not have a classic backlight, so in some cases
some sort of brightness/contrast emulation throug
Quoting Tvrtko Ursulin (2019-10-10 13:31:04)
>
> On 10/10/2019 12:02, Chris Wilson wrote:
> > Make sure that we copy across the registers from one engine to the next,
> > as we hop around a virtual engine.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Tvrtko Ursulin
> > ---
> > Skip the test on g
== Series Details ==
Series: series starting with [v2,1/3] drm/i915: Add microcontrollers
documentation section
URL : https://patchwork.freedesktop.org/series/67810/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14740_full
==
Op 10-10-2019 om 14:39 schreef Ville Syrjälä:
> On Thu, Oct 10, 2019 at 01:56:42PM +0200, Maarten Lankhorst wrote:
>> Op 08-10-2019 om 19:03 schreef Ville Syrjälä:
>>> On Fri, Oct 04, 2019 at 01:34:57PM +0200, Maarten Lankhorst wrote:
Use this in all the places where we try to acquire planes a
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Check that registers are
preserved between virtual engines
URL : https://patchwork.freedesktop.org/series/67843/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7051 -> Patchwork_14747
=
Check the logical ring context by asserting that the registers hold
expected start during execution. (It's a bit chicken-and-egg for how
could we manage to execute our request if the registers were not being
updated. Still, it's nice to verify that the HW is working as expected.)
Signed-off-by: Ch
We want the general purpose registers to be clear in all new contexts so
that we can be confident that no information is leaked from one to the
next.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 185 ++---
1 file changed, 166 in
Quoting Chris Wilson (2019-10-10 14:15:21)
> +static int __live_gpr_clear(struct i915_gem_context *fixme,
> + struct intel_engine_cs *engine,
> + struct i915_vma *scratch)
> +{
> + struct intel_context *ce;
> + struct i915_request *rq;
On Thu, 10 Oct 2019, Hans de Goede wrote:
> Hi Jani,
>
> During plumbers I had some discussions with Daniel about supporting
> OLED screens. Userspace may need to know that a panel is OLED for 2
> reasons:
>
> 1) To avoid screen burn-in
> 2) OLED screens do not have a classic backlight, so in some
On Wed, Oct 09, 2019 at 06:46:38PM -0400, Lyude Paul wrote:
> oh, completely forgot about this one
>
> Reviewed-by: Lyude Paul
Thanks for your review, applied to drm-misc-next.
-Daniel
>
> On Thu, 2019-10-10 at 00:41 +0200, Daniel Vetter wrote:
> > Private atomic objects have grown their own lo
== Series Details ==
Series: drm/i915/vbt: Handle generic DTD block
URL : https://patchwork.freedesktop.org/series/67811/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7046_full -> Patchwork_14741_full
Summary
---
**
Check the user's flags on the struct file before deciding whether or not
to stall before submitting a request. This allows us to reasonably
cheaply honour O_NONBLOCK without checking at more critical phases
during request submission.
Suggested-by: Joonas Lahtinen
Signed-off-by: Chris Wilson
Cc:
Quoting Chris Wilson (2019-10-10 14:48:49)
> Check the user's flags on the struct file before deciding whether or not
> to stall before submitting a request. This allows us to reasonably
> cheaply honour O_NONBLOCK without checking at more critical phases
> during request submission.
One might rea
Op 07-10-2019 om 21:37 schreef Matt Roper:
> On Fri, Oct 04, 2019 at 01:34:54PM +0200, Maarten Lankhorst wrote:
>> We have a src and dect rectangle, use it instead of relying on
>> the core drm properties.
>>
>> This removes the special case in the watermark code for cursor w/h.
>>
>> Signed-off-by
Op 08-10-2019 om 19:06 schreef Ville Syrjälä:
> On Fri, Oct 04, 2019 at 01:34:58PM +0200, Maarten Lankhorst wrote:
>> We want to split drm_crtc_state into the user visible state
>> and actual hardware state. To prepare for this, we need some
>> ground rules what should be in each state:
>>
>> In ua
No good reason why we must always use a static ringsize, so let
userspace select one during construction.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 83 +++--
include/uapi/drm/i915_drm.h | 12 +++
2 files cha
Hi Dave and Daniel,
This pull request includes the ones we missed for -rc1
drm-intel-next-fixes-2019-09-26 & drm-intel-next-fixes-2019-09-19
plus few fixes for execlists requests and CML display.
Here goes drm-intel-fixes-2019-10-10:
- Fix CML display by adding a missing ID.
- Drop redundant list
On Thu, Oct 10, 2019 at 04:21:00PM +0200, Maarten Lankhorst wrote:
> Op 08-10-2019 om 19:06 schreef Ville Syrjälä:
> > On Fri, Oct 04, 2019 at 01:34:58PM +0200, Maarten Lankhorst wrote:
> >> We want to split drm_crtc_state into the user visible state
> >> and actual hardware state. To prepare for t
From: Ville Syrjälä
The array is there only for timeout, "data" doesn't mean anything
so let's rename the thing to be more descriptive.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/
From: Ville Syrjälä
Make the ways/sets arrays static cosnt u8 to shrink things a bit.
text data bss dec hex filename
- 23935629 128 246926074 i915_drv.o
+ 23818629 128 245755fff i915_drv.o
Signed-off-by: Ville Syrjälä
---
From: Ville Syrjälä
The .read_2_2() hooks is never called for any of the message
types with a zero timeout. So it's all just dead weight which
we can chuck.
text data bss dec hex filename
- 34701360 0 3506188f5 intel_hdmi.o
+ 346333
From: Ville Syrjälä
All the timeout values fit in u16, so let's shrink the structure
a bit.
This ends up actually increasing the .text size a bit due to
some changes in instructions (constant imul+small jmps replaced
with mov+bigger jmpqs). Seems pretty arbitrary to me so I'll
just pretend I did
From: Ville Syrjälä
The only reason for the timeout2 value in the array is the
HDCP_2_2_AKE_SEND_HPRIME message. But that one still needs
special casing inside the loop, and so just ends up making
the code harder to read. Let's just remove this leaky
timeout2 abstraction and special case that one
On 10/10/2019 10:27, Chris Wilson wrote:
From: Lionel Landwerlin
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine. For now, we want to
pull the knowledge of which engine we use into a central property.
Signed-off-by: Lionel L
On 10/10/2019 10:27, Chris Wilson wrote:
Now that we have the engine stored in i915_perf, we have a means of
accessing intel_gt should we require it. However, we are currently only
using the intel_gt to find the right intel_uncore, so replace our
i915_perf.gt pointer with the more useful i915_per
Quoting Lionel Landwerlin (2019-10-10 15:57:32)
> On 10/10/2019 10:27, Chris Wilson wrote:
> > From: Lionel Landwerlin
> >
> > We'll use this information later to verify that a client trying to
> > reconfigure the stream does so on the right engine. For now, we want to
> > pull the knowledge of wh
From: Lionel Landwerlin
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine. For now, we want to
pull the knowledge of which engine we use into a central property.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
Now that we have the engine stored in i915_perf, we have a means of
accessing intel_gt should we require it. However, we are currently only
using the intel_gt to find the right intel_uncore, so replace our
i915_perf.gt pointer with the more useful i915_perf.uncore.
Signed-off-by: Chris Wilson
Cc:
On 10/10/2019 00:19, Chris Wilson wrote:
From: Lionel Landwerlin
Introduce a new perf_ioctl command to change the OA configuration of the
active stream. This allows the OA stream to be reconfigured between
batch buffers, giving greater flexibility in sampling. We inject a
request into the OA co
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Check known register
values within the context
URL : https://patchwork.freedesktop.org/series/67849/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7055 -> Patchwork_14748
=
Quoting Lionel Landwerlin (2019-10-10 16:22:25)
> On 10/10/2019 00:19, Chris Wilson wrote:
> > From: Lionel Landwerlin
> >
> > Introduce a new perf_ioctl command to change the OA configuration of the
> > active stream. This allows the OA stream to be reconfigured between
> > batch buffers, giving
Check the logical ring context by asserting that the registers hold
expected start during execution. (It's a bit chicken-and-egg for how
could we manage to execute our request if the registers were not being
updated. Still, it's nice to verify that the HW is working as expected.)
Signed-off-by: Ch
We want the general purpose registers to be clear in all new contexts so
that we can be confident that no information is leaked from one to the
next.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/selftest_lrc.c | 185 ++---
1 file changed, 166 in
The locks (active.lock and rq->lock) need to be taken with disabled
interrupts. This is done in i915_request_retire() by disabling the
interrupts independently of the locks itself.
While local_irq_disable()+spin_lock() equals spin_lock_irq() on vanilla
it does not on PREEMPT_RT. Also, it is not obv
On 10/10/2019 18:44, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-10-10 16:22:25)
On 10/10/2019 00:19, Chris Wilson wrote:
From: Lionel Landwerlin
Introduce a new perf_ioctl command to change the OA configuration of the
active stream. This allows the OA stream to be reconfigured betwee
On 10/10/2019 00:19, Chris Wilson wrote:
We set out-of-bound parameters inside the i915_requests.flags field,
such as disabling preemption or marking the end-of-context. We should
not coalesce consecutive requests if they have differing instructions
as we only inspect the last active request in a
== Series Details ==
Series: series starting with [01/10] drm/i915: Note the addition of timeslicing
to the pretend scheduler
URL : https://patchwork.freedesktop.org/series/67827/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7047_full -> Patchwork_14742_full
== Series Details ==
Series: Enable bigjoiner support, second approach. (rev3)
URL : https://patchwork.freedesktop.org/series/67590/
State : failure
== Summary ==
Applying: HAX to make DSC work on the icelake test system
Applying: drm/i915: Fix for_each_intel_plane_mask definition
Using index
== Series Details ==
Series: drm/i915: Honour O_NONBLOCK before throttling execbuf submissions
URL : https://patchwork.freedesktop.org/series/67850/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7056 -> Patchwork_14749
Summ
== Series Details ==
Series: RFC drm/i915: Allow userspace to specify ringsize on construction
URL : https://patchwork.freedesktop.org/series/67852/
State : failure
== Summary ==
Applying: RFC drm/i915: Allow userspace to specify ringsize on construction
Using index info to reconstruct a base
== Series Details ==
Series: series starting with [1/5] drm/i915: Shrink eDRAM ways/sets arrays
URL : https://patchwork.freedesktop.org/series/67853/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7056 -> Patchwork_14752
Sum
On Wed, Oct 09, 2019 at 10:37:21PM +, Patchwork wrote:
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Move SAGV block time to
dev_priv (rev2)
URL : https://patchwork.freedesktop.org/series/67799/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7da5381
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/perf: store the associated
engine of a stream
URL : https://patchwork.freedesktop.org/series/67857/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7056 -> Patchwork_14753
==
Quoting Sebastian Andrzej Siewior (2019-10-10 17:06:40)
> The locks (active.lock and rq->lock) need to be taken with disabled
> interrupts. This is done in i915_request_retire() by disabling the
> interrupts independently of the locks itself.
> While local_irq_disable()+spin_lock() equals spin_lock
On 2019-10-10 19:11:27 [+0100], Chris Wilson wrote:
> > --- a/drivers/gpu/drm/i915/i915_request.c
> > +++ b/drivers/gpu/drm/i915/i915_request.c
> > @@ -251,15 +251,13 @@ static bool i915_request_retire(struct i
> > active->retire(active, rq);
> > }
> >
> > - local_ir
After the state is committed, we readout the HW registers and compare
the HW state with the SW state that we just committed.
For Transcdoer port sync, we add master_transcoder and the
salves bitmask to the crtc_state, hence we need to read those during
the HW state readout to avoid pipe state misma
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Check known register
values within the context
URL : https://patchwork.freedesktop.org/series/67862/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7057 -> Patchwork_14754
=
== Series Details ==
Series: drm/i915: Don't disable interrupts independently of the lock (rev2)
URL : https://patchwork.freedesktop.org/series/59289/
State : failure
== Summary ==
Applying: drm/i915: Don't disable interrupts independently of the lock
error: sha1 information is lacking or usel
== Series Details ==
Series: series starting with [v7,1/6] drm/i915/display/icl: Save Master
transcoder in slave's crtc_state for Transcoder Port Sync (rev2)
URL : https://patchwork.freedesktop.org/series/67806/
State : failure
== Summary ==
Applying: drm/i915/display/icl: Save Master transco
Those features could be fused off on GEN9 non-low power and newer
GENs.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/intel_device_info.c | 6 ++
2 files changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/
If all pipes are fused off it means that display is disabled, similar
like we handle for GEN 7 and 8 right above.
On GEN 9 the bit 31 is "Internal Graphics Disable" and on newer GENs
it has another function, probably on GEN 9 when bit 31 is set all
the 3 pipes disable bit are set, so we can unify
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