Quoting Daniele Ceraolo Spurio (2019-10-10 00:04:24) > There are small differences between the blitter and the video engines in > the xcs context image (e.g. registers 0x200 and 0x204 only exist on the > blitter). Since we never explicitly set a value for those register and > given that we don't need to update the offsets in the lrc image when we > change engine within the class for virtual engine because the HW can > handle that, instead of having a separate define for the BCS we can > just restrict the programming to the part we're interested in, which is > common across the engines.
Yeah, my thinking was to be as complete as possible so that if we needed to apply register updates, we could. It was also a fascinating insight into what was stored, I was planning on using it for doing isolation testing (albeit that's a bit chicken-and-egg). > Bspec: 45584 > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospu...@intel.com> > Cc: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuopp...@linux.intel.com> > Cc: Stuart Summers <stuart.summ...@intel.com> No qualms about restricting ourselves to the bare essentials on the basis that the context image is meant to be relative-addressed. It did not improve stability of tgl-gem however. Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk> -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
