art_offset = htons(offset);
>
> - offset = htons((__force u16)(skb_transport_header(skb) -
Just curious, why does this require a __force, or even a cast?
Regardless, your proposed way of writing it is easier to read.
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> -
always assumed to be zero, and the length is
> taken from the other packet headers. So making these fields
> explicitly big endian has no effect on the behavior of the code.
>
> Signed-off-by: Alex Elder
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
> include/linux/if_rmne
Carpenter
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver")
> Signed-off-by: Jonathan Marek
> ---
> drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
On Wed 03 Mar 14:01 CST 2021, Siddharth Gupta wrote:
> From: Raghavendra Rao Ananta
>
> For security reasons scnprintf() is preferred over sprintf().
> Hence, convert the remoteproc's sysfs show functions accordingly.
>
Thanks for the patch Siddharth.
There's no possibility for these calls
The condition guarding the power_supply_put() calls in error and
removal paths are backwards, resulting in a guaranteed NULL pointer
dereference if no power supply was acquired.
Fixes: 59fa3def35de ("usb: dwc3: add a power supply for current control")
Signed-off-by: Bjorn Andersson
--
On Tue 02 Mar 09:47 CST 2021, Linus Walleij wrote:
> On Sat, Feb 27, 2021 at 10:22 AM Dan Carpenter
> wrote:
>
> > New smatch warnings:
> > drivers/pinctrl/qcom/pinctrl-lpass-lpi.c:458 lpi_config_set() error:
> > uninitialized symbol 'strength'.
> >
> > Old smatch warnings:
> >
On Fri 26 Feb 12:23 CST 2021, Rob Clark wrote:
> On Fri, Feb 26, 2021 at 9:24 AM Bjorn Andersson
> wrote:
> >
> > On Fri 26 Feb 03:55 CST 2021, Sai Prakash Ranjan wrote:
> >
> > > Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU
> > > bot
On Fri 26 Feb 03:55 CST 2021, Sai Prakash Ranjan wrote:
> Adreno(GPU) SMMU and APSS(Application Processor SubSystem) SMMU
> both implement "arm,mmu-500" in some QTI SoCs and to run through
> adreno smmu specific implementation such as enabling split pagetables
> support, we need to match the
.
Alex Elder (2):
rpmsg: glink: fix some kerneldoc comments
rpmsg: glink: add include of header file
Bjorn Andersson (1):
rpmsg: glink: Guard qcom_glink_ssr_notify() with correct config
drivers/rpmsg/qcom_glink_ssr.c | 17
The following changes since commit 5c8fe583cce542aa0b84adc939ce85293de36e5e:
Linux 5.11-rc1 (2020-12-27 15:30:22 -0800)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc.git
tags/rproc-v5.12
for you to fetch changes up to
The following changes since commit 5c8fe583cce542aa0b84adc939ce85293de36e5e:
Linux 5.11-rc1 (2020-12-27 15:30:22 -0800)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc.git
tags/hwlock-v5.12
for you to fetch changes up to
On Thu 11 Feb 22:59 CST 2021, Rajendra Nayak wrote:
> From: Maulik Shah
>
> GPIOs that can be configured as wakeup sources, have their
> interrupt lines routed to PDC interrupt controller.
>
> Provide the interrupt map of the GPIO to its wakeup capable
> interrupt parent
On Thu 18 Feb 14:55 CST 2021, Kuogee Hsieh wrote:
> Allow supported link rate to be limited to the value specified at
> dtsi. If it is not specified, then link rate is derived from dpcd
> directly. Below are examples,
> link-rate = <162000> for max link rate limited at 1.62G
> link-rate =
On Tue 16 Feb 05:12 CST 2021, Vinod Koul wrote:
> Add the CPUfreq compatible for SM8350 SoC along with note for using the
> specific compatible for SoCs
>
> Signed-off-by: Vinod Koul
> ---
> Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt | 4 +++-
> 1 file changed, 3
On Fri 12 Feb 11:33 CST 2021, Serge Semin wrote:
> On Wed, Feb 10, 2021 at 10:33:26PM +0300, Serge Semin wrote:
> > On Wed, Feb 10, 2021 at 12:56:59PM -0600, Bjorn Andersson wrote:
> > > On Wed 10 Feb 12:40 CST 2021, Serge Semin wrote:
> > >
> > > > On Wed
On Wed 10 Feb 13:33 CST 2021, Serge Semin wrote:
> On Wed, Feb 10, 2021 at 12:56:59PM -0600, Bjorn Andersson wrote:
> > On Wed 10 Feb 12:40 CST 2021, Serge Semin wrote:
> >
> > > On Wed, Feb 10, 2021 at 12:17:27PM -0600, Rob Herring wrote:
> > > > On Wed,
On Wed 10 Feb 04:45 CST 2021, Vinod Koul wrote:
> Add the SM8350 audio, compute, modem and sensor remoteprocs to the PAS
> DT binding.
>
> Signed-off-by: Vinod Koul
> ---
> .../devicetree/bindings/remoteproc/qcom,adsp.txt | 12
> 1 file changed, 12 insertions(+)
>
> diff
On Wed 10 Feb 12:41 CST 2021, Jakub Kicinski wrote:
> On Wed, 10 Feb 2021 11:55:31 +0530 Manivannan Sadhasivam wrote:
> > On Tue, Feb 09, 2021 at 08:17:44AM -0800, Jakub Kicinski wrote:
> > > On Tue, 9 Feb 2021 10:20:30 +0100 Aleksander Morgado wrote:
> > > > This may be a stupid suggestion,
naming so not to fail on the legacy DTS-files passed to the
> > > newer kernels.
> > >
> > > Signed-off-by: Serge Semin
> > > Reviewed-by: Bjorn Andersson
> > > ---
> > > drivers/usb/dwc3/dwc3-qcom.c | 3 ++-
> > > 1 file changed, 2 insertions
On Tue 09 Feb 17:25 CST 2021, Doug Anderson wrote:
> Hi,
>
> On Tue, Feb 9, 2021 at 8:09 AM Bjorn Andersson
> wrote:
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
> > b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
> > index 216a74f0057c..2f44
On Mon 01 Feb 09:50 CST 2021, mda...@codeaurora.org wrote:
> On 2021-02-01 12:13, Vinod Koul wrote:
> > On 01-02-21, 11:52, mda...@codeaurora.org wrote:
> > > On 2021-02-01 11:35, Vinod Koul wrote:
> > > > On 27-01-21, 23:56, mda...@codeaurora.org wrote:
> >
> > > > > The actual LOCK/UNLOCK
On Tue 09 Feb 08:27 CST 2021, Rob Herring wrote:
> On Mon, Feb 8, 2021 at 5:10 PM Alexandre Belloni
> wrote:
> >
> > On 08/02/2021 23:14:02+0100, Arnd Bergmann wrote:
> > > On Mon, Feb 8, 2021 at 10:35 PM Alexandre Belloni
> > > wrote:
> > > > On 08/02/2021 20:52:37+0100, Arnd Bergmann wrote:
>
), so some shuffling and trial and error was used to come up
with acceptable regions.
With this in order, enable the IPA device.
Signed-off-by: Bjorn Andersson
---
.../boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 26 +--
1 file changed, 13 insertions(+), 13 deletions(-)
diff --
and then
piecemeal patch this up on the various devices, push the configuration
of these regions out to the individual device dts files.
Signed-off-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi| 89 +--
arch/arm64/boot/dts/qcom/sdm845-db845c.dts| 85
On Sat 06 Feb 13:47 CST 2021, Geert Uytterhoeven wrote:
> Hi Arnd,
>
> On Sat, Feb 6, 2021 at 3:36 PM Arnd Bergmann wrote:
> > That said, I'm still not happy about the patch we discussed in the
> > other email thread[1] and I'd like to handle it a little more strictly in
> > the future, but I
On Mon 08 Feb 11:21 CST 2021, Kalle Valo wrote:
> Amit Pundir writes:
>
> > Hi Kalle,
> >
> > On Mon, 7 Dec 2020 at 22:25, Kalle Valo wrote:
> >>
> >> This is firmware version specific, right? There's also enum
> >> ath10k_fw_features which is embedded within firmware-N.bin, we could add
> >>
On Thu 04 Feb 10:58 CST 2021, Vinod Koul wrote:
> Add the registers for UFS found in SM8350. The UFS phy used in SM8350
> seems to have same offsets as V5 phy, although Documentation for that is
> lacking.
>
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Signed-off
On Wed 03 Feb 12:40 CST 2021, Jakub Kicinski wrote:
> On Wed, 3 Feb 2021 19:28:28 +0100 Loic Poulain wrote:
> > On Wed, 3 Feb 2021 at 19:05, Jakub Kicinski wrote:
> > > On Wed, 03 Feb 2021 09:45:06 +0530 Manivannan Sadhasivam wrote:
> > > > The current patchset only supports QMI channel so I'd
On Wed 03 Feb 12:05 CST 2021, Jakub Kicinski wrote:
> On Wed, 03 Feb 2021 09:45:06 +0530 Manivannan Sadhasivam wrote:
> > >> Jakub, Dave, Adding you both to get your reviews on this series. I've
> > >> provided an explanation above and in the previous iteration [1].
> > >
> > >Let's be clear
n
> Signed-off-by: Serge Semin
> Reviewed-by: Bjorn Andersson
> ---
> drivers/usb/dwc3/dwc3-qcom.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> index c703d552bbcf..49ad8d507d37 100644
&
On Fri 08 Jan 12:15 CST 2021, Akhil P Oommen wrote:
Please align the $subject prefix with other changes in the same file.
I fixed it up while picking up the patch this time.
Regards,
Bjorn
> Add support for gpu fuse to help identify the supported opps.
>
> Signed-off-by: Akhil P Oommen
> ---
On Wed 27 Jan 08:49 CST 2021, Robert Foss wrote:
> Build camera ISP driver as a module.
>
Isn't this enabled since b47c5fc15d88 ("arm64: defconfig: Enable
Qualcomm CAMCC, CAMSS and CCI drivers")?
Regards,
Bjorn
> Signed-off-by: Robert Foss
> ---
> arch/arm64/configs/defconfig | 1 +
> 1
On Tue 02 Feb 15:37 CST 2021, Rob Herring wrote:
> On Tue, Feb 2, 2021 at 1:48 PM Bjorn Andersson
> wrote:
> >
> > On Sat 30 Jan 10:14 CST 2021, Dmitry Baryshkov wrote:
> >
> > > On Sat, 30 Jan 2021 at 06:53, Bjorn Andersson
> > > wrote:
> >
On Sat 30 Jan 10:14 CST 2021, Dmitry Baryshkov wrote:
> On Sat, 30 Jan 2021 at 06:53, Bjorn Andersson
> wrote:
> >
> > On Fri 29 Jan 16:19 CST 2021, Dmitry Baryshkov wrote:
> >
> > > On Sat, 30 Jan 2021 at 00:50, Bjorn Helgaas wrote:
> > > >
>
On Thu 28 Jan 22:46 CST 2021, Wesley Cheng wrote:
> In order to take advantage of the TX fifo resizing logic, manually add
> these properties to the DWC3 child node by default. This will allow
> the DWC3 gadget to resize the TX fifos for the IN endpoints, which
> help with performance.
>
>
On Thu 28 Jan 11:52 CST 2021, Dmitry Baryshkov wrote:
> Add qca6391 to device tree as a way to provide power domain to WiFi and
> BT parts of the chip.
>
> Signed-off-by: Dmitry Baryshkov
> ---
> arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 61
> 1 file changed, 61
On Fri 29 Jan 16:19 CST 2021, Dmitry Baryshkov wrote:
> On Sat, 30 Jan 2021 at 00:50, Bjorn Helgaas wrote:
> >
> > On Fri, Jan 29, 2021 at 06:45:21AM +0300, Dmitry Baryshkov wrote:
> > > On 28/01/2021 22:26, Rob Herring wrote:
> > > > On Thu, Jan 28, 2021 at 11:52 AM Dmitry Baryshkov
> > > >
On Wed 27 Jan 06:30 CST 2021, Vinod Koul wrote:
> Document the SM8350 SoC binding and also the boards using it.
>
> Acked-by: Rob Herring
> Signed-off-by: Vinod Koul
Reviewed-by: Bjorn Andersson
> ---
> Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++
&g
On Sun 24 Jan 13:49 CST 2021, Jonathan Albrieux wrote:
> On Sun, Jan 24, 2021 at 04:51:31PM +0100, Stephan Gerhold wrote:
> > On Sun, Jan 24, 2021 at 04:07:19PM +0100, Konrad Dybcio wrote:
> > > > +_i2c3 {
> > > > + status = "okay";
> > > > +
> > > > + imu@68 {
> > > > +
.
Fixes: a0d67b94e2ef ("opp: Implement dev_pm_opp_set_opp()")
Signed-off-by: Bjorn Andersson
---
drivers/opp/core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index 583bb1274df9..3ff05f40e443 100644
--- a/drivers/opp/co
On Wed 27 Jan 20:49 CST 2021, Can Guo wrote:
> The initialization of clk_scaling.min_gear was removed by mistake. This
> change adds it back, otherwise clock scaling down would fail.
>
Thanks for the patch Can, it solves the problem I'm seeing!
Reviewed-by: Bjorn Andersson
Tested-
On Wed 27 Jan 12:14 CST 2021, Konrad Dybcio wrote:
> MDM9607 TSENS IP is very similar to the one of MSM8916, with
> minor adjustments to various tuning values.
>
> Signed-off-by: Konrad Dybcio
> ---
> .../bindings/thermal/qcom-tsens.yaml | 2 +
> drivers/thermal/qcom/tsens-v0_1.c
On Wed 27 Jan 09:15 CST 2021, Greg KH wrote:
> On Wed, Jan 13, 2021 at 08:56:25PM +0530, Manivannan Sadhasivam wrote:
> > Hi Greg,
> >
> > On Wed, Jan 06, 2021 at 10:44:13AM -0800, Hemant Kumar wrote:
> > > This patch series adds support for UCI driver. UCI driver enables
> > > userspace
> > >
On Tue 26 Jan 08:06 CST 2021, N?colas F. R. A. Prado wrote:
> Add the necessary devicetree nodes for the Qualcomm SPMI Flash LEDs
> present in PM8941.
>
> Signed-off-by: Nícolas F. R. A. Prado
> ---
> Changes in v2:
> - Moved from hammerhead dts to pm8941 dtsi, as it was this way downstream
> -
On Tue 26 Jan 08:06 CST 2021, N?colas F. R. A. Prado wrote:
> Enable module for the Qualcomm SPMI Flash LEDs present on the PM8941
> PMIC.
>
> Signed-off-by: Nícolas F. R. A. Prado
> ---
> Changes in v2:
> - Enabled CONFIG_LEDS_CLASS_FLASH since the driver now depends on it.
>
>
On Tue 26 Jan 08:04 CST 2021, N?colas F. R. A. Prado wrote:
> Add devicetree binding for QCOM SPMI Flash LEDs, which are part of
> PM8941, and are used both as lantern and camera flash.
>
> Signed-off-by: Nícolas F. R. A. Prado
> ---
> Changes in v2:
> - Add this commit
>
>
the firmware path from there. Otherwise, if the property
> is missing we fallback to the predefined path from driver resource
> structure.
>
Reviewed-by: Bjorn Andersson
But firmware-name is not mentioned in the dt binding.
Regards,
Bjorn
> Signed-off-by: Stanimir Varbanov
> -
irrespective of controlled_remotely property.
>
> Signed-off-by: Thara Gopinath
Reviewed-by: Bjorn Andersson
And from John on IRC:
Tested-by: John Stultz
Regards,
Bjorn
> ---
>
> v1->v2:
> - As per Shawn's suggestion, use devm_clk_get_opti
On Tue 26 Jan 08:05 CST 2021, N?colas F. R. A. Prado wrote:
> Add driver for the Qualcomm SPMI Flash LEDs. These are controlled
> through an SPMI bus and are part of the PM8941 PMIC. There are two LEDs
> present in the chip, and can be used independently as camera flash or
> together in torch
On Tue 26 Jan 10:21 CST 2021, Mark Rutland wrote:
> On Tue, Jan 26, 2021 at 02:58:33PM +, Matthew Wilcox wrote:
> > On Tue, Jan 26, 2021 at 10:47:34AM +, Mark Rutland wrote:
> > > Hi,
> > >
> > > When fuzzing arm64 with Syzkaller, I'm seeing some splats where
> > > this_cpu_ptr() is used
On Mon 25 Jan 22:32 CST 2021, Wesley Cheng wrote:
> On 1/25/2021 5:55 PM, Bjorn Andersson wrote:
> > On Mon 25 Jan 19:14 CST 2021, Wesley Cheng wrote:
> >
> >>
> >>
> >> On 1/22/2021 9:12 AM, Bjorn Andersson wrote:
> >>> On Thu 21 Jan 22:01
>
Reviewed-by: Bjorn Andersson
> Signed-off-by: Vinod Koul
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.h | 27 +++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h
> b/drivers/phy/qualcomm/phy-qcom-qmp.h
>
On Wed 13 Jan 12:38 CST 2021, AngeloGioacchino Del Regno wrote:
> In commit 734bdefdb043 ("clk: qcom: rcg2: Stop hardcoding gfx3d
> pingpong parent numbers") the gfx3d ping-pong ops (clk_gfx3d_ops)
I believe you're referring to patch 5 here, which when merged won't have
this hash. So you'd need
On Tue 26 Jan 02:00 CST 2021, Vinod Koul wrote:
> On 25-01-21, 11:25, Bjorn Andersson wrote:
> > On Sun 17 Jan 22:43 CST 2021, Vinod Koul wrote:
> >
> > > Add device tree bindings for global clock controller on SM8350 SoCs.
> > >
> > > Reviewed-by: Ro
On Tue 26 Jan 02:52 CST 2021, Jiapeng Zhong wrote:
> Fix the following coccicheck warnings:
>
> ./drivers/firmware/qcom_scm.c:324:20-22: WARNING !A || A && B is
> equivalent to !A || B.
>
Reviewed-by: Bjorn Andersson
> Reported-by: Abaci Robot
>
On Tue 26 Jan 06:45 CST 2021, Lee Jones wrote:
> Fixes the following W=1 kernel build warning(s):
>
> drivers/clk/qcom/clk-rpm.c:453:29: warning: ‘clk_rpm_branch_ops’ defined but
> not used [-Wunused-const-variable=]
>
> Cc: Andy Gross
> Cc: Bjorn Andersson
> Cc:
:77:32: warning:
> ‘mmcc_xo_mmpll0_1_2_gpll0_map’ defined but not used [-Wunused-const-variable=]
>
> Cc: Andy Gross
> Cc: Bjorn Andersson
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-arm-...@vger.kernel.org
> Cc: linux-...@vger.kernel.org
Reviewed-by: Bjorn Andersson
>
riable]
>
> Cc: Andy Gross
> Cc: Bjorn Andersson
> Cc: Michael Turquette
> Cc: Stephen Boyd
> Cc: linux-arm-...@vger.kernel.org
> Cc: linux-...@vger.kernel.org
Reviewed-by: Bjorn Andersson
> Signed-off-by: Lee Jones
> ---
> drivers/clk/qcom/gcc-ipq4019.c | 7
On Tue 26 Jan 06:45 CST 2021, Lee Jones wrote:
> Fixes the following W=1 kernel build warning(s):
>
> drivers/clk/qcom/clk-regmap.c:97: warning: Function parameter or member
> 'dev' not described in 'devm_clk_register_regmap'
>
> Cc: Andy Gross
> Cc: Bjorn Andersson
&g
Add devicetree binding for the global clock controller found in the
Qualcomm SC8180x platform.
Signed-off-by: Bjorn Andersson
---
Changes since v1:
- None
.../bindings/clock/qcom,gcc-sc8180x.yaml | 76 +
include/dt-bindings/clock/qcom,gcc-sc8180x.h | 309 ++
2 files
Add clocks, resets and some of the GDSC provided by the global clock
controller found in the Qualcomm SC8180x platform.
Signed-off-by: Bjorn Andersson
---
Changes since v1:
- Fixes all gdsc addresses (missed to fold the fixup that subtracted gcc base
in v1)
drivers/clk/qcom/Kconfig
Add pinctrl driver for the sc8180x TLMM block.
A noteworthy difference from previous TLMM blocks is that the registers
for GPIO 177 through 189 are for some reason offset from the typical
layout. Other than that the driver is same old...
Signed-off-by: Bjorn Andersson
---
drivers/pinctrl/qcom
Add binding for the TLMM block in the Qualcomm SC8180X platform.
Signed-off-by: Bjorn Andersson
---
.../pinctrl/qcom,sc8180x-pinctrl.yaml | 152 ++
1 file changed, 152 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/qcom,sc8180x-pinctrl.yaml
Several properties are shared between all TLMM bindings. By providing a
common binding to define these properties each platform's binding can be
reduced to just listing which of these properties should be checked for
- or further specified.
Reviewed-by: Vinod Koul
Signed-off-by: Bjorn Andersson
On Mon 25 Jan 19:14 CST 2021, Wesley Cheng wrote:
>
>
> On 1/22/2021 9:12 AM, Bjorn Andersson wrote:
> > On Thu 21 Jan 22:01 CST 2021, Wesley Cheng wrote:
> >
>
> Hi Bjorn,
> >
> > Under what circumstances should we specify this? And in particular a
On Mon 25 Jan 04:09 CST 2021, Vinod Koul wrote:
> Add the tables for init sequences for UFS QMP phy found in SM8350 SoC.
>
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Signed-off-by: Vinod Koul
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 127 +++
ied to the
> destination result buffer. qce_ahash_final cannot be made to alter this
> behavior and allowed to proceed if rctx->buflen is 0 because the crypto
> engine BAM does not allow for zero length transfers.
>
Please drop "drivers: " from $subject.
Apart from th
On Mon 25 Jan 09:47 CST 2021, Konrad Dybcio wrote:
>
> > I know how bad it is, so I understand your desire to not have to rebase
> > that, but I will merge things as they become ready on the list.
> >
> > So please post your change (perhaps it's posted and I'm failing to find
> > it in my
On Mon 25 Jan 08:51 CST 2021, AngeloGioacchino Del Regno wrote:
> Il 25/01/21 11:40, Hans Verkuil ha scritto:
> > On 18/01/2021 18:45, AngeloGioacchino Del Regno wrote:
> > > Il 18/01/21 18:21, Stanimir Varbanov ha scritto:
> > > > > diff --git a/drivers/media/platform/qcom/venus/core.c
> > > >
On Sun 24 Jan 11:33 CST 2021, Konrad Dybcio wrote:
>
> > All msm8974 dts(i) files use this style. Deviating from it for this doesn't
> > make sense. And yes msm8974 should probably be converted to the newer label
> > style (as was done with msm8916 a while ago).
>
> I have a >3k lines commit
On Fri 15 Jan 03:13 CST 2021, Arnaud POULIQUEN wrote:
> Hi Mathieu,
>
>
> On 1/14/21 8:05 PM, Mathieu Poirier wrote:
> > On Wed, Jan 06, 2021 at 02:37:14PM +0100, Arnaud Pouliquen wrote:
> >> The rpmsg_create_ept function is invoked when the device is opened.
> >> As only one endpoint must be
On Mon 25 Jan 05:35 CST 2021, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> Compile-testing without CONFIG_REMOTEPROC results in a build failure:
>
> >>> referenced by ipa_main.c
> >>> net/ipa/ipa_main.o:(ipa_probe) in archive drivers/built-in.a
> ld.lld: error: undefined
y: Vinod Koul
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
> drivers/clk/qcom/Kconfig |8 +
> drivers/clk/qcom/Makefile |1 +
> drivers/clk/qcom/gcc-sm8350.c | 3790 +
> 3 files changed, 3799 insertions(+)
> create mode 1006
On Sun 17 Jan 22:43 CST 2021, Vinod Koul wrote:
> Driver uses regval variable for holding register values, replace with a
> shorter one val
>
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Suggested-by: Stephen Boyd
> Signed-off-by: Vinod Koul
> ---
> drivers/clk/qcom
14
> +#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK15
> +#define GCC_AGGRE_UFS_PHY_AXI_CLK16
> +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 17
> +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 18
>
On Sun 17 Jan 22:43 CST 2021, Vinod Koul wrote:
> From: Vivek Aknurwar
>
> Lucid 5LPE is a slightly different Lucid PLL with different offsets and
> porgramming sequence so add support for these
>
> Signed-off-by: Vivek Aknurwar
> Signed-off-by: Jeevan Shriram
> [vkoul: rebase and tidy up
On Sun 17 Jan 22:43 CST 2021, Vinod Koul wrote:
> Trion 5LPE set rate uses code similar to alpha_pll_trion_set_rate() but
> with different registers. Modularize these by moving out latch and latch
> ack bits so that we can reuse the function.
>
Reviewed-by: Bjorn Andersson
Re
On Mon 25 Jan 04:09 CST 2021, Vinod Koul wrote:
> Add the compatible strings for the UFS PHY found on SM8350 SoC.
>
Reviewed-by: Bjorn Andersson
> Signed-off-by: Vinod Koul
> ---
> Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml | 1 +
> 1 file changed, 1 inse
ound in SM8350 SoC.
>
This can/should be picked up independently of the other patches, so
would have been better sent solo.
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Signed-off-by: Vinod Koul
> ---
> Documentation/devicetree/bindings/ufs/ufshcd-pltfrm.txt | 2 ++
>
On Mon 25 Jan 04:59 CST 2021, Robert Marko wrote:
> On Fri, Jan 22, 2021 at 7:56 PM Bjorn Andersson
> wrote:
>
> > On Fri 02 Oct 12:41 CDT 2020, Robert Marko wrote:
> >
> > > On Wed, Sep 9, 2020 at 9:56 PM Robert Marko
> > wrote:
> > > >
On Mon 07 Sep 05:19 CDT 2020, Robert Marko wrote:
> Since we now have driver for the SDHCI VQMMC LDO needed
> for I/0 voltage levels lets introduce the necessary node for it.
>
> Signed-off-by: Robert Marko
> Cc: Luka Perkov
> ---
> arch/arm/boot/dts/qcom-ipq4019.dtsi | 10 ++
> 1
thentication transformations and is always 0.
> Remove these two redundant parameters in qce_start.
>
Please drop "drivers: " from $subject.
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Signed-off-by: Thara Gopinath
> ---
> drivers/crypto/qce/common.c | 17 +++
has gone away in the
newer chips. I am however not able to find anything about it, so I'm in
favor of merging this patch and if anyone actually uses the driver on
the older hardware we'd have to go back and quirk it somehow.
Acked-by: Bjorn Andersson
Regards,
Bjorn
> - qce_write(qce, REG_ENCR_
On Wed 20 Jan 12:48 CST 2021, Thara Gopinath wrote:
> src_table is unused and hence remove it from struct qce_cipher_reqctx
>
> Signed-off-by: Thara Gopinath
> ---
> drivers/crypto/qce/cipher.h | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/drivers/crypto/qce/cipher.h
On Wed 20 Jan 12:48 CST 2021, Thara Gopinath wrote:
> This patch contains the following fixes for the supported encryption
> algorithms in the Qualcomm crypto engine(CE)
> 1. Return unsupported if key1 = key2 for AES XTS algorithm since CE
> does not support this and the operation causes the
On Wed 20 Jan 12:48 CST 2021, Thara Gopinath wrote:
Please drop "drivers: " from $subject.
> Export and import interfaces save and restore partial transformation
> states. The partial states were being stored and restored in struct
> sha1_state for sha1/hmac(sha1) transformations and
On Fri 22 Jan 16:47 CST 2021, Linus Walleij wrote:
> On Thu, Jan 21, 2021 at 12:49 PM Pan Bian wrote:
>
> > Put child node before return to fix potential reference count leak.
> > Generally, the reference count of child is incremented and decremented
> > automatically in the macro
On Sun 29 Nov 12:50 CST 2020, Jonathan McDowell wrote:
> Gentle poke; did this just get missed or is there some reason not to
> apply it?
>
There's no reason why this wasn't applied. I've picked it up now.
Thank you,
Bjorn
> On Sun, Jul 05, 2020 at 03:25:44PM +0100, Jonathan McDowell wrote:
>
On Fri 02 Oct 12:41 CDT 2020, Robert Marko wrote:
> On Wed, Sep 9, 2020 at 9:56 PM Robert Marko wrote:
> >
> > 8devices Habanero DVK is a dual-band SoM development kit based on Qualcomm
> > IPQ4019 + QCA8075 platform.
> >
> > Specs are:
> > CPU: QCA IPQ4019
> > RAM: DDR3L 512MB
> > Storage: 32MB
On Wed 30 Dec 09:51 CST 2020, Iskren Chernev wrote:
> From: Brian Masney
>
> Add support for the a3xx GPU
>
> Signed-off-by: Brian Masney
As discussed on IRC I'm waiting for a respin of this with your S-o-b
added after Brian's.
Thanks,
Bjorn
> ---
> arch/arm/boot/dts/qcom-msm8974.dtsi |
On Thu 21 Jan 22:01 CST 2021, Wesley Cheng wrote:
> Some devices have USB compositions which may require multiple endpoints
> that support EP bursting. HW defined TX FIFO sizes may not always be
> sufficient for these compositions. By utilizing flexible TX FIFO
> allocation, this allows for
rom:, but based on the
changes you've done I don't think he has certified the origin of this
patch anymore.
So the line crediting his work above and your alone S-o-b seems more
reasonable.
For the content of the patch:
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Signed-off-by: Jeevan Shriram
>
On Thu 21 Jan 11:17 CST 2021, Vinod Koul wrote:
> Add device tree binding Documentation details for Qualcomm SM8350
> pinctrl driver.
>
Reviewed-by: Bjorn Andersson
Although that's dependent on the acceptance of the common binding in a
state similar its current one.
Regards,
Bjorn
On Thu 21 Jan 07:20 CST 2021, Linus Walleij wrote:
> On Wed, Jan 20, 2021 at 11:21 PM Bjorn Andersson
> wrote:
>
> > Several properties are shared between all TLMM bindings. By providing a
> > common binding to define these properties each platform's binding can be
> &
On Wed 20 Jan 01:29 CST 2021, Jiapeng Zhong wrote:
> Fix the following coccicheck warnings:
>
> ./drivers/pinctrl/qcom/pinctrl-ssbi-gpio.c:340:3-15: WARNING:
> Assignment of 0/1 to bool variable.
>
> Reported-by: Abaci Robot
> Signed-off-by: Jiapeng Zhong
Reviewe
On Wed 20 Jan 16:35 CST 2021, Bjorn Andersson wrote:
> diff --git a/drivers/clk/qcom/gcc-sc8180x.c b/drivers/clk/qcom/gcc-sc8180x.c
[..]
> +static struct gdsc emac_gdsc = {
> + .gdscr = 0x106004,
Seems like I missed squashing the fixup where I subtract the gcc base
address after
The primary SMMU found in Qualcomm SC8180X platform needs to use the
Qualcomm implementation, so add a specific compatible for this.
Signed-off-by: Bjorn Andersson
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm
Add compatible for the ARM SMMU found in the Qualcomm SC8180x platform.
Signed-off-by: Bjorn Andersson
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
b/Documentation/devicetree
Add compatible for the Qualcomm SC8180x APCS block to the Qualcomm APCS
binding.
Signed-off-by: Bjorn Andersson
---
.../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss
The Qualcomm SC8180X platform has a APSS block exposing the usual IPC
bits, add a compatible for this.
Signed-off-by: Bjorn Andersson
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
b/drivers/mailbox/qcom
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