Kattungal, Deepak had written, on 04/09/2010 12:06 PM, the following:
[..]
+ /* TX and RX FIFO Clear; FIFO dis */
+ serial_write_reg(p, UART_FCR, 0xA6);
NAK
Late realization: should be checking if FIFO clear actually occurred
before proceeding (FIFO clear bits will be cleared by h/w
Hi Nishanth
My comments below.
Regards
Deepak
-Original Message-
From: Menon, Nishanth
Sent: Friday, April 09, 2010 12:00 PM
To: linux-omap
Cc: Kattungal, Deepak; Raja, Govindraj; Kevin Hilman; Tero Kristo
Subject: Re: [PM][PATCH 2/4] OMAP3: Serial: Errata i202: fix for MDR1 access
Menon, Nishanth had written, on 04/08/2010 12:54 PM, the following:
From: Deepak K
[...]
Cc: Govindraj R
Cc: Kevin Hilman
Cc: Tero Kristo
Signed-off-by: Deepak K
Signed-off-by: Nishanth Menon
---
Note: original patch was done for android kernel, ported and sanity
tested
arch/arm/mach-
From: Deepak K
Original patch:
http://git.omapzoom.org/?p=kernel/omap.git;a=commitdiff;h=42d4a342c009bd9727c100abc8a4bc3063c22f0c
Errata i202 (OMAP3430 - 1.12, OMAP3630 - 1.6):
UART module MDR1 register access can cause a dummy underrun
condition which could result in a freeze in the case of IrD
