Re: [Qemu-devel] [PATCH v3 3/3] contrib: add vhost-user-input

On Mon, May 13, 2019 at 08:33:25PM +0200, Marc-André Lureau wrote: > Add a vhost-user input backend example, based on virtio-input-host > device. It takes an evdev path as argument, and can be associated with > a vhost-user-input device via a UNIX socket: > > $ vhost-user-input -p /dev/input/event

[Qemu-devel] [PATCH] docs: provide documentation on the POWER9 XIVE interrupt controller

This documents the overall XIVE architecture and gives an overview of the QEMU models. It also provides documentation on the 'info pic' command. Signed-off-by: Cédric Le Goater --- docs/index.rst | 1 + docs/ppc/index.rst | 13 ++ docs/ppc/xive.rst | 344 +

[Qemu-devel] [PATCH v12 04/12] target/rx: RX disassembler

Signed-off-by: Yoshinori Sato --- include/disas/dis-asm.h |5 + target/rx/disas.c | 1480 +++ 2 files changed, 1485 insertions(+) create mode 100644 target/rx/disas.c diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h index 9240e

[Qemu-devel] [PATCH v12 08/12] hw/rx: RX Target hardware definition

rx62n - RX62N cpu. rx-virt - RX QEMU virtual target. Signed-off-by: Yoshinori Sato --- include/hw/rx/rx.h| 7 ++ include/hw/rx/rx62n.h | 94 hw/rx/rx-virt.c | 105 ++ hw/rx/rx62n.c | 238 +++

Re: [Qemu-devel] [PATCH v2 1/2] vfio/mdev: add version attribute for mdev device

On Mon, May 13, 2019 at 09:28:04PM +0800, Erik Skultety wrote: > On Fri, May 10, 2019 at 11:48:38AM +0200, Cornelia Huck wrote: > > On Fri, 10 May 2019 10:36:09 +0100 > > "Dr. David Alan Gilbert" wrote: > > > > > * Cornelia Huck (coh...@redhat.com) wrote: > > > > On Thu, 9 May 2019 17:48:26 +0100

Re: [Qemu-devel] [PATCH v3] ui/console: Precautionary glBindTexture and surface->texture validation in surface_gl_update_texture

On Tue, May 07, 2019 at 11:05:01AM +0300, Marcel Apfelbaum wrote: > From: HOU Qiming > > In a GVT-g setup with dmabuf and GTK GUI, the current 2D texture at > surface_gl_update_texture is not necessarily > surface->texture. Adding a glBindTexture fixes related crashes and > artifacts, and is gene

[Qemu-devel] [PULL 16/31] tcg/i386: Support vector variable shift opcodes

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 35 +++ 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 241bf19413..b240633455 100644 --- a/tcg/i3

[Qemu-devel] [PATCH v12 02/12] target/rx: TCG helper

Signed-off-by: Yoshinori Sato --- target/rx/helper.h| 31 target/rx/helper.c| 148 target/rx/op_helper.c | 481 ++ 3 files changed, 660 insertions(+) create mode 100644 target/rx/helper.h create mode 100644 target/rx

Re: [Qemu-devel] [PATCHv4 0/2] ui/curses: BSD portability fixes

On Sat, Apr 27, 2019 at 08:33:05PM +0200, Samuel Thibault wrote: > BSD needs a few fixes for wide character manipulations. > > Difference with v1: > - Fix unitialized value in error message > > Difference with v2: > - Add cchar_t manipulation fix > > Difference with v3: > - use mbrtowc/wcrtomb i

[Qemu-devel] [PATCH v12 07/12] hw/char: RX62N serial communication interface (SCI)

This module supported only non FIFO type. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/char/renesas_sci.h | 45 ++ hw/char/renesas_sci.c | 340 +

[Qemu-devel] [PATCH v12 05/12] hw/intc: RX62N interrupt controller (ICUa)

This implementation supported only ICUa. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/intc/rx_icu.h | 57 +++ hw/intc/rx_icu.c | 376 +++

[Qemu-devel] [PATCH v12 11/12] qemu/bitops.h: Add extract8 and extract16

Signed-off-by: Yoshinori Sato --- include/qemu/bitops.h | 38 ++ 1 file changed, 38 insertions(+) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 3f0926cf40..764f9d1ea0 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -301,6 +

[Qemu-devel] [PATCH v12 01/12] target/rx: TCG translation

This part only supported RXv1 instructions. Instruction manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032ej0120_rxsm.pdf Signed-off-by: Yoshinori Sato --- target/rx/translate.c | 2432 +++ target/rx/Makefile.objs | 1

[Qemu-devel] [PATCH v12 03/12] target/rx: CPU definition

Signed-off-by: Yoshinori Sato --- target/rx/cpu.h | 227 target/rx/cpu.c | 222 ++ target/rx/gdbstub.c | 112 ++ target/rx/monitor.c | 38 + 4 files change

[Qemu-devel] [PATCH v12 00/12] Add RX archtecture support

Hello. This patch series is added Renesas RX target emulation. I fixed the ROM address because v11 was incorrect. My git repository is bellow. git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git tags/rx-20190514 Testing binaries bellow. u-boot Download - https://osdn.net/users/ysato/pf/qemu/dl/u-b

[Qemu-devel] [PATCH v12 09/12] Add rx-softmmu

Signed-off-by: Yoshinori Sato --- configure | 8 default-configs/rx-softmmu.mak | 3 +++ include/sysemu/arch_init.h | 1 + arch_init.c| 2 ++ hw/Kconfig | 1 + 5 files changed, 15 insertions(+) create mode 100644 default-c

[Qemu-devel] [PATCH v12 06/12] hw/timer: RX62N internal timer modules

renesas_tmr: 8bit timer modules. renesas_cmt: 16bit compare match timer modules. This part use many renesas's CPU. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/timer/renesas_cmt.h | 38 +++

[Qemu-devel] [PATCH v12 12/12] MAINTAINERS: Add RX

Signed-off-by: Yoshinori Sato --- MAINTAINERS | 19 +++ 1 file changed, 19 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a73a61a546..ef6a02702e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -272,6 +272,13 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux

[Qemu-devel] [PATCH v12 10/12] hw/registerfields.h: Add 8bit and 16bit register macros.

Some RX peripheral using 8bit and 16bit registers. Added 8bit and 16bit APIs. Signed-off-by: Yoshinori Sato --- include/hw/registerfields.h | 32 +++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/include/hw/registerfields.h b/include/hw/registerfields

[Qemu-devel] [PULL 08/31] tcg: Support cross-class moves without instruction support

PowerPC Altivec does not support direct moves between vector registers and general registers. So when tcg_out_mov fails, we can use the backing memory for the temporary to perform the move. Acked-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/tcg.c | 31

[Qemu-devel] [PULL 03/31] tcg: Allow add_vec, sub_vec, neg_vec, not_vec to be expanded

PowerPC Altivec does not support add and subtract of 64-bit elements. Prepare for that configuration by not assuming the operation is universally supported. Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 49 ++

[Qemu-devel] [PATCH] i386: Enable IA32_MISC_ENABLE MWAIT bit when exposing mwait/monitor

From: Wanpeng Li The CPUID.01H:ECX[bit 3] ought to mirror the value of the MSR IA32_MISC_ENABLE MWAIT bit and as userspace has control of them both, it is userspace's job to configure both bits to match on the initial setup. Cc: Eduardo Habkost Cc: Paolo Bonzini Cc: Radim Krčmář Signed-off

Re: [Qemu-devel] [libvirt] QMP; unsigned 64-bit ints; JSON standards compliance

Eric Blake writes: > On 5/13/19 8:53 AM, Markus Armbruster wrote: > >>> We have a few options >>> >>> 1. Use string format for values > 2^53-1, int format below that >>> 2. Use string format for all fields which are 64-bit ints whether >>> signed or unsigned >>> 3. Use string format for al

Re: [Qemu-devel] [PATCH v7 1/8] vhost-user: add vhost_user_gpu_set_socket()

Hi, > +VhostUserGpuCursorUpdate > + > + > ++-+---+---++ > +| pos | hot_x | hot_y | cursor | > ++-+---+---++ > + > +:pos: a ``VhostUserGpuCursorPos``, the cursor location > + > +:hot_x/hot_y: ``u32``, the cursor hot location > + > +:

[Qemu-devel] [PULL 06/31] tcg/arm: Use tcg_out_mov_reg in tcg_out_mov

We have a function that takes an additional condition parameter over the standard backend interface. It already takes care of eliding no-op moves. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/arm/tcg-target

Re: [Qemu-devel] [Qemu-ppc] [PATCH v8 5/6] ppc: spapr: Enable FWNMI capability

On Tuesday 14 May 2019 10:17 AM, David Gibson wrote: > On Mon, May 13, 2019 at 04:00:43PM +0530, Aravinda Prasad wrote: >> >> >> On Friday 10 May 2019 03:23 PM, David Gibson wrote: >>> On Fri, May 10, 2019 at 12:45:29PM +0530, Aravinda Prasad wrote: On Friday 10 May 2019 12:16 PM,

Re: [Qemu-devel] [PATCH 08/13] target/arm/monitor: Add query-sve-vector-lengths

Andrew Jones writes: > On Mon, May 13, 2019 at 06:12:38PM +0200, Markus Armbruster wrote: >> Andrew Jones writes: >> >> > Provide a QMP interface to query the supported SVE vector lengths. >> > A migratable guest will need to explicitly specify a valid set of >> > lengths on the command line an

Re: [Qemu-devel] [PATCH v8 3/6] libnvdimm: add dax_dev sync flag

> > > > > > Hi Dan, > > > > While testing device mapper with DAX, I faced a bug with the commit: > > > > commit ad428cdb525a97d15c0349fdc80f3d58befb50df > > Author: Dan Williams > > Date: Wed Feb 20 21:12:50 2019 -0800 > > > > When I reverted the condition to old code[1] it worked for me. I >

[Qemu-devel] [PULL 20/31] tcg: Add support for integer absolute value

Remove a function of the same name from target/arm/. Use a branchless implementation of abs gleaned from gcc. Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 5 + target/arm/translat

Re: [Qemu-devel] [Qemu-ppc] [PATCH v8 4/6] target/ppc: Build rtas error log upon an MCE

On Tuesday 14 May 2019 10:10 AM, David Gibson wrote: > On Tue, May 14, 2019 at 09:56:41AM +0530, Aravinda Prasad wrote: >> >> >> On Tuesday 14 May 2019 05:38 AM, David Gibson wrote: >>> On Mon, May 13, 2019 at 01:30:53PM +0200, Greg Kurz wrote: On Mon, 22 Apr 2019 12:33:26 +0530 Aravin

Re: [Qemu-devel] How do we do user input bitmap properties?

Andrew Jones writes: > On Thu, Apr 18, 2019 at 07:48:09PM +0200, Markus Armbruster wrote: >> Daniel P. Berrangé writes: >> >> > On Thu, Apr 18, 2019 at 11:28:41AM +0200, Andrew Jones wrote: >> >> Hi all, >> >> >> >> First some background: >> >> >> >> For the userspace side of AArch64 guest SV

[Qemu-devel] [PULL 17/31] tcg/aarch64: Support vector variable shift opcodes

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.opc.h | 2 ++ tcg/aarch64/tcg-target.inc.c | 42 3 files changed, 45 insertions(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.

Re: [Qemu-devel] [Qemu-ppc] [PATCH v8 4/6] target/ppc: Build rtas error log upon an MCE

On Tue, May 14, 2019 at 09:56:41AM +0530, Aravinda Prasad wrote: > > > On Tuesday 14 May 2019 05:38 AM, David Gibson wrote: > > On Mon, May 13, 2019 at 01:30:53PM +0200, Greg Kurz wrote: > >> On Mon, 22 Apr 2019 12:33:26 +0530 > >> Aravinda Prasad wrote: > >> > >>> Upon a machine check exception

Re: [Qemu-devel] [Qemu-ppc] [PATCH v8 5/6] ppc: spapr: Enable FWNMI capability

On Mon, May 13, 2019 at 04:00:43PM +0530, Aravinda Prasad wrote: > > > On Friday 10 May 2019 03:23 PM, David Gibson wrote: > > On Fri, May 10, 2019 at 12:45:29PM +0530, Aravinda Prasad wrote: > >> > >> > >> On Friday 10 May 2019 12:16 PM, David Gibson wrote: > >>> On Mon, Apr 22, 2019 at 12:33:35

Re: [Qemu-devel] [RFC v2 PATCH 3/3] spapr: Add Hcalls to support PAPR NVDIMM device

On Mon, May 13, 2019 at 04:28:36AM -0500, Shivaprasad G Bhat wrote: > This patch implements few of the necessary hcalls for the nvdimm support. > > PAPR semantics is such that each NVDIMM device is comprising of multiple > SCM(Storage Class Memory) blocks. The guest requests the hypervisor to bind

[Qemu-devel] [PULL 18/31] tcg: Add gvec expanders for vector shift by scalar

Allow expansion either via shift by scalar or by replicating the scalar for shift by vector. Signed-off-by: Richard Henderson --- v3: Use a private structure for do_gvec_shifts. --- tcg/tcg-op-gvec.h | 7 ++ tcg/tcg-op.h | 4 + tcg/tcg-op-gvec.c | 214 +++

[Qemu-devel] [PATCH 0/2] target/arm: Minor bit field improvements

The tcg extract2 patch on which this depended is now in master. r~ Richard Henderson (2): target/arm: Use extract2 for EXTR target/arm: Simplify BFXIL expansion target/arm/translate-a64.c | 44 -- 1 file changed, 23 insertions(+), 21 deletions(-) -- 2

Re: [Qemu-devel] [Qemu-ppc] [PATCH v8 4/6] target/ppc: Build rtas error log upon an MCE

On Tuesday 14 May 2019 05:38 AM, David Gibson wrote: > On Mon, May 13, 2019 at 01:30:53PM +0200, Greg Kurz wrote: >> On Mon, 22 Apr 2019 12:33:26 +0530 >> Aravinda Prasad wrote: >> >>> Upon a machine check exception (MCE) in a guest address space, >>> KVM causes a guest exit to enable QEMU to b

[Qemu-devel] [PATCH] kbd-state: fix autorepeat handling

When allowing multiple down-events in a row (key autorepeat) we can't use change_bit() any more to update the state, because autorepeat events don't change the key state. We have to explicitly use set_bit() and clear_bit() instead. Cc: qemu-sta...@nongnu.org Fixes: 35921860156e kbd-state: don't b

[Qemu-devel] [PULL 26/31] target/ppc: Use tcg_gen_abs_i32

From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20190423102145.14812-2-f4...@amsat.org> Signed-off-by: Richard Henderson --- target/ppc/translate/spe-impl.inc.c | 14 +- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git a/target/ppc/transla

[Qemu-devel] [PULL 11/31] tcg: Add tcg_out_dupm_vec to the backend interface

Currently stubbed out in all backends that support vectors. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 6 ++ tcg/i386/tcg-target.inc.c| 7 +++ tcg/tcg.c| 19 ++- 3 files changed, 31 insertions(+), 1 deletion(-) diff --gi

[Qemu-devel] [PATCH 2/2] target/arm: Simplify BFXIL expansion

The mask implied by the extract is redundant with the one implied by the deposit. Also, fix spelling of BFXIL. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/ar

Re: [Qemu-devel] [PATCH v3 38/39] tcg/arm: Use LDRD to load tlb mask+table

On Sat, May 11, 2019 at 12:13 PM Richard Henderson wrote: > > On 5/10/19 2:08 PM, Alistair Francis wrote: > >> +if (use_armv6_instructions && TARGET_LONG_BITS == 64) { > >> +tcg_out_ldrd_8(s, COND_AL, TCG_REG_R2, TCG_REG_R1, cmp_off); > ... > > > > This is complex and I'm proba

[Qemu-devel] [PATCH 1/2] target/arm: Use extract2 for EXTR

This is, after all, how we implement extract2 in tcg/aarch64. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 38 -- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/target/arm/translate-a64.c b/targ

Re: [Qemu-devel] [RFC v2 PATCH 2/3] spapr: Add NVDIMM device support

On Mon, May 13, 2019 at 04:28:02AM -0500, Shivaprasad G Bhat wrote: > Add support for NVDIMM devices for sPAPR. Piggyback on existing nvdimm > device interface in QEMU to support virtual NVDIMM devices for Power (May have > to re-look at this later). Create the required DT entries for the > device

Re: [Qemu-devel] [PATCH v11 00/12] Add RX archtecture support

ixed build errors and cleaned up the code. > > > > My git repository is bellow. > > git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git tags/rx-20190513 > > This tag isn't exactly the same as the series you posted, some patches > are ordered differently, leading

Re: [Qemu-devel] [PATCH v4 12/14] spapr/irq: initialize the IRQ device only once

On Mon, May 13, 2019 at 10:42:43AM +0200, Cédric Le Goater wrote: > Add a check to make sure that the routine initializing the emulated > IRQ device is called once. We don't have much to test on the XICS > side, so we introduce a 'init' boolean under ICSState. > > Signed-off-by: Cédric Le Goater

Re: [Qemu-devel] [PATCH v4 13/14] ppc/xics: fix irq priority in ics_set_irq_type()

On Mon, May 13, 2019 at 10:42:44AM +0200, Cédric Le Goater wrote: > Recent commits changed the behavior of ics_set_irq_type() to > initialize correctly LSIs at the KVM level. ics_set_irq_type() is also > called by the realize routine of the different devices of the machine > when initial interrupts

Re: [Qemu-devel] [PATCH v4 04/14] spapr/xive: add state synchronization with KVM

On Mon, May 13, 2019 at 10:42:35AM +0200, Cédric Le Goater wrote: > This extends the KVM XIVE device backend with 'synchronize_state' > methods used to retrieve the state from KVM. The HW state of the > sources, the KVM device and the thread interrupt contexts are > collected for the monitor usage

Re: [Qemu-devel] [Qemu-ppc] [PATCH v8 4/6] target/ppc: Build rtas error log upon an MCE

On Mon, May 13, 2019 at 01:30:53PM +0200, Greg Kurz wrote: > On Mon, 22 Apr 2019 12:33:26 +0530 > Aravinda Prasad wrote: > > > Upon a machine check exception (MCE) in a guest address space, > > KVM causes a guest exit to enable QEMU to build and pass the > > error to the guest in the PAPR defined

[Qemu-devel] [PULL 14/31] tcg: Add INDEX_op_dupm_vec

Allow the backend to expand dup from memory directly, instead of forcing the value into a temp first. This is especially important if integer/vector register moves do not exist. Note that officially tcg_out_dupm_vec is allowed to fail. If it did, we could fix this up relatively easily: VECE ==

[Qemu-devel] [PULL 30/31] target/xtensa: Use tcg_gen_abs_i32

Acked-by: Max Filippov Signed-off-by: Richard Henderson --- target/xtensa/translate.c | 9 + 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 301c8e3161..b063fa85f2 100644 --- a/target/xtensa/translate.c +++ b/target

[Qemu-devel] [PULL 01/31] tcg: Implement tcg_gen_gvec_3i()

From: David Hildenbrand Let's add tcg_gen_gvec_3i(), similar to tcg_gen_gvec_2i(), however without introducing "gen_helper_gvec_3i *fnoi", as it isn't needed for now. Reviewed-by: Alex Bennée Signed-off-by: David Hildenbrand Message-Id: <20190416185301.25344-2-da...@redhat.com> Signed-off-by:

Re: [Qemu-devel] [PATCH v1 1/1] target/arm: Fix vector operation segfault

On 5/13/19 5:08 PM, Alistair Francis wrote: > We hit the second switch case as > NEON_3R_VQADD and NEON_3R_VQSUB don't return from the function in the > first switch case. That's the bug, not here in this second switch. r~

[Qemu-devel] [PULL 23/31] tcg/aarch64: Support vector absolute value

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 +- tcg/aarch64/tcg-target.inc.c | 6 ++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 21d06d928c..e43554c3c7 100644 --- a/

[Qemu-devel] [PULL 25/31] target/cris: Use tcg_gen_abs_tl

Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/cris/translate.c | 9 + 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/target/cris/translate.c b/target/cris/translate.c index b005a5c20e..31b40a57f9 100644 --- a/target/cris/translate.c +++ b/target

[Qemu-devel] [PULL 00/31] tcg: gvec improvments

16:52:56 +0100) are available in the Git repository at: https://github.com/rth7680/qemu.git tags/pull-tcg-20190513 for you to fetch changes up to a7b6d286cfb5205b9f5330aefc5727269b3d810f: tcg/aarch64: Do not advertise minmax for MO_64 (2019-05-13

[Qemu-devel] [PATCH v1 1/1] target/arm: Fix vector operation segfault

Commit 89e68b575 "target/arm: Use vector operations for saturation" causes this abort() when booting QEMU ARM with a Cortex-A15: 0 0x74c2382f in raise () at /usr/lib/libc.so.6 1 0x74c0e672 in abort () at /usr/lib/libc.so.6 2 0x559c1839 in disas_neon_data_insn (insn=, s=

[Qemu-devel] [PULL 21/31] tcg: Add support for vector absolute value

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 5 +++ tcg/aarch64/tcg-target.h | 1 + tcg/i386/tcg-target.h| 1 + tcg/tcg-op-gvec.h| 2 ++ tcg/tcg-opc.h| 1 + tcg/tcg.h| 1 + accel/tcg

[Qemu-devel] [PULL 22/31] tcg/i386: Support vector absolute value

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 15 +++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7445f05885..66f16fbe3c 100644 --- a/tcg/i386/tcg-target.h +++

[Qemu-devel] [PULL 15/31] tcg: Add gvec expanders for variable shift

The gvec expanders perform a modulo on the shift count. If the target requires alternate behaviour, then it cannot use the generic gvec expanders anyway, and will have to have its own custom code. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 15

[Qemu-devel] [PULL 29/31] target/tricore: Use tcg_gen_abs_tl

From: Philippe Mathieu-Daudé Reviewed-by: Bastian Koppelmann Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20190423102145.14812-3-f4...@amsat.org> Signed-off-by: Richard Henderson --- target/tricore/translate.c | 27 +-- 1 file changed, 5 insertions(+), 22 deletio

[Qemu-devel] [PULL 05/31] tcg: Assert fixed_reg is read-only

The only fixed_reg is cpu_env, and it should not be modified during any TB. Therefore code that tries to special-case moves into a fixed_reg is dead. Remove it. Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- tcg/tcg.c | 87 +++

[Qemu-devel] [PULL 24/31] target/arm: Use tcg_gen_abs_i64 and tcg_gen_gvec_abs

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/helper.h| 2 -- target/arm/neon_helper.c | 5 - target/arm/translate-a64.c | 41 +- target/arm/translate.c | 11 +++--- 4 files changed, 8 insertions(+), 51 deleti

[Qemu-devel] [PULL 28/31] target/s390x: Use tcg_gen_abs_i64

Reviewed-by: David Hildenbrand Signed-off-by: Richard Henderson --- target/s390x/translate.c | 8 +--- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target/s390x/translate.c b/target/s390x/translate.c index d4951836ad..e8e8a79b7d 100644 --- a/target/s390x/translate.c +++ b/tar

[Qemu-devel] [PULL 27/31] target/ppc: Use tcg_gen_abs_tl

Signed-off-by: Richard Henderson --- target/ppc/translate.c | 68 +++--- 1 file changed, 24 insertions(+), 44 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 8d08625c33..b5217f632f 100644 --- a/target/ppc/translate.c +++ b/targe

[Qemu-devel] [PULL 10/31] tcg: Manually expand INDEX_op_dup_vec

This case is similar to INDEX_op_mov_* in that we need to do different things depending on the current location of the source. Signed-off-by: Richard Henderson --- v3: Added some commentary to the tcg_reg_alloc_* functions. --- tcg/aarch64/tcg-target.inc.c | 9 ++- tcg/i386/tcg-target.inc.c

[Qemu-devel] [PULL 31/31] tcg/aarch64: Do not advertise minmax for MO_64

The min/max instructions are not available for 64-bit elements. Fixes: 93f332a50371 Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 1248

[Qemu-devel] [PULL 09/31] tcg: Promote tcg_out_{dup, dupi}_vec to backend interface

The i386 backend already has these functions, and the aarch64 backend could easily split out one. Nothing is done with these functions yet, but this will aid register allocation of INDEX_op_dup_vec in a later patch. Adjust the aarch64 tcg_out_dupi_vec signature to match the new interface. Review

[Qemu-devel] [PULL 19/31] tcg/i386: Support vector scalar shift opcodes

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 2 +- tcg/i386/tcg-target.inc.c | 35 +++ 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index b240633455..618aa520d2 100644 --- a/tcg/i3

[Qemu-devel] [PULL 12/31] tcg/i386: Implement tcg_out_dupm_vec

At the same time, improve tcg_out_dupi_vec wrt broadcast from the constant pool. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 57 +-- 1 file changed, 43 insertions(+), 14 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-t

[Qemu-devel] [PULL 02/31] tcg: Do not recreate INDEX_op_neg_vec unless supported

Use tcg_can_emit_vec_op instead of just TCG_TARGET_HAS_neg_vec, so that we check the type and vece for the actual operation. Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- tcg/optimize.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/tcg/optimize.c b/

[Qemu-devel] [PULL 13/31] tcg/aarch64: Implement tcg_out_dupm_vec

The LD1R instruction does all the work. Note that the only useful addressing mode is a base register with no offset. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 37 ++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/tcg/aa

[Qemu-devel] [PULL 07/31] tcg: Return bool success from tcg_out_mov

This patch merely changes the interface, aborting on all failures, of which there are currently none. Reviewed-by: Alex Bennée Reviewed-by: David Hildenbrand Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: David Gibson Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 5 +

Re: [Qemu-devel] [PATCH] cadence_gem: Don't define GEM_INT_Q1_MASK twice

On Mon, May 13, 2019 at 12:57 PM Jonathan Behrens wrote: > > Signed-off-by: Jonathan Behrens Good find. Thanks for the patch! Reviewed-by: Alistair Francis Can this go via your tree Jason? Alistair > --- > hw/net/cadence_gem.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/hw/net/

Re: [Qemu-devel] [PATCH] configure: Disable slirp if --disable-system

On 5/11/19 5:47 AM, Aleksandar Markovic wrote: > > On May 10, 2019 10:36 PM, "Richard Henderson" > wrote: >> >> For linux-user, there is no need to add slirp to the set of >> git modules checked out, nor build it. >> >> This also avoids a makefile bug wrt insu

[Qemu-devel] [Bug 1828867] Re: QEmu translation is incorrect when using REX in combination with LAHF/SAHF

** Tags added: tcg testcase x86 -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1828867 Title: QEmu translation is incorrect when using REX in combination with LAHF/SAHF Status in QEMU: New Bug

Re: [Qemu-devel] [Qemu-block] [PATCH v3 1/3] block: introducing 'bdrv_co_delete_file' interface

It looks like this one has gone un-noticed for a little while. On 3/26/19 5:17 PM, Daniel Henrique Barboza wrote: > Adding to Block Drivers the capability of being able to clean up > its created files can be useful in certain situations. For the > LUKS driver, for instance, a failure in one of its

[Qemu-devel] [PATCH] cadence_gem: Don't define GEM_INT_Q1_MASK twice

Signed-off-by: Jonathan Behrens --- hw/net/cadence_gem.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 7f63411430..37cb8a4e5c 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -146,7 +146,6 @@ #define GEM_DESCONF7 (0x0

Re: [Qemu-devel] [PATCH v2] iotests: Filter 175's allocation information

On Mon, May 13, 2019, 18:52 Max Reitz wrote: > It is possible for an empty file to take up blocks on a filesystem. > Make iotest 175 take this into account. > > Reported-by: Thomas Huth > Signed-off-by: Max Reitz > --- > v2: [Nir] > - Use a function for filtering > - s/empty_blocks/extra_blocks

Re: [Qemu-devel] [PATCH 00/13] target/arm/kvm: enable SVE in guests

On Mon, May 13, 2019 at 11:46:29AM -0700, Richard Henderson wrote: > On 5/12/19 1:36 AM, Andrew Jones wrote: > >CPU type | accel | sve-max-vq | sve-vls-map > >--- > > 1) max | tcg | $MAX_VQ | $VLS_MAP > > 2) max | kvm | $MAX_VQ |

Re: [Qemu-devel] [Qemu-block] [PATCH] nvme: add Get/Set Feature Timestamp support

On 4/9/19 9:19 AM, Stefan Hajnoczi wrote: > On Fri, Apr 05, 2019 at 03:41:17PM -0600, Kenneth Heitke wrote: >> Signed-off-by: Kenneth Heitke >> --- >> hw/block/nvme.c | 120 +- >> hw/block/nvme.h | 3 ++ >> hw/block/trace-events | 2 + >>

[Qemu-devel] [Bug 1823458] Update Released

The verification of the Stable Release Update for qemu has completed successfully and the package has now been released to -updates. In the event that you encounter a regression using the package from -updates please report a new bug using ubuntu-bug and tag the bug report regression-update so we c

[Qemu-devel] [Bug 1823458] Re: race condition between vhost_net_stop and CHR_EVENT_CLOSED on shutdown crashes qemu

This bug was fixed in the package qemu - 1:2.8+dfsg-3ubuntu2.9~cloud5.1 --- qemu (1:2.8+dfsg-3ubuntu2.9~cloud5.1) xenial-ocata; urgency=medium . * d/p/lp1823458/add-VirtIONet-vhost_stopped-flag-to-prevent-multiple.patch, d/p/lp1823458/do-not-call-vhost_net_cleanup-on-running-

[Qemu-devel] [Bug 1823458] Re: race condition between vhost_net_stop and CHR_EVENT_CLOSED on shutdown crashes qemu

This bug was fixed in the package qemu - 1:2.5+dfsg-5ubuntu10.37~cloud0 --- qemu (1:2.5+dfsg-5ubuntu10.37~cloud0) trusty-mitaka; urgency=medium . * New update for the Ubuntu Cloud Archive. . qemu (1:2.5+dfsg-5ubuntu10.37) xenial; urgency=medium . * d/p/lp1823458/add-VirtIONe

[Qemu-devel] [Bug 1823458] Update Released

The verification of the Stable Release Update for qemu has completed successfully and the package has now been released to -updates. In the event that you encounter a regression using the package from -updates please report a new bug using ubuntu-bug and tag the bug report regression-update so we c

[Qemu-devel] [PATCH v7 8/8] hw/display: add vhost-user-vga & gpu-pci

Add new virtio-gpu devices with a "vhost-user" property. The associated vhost-user backend is used to handle the virtio rings and provide rendering results thanks to the vhost-user-gpu protocol. Example usage: -object vhost-user-backend,id=vug,cmd="./vhost-user-gpu" -device vhost-user-vga,vhost-us

[Qemu-devel] [PATCH v7 5/8] contrib: add vhost-user-gpu

Add a vhost-user gpu backend, based on virtio-gpu/3d device. It is to be associated with a vhost-user-gpu device. Various TODO and nice to have items: - multi-head support - crash & resume handling - accelerated rendering/display that avoids the waiting round trips - edid support Signed-off-by: M

Re: [Qemu-devel] [PATCH 00/13] target/arm/kvm: enable SVE in guests

On 5/12/19 1:36 AM, Andrew Jones wrote: >CPU type | accel | sve-max-vq | sve-vls-map >--- > 1) max | tcg | $MAX_VQ | $VLS_MAP > 2) max | kvm | $MAX_VQ | $VLS_MAP > 3)host | kvm | N/A | $VLS_MAP This doesn't seem r

[Qemu-devel] [PATCH v7 7/8] virtio-gpu: split virtio-gpu-pci & virtio-vga

Add base classes that are common to vhost-user-gpu-pci and vhost-user-vga. Signed-off-by: Marc-André Lureau --- hw/display/virtio-vga.h | 32 + hw/display/virtio-gpu-pci.c | 52 +- hw/display/virtio-vga.c | 135 ++-- MAINTAINERS

[Qemu-devel] [PATCH v7 3/8] virtio-gpu: add a pixman helper header

This will allow to share the format conversion function with vhost-user-gpu. Signed-off-by: Marc-André Lureau --- include/hw/virtio/virtio-gpu-pixman.h | 45 +++ hw/display/virtio-gpu.c | 29 ++--- 2 files changed, 48 insertions(+), 26 deletions(

[Qemu-devel] [PATCH v7 6/8] virtio-gpu: split virtio-gpu, introduce virtio-gpu-base

Add a base class that is common to virtio-gpu and vhost-user-gpu devices. The VirtIOGPUBase base class provides common functionalities necessary for both virtio-gpu and vhost-user-gpu: - common configuration (max-outputs, initial resolution, flags) - virtio device initialization, including queue s

[Qemu-devel] [PATCH v7 4/8] util: compile drm.o on Linux

OpenGL isn't required to use DRM rendernodes. The following patches uses it for 2d resources for ex. Signed-off-by: Marc-André Lureau --- util/Makefile.objs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/Makefile.objs b/util/Makefile.objs index 9206878dec..657d59df3f 10

[Qemu-devel] [PATCH v7 1/8] vhost-user: add vhost_user_gpu_set_socket()

Add a new vhost-user message to give a unix socket to a vhost-user backend for GPU display updates. Back when I started that work, I added a new GPU channel because the vhost-user protocol wasn't bidirectional. Since then, there is a vhost-user-slave channel for the slave to send requests to the m

[Qemu-devel] [PATCH v7 2/8] virtio-gpu: add bswap helpers header

The helper functions are useful to build the vhost-user-gpu backend. Signed-off-by: Marc-André Lureau --- include/hw/virtio/virtio-gpu-bswap.h | 61 hw/display/virtio-gpu.c | 43 +--- 2 files changed, 62 insertions(+), 42 deletions(-) cr

[Qemu-devel] [PATCH v7 0/8] Add vhost-user-gpu

Hi, vhost-user allows to drive a virtio device in a seperate process. After vhost-user-net, we have seen vhost-user-{scsi,blk,crypto,input} added more recently. This series, initially proposed ~3 years ago, time flies (https://lists.gnu.org/archive/html/qemu-devel/2016-06/msg01905.html) contribut

Re: [Qemu-devel] How do we do user input bitmap properties?

On Thu, Apr 18, 2019 at 07:48:09PM +0200, Markus Armbruster wrote: > Daniel P. Berrangé writes: > > > On Thu, Apr 18, 2019 at 11:28:41AM +0200, Andrew Jones wrote: > >> Hi all, > >> > >> First some background: > >> > >> For the userspace side of AArch64 guest SVE support we need to > >> expose

[Qemu-devel] [PATCH v3 1/3] libvhost-user: fix cast warnings on 32 bits

Fixes warnings: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Signed-off-by: Marc-André Lureau --- contrib/libvhost-user/libvhost-user.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/contrib/libvhost-user/libvhost-user.c b/contrib/

[Qemu-devel] [PATCH v3 3/3] contrib: add vhost-user-input

Add a vhost-user input backend example, based on virtio-input-host device. It takes an evdev path as argument, and can be associated with a vhost-user-input device via a UNIX socket: $ vhost-user-input -p /dev/input/eventX -s /tmp/vui.sock $ qemu ... -chardev socket,id=vuic,path=/tmp/vui.sock -

[Qemu-devel] [PATCH v3 0/3] Add vhost-user-input

Hi, v3: - rebased, fixing some warnings found during merge v2: - build fixes v1: (changes since original v6 series) - add "libvhost-user: fix -Waddress-of-packed-member" & "util: simplify unix_listen()" - use unix_listen() - build vhost-user-input by default (when applicable) Marc-André Lureau

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