On Mon, 2019-02-11 at 12:06 +0100, Marek Vasut wrote:
> On 2/11/19 7:23 AM, Chee, Tien Fong wrote:
> >
> > On Tue, 2019-02-05 at 09:51 +0100, Marek Vasut wrote:
> > >
> > > On 2/1/19 5:50 PM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Fri, 2019-02-01 at 09:29 +0100, Marek Vasut wrote:
>
On 2/11/19 7:23 AM, Chee, Tien Fong wrote:
> On Tue, 2019-02-05 at 09:51 +0100, Marek Vasut wrote:
>> On 2/1/19 5:50 PM, Chee, Tien Fong wrote:
>>>
>>> On Fri, 2019-02-01 at 09:29 +0100, Marek Vasut wrote:
On 2/1/19 4:59 AM, Chee, Tien Fong wrote:
>
>
> On Thu, 2019-01-31 at 1
On Tue, 2019-02-05 at 09:51 +0100, Marek Vasut wrote:
> On 2/1/19 5:50 PM, Chee, Tien Fong wrote:
> >
> > On Fri, 2019-02-01 at 09:29 +0100, Marek Vasut wrote:
> > >
> > > On 2/1/19 4:59 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
> >
On 2/1/19 5:50 PM, Chee, Tien Fong wrote:
> On Fri, 2019-02-01 at 09:29 +0100, Marek Vasut wrote:
>> On 2/1/19 4:59 AM, Chee, Tien Fong wrote:
>>>
>>> On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
>
>
> From: Tien Fon
On Fri, 2019-02-01 at 09:29 +0100, Marek Vasut wrote:
> On 2/1/19 4:59 AM, Chee, Tien Fong wrote:
> >
> > On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
> > >
> > > On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
> > > >
> > > > Add defa
On 2/1/19 4:59 AM, Chee, Tien Fong wrote:
> On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
>> On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee
>>>
>>> Add default fitImage file bundling FPGA bitstreams for Arria10.
>>>
>>> Signed-off-by: Tien Fong Chee
>>> -
On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
> On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> >
> > From: Tien Fong Chee
> >
> > Add default fitImage file bundling FPGA bitstreams for Arria10.
> >
> > Signed-off-by: Tien Fong Chee
> > ---
> > board/altera/arria10-socdk/fit_spl
On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add default fitImage file bundling FPGA bitstreams for Arria10.
>
> Signed-off-by: Tien Fong Chee
> ---
> board/altera/arria10-socdk/fit_spl_fpga.its | 31
> +
> 1 file changed, 31 inser
From: Tien Fong Chee
Add default fitImage file bundling FPGA bitstreams for Arria10.
Signed-off-by: Tien Fong Chee
---
board/altera/arria10-socdk/fit_spl_fpga.its | 31 +
1 file changed, 31 insertions(+)
create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.it
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