Hi Simon
On 09/25/2017 04:15 AM, Simon Glass wrote:
> On 22 September 2017 at 09:37, wrote:
>> From: Nicolas Le Bayon
>>
>> 32MB are reserved for Trusted Zone purpose
>
> Isn't this called TrustZone ?
Correct, i will send a v3 with this typo fix
>
>>
>> Signed-off-by: Nicolas Le Bayon
>> -
From: Patrice Chotard
Update the CONFIG_EXTRA_ENV_SETTINGS, BOOT_TARGET_DEVICES and CONFIG_BOOTARGS
Fix SDRAM size
v3: fix typo in patch 2
v2: rebase on v2017.09
Lee Jones (1):
board: STiH410-B2260: set ramdisk_addr_r to 0x4800
Nicolas Le Bayon (1):
board: STiH410-B2260: fix sdram size
From: Lee Jones
Add missing ramdisk_addr_r param and set it to 0x4800
Signed-off-by: Lee Jones
Reviewed-by: Simon Glass
---
v3: none
v2: rebase on v2017.09
include/configs/stih410-b2260.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/stih410-b2260.h b/include/confi
From: Nicolas Le Bayon
32MB are reserved for TrustZone purpose
Signed-off-by: Nicolas Le Bayon
---
v3: fix typo, replace "Trusted Zone" by "TrustZone"
v2: rebase on v2017.09
include/configs/stih410-b2260.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/sti
From: Patrice Chotard
Update environment variable by updating:
_ BOOT_TARGET_DEVICE
_ CONFIGS_BOOTARGS
_ kernel_addr_r, fdtfile, fdt_addr_r, scriptaddr, fdt_high, intird_high
Signed-off-by: Patrice Chotard
Reviewed-by: Simon Glass
---
v3: none
v2: rebase on v2017.09
configs/stih410-b2260_
On Wed, Aug 30, 2017 at 8:56 PM, Jagan Teki wrote:
> On Wed, Aug 30, 2017 at 8:06 PM, Suresh Gupta wrote:
>> It is recommended to check either controller is free to take
>> new spi action. The IP_ACC and AHB_ACC bits indicates that
>> the controller is busy in IP or AHB mode respectively.
>> And
On Thu, Aug 31, 2017 at 7:43 PM, Jagan Teki wrote:
> On Thu, Aug 31, 2017 at 10:26 AM, Yogesh Gaur
> wrote:
>> Add MT35XU512ABA1G12 parameters to NOR flash parameters array.
>>
>> The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support
>> dual and quad. Supports subsector erase
From: zijun_hu
macro branch_if_master checks master CPU via (Aff3 & (Aff2:Aff1:Aff0))
it is simple but a little obscure.
fix by checking Affx fields within MPIDR_EL1 directly.
Signed-off-by: zijun_hu
---
arch/arm/include/asm/macro.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm
On Fri, Sep 15, 2017 at 2:45 AM, Marek Vasut wrote:
> The flash chip is 2 MiB , organized as 32 x 64 kiB sectors .
> Rectify the entry to match the datasheet, reality and Linux SNOR IDs.
>
> Signed-off-by: Marek Vasut
> Cc: Jagan Teki
Applied to u-boot-spi/master
thanks!
--
Jagan Teki
Free So
On Fri, Sep 15, 2017 at 7:51 PM, Vsevolod Gribov
wrote:
> Spansion S25FS256S and S25FL256S flashes have equal JEDEC ID and ext ID.
> As far as S25FL256S occures in spi_flash_ids before S25FS256S, U-Boot
> incorrectly detects FS flash as FL. Thus its better to compare with
> S25FS256S first.
> ---
Hi Vikas
On 09/19/2017 12:40 AM, Vikas Manocha wrote:
> Hi Patrice,
>
> On 09/13/2017 09:00 AM, patrice.chot...@st.com wrote:
>> From: Patrice Chotard
>>
>> STM32F7 and STM32H7 shares the same UART block, add
>> STM32H7 compatible string.
>>
>> Signed-off-by: Patrice Chotard
>> ---
>> drivers
Hi Vikas
On 09/20/2017 03:39 AM, Vikas Manocha wrote:
> Hi Patrice,
>
> On 09/13/2017 09:00 AM, patrice.chot...@st.com wrote:
>> From: Patrice Chotard
>>
>> This driver implements basic clock setup, only clock gating
>> is implemented.
>>
>> This driver doesn't implement .of_match as it's binded
Hi Tom,
Please pull this PR.
thanks!
Jagan.
The following changes since commit 1f6049e2501b5c35c61435dbc05ba96743202674:
tools/mkimage: Make the path to the dtc binary that mkimage calls
configurable (2017-09-24 07:33:03 -0400)
are available in the git repository at:
git://git.denx.de/u-
Dear Tom,
In message <1506263222-7080-1-git-send-email-tr...@konsulko.com> you wrote:
>
> The following series has been applied. I am posting this for the record.
Argghhh... This is not the way things should be done.
I am definitely unhappy here - not so much about the patches, but
about the p
Hi Duncan,
make menuconfig
HOSTCC scripts/kconfig/mconf.o
In file included from scripts/kconfig/mconf.c:23:0:
scripts/kconfig/lxdialog/dialog.h:26:20: fatal error: curses.h: No such file or
directory
#include CURSES_LOC
It seems like you are missing ncurses5-dev package.
Appears CURS
On 09/24/2017 07:28 PM, Tom Rini wrote:
> On Sun, Sep 24, 2017 at 06:50:01PM +0200, Marek Vasut wrote:
>> On 09/24/2017 04:26 PM, Tom Rini wrote:
>>> The following series has been applied. I am posting this for the record.
>>>
>>> For the record, I do not believe that using git submodules is a goo
RK3188 using the same ddr_conf for both 15 bit and 16 bit row address.
Signed-off-by: Kever Yang
---
drivers/ram/rockchip/sdram_rk3188.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/ram/rockchip/sdram_rk3188.c
b/drivers/ram/rockchip/sdram_rk3188.c
index 9
On 09/25/2017 04:14 AM, Simon Glass wrote:
> Hi Marek,
>
> On 24 September 2017 at 07:05, Marek Vasut wrote:
>> On 09/24/2017 02:52 PM, Tom Rini wrote:
>>> On Sun, Sep 24, 2017 at 02:07:27PM +0200, Marek Vasut wrote:
On 09/24/2017 01:36 PM, Tom Rini wrote:
> On Sun, Sep 24, 2017 at 10:28
On 09/25/2017 02:37 AM, ali...@peloton-tech.com wrote:
From: Alison Chaiken
Create a common exit for most of the error handling code in
do_rename_gpt_parts. Delete the list elements in disk_partitions
before calling INIT_LIST_HEAD from get_gpt_info() a second time.
The SIZEOF_MISMATCH error
From: Tien Fong Chee
This patchset adding FPGA and SDRAM drivers, enable fpga loadfs to program FPGA
, SPL loading U-boot and booting to U-boot console. This version mainly resolved
comments from Marek in [v1].
This series is working on top of u-boot.git - http://git.denx.de/u-boot.git .
[v1]: h
From: Tien Fong Chee
This patch adds description on properties about location of FPGA RBFs are
stored, type and functionality of RBF used to configure FPGA.
Signed-off-by: Tien Fong Chee
---
doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt | 11 +++
1 file changed, 11 inse
From: Tien Fong Chee
This DT binding doc is porting from Linux DT binding doc.
commit 1adcbea4201a6852362aa5ece573f1f169b28113
Add a device tree bindings document for the SoCFPGA Arria10
FPGA Manager driver.
Signed-off-by: Alan Tull
Acked-by: Rob Herring
Acked-By: Moritz Fischer
Signed-off-b
From: Tien Fong Chee
Existing FPGA program write is always assume RBF data >= 32 bytes, so
any rbf data less than 32 bytes writing to FPGA would be failed.
This patch enhances the FPGA program write to support rbf data with
size >= 4 bytes.
Signed-off-by: Tien Fong Chee
---
drivers/fpga/socfpg
From: Tien Fong Chee
Add code necessary into the FPGA driver framework in U-Boot
so it can be used via the 'fpga' command for programing Arria 10
SoCFPGA.
Signed-off-by: Tien Fong Chee
---
cmd/fpga.c| 2 +-
drivers/fpga/altera.c | 39 +++
driver
From: Tien Fong Chee
These FPGA bitstream properties would help bootloader to understand
how to configure FPGA and where to look the FPGA RBF files during
booting.
Signed-off-by: Tien Fong Chee
---
arch/arm/dts/socfpga_arria10.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/ar
From: Tien Fong Chee
This patch is for enabling the DDR support on Arria 10.
Signed-off-by: Tien Fong Chee
---
drivers/ddr/altera/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index ac4ab85..02f8b7c 100644
--- a/drivers/d
From: Tien Fong Chee
Current sdram driver is only applied to gen5 device, hence it is better
to rename sdram driver to more specific name which is related to gen5
device.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/sdram.h | 434 +
.../inclu
From: Tien Fong Chee
Add DDR driver suppport for Arria 10.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/sdram.h | 2 +
arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
drivers/ddr/altera/sdram_arria10.c | 735 +
From: Tien Fong Chee
Add compatible strings for Intel Arria 10 SoCFPGA device.
Signed-off-by: Tien Fong Chee
---
include/fdtdec.h | 2 ++
lib/fdtdec.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 4a0947c..095ff36 100644
--- a/include/fdtd
From: Tien Fong Chee
Add support to memory allocation in SPL for preparation to enable FAT
in SPL. Memory allocation is needed by FAT to work properly.
Signed-off-by: Tien Fong Chee
---
include/configs/socfpga_common.h | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(
From: Tien Fong Chee
Add function for both multiple DRAM bank and single DRAM bank size
initialization. This common functionality could be used by every single
SOCFPGA board.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/board.c| 7 +++
include/configs/socfpga_common.h | 1 +
From: Tien Fong Chee
These drivers handle FPGA program operation from flash loading
RBF to memory and then to program FPGA.
Signed-off-by: Tien Fong Chee
---
.../include/mach/fpga_manager_arria10.h| 27 ++
drivers/fpga/socfpga_arria10.c | 391 ++
Hi Philipp, Heiko:
I finally got the upstream u-boot run on a rk3188 board which can be
attached by DS5 debugger,
if you have some registers info want to check, please let me know.
On 2017年09月21日 18:44, Heiko Stübner wrote:
Am Donnerstag, 21. September 2017, 12:25:17 CEST schrieb Dr. Phili
From: Tien Fong Chee
Clock frequency info is required in U-boot.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/board.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 965f9dc..a00f63b 100644
--- a/arch/arm/
From: Tien Fong Chee
fpga-mgr node is required in SPL, because SPL needs information
from the node to configure FPGA in Arria 10.
Signed-off-by: Tien Fong Chee
---
arch/arm/dts/socfpga_arria10.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/socfpga_arria10.dtsi
b/arch/ar
From: Tien Fong Chee
Enable generic filesystem interface drivers(fs.c and fat/) build
for SPL. This would allow generic filesystem being used in SPL.
Signed-off-by: Tien Fong Chee
---
common/spl/Kconfig | 8
doc/README.SPL | 1 +
fs/Makefile| 1 +
3 files changed, 10 inser
From: Tien Fong Chee
This patch enables DDR Kconfig support for Arria 10.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/Kconfig | 1 +
drivers/ddr/altera/Kconfig| 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-soc
Hi Jagan,
Hi Tom,
Please pull this PR.
Would you find some time and look into following patch:
http://patchwork.ozlabs.org/patch/813266/
Thanks in advance,
Łukasz
thanks!
Jagan.
The following changes since commit 1f6049e2501b5c35c61435dbc05ba96743202674:
tools/mkimage: Make the path
From: Tien Fong Chee
Enhance preloader header with both additional program length and program
entry offset attributes, which offset is relative to the start of program
header.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/boot0.h | 11 +--
1 file changed, 9 inser
From: Tien Fong Chee
SoC FPGA info is required in both SPL and U-boot.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/board.c| 3 +++
arch/arm/mach-socfpga/misc_arria10.c | 5 -
arch/arm/mach-socfpga/spl.c | 6 ++
3 files changed, 9 insertions(+), 5 deletions(
From: Tien Fong Chee
Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/spl.c | 55 +
common/spl/spl_mmc.c | 2 +-
configs/socfpga_arria10_defconfig | 57 +++
On Mon, Sep 25, 2017 at 2:11 PM, Łukasz Majewski wrote:
> Hi Jagan,
>
>> Hi Tom,
>>
>> Please pull this PR.
>
>
> Would you find some time and look into following patch:
>
> http://patchwork.ozlabs.org/patch/813266/
Of-course, will comment on respective patch itself.
thanks!
--
Jagan Teki
Free
Andy,
Excellent news.
Looks like Heiko and I figured out what breaks the series last week (i.e. the
SPL corrupts
the TPL’s stack—so my chaining will break things).
I’ll resubmit without the chained returns later and then we can have a final
test tomorrow.
Regards,
Philipp.
> On 25 Sep 2017, a
The intent of this patch is to create the initial files necessary to
support the nyan-kitty device by copying nyan-big files and renaming all
the nyan-big references and tags to be nyan-kitty.
This will make a u-boot that will act exactly like the nyan-big build,
except will say "nyan-kitty" where
From: Tien Fong Chee
This DT binding doc is porting from Linux DT binding doc.
commit 1adcbea4201a6852362aa5ece573f1f169b28113
Add a device tree bindings document for the SoCFPGA Arria10
FPGA Manager driver.
Signed-off-by: Alan Tull
Acked-by: Rob Herring
Acked-By: Moritz Fischer
Signed-off-b
Marek Vasut wrote:
> On 09/22/2017 04:00 PM, David Müller (ELSOFT AG) wrote:
>> On my custom MX6Q board, the code hangs on the read of the
>> "PCIE_PL_PFLR". Please note that this code sequence is not entered
>> the first time after a power up; I have to execute a U-Boot reset
>> to actually trig
Hi Heiko:
On 2017年09月22日 13:56, Heiko Stuebner wrote:
Am Freitag, 22. September 2017, 08:50:49 CEST schrieb Andy Yan:
Hi Heiko:
On 2017年09月22日 08:24, Andy Yan wrote:
Hi Heiko:
On 2017年09月21日 22:55, Heiko Stübner wrote:
Hi Andy,
Am Donnerstag, 21. September 2017, 22:03:32 CEST schrieb An
On 09/25/2017 10:39 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> This DT binding doc is porting from Linux DT binding doc.
> commit 1adcbea4201a6852362aa5ece573f1f169b28113
>
> Add a device tree bindings document for the SoCFPGA Arria10
> FPGA Manager driver.
>
> Signed-off-by
On 09/25/2017 10:39 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> This patch adds description on properties about location of FPGA RBFs are
> stored, type and functionality of RBF used to configure FPGA.
>
> Signed-off-by: Tien Fong Chee
Why does this patch have different tags
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add code necessary into the FPGA driver framework in U-Boot
> so it can be used via the 'fpga' command for programing Arria 10
> SoCFPGA.
>
> Signed-off-by: Tien Fong Chee
> ---
[...]
> +#if defined(CONFIG_CMD_
On 09/25/2017 10:39 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> This patch adds description on properties about location of FPGA RBFs are
> stored, type and functionality of RBF used to configure FPGA.
>
> Signed-off-by: Tien Fong Chee
> ---
> doc/device-tree-bindings/fpga/a
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add compatible strings for Intel Arria 10 SoCFPGA device.
>
> Signed-off-by: Tien Fong Chee
Applied, thanks
> ---
> include/fdtdec.h | 2 ++
> lib/fdtdec.c | 2 ++
> 2 files changed, 4 insertions(+)
>
> d
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Current sdram driver is only applied to gen5 device, hence it is better
> to rename sdram driver to more specific name which is related to gen5
> device.
>
> Signed-off-by: Tien Fong Chee
> ---
> arch/arm/mach-s
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> These drivers handle FPGA program operation from flash loading
> RBF to memory and then to program FPGA.
>
> Signed-off-by: Tien Fong Chee
Did you run checkpatch on this before submitting ? I presume no ...
> -
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add function for both multiple DRAM bank and single DRAM bank size
> initialization. This common functionality could be used by every single
> SOCFPGA board.
>
> Signed-off-by: Tien Fong Chee
I'd like TB on Gen5
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add DDR driver suppport for Arria 10.
>
> Signed-off-by: Tien Fong Chee
> ---
> arch/arm/mach-socfpga/include/mach/sdram.h | 2 +
> arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
> drive
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Existing FPGA program write is always assume RBF data >= 32 bytes, so
> any rbf data less than 32 bytes writing to FPGA would be failed.
> This patch enhances the FPGA program write to support rbf data with
> size
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Enhance preloader header with both additional program length and program
> entry offset attributes, which offset is relative to the start of program
> header.
>
> Signed-off-by: Tien Fong Chee
> ---
> arch/arm/m
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> This patch is for enabling the DDR support on Arria 10.
>
> Signed-off-by: Tien Fong Chee
> ---
> drivers/ddr/altera/Makefile | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/ddr/altera/Makefile
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Enable generic filesystem interface drivers(fs.c and fat/) build
> for SPL. This would allow generic filesystem being used in SPL.
>
> Signed-off-by: Tien Fong Chee
+CC Simon, I'd like a RB on this one.
> ---
>
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Clock frequency info is required in U-boot.
>
> Signed-off-by: Tien Fong Chee
I want a TB on Gen 5
> ---
> arch/arm/mach-socfpga/board.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.
This patch seems to be doing more than just one thing ...
> Signed-off-by: Tien Fong Chee
> ---
> arch/arm/mach-socfpga/spl.c | 55 +
On 09/25/2017 11:05 AM, David Müller (ELSOFT AG) wrote:
> Marek Vasut wrote:
>
>> On 09/22/2017 04:00 PM, David Müller (ELSOFT AG) wrote:
>>> On my custom MX6Q board, the code hangs on the read of the
>>> "PCIE_PL_PFLR". Please note that this code sequence is not entered
>>> the first time after
On 09/25/2017 10:40 AM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee
>
> Add support to memory allocation in SPL for preparation to enable FAT
> in SPL. Memory allocation is needed by FAT to work properly.
>
> Signed-off-by: Tien Fong Chee
Gen 5 does have malloc support in SPL, so wh
On Wed, Sep 13, 2017 at 3:09 PM, Lukasz Majewski wrote:
> The content of Bank Address Register (BAR) is volatile. It is cleared
> after power cycle or reset command (RESET F0h).
>
> Some memories (like e.g. s25fl256s) use it to access memory larger than
> 0x100 (16 MiB).
>
> The problem shows
On Fri, Sep 22, 2017 at 09:57:22PM +, Andre Przywara wrote:
> The sunxi-specific SPI load routine only knows how to load a legacy
> U-Boot image.
> Teach it how to handle FIT images as well, simply by providing the
> existing SPL FIT loader with the right loader routine to access the SPI
> NOR
On Mon, Sep 18, 2017 at 7:13 AM, Adam Ford wrote:
> A few small additional items are needed to support DM_SPI and
> DM_SERIAL, so those were added to da850-evm-u-boot.dtsi
>
> Signed-off-by: Adam Ford
> ---
> V4: Re-sync with latest master
> V3: New to series. I forgot to generate this before. T
On Mon, Jun 5, 2017 at 2:37 PM, Suresh Gupta wrote:
> In some of the QSPI controller version, there must be atleast
> 128bit data available in TX FIFO for any pop operation otherwise
> error bit will be set. The code will not make any behavior change
> for previous controller as the transfer data
Hi Jagan,
On Wed, Sep 13, 2017 at 3:09 PM, Lukasz Majewski wrote:
The content of Bank Address Register (BAR) is volatile. It is cleared
after power cycle or reset command (RESET F0h).
Some memories (like e.g. s25fl256s) use it to access memory larger than
0x100 (16 MiB).
The problem show
Hi Andy,
Am Montag, 25. September 2017, 17:45:03 CEST schrieb Andy Yan:
> On 2017年09月22日 13:56, Heiko Stuebner wrote:
> > Am Freitag, 22. September 2017, 08:50:49 CEST schrieb Andy Yan:
> >> Hi Heiko:
> >>
> >> On 2017年09月22日 08:24, Andy Yan wrote:
> >>> Hi Heiko:
> >>>
> >>> On 2017年09月21日 22:5
The content of Bank Address Register (BAR) is volatile. It is cleared
after power cycle or reset command (RESET F0h).
Some memories (like e.g. s25fl256s) use it to access memory larger than
0x100 (16 MiB).
The problem shows up when one:
1. Reads/writes/erases memory > 16 MiB
2. Calls "reset"
On Friday 18 August 2017 01:00 PM, Jaehoon Chung wrote:
> On 08/04/2017 06:34 PM, Suniel Mahesh wrote:
>> On Monday 17 July 2017 04:38 PM, Jaehoon Chung wrote:
>>> On 06/20/2017 01:53 AM, suni...@techveda.org wrote:
From: Suniel Mahesh
priv pointer should be freed before returning w
On Sat, Sep 23, 2017 at 05:59:15PM +, Antony Antony wrote:
> Add initial DT for NanoPi NEO Plus2 by FriendlyARM
> - Allwinner quad core H5 Cortex A53 with an ARM Mali-450MP GPU
> - 1 GB DDR3 RAM
> - 8GB eMMC flash (Samsung KLM8G1WEPD-B031)
> - micro SD card slot
> - Gigabit Ethernet (external R
Hi Heiko:
On 2017年09月25日 18:29, Heiko Stübner wrote:
Hi Andy,
Am Montag, 25. September 2017, 17:45:03 CEST schrieb Andy Yan:
On 2017年09月22日 13:56, Heiko Stuebner wrote:
Am Freitag, 22. September 2017, 08:50:49 CEST schrieb Andy Yan:
Hi Heiko:
On 2017年09月22日 08:24, Andy Yan wrote:
Hi Heiko
Am Montag, 25. September 2017, 19:49:01 CEST schrieb Andy Yan:
> Hi Heiko:
>
> On 2017年09月25日 18:29, Heiko Stübner wrote:
> > Hi Andy,
> >
> > Am Montag, 25. September 2017, 17:45:03 CEST schrieb Andy Yan:
> >> On 2017年09月22日 13:56, Heiko Stuebner wrote:
> >>> Am Freitag, 22. September 2017, 08:5
On Sep 25, 2017 3:11 AM, "Jagan Teki" wrote:
On Mon, Sep 18, 2017 at 7:13 AM, Adam Ford wrote:
> A few small additional items are needed to support DM_SPI and
> DM_SERIAL, so those were added to da850-evm-u-boot.dtsi
>
> Signed-off-by: Adam Ford
> ---
> V4: Re-sync with latest master
> V3: New
Hi Fabio,
On 23/09/2017 17:11, Fabio Estevam wrote:
> On Sat, Sep 23, 2017 at 10:01 AM, Fabio Estevam wrote:
>> Hi Stefano,
>>
>> On Sat, Sep 23, 2017 at 5:43 AM, Stefano Babic wrote:
>>
>>> Max has already fixed apalis / colibri, see for example
>>> http://patchwork.ozlabs.org/patch/817053/. I
On 24/09/2017 13:27, Max Krummenacher wrote:
> Hi
>
>
> I propose to drop my patches in favor of Fabio's solution.
>
>
Agree, I will merge them.
Regards,
Stefano
> Reviewed-by: Max Krummenacher
>
>
> Max
>
>
> *Von
On 30/08/2017 08:14, Peng Fan wrote:
> Typo fix: CONIFG->CONFIG
>
> Signed-off-by: Peng Fan
> Cc: Tom Rini
> ---
>
> V2: new
> V3: none
> V4: none
>
> scripts/Makefile.uncmd_spl | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/scripts/Makefile.uncmd_spl b/scripts/Make
Hi Peng,
On 30/08/2017 08:14, Peng Fan wrote:
> Enable DM MMC/I2C/PMIC/GPIO/REGULATOR.
>
> Signed-off-by: Peng Fan
> Cc: Fabio Estevam
> Cc: Stefano Babic
> ---
>
> V2->V4: none
>
> board/freescale/mx6sabresd/mx6sabresd.c | 326
> +---
> configs/mx6sabresd_defco
Hi York,
If you don't mind, I would like to ask you for some help and
clarification regarding your work.
Add jump_to_image_linux() for arm64. Add "noreturn" flag to
armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon
boot.
I'm trying to do the same on imx6q board (armv7).
On 09/25/2017 04:17 PM, Łukasz Majewski wrote:
Nit -- Eanble in subject .
^^ Enable
Best regards,
Marek Vasut
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On Fri, Sep 22, 2017 at 7:00 AM, David Müller (ELSOFT AG)
wrote:
> Hello
>
> Does the code below really work?
Hi Dave,
This patch does work to resolve the issue stated in the commit log
which was to fix failing to boot on a 4.11+ kernel which stems from
the fact that we have no reliable way to r
Marek,
The latest u-boot-usb master branch breaks the following unit tests for
the sandbox target (as run by test/py):
8 failed
... test_ut[ut_dm_blk_usb]
... test_ut[ut_dm_usb_flash]
... test_ut[ut_dm_usb_keyb]
... test_ut[ut_dm_usb_multi]
... test_ut[ut_dm_usb_remove]
... test_ut[ut_dm_usb_t
The following changes since commit 1f6049e2501b5c35c61435dbc05ba96743202674:
tools/mkimage: Make the path to the dtc binary that mkimage calls
configurable (2017-09-24 07:33:03 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-usb.git master
for you to fetch changes up
On 09/15/2017 09:10 PM, Marek Vasut wrote:
> Add initial support for setting the vqmmc regulator. Since we do not
> support 1V8 modes, set the regulator to 3V3 and enable it.
>
> Signed-off-by: Marek Vasut
> Cc: Masahiro Yamada
> Cc: Jaehoon Chung
Anything ?! I don't see this in the PR ...
>
On 09/25/2017 06:13 PM, Stephen Warren wrote:
> Marek,
+CC Bin
I will drop the xhci patchset and hope to get a fixed one from him.
> The latest u-boot-usb master branch breaks the following unit tests for
> the sandbox target (as run by test/py):
>
> 8 failed
> ... test_ut[ut_dm_blk_usb]
> ...
On 09/25/2017 07:17 AM, Łukasz Majewski wrote:
> Hi York,
>
> If you don't mind, I would like to ask you for some help and
> clarification regarding your work.
>
>> Add jump_to_image_linux() for arm64. Add "noreturn" flag to
>> armv8_switch_to_el2(). Add hooks to fsl-layerscape to enable falcon
>
On 09/25/2017 10:40 AM, Marek Vasut wrote:
On 09/25/2017 06:13 PM, Stephen Warren wrote:
Marek,
+CC Bin
I will drop the xhci patchset and hope to get a fixed one from him.
The latest branch content (0184c6fb34b4 "usb: dwc2: Align size of
invalidating dcache before starting DMA") passes the
On 09/14/2017 12:53 PM, York Sun wrote:
> Commit a8ecb39e accidentally reverted config macro CONFIG_ARCH_LS1021A
> to CONFIG_LS102XA.
>
> Signed-off-by: York Sun
> ---
Applied to fsl-qoriq mater.
York
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On 08/17/2017 10:24 PM, Ashish Kumar wrote:
> It is not necessary for every SoC to have 2 SATA controller.
> So put SATA1, SATA2 code under respective defines.
>
> Signed-off-by: Prabhakar Kushwaha
> Signed-off-by: Ashish Kumar
> ---
Applied to fsl-qoriq mater. Thanks.
York
___
On 08/18/2017 02:47 AM, Santan Kumar wrote:
> CONFIG_DISPLAY_BOARDINFO_LATE config is used to delay
> the prints of boardinfo late in cycle during uboot boot.
> This feature is not required in case of QSPI_BOOT.
>
> Signed-off-by: Santan Kumar
> Signed-off-by: Priyanka Jain
> ---
Applied to fsl
On 08/18/2017 02:47 AM, Santan Kumar wrote:
> As per updated board design, different QSPI flash
> is connected on boards, hence change QSPI flash type
> from Micron n25q512a device to spansion s25fs512s
> device in dts and config.
>
> Signed-off-by: Santan Kumar
> Signed-off-by: Yogesh Ga
On 08/31/2017 12:59 AM, Bharat Bhushan wrote:
> "pci: layerscape: Fixup device tree node for ls2088a" added
> support for LS208xA devices but fixing iommu-map property
> is missing. This patch adds support for fixing iommu-map.
>
> Signed-off-by: Bharat Bhushan
> Signed-off-by: Ioana Ciornei
> -
On 09/04/2017 03:14 AM, Sriram Dash wrote:
> IFC code is put under CONFIG_FSL_IFC
>
> Signed-off-by: Sriram Dash
> ---
Applied to fsl-qoriq mater. Thanks.
York
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On 09/04/2017 03:15 AM, Sriram Dash wrote:
> I2C code is put under CONFIG_SYS_I2C
>
> Signed-off-by: Sriram Dash
> ---
Applied to fsl-qoriq mater. Thanks.
York
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On 08/29/2017 02:50 AM, Priyanka Jain wrote:
> For most of ls2080ardb use-cases, mc private DRAM block is required
> to be of 1.75GB.
> Henc set mcmemsize=0x7000 in default env
>
> Signed-off-by: Priyanka Jain
> ---
Applied to fsl-qoriq mater. Thanks.
York
On 09/14/2017 09:49 PM, Priyanka Jain wrote:
> As per current implementation, default value of board env is
> based on board filename i.e ls2080ardb.
>
> With distro support changes, this env is used to decide upon
> kernel dtb which is different for other SoCs (ls2088a, ls2081a)
> combination sup
On 09/18/2017 12:16 AM, Yangbo Lu wrote:
> PPA loading during SPL stage is not required for nornal
> SD boot scenario.
>
> Signed-off-by: Yangbo Lu
> ---
Applied to fsl-qoriq mater. Thanks.
York
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On 09/14/2017 07:09 PM, Yangbo Lu wrote:
> Current u-boot disables IFC support for SD boot on all ls1043a
> boards. Actually IFC only conflicts with QSPI on ls1043a hardware.
> Only when QSPI is used, IFC should be disabled. Otherwise,
> the u-boot with ls1043aqds_sdcard_ifc_defconfig would not wor
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