Hi Peng,
On 30/08/2017 08:14, Peng Fan wrote:
> Enable DM MMC/I2C/PMIC/GPIO/REGULATOR.
>
> Signed-off-by: Peng Fan <[email protected]>
> Cc: Fabio Estevam <[email protected]>
> Cc: Stefano Babic <[email protected]>
> ---
>
> V2->V4: none
>
> board/freescale/mx6sabresd/mx6sabresd.c | 326
> +++++++++++++-------------------
> configs/mx6sabresd_defconfig | 15 ++
> include/configs/mx6sabresd.h | 15 +-
> 3 files changed, 146 insertions(+), 210 deletions(-)
>
> diff --git a/board/freescale/mx6sabresd/mx6sabresd.c
> b/board/freescale/mx6sabresd/mx6sabresd.c
> index fa75ab0..2123a9d 100644
> --- a/board/freescale/mx6sabresd/mx6sabresd.c
> +++ b/board/freescale/mx6sabresd/mx6sabresd.c
> @@ -12,7 +12,6 @@
> #include <asm/arch/mx6-pins.h>
> #include <linux/errno.h>
> #include <asm/gpio.h>
> -#include <asm/mach-imx/mxc_i2c.h>
> #include <asm/mach-imx/iomux-v3.h>
> #include <asm/mach-imx/boot_mode.h>
> #include <asm/mach-imx/video.h>
> @@ -24,7 +23,6 @@
> #include <asm/arch/crm_regs.h>
> #include <asm/io.h>
> #include <asm/arch/sys_proto.h>
> -#include <i2c.h>
> #include <power/pmic.h>
> #include <power/pfuze100_pmic.h>
> #include "../common/pfuze.h"
> @@ -46,14 +44,6 @@ DECLARE_GLOBAL_DATA_PTR;
> #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
> PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
>
> -#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
> - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
> - PAD_CTL_ODE | PAD_CTL_SRE_FAST)
> -
> -#define I2C_PMIC 1
> -
> -#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
> -
> #define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
>
> #define KEY_VOL_UP IMX_GPIO_NR(1, 4)
> @@ -93,6 +83,7 @@ static void setup_iomux_enet(void)
> {
> SETUP_IOMUX_PADS(enet_pads);
>
> + gpio_request(IMX_GPIO_NR(1, 25), "phy_rst");
> /* Reset AR8031 PHY */
> gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
> mdelay(10);
> @@ -100,47 +91,6 @@ static void setup_iomux_enet(void)
> udelay(100);
> }
>
> -static iomux_v3_cfg_t const usdhc2_pads[] = {
> - IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> /* CD */
> -};
> -
> -static iomux_v3_cfg_t const usdhc3_pads[] = {
> - IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /*
> CD */
> -};
> -
> -static iomux_v3_cfg_t const usdhc4_pads[] = {
> - IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> - IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> -};
> -
> static iomux_v3_cfg_t const ecspi1_pads[] = {
> IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
> IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
> @@ -187,6 +137,7 @@ static iomux_v3_cfg_t const bl_pads[] = {
> static void enable_backlight(void)
> {
> SETUP_IOMUX_PADS(bl_pads);
> + gpio_request(DISP0_PWR_EN, "disp0_pwr_en");
> gpio_direction_output(DISP0_PWR_EN, 1);
> }
>
> @@ -201,32 +152,6 @@ static void enable_lvds(struct display_info_t const *dev)
> enable_backlight();
> }
>
> -static struct i2c_pads_info mx6q_i2c_pad_info1 = {
> - .scl = {
> - .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
> - .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
> - .gp = IMX_GPIO_NR(4, 12)
> - },
> - .sda = {
> - .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
> - .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
> - .gp = IMX_GPIO_NR(4, 13)
> - }
> -};
> -
> -static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
> - .scl = {
> - .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
> - .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
> - .gp = IMX_GPIO_NR(4, 12)
> - },
> - .sda = {
> - .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
> - .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
> - .gp = IMX_GPIO_NR(4, 13)
> - }
> -};
> -
> static void setup_spi(void)
> {
> SETUP_IOMUX_PADS(ecspi1_pads);
> @@ -253,121 +178,11 @@ static void setup_iomux_uart(void)
> SETUP_IOMUX_PADS(uart1_pads);
> }
>
> -#ifdef CONFIG_FSL_ESDHC
> -struct fsl_esdhc_cfg usdhc_cfg[3] = {
> - {USDHC2_BASE_ADDR},
> - {USDHC3_BASE_ADDR},
> - {USDHC4_BASE_ADDR},
> -};
> -
> -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
> -#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
> -
> int board_mmc_get_env_dev(int devno)
> {
> return devno - 1;
> }
>
> -int board_mmc_getcd(struct mmc *mmc)
> -{
> - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> - int ret = 0;
> -
> - switch (cfg->esdhc_base) {
> - case USDHC2_BASE_ADDR:
> - ret = !gpio_get_value(USDHC2_CD_GPIO);
> - break;
> - case USDHC3_BASE_ADDR:
> - ret = !gpio_get_value(USDHC3_CD_GPIO);
> - break;
> - case USDHC4_BASE_ADDR:
> - ret = 1; /* eMMC/uSDHC4 is always present */
> - break;
> - }
> -
> - return ret;
> -}
> -
> -int board_mmc_init(bd_t *bis)
> -{
> -#ifndef CONFIG_SPL_BUILD
> - int ret;
> - int i;
> -
> - /*
> - * According to the board_mmc_init() the following map is done:
> - * (U-Boot device node) (Physical Port)
> - * mmc0 SD2
> - * mmc1 SD3
> - * mmc2 eMMC
> - */
> - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
> - switch (i) {
> - case 0:
> - SETUP_IOMUX_PADS(usdhc2_pads);
> - gpio_direction_input(USDHC2_CD_GPIO);
> - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> - break;
> - case 1:
> - SETUP_IOMUX_PADS(usdhc3_pads);
> - gpio_direction_input(USDHC3_CD_GPIO);
> - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> - break;
> - case 2:
> - SETUP_IOMUX_PADS(usdhc4_pads);
> - usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
> - break;
> - default:
> - printf("Warning: you configured more USDHC controllers"
> - "(%d) then supported by the board (%d)\n",
> - i + 1, CONFIG_SYS_FSL_USDHC_NUM);
> - return -EINVAL;
> - }
> -
> - ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
> - if (ret)
> - return ret;
> - }
> -
> - return 0;
> -#else
> - struct src *psrc = (struct src *)SRC_BASE_ADDR;
> - unsigned reg = readl(&psrc->sbmr1) >> 11;
> - /*
> - * Upon reading BOOT_CFG register the following map is done:
> - * Bit 11 and 12 of BOOT_CFG register can determine the current
> - * mmc port
> - * 0x1 SD1
> - * 0x2 SD2
> - * 0x3 SD4
> - */
> -
> - switch (reg & 0x3) {
> - case 0x1:
> - SETUP_IOMUX_PADS(usdhc2_pads);
> - usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
> - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
> - break;
> - case 0x2:
> - SETUP_IOMUX_PADS(usdhc3_pads);
> - usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
> - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
> - break;
> - case 0x3:
> - SETUP_IOMUX_PADS(usdhc4_pads);
> - usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
> - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
> - gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
> - break;
> - }
> -
> - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
> -#endif
> -}
> -#endif
> -
> static int ar8031_phy_fixup(struct phy_device *phydev)
> {
> unsigned short val;
> @@ -580,6 +395,8 @@ static void setup_usb(void)
> imx_iomux_set_gpr_register(1, 13, 1, 0);
>
> SETUP_IOMUX_PADS(usb_hc1_pads);
> +
> + gpio_request(IMX_GPIO_NR(1, 29), "usb1");
> }
>
> int board_ehci_hcd_init(int port)
> @@ -632,13 +449,13 @@ int board_init(void)
> /* address of boot parameters */
> gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
>
> + gpio_request(IMX_GPIO_NR(3, 19), "pcie_power");
> + gpio_request(IMX_GPIO_NR(7, 12), "pcie_reset");
> +
> #ifdef CONFIG_MXC_SPI
> setup_spi();
> #endif
> - if (is_mx6dq() || is_mx6dqp())
> - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
> - else
> - setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
> +
> #ifdef CONFIG_USB_EHCI_MX6
> setup_usb();
> #endif
> @@ -646,34 +463,36 @@ int board_init(void)
> return 0;
> }
>
> +#ifndef CONFIG_SPL_BUILD
> int power_init_board(void)
> {
> - struct pmic *p;
> + struct udevice *dev;
> unsigned int reg;
> int ret;
>
> - p = pfuze_common_init(I2C_PMIC);
> - if (!p)
> + dev = pfuze_common_init();
> + if (!dev)
> return -ENODEV;
>
> - ret = pfuze_mode_init(p, APS_PFM);
> + ret = pfuze_mode_init(dev, APS_PFM);
> if (ret < 0)
> return ret;
>
> /* Increase VGEN3 from 2.5 to 2.8V */
> - pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
> + reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL);
> reg &= ~LDO_VOL_MASK;
> reg |= LDOB_2_80V;
> - pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
> + pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg);
>
> /* Increase VGEN5 from 2.8 to 3V */
> - pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
> + reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
> reg &= ~LDO_VOL_MASK;
> reg |= LDOB_3_00V;
> - pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
> + pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
>
> return 0;
> }
> +#endif
>
> #ifdef CONFIG_MXC_SPI
> int board_spi_cs_gpio(unsigned bus, unsigned cs)
> @@ -747,6 +566,115 @@ int board_fit_config_name_match(const char *name)
> }
> #endif
>
> +#ifdef CONFIG_FSL_ESDHC
> +static iomux_v3_cfg_t const usdhc2_pads[] = {
> + IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
> /* CD */
> +};
> +
> +static iomux_v3_cfg_t const usdhc3_pads[] = {
> + IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /*
> CD */
> +};
> +
> +static iomux_v3_cfg_t const usdhc4_pads[] = {
> + IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> + IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
> +};
> +
> +struct fsl_esdhc_cfg usdhc_cfg[3] = {
> + {USDHC2_BASE_ADDR},
> + {USDHC3_BASE_ADDR},
> + {USDHC4_BASE_ADDR},
> +};
> +
> +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
> +#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
> +
> +int board_mmc_getcd(struct mmc *mmc)
> +{
> + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
> + int ret = 0;
> +
> + switch (cfg->esdhc_base) {
> + case USDHC2_BASE_ADDR:
> + ret = !gpio_get_value(USDHC2_CD_GPIO);
> + break;
> + case USDHC3_BASE_ADDR:
> + ret = !gpio_get_value(USDHC3_CD_GPIO);
> + break;
> + case USDHC4_BASE_ADDR:
> + ret = 1; /* eMMC/uSDHC4 is always present */
> + break;
> + }
> +
> + return ret;
> +}
> +
> +int board_mmc_init(bd_t *bis)
> +{
> + struct src *psrc = (struct src *)SRC_BASE_ADDR;
> + unsigned reg = readl(&psrc->sbmr1) >> 11;
> + /*
> + * Upon reading BOOT_CFG register the following map is done:
> + * Bit 11 and 12 of BOOT_CFG register can determine the current
> + * mmc port
> + * 0x1 SD1
> + * 0x2 SD2
> + * 0x3 SD4
> + */
> +
> + switch (reg & 0x3) {
> + case 0x1:
> + SETUP_IOMUX_PADS(usdhc2_pads);
> + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
> + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
> + break;
> + case 0x2:
> + SETUP_IOMUX_PADS(usdhc3_pads);
> + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
> + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
> + break;
> + case 0x3:
> + SETUP_IOMUX_PADS(usdhc4_pads);
> + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
> + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
> + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
> + break;
> + }
> +
> + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
> +}
> +#endif
> +
> static void ccgr_init(void)
> {
> struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
> diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig
> index 7491e9c..3eab67e 100644
> --- a/configs/mx6sabresd_defconfig
> +++ b/configs/mx6sabresd_defconfig
> @@ -40,6 +40,8 @@ CONFIG_CMD_DHCP=y
> CONFIG_CMD_MII=y
> CONFIG_CMD_PING=y
> CONFIG_CMD_CACHE=y
> +CONFIG_CMD_PMIC=y
> +CONFIG_CMD_REGULATOR=y
> CONFIG_CMD_EXT2=y
> CONFIG_CMD_EXT4=y
> CONFIG_CMD_EXT4_WRITE=y
> @@ -47,10 +49,23 @@ CONFIG_CMD_FAT=y
> CONFIG_CMD_FS_GENERIC=y
> CONFIG_OF_CONTROL=y
> CONFIG_OF_LIST="imx6q-sabresd imx6dl-sabresd imx6qp-sabresd"
> +# CONFIG_BLK is not set
> +CONFIG_DM_GPIO=y
> +CONFIG_DM_I2C=y
> +CONFIG_DM_MMC=y
> +# CONFIG_DM_MMC_OPS is not set
> CONFIG_SPI_FLASH=y
> CONFIG_SPI_FLASH_STMICRO=y
> CONFIG_PHYLIB=y
> CONFIG_PCI=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_IMX6=y
> +CONFIG_DM_PMIC=y
> +CONFIG_DM_PMIC_PFUZE100=y
> +CONFIG_DM_REGULATOR=y
> +CONFIG_DM_REGULATOR_PFUZE100=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_DM_REGULATOR_GPIO=y
> CONFIG_USB=y
> CONFIG_USB_STORAGE=y
> CONFIG_USB_GADGET=y
> diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
> index 5410881..a945641 100644
> --- a/include/configs/mx6sabresd.h
> +++ b/include/configs/mx6sabresd.h
> @@ -43,20 +43,9 @@
> #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19)
> #endif
>
> -/* I2C Configs */
> -#define CONFIG_SYS_I2C
> #define CONFIG_SYS_I2C_MXC
> -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
> -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
> -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
> #define CONFIG_SYS_I2C_SPEED 100000
>
> -/* PMIC */
> -#define CONFIG_POWER
> -#define CONFIG_POWER_I2C
> -#define CONFIG_POWER_PFUZE100
> -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
> -
> /* USB Configs */
> #ifdef CONFIG_CMD_USB
> #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
> @@ -67,4 +56,8 @@
> #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller
> number */
> #endif
>
> +#ifdef CONFIG_SPL_BUILD
> +#undef CONFIG_SYS_I2C_MXC
> +#endif
> +
> #endif /* __MX6SABRESD_CONFIG_H */
>
Enabling DM drivers seems to break sabresd:
arm: + mx6sabresd
+common/usb_storage.c: In function 'usb_stor_probe_device':
+common/usb_storage.c:218:30: error: 'struct usb_device' has no member
named 'dev'
+ data = dev_get_platdata(udev->dev);
+ ^
+common/usb_storage.c:228:32: error: 'struct usb_device' has no member
named 'dev'
+ ret = blk_create_devicef(udev->dev, "usb_storage_blk", str,
+ ^
Can you take a look ?
Best regards,
Stefano
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