Re: [PATCH] drm/amd/amdgpu: Add sensors debugfs support

[Edward O'Callaghan]

On 09/15/2016 11:22 PM, Tom St Denis wrote:
> This patch adds a callback to powerplay which
> reads specific PP sensors (vdd/clocks/load) which is then
> accessible via debugfs.  The idea being is it'll be a standard
> interface between different ASICs that userland tools can
> read.
> 
> Currently only CZ/ST is supported but the others are
> NULL'ed off so they shouldn't cause any sort of oops.
> 
> Signed-off-by: Tom St Denis 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31 +++
>  drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 20 +
>  drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 96 
> ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   |  1 +
>  .../gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c|  1 +
>  .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  |  1 +
>  drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  |  1 +
>  drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  | 10 +++
>  drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  1 +
>  9 files changed, 162 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 9103e7baf26e..b6a4588c95ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2841,6 +2841,29 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct 
> file *f, char __user *buf,
>   return result;
>  }
>  
> +static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
> + size_t size, loff_t *pos)
> +{
> + struct amdgpu_device *adev = f->f_inode->i_private;
> + int r;
> + int32_t value;
> +
> + if (size != 4 || *pos & 0x3)

Just some minor questions,

maybe I miss-read but maybe dereference pos the once and have it const?

> + return -EINVAL;
> +
> + /* convert offset to sensor number */
> + *pos >>= 2;
Is the intent here just a local mutation or a in-place global state
transition?

Kind Regards,
Edward.

> +
> + if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
> + r = 
> adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, *pos, 
> );
> + else
> + r = -EINVAL;
> +
> + if (!r)
> + r = put_user(value, (int32_t *)buf);
> +
> + return !r ? 4 : r;
> +}
>  
>  static const struct file_operations amdgpu_debugfs_regs_fops = {
>   .owner = THIS_MODULE,
> @@ -2873,12 +2896,19 @@ static const struct file_operations 
> amdgpu_debugfs_gca_config_fops = {
>   .llseek = default_llseek
>  };
>  
> +static const struct file_operations amdgpu_debugfs_sensors_fops = {
> + .owner = THIS_MODULE,
> + .read = amdgpu_debugfs_sensor_read,
> + .llseek = default_llseek
> +};
> +
>  static const struct file_operations *debugfs_regs[] = {
>   _debugfs_regs_fops,
>   _debugfs_regs_didt_fops,
>   _debugfs_regs_pcie_fops,
>   _debugfs_regs_smc_fops,
>   _debugfs_gca_config_fops,
> + _debugfs_sensors_fops,
>  };
>  
>  static const char *debugfs_regs_names[] = {
> @@ -2887,6 +2917,7 @@ static const char *debugfs_regs_names[] = {
>   "amdgpu_regs_pcie",
>   "amdgpu_regs_smc",
>   "amdgpu_gca_config",
> + "amdgpu_sensors",
>  };
>  
>  static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index b1d19409bf86..ee0368381e82 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -894,6 +894,25 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t 
> value)
>   return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
>  }
>  
> +static int pp_dpm_read_sensor(void *handle, int idx, int32_t *value)
> +{
> + struct pp_hwmgr *hwmgr;
> +
> + if (!handle)
> + return -EINVAL;
> +
> + hwmgr = ((struct pp_instance *)handle)->hwmgr;
> +
> + PP_CHECK_HW(hwmgr);
> +
> + if (hwmgr->hwmgr_func->read_sensor == NULL) {
> + printk(KERN_INFO "%s was not implemented.\n", __func__);
> + return 0;
> + }
> +
> + return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value);
> +}
> +
>  const struct amd_powerplay_funcs pp_dpm_funcs = {
>   .get_temperature = pp_dpm_get_temperature,
>   .load_firmware = pp_dpm_load_fw,
> @@ -920,6 +939,7 @@ const struct amd_powerplay_funcs pp_dpm_funcs = {
>   .set_sclk_od = pp_dpm_set_sclk_od,
>   .get_mclk_od = pp_dpm_get_mclk_od,
>   .set_mclk_od = pp_dpm_set_mclk_od,
> + .read_sensor = pp_dpm_read_sensor,
>  };
>  
>  static int amd_pp_instance_init(struct amd_pp_init *pp_init,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
> index 5ecef1732e20..9f3c5a8a903c 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c

Re: Add read_sensor() support for fiji/tonga/iceland/polaris10

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan 

On 09/16/2016 04:21 AM, Tom St Denis wrote:
> Tested on my Tonga but should in theory work for the others as 
> well since they're 99% copy/paste (except which SMC reg is read
> for GPU load...)
> 
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> 



signature.asc
Description: OpenPGP digital signature
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/5] drm/amdgpu: fix a bunch of coding style issues in amdgpu_ttm.c

[Michel Dänzer]

On 15/09/16 10:10 PM, Christian König wrote:
> From: Christian König 
> 
> No intented functional change.
> 
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 65 
> +
>  1 file changed, 42 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 428ffb6..1965209 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -214,9 +214,11 @@ static void amdgpu_evict_flags(struct ttm_buffer_object 
> *bo,
>   switch (bo->mem.mem_type) {
>   case TTM_PL_VRAM:
>   if (rbo->adev->mman.buffer_funcs_ring->ready == false) {
> - amdgpu_ttm_placement_from_domain(rbo, 
> AMDGPU_GEM_DOMAIN_CPU);
> + amdgpu_ttm_placement_from_domain(rbo,
> +  AMDGPU_GEM_DOMAIN_CPU);
>   } else {
> - amdgpu_ttm_placement_from_domain(rbo, 
> AMDGPU_GEM_DOMAIN_GTT);
> + amdgpu_ttm_placement_from_domain(rbo,
> +  AMDGPU_GEM_DOMAIN_GTT);

I don't see the point of this kind of change. We save all of 5 columns
of horizontal space, but for that we reduce readability by breaking up a
single line statement to multiple lines.

It makes more sense when saving a more significant amount of horizontal
space or when the statement already spans multiple lines though.


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu/sdma3: drop unused functions

[Alex Deucher]

These are not used yet.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 25 -
 1 file changed, 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index bee4978..cabb9fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -499,31 +499,6 @@ static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring 
*ring, u64 addr, u64 se
amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 }
 
-unsigned init_cond_exec(struct amdgpu_ring *ring)
-{
-   unsigned ret;
-   amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
-   amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
-   amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
-   amdgpu_ring_write(ring, 1);
-   ret = ring->wptr;/* this is the offset we need patch later */
-   amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it 
later */
-   return ret;
-}
-
-void patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
-{
-   unsigned cur;
-   BUG_ON(ring->ring[offset] != 0x55aa55aa);
-
-   cur = ring->wptr - 1;
-   if (likely(cur > offset))
-   ring->ring[offset] = cur - offset;
-   else
-   ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
-}
-
-
 /**
  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
  *
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/3] drm/amdgpu/gfx6: drop gds_switch callback

[Alex Deucher]

GDS works differently on GFX6, plus the callback was
empty.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 10 --
 1 file changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index d33d321..e7293f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2678,14 +2678,6 @@ static uint64_t gfx_v6_0_get_gpu_clock_counter(struct 
amdgpu_device *adev)
return clock;
 }
 
-static void gfx_v6_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
- uint32_t vmid,
- uint32_t gds_base, uint32_t gds_size,
- uint32_t gws_base, uint32_t gws_size,
- uint32_t oa_base, uint32_t oa_size)
-{
-}
-
 static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
 {
amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
@@ -3115,7 +3107,6 @@ static const struct amdgpu_ring_funcs 
gfx_v6_0_ring_funcs_gfx = {
.emit_fence = gfx_v6_0_ring_emit_fence,
.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
.emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
-   .emit_gds_switch = gfx_v6_0_ring_emit_gds_switch,
.emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
.emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
.test_ring = gfx_v6_0_ring_test_ring,
@@ -3133,7 +3124,6 @@ static const struct amdgpu_ring_funcs 
gfx_v6_0_ring_funcs_compute = {
.emit_fence = gfx_v6_0_ring_emit_fence,
.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
.emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
-   .emit_gds_switch = gfx_v6_0_ring_emit_gds_switch,
.emit_hdp_flush = gfx_v6_0_ring_emit_hdp_flush,
.emit_hdp_invalidate = gfx_v6_0_ring_emit_hdp_invalidate,
.test_ring = gfx_v6_0_ring_test_ring,
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/3] drm/amdgpu/gfx6: add ring_emit_cntxcntl

[Alex Deucher]

Missing for gfx6.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 3cf4e9e..d33d321 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2686,6 +2686,13 @@ static void gfx_v6_0_ring_emit_gds_switch(struct 
amdgpu_ring *ring,
 {
 }
 
+static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
+{
+   amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
+   amdgpu_ring_write(ring, 0x8000);
+   amdgpu_ring_write(ring, 0);
+}
+
 static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
.get_gpu_clock_counter = _v6_0_get_gpu_clock_counter,
.select_se_sh = _v6_0_select_se_sh,
@@ -3114,6 +3121,7 @@ static const struct amdgpu_ring_funcs 
gfx_v6_0_ring_funcs_gfx = {
.test_ring = gfx_v6_0_ring_test_ring,
.test_ib = gfx_v6_0_ring_test_ib,
.insert_nop = amdgpu_ring_insert_nop,
+   .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
 };
 
 static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/3] drm/amdgpu/gfx6: drop duplicate code

[Alex Deucher]

The compute functions just called the gfx functions, drop
the wrapper.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 33 +
 1 file changed, 9 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 9697994..3cf4e9e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1324,8 +1324,8 @@ static void gfx_v6_0_ring_emit_hdp_invalidate(struct 
amdgpu_ring *ring)
amdgpu_ring_write(ring, 0x1);
 }
 
-static void gfx_v6_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
-u64 seq, unsigned flags)
+static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
+u64 seq, unsigned flags)
 {
bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
@@ -1351,17 +1351,9 @@ static void gfx_v6_0_ring_emit_fence_gfx(struct 
amdgpu_ring *ring, u64 addr,
amdgpu_ring_write(ring, upper_32_bits(seq));
 }
 
-static void gfx_v6_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
-u64 addr, u64 seq,
-unsigned flags)
-{
-   gfx_v6_0_ring_emit_fence_gfx(ring, addr, seq, flags);
-}
-
-
-static void gfx_v6_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
- struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
+static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
+ struct amdgpu_ib *ib,
+ unsigned vm_id, bool ctx_switch)
 {
u32 header, control = 0;
 
@@ -1388,13 +1380,6 @@ static void gfx_v6_0_ring_emit_ib_gfx(struct amdgpu_ring 
*ring,
amdgpu_ring_write(ring, control);
 }
 
-static void gfx_v6_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
- struct amdgpu_ib *ib,
- unsigned vm_id, bool ctx_switch)
-{
-   gfx_v6_0_ring_emit_ib_gfx(ring, ib, vm_id, ctx_switch);
-}
-
 /**
  * gfx_v6_0_ring_test_ib - basic ring IB test
  *
@@ -3119,8 +3104,8 @@ static const struct amdgpu_ring_funcs 
gfx_v6_0_ring_funcs_gfx = {
.get_wptr = gfx_v6_0_ring_get_wptr,
.set_wptr = gfx_v6_0_ring_set_wptr_gfx,
.parse_cs = NULL,
-   .emit_ib = gfx_v6_0_ring_emit_ib_gfx,
-   .emit_fence = gfx_v6_0_ring_emit_fence_gfx,
+   .emit_ib = gfx_v6_0_ring_emit_ib,
+   .emit_fence = gfx_v6_0_ring_emit_fence,
.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
.emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
.emit_gds_switch = gfx_v6_0_ring_emit_gds_switch,
@@ -3136,8 +3121,8 @@ static const struct amdgpu_ring_funcs 
gfx_v6_0_ring_funcs_compute = {
.get_wptr = gfx_v6_0_ring_get_wptr,
.set_wptr = gfx_v6_0_ring_set_wptr_compute,
.parse_cs = NULL,
-   .emit_ib = gfx_v6_0_ring_emit_ib_compute,
-   .emit_fence = gfx_v6_0_ring_emit_fence_compute,
+   .emit_ib = gfx_v6_0_ring_emit_ib,
+   .emit_fence = gfx_v6_0_ring_emit_fence,
.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
.emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
.emit_gds_switch = gfx_v6_0_ring_emit_gds_switch,
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/5] drm/amdgpu: fix a bunch of coding style issues in amdgpu_gem.c

[Alex Deucher]

On Thu, Sep 15, 2016 at 9:10 AM, Christian König
 wrote:
> From: Christian König 
>
> No intented functional change.
>

"intended"

In general, with respect to the white space changes, I think the code
is more readable as is, but I don't have a strong opinion either way,
if you prefer this.

> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 18 --
>  1 file changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index 88fbed2..70e294b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -58,7 +58,8 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, 
> unsigned long size,
> alignment = PAGE_SIZE;
> }
>
> -   if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS 
> | AMDGPU_GEM_DOMAIN_OA))) {
> +   if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS 
> |
> +   AMDGPU_GEM_DOMAIN_OA))) {
> /* Maximum bo size is the unpinned gtt size since we use the 
> gtt to
>  * handle vram to system pool migrations.
>  */
> @@ -116,7 +117,8 @@ void amdgpu_gem_force_release(struct amdgpu_device *adev)
>   * Call from drm_gem_handle_create which appear in both new and open ioctl
>   * case.
>   */
> -int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file 
> *file_priv)
> +int amdgpu_gem_object_open(struct drm_gem_object *obj,
> +  struct drm_file *file_priv)
>  {
> struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
> struct amdgpu_device *adev = rbo->adev;
> @@ -408,9 +410,11 @@ int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, 
> void *data,
> }
> robj = gem_to_amdgpu_bo(gobj);
> if (timeout == 0)
> -   ret = reservation_object_test_signaled_rcu(robj->tbo.resv, 
> true);
> +   ret = reservation_object_test_signaled_rcu(robj->tbo.resv,
> +  true);
> else
> -   ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, 
> true, true, timeout);
> +   ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, 
> true,
> + true, timeout);
>
> /* ret == 0 means not signaled,
>  * ret > 0 means signaled
> @@ -480,7 +484,8 @@ out:
>   * vital here, so they are not reported back to userspace.
>   */
>  static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
> -   struct amdgpu_bo_va *bo_va, uint32_t 
> operation)
> +   struct amdgpu_bo_va *bo_va,
> +   uint32_t operation)
>  {
> struct ttm_validate_buffer tv, *entry;
> struct amdgpu_bo_list_entry vm_pd;
> @@ -704,7 +709,8 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
> uint32_t handle;
> int r;
>
> -   args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * 
> ((args->bpp + 1) / 8);
> +   args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) *
> +   ((args->bpp + 1) / 8);
> args->size = (u64)args->pitch * args->height;
> args->size = ALIGN(args->size, PAGE_SIZE);
>
> --
> 2.5.0
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 2/5] drm/amdgpu: fix a bunch of coding style issues in amdgpu_ttm.c

[Alex Deucher]

On Thu, Sep 15, 2016 at 9:10 AM, Christian König
 wrote:
> From: Christian König 
>
> No intented functional change.

"intended"

In general, with respect to the white space changes, I think the code
is more readable as is, but I don't have a strong opinion either way,
if you prefer this.  One additional comment below.

>
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 65 
> +
>  1 file changed, 42 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 428ffb6..1965209 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -214,9 +214,11 @@ static void amdgpu_evict_flags(struct ttm_buffer_object 
> *bo,
> switch (bo->mem.mem_type) {
> case TTM_PL_VRAM:
> if (rbo->adev->mman.buffer_funcs_ring->ready == false) {
> -   amdgpu_ttm_placement_from_domain(rbo, 
> AMDGPU_GEM_DOMAIN_CPU);
> +   amdgpu_ttm_placement_from_domain(rbo,
> +
> AMDGPU_GEM_DOMAIN_CPU);
> } else {
> -   amdgpu_ttm_placement_from_domain(rbo, 
> AMDGPU_GEM_DOMAIN_GTT);
> +   amdgpu_ttm_placement_from_domain(rbo,
> +
> AMDGPU_GEM_DOMAIN_GTT);
> for (i = 0; i < rbo->placement.num_placement; ++i) {
> if (!(rbo->placements[i].flags &
>   TTM_PL_FLAG_TT))
> @@ -524,7 +526,8 @@ memcpy:
> return 0;
>  }
>
> -static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct 
> ttm_mem_reg *mem)
> +static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev,
> +struct ttm_mem_reg *mem)
>  {
> struct ttm_mem_type_manager *man = >man[mem->mem_type];
> struct amdgpu_device *adev = amdgpu_get_adev(bdev);
> @@ -545,7 +548,8 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device 
> *bdev, struct ttm_mem_
> case TTM_PL_VRAM:
> mem->bus.offset = mem->start << PAGE_SHIFT;
> /* check if it's visible */
> -   if ((mem->bus.offset + mem->bus.size) > 
> adev->mc.visible_vram_size)
> +   if ((mem->bus.offset + mem->bus.size) >
> +   adev->mc.visible_vram_size)
> return -EINVAL;
> mem->bus.base = adev->mc.aper_base;
> mem->bus.is_iomem = true;
> @@ -579,7 +583,8 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device 
> *bdev, struct ttm_mem_
> return 0;
>  }
>
> -static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct 
> ttm_mem_reg *mem)
> +static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev,
> +  struct ttm_mem_reg *mem)
>  {
>  }
>
> @@ -791,7 +796,8 @@ int amdgpu_ttm_recover_gart(struct amdgpu_device *adev)
> bo_mem.mem_type = TTM_PL_TT;
> spin_lock(>gtt_list_lock);
> list_for_each_entry_safe(gtt, tmp, >gtt_list, list) {
> -   flags = amdgpu_ttm_tt_pte_flags(gtt->adev, >ttm.ttm, 
> _mem);
> +   flags = amdgpu_ttm_tt_pte_flags(gtt->adev, >ttm.ttm,
> +   _mem);
> r = amdgpu_gart_bind(adev, gtt->offset, 
> gtt->ttm.ttm.num_pages,
>  gtt->ttm.ttm.pages, gtt->ttm.dma_address,
>  flags);
> @@ -856,7 +862,8 @@ static struct ttm_tt *amdgpu_ttm_tt_create(struct 
> ttm_bo_device *bdev,
> }
> gtt->ttm.ttm.func = _backend_func;
> gtt->adev = adev;
> -   if (ttm_dma_tt_init(>ttm, bdev, size, page_flags, 
> dummy_read_page)) {
> +   if (ttm_dma_tt_init(>ttm, bdev, size, page_flags,
> +   dummy_read_page)) {
> kfree(gtt);
> return NULL;
> }
> @@ -887,7 +894,8 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
>
> if (slave && ttm->sg) {
> drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
> -gtt->ttm.dma_address, 
> ttm->num_pages);
> +gtt->ttm.dma_address,
> +ttm->num_pages);
> ttm->state = tt_unbound;
> return 0;
> }
> @@ -906,13 +914,17 @@ static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm)
> }
>
> for (i = 0; i < ttm->num_pages; i++) {
> -   gtt->ttm.dma_address[i] = pci_map_page(adev->pdev, 
> ttm->pages[i],
> +   gtt->ttm.dma_address[i] = pci_map_page(adev->pdev,

[PATCH] drm/amd/powerplay: Add read_sensor support to tonga/fiji/polaris/iceland

[Tom St Denis]

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   | 35 +-
 .../gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c| 35 +-
 .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  | 34 -
 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  | 34 -
 drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  |  2 ++
 5 files changed, 136 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
index c64def1884c9..06aacefe5df1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
@@ -5104,6 +5104,39 @@ static void fiji_print_current_perforce_level(
seq_printf(m, "vce%sabled\n", data->vce_power_gated ? "dis" : "en");
 }
 
+static int fiji_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
+{
+   uint32_t sclk, mclk, activity_percent;
+   uint32_t offset;
+   struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
+
+   switch (idx) {
+   case AMDGPU_PP_SENSOR_GFX_SCLK:
+   smum_send_msg_to_smc(hwmgr->smumgr, 
(PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency));
+   sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+   *value = sclk;
+   return 0;
+   case AMDGPU_PP_SENSOR_GFX_MCLK:
+   smum_send_msg_to_smc(hwmgr->smumgr, 
(PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency));
+   mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+   *value = mclk;
+   return 0;
+   case AMDGPU_PP_SENSOR_GPU_LOAD:
+   offset = data->soft_regs_start + offsetof(SMU73_SoftRegisters, 
AverageGraphicsActivity);
+   activity_percent = cgs_read_ind_register(hwmgr->device, 
CGS_IND_REG__SMC, offset);
+   activity_percent += 0x80;
+   activity_percent >>= 8;
+   *value = (activity_percent > 100) ? 100 : activity_percent;
+   return 0;
+   case AMDGPU_PP_SENSOR_GPU_TEMP:
+   *value = fiji_thermal_get_temperature(hwmgr);
+   return 0;
+   default:
+   return -EINVAL;
+   }
+}
+
+
 static int fiji_program_display_gap(struct pp_hwmgr *hwmgr)
 {
struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
@@ -5590,7 +5623,7 @@ static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
.set_sclk_od = fiji_set_sclk_od,
.get_mclk_od = fiji_get_mclk_od,
.set_mclk_od = fiji_set_mclk_od,
-   .read_sensor = NULL,
+   .read_sensor = fiji_read_sensor,
 };
 
 int fiji_hwmgr_init(struct pp_hwmgr *hwmgr)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
index d7a1410402d4..79b4b47d65f3 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c
@@ -5134,6 +5134,39 @@ iceland_print_current_perforce_level(struct pp_hwmgr 
*hwmgr, struct seq_file *m)
seq_printf(m, "vce%sabled\n", data->vce_power_gated ? "dis" : "en");
 }
 
+static int iceland_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
+{
+   uint32_t sclk, mclk, activity_percent;
+   uint32_t offset;
+   struct iceland_hwmgr *data = (struct iceland_hwmgr *)(hwmgr->backend);
+
+   switch (idx) {
+   case AMDGPU_PP_SENSOR_GFX_SCLK:
+   smum_send_msg_to_smc(hwmgr->smumgr, 
(PPSMC_Msg)(PPSMC_MSG_API_GetSclkFrequency));
+   sclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+   *value = sclk;
+   return 0;
+   case AMDGPU_PP_SENSOR_GFX_MCLK:
+   smum_send_msg_to_smc(hwmgr->smumgr, 
(PPSMC_Msg)(PPSMC_MSG_API_GetMclkFrequency));
+   mclk = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
+   *value = mclk;
+   return 0;
+   case AMDGPU_PP_SENSOR_GPU_LOAD:
+   offset = data->soft_regs_start + offsetof(SMU71_SoftRegisters, 
AverageGraphicsActivity);
+   activity_percent = cgs_read_ind_register(hwmgr->device, 
CGS_IND_REG__SMC, offset);
+   activity_percent += 0x80;
+   activity_percent >>= 8;
+   *value = (activity_percent > 100) ? 100 : activity_percent;
+   return 0;
+   case AMDGPU_PP_SENSOR_GPU_TEMP:
+   *value = iceland_thermal_get_temperature(hwmgr);
+   return 0;
+   default:
+   return -EINVAL;
+   }
+}
+
+
 int iceland_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr 
*hwmgr)
 {
uint32_t num_active_displays = 0;
@@ -5663,7 +5696,7 @@ static const struct pp_hwmgr_func iceland_hwmgr_funcs = {
.set_sclk_od = iceland_set_sclk_od,
.get_mclk_od = iceland_get_mclk_od,
.set_mclk_od = 

Re: [PATCH] drm/amdgpu: fix ring space allocation for IB scheduling

[Christian König]

Am 15.09.2016 um 20:08 schrieb Alex Deucher:

GFX IB frame is much bigger than other ring, so set the
limit larger.

Signed-off-by: Alex Deucher 


Could we rather add some fields to the ring structure to indicate how 
many base + per IB dw we need to allocate?


Probably better than having engine specific code here.

Christian.


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 6 +-
  1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 2aa741c..e11e4cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -152,7 +152,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned 
num_ibs,
return -EINVAL;
}
  
-	r = amdgpu_ring_alloc(ring, 256 * num_ibs);

+   /* GFX DMA frame is much bigger than other rings */
+   if (ring->type == AMDGPU_RING_TYPE_GFX)
+   r = amdgpu_ring_alloc(ring, 512 + num_ibs * 16);
+   else
+   r = amdgpu_ring_alloc(ring, 256 + num_ibs * 16);
if (r) {
dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
return r;



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 5/5] drm/amdgpu: rename all rbo variable to abo

[Alex Deucher]

On Thu, Sep 15, 2016 at 9:10 AM, Christian König
 wrote:
> From: Christian König 
>
> Just to cleanup some radeon leftovers.
>
> sed -i "s/rbo/abo/g" drivers/gpu/drm/amd/amdgpu/*.c
> sed -i "s/rbo/abo/g" drivers/gpu/drm/amd/amdgpu/*.h
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  4 +--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 42 +--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  | 44 
> ++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 20 ++---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c  | 16 +--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 24 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |  8 +++---
>  drivers/gpu/drm/amd/amdgpu/dce_v10_0.c  | 36 +++
>  drivers/gpu/drm/amd/amdgpu/dce_v11_0.c  | 36 +++
>  drivers/gpu/drm/amd/amdgpu/dce_v6_0.c   | 36 +++
>  drivers/gpu/drm/amd/amdgpu/dce_v8_0.c   | 36 +++
>  drivers/gpu/drm/amd/amdgpu/dce_virtual.c| 12 
>  12 files changed, 157 insertions(+), 157 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index ed91f08..c30635a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -701,7 +701,7 @@ struct amdgpu_flip_work {
> int crtc_id;
> uint64_tbase;
> struct drm_pending_vblank_event *event;
> -   struct amdgpu_bo*old_rbo;
> +   struct amdgpu_bo*old_abo;
> struct fence*excl;
> unsignedshared_count;
> struct fence**shared;
> @@ -2436,7 +2436,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, 
> void *data);
>  int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
>u32 ip_instance, u32 ring,
>struct amdgpu_ring **out_ring);
> -void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
> +void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
>  bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
>  int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
>  int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 93fd761..783e1d8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -154,17 +154,17 @@ static void amdgpu_unpin_work_func(struct work_struct 
> *__work)
> int r;
>
> /* unpin of the old buffer */
> -   r = amdgpu_bo_reserve(work->old_rbo, false);
> +   r = amdgpu_bo_reserve(work->old_abo, false);
> if (likely(r == 0)) {
> -   r = amdgpu_bo_unpin(work->old_rbo);
> +   r = amdgpu_bo_unpin(work->old_abo);
> if (unlikely(r != 0)) {
> DRM_ERROR("failed to unpin buffer after flip\n");
> }
> -   amdgpu_bo_unreserve(work->old_rbo);
> +   amdgpu_bo_unreserve(work->old_abo);
> } else
> DRM_ERROR("failed to reserve buffer after flip\n");
>
> -   amdgpu_bo_unref(>old_rbo);
> +   amdgpu_bo_unref(>old_abo);
> kfree(work->shared);
> kfree(work);
>  }
> @@ -181,7 +181,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
> struct amdgpu_framebuffer *new_amdgpu_fb;
> struct drm_gem_object *obj;
> struct amdgpu_flip_work *work;
> -   struct amdgpu_bo *new_rbo;
> +   struct amdgpu_bo *new_abo;
> unsigned long flags;
> u64 tiling_flags;
> u64 base;
> @@ -204,28 +204,28 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
> obj = old_amdgpu_fb->obj;
>
> /* take a reference to the old object */
> -   work->old_rbo = gem_to_amdgpu_bo(obj);
> -   amdgpu_bo_ref(work->old_rbo);
> +   work->old_abo = gem_to_amdgpu_bo(obj);
> +   amdgpu_bo_ref(work->old_abo);
>
> new_amdgpu_fb = to_amdgpu_framebuffer(fb);
> obj = new_amdgpu_fb->obj;
> -   new_rbo = gem_to_amdgpu_bo(obj);
> +   new_abo = gem_to_amdgpu_bo(obj);
>
> /* pin the new buffer */
> -   r = amdgpu_bo_reserve(new_rbo, false);
> +   r = amdgpu_bo_reserve(new_abo, false);
> if (unlikely(r != 0)) {
> -   DRM_ERROR("failed to reserve new rbo buffer before flip\n");
> +   DRM_ERROR("failed to reserve new abo buffer before flip\n");
> goto cleanup;
> }
>
> -   r = 

Re: [PATCH 1/5] drm/amdgpu: remove unused member from struct amdgpu_bo

[Alex Deucher]

On Thu, Sep 15, 2016 at 9:10 AM, Christian König
 wrote:
> From: Christian König 
>
> Not used in a while.
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 -
>  2 files changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index ee55763..3b3981d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -446,8 +446,6 @@ struct amdgpu_bo_va {
>  #define AMDGPU_GEM_DOMAIN_MAX  0x3
>
>  struct amdgpu_bo {
> -   /* Protected by gem.mutex */
> -   struct list_headlist;
> /* Protected by tbo.reserved */
> u32 prefered_domains;
> u32 allowed_domains;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index d6e6c93..4289c31 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -360,7 +360,6 @@ int amdgpu_bo_create_restricted(struct amdgpu_device 
> *adev,
> return r;
> }
> bo->adev = adev;
> -   INIT_LIST_HEAD(>list);
> INIT_LIST_HEAD(>shadow_list);
> INIT_LIST_HEAD(>va);
> bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
> --
> 2.5.0
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amdgpu: fix ring space allocation for IB scheduling

[Alex Deucher]

GFX IB frame is much bigger than other ring, so set the
limit larger.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 2aa741c..e11e4cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -152,7 +152,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned 
num_ibs,
return -EINVAL;
}
 
-   r = amdgpu_ring_alloc(ring, 256 * num_ibs);
+   /* GFX DMA frame is much bigger than other rings */
+   if (ring->type == AMDGPU_RING_TYPE_GFX)
+   r = amdgpu_ring_alloc(ring, 512 + num_ibs * 16);
+   else
+   r = amdgpu_ring_alloc(ring, 256 + num_ibs * 16);
if (r) {
dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
return r;
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/amdgpu: Add sensors debugfs support

[StDenis, Tom]

Hi Alex,


I don't know much about the hwmon API but maybe the backend could be useful for 
some hwmon glue?


Though I'd like to keep the frontend (debugfs) for now until we sort out hwmon 
changes.


Tom



From: Deucher, Alexander
Sent: Thursday, September 15, 2016 11:10
To: StDenis, Tom; Christian König; amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amd/amdgpu: Add sensors debugfs support


FWIW, temperature and fan are already exposed via standard hwmon interfaces.  
It might be better to use standard interfaces for some of these things if they 
exist.



Alex



From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of 
StDenis, Tom
Sent: Thursday, September 15, 2016 9:32 AM
To: Christian König; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amd/amdgpu: Add sensors debugfs support



I don't mind splitting this into pp/headers then amdgpu_device.c.



Took a bit to get the userland formatting pretty but it works.  Can --top the 
PM values.  If we could get temp/watt/etc readings in the kernel I could throw 
those in userland too.



Tom





From: Christian König >
Sent: Thursday, September 15, 2016 09:29
To: Tom St Denis; 
amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom
Subject: Re: [PATCH] drm/amd/amdgpu: Add sensors debugfs support



Am 15.09.2016 um 15:22 schrieb Tom St Denis:
> This patch adds a callback to powerplay which
> reads specific PP sensors (vdd/clocks/load) which is then
> accessible via debugfs.  The idea being is it'll be a standard
> interface between different ASICs that userland tools can
> read.
>
> Currently only CZ/ST is supported but the others are
> NULL'ed off so they shouldn't cause any sort of oops.
>
> Signed-off-by: Tom St Denis >

Might be a good idea to split this into implementing the
backend/frontend functions, but this way works for me as well.

Acked-by: Christian König 
>.

Regards,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31 +++
>   drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 20 +
>   drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 96 
> ++
>   drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   |  1 +
>   .../gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c|  1 +
>   .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  |  1 +
>   drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  |  1 +
>   drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  | 10 +++
>   drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  1 +
>   9 files changed, 162 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 9103e7baf26e..b6a4588c95ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2841,6 +2841,29 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct 
> file *f, char __user *buf,
>return result;
>   }
>
> +static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
> + size_t size, loff_t *pos)
> +{
> + struct amdgpu_device *adev = f->f_inode->i_private;
> + int r;
> + int32_t value;
> +
> + if (size != 4 || *pos & 0x3)
> + return -EINVAL;
> +
> + /* convert offset to sensor number */
> + *pos >>= 2;
> +
> + if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
> + r = 
> adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, *pos, 
> );
> + else
> + r = -EINVAL;
> +
> + if (!r)
> + r = put_user(value, (int32_t *)buf);
> +
> + return !r ? 4 : r;
> +}
>
>   static const struct file_operations amdgpu_debugfs_regs_fops = {
>.owner = THIS_MODULE,
> @@ -2873,12 +2896,19 @@ static const struct file_operations 
> amdgpu_debugfs_gca_config_fops = {
>.llseek = default_llseek
>   };
>
> +static const struct file_operations amdgpu_debugfs_sensors_fops = {
> + .owner = THIS_MODULE,
> + .read = amdgpu_debugfs_sensor_read,
> + .llseek = default_llseek
> +};
> +
>   static const struct file_operations *debugfs_regs[] = {
>_debugfs_regs_fops,
>_debugfs_regs_didt_fops,
>_debugfs_regs_pcie_fops,
>_debugfs_regs_smc_fops,
>_debugfs_gca_config_fops,
> + _debugfs_sensors_fops,
>   };
>
>   static const char *debugfs_regs_names[] = {
> @@ -2887,6 +2917,7 @@ static const char *debugfs_regs_names[] = {
>"amdgpu_regs_pcie",
>"amdgpu_regs_smc",
>"amdgpu_gca_config",
> + "amdgpu_sensors",
>   };
>
>   static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
> 

[PATCH] drm/amdgpu/si: fix ring size for compute

[Alex Deucher]

We switched the other asics, but missed this.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index a1484b8..9697994 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -2779,7 +2779,7 @@ static int gfx_v6_0_sw_init(void *handle)
ring->queue = i;
sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, 
ring->queue);
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
-   r = amdgpu_ring_init(adev, ring, 1024 * 1024,
+   r = amdgpu_ring_init(adev, ring, 1024,
 0x8000, 0xf,
 >gfx.eop_irq, irq_type,
 AMDGPU_RING_TYPE_COMPUTE);
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 6/6] drm/amdgpu: add VRAM manager v2

[Alex Deucher]

On Thu, Sep 15, 2016 at 6:12 AM, Christian König
 wrote:
> From: Christian König 
>
> Split VRAM allocations into 4MB blocks.
>
> v2: fix typo in comment, some suggested cleanups
>
> Signed-off-by: Christian König 
> ---
>  drivers/gpu/drm/amd/amdgpu/Makefile  |   2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h  |   1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   |   7 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  |   4 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c   |   1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |   2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h  |   1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 222 
> +++
>  8 files changed, 238 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index f2b97cb..236e9df 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -30,7 +30,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
> atombios_encoders.o amdgpu_sa.o atombios_i2c.o \
> amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
> amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
> -   amdgpu_gtt_mgr.o
> +   amdgpu_gtt_mgr.o amdgpu_vram_mgr.o
>
>  # add asic specific block
>  amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 588baaf..ee55763 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -98,6 +98,7 @@ extern char *amdgpu_disable_cu;
>  extern int amdgpu_sclk_deep_sleep_en;
>  extern char *amdgpu_virtual_display;
>  extern unsigned amdgpu_pp_feature_mask;
> +extern int amdgpu_vram_page_split;
>
>  #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
>  #define AMDGPU_MAX_USEC_TIMEOUT10  /* 100 ms */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 5686d12..f26b067 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1012,6 +1012,13 @@ static void amdgpu_check_arguments(struct 
> amdgpu_device *adev)
>  amdgpu_vm_block_size);
> amdgpu_vm_block_size = 9;
> }
> +
> +   if ((amdgpu_vram_page_split != -1 && amdgpu_vram_page_split < 16) ||
> +   !amdgpu_check_pot_argument(amdgpu_vram_page_split)) {
> +   dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
> +amdgpu_vram_page_split);
> +   amdgpu_vram_page_split = 1024;
> +   }
>  }
>
>  /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 902da13..44e605d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -83,6 +83,7 @@ int amdgpu_vm_size = 64;
>  int amdgpu_vm_block_size = -1;
>  int amdgpu_vm_fault_stop = 0;
>  int amdgpu_vm_debug = 0;
> +int amdgpu_vram_page_split = 1024;
>  int amdgpu_exp_hw_support = 0;
>  int amdgpu_dal = -1;
>  int amdgpu_sched_jobs = 32;
> @@ -164,6 +165,9 @@ module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, 
> int, 0444);
>  MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = 
> enabled)");
>  module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
>
> +MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM 
> allocations (default 1024)");
> +module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);

Not a big deal, but maybe make this unsigned instead of int?  I don't
see any use for negative values.

Alex

> +
>  MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = 
> disable (default))");
>  module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 03c6bfc..d6e6c93 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -970,6 +970,7 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
> WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
> WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
>  !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
> +   WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
>
> return bo->tbo.offset;
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 4b8b39c..428ffb6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -168,7 +168,7 @@ static 

[PATCH 1/2] drm/amd/powerplay: Add read_sensor() callback to hwmgr

[Tom St Denis]

Provides standardized interface to read various sensors.
The API is extensible (by adding to the end of the
amd_pp_sensors enumeration list.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 20 +
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 96 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   |  1 +
 .../gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c|  1 +
 .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  |  1 +
 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  |  1 +
 drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  | 10 +++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  1 +
 8 files changed, 131 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index b1d19409bf86..ee0368381e82 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -894,6 +894,25 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
 }
 
+static int pp_dpm_read_sensor(void *handle, int idx, int32_t *value)
+{
+   struct pp_hwmgr *hwmgr;
+
+   if (!handle)
+   return -EINVAL;
+
+   hwmgr = ((struct pp_instance *)handle)->hwmgr;
+
+   PP_CHECK_HW(hwmgr);
+
+   if (hwmgr->hwmgr_func->read_sensor == NULL) {
+   printk(KERN_INFO "%s was not implemented.\n", __func__);
+   return 0;
+   }
+
+   return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value);
+}
+
 const struct amd_powerplay_funcs pp_dpm_funcs = {
.get_temperature = pp_dpm_get_temperature,
.load_firmware = pp_dpm_load_fw,
@@ -920,6 +939,7 @@ const struct amd_powerplay_funcs pp_dpm_funcs = {
.set_sclk_od = pp_dpm_set_sclk_od,
.get_mclk_od = pp_dpm_get_mclk_od,
.set_mclk_od = pp_dpm_set_mclk_od,
+   .read_sensor = pp_dpm_read_sensor,
 };
 
 static int amd_pp_instance_init(struct amd_pp_init *pp_init,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 5ecef1732e20..9f3c5a8a903c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1857,6 +1857,101 @@ static int cz_get_max_high_clocks(struct pp_hwmgr 
*hwmgr, struct amd_pp_simple_c
return 0;
 }
 
+static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
+{
+   struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+
+   struct phm_clock_voltage_dependency_table *table =
+   hwmgr->dyn_state.vddc_dependency_on_sclk;
+
+   struct phm_vce_clock_voltage_dependency_table *vce_table =
+   hwmgr->dyn_state.vce_clock_voltage_dependency_table;
+
+   struct phm_uvd_clock_voltage_dependency_table *uvd_table =
+   hwmgr->dyn_state.uvd_clock_voltage_dependency_table;
+
+   uint32_t sclk_index = 
PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 
ixTARGET_AND_CURRENT_PROFILE_INDEX),
+   TARGET_AND_CURRENT_PROFILE_INDEX, 
CURR_SCLK_INDEX);
+   uint32_t uvd_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, 
CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
+   TARGET_AND_CURRENT_PROFILE_INDEX_2, 
CURR_UVD_INDEX);
+   uint32_t vce_index = PHM_GET_FIELD(cgs_read_ind_register(hwmgr->device, 
CGS_IND_REG__SMC, ixTARGET_AND_CURRENT_PROFILE_INDEX_2),
+   TARGET_AND_CURRENT_PROFILE_INDEX_2, 
CURR_VCE_INDEX);
+
+   uint32_t sclk, vclk, dclk, ecclk, tmp, activity_percent;
+   uint16_t vddnb, vddgfx;
+   int result;
+
+   switch (idx) {
+   case AMDGPU_PP_SENSOR_GFX_SCLK:
+   if (sclk_index < NUM_SCLK_LEVELS) {
+   sclk = table->entries[sclk_index].clk;
+   *value = sclk;
+   return 0;
+   }
+   return -EINVAL;
+   case AMDGPU_PP_SENSOR_VDDNB:
+   tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 
ixSMUSVI_NB_CURRENTVID) &
+   CURRENT_NB_VID_MASK) >> CURRENT_NB_VID__SHIFT;
+   vddnb = cz_convert_8Bit_index_to_voltage(hwmgr, tmp);
+   *value = vddnb;
+   return 0;
+   case AMDGPU_PP_SENSOR_VDDGFX:
+   tmp = (cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, 
ixSMUSVI_GFX_CURRENTVID) &
+   CURRENT_GFX_VID_MASK) >> CURRENT_GFX_VID__SHIFT;
+   vddgfx = cz_convert_8Bit_index_to_voltage(hwmgr, (u16)tmp);
+   *value = vddgfx;
+   return 0;
+   case AMDGPU_PP_SENSOR_UVD_VCLK:
+   if (!cz_hwmgr->uvd_power_gated) {
+   if (uvd_index >= CZ_MAX_HARDWARE_POWERLEVELS) {
+   

[PATCH 2/2] drm/amd/amdgpu: Hook up read_sensor() to debugfs

[Tom St Denis]

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31 ++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9103e7baf26e..b6a4588c95ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2841,6 +2841,29 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct 
file *f, char __user *buf,
return result;
 }
 
+static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
+   size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = f->f_inode->i_private;
+   int r;
+   int32_t value;
+
+   if (size != 4 || *pos & 0x3)
+   return -EINVAL;
+
+   /* convert offset to sensor number */
+   *pos >>= 2;
+
+   if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
+   r = 
adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, *pos, );
+   else
+   r = -EINVAL;
+
+   if (!r)
+   r = put_user(value, (int32_t *)buf);
+
+   return !r ? 4 : r;
+}
 
 static const struct file_operations amdgpu_debugfs_regs_fops = {
.owner = THIS_MODULE,
@@ -2873,12 +2896,19 @@ static const struct file_operations 
amdgpu_debugfs_gca_config_fops = {
.llseek = default_llseek
 };
 
+static const struct file_operations amdgpu_debugfs_sensors_fops = {
+   .owner = THIS_MODULE,
+   .read = amdgpu_debugfs_sensor_read,
+   .llseek = default_llseek
+};
+
 static const struct file_operations *debugfs_regs[] = {
_debugfs_regs_fops,
_debugfs_regs_didt_fops,
_debugfs_regs_pcie_fops,
_debugfs_regs_smc_fops,
_debugfs_gca_config_fops,
+   _debugfs_sensors_fops,
 };
 
 static const char *debugfs_regs_names[] = {
@@ -2887,6 +2917,7 @@ static const char *debugfs_regs_names[] = {
"amdgpu_regs_pcie",
"amdgpu_regs_smc",
"amdgpu_gca_config",
+   "amdgpu_sensors",
 };
 
 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
-- 
2.10.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/amdgpu: Add sensors debugfs support

[StDenis, Tom]

I don't mind splitting this into pp/headers then amdgpu_device.c.


Took a bit to get the userland formatting pretty but it works.  Can --top the 
PM values.  If we could get temp/watt/etc readings in the kernel I could throw 
those in userland too.


Tom



From: Christian König 
Sent: Thursday, September 15, 2016 09:29
To: Tom St Denis; amd-gfx@lists.freedesktop.org
Cc: StDenis, Tom
Subject: Re: [PATCH] drm/amd/amdgpu: Add sensors debugfs support

Am 15.09.2016 um 15:22 schrieb Tom St Denis:
> This patch adds a callback to powerplay which
> reads specific PP sensors (vdd/clocks/load) which is then
> accessible via debugfs.  The idea being is it'll be a standard
> interface between different ASICs that userland tools can
> read.
>
> Currently only CZ/ST is supported but the others are
> NULL'ed off so they shouldn't cause any sort of oops.
>
> Signed-off-by: Tom St Denis 

Might be a good idea to split this into implementing the
backend/frontend functions, but this way works for me as well.

Acked-by: Christian König .

Regards,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31 +++
>   drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 20 +
>   drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 96 
> ++
>   drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   |  1 +
>   .../gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c|  1 +
>   .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  |  1 +
>   drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  |  1 +
>   drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  | 10 +++
>   drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  1 +
>   9 files changed, 162 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 9103e7baf26e..b6a4588c95ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2841,6 +2841,29 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct 
> file *f, char __user *buf,
>return result;
>   }
>
> +static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
> + size_t size, loff_t *pos)
> +{
> + struct amdgpu_device *adev = f->f_inode->i_private;
> + int r;
> + int32_t value;
> +
> + if (size != 4 || *pos & 0x3)
> + return -EINVAL;
> +
> + /* convert offset to sensor number */
> + *pos >>= 2;
> +
> + if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
> + r = 
> adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, *pos, 
> );
> + else
> + r = -EINVAL;
> +
> + if (!r)
> + r = put_user(value, (int32_t *)buf);
> +
> + return !r ? 4 : r;
> +}
>
>   static const struct file_operations amdgpu_debugfs_regs_fops = {
>.owner = THIS_MODULE,
> @@ -2873,12 +2896,19 @@ static const struct file_operations 
> amdgpu_debugfs_gca_config_fops = {
>.llseek = default_llseek
>   };
>
> +static const struct file_operations amdgpu_debugfs_sensors_fops = {
> + .owner = THIS_MODULE,
> + .read = amdgpu_debugfs_sensor_read,
> + .llseek = default_llseek
> +};
> +
>   static const struct file_operations *debugfs_regs[] = {
>_debugfs_regs_fops,
>_debugfs_regs_didt_fops,
>_debugfs_regs_pcie_fops,
>_debugfs_regs_smc_fops,
>_debugfs_gca_config_fops,
> + _debugfs_sensors_fops,
>   };
>
>   static const char *debugfs_regs_names[] = {
> @@ -2887,6 +2917,7 @@ static const char *debugfs_regs_names[] = {
>"amdgpu_regs_pcie",
>"amdgpu_regs_smc",
>"amdgpu_gca_config",
> + "amdgpu_sensors",
>   };
>
>   static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
> b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> index b1d19409bf86..ee0368381e82 100644
> --- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> +++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
> @@ -894,6 +894,25 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t 
> value)
>return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
>   }
>
> +static int pp_dpm_read_sensor(void *handle, int idx, int32_t *value)
> +{
> + struct pp_hwmgr *hwmgr;
> +
> + if (!handle)
> + return -EINVAL;
> +
> + hwmgr = ((struct pp_instance *)handle)->hwmgr;
> +
> + PP_CHECK_HW(hwmgr);
> +
> + if (hwmgr->hwmgr_func->read_sensor == NULL) {
> + printk(KERN_INFO "%s was not implemented.\n", __func__);
> + return 0;
> + }
> +
> + return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value);
> +}
> +
>   const struct amd_powerplay_funcs pp_dpm_funcs = {
>.get_temperature = pp_dpm_get_temperature,
>.load_firmware = pp_dpm_load_fw,
> @@ 

Add sensors support to debugfs for Powerplay

[Tom St Denis]

This patch adds the ability to read various sensors from userspace.
It's extensible so we can always add more later on.

Currently CZ/ST supported (CZ tested with a WIP copy of the debug
tool).

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH] drm/amd/amdgpu: Add sensors debugfs support

[Tom St Denis]

This patch adds a callback to powerplay which
reads specific PP sensors (vdd/clocks/load) which is then
accessible via debugfs.  The idea being is it'll be a standard
interface between different ASICs that userland tools can
read.

Currently only CZ/ST is supported but the others are
NULL'ed off so they shouldn't cause any sort of oops.

Signed-off-by: Tom St Denis 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 31 +++
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c  | 20 +
 drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c | 96 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c   |  1 +
 .../gpu/drm/amd/powerplay/hwmgr/iceland_hwmgr.c|  1 +
 .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c  |  1 +
 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c  |  1 +
 drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h  | 10 +++
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h  |  1 +
 9 files changed, 162 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9103e7baf26e..b6a4588c95ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2841,6 +2841,29 @@ static ssize_t amdgpu_debugfs_gca_config_read(struct 
file *f, char __user *buf,
return result;
 }
 
+static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
+   size_t size, loff_t *pos)
+{
+   struct amdgpu_device *adev = f->f_inode->i_private;
+   int r;
+   int32_t value;
+
+   if (size != 4 || *pos & 0x3)
+   return -EINVAL;
+
+   /* convert offset to sensor number */
+   *pos >>= 2;
+
+   if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
+   r = 
adev->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, *pos, );
+   else
+   r = -EINVAL;
+
+   if (!r)
+   r = put_user(value, (int32_t *)buf);
+
+   return !r ? 4 : r;
+}
 
 static const struct file_operations amdgpu_debugfs_regs_fops = {
.owner = THIS_MODULE,
@@ -2873,12 +2896,19 @@ static const struct file_operations 
amdgpu_debugfs_gca_config_fops = {
.llseek = default_llseek
 };
 
+static const struct file_operations amdgpu_debugfs_sensors_fops = {
+   .owner = THIS_MODULE,
+   .read = amdgpu_debugfs_sensor_read,
+   .llseek = default_llseek
+};
+
 static const struct file_operations *debugfs_regs[] = {
_debugfs_regs_fops,
_debugfs_regs_didt_fops,
_debugfs_regs_pcie_fops,
_debugfs_regs_smc_fops,
_debugfs_gca_config_fops,
+   _debugfs_sensors_fops,
 };
 
 static const char *debugfs_regs_names[] = {
@@ -2887,6 +2917,7 @@ static const char *debugfs_regs_names[] = {
"amdgpu_regs_pcie",
"amdgpu_regs_smc",
"amdgpu_gca_config",
+   "amdgpu_sensors",
 };
 
 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index b1d19409bf86..ee0368381e82 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -894,6 +894,25 @@ static int pp_dpm_set_mclk_od(void *handle, uint32_t value)
return hwmgr->hwmgr_func->set_mclk_od(hwmgr, value);
 }
 
+static int pp_dpm_read_sensor(void *handle, int idx, int32_t *value)
+{
+   struct pp_hwmgr *hwmgr;
+
+   if (!handle)
+   return -EINVAL;
+
+   hwmgr = ((struct pp_instance *)handle)->hwmgr;
+
+   PP_CHECK_HW(hwmgr);
+
+   if (hwmgr->hwmgr_func->read_sensor == NULL) {
+   printk(KERN_INFO "%s was not implemented.\n", __func__);
+   return 0;
+   }
+
+   return hwmgr->hwmgr_func->read_sensor(hwmgr, idx, value);
+}
+
 const struct amd_powerplay_funcs pp_dpm_funcs = {
.get_temperature = pp_dpm_get_temperature,
.load_firmware = pp_dpm_load_fw,
@@ -920,6 +939,7 @@ const struct amd_powerplay_funcs pp_dpm_funcs = {
.set_sclk_od = pp_dpm_set_sclk_od,
.get_mclk_od = pp_dpm_get_mclk_od,
.set_mclk_od = pp_dpm_set_mclk_od,
+   .read_sensor = pp_dpm_read_sensor,
 };
 
 static int amd_pp_instance_init(struct amd_pp_init *pp_init,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
index 5ecef1732e20..9f3c5a8a903c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/cz_hwmgr.c
@@ -1857,6 +1857,101 @@ static int cz_get_max_high_clocks(struct pp_hwmgr 
*hwmgr, struct amd_pp_simple_c
return 0;
 }
 
+static int cz_read_sensor(struct pp_hwmgr *hwmgr, int idx, int32_t *value)
+{
+   struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
+
+   struct phm_clock_voltage_dependency_table *table =
+   

[PATCH 5/5] drm/amdgpu: rename all rbo variable to abo

[Christian König]

From: Christian König 

Just to cleanup some radeon leftovers.

sed -i "s/rbo/abo/g" drivers/gpu/drm/amd/amdgpu/*.c
sed -i "s/rbo/abo/g" drivers/gpu/drm/amd/amdgpu/*.h

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h |  4 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 42 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  | 44 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 20 ++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c  | 16 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 24 
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c |  8 +++---
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c  | 36 +++
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c  | 36 +++
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c   | 36 +++
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c   | 36 +++
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c| 12 
 12 files changed, 157 insertions(+), 157 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ed91f08..c30635a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -701,7 +701,7 @@ struct amdgpu_flip_work {
int crtc_id;
uint64_tbase;
struct drm_pending_vblank_event *event;
-   struct amdgpu_bo*old_rbo;
+   struct amdgpu_bo*old_abo;
struct fence*excl;
unsignedshared_count;
struct fence**shared;
@@ -2436,7 +2436,7 @@ int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, 
void *data);
 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
   u32 ip_instance, u32 ring,
   struct amdgpu_ring **out_ring);
-void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain);
+void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 93fd761..783e1d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -154,17 +154,17 @@ static void amdgpu_unpin_work_func(struct work_struct 
*__work)
int r;
 
/* unpin of the old buffer */
-   r = amdgpu_bo_reserve(work->old_rbo, false);
+   r = amdgpu_bo_reserve(work->old_abo, false);
if (likely(r == 0)) {
-   r = amdgpu_bo_unpin(work->old_rbo);
+   r = amdgpu_bo_unpin(work->old_abo);
if (unlikely(r != 0)) {
DRM_ERROR("failed to unpin buffer after flip\n");
}
-   amdgpu_bo_unreserve(work->old_rbo);
+   amdgpu_bo_unreserve(work->old_abo);
} else
DRM_ERROR("failed to reserve buffer after flip\n");
 
-   amdgpu_bo_unref(>old_rbo);
+   amdgpu_bo_unref(>old_abo);
kfree(work->shared);
kfree(work);
 }
@@ -181,7 +181,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
struct amdgpu_framebuffer *new_amdgpu_fb;
struct drm_gem_object *obj;
struct amdgpu_flip_work *work;
-   struct amdgpu_bo *new_rbo;
+   struct amdgpu_bo *new_abo;
unsigned long flags;
u64 tiling_flags;
u64 base;
@@ -204,28 +204,28 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
obj = old_amdgpu_fb->obj;
 
/* take a reference to the old object */
-   work->old_rbo = gem_to_amdgpu_bo(obj);
-   amdgpu_bo_ref(work->old_rbo);
+   work->old_abo = gem_to_amdgpu_bo(obj);
+   amdgpu_bo_ref(work->old_abo);
 
new_amdgpu_fb = to_amdgpu_framebuffer(fb);
obj = new_amdgpu_fb->obj;
-   new_rbo = gem_to_amdgpu_bo(obj);
+   new_abo = gem_to_amdgpu_bo(obj);
 
/* pin the new buffer */
-   r = amdgpu_bo_reserve(new_rbo, false);
+   r = amdgpu_bo_reserve(new_abo, false);
if (unlikely(r != 0)) {
-   DRM_ERROR("failed to reserve new rbo buffer before flip\n");
+   DRM_ERROR("failed to reserve new abo buffer before flip\n");
goto cleanup;
}
 
-   r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, 
);
+   r = amdgpu_bo_pin_restricted(new_abo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, 
);
if (unlikely(r != 0)) {
r = -EINVAL;
-   DRM_ERROR("failed to pin new rbo buffer before flip\n");
+   DRM_ERROR("failed to pin new abo buffer before 

[PATCH 1/5] drm/amdgpu: remove unused member from struct amdgpu_bo

[Christian König]

From: Christian König 

Not used in a while.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 2 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 -
 2 files changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index ee55763..3b3981d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -446,8 +446,6 @@ struct amdgpu_bo_va {
 #define AMDGPU_GEM_DOMAIN_MAX  0x3
 
 struct amdgpu_bo {
-   /* Protected by gem.mutex */
-   struct list_headlist;
/* Protected by tbo.reserved */
u32 prefered_domains;
u32 allowed_domains;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index d6e6c93..4289c31 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -360,7 +360,6 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
return r;
}
bo->adev = adev;
-   INIT_LIST_HEAD(>list);
INIT_LIST_HEAD(>shadow_list);
INIT_LIST_HEAD(>va);
bo->prefered_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
-- 
2.5.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/5] drm/amdgpu: fix a bunch of coding style issues in amdgpu_gem.c

[Christian König]

From: Christian König 

No intented functional change.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 88fbed2..70e294b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -58,7 +58,8 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, 
unsigned long size,
alignment = PAGE_SIZE;
}
 
-   if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | 
AMDGPU_GEM_DOMAIN_OA))) {
+   if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS |
+   AMDGPU_GEM_DOMAIN_OA))) {
/* Maximum bo size is the unpinned gtt size since we use the 
gtt to
 * handle vram to system pool migrations.
 */
@@ -116,7 +117,8 @@ void amdgpu_gem_force_release(struct amdgpu_device *adev)
  * Call from drm_gem_handle_create which appear in both new and open ioctl
  * case.
  */
-int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file 
*file_priv)
+int amdgpu_gem_object_open(struct drm_gem_object *obj,
+  struct drm_file *file_priv)
 {
struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
struct amdgpu_device *adev = rbo->adev;
@@ -408,9 +410,11 @@ int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, 
void *data,
}
robj = gem_to_amdgpu_bo(gobj);
if (timeout == 0)
-   ret = reservation_object_test_signaled_rcu(robj->tbo.resv, 
true);
+   ret = reservation_object_test_signaled_rcu(robj->tbo.resv,
+  true);
else
-   ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, 
true, timeout);
+   ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true,
+ true, timeout);
 
/* ret == 0 means not signaled,
 * ret > 0 means signaled
@@ -480,7 +484,8 @@ out:
  * vital here, so they are not reported back to userspace.
  */
 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
-   struct amdgpu_bo_va *bo_va, uint32_t 
operation)
+   struct amdgpu_bo_va *bo_va,
+   uint32_t operation)
 {
struct ttm_validate_buffer tv, *entry;
struct amdgpu_bo_list_entry vm_pd;
@@ -704,7 +709,8 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
uint32_t handle;
int r;
 
-   args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * 
((args->bpp + 1) / 8);
+   args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) *
+   ((args->bpp + 1) / 8);
args->size = (u64)args->pitch * args->height;
args->size = ALIGN(args->size, PAGE_SIZE);
 
-- 
2.5.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/5] drm/amdgpu: remove adev pointer from struct amdgpu_bo

[Christian König]

From: Christian König 

It's completely pointsless to have two pointers to the
device in the same structur.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  6 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 10 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c|  4 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c |  4 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 50 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.h |  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 17 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c|  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c |  2 +-
 9 files changed, 50 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3b3981d..ed91f08 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -465,7 +465,6 @@ struct amdgpu_bo {
 */
struct list_headva;
/* Constant after initialization */
-   struct amdgpu_device*adev;
struct drm_gem_object   gem_base;
struct amdgpu_bo*parent;
struct amdgpu_bo*shadow;
@@ -2144,6 +2143,11 @@ struct amdgpu_device {
 
 };
 
+static inline struct amdgpu_device *amdgpu_get_adev(struct ttm_bo_device *bdev)
+{
+   return container_of(bdev, struct amdgpu_device, mman.bdev);
+}
+
 bool amdgpu_device_is_px(struct drm_device *dev);
 int amdgpu_device_init(struct amdgpu_device *adev,
   struct drm_device *ddev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 187c366..5beab71 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -355,6 +355,7 @@ static void amdgpu_cs_report_moved_bytes(struct 
amdgpu_device *adev,
 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 struct amdgpu_bo *bo)
 {
+   struct amdgpu_device *adev = amdgpu_get_adev(bo->tbo.bdev);
u64 initial_bytes_moved;
uint32_t domain;
int r;
@@ -372,9 +373,9 @@ static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
 
 retry:
amdgpu_ttm_placement_from_domain(bo, domain);
-   initial_bytes_moved = atomic64_read(>adev->num_bytes_moved);
+   initial_bytes_moved = atomic64_read(>num_bytes_moved);
r = ttm_bo_validate(>tbo, >placement, true, false);
-   p->bytes_moved += atomic64_read(>adev->num_bytes_moved) -
+   p->bytes_moved += atomic64_read(>num_bytes_moved) -
initial_bytes_moved;
 
if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
@@ -400,6 +401,7 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 
struct amdgpu_bo_list_entry *candidate = p->evictable;
struct amdgpu_bo *bo = candidate->robj;
+   struct amdgpu_device *adev = amdgpu_get_adev(bo->tbo.bdev);
u64 initial_bytes_moved;
uint32_t other;
 
@@ -420,9 +422,9 @@ static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
 
/* Good we can try to move this BO somewhere else */
amdgpu_ttm_placement_from_domain(bo, other);
-   initial_bytes_moved = atomic64_read(>adev->num_bytes_moved);
+   initial_bytes_moved = atomic64_read(>num_bytes_moved);
r = ttm_bo_validate(>tbo, >placement, true, false);
-   p->bytes_moved += atomic64_read(>adev->num_bytes_moved) -
+   p->bytes_moved += atomic64_read(>num_bytes_moved) -
initial_bytes_moved;
 
if (unlikely(r))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 70e294b..480ae7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -121,7 +121,7 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj,
   struct drm_file *file_priv)
 {
struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj);
-   struct amdgpu_device *adev = rbo->adev;
+   struct amdgpu_device *adev = amdgpu_get_adev(rbo->tbo.bdev);
struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
struct amdgpu_vm *vm = >vm;
struct amdgpu_bo_va *bo_va;
@@ -144,7 +144,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
 struct drm_file *file_priv)
 {
struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
-   struct amdgpu_device *adev = bo->adev;
+   struct amdgpu_device *adev = amdgpu_get_adev(bo->tbo.bdev);
struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
struct amdgpu_vm *vm = >vm;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index 32fa7b7..4731231 100644
--- 

[PATCH 5/6] drm/amdgpu: enable amdgpu_move_blit to handle multiple MM nodes v2

[Christian König]

From: Christian König 

This allows us to move scattered buffers around.

v2: fix a couple of typos, handle scattered to scattered moves as well.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 118 +++-
 1 file changed, 85 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index b1f5d73..4b8b39c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -259,64 +259,116 @@ static void amdgpu_move_null(struct ttm_buffer_object 
*bo,
new_mem->mm_node = NULL;
 }
 
-static int amdgpu_move_blit(struct ttm_buffer_object *bo,
-   bool evict, bool no_wait_gpu,
-   struct ttm_mem_reg *new_mem,
-   struct ttm_mem_reg *old_mem)
+static int amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
+  struct drm_mm_node *mm_node,
+  struct ttm_mem_reg *mem,
+  uint64_t *addr)
 {
-   struct amdgpu_device *adev;
-   struct amdgpu_ring *ring;
-   uint64_t old_start, new_start;
-   struct fence *fence;
int r;
 
-   adev = amdgpu_get_adev(bo->bdev);
-   ring = adev->mman.buffer_funcs_ring;
-   old_start = (u64)old_mem->start << PAGE_SHIFT;
-   new_start = (u64)new_mem->start << PAGE_SHIFT;
-
-   switch (old_mem->mem_type) {
+   switch (mem->mem_type) {
case TTM_PL_TT:
-   r = amdgpu_ttm_bind(bo, old_mem);
+   r = amdgpu_ttm_bind(bo, mem);
if (r)
return r;
 
case TTM_PL_VRAM:
-   old_start += bo->bdev->man[old_mem->mem_type].gpu_offset;
+   *addr = mm_node->start << PAGE_SHIFT;
+   *addr += bo->bdev->man[mem->mem_type].gpu_offset;
break;
default:
-   DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
+   DRM_ERROR("Unknown placement %d\n", mem->mem_type);
return -EINVAL;
}
-   switch (new_mem->mem_type) {
-   case TTM_PL_TT:
-   r = amdgpu_ttm_bind(bo, new_mem);
-   if (r)
-   return r;
 
-   case TTM_PL_VRAM:
-   new_start += bo->bdev->man[new_mem->mem_type].gpu_offset;
-   break;
-   default:
-   DRM_ERROR("Unknown placement %d\n", old_mem->mem_type);
-   return -EINVAL;
-   }
+   return 0;
+}
+
+static int amdgpu_move_blit(struct ttm_buffer_object *bo,
+   bool evict, bool no_wait_gpu,
+   struct ttm_mem_reg *new_mem,
+   struct ttm_mem_reg *old_mem)
+{
+   struct amdgpu_device *adev = amdgpu_get_adev(bo->bdev);
+   struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+
+   struct drm_mm_node *old_mm, *new_mm;
+   uint64_t old_start, old_size, new_start, new_size;
+   unsigned long num_pages;
+   struct fence *fence = NULL;
+   int r;
+
+   BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
+
if (!ring->ready) {
DRM_ERROR("Trying to move memory with ring turned off.\n");
return -EINVAL;
}
 
-   BUILD_BUG_ON((PAGE_SIZE % AMDGPU_GPU_PAGE_SIZE) != 0);
+   old_mm = old_mem->mm_node;
+   r = amdgpu_mm_node_addr(bo, old_mm, old_mem, _start);
+   if (r)
+   return r;
+   old_size = old_mm->size;
+
 
-   r = amdgpu_copy_buffer(ring, old_start, new_start,
-  new_mem->num_pages * PAGE_SIZE, /* bytes */
-  bo->resv, , false);
+   new_mm = new_mem->mm_node;
+   r = amdgpu_mm_node_addr(bo, new_mm, new_mem, _start);
if (r)
return r;
+   new_size = new_mm->size;
+
+   num_pages = new_mem->num_pages;
+   while (num_pages) {
+   unsigned long cur_pages = min(old_size, new_size);
+   struct fence *next;
+
+   r = amdgpu_copy_buffer(ring, old_start, new_start,
+  cur_pages * PAGE_SIZE,
+  bo->resv, , false);
+   if (r)
+   goto error;
+
+   fence_put(fence);
+   fence = next;
+
+   num_pages -= cur_pages;
+   if (!num_pages)
+   break;
+
+   old_size -= cur_pages;
+   if (!old_size) {
+   r = amdgpu_mm_node_addr(bo, ++old_mm, old_mem,
+   _start);
+   if (r)
+   goto error;
+   old_size = old_mm->size;
+   } else {
+   old_start += cur_pages 

[PATCH 3/6] drm/amdgpu: set at least the node size in the gtt manager

[Christian König]

From: Christian König 

Otherwise the new VM code becomes confused.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 262e872..957a788 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -167,6 +167,7 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager 
*man,
return -ENOMEM;
 
node->start = AMDGPU_BO_INVALID_OFFSET;
+   node->size = mem->num_pages;
mem->mm_node = node;
 
if (place->fpfn || place->lpfn || place->flags & TTM_PL_FLAG_TOPDOWN) {
-- 
2.5.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/6] drm/amdgpu: add AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag v3

[Christian König]

From: Christian König 

Add a flag noting that a BO must be created using linear VRAM
and set this flag on all in kernel users where appropriate.

Hopefully I haven't missed anything.

v2: add it in a few more places, fix CPU mapping.
v3: rename to VRAM_CONTIGUOUS, fix typo in CS code.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c|  6 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |  9 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c   |  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 12 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c|  6 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c|  3 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c |  6 --
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c  |  9 ++---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |  6 --
 include/uapi/drm/amdgpu_drm.h  |  2 ++
 13 files changed, 53 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index f1c53a2..79a3b98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -146,7 +146,8 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device 
*cgs_device,
switch(type) {
case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
case CGS_GPU_MEM_TYPE__VISIBLE_FB:
-   flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+   flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+   AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
domain = AMDGPU_GEM_DOMAIN_VRAM;
if (max_offset > adev->mc.real_vram_size)
return -EINVAL;
@@ -157,7 +158,8 @@ static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device 
*cgs_device,
break;
case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
-   flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
+   flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
+   AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
domain = AMDGPU_GEM_DOMAIN_VRAM;
if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
place.fpfn =
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index b0f6e69..187c366 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1195,6 +1195,15 @@ int amdgpu_cs_sysvm_access_required(struct 
amdgpu_cs_parser *parser)
r = amdgpu_ttm_bind(>tbo, >tbo.mem);
if (unlikely(r))
return r;
+
+   if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
+   continue;
+
+   bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+   amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains);
+   r = ttm_bo_validate(>tbo, >placement, false, false);
+   if (unlikely(r))
+   return r;
}
 
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9103e7b..5686d12 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -264,7 +264,8 @@ static int amdgpu_vram_scratch_init(struct amdgpu_device 
*adev)
if (adev->vram_scratch.robj == NULL) {
r = amdgpu_bo_create(adev, AMDGPU_GPU_PAGE_SIZE,
 PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
-AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
+AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 NULL, NULL, >vram_scratch.robj);
if (r) {
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 10e0211..95a4cdd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -148,7 +148,8 @@ static int amdgpufb_create_pinned_object(struct 
amdgpu_fbdev *rfbdev,
aligned_size = ALIGN(size, PAGE_SIZE);
ret = amdgpu_gem_object_create(adev, aligned_size, 0,
   AMDGPU_GEM_DOMAIN_VRAM,
-  AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
+  AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
+  AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
   true, );
if (ret) {
printk(KERN_ERR "failed to allocate framebuffer (%d)\n",
diff 

[PATCH 6/6] drm/amdgpu: add VRAM manager v2

[Christian König]

From: Christian König 

Split VRAM allocations into 4MB blocks.

v2: fix typo in comment, some suggested cleanups

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/Makefile  |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c   |   7 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c  |   4 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c   |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h  |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 222 +++
 8 files changed, 238 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index f2b97cb..236e9df 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -30,7 +30,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
atombios_encoders.o amdgpu_sa.o atombios_i2c.o \
amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
-   amdgpu_gtt_mgr.o
+   amdgpu_gtt_mgr.o amdgpu_vram_mgr.o
 
 # add asic specific block
 amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 588baaf..ee55763 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -98,6 +98,7 @@ extern char *amdgpu_disable_cu;
 extern int amdgpu_sclk_deep_sleep_en;
 extern char *amdgpu_virtual_display;
 extern unsigned amdgpu_pp_feature_mask;
+extern int amdgpu_vram_page_split;
 
 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
 #define AMDGPU_MAX_USEC_TIMEOUT10  /* 100 ms */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5686d12..f26b067 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1012,6 +1012,13 @@ static void amdgpu_check_arguments(struct amdgpu_device 
*adev)
 amdgpu_vm_block_size);
amdgpu_vm_block_size = 9;
}
+
+   if ((amdgpu_vram_page_split != -1 && amdgpu_vram_page_split < 16) ||
+   !amdgpu_check_pot_argument(amdgpu_vram_page_split)) {
+   dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
+amdgpu_vram_page_split);
+   amdgpu_vram_page_split = 1024;
+   }
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 902da13..44e605d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -83,6 +83,7 @@ int amdgpu_vm_size = 64;
 int amdgpu_vm_block_size = -1;
 int amdgpu_vm_fault_stop = 0;
 int amdgpu_vm_debug = 0;
+int amdgpu_vram_page_split = 1024;
 int amdgpu_exp_hw_support = 0;
 int amdgpu_dal = -1;
 int amdgpu_sched_jobs = 32;
@@ -164,6 +165,9 @@ module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, 
int, 0444);
 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = 
enabled)");
 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
 
+MODULE_PARM_DESC(vram_page_split, "Number of pages after we split VRAM 
allocations (default 1024)");
+module_param_named(vram_page_split, amdgpu_vram_page_split, int, 0444);
+
 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = 
disable (default))");
 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 03c6bfc..d6e6c93 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -970,6 +970,7 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
+   WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
 
return bo->tbo.offset;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 4b8b39c..428ffb6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -168,7 +168,7 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, 
uint32_t type,
break;
case TTM_PL_VRAM:
/* "On-card" video ram */
-   man->func = _bo_manager_func;
+   man->func = _vram_mgr_func;
man->gpu_offset = adev->mc.vram_start;
man->flags = TTM_MEMTYPE_FLAG_FIXED |
 

[PATCH 4/6] drm/amdgpu: handle multiple MM nodes in the VMs v2

[Christian König]

From: Christian König 

This allows us to map scattered VRAM BOs to the VMs.

v2: fix offset handling, use pfn instead of offset,
fix PAGE_SIZE != AMDGPU_GPU_PAGE_SIZE case

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 81 +++---
 1 file changed, 46 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 87c990e..d3a2d1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1049,8 +1049,8 @@ error_free:
  * @pages_addr: DMA addresses to use for mapping
  * @vm: requested vm
  * @mapping: mapped range and flags to use for the update
- * @addr: addr to set the area to
  * @flags: HW flags for the mapping
+ * @nodes: array of drm_mm_nodes with the MC addresses
  * @fence: optional resulting fence
  *
  * Split the mapping into smaller chunks so that each update fits
@@ -1063,12 +1063,11 @@ static int amdgpu_vm_bo_split_mapping(struct 
amdgpu_device *adev,
  dma_addr_t *pages_addr,
  struct amdgpu_vm *vm,
  struct amdgpu_bo_va_mapping *mapping,
- uint32_t flags, uint64_t addr,
+ uint32_t flags,
+ struct drm_mm_node *nodes,
  struct fence **fence)
 {
-   const uint64_t max_size = 64ULL * 1024ULL * 1024ULL / 
AMDGPU_GPU_PAGE_SIZE;
-
-   uint64_t src = 0, start = mapping->it.start;
+   uint64_t pfn, src = 0, start = mapping->it.start;
int r;
 
/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go 
here
@@ -1081,23 +1080,40 @@ static int amdgpu_vm_bo_split_mapping(struct 
amdgpu_device *adev,
 
trace_amdgpu_vm_bo_update(mapping);
 
-   if (pages_addr) {
-   if (flags == gtt_flags)
-   src = adev->gart.table_addr + (addr >> 12) * 8;
-   addr = 0;
+   pfn = mapping->offset >> PAGE_SHIFT;
+   if (nodes) {
+   while (pfn >= nodes->size) {
+   pfn -= nodes->size;
+   ++nodes;
+   }
}
-   addr += mapping->offset;
 
-   if (!pages_addr || src)
-   return amdgpu_vm_bo_update_mapping(adev, exclusive,
-  src, pages_addr, vm,
-  start, mapping->it.last,
-  flags, addr, fence);
+   do {
+   uint64_t max_entries;
+   uint64_t addr, last;
+
+   if (nodes) {
+   addr = nodes->start << PAGE_SHIFT;
+   max_entries = (nodes->size - pfn) *
+   (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
+   } else {
+   addr = 0;
+   max_entries = S64_MAX;
+   }
 
-   while (start != mapping->it.last + 1) {
-   uint64_t last;
+   if (pages_addr) {
+   if (flags == gtt_flags)
+   src = adev->gart.table_addr +
+   (addr >> AMDGPU_GPU_PAGE_SHIFT) * 8;
+   else
+   max_entries = min(max_entries, 16ull * 1024ull);
+   addr = 0;
+   } else if (flags & AMDGPU_PTE_VALID) {
+   addr += adev->vm_manager.vram_base_offset;
+   }
+   addr += pfn << PAGE_SHIFT;
 
-   last = min((uint64_t)mapping->it.last, start + max_size - 1);
+   last = min((uint64_t)mapping->it.last, start + max_entries - 1);
r = amdgpu_vm_bo_update_mapping(adev, exclusive,
src, pages_addr, vm,
start, last, flags, addr,
@@ -1105,9 +1121,14 @@ static int amdgpu_vm_bo_split_mapping(struct 
amdgpu_device *adev,
if (r)
return r;
 
+   pfn += last - start + 1;
+   if (nodes && nodes->size == pfn) {
+   pfn = 0;
+   ++nodes;
+   }
start = last + 1;
-   addr += max_size * AMDGPU_GPU_PAGE_SIZE;
-   }
+
+   } while (unlikely(start != mapping->it.last + 1));
 
return 0;
 }
@@ -1131,34 +1152,24 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
dma_addr_t *pages_addr = NULL;
uint32_t gtt_flags, flags;
struct ttm_mem_reg *mem;
+   struct drm_mm_node *nodes;
struct fence *exclusive;
-   uint64_t addr;
int r;
 
if (clear) {
mem = 

[PATCH 2/6] drm/amdgpu: use explicit limit for VRAM_CONTIGUOUS

[Christian König]

From: Christian König 

Split VRAM won't have a valid offset, so just set an explicit limit
when the flag is given to trigger reallocation if necessary.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 3bddc68..03c6bfc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -123,12 +123,17 @@ static void amdgpu_ttm_placement_init(struct 
amdgpu_device *adev,
 
if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
+   unsigned lpfn = 0;
+
+   /* This forces a reallocation if the flag wasn't set before */
+   if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
+   lpfn = adev->mc.real_vram_size >> PAGE_SHIFT;
 
if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS &&
!(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
adev->mc.visible_vram_size < adev->mc.real_vram_size) {
places[c].fpfn = visible_pfn;
-   places[c].lpfn = 0;
+   places[c].lpfn = lpfn;
places[c].flags = TTM_PL_FLAG_WC |
TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_VRAM |
TTM_PL_FLAG_TOPDOWN;
@@ -136,7 +141,7 @@ static void amdgpu_ttm_placement_init(struct amdgpu_device 
*adev,
}
 
places[c].fpfn = 0;
-   places[c].lpfn = 0;
+   places[c].lpfn = lpfn;
places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
TTM_PL_FLAG_VRAM;
if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
-- 
2.5.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[ANNOUNCE] xf86-video-ati 7.7.1

[Michel Dänzer]

I'm pleased to announce the 7.7.1 release of xf86-video-ati, the Xorg
driver for ATI/AMD Radeon GPUs supported by the radeon kernel driver.
This release supports xserver versions 1.9-1.18.

This is a stable point release containing only fixes for
crash/hang/corruption bugs and other minor changes.

Thanks to Qiang Yu for his contributions to this release!


Michel Dänzer (15):
  Handle Zaphod mode correctly in radeon_mode_hotplug
  Explicitly set the fbcon pixmap pitch again
  Only use RandR APIs if RandR is enabled
  Don't enable micro-tiling for scanout buffers on pre-R600
  Wait for pending flips to complete before turning off an output or CRTC
  Also call drmmode_clear_pending_flip from radeon_scanout_flip_abort
  Don't override crtc parameter value in drmmode_flip_handler/abort
  Also handle disabled CRTCs in drmmode_clear_pending_flip
  glamor: Fix radeon_glamor_share_pixmap_backing for priv->bo == NULL
  Consolidate get_drawable_pixmap helper
  Move DRI2's local fixup_glamor helper to radeon_glamor_set_pixmap_bo
  glamor: Reallocate linear pixmap BO if necessary for DRI2 PRIME
  Destroy all dedicated scanout buffers during CloseScreen
  DRI2: Add interpolated_vblanks in radeon_dri2_get_crtc_msc
  Bump version for 7.7.1 release

Qiang Yu (3):
  Remove RR_Capability_SinkOutput for GPU without CRTC
  Fix radeon_mode_hotplug crash on multi GPU platform.
  DRI2: Fix radeon_dri2_exchange_buffers width/height copy'n'paste error

git tag: xf86-video-ati-7.7.1

http://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-7.7.1.tar.bz2
MD5:  e46f30e24d9d6acdb256d8a63e0ec07c  xf86-video-ati-7.7.1.tar.bz2
SHA1: 146be259bd725a0252e2909e1320e42e0a11d582  xf86-video-ati-7.7.1.tar.bz2
SHA256: 00a58588db62ee309095c5c5920bbd248d965e8627f88affe68a73b18865078d  
xf86-video-ati-7.7.1.tar.bz2
PGP:  
http://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-7.7.1.tar.bz2.sig

http://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-7.7.1.tar.gz
MD5:  c01f4204fc2bd1890010d7c50a4a01e3  xf86-video-ati-7.7.1.tar.gz
SHA1: 1369b2c48af1cf06673be0e87285b5ab61b7a282  xf86-video-ati-7.7.1.tar.gz
SHA256: 890906208cfa41d3ab720e0cfa2ec3ff390fc40e3cdd4f21873db4c5c94abd85  
xf86-video-ati-7.7.1.tar.gz
PGP:  
http://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-7.7.1.tar.gz.sig


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer



signature.asc
Description: OpenPGP digital signature
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[ANNOUNCE] xf86-video-amdgpu 1.1.1

[Michel Dänzer]

I'm pleased to announce the 1.1.1 release of xf86-video-amdgpu, the Xorg
driver for AMD Radeon GPUs supported by the amdgpu kernel driver.
This release supports xserver versions 1.9-1.18.

This is a stable point release containing only fixes and other minor changes.

Highlights:

* Support for all currently available GPUs supported by the amdgpu
  kernel driver.
* A few fixes for crash/hang bugs.

Thanks to everybody who contributed to this release in any way!


Alex Deucher (1):
  add missing bonaire pci id

Flora Cui (3):
  add strato pci id
  Add more Polaris 10 PCI IDs
  Add more Polaris 11 PCI IDs

Marek Olšák (1):
  Fix cursor size for SI

Michel Dänzer (14):
  Handle Zaphod mode correctly in amdgpu_mode_hotplug
  glamor: Fix amdgpu_glamor_share_pixmap_backing for priv->bo == NULL
  Remove amdgpu_share_pixmap_backing
  Add amdgpu_pixmap_get_tiling_info
  Consolidate get_drawable_pixmap helper
  Move DRI2's local fixup_glamor helper to amdgpu_glamor_set_pixmap_bo v2
  glamor: Reallocate linear pixmap BO if necessary for DRI2 PRIME
  Destroy all dedicated scanout buffers during CloseScreen
  Only use RandR APIs if RandR is enabled
  DRI2: Add interpolated_vblanks in amdgpu_dri2_get_crtc_msc
  Add Mullins PCI IDs
  Add missing Kaveri PCI ID (1318)
  Use --with-xorg-conf-dir=$prefix/share/X11/xorg.conf.d by default
  Bump version for the 1.1.1 release

Qiang Yu (3):
  Remove RR_Capability_SinkOutput for GPU without CRTC.
  Fix amdgpu_mode_hotplug crash on multi GPU platform.
  DRI2: Fix amdgpu_dri2_exchange_buffers width/height copy'n'paste error

Ronie Salgado (1):
  Add SI PCI IDs

git tag: xf86-video-amdgpu-1.1.1

http://xorg.freedesktop.org/archive/individual/driver/xf86-video-amdgpu-1.1.1.tar.bz2
MD5:  8b2e2852299b330da709d0526b2b8134  xf86-video-amdgpu-1.1.1.tar.bz2
SHA1: 402df5fa62631e7e049261bc29cdc0eb5febe119  xf86-video-amdgpu-1.1.1.tar.bz2
SHA256: b6dfe5fb2a9bba5048135c75a507827bc887ac0790214d62b28c47f22fdd238f  
xf86-video-amdgpu-1.1.1.tar.bz2
PGP:  
http://xorg.freedesktop.org/archive/individual/driver/xf86-video-amdgpu-1.1.1.tar.bz2.sig

http://xorg.freedesktop.org/archive/individual/driver/xf86-video-amdgpu-1.1.1.tar.gz
MD5:  23e39d8586fb89da3e606ebbc2f8e911  xf86-video-amdgpu-1.1.1.tar.gz
SHA1: 1acf7e7ead43e69b9122e9bb25b95a734cf3ace3  xf86-video-amdgpu-1.1.1.tar.gz
SHA256: 40dec655b7f9385d08fd648c359eff63012bfacc16397590ad2f9682e1e4527c  
xf86-video-amdgpu-1.1.1.tar.gz
PGP:  
http://xorg.freedesktop.org/archive/individual/driver/xf86-video-amdgpu-1.1.1.tar.gz.sig


-- 
Earthling Michel Dänzer   |   http://www.amd.com
Libre software enthusiast | Mesa and X developer



signature.asc
Description: OpenPGP digital signature
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 3/5] drm/amdgpu:fix RB cost calculator

[Christian König]

256dw for the header are probably not enough.

Since we now uses NOPs for the CE/DE sync we only need 256dw for that 
alone. I suggest to raise that to 512.


Christian.

Am 15.09.2016 um 00:24 schrieb Andy Furniss:
This has just gone into drm-next-4.9-wip and caused lots of logging 
noise.


Seems to work OK though.

Sep 14 23:18:38 ph4 kernel: [drm:gfx_v8_0_ring_emit_fence_gfx 
[amdgpu]] *ERROR* amdgpu: writing more dwords to the ring than expected!

Sep 14 23:18:38 ph4 last message repeated 11 times
Sep 14 23:18:38 ph4 kernel: [drm:gfx_v8_ring_emit_sb [amdgpu]] *ERROR* 
amdgpu: writing more dwords to the ring than expected!
Sep 14 23:18:38 ph4 kernel: [drm:gfx_v8_ring_emit_sb [amdgpu]] *ERROR* 
amdgpu: writing more dwords to the ring than expected!
Sep 14 23:18:38 ph4 kernel: [drm:amdgpu_ring_insert_nop [amdgpu]] 
*ERROR* amdgpu: writing more dwords to the ring than expected!

Sep 14 23:18:38 ph4 last message repeated 10 times
Sep 14 23:18:38 ph4 kernel: [drm:gfx_v8_0_ring_emit_ib_gfx [amdgpu]] 
*ERROR* amdgpu: writing more dwords to the ring than expected!
Sep 14 23:18:38 ph4 kernel: [drm:gfx_v8_0_ring_emit_ib_gfx [amdgpu]] 
*ERROR* amdgpu: writing more dwords to the ring than expected!
Sep 14 23:18:38 ph4 kernel: [drm:gfx_v8_0_ring_emit_hdp_invalidate 
[amdgpu]] *ERROR* amdgpu: writing more dwords to the ring than expected!

Sep 14 23:18:38 ph4 last message repeated 4 times
Sep 14 23:18:38 ph4 kernel: [drm:gfx_v8_0_ring_emit_fence_gfx 
[amdgpu]] *ERROR* amdgpu: writing more dwords to the ring than expected!

Sep 14 23:18:38 ph4 last message repeated 11 times
Sep 14 23:18:38 ph4 kernel: [drm:gfx_v8_ring_emit_sb [amdgpu]] *ERROR* 
amdgpu: writing more dwords to the ring than expected!
Sep 14 23:18:38 ph4 kernel: [drm:gfx_v8_ring_emit_sb [amdgpu]] *ERROR* 
amdgpu: writing more dwords to the ring than expected!
Sep 14 23:18:38 ph4 kernel: [drm:amdgpu_ring_insert_nop [amdgpu]] 
*ERROR* amdgpu: writing more dwords to the ring than expected!

Sep 14 23:18:38 ph4 last message repeated 10 times

Monk Liu wrote:

Change-Id: Ie3e4587ed49c487c562f45a99f236a76727ace1e
Signed-off-by: Monk Liu 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

index 029ee79..6ad45fa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -151,7 +151,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, 
unsigned num_ibs,

  return -EINVAL;
  }

-r = amdgpu_ring_alloc(ring, 256 * num_ibs);
+r = amdgpu_ring_alloc(ring, 256 + (num_ibs << 4));
  if (r) {
  dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
  return r;



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx