Re: [PATCH] drm/amdgpu: check scratch registers to see if we need post (v2)

[Zhang, Jerry (Junwei)]

Thanks for update.
That's fine for me.

Feel free to add my RB.
Reviewed-by: Junwei Zhang 


On 07/04/2017 04:20 AM, Alex Deucher wrote:

Rather than checking the CONGIG_MEMSIZE register as that may
not be reliable on some APUs.

v2: The scratch register is only used on CIK+

Reviewed-by: Christian König 
Signed-off-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 ++-
  1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 63f4bed..8042a8a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -722,7 +722,12 @@ bool amdgpu_need_post(struct amdgpu_device *adev)
adev->has_hw_reset = false;
return true;
}
-   /* then check MEM_SIZE, in case the crtcs are off */
+
+   /* bios scratch used on CIK+ */
+   if (adev->asic_type >= CHIP_BONAIRE)
+   return amdgpu_atombios_scratch_need_asic_init(adev);
+
+   /* check MEM_SIZE for older asics */
reg = amdgpu_asic_get_config_memsize(adev);

if ((reg != 0) && (reg != 0x))


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 6/6] drm/amd/powerplay: added didt support for vega10

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Evan Quan
> Sent: Thursday, July 06, 2017 9:59 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander; Quan, Evan
> Subject: [PATCH 6/6] drm/amd/powerplay: added didt support for vega10
> 
> Change-Id: If2f955469e5b037e0726999b10eb10c08740b208
> Signed-off-by: Evan Quan 

Series is:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c |   56 +
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.h |5 +
>  .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.c | 1291
> 
>  .../gpu/drm/amd/powerplay/hwmgr/vega10_powertune.h |   16 +
>  .../gpu/drm/amd/powerplay/inc/hardwaremanager.h|5 +
>  drivers/gpu/drm/amd/powerplay/inc/pp_debug.h   |6 +
>  drivers/gpu/drm/amd/powerplay/inc/pp_soc15.h   |2 +
>  7 files changed, 1381 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 780efaf..ae11d30 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -145,6 +145,19 @@ static void vega10_set_default_registry_data(struct
> pp_hwmgr *hwmgr)
>   data->registry_data.vr1hot_enabled = 1;
>   data->registry_data.regulator_hot_gpio_support = 1;
> 
> + data->registry_data.didt_support = 1;
> + if (data->registry_data.didt_support) {
> + data->registry_data.didt_mode = 6;
> + data->registry_data.sq_ramping_support = 1;
> + data->registry_data.db_ramping_support = 0;
> + data->registry_data.td_ramping_support = 0;
> + data->registry_data.tcp_ramping_support = 0;
> + data->registry_data.dbr_ramping_support = 0;
> + data->registry_data.edc_didt_support = 1;
> + data->registry_data.gc_didt_support = 0;
> + data->registry_data.psm_didt_support = 0;
> + }
> +
>   data->display_voltage_mode =
> PPVEGA10_VEGA10DISPLAYVOLTAGEMODE_DFLT;
>   data->dcef_clk_quad_eqn_a =
> PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
>   data->dcef_clk_quad_eqn_b =
> PPREGKEY_VEGA10QUADRATICEQUATION_DFLT;
> @@ -222,6 +235,8 @@ static int vega10_set_features_platform_caps(struct
> pp_hwmgr *hwmgr)
>   phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>   PHM_PlatformCaps_PowerContainment);
>   phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
> + PHM_PlatformCaps_DiDtSupport);
> + phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>   PHM_PlatformCaps_SQRamping);
>   phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>   PHM_PlatformCaps_DBRamping);
> @@ -229,6 +244,34 @@ static int vega10_set_features_platform_caps(struct
> pp_hwmgr *hwmgr)
>   PHM_PlatformCaps_TDRamping);
>   phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
>   PHM_PlatformCaps_TCPRamping);
> + phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
> + PHM_PlatformCaps_DBRRamping);
> + phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
> + PHM_PlatformCaps_DiDtEDCEnable);
> + phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
> + PHM_PlatformCaps_GCEDC);
> + phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
> + PHM_PlatformCaps_PSM);
> +
> + if (data->registry_data.didt_support) {
> + phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> PHM_PlatformCaps_DiDtSupport);
> + if (data->registry_data.sq_ramping_support)
> + phm_cap_set(hwmgr-
> >platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
> + if (data->registry_data.db_ramping_support)
> + phm_cap_set(hwmgr-
> >platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
> + if (data->registry_data.td_ramping_support)
> + phm_cap_set(hwmgr-
> >platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
> + if (data->registry_data.tcp_ramping_support)
> + phm_cap_set(hwmgr-
> >platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
> + if (data->registry_data.dbr_ramping_support)
> + phm_cap_set(hwmgr-
> >platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
> + if (data->registry_data.edc_didt_support)
> + phm_cap_set(hwmgr-
> >platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
> + if (data->registry_data.gc_didt_support)
> + phm_cap_set(hwmgr-
> >platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
> + if 

[PATCH] drm/radeon: Fix eDP for single-display iMac10,1 (v2)

[Mario Kleiner]

The late 2009, 27 inch Apple iMac10,1 has an
internal eDP display and an external Mini-
Displayport output, driven by a DCE-3.2, RV730
Radeon Mobility HD-4670.

The machine worked fine in a dual-display setup
with eDP panel + externally connected HDMI
or DVI-D digital display sink, connected via
MiniDP to DVI or HDMI adapter.

However, booting the machine single-display with
only eDP panel results in a completely black
display - even backlight powering off, as soon as
the radeon modesetting driver loads.

This patch fixes the single dispay eDP case by
assigning encoders based on dig->linkb, similar
to DCE-4+. While this should not be generally
necessary (Alex: "...atom on normal boards
should be able to handle any mapping."), Apple
seems to use some special routing here.

One remaining problem not solved by this patch
is that an external Minidisplayport->DP sink
does still not work on iMac10,1, whereas external
DVI and HDMI sinks continue to work.

The problem affects at least all tested kernels
since Linux 3.13 - didn't test earlier kernels, so
backporting to stable probably makes sense.

v2: With the original patch from 2016, Alex was worried it
will break other DCE3.2 systems. Use dmi_match() to
apply this special encoder assignment only for the
Apple iMac 10,1 from late 2009.

Signed-off-by: Mario Kleiner 
Cc: Alex Deucher 
Cc: Michel Dänzer 
Cc: 
---
 drivers/gpu/drm/radeon/atombios_encoders.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c 
b/drivers/gpu/drm/radeon/atombios_encoders.c
index fa4f8f0..e67ed38 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -31,6 +31,7 @@
 #include "radeon_asic.h"
 #include "atom.h"
 #include 
+#include 
 
 extern int atom_debug;
 
@@ -2184,9 +2185,17 @@ int radeon_atom_pick_dig_encoder(struct drm_encoder 
*encoder, int fe_idx)
goto assigned;
}
 
-   /* on DCE32 and encoder can driver any block so just crtc id */
+   /*
+* On DCE32 any encoder can drive any block so usually just use crtc id,
+* but Apple thinks different at least on iMac10,1, so there use linkb,
+* otherwise the internal eDP panel will stay dark.
+*/
if (ASIC_IS_DCE32(rdev)) {
-   enc_idx = radeon_crtc->crtc_id;
+   if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1"))
+   enc_idx = (dig->linkb) ? 1 : 0;
+   else
+   enc_idx = radeon_crtc->crtc_id;
+
goto assigned;
}
 
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/6] drm/amd/powerplay: added support for new se_cac_idx APIs to cgs

[Evan Quan]

Change-Id: If2ac93808d1922fe3dbec64a58f674a9c342088d
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 4 
 drivers/gpu/drm/amd/include/cgs_common.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 02b469b..8016f90 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -240,6 +240,8 @@ static uint32_t amdgpu_cgs_read_ind_register(struct 
cgs_device *cgs_device,
return RREG32_DIDT(index);
case CGS_IND_REG_GC_CAC:
return RREG32_GC_CAC(index);
+   case CGS_IND_REG_SE_CAC:
+   return RREG32_SE_CAC(index);
case CGS_IND_REG__AUDIO_ENDPT:
DRM_ERROR("audio endpt register access not implemented.\n");
return 0;
@@ -266,6 +268,8 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device 
*cgs_device,
return WREG32_DIDT(index, value);
case CGS_IND_REG_GC_CAC:
return WREG32_GC_CAC(index, value);
+   case CGS_IND_REG_SE_CAC:
+   return WREG32_SE_CAC(index, value);
case CGS_IND_REG__AUDIO_ENDPT:
DRM_ERROR("audio endpt register access not implemented.\n");
return;
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h 
b/drivers/gpu/drm/amd/include/cgs_common.h
index 0a94f74..b46d12d 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -50,6 +50,7 @@ enum cgs_ind_reg {
CGS_IND_REG__UVD_CTX,
CGS_IND_REG__DIDT,
CGS_IND_REG_GC_CAC,
+   CGS_IND_REG_SE_CAC,
CGS_IND_REG__AUDIO_ENDPT
 };
 
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/6] drm/amd/powerplay: added index gc cac read/write apis for vega10

[Evan Quan]

Change-Id: I1a62db8c764d368e6ba08440ad1761adb55d85fd
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 24 
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index f5669af..c0a5250 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -196,6 +196,28 @@ static void soc15_didt_wreg(struct amdgpu_device *adev, 
u32 reg, u32 v)
spin_unlock_irqrestore(>didt_idx_lock, flags);
 }
 
+static u32 soc15_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
+{
+   unsigned long flags;
+   u32 r;
+
+   spin_lock_irqsave(>gc_cac_idx_lock, flags);
+   WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
+   r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA);
+   spin_unlock_irqrestore(>gc_cac_idx_lock, flags);
+   return r;
+}
+
+static void soc15_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+{
+   unsigned long flags;
+
+   spin_lock_irqsave(>gc_cac_idx_lock, flags);
+   WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg));
+   WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v));
+   spin_unlock_irqrestore(>gc_cac_idx_lock, flags);
+}
+
 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 {
if (adev->flags & AMD_IS_APU)
@@ -567,6 +589,8 @@ static int soc15_common_early_init(void *handle)
adev->uvd_ctx_wreg = _uvd_ctx_wreg;
adev->didt_rreg = _didt_rreg;
adev->didt_wreg = _didt_wreg;
+   adev->gc_cac_rreg = _gc_cac_rreg;
+   adev->gc_cac_wreg = _gc_cac_wreg;
 
adev->asic_funcs = _asic_funcs;
 
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 5/6] drm/amd/powerplay: added grbm_idx_mutex lock/unlock to cgs v2 - v2: rename param 'en' as 'lock'

[Evan Quan]

Change-Id: If7088d6046c84355b8f1308d584ab6524ceab724
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c  | 12 
 drivers/gpu/drm/amd/include/cgs_common.h |  5 +
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 8016f90..3d41cd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -614,6 +614,17 @@ static int amdgpu_cgs_enter_safe_mode(struct cgs_device 
*cgs_device,
return 0;
 }
 
+static void amdgpu_cgs_lock_grbm_idx(struct cgs_device *cgs_device,
+   bool lock)
+{
+   CGS_FUNC_ADEV;
+
+   if (lock)
+   mutex_lock(>grbm_idx_mutex);
+   else
+   mutex_unlock(>grbm_idx_mutex);
+}
+
 static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
enum cgs_ucode_id type,
struct cgs_firmware_info *info)
@@ -1136,6 +1147,7 @@ static const struct cgs_ops amdgpu_cgs_ops = {
.query_system_info = amdgpu_cgs_query_system_info,
.is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
.enter_safe_mode = amdgpu_cgs_enter_safe_mode,
+   .lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
 };
 
 static const struct cgs_os_ops amdgpu_cgs_os_ops = {
diff --git a/drivers/gpu/drm/amd/include/cgs_common.h 
b/drivers/gpu/drm/amd/include/cgs_common.h
index b46d12d..0214f63 100644
--- a/drivers/gpu/drm/amd/include/cgs_common.h
+++ b/drivers/gpu/drm/amd/include/cgs_common.h
@@ -407,6 +407,8 @@ typedef int (*cgs_is_virtualization_enabled_t)(void 
*cgs_device);
 
 typedef int (*cgs_enter_safe_mode)(struct cgs_device *cgs_device, bool en);
 
+typedef void (*cgs_lock_grbm_idx)(struct cgs_device *cgs_device, bool lock);
+
 struct cgs_ops {
/* memory management calls (similar to KFD interface) */
cgs_alloc_gpu_mem_t alloc_gpu_mem;
@@ -442,6 +444,7 @@ struct cgs_ops {
cgs_query_system_info query_system_info;
cgs_is_virtualization_enabled_t is_virtualization_enabled;
cgs_enter_safe_mode enter_safe_mode;
+   cgs_lock_grbm_idx lock_grbm_idx;
 };
 
 struct cgs_os_ops; /* To be define in OS-specific CGS header */
@@ -518,4 +521,6 @@ struct cgs_device
 #define cgs_enter_safe_mode(cgs_device, en) \
CGS_CALL(enter_safe_mode, cgs_device, en)
 
+#define cgs_lock_grbm_idx(cgs_device, lock) \
+   CGS_CALL(lock_grbm_idx, cgs_device, lock)
 #endif /* _CGS_COMMON_H */
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/6] drm/amd/powerplay: added new se_cac_idx r/w APIs v2 - v2: added missing spinlock init

[Evan Quan]

Change-Id: I9f16ec9f5bab9abe83e9df01609893b38bb691fe
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 6 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index fdf6599..6a5021f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1562,6 +1562,10 @@ struct amdgpu_device {
spinlock_t gc_cac_idx_lock;
amdgpu_rreg_t   gc_cac_rreg;
amdgpu_wreg_t   gc_cac_wreg;
+   /* protects concurrent se_cac register access */
+   spinlock_t se_cac_idx_lock;
+   amdgpu_rreg_t   se_cac_rreg;
+   amdgpu_wreg_t   se_cac_wreg;
/* protects concurrent ENDPOINT (audio) register access */
spinlock_t audio_endpt_idx_lock;
amdgpu_block_rreg_t audio_endpt_rreg;
@@ -1756,6 +1760,8 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device 
*adev);
 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
+#define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
+#define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), 
(reg))
 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, 
(block), (reg), (v))
 #define WREG32_P(reg, val, mask)   \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7233800..1392f44 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2119,6 +2119,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
spin_lock_init(>uvd_ctx_idx_lock);
spin_lock_init(>didt_idx_lock);
spin_lock_init(>gc_cac_idx_lock);
+   spin_lock_init(>se_cac_idx_lock);
spin_lock_init(>audio_endpt_idx_lock);
spin_lock_init(>mm_stats.lock);
 
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 3/6] drm/amd/powerplay: added soc15 support for new se_cac_idx APIs

[Evan Quan]

Change-Id: I9b925397d7ac61bcf9f0e8850f2d8b3dabd4a105
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 24 
 1 file changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index c0a5250..9cf7fb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -218,6 +218,28 @@ static void soc15_gc_cac_wreg(struct amdgpu_device *adev, 
u32 reg, u32 v)
spin_unlock_irqrestore(>gc_cac_idx_lock, flags);
 }
 
+static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg)
+{
+   unsigned long flags;
+   u32 r;
+
+   spin_lock_irqsave(>se_cac_idx_lock, flags);
+   WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
+   r = RREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA);
+   spin_unlock_irqrestore(>se_cac_idx_lock, flags);
+   return r;
+}
+
+static void soc15_se_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+{
+   unsigned long flags;
+
+   spin_lock_irqsave(>se_cac_idx_lock, flags);
+   WREG32_SOC15(GC, 0, mmSE_CAC_IND_INDEX, (reg));
+   WREG32_SOC15(GC, 0, mmSE_CAC_IND_DATA, (v));
+   spin_unlock_irqrestore(>se_cac_idx_lock, flags);
+}
+
 static u32 soc15_get_config_memsize(struct amdgpu_device *adev)
 {
if (adev->flags & AMD_IS_APU)
@@ -591,6 +613,8 @@ static int soc15_common_early_init(void *handle)
adev->didt_wreg = _didt_wreg;
adev->gc_cac_rreg = _gc_cac_rreg;
adev->gc_cac_wreg = _gc_cac_wreg;
+   adev->se_cac_rreg = _se_cac_rreg;
+   adev->se_cac_wreg = _se_cac_wreg;
 
adev->asic_funcs = _asic_funcs;
 
-- 
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 06/12] drm/amdgpu: Correctly establish the suspend/resume hook for amdkfd

[Yong Zhao]

Hi Alex,

As far as I know, we never tested suspend/resume on the setting you 
mentioned. Theoretically it should work.


When I read the code now, I was wondering whether we should stop kfd 
before amdgpu_bo_evict_vram() and amdgpu_fence_driver_suspend(). If 
that's not needed, it may make more sense to stick to the previous 
design which kept the kfd suspend/resume inside your IP block 
suspend/resume.


Regards,

Yong


On 2017-07-06 05:06 PM, Alex Deucher wrote:

On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling  wrote:

From: Yong Zhao 

Signed-off-by: Yong Zhao 
Reviewed-by: Felix Kuehling 

Does this work properly for multiple GPUs?  E.g., if one is suspended
and another is not?  E.g., PX laptops where we runtime suspend the
dGPU while the APU is still running.

Alex


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
  drivers/gpu/drm/amd/amdgpu/cik.c   | 9 +
  2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5b1220f..bc69b9c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -56,6 +56,8 @@
  #include 
  #include "amdgpu_vf_error.h"

+#include "amdgpu_amdkfd.h"
+
  MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
  MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");

@@ -2397,6 +2399,8 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
suspend, bool fbcon)
 drm_modeset_unlock_all(dev);
 }

+   amdgpu_amdkfd_suspend(adev);
+
 /* unpin the front buffers and cursors */
 list_for_each_entry(crtc, >mode_config.crtc_list, head) {
 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
@@ -2537,6 +2541,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool 
resume, bool fbcon)
 }
 }
 }
+   r = amdgpu_amdkfd_resume(adev);
+   if (r)
+   return r;

 /* blat the mode back in */
 if (fbcon) {
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 6ce9f80..00639bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1825,21 +1825,14 @@ static int cik_common_suspend(void *handle)
  {
 struct amdgpu_device *adev = (struct amdgpu_device *)handle;

-   amdgpu_amdkfd_suspend(adev);
-
 return cik_common_hw_fini(adev);
  }

  static int cik_common_resume(void *handle)
  {
-   int r;
 struct amdgpu_device *adev = (struct amdgpu_device *)handle;

-   r = cik_common_hw_init(adev);
-   if (r)
-   return r;
-
-   return amdgpu_amdkfd_resume(adev);
+   return cik_common_hw_init(adev);
  }

  static bool cik_common_is_idle(void *handle)
--
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 0/5] amdgpu: Visible VRAM Management Improvements, next take

[John Brooks]

On Thu, Jul 06, 2017 at 07:51:25PM +0900, Michel Dänzer wrote:
> From: Michel Dänzer 
> 
> This is a rearrangement of some patches of John's, with some improvements
> of mine, and a patch of mine, rebased on current amd-staging-4.11.
> Details about changes in the individual patches.
> 
> John Brooks (4):
>   drm/amdgpu: Add vis_vramlimit module parameter
>   drm/amdgpu: Throttle visible VRAM moves separately
>   drm/amdgpu: Set/clear CPU_ACCESS flag on page fault and move to VRAM
>   drm/amdgpu: Don't force BOs into visible VRAM for page faults
> 
> Michel Dänzer (1):
>   drm/amdgpu: Try evicting from CPU visible to invisible VRAM first
> 
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  7 ++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 92 
> --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|  4 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 49 +---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 45 +++
>  5 files changed, 157 insertions(+), 40 deletions(-)
> 
> -- 
> 2.13.2
> 

Thanks :)

I'll test it today or tomorrow and report back.

--
John Brooks
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 06/12] drm/amdgpu: Correctly establish the suspend/resume hook for amdkfd

[Yong Zhao]

On 2017-07-06 05:44 PM, Alex Deucher wrote:

On Thu, Jul 6, 2017 at 5:33 PM, Yong Zhao  wrote:

Hi Alex,

As far as I know, we never tested suspend/resume on the setting you
mentioned. Theoretically it should work.

Are the kfd s/r entry points global or per GPU?  If you have two GPUs
and you suspend one, will it suspend the entire kfd?  I'm fine with
the change, it's no worse than the current situation.  Mostly just
curious.
kfd s/r is per GPU. If we suspend only one out of two GPUs, the other 
one will keep working.



When I read the code now, I was wondering whether we should stop kfd before
amdgpu_bo_evict_vram() and amdgpu_fence_driver_suspend(). If that's not
needed, it may make more sense to stick to the previous design which kept
the kfd suspend/resume inside your IP block suspend/resume.

I think it makes more sense to put the kfd calls in the common device
s/r code rather than in the soc specific ip functions.  Change is:
Reviewed-by: Alex Deucher 



Regards,

Yong



On 2017-07-06 05:06 PM, Alex Deucher wrote:

On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling 
wrote:

From: Yong Zhao 

Signed-off-by: Yong Zhao 
Reviewed-by: Felix Kuehling 

Does this work properly for multiple GPUs?  E.g., if one is suspended
and another is not?  E.g., PX laptops where we runtime suspend the
dGPU while the APU is still running.

Alex


---
   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
   drivers/gpu/drm/amd/amdgpu/cik.c   | 9 +
   2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 5b1220f..bc69b9c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -56,6 +56,8 @@
   #include 
   #include "amdgpu_vf_error.h"

+#include "amdgpu_amdkfd.h"
+
   MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
   MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");

@@ -2397,6 +2399,8 @@ int amdgpu_device_suspend(struct drm_device *dev,
bool suspend, bool fbcon)
  drm_modeset_unlock_all(dev);
  }

+   amdgpu_amdkfd_suspend(adev);
+
  /* unpin the front buffers and cursors */
  list_for_each_entry(crtc, >mode_config.crtc_list, head) {
  struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
@@ -2537,6 +2541,9 @@ int amdgpu_device_resume(struct drm_device *dev,
bool resume, bool fbcon)
  }
  }
  }
+   r = amdgpu_amdkfd_resume(adev);
+   if (r)
+   return r;

  /* blat the mode back in */
  if (fbcon) {
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c
b/drivers/gpu/drm/amd/amdgpu/cik.c
index 6ce9f80..00639bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1825,21 +1825,14 @@ static int cik_common_suspend(void *handle)
   {
  struct amdgpu_device *adev = (struct amdgpu_device *)handle;

-   amdgpu_amdkfd_suspend(adev);
-
  return cik_common_hw_fini(adev);
   }

   static int cik_common_resume(void *handle)
   {
-   int r;
  struct amdgpu_device *adev = (struct amdgpu_device *)handle;

-   r = cik_common_hw_init(adev);
-   if (r)
-   return r;
-
-   return amdgpu_amdkfd_resume(adev);
+   return cik_common_hw_init(adev);
   }

   static bool cik_common_is_idle(void *handle)
--
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx




___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH libdrm] libdrm_amdgpu: add kernel semaphore support

[Dave Airlie]

Chrstian,

you are probably the best person to ack this, I'd like to get the radv
code landed
and allow the GL code to get going.

Dave.

> This adds kernel semaphore support to the command submission
> interface in what should be a backwards compatible manner,
> it adds a new command submission API.
>
> Signed-off-by: Dave Airlie 
> ---
>  amdgpu/amdgpu.h|  29 -
>  amdgpu/amdgpu_cs.c | 118 
> +
>  2 files changed, 138 insertions(+), 9 deletions(-)
>
> diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
> index 1901fa8..649b66e 100644
> --- a/amdgpu/amdgpu.h
> +++ b/amdgpu/amdgpu.h
> @@ -369,6 +369,16 @@ struct amdgpu_cs_request {
> struct amdgpu_cs_fence_info fence_info;
>  };
>
> +struct amdgpu_cs_request_syncobj {
> +   /*
> +*
> +*/
> +   uint32_t number_in_syncobj;
> +   uint32_t number_out_syncobj;
> +   uint32_t *in_syncobj;
> +   uint32_t *out_syncobj;
> +};
> +
>  /**
>   * Structure which provide information about GPU VM MC Address space
>   * alignments requirements
> @@ -886,6 +896,12 @@ int amdgpu_cs_submit(amdgpu_context_handle context,
>  struct amdgpu_cs_request *ibs_request,
>  uint32_t number_of_requests);
>
> +int amdgpu_cs_submit_syncobj(amdgpu_context_handle context,
> +uint64_t flags,
> +struct amdgpu_cs_request *ibs_request,
> +struct amdgpu_cs_request_syncobj *ibs_syncobj,
> +uint32_t number_of_requests);
> +
>  /**
>   *  Query status of Command Buffer Submission
>   *
> @@ -1328,8 +1344,19 @@ int 
> amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem);
>  */
>  const char *amdgpu_get_marketing_name(amdgpu_device_handle dev);
>
> +
> +int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
> +uint32_t *syncobj);
> +int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
> +uint32_t syncobj,
> +int *shared_fd);
> +int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
> +int shared_fd,
> +uint32_t *syncobj);
> +int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
> + uint32_t syncobj);
> +
>  #ifdef __cplusplus
>  }
>  #endif
> -
>  #endif /* #ifdef _AMDGPU_H_ */
> diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
> index 868eb7b..339c5f9 100644
> --- a/amdgpu/amdgpu_cs.c
> +++ b/amdgpu/amdgpu_cs.c
> @@ -168,7 +168,8 @@ int amdgpu_cs_query_reset_state(amdgpu_context_handle 
> context,
>   * \sa amdgpu_cs_submit()
>  */
>  static int amdgpu_cs_submit_one(amdgpu_context_handle context,
> -   struct amdgpu_cs_request *ibs_request)
> +   struct amdgpu_cs_request *ibs_request,
> +   struct amdgpu_cs_request_syncobj 
> *syncobj_request)
>  {
> union drm_amdgpu_cs cs;
> uint64_t *chunk_array;
> @@ -176,10 +177,13 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle 
> context,
> struct drm_amdgpu_cs_chunk_data *chunk_data;
> struct drm_amdgpu_cs_chunk_dep *dependencies = NULL;
> struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
> +   struct drm_amdgpu_cs_chunk_sem *in_syncobj_dependencies = NULL;
> +   struct drm_amdgpu_cs_chunk_sem *out_syncobj_dependencies = NULL;
> struct list_head *sem_list;
> amdgpu_semaphore_handle sem, tmp;
> -   uint32_t i, size, sem_count = 0;
> +   uint32_t i, j, size, sem_count = 0;
> bool user_fence;
> +   uint32_t sem_size = 0;
> int r = 0;
>
> if (ibs_request->ip_type >= AMDGPU_HW_IP_NUM)
> @@ -194,7 +198,11 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle 
> context,
> }
> user_fence = (ibs_request->fence_info.handle != NULL);
>
> -   size = ibs_request->number_of_ibs + (user_fence ? 2 : 1) + 1;
> +   if (syncobj_request) {
> +   sem_size += syncobj_request->number_in_syncobj ? 1 : 0;
> +   sem_size += syncobj_request->number_out_syncobj ? 1 : 0;
> +   }
> +   size = ibs_request->number_of_ibs + (user_fence ? 2 : 1) + 1 + 
> sem_size;
>
> chunk_array = alloca(sizeof(uint64_t) * size);
> chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
> @@ -306,6 +314,45 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle 
> context,
> chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies;
> }
>
> +   if (syncobj_request) {
> +   if (syncobj_request->number_in_syncobj) {
> +   in_syncobj_dependencies = malloc(sizeof(struct 
> drm_amdgpu_cs_chunk_sem) * syncobj_request->number_in_syncobj);
> +   if (!in_syncobj_dependencies) {
> + 

Re: [PATCH 09/12] drm/amdgpu: disallow foreign BOs in the display path

[Felix Kuehling]

On 17-07-06 05:13 PM, Alex Deucher wrote:
> On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling  wrote:
>> From: Christian König 
>>
>> Pinning them in other devices VRAM would obviously not work.
>>
>> Signed-off-by: Christian König 
>> Reviewed-by: Felix Kuehling 
> Do we need to check in the DC (amdgpu_dm_types.c) and the dce
> (dce_v*_0.c) code as well?

Probably. I have it as a TODO on my separate P2P patch series.

Regards,
  Felix

>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 ++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> index 3341c34..bd6b0dc 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>> @@ -180,6 +180,12 @@ int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
>> obj = new_amdgpu_fb->obj;
>> new_abo = gem_to_amdgpu_bo(obj);
>>
>> +   if (amdgpu_ttm_adev(new_abo->tbo.bdev) != adev) {
>> +   DRM_ERROR("Foreign BOs not allowed in the display engine\n");
>> +   r = -EINVAL;
>> +   goto cleanup;
>> +   }
>> +
>> /* pin the new buffer */
>> r = amdgpu_bo_reserve(new_abo, false);
>> if (unlikely(r != 0)) {
>> --
>> 1.9.1
>>
>> ___
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 06/12] drm/amdgpu: Correctly establish the suspend/resume hook for amdkfd

[Alex Deucher]

On Thu, Jul 6, 2017 at 5:33 PM, Yong Zhao  wrote:
> Hi Alex,
>
> As far as I know, we never tested suspend/resume on the setting you
> mentioned. Theoretically it should work.

Are the kfd s/r entry points global or per GPU?  If you have two GPUs
and you suspend one, will it suspend the entire kfd?  I'm fine with
the change, it's no worse than the current situation.  Mostly just
curious.

>
> When I read the code now, I was wondering whether we should stop kfd before
> amdgpu_bo_evict_vram() and amdgpu_fence_driver_suspend(). If that's not
> needed, it may make more sense to stick to the previous design which kept
> the kfd suspend/resume inside your IP block suspend/resume.

I think it makes more sense to put the kfd calls in the common device
s/r code rather than in the soc specific ip functions.  Change is:
Reviewed-by: Alex Deucher 


>
> Regards,
>
> Yong
>
>
>
> On 2017-07-06 05:06 PM, Alex Deucher wrote:
>>
>> On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling 
>> wrote:
>>>
>>> From: Yong Zhao 
>>>
>>> Signed-off-by: Yong Zhao 
>>> Reviewed-by: Felix Kuehling 
>>
>> Does this work properly for multiple GPUs?  E.g., if one is suspended
>> and another is not?  E.g., PX laptops where we runtime suspend the
>> dGPU while the APU is still running.
>>
>> Alex
>>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
>>>   drivers/gpu/drm/amd/amdgpu/cik.c   | 9 +
>>>   2 files changed, 8 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> index 5b1220f..bc69b9c 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> @@ -56,6 +56,8 @@
>>>   #include 
>>>   #include "amdgpu_vf_error.h"
>>>
>>> +#include "amdgpu_amdkfd.h"
>>> +
>>>   MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
>>>   MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
>>>
>>> @@ -2397,6 +2399,8 @@ int amdgpu_device_suspend(struct drm_device *dev,
>>> bool suspend, bool fbcon)
>>>  drm_modeset_unlock_all(dev);
>>>  }
>>>
>>> +   amdgpu_amdkfd_suspend(adev);
>>> +
>>>  /* unpin the front buffers and cursors */
>>>  list_for_each_entry(crtc, >mode_config.crtc_list, head) {
>>>  struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
>>> @@ -2537,6 +2541,9 @@ int amdgpu_device_resume(struct drm_device *dev,
>>> bool resume, bool fbcon)
>>>  }
>>>  }
>>>  }
>>> +   r = amdgpu_amdkfd_resume(adev);
>>> +   if (r)
>>> +   return r;
>>>
>>>  /* blat the mode back in */
>>>  if (fbcon) {
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c
>>> b/drivers/gpu/drm/amd/amdgpu/cik.c
>>> index 6ce9f80..00639bf 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
>>> @@ -1825,21 +1825,14 @@ static int cik_common_suspend(void *handle)
>>>   {
>>>  struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>
>>> -   amdgpu_amdkfd_suspend(adev);
>>> -
>>>  return cik_common_hw_fini(adev);
>>>   }
>>>
>>>   static int cik_common_resume(void *handle)
>>>   {
>>> -   int r;
>>>  struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>>
>>> -   r = cik_common_hw_init(adev);
>>> -   if (r)
>>> -   return r;
>>> -
>>> -   return amdgpu_amdkfd_resume(adev);
>>> +   return cik_common_hw_init(adev);
>>>   }
>>>
>>>   static bool cik_common_is_idle(void *handle)
>>> --
>>> 1.9.1
>>>
>>> ___
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
>
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 09/12] drm/amdgpu: disallow foreign BOs in the display path

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling  wrote:
> From: Christian König 
>
> Pinning them in other devices VRAM would obviously not work.
>
> Signed-off-by: Christian König 
> Reviewed-by: Felix Kuehling 

Do we need to check in the DC (amdgpu_dm_types.c) and the dce
(dce_v*_0.c) code as well?

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 3341c34..bd6b0dc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -180,6 +180,12 @@ int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
> obj = new_amdgpu_fb->obj;
> new_abo = gem_to_amdgpu_bo(obj);
>
> +   if (amdgpu_ttm_adev(new_abo->tbo.bdev) != adev) {
> +   DRM_ERROR("Foreign BOs not allowed in the display engine\n");
> +   r = -EINVAL;
> +   goto cleanup;
> +   }
> +
> /* pin the new buffer */
> r = amdgpu_bo_reserve(new_abo, false);
> if (unlikely(r != 0)) {
> --
> 1.9.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 06/12] drm/amdgpu: Correctly establish the suspend/resume hook for amdkfd

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling  wrote:
> From: Yong Zhao 
>
> Signed-off-by: Yong Zhao 
> Reviewed-by: Felix Kuehling 

Does this work properly for multiple GPUs?  E.g., if one is suspended
and another is not?  E.g., PX laptops where we runtime suspend the
dGPU while the APU is still running.

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7 +++
>  drivers/gpu/drm/amd/amdgpu/cik.c   | 9 +
>  2 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 5b1220f..bc69b9c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -56,6 +56,8 @@
>  #include 
>  #include "amdgpu_vf_error.h"
>
> +#include "amdgpu_amdkfd.h"
> +
>  MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
>  MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
>
> @@ -2397,6 +2399,8 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
> suspend, bool fbcon)
> drm_modeset_unlock_all(dev);
> }
>
> +   amdgpu_amdkfd_suspend(adev);
> +
> /* unpin the front buffers and cursors */
> list_for_each_entry(crtc, >mode_config.crtc_list, head) {
> struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
> @@ -2537,6 +2541,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool 
> resume, bool fbcon)
> }
> }
> }
> +   r = amdgpu_amdkfd_resume(adev);
> +   if (r)
> +   return r;
>
> /* blat the mode back in */
> if (fbcon) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c 
> b/drivers/gpu/drm/amd/amdgpu/cik.c
> index 6ce9f80..00639bf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik.c
> @@ -1825,21 +1825,14 @@ static int cik_common_suspend(void *handle)
>  {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> -   amdgpu_amdkfd_suspend(adev);
> -
> return cik_common_hw_fini(adev);
>  }
>
>  static int cik_common_resume(void *handle)
>  {
> -   int r;
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> -   r = cik_common_hw_init(adev);
> -   if (r)
> -   return r;
> -
> -   return amdgpu_amdkfd_resume(adev);
> +   return cik_common_hw_init(adev);
>  }
>
>  static bool cik_common_is_idle(void *handle)
> --
> 1.9.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 04/12] drm/amdgpu: Make SDMA phase quantum configurable

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling  wrote:
> Set a configurable SDMA phase quantum when enabling SDMA context
> switching. The default value significantly reduces SDMA latency
> in page table updates when user-mode SDMA queues have concurrent
> activity, compared to the initial HW setting.
>
> Signed-off-by: Felix Kuehling 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  4 
>  drivers/gpu/drm/amd/amdgpu/cik_sdma.c   | 32 ++-
>  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c  | 32 ++-
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  | 34 
> -
>  5 files changed, 100 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 810796a..2129fbb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -106,6 +106,7 @@
>  extern unsigned amdgpu_pcie_lane_cap;
>  extern unsigned amdgpu_cg_mask;
>  extern unsigned amdgpu_pg_mask;
> +extern unsigned amdgpu_sdma_phase_quantum;
>  extern char *amdgpu_disable_cu;
>  extern char *amdgpu_virtual_display;
>  extern unsigned amdgpu_pp_feature_mask;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 4bf4a80..02cf24e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -107,6 +107,7 @@
>  unsigned amdgpu_pcie_lane_cap = 0;
>  unsigned amdgpu_cg_mask = 0x;
>  unsigned amdgpu_pg_mask = 0x;
> +unsigned amdgpu_sdma_phase_quantum = 32;
>  char *amdgpu_disable_cu = NULL;
>  char *amdgpu_virtual_display = NULL;
>  unsigned amdgpu_pp_feature_mask = 0x;
> @@ -223,6 +224,9 @@
>  MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power 
> gating)");
>  module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
>
> +MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 
> 1K GPU clock cycles, 0 = no change (default 32))");
> +module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 
> 0444);
> +
>  MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
>  module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c 
> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index 4a9cea0..f508f4d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -351,14 +351,44 @@ static void cik_sdma_rlc_stop(struct amdgpu_device 
> *adev)
>   */
>  static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
>  {
> -   u32 f32_cntl;
> +   u32 f32_cntl, phase_quantum = 0;
> int i;
>
> +   if (amdgpu_sdma_phase_quantum) {
> +   unsigned value = amdgpu_sdma_phase_quantum;
> +   unsigned unit = 0;
> +
> +   while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
> +   SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
> +   value = (value + 1) >> 1;
> +   unit++;
> +   }
> +   if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
> +   SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
> +   value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
> +SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
> +   unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
> +   SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
> +   WARN_ONCE(1,
> +   "clamping sdma_phase_quantum to %uK clock cycles\n",
> + value << unit);
> +   }
> +   phase_quantum =
> +   value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
> +   unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
> +   }
> +
> for (i = 0; i < adev->sdma.num_instances; i++) {
> f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
> if (enable) {
> f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
> AUTO_CTXSW_ENABLE, 1);
> +   if (amdgpu_sdma_phase_quantum) {
> +   WREG32(mmSDMA0_PHASE0_QUANTUM + 
> sdma_offsets[i],
> +  phase_quantum);
> +   WREG32(mmSDMA0_PHASE1_QUANTUM + 
> sdma_offsets[i],
> +  phase_quantum);
> +   }
> } else {
> f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
> AUTO_CTXSW_ENABLE, 0);
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 
> 

Re: [PATCH 03/12] drm/amdgpu: Enable SDMA context switching for CIK

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling  wrote:
> Enable SDMA context switching on CIK (copied from sdma_v3_0.c).
>
> Signed-off-by: Felix Kuehling 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 30 ++
>  1 file changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c 
> b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index c216e16..4a9cea0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -342,6 +342,33 @@ static void cik_sdma_rlc_stop(struct amdgpu_device *adev)
>  }
>
>  /**
> + * cik_ctx_switch_enable - stop the async dma engines context switch
> + *
> + * @adev: amdgpu_device pointer
> + * @enable: enable/disable the DMA MEs context switch.
> + *
> + * Halt or unhalt the async dma engines context switch (VI).
> + */
> +static void cik_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
> +{
> +   u32 f32_cntl;
> +   int i;
> +
> +   for (i = 0; i < adev->sdma.num_instances; i++) {
> +   f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
> +   if (enable) {
> +   f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
> +   AUTO_CTXSW_ENABLE, 1);
> +   } else {
> +   f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
> +   AUTO_CTXSW_ENABLE, 0);
> +   }
> +
> +   WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
> +   }
> +}
> +
> +/**
>   * cik_sdma_enable - stop the async dma engines
>   *
>   * @adev: amdgpu_device pointer
> @@ -537,6 +564,8 @@ static int cik_sdma_start(struct amdgpu_device *adev)
>
> /* halt the engine before programing */
> cik_sdma_enable(adev, false);
> +   /* enable sdma ring preemption */
> +   cik_ctx_switch_enable(adev, true);
>
> /* start the gfx rings and rlc compute queues */
> r = cik_sdma_gfx_resume(adev);
> @@ -984,6 +1013,7 @@ static int cik_sdma_hw_fini(void *handle)
>  {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> +   cik_ctx_switch_enable(adev, false);
> cik_sdma_enable(adev, false);
>
> return 0;
> --
> 1.9.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 02/12] drm/amdgpu: Enable SDMA_CNTL.ATC_L1_ENABLE for SDMA on CZ

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:11 PM, Felix Kuehling  wrote:
> From: shaoyunl 
>
> For GFX context, the  ATC bit in SDMA*_GFX_VIRTUAL_ADDRESS  can be cleared
> to perform in VM mode. For RLC context, to support ATC mode , ATC bit in
> SDMA*_RLC*_VIRTUAL_ADDRESS should be set. SDMA_CNTL.ATC_L1_ENABLE bit is
> global setting that enables the  L1-L2 translation for ATC address.
>
> Signed-off-by: shaoyun liu 
> Reviewed-by: Felix Kuehling 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 
> b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 1d766ae..67a29fb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -556,12 +556,18 @@ static void sdma_v3_0_ctx_switch_enable(struct 
> amdgpu_device *adev, bool enable)
>
> for (i = 0; i < adev->sdma.num_instances; i++) {
> f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
> -   if (enable)
> +   if (enable) {
> f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
> AUTO_CTXSW_ENABLE, 1);
> -   else
> +   f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
> +   ATC_L1_ENABLE, 1);
> +   } else {
> f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
> AUTO_CTXSW_ENABLE, 0);
> +   f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
> +   ATC_L1_ENABLE, 1);
> +   }
> +
> WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
> }
>  }
> --
> 1.9.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 00/12] Patches from amd-kfd-staging

[Felix Kuehling]

I split the P2P patches into a separate series for review. Patches 1-6
from this series should still be valid.

I still need Reviewed-by's for patches 1 and 4.

Patches 2 and 5 are by other authors and reviewed by me. But I'd feel
better to get at least an Acked-by from some amdgpu folks.

Thanks,
  Felix


On 17-07-03 05:11 PM, Felix Kuehling wrote:
> Varios cleaned-up and some squashed patches from amd-kfg-staging
> that are not necessarily KFD-on-dGPU-specific. The intention is to
> minimize differences between amd-kfd-staging and upstream before
> reviewing KFD-specific changes for upstreaming.
>
> Patches 7-12 are a rebased (multiple times) patch series by
> Christian for allowing foreign BO imports for peer-to-peer buffer
> access.
>
> Amber Lin (1):
>   drm/amdgpu: handle foreign BOs in the VM mapping
>
> Christian König (5):
>   drm: export drm_gem_prime_dmabuf_ops
>   drm/amdgpu: disallow foreign BOs for UVD/VCE
>   drm/amdgpu: disallow foreign BOs in the display path
>   drm/amdgpu: separate BO from GEM object
>   drm/amdgpu: enable foreign DMA-buf objects
>
> Felix Kuehling (3):
>   drm/amdgpu: implement vm_operations_struct.access
>   drm/amdgpu: Enable SDMA context switching for CIK
>   drm/amdgpu: Make SDMA phase quantum configurable
>
> Jay Cornwall (1):
>   drm/amdgpu: Send no-retry XNACK for all fault types
>
> Yong Zhao (1):
>   drm/amdgpu: Correctly establish the suspend/resume hook for amdkfd
>
> shaoyunl (1):
>   drm/amdgpu: Enable SDMA_CNTL.ATC_L1_ENABLE for SDMA on CZ
>
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h |  15 ++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |   3 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c  |   7 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c |   6 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |   6 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c |  41 ++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c  |   7 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c   |  79 ++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 147 
> +++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h |   2 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  |  17 +++-
>  drivers/gpu/drm/amd/amdgpu/cik.c|   9 +-
>  drivers/gpu/drm/amd/amdgpu/cik_sdma.c   |  60 
>  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c|   3 +
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c |   3 +
>  drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c  |  42 +++-
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c  |  34 ++-
>  drivers/gpu/drm/drm_prime.c |   3 +-
>  include/drm/drmP.h  |   2 +
>  19 files changed, 446 insertions(+), 40 deletions(-)
>

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/6] drm/amdgpu: disallow foreign BOs for UVD/VCE

[Felix Kuehling]

From: Christian König 

They don't support VM mode yet.

Signed-off-by: Christian König 
Reviewed-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 82131d7..24035e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -1343,7 +1343,8 @@ struct amdgpu_bo_va_mapping *
struct amdgpu_bo_list_entry *lobj;
 
lobj = >bo_list->array[i];
-   if (!lobj->bo_va)
+   if (!lobj->bo_va ||
+   amdgpu_ttm_adev(lobj->bo_va->bo->tbo.bdev) != parser->adev)
continue;
 
list_for_each_entry(mapping, >bo_va->valids, list) {
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 5/6] drm/amdgpu: handle foreign BOs in the VM mapping

[Felix Kuehling]

From: Amber Lin 

Set the system bit for foreign BO mappings and use the remote VRAM
BAR address as the VRAM base offset.

Signed-off-by: Amber Lin 
Reviewed-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 +
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 1d1810d..5f08e81 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1582,6 +1582,7 @@ static int amdgpu_vm_bo_split_mapping(struct 
amdgpu_device *adev,
  dma_addr_t *pages_addr,
  struct amdgpu_vm *vm,
  struct amdgpu_bo_va_mapping *mapping,
+ uint64_t vram_base_offset,
  uint64_t flags,
  struct drm_mm_node *nodes,
  struct dma_fence **fence)
@@ -1640,7 +1641,7 @@ static int amdgpu_vm_bo_split_mapping(struct 
amdgpu_device *adev,
max_entries = min(max_entries, 16ull * 1024ull);
addr = 0;
} else if (flags & AMDGPU_PTE_VALID) {
-   addr += adev->vm_manager.vram_base_offset;
+   addr += vram_base_offset;
}
addr += pfn << PAGE_SHIFT;
 
@@ -1685,6 +1686,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
struct ttm_mem_reg *mem;
struct drm_mm_node *nodes;
struct dma_fence *exclusive;
+   uint64_t vram_base_offset = adev->vm_manager.vram_base_offset;
+   struct amdgpu_device *bo_adev;
int r;
 
if (clear || !bo_va->bo) {
@@ -1706,9 +1709,15 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
 
if (bo_va->bo) {
flags = amdgpu_ttm_tt_pte_flags(adev, bo_va->bo->tbo.ttm, mem);
+   bo_adev = amdgpu_ttm_adev(bo_va->bo->tbo.bdev);
gtt_flags = (amdgpu_ttm_is_bound(bo_va->bo->tbo.ttm) &&
-   adev == amdgpu_ttm_adev(bo_va->bo->tbo.bdev)) ?
+   adev == bo_adev) ?
flags : 0;
+   if (mem && mem->mem_type == TTM_PL_VRAM &&
+   adev != bo_adev) {
+   flags |= AMDGPU_PTE_SYSTEM;
+   vram_base_offset = bo_adev->mc.aper_base;
+   }
} else {
flags = 0x0;
gtt_flags = ~0x0;
@@ -1722,8 +1731,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
list_for_each_entry(mapping, _va->invalids, list) {
r = amdgpu_vm_bo_split_mapping(adev, exclusive,
   gtt_flags, pages_addr, vm,
-  mapping, flags, nodes,
-  _va->last_pt_update);
+  mapping, vram_base_offset, flags,
+  nodes, _va->last_pt_update);
if (r)
return r;
}
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/6] drm/amdgpu: separate BO from GEM object

[Felix Kuehling]

From: Christian König 

This allows us to have multiple GEM objects for one BO.

Signed-off-by: Christian König 
Reviewed-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h| 12 +++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c| 41 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c |  7 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c  | 20 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 17 +++--
 5 files changed, 77 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 2129fbb..f3d99cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -414,6 +414,12 @@ struct amdgpu_bo_va {
 
 #define AMDGPU_GEM_DOMAIN_MAX  0x3
 
+struct amdgpu_gem_object {
+   struct drm_gem_object   base;
+   struct list_headlist;
+   struct amdgpu_bo*bo;
+};
+
 struct amdgpu_bo {
/* Protected by tbo.reserved */
u32 prefered_domains;
@@ -430,12 +436,14 @@ struct amdgpu_bo {
void*metadata;
u32 metadata_size;
unsignedprime_shared_count;
+   /* GEM objects refereing to this BO */
+   struct list_headgem_objects;
+
/* list of all virtual address to which this bo
 * is associated to
 */
struct list_headva;
/* Constant after initialization */
-   struct drm_gem_object   gem_base;
struct amdgpu_bo*parent;
struct amdgpu_bo*shadow;
 
@@ -444,7 +452,7 @@ struct amdgpu_bo {
struct list_headmn_list;
struct list_headshadow_list;
 };
-#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
+#define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_gem_object, 
base)->bo
 
 void amdgpu_gem_object_free(struct drm_gem_object *obj);
 int amdgpu_gem_object_open(struct drm_gem_object *obj,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 96c4493..f7e9bdf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -33,14 +33,20 @@
 
 void amdgpu_gem_object_free(struct drm_gem_object *gobj)
 {
-   struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj);
+   struct amdgpu_gem_object *aobj;
 
-   if (robj) {
-   if (robj->gem_base.import_attach)
-   drm_prime_gem_destroy(>gem_base, robj->tbo.sg);
-   amdgpu_mn_unregister(robj);
-   amdgpu_bo_unref();
-   }
+   aobj = container_of((gobj), struct amdgpu_gem_object, base);
+   if (aobj->base.import_attach)
+   drm_prime_gem_destroy(>base, aobj->bo->tbo.sg);
+
+   ww_mutex_lock(>bo->tbo.resv->lock, NULL);
+   list_del(>list);
+   ww_mutex_unlock(>bo->tbo.resv->lock);
+
+   amdgpu_mn_unregister(aobj->bo);
+   amdgpu_bo_unref(>bo);
+   drm_gem_object_release(>base);
+   kfree(aobj);
 }
 
 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
@@ -49,6 +55,7 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, 
unsigned long size,
struct drm_gem_object **obj)
 {
struct amdgpu_bo *robj;
+   struct amdgpu_gem_object *gobj;
unsigned long max_size;
int r;
 
@@ -83,7 +90,23 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, 
unsigned long size,
}
return r;
}
-   *obj = >gem_base;
+
+   gobj = kzalloc(sizeof(struct amdgpu_gem_object), GFP_KERNEL);
+   if (unlikely(!gobj)) {
+   amdgpu_bo_unref();
+   return -ENOMEM;
+   }
+
+   r = drm_gem_object_init(adev->ddev, >base, amdgpu_bo_size(robj));
+   if (unlikely(r)) {
+   kfree(gobj);
+   amdgpu_bo_unref();
+   return r;
+   }
+
+   list_add(>list, >gem_objects);
+   gobj->bo = robj;
+   *obj = >base;
 
return 0;
 }
@@ -703,7 +726,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
struct drm_amdgpu_gem_create_in info;
void __user *out = (void __user *)(uintptr_t)args->value;
 
-   info.bo_size = robj->gem_base.size;
+   info.bo_size = amdgpu_bo_size(robj);
info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT;
info.domains = robj->prefered_domains;
info.domain_flags = robj->flags;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index c34cf2c..44b7e71 100644
--- 

[PATCH 3/6] drm/amdgpu: disallow foreign BOs in the display path

[Felix Kuehling]

From: Christian König 

Pinning them in other devices VRAM would obviously not work.

Signed-off-by: Christian König 
Reviewed-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 3341c34..bd6b0dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -180,6 +180,12 @@ int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
obj = new_amdgpu_fb->obj;
new_abo = gem_to_amdgpu_bo(obj);
 
+   if (amdgpu_ttm_adev(new_abo->tbo.bdev) != adev) {
+   DRM_ERROR("Foreign BOs not allowed in the display engine\n");
+   r = -EINVAL;
+   goto cleanup;
+   }
+
/* pin the new buffer */
r = amdgpu_bo_reserve(new_abo, false);
if (unlikely(r != 0)) {
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/6] drm: Add helper to check exporting driver of a DMA-buf

[Christian König]

Am 06.07.2017 um 22:16 schrieb Felix Kuehling:

This allows drivers to check if a DMA-buf contains a GEM object and
whether it comes from the same driver. It may be from the same or a
different device.

Signed-off-by: Felix Kuehling 


I think Daniel/Dave hadmore a function which returns the casted GEM 
object or NULL in mind, but that should o it as well.


Patch is Reviewed-by: Christian König 

Regards,
Christian.


---
  drivers/gpu/drm/drm_prime.c | 24 
  include/drm/drmP.h  |  2 ++
  2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index 25aa455..a50baec 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -594,6 +594,30 @@ int drm_gem_prime_handle_to_fd(struct drm_device *dev,
  EXPORT_SYMBOL(drm_gem_prime_handle_to_fd);
  
  /**

+ * drm_gem_prime_dmabuf_is_from_driver - check exporting driver of a dma-buf
+ * @dma_buf: dma-buf object to check
+ * @driver: driver that is the expected exporter of the dma-buf
+ *
+ * Returns true if @driver exported @dma_buf. Returns false if
+ * @dma_buf was exported by a different driver.
+ */
+bool drm_gem_prime_dmabuf_is_from_driver(const struct dma_buf *dma_buf,
+const struct drm_driver *driver)
+{
+   struct drm_gem_object *obj;
+
+   if (dma_buf->ops != _gem_prime_dmabuf_ops)
+   return false;
+
+   obj = dma_buf->priv;
+   if (obj->dev->driver != driver)
+   return false;
+
+   return true;
+}
+EXPORT_SYMBOL(drm_gem_prime_dmabuf_is_from_driver);
+
+/**
   * drm_gem_prime_import - helper library implementation of the import callback
   * @dev: drm_device to import into
   * @dma_buf: dma-buf object to import
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 6105c05..052f747 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -767,6 +767,8 @@ extern struct dma_buf *drm_gem_prime_export(struct 
drm_device *dev,
  extern int drm_gem_prime_handle_to_fd(struct drm_device *dev,
struct drm_file *file_priv, uint32_t handle, uint32_t flags,
int *prime_fd);
+extern bool drm_gem_prime_dmabuf_is_from_driver(const struct dma_buf *dma_buf,
+   const struct drm_driver *driver);
  extern struct drm_gem_object *drm_gem_prime_import(struct drm_device *dev,
struct dma_buf *dma_buf);
  extern int drm_gem_prime_fd_to_handle(struct drm_device *dev,



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 6/6] drm/amdgpu: enable foreign DMA-buf objects v2

[Felix Kuehling]

From: Christian König 

We should be able to handle BOs from other instances as well.

v2:
* Add a module option that is off-by-default
* Use new DRM helper function to check the exporting driver

Signed-off-by: Christian König 
Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  4 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  6 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c | 60 +++
 3 files changed, 69 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f3d99cb..a8b0e21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -126,6 +126,8 @@
 extern int amdgpu_cik_support;
 #endif
 
+extern int amdgpu_p2p_sharing;
+
 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
 #define AMDGPU_MAX_USEC_TIMEOUT10  /* 100 ms */
@@ -468,6 +470,8 @@ struct drm_gem_object *
 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
struct drm_gem_object *gobj,
int flags);
+struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
+  struct dma_buf *dma_buf);
 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 02cf24e..3ff51a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -118,6 +118,7 @@
 int amdgpu_param_buf_per_se = 0;
 int amdgpu_job_hang_limit = 0;
 int amdgpu_lbpw = -1;
+int amdgpu_p2p_sharing = 0;
 
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -267,6 +268,9 @@
 module_param_named(cik_support, amdgpu_cik_support, int, 0444);
 #endif
 
+MODULE_PARM_DESC(p2p_sharing, "Enable P2P buffer sharing (1 = enabled, 0 = 
disabled (default))");
+module_param_named(p2p_sharing, amdgpu_p2p_sharing, int, 0444);
+
 
 static const struct pci_device_id pciidlist[] = {
 #ifdef  CONFIG_DRM_AMDGPU_SI
@@ -813,7 +817,7 @@ long amdgpu_drm_ioctl(struct file *filp,
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
.gem_prime_export = amdgpu_gem_prime_export,
-   .gem_prime_import = drm_gem_prime_import,
+   .gem_prime_import = amdgpu_gem_prime_import,
.gem_prime_pin = amdgpu_gem_prime_pin,
.gem_prime_unpin = amdgpu_gem_prime_unpin,
.gem_prime_res_obj = amdgpu_gem_prime_res_obj,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
index b9425ed..2079d51 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
@@ -159,3 +159,63 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device 
*dev,
 
return drm_gem_prime_export(dev, gobj, flags);
 }
+
+static struct drm_gem_object *
+amdgpu_gem_prime_foreign_bo(struct amdgpu_device *adev, struct amdgpu_bo *bo)
+{
+   struct amdgpu_gem_object *gobj;
+   int r;
+
+   ww_mutex_lock(>tbo.resv->lock, NULL);
+
+   list_for_each_entry(gobj, >gem_objects, list) {
+   if (gobj->base.dev != adev->ddev)
+   continue;
+
+   ww_mutex_unlock(>tbo.resv->lock);
+   drm_gem_object_reference(>base);
+   return >base;
+   }
+
+
+   gobj = kzalloc(sizeof(struct amdgpu_gem_object), GFP_KERNEL);
+   if (unlikely(!gobj)) {
+   ww_mutex_unlock(>tbo.resv->lock);
+   return ERR_PTR(-ENOMEM);
+   }
+
+   r = drm_gem_object_init(adev->ddev, >base, amdgpu_bo_size(bo));
+   if (unlikely(r)) {
+   kfree(gobj);
+   ww_mutex_unlock(>tbo.resv->lock);
+   return ERR_PTR(r);
+   }
+
+   list_add(>list, >gem_objects);
+   gobj->bo = amdgpu_bo_ref(bo);
+   bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+
+   ww_mutex_unlock(>tbo.resv->lock);
+
+   return >base;
+}
+
+struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
+  struct dma_buf *dma_buf)
+{
+   struct amdgpu_device *adev = dev->dev_private;
+
+   if (amdgpu_p2p_sharing &&
+   drm_gem_prime_dmabuf_is_from_driver(dma_buf, dev->driver)) {
+   struct drm_gem_object *obj = dma_buf->priv;
+
+   if (obj->dev != dev) {
+   /* It's a amdgpu_bo from a different driver instance */
+ 

[PATCH 1/6] drm: Add helper to check exporting driver of a DMA-buf

[Felix Kuehling]

This allows drivers to check if a DMA-buf contains a GEM object and
whether it comes from the same driver. It may be from the same or a
different device.

Signed-off-by: Felix Kuehling 
---
 drivers/gpu/drm/drm_prime.c | 24 
 include/drm/drmP.h  |  2 ++
 2 files changed, 26 insertions(+)

diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index 25aa455..a50baec 100644
--- a/drivers/gpu/drm/drm_prime.c
+++ b/drivers/gpu/drm/drm_prime.c
@@ -594,6 +594,30 @@ int drm_gem_prime_handle_to_fd(struct drm_device *dev,
 EXPORT_SYMBOL(drm_gem_prime_handle_to_fd);
 
 /**
+ * drm_gem_prime_dmabuf_is_from_driver - check exporting driver of a dma-buf
+ * @dma_buf: dma-buf object to check
+ * @driver: driver that is the expected exporter of the dma-buf
+ *
+ * Returns true if @driver exported @dma_buf. Returns false if
+ * @dma_buf was exported by a different driver.
+ */
+bool drm_gem_prime_dmabuf_is_from_driver(const struct dma_buf *dma_buf,
+const struct drm_driver *driver)
+{
+   struct drm_gem_object *obj;
+
+   if (dma_buf->ops != _gem_prime_dmabuf_ops)
+   return false;
+
+   obj = dma_buf->priv;
+   if (obj->dev->driver != driver)
+   return false;
+
+   return true;
+}
+EXPORT_SYMBOL(drm_gem_prime_dmabuf_is_from_driver);
+
+/**
  * drm_gem_prime_import - helper library implementation of the import callback
  * @dev: drm_device to import into
  * @dma_buf: dma-buf object to import
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 6105c05..052f747 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -767,6 +767,8 @@ extern struct dma_buf *drm_gem_prime_export(struct 
drm_device *dev,
 extern int drm_gem_prime_handle_to_fd(struct drm_device *dev,
struct drm_file *file_priv, uint32_t handle, uint32_t flags,
int *prime_fd);
+extern bool drm_gem_prime_dmabuf_is_from_driver(const struct dma_buf *dma_buf,
+   const struct drm_driver *driver);
 extern struct drm_gem_object *drm_gem_prime_import(struct drm_device *dev,
struct dma_buf *dma_buf);
 extern int drm_gem_prime_fd_to_handle(struct drm_device *dev,
-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 0/6] Experimental P2P buffer sharing

[Felix Kuehling]

This patch series adds experimental P2P buffer sharing. It's disabled
by default and can be enabled with amdgpu.p2p_sharing=1.

TODO:
* Add a whitelist of chipsets that support P2P access
* Refine UVD/VCE handling on newer IP versions with GPUVM support
* Handle foreign BOs in DC path
* Test for regressions in existing multi-GPU buffer sharing use cases

Amber Lin (1):
  drm/amdgpu: handle foreign BOs in the VM mapping

Christian König (4):
  drm/amdgpu: disallow foreign BOs for UVD/VCE
  drm/amdgpu: disallow foreign BOs in the display path
  drm/amdgpu: separate BO from GEM object
  drm/amdgpu: enable foreign DMA-buf objects v2

Felix Kuehling (1):
  drm: Add helper to check exporting driver of a DMA-buf

 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 16 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  3 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_display.c |  6 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  6 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 41 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c  |  7 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c   | 80 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 17 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  | 17 --
 drivers/gpu/drm/drm_prime.c | 24 +
 include/drm/drmP.h  |  2 +
 11 files changed, 193 insertions(+), 26 deletions(-)

-- 
1.9.1

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 2/2] drm/amdgpu/soc15: init nbio registers for vega10

[Alex Deucher]

Call nbio init registers on hw_init to set up any
nbio registers that need initialization at hw init time.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index f5669af..10cc01e 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -691,6 +691,9 @@ static int soc15_common_hw_init(void *handle)
soc15_pcie_gen3_enable(adev);
/* enable aspm */
soc15_program_aspm(adev);
+   /* setup nbio registers */
+   if (!(adev->flags & AMD_IS_APU))
+   nbio_v6_1_init_registers(adev);
/* enable the doorbell aperture */
soc15_enable_doorbell_aperture(adev, true);
 
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 1/2] drm/amdgpu: add nbio 6.1 register init function

[Alex Deucher]

Used for nbio registers that need to be initialized.  Currently
only used for a golden setting that got missed on some boards.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 13 +
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h |  1 +
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
index 61c0028..045988b 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
@@ -32,6 +32,7 @@
 
 #define smnCPM_CONTROL 
 0x11180460
 #define smnPCIE_CNTL2  
 0x11180070
+#define smnPCIE_CONFIG_CNTL
 0x11180044
 
 u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
 {
@@ -256,3 +257,15 @@ void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev)
adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
}
 }
+
+void nbio_v6_1_init_registers(struct amdgpu_device *adev)
+{
+   uint32_t def, data;
+
+   def = data = RREG32_PCIE(smnPCIE_CONFIG_CNTL);
+   data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, 
CI_SWUS_MAX_READ_REQUEST_SIZE_MODE, 1);
+   data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL, 
CI_SWUS_MAX_READ_REQUEST_SIZE_PRIV, 1);
+
+   if (def != data)
+   WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h 
b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
index f6f8bc0..686e4b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h
@@ -50,5 +50,6 @@ void nbio_v6_1_update_medium_grain_clock_gating(struct 
amdgpu_device *adev, bool
 void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, 
bool enable);
 void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
 void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev);
+void nbio_v6_1_init_registers(struct amdgpu_device *adev);
 
 #endif
-- 
2.5.5

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 11/11] drm/amdgpu: add sysvm_size

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König  wrote:
> From: Christian König 
>
> Limit the size of the SYSVM. This saves us a bunch of visible VRAM,
> but also limitates the maximum BO size we can swap out.

Update the description.  The limitation is removed now.

>
> v2: rebased and cleaned up after GART to SYSVM rename.
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c  | 6 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 6 --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c   | 9 +
>  5 files changed, 16 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 1ed6b7a..81de31a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -77,6 +77,7 @@
>  extern int amdgpu_modeset;
>  extern int amdgpu_vram_limit;
>  extern int amdgpu_gart_size;
> +extern unsigned amdgpu_sysvm_size;
>  extern int amdgpu_moverate;
>  extern int amdgpu_benchmarking;
>  extern int amdgpu_testing;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 228b262..daded9c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -1086,6 +1086,12 @@ static void amdgpu_check_arguments(struct 
> amdgpu_device *adev)
> }
> }
>
> +   if (amdgpu_sysvm_size < 32) {
> +   dev_warn(adev->dev, "sysvm size (%d) too small\n",
> +amdgpu_sysvm_size);
> +   amdgpu_sysvm_size = 32;
> +   }
> +
> amdgpu_check_vm_size(adev);
>
> amdgpu_check_block_size(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 4bf4a80..56f9867 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -75,6 +75,7 @@
>
>  int amdgpu_vram_limit = 0;
>  int amdgpu_gart_size = -1; /* auto */
> +unsigned amdgpu_sysvm_size = 256;
>  int amdgpu_moverate = -1; /* auto */
>  int amdgpu_benchmarking = 0;
>  int amdgpu_testing = 0;
> @@ -124,6 +125,9 @@ module_param_named(vramlimit, amdgpu_vram_limit, int, 
> 0600);
>  MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 
> 64, etc., -1 = auto)");
>  module_param_named(gartsize, amdgpu_gart_size, int, 0600);
>
> +MODULE_PARM_DESC(sysvmsize, "Size of the system VM in megabytes (default 
> 256)");
> +module_param_named(sysvmsize, amdgpu_sysvm_size, int, 0600);
> +
>  MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, 
> etc., -1=auto, 0=1=disabled)");
>  module_param_named(moverate, amdgpu_moverate, int, 0600);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> index f46a97d..bbf6bd0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> @@ -42,6 +42,7 @@ struct amdgpu_gtt_mgr {
>  static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager *man,
>unsigned long p_size)
>  {
> +   struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
> struct amdgpu_gtt_mgr *mgr;
> uint64_t start, size;
>
> @@ -50,7 +51,7 @@ static int amdgpu_gtt_mgr_init(struct ttm_mem_type_manager 
> *man,
> return -ENOMEM;
>
> start = AMDGPU_GTT_MAX_TRANSFER_SIZE * 
> AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
> -   size = p_size - start;
> +   size = (adev->mc.sysvm_size >> PAGE_SHIFT) - start;
> drm_mm_init(>mm, start, size);
> spin_lock_init(>lock);
> mgr->available = p_size;
> @@ -112,6 +113,7 @@ int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
>  const struct ttm_place *place,
>  struct ttm_mem_reg *mem)
>  {
> +   struct amdgpu_device *adev = amdgpu_ttm_adev(man->bdev);
> struct amdgpu_gtt_mgr *mgr = man->priv;
> struct drm_mm_node *node = mem->mm_node;
> enum drm_mm_insert_mode mode;
> @@ -129,7 +131,7 @@ int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager *man,
> if (place && place->lpfn)
> lpfn = place->lpfn;
> else
> -   lpfn = man->size;
> +   lpfn = adev->sysvm.num_cpu_pages;
>
> mode = DRM_MM_INSERT_BEST;
> if (place && place->flags & TTM_PL_FLAG_TOPDOWN)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c
> index ff436ad..711e4b6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c
> @@ -62,14 

Re: [PATCH 09/11] drm/amdgpu: move amdgpu_sysvm_location into amdgpu_sysvm.c as well

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König  wrote:
> From: Christian König 
>
> No intended functional change.
>
> Signed-off-by: Christian König 

I think I'd prefer to keep this together with the vram_location
function.  Maybe move both of them?

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  1 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 36 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c  | 38 
> ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.h  |  2 ++
>  4 files changed, 40 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index a2c0eac..1ed6b7a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1862,7 +1862,6 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
>  uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt 
> *ttm,
>  struct ttm_mem_reg *mem);
>  void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, 
> u64 base);
> -void amdgpu_sysvm_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
>  void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
>  int amdgpu_ttm_init(struct amdgpu_device *adev);
>  void amdgpu_ttm_fini(struct amdgpu_device *adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 46a82d3..228b262 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -666,42 +666,6 @@ void amdgpu_vram_location(struct amdgpu_device *adev, 
> struct amdgpu_mc *mc, u64
> mc->vram_end, mc->real_vram_size >> 20);
>  }
>
> -/**
> - * amdgpu_sysvm_location - try to find SYSVM location
> - * @adev: amdgpu device structure holding all necessary informations
> - * @mc: memory controller structure holding memory informations
> - *
> - * Function will place try to place SYSVM before or after VRAM.
> - *
> - * If SYSVM size is bigger than space left then we ajust SYSVM size.
> - * Thus function will never fails.
> - *
> - * FIXME: when reducing SYSVM size align new size on power of 2.
> - */
> -void amdgpu_sysvm_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
> -{
> -   u64 size_af, size_bf;
> -
> -   size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->sysvm_base_align) 
> & ~mc->sysvm_base_align;
> -   size_bf = mc->vram_start & ~mc->sysvm_base_align;
> -   if (size_bf > size_af) {
> -   if (mc->sysvm_size > size_bf) {
> -   dev_warn(adev->dev, "limiting SYSVM\n");
> -   mc->sysvm_size = size_bf;
> -   }
> -   mc->sysvm_start = 0;
> -   } else {
> -   if (mc->sysvm_size > size_af) {
> -   dev_warn(adev->dev, "limiting SYSVM\n");
> -   mc->sysvm_size = size_af;
> -   }
> -   mc->sysvm_start = (mc->vram_end + 1 + mc->sysvm_base_align) & 
> ~mc->sysvm_base_align;
> -   }
> -   mc->sysvm_end = mc->sysvm_start + mc->sysvm_size - 1;
> -   dev_info(adev->dev, "SYSVM: %lluM 0x%016llX - 0x%016llX\n",
> -   mc->sysvm_size >> 20, mc->sysvm_start, mc->sysvm_end);
> -}
> -
>  /*
>   * GPU helpers function.
>   */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c
> index 50fc8d7..ff436ad 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.c
> @@ -73,6 +73,44 @@ void amdgpu_sysvm_set_defaults(struct amdgpu_device *adev)
>  }
>
>  /**
> + * amdgpu_sysvm_location - try to find SYSVM location
> + * @adev: amdgpu device structure holding all necessary informations
> + * @mc: memory controller structure holding memory informations
> + *
> + * Function will place try to place SYSVM before or after VRAM.
> + *
> + * If SYSVM size is bigger than space left then we ajust SYSVM size.
> + * Thus function will never fails.
> + *
> + * FIXME: when reducing SYSVM size align new size on power of 2.
> + */
> +void amdgpu_sysvm_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
> +{
> +   u64 size_af, size_bf;
> +
> +   size_af = ((adev->mc.mc_mask - mc->vram_end) + mc->sysvm_base_align) &
> +   ~mc->sysvm_base_align;
> +   size_bf = mc->vram_start & ~mc->sysvm_base_align;
> +   if (size_bf > size_af) {
> +   if (mc->sysvm_size > size_bf) {
> +   dev_warn(adev->dev, "limiting SYSVM\n");
> +   mc->sysvm_size = size_bf;
> +   }
> +   mc->sysvm_start = 0;
> +   } else {
> +   if (mc->sysvm_size > size_af) {
> +   dev_warn(adev->dev, "limiting SYSVM\n");

Re: [PATCH 10/11] drm/amdgpu: setup GTT size directly from module parameter

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König  wrote:
> From: Christian König 
>
> Instead of relying on the sysvm_size to be the same as the module parameter.
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 12 +---
>  1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 9240357..72dd83e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1097,6 +1097,7 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
>
>  int amdgpu_ttm_init(struct amdgpu_device *adev)
>  {
> +   uint64_t gtt_size;
> int r;
>
> r = amdgpu_ttm_global_init(adev);
> @@ -1143,14 +1144,19 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
> }
> DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
>  (unsigned) (adev->mc.real_vram_size / (1024 * 1024)));
> -   r = ttm_bo_init_mm(>mman.bdev, TTM_PL_TT,
> -   adev->mc.sysvm_size >> PAGE_SHIFT);
> +
> +   if (amdgpu_gart_size == -1)
> +   gtt_size = max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
> +  adev->mc.mc_vram_size);
> +   else
> +   gtt_size = (uint64_t)amdgpu_gart_size << 20;
> +   r = ttm_bo_init_mm(>mman.bdev, TTM_PL_TT, gtt_size >> 
> PAGE_SHIFT);
> if (r) {
> DRM_ERROR("Failed initializing GTT heap.\n");
> return r;
> }
> DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
> -(unsigned)(adev->mc.sysvm_size / (1024 * 1024)));
> +(unsigned)(gtt_size / (1024 * 1024)));
>
> adev->gds.mem.total_size = adev->gds.mem.total_size << 
> AMDGPU_GDS_SHIFT;
> adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size 
> << AMDGPU_GDS_SHIFT;
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 08/11] drm/amdgpu: move SYSVM struct and function into amdgpu_sysvm.h

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König  wrote:
> From: Christian König 
>
> No functional change.
>
> Signed-off-by: Christian König 

I agree with what the patch does, but I'd prefer gart to sysvm for the naming.
Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h   | 48 +--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.h | 77 
> +++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h   |  1 +
>  3 files changed, 79 insertions(+), 47 deletions(-)
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.h
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index abe191f..a2c0eac 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -69,6 +69,7 @@
>
>  #include "gpu_scheduler.h"
>  #include "amdgpu_virt.h"
> +#include "amdgpu_sysvm.h"
>
>  /*
>   * Modules parameters.
> @@ -534,53 +535,6 @@ int amdgpu_fence_slab_init(void);
>  void amdgpu_fence_slab_fini(void);
>
>  /*
> - * GART structures, functions & helpers
> - */
> -struct amdgpu_mc;
> -
> -#define AMDGPU_GPU_PAGE_SIZE 4096
> -#define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
> -#define AMDGPU_GPU_PAGE_SHIFT 12
> -#define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & 
> ~AMDGPU_GPU_PAGE_MASK)
> -
> -struct amdgpu_sysvm {
> -   dma_addr_t  table_addr;
> -   struct amdgpu_bo*robj;
> -   void*ptr;
> -   unsignednum_gpu_pages;
> -   unsignednum_cpu_pages;
> -   unsignedtable_size;
> -#ifdef CONFIG_DRM_AMDGPU_SYSVM_DEBUGFS
> -   struct page **pages;
> -#endif
> -   boolready;
> -
> -   /* Asic default pte flags */
> -   uint64_tsysvm_pte_flags;
> -
> -   const struct amdgpu_sysvm_funcs *sysvm_funcs;
> -};
> -
> -void amdgpu_sysvm_set_defaults(struct amdgpu_device *adev);
> -int amdgpu_sysvm_table_ram_alloc(struct amdgpu_device *adev);
> -void amdgpu_sysvm_table_ram_free(struct amdgpu_device *adev);
> -int amdgpu_sysvm_table_vram_alloc(struct amdgpu_device *adev);
> -void amdgpu_sysvm_table_vram_free(struct amdgpu_device *adev);
> -int amdgpu_sysvm_table_vram_pin(struct amdgpu_device *adev);
> -void amdgpu_sysvm_table_vram_unpin(struct amdgpu_device *adev);
> -int amdgpu_sysvm_init(struct amdgpu_device *adev);
> -void amdgpu_sysvm_fini(struct amdgpu_device *adev);
> -int amdgpu_sysvm_unbind(struct amdgpu_device *adev, uint64_t offset,
> -   int pages);
> -int amdgpu_sysvm_map(struct amdgpu_device *adev, uint64_t offset,
> -   int pages, dma_addr_t *dma_addr, uint64_t flags,
> -   void *dst);
> -int amdgpu_sysvm_bind(struct amdgpu_device *adev, uint64_t offset,
> -int pages, struct page **pagelist,
> -dma_addr_t *dma_addr, uint64_t flags);
> -int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
> -
> -/*
>   * VMHUB structures, functions & helpers
>   */
>  struct amdgpu_vmhub {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.h
> new file mode 100644
> index 000..7846765
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sysvm.h
> @@ -0,0 +1,77 @@
> +/*
> + * Copyright 2017 Advanced Micro Devices, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + */
> +
> +#ifndef __AMDGPU_SYSVM_H__
> +#define __AMDGPU_SYSVM_H__
> +
> +#include 
> +
> +/*
> + * SYSVM structures, functions & helpers
> + */
> +struct amdgpu_device;
> +struct amdgpu_bo;
> +struct amdgpu_sysvm_funcs;
> +
> +#define AMDGPU_GPU_PAGE_SIZE 

Re: [PATCH 06/11] drm/amdgpu: use TTM values instead of MC values for the info queries

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König  wrote:
> From: Christian König 
>
> Use the TTM values instead of the hardware config here.
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 10 ++
>  1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> index 00ef2fc..7a8da32 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> @@ -484,7 +484,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
> *data, struct drm_file
> vram_gtt.vram_size -= adev->vram_pin_size;
> vram_gtt.vram_cpu_accessible_size = 
> adev->mc.visible_vram_size;
> vram_gtt.vram_cpu_accessible_size -= (adev->vram_pin_size - 
> adev->invisible_pin_size);
> -   vram_gtt.gtt_size  = adev->mc.gtt_size;
> +   vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
> +   vram_gtt.gtt_size *= PAGE_SIZE;
> vram_gtt.gtt_size -= adev->gart_pin_size;
> return copy_to_user(out, _gtt,
> min((size_t)size, sizeof(vram_gtt))) ? 
> -EFAULT : 0;
> @@ -509,9 +510,10 @@ static int amdgpu_info_ioctl(struct drm_device *dev, 
> void *data, struct drm_file
> mem.cpu_accessible_vram.max_allocation =
> mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
>
> -   mem.gtt.total_heap_size = adev->mc.gtt_size;
> -   mem.gtt.usable_heap_size =
> -   adev->mc.gtt_size - adev->gart_pin_size;
> +   mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
> +   mem.gtt.total_heap_size *= PAGE_SIZE;
> +   mem.gtt.usable_heap_size = mem.gtt.total_heap_size
> +   - adev->gart_pin_size;
> mem.gtt.heap_usage = atomic64_read(>gtt_usage);
> mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
>
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 05/11] drm/amdgpu: remove maximum BO size limitation v2

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König  wrote:
> From: Christian König 
>
> We can finally remove this now.
>
> v2: remove now unused max_size variable as well.
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 12 
>  1 file changed, 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index 96c4493..917ac5e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -49,7 +49,6 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, 
> unsigned long size,
> struct drm_gem_object **obj)
>  {
> struct amdgpu_bo *robj;
> -   unsigned long max_size;
> int r;
>
> *obj = NULL;
> @@ -58,17 +57,6 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, 
> unsigned long size,
> alignment = PAGE_SIZE;
> }
>
> -   if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS 
> | AMDGPU_GEM_DOMAIN_OA))) {
> -   /* Maximum bo size is the unpinned gtt size since we use the 
> gtt to
> -* handle vram to system pool migrations.
> -*/
> -   max_size = adev->mc.gtt_size - adev->gart_pin_size;
> -   if (size > max_size) {
> -   DRM_DEBUG("Allocation size %ldMb bigger than %ldMb 
> limit\n",
> - size >> 20, max_size >> 20);
> -   return -ENOMEM;
> -   }
> -   }
>  retry:
> r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain,
>  flags, NULL, NULL, );
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 04/11] drm/amdgpu: stop mapping BOs to GTT

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König  wrote:
> From: Christian König 
>
> No need to map BOs to GTT on eviction and intermediate transfers any more.
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 19 ++-
>  1 file changed, 2 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 1fc9866..5c7a6c5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -199,7 +199,6 @@ static void amdgpu_evict_flags(struct ttm_buffer_object 
> *bo,
> .lpfn = 0,
> .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
> };
> -   unsigned i;
>
> if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) {
> placement->placement = 
> @@ -217,20 +216,6 @@ static void amdgpu_evict_flags(struct ttm_buffer_object 
> *bo,
> amdgpu_ttm_placement_from_domain(abo, 
> AMDGPU_GEM_DOMAIN_CPU);
> } else {
> amdgpu_ttm_placement_from_domain(abo, 
> AMDGPU_GEM_DOMAIN_GTT);
> -   for (i = 0; i < abo->placement.num_placement; ++i) {
> -   if (!(abo->placements[i].flags &
> - TTM_PL_FLAG_TT))
> -   continue;
> -
> -   if (abo->placements[i].lpfn)
> -   continue;
> -
> -   /* set an upper limit to force directly
> -* allocating address space for the BO.
> -*/
> -   abo->placements[i].lpfn =
> -   adev->mc.gtt_size >> PAGE_SHIFT;
> -   }
> }
> break;
> case TTM_PL_TT:
> @@ -391,7 +376,7 @@ static int amdgpu_move_vram_ram(struct ttm_buffer_object 
> *bo,
> placement.num_busy_placement = 1;
> placement.busy_placement = 
> placements.fpfn = 0;
> -   placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
> +   placements.lpfn = 0;
> placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
> r = ttm_bo_mem_space(bo, , _mem,
>  interruptible, no_wait_gpu);
> @@ -438,7 +423,7 @@ static int amdgpu_move_ram_vram(struct ttm_buffer_object 
> *bo,
> placement.num_busy_placement = 1;
> placement.busy_placement = 
> placements.fpfn = 0;
> -   placements.lpfn = adev->mc.gtt_size >> PAGE_SHIFT;
> +   placements.lpfn = 0;
> placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
> r = ttm_bo_mem_space(bo, , _mem,
>  interruptible, no_wait_gpu);
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 03/11] drm/amdgpu: use the GTT windows for BO moves v2

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König  wrote:
> From: Christian König 
>
> This way we don't need to map the full BO at a time any more.
>
> v2: use fixed windows for src/dst
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 125 
> +++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h |   2 +
>  2 files changed, 108 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 15148f1..1fc9866 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -47,10 +47,15 @@
>
>  #define DRM_FILE_PAGE_OFFSET (0x1ULL >> PAGE_SHIFT)
>
> +static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
> +struct ttm_mem_reg *mem, unsigned num_pages,
> +uint64_t offset, unsigned window,
> +struct amdgpu_ring *ring,
> +uint64_t *addr);
> +
>  static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
>  static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
>
> -
>  /*
>   * Global memory.
>   */
> @@ -97,6 +102,8 @@ static int amdgpu_ttm_global_init(struct amdgpu_device 
> *adev)
> goto error_bo;
> }
>
> +   mutex_init(>mman.gtt_window_lock);
> +
> ring = adev->mman.buffer_funcs_ring;
> rq = >sched.sched_rq[AMD_SCHED_PRIORITY_KERNEL];
> r = amd_sched_entity_init(>sched, >mman.entity,
> @@ -123,6 +130,7 @@ static void amdgpu_ttm_global_fini(struct amdgpu_device 
> *adev)
> if (adev->mman.mem_global_referenced) {
> amd_sched_entity_fini(adev->mman.entity.sched,
>   >mman.entity);
> +   mutex_destroy(>mman.gtt_window_lock);
> drm_global_item_unref(>mman.bo_global_ref.ref);
> drm_global_item_unref(>mman.mem_global_ref);
> adev->mman.mem_global_referenced = false;
> @@ -256,10 +264,13 @@ static uint64_t amdgpu_mm_node_addr(struct 
> ttm_buffer_object *bo,
> struct drm_mm_node *mm_node,
> struct ttm_mem_reg *mem)
>  {
> -   uint64_t addr;
> +   uint64_t addr = 0;
>
> -   addr = mm_node->start << PAGE_SHIFT;
> -   addr += bo->bdev->man[mem->mem_type].gpu_offset;
> +   if (mem->mem_type != TTM_PL_TT ||
> +   amdgpu_gtt_mgr_is_allocated(mem)) {
> +   addr = mm_node->start << PAGE_SHIFT;
> +   addr += bo->bdev->man[mem->mem_type].gpu_offset;
> +   }
> return addr;
>  }
>
> @@ -284,34 +295,41 @@ static int amdgpu_move_blit(struct ttm_buffer_object 
> *bo,
> return -EINVAL;
> }
>
> -   if (old_mem->mem_type == TTM_PL_TT) {
> -   r = amdgpu_ttm_bind(bo, old_mem);
> -   if (r)
> -   return r;
> -   }
> -
> old_mm = old_mem->mm_node;
> old_size = old_mm->size;
> old_start = amdgpu_mm_node_addr(bo, old_mm, old_mem);
>
> -   if (new_mem->mem_type == TTM_PL_TT) {
> -   r = amdgpu_ttm_bind(bo, new_mem);
> -   if (r)
> -   return r;
> -   }
> -
> new_mm = new_mem->mm_node;
> new_size = new_mm->size;
> new_start = amdgpu_mm_node_addr(bo, new_mm, new_mem);
>
> num_pages = new_mem->num_pages;
> +   mutex_lock(>mman.gtt_window_lock);
> while (num_pages) {
> -   unsigned long cur_pages = min(old_size, new_size);
> +   unsigned long cur_pages = min(min(old_size, new_size),
> + 
> (u64)AMDGPU_GTT_MAX_TRANSFER_SIZE);
> +   uint64_t from = old_start, to = new_start;
> struct dma_fence *next;
>
> -   r = amdgpu_copy_buffer(ring, old_start, new_start,
> +   if (old_mem->mem_type == TTM_PL_TT &&
> +   !amdgpu_gtt_mgr_is_allocated(old_mem)) {
> +   r = amdgpu_map_buffer(bo, old_mem, cur_pages,
> + old_start, 0, ring, );
> +   if (r)
> +   goto error;
> +   }
> +
> +   if (new_mem->mem_type == TTM_PL_TT &&
> +   !amdgpu_gtt_mgr_is_allocated(new_mem)) {
> +   r = amdgpu_map_buffer(bo, new_mem, cur_pages,
> + new_start, 1, ring, );
> +   if (r)
> +   goto error;
> +   }
> +
> +   r = amdgpu_copy_buffer(ring, from, to,
>cur_pages * PAGE_SIZE,
> -

Re: [PATCH 02/11] drm/amdgpu: add amdgpu_gart_map function v2

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König  wrote:
> From: Christian König 
>
> This allows us to write the mapped PTEs into
> an IB instead of the table directly.
>
> v2: fix build with debugfs enabled, remove unused assignment
>
> Signed-off-by: Christian König 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  3 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 62 
> 
>  2 files changed, 51 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 810796a..4a2b33d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -572,6 +572,9 @@ int amdgpu_gart_init(struct amdgpu_device *adev);
>  void amdgpu_gart_fini(struct amdgpu_device *adev);
>  int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
> int pages);
> +int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
> +   int pages, dma_addr_t *dma_addr, uint64_t flags,
> +   void *dst);
>  int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
>  int pages, struct page **pagelist,
>  dma_addr_t *dma_addr, uint64_t flags);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> index 8877015..c808388 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> @@ -280,6 +280,41 @@ int amdgpu_gart_unbind(struct amdgpu_device *adev, 
> uint64_t offset,
>  }
>
>  /**
> + * amdgpu_gart_map - map dma_addresses into GART entries
> + *
> + * @adev: amdgpu_device pointer
> + * @offset: offset into the GPU's gart aperture
> + * @pages: number of pages to bind
> + * @dma_addr: DMA addresses of pages
> + *
> + * Map the dma_addresses into GART entries (all asics).
> + * Returns 0 for success, -EINVAL for failure.
> + */
> +int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
> +   int pages, dma_addr_t *dma_addr, uint64_t flags,
> +   void *dst)
> +{
> +   uint64_t page_base;
> +   unsigned i, j, t;
> +
> +   if (!adev->gart.ready) {
> +   WARN(1, "trying to bind memory to uninitialized GART !\n");
> +   return -EINVAL;
> +   }
> +
> +   t = offset / AMDGPU_GPU_PAGE_SIZE;
> +
> +   for (i = 0; i < pages; i++) {
> +   page_base = dma_addr[i];
> +   for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); j++, t++) 
> {
> +   amdgpu_gart_set_pte_pde(adev, dst, t, page_base, 
> flags);
> +   page_base += AMDGPU_GPU_PAGE_SIZE;
> +   }
> +   }
> +   return 0;
> +}
> +
> +/**
>   * amdgpu_gart_bind - bind pages into the gart page table
>   *
>   * @adev: amdgpu_device pointer
> @@ -296,31 +331,30 @@ int amdgpu_gart_bind(struct amdgpu_device *adev, 
> uint64_t offset,
>  int pages, struct page **pagelist, dma_addr_t *dma_addr,
>  uint64_t flags)
>  {
> -   unsigned t;
> -   unsigned p;
> -   uint64_t page_base;
> -   int i, j;
> +#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
> +   unsigned i,t,p;
> +#endif
> +   int r;
>
> if (!adev->gart.ready) {
> WARN(1, "trying to bind memory to uninitialized GART !\n");
> return -EINVAL;
> }
>
> +#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
> t = offset / AMDGPU_GPU_PAGE_SIZE;
> p = t / (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
> -
> -   for (i = 0; i < pages; i++, p++) {
> -#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
> +   for (i = 0; i < pages; i++, p++)
> adev->gart.pages[p] = pagelist[i];
>  #endif
> -   if (adev->gart.ptr) {
> -   page_base = dma_addr[i];
> -   for (j = 0; j < (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE); 
> j++, t++) {
> -   amdgpu_gart_set_pte_pde(adev, adev->gart.ptr, 
> t, page_base, flags);
> -   page_base += AMDGPU_GPU_PAGE_SIZE;
> -   }
> -   }
> +
> +   if (adev->gart.ptr) {
> +   r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
> +   adev->gart.ptr);
> +   if (r)
> +   return r;
> }
> +
> mb();
> amdgpu_gart_flush_gpu_tlb(adev, 0);
> return 0;
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 01/11] drm/amdgpu: reserve the first 2x512 of GART

[Alex Deucher]

On Mon, Jul 3, 2017 at 5:44 AM, Christian König  wrote:
> From: Christian König 
>
> We want to use them as remap address space.
>
> Signed-off-by: Christian König 

2x512 pages.  With that updated:
Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 5 -
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 +++
>  2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> index 1ef6255..f46a97d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> @@ -43,12 +43,15 @@ static int amdgpu_gtt_mgr_init(struct 
> ttm_mem_type_manager *man,
>unsigned long p_size)
>  {
> struct amdgpu_gtt_mgr *mgr;
> +   uint64_t start, size;
>
> mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
> if (!mgr)
> return -ENOMEM;
>
> -   drm_mm_init(>mm, 0, p_size);
> +   start = AMDGPU_GTT_MAX_TRANSFER_SIZE * 
> AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
> +   size = p_size - start;
> +   drm_mm_init(>mm, start, size);
> spin_lock_init(>lock);
> mgr->available = p_size;
> man->priv = mgr;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index 776a20a..c8059f0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -34,6 +34,9 @@
>  #define AMDGPU_PL_FLAG_GWS (TTM_PL_FLAG_PRIV << 1)
>  #define AMDGPU_PL_FLAG_OA  (TTM_PL_FLAG_PRIV << 2)
>
> +#define AMDGPU_GTT_MAX_TRANSFER_SIZE   512
> +#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS2
> +
>  struct amdgpu_mman {
> struct ttm_bo_global_refbo_global_ref;
> struct drm_global_reference mem_global_ref;
> --
> 2.7.4
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH][drm-next] drm/amdgpu: make arrays pctl0_data and pctl1_data static

[Alex Deucher]

On Thu, Jul 6, 2017 at 5:58 AM, Colin King  wrote:
> From: Colin Ian King 
>
> The arrays pctl0_data and pctl1_data do not need to be in global scope,
> so them both static.
>
> Cleans up sparse warnings:
> symbol 'pctl0_data' was not declared. Should it be static?
> symbol 'pctl1_data' was not declared. Should it be static?
>
> Signed-off-by: Colin Ian King 


Applied.  thanks!

Alex

> ---
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 9804318f3488..4c079207d699 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -249,7 +249,7 @@ struct pctl_data {
>  uint32_t data;
>  };
>
> -const struct pctl_data pctl0_data[] = {
> +static const struct pctl_data pctl0_data[] = {
>  {0x0, 0x7a640},
>  {0x9, 0x2a64a},
>  {0xd, 0x2a680},
> @@ -274,7 +274,7 @@ const struct pctl_data pctl0_data[] = {
>  #define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE  0xa640
>  #define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833
>
> -const struct pctl_data pctl1_data[] = {
> +static const struct pctl_data pctl1_data[] = {
>  {0x0, 0x39a000},
>  {0x3b, 0x44a040},
>  {0x81, 0x2a08d},
> --
> 2.11.0
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v4 04/14] drm: amd: remove dead code and pointless local lut storage

[Peter Rosin]

The redundant fb helpers .load_lut, .gamma_set and .gamma_get are
no longer used. Remove the dead code and hook up the crtc .gamma_set
to use the crtc gamma_store directly instead of duplicating that
info locally.

Signed-off-by: Peter Rosin 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c   | 24 
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h |  1 -
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c   | 27 +++
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c   | 27 +++
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c| 27 +++
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c| 27 +++
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 23 ---
 7 files changed, 28 insertions(+), 128 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index c0d8c6f..7dc3780 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -312,31 +312,7 @@ static int amdgpu_fbdev_destroy(struct drm_device *dev, 
struct amdgpu_fbdev *rfb
return 0;
 }
 
-/** Sets the color ramps on behalf of fbcon */
-static void amdgpu_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
- u16 blue, int regno)
-{
-   struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-
-   amdgpu_crtc->lut_r[regno] = red >> 6;
-   amdgpu_crtc->lut_g[regno] = green >> 6;
-   amdgpu_crtc->lut_b[regno] = blue >> 6;
-}
-
-/** Gets the color ramps on behalf of fbcon */
-static void amdgpu_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 
*green,
- u16 *blue, int regno)
-{
-   struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-
-   *red = amdgpu_crtc->lut_r[regno] << 6;
-   *green = amdgpu_crtc->lut_g[regno] << 6;
-   *blue = amdgpu_crtc->lut_b[regno] << 6;
-}
-
 static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = {
-   .gamma_set = amdgpu_crtc_fb_gamma_set,
-   .gamma_get = amdgpu_crtc_fb_gamma_get,
.fb_probe = amdgpufb_create,
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 43a9d3a..39f7eda 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -369,7 +369,6 @@ struct amdgpu_atom_ss {
 struct amdgpu_crtc {
struct drm_crtc base;
int crtc_id;
-   u16 lut_r[256], lut_g[256], lut_b[256];
bool enabled;
bool can_tile;
uint32_t crtc_offset;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 9f78c03..c958023 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2267,6 +2267,7 @@ static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct amdgpu_device *adev = dev->dev_private;
+   u16 *r, *g, *b;
int i;
u32 tmp;
 
@@ -2304,11 +2305,14 @@ static void dce_v10_0_crtc_load_lut(struct drm_crtc 
*crtc)
WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x0007);
 
WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
+   r = crtc->gamma_store;
+   g = r + crtc->gamma_size;
+   b = g + crtc->gamma_size;
for (i = 0; i < 256; i++) {
WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
-  (amdgpu_crtc->lut_r[i] << 20) |
-  (amdgpu_crtc->lut_g[i] << 10) |
-  (amdgpu_crtc->lut_b[i] << 0));
+  ((*r++ & 0xffc0) << 14) |
+  ((*g++ & 0xffc0) << 4) |
+  (*b++ >> 6));
}
 
tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
@@ -2624,15 +2628,6 @@ static int dce_v10_0_crtc_gamma_set(struct drm_crtc 
*crtc, u16 *red, u16 *green,
u16 *blue, uint32_t size,
struct drm_modeset_acquire_ctx *ctx)
 {
-   struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-   int i;
-
-   /* userspace palettes are always correct as is */
-   for (i = 0; i < size; i++) {
-   amdgpu_crtc->lut_r[i] = red[i] >> 6;
-   amdgpu_crtc->lut_g[i] = green[i] >> 6;
-   amdgpu_crtc->lut_b[i] = blue[i] >> 6;
-   }
dce_v10_0_crtc_load_lut(crtc);
 
return 0;
@@ -2844,14 +2839,12 @@ static const struct drm_crtc_helper_funcs 
dce_v10_0_crtc_helper_funcs = {
.mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
.prepare = dce_v10_0_crtc_prepare,
.commit = dce_v10_0_crtc_commit,
-   .load_lut = dce_v10_0_crtc_load_lut,
.disable = dce_v10_0_crtc_disable,
 };
 
 static int dce_v10_0_crtc_init(struct 

[PATCH][drm-next] drm/amdgpu: make arrays pctl0_data and pctl1_data static

[Colin King]

From: Colin Ian King 

The arrays pctl0_data and pctl1_data do not need to be in global scope,
so them both static.

Cleans up sparse warnings:
symbol 'pctl0_data' was not declared. Should it be static?
symbol 'pctl1_data' was not declared. Should it be static?

Signed-off-by: Colin Ian King 
---
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 9804318f3488..4c079207d699 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -249,7 +249,7 @@ struct pctl_data {
 uint32_t data;
 };
 
-const struct pctl_data pctl0_data[] = {
+static const struct pctl_data pctl0_data[] = {
 {0x0, 0x7a640},
 {0x9, 0x2a64a},
 {0xd, 0x2a680},
@@ -274,7 +274,7 @@ const struct pctl_data pctl0_data[] = {
 #define PCTL0_STCTRL_REG_SAVE_RANGE0_BASE  0xa640
 #define PCTL0_STCTRL_REG_SAVE_RANGE0_LIMIT 0xa833
 
-const struct pctl_data pctl1_data[] = {
+static const struct pctl_data pctl1_data[] = {
 {0x0, 0x39a000},
 {0x3b, 0x44a040},
 {0x81, 0x2a08d},
-- 
2.11.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v4 12/14] drm: radeon: remove dead code and pointless local lut storage

[Peter Rosin]

The redundant fb helpers .load_lut, .gamma_set and .gamma_get are
no longer used. Remove the dead code and hook up the crtc .gamma_set
to use the crtc gamma_store directly instead of duplicating that
info locally.

Signed-off-by: Peter Rosin 
---
 drivers/gpu/drm/radeon/atombios_crtc.c  |  1 -
 drivers/gpu/drm/radeon/radeon_connectors.c  |  7 ++-
 drivers/gpu/drm/radeon/radeon_display.c | 71 -
 drivers/gpu/drm/radeon/radeon_fb.c  |  2 -
 drivers/gpu/drm/radeon/radeon_legacy_crtc.c |  1 -
 drivers/gpu/drm/radeon/radeon_mode.h|  4 --
 6 files changed, 33 insertions(+), 53 deletions(-)

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c 
b/drivers/gpu/drm/radeon/atombios_crtc.c
index 3c492a0..02baaaf 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -2217,7 +2217,6 @@ static const struct drm_crtc_helper_funcs 
atombios_helper_funcs = {
.mode_set_base_atomic = atombios_crtc_set_base_atomic,
.prepare = atombios_crtc_prepare,
.commit = atombios_crtc_commit,
-   .load_lut = radeon_crtc_load_lut,
.disable = atombios_crtc_disable,
 };
 
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c 
b/drivers/gpu/drm/radeon/radeon_connectors.c
index 27affbd..2f642cb 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -773,12 +773,15 @@ static int radeon_connector_set_property(struct 
drm_connector *connector, struct
 
if (connector->encoder->crtc) {
struct drm_crtc *crtc  = connector->encoder->crtc;
-   const struct drm_crtc_helper_funcs *crtc_funcs = 
crtc->helper_private;
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 
radeon_crtc->output_csc = radeon_encoder->output_csc;
 
-   (*crtc_funcs->load_lut)(crtc);
+   /*
+* Our .gamma_set assumes the .gamma_store has been
+* prefilled and don't care about its arguments.
+*/
+   crtc->funcs->gamma_set(crtc, NULL, NULL, NULL, 0, NULL);
}
}
 
diff --git a/drivers/gpu/drm/radeon/radeon_display.c 
b/drivers/gpu/drm/radeon/radeon_display.c
index 17d3daf..8b7d7a0 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -42,6 +42,7 @@ static void avivo_crtc_load_lut(struct drm_crtc *crtc)
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct radeon_device *rdev = dev->dev_private;
+   u16 *r, *g, *b;
int i;
 
DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
@@ -60,11 +61,14 @@ static void avivo_crtc_load_lut(struct drm_crtc *crtc)
WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x003f);
 
WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
+   r = crtc->gamma_store;
+   g = r + crtc->gamma_size;
+   b = g + crtc->gamma_size;
for (i = 0; i < 256; i++) {
WREG32(AVIVO_DC_LUT_30_COLOR,
-(radeon_crtc->lut_r[i] << 20) |
-(radeon_crtc->lut_g[i] << 10) |
-(radeon_crtc->lut_b[i] << 0));
+  ((*r++ & 0xffc0) << 14) |
+  ((*g++ & 0xffc0) << 4) |
+  (*b++ >> 6));
}
 
/* Only change bit 0 of LUT_SEL, other bits are set elsewhere */
@@ -76,6 +80,7 @@ static void dce4_crtc_load_lut(struct drm_crtc *crtc)
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct radeon_device *rdev = dev->dev_private;
+   u16 *r, *g, *b;
int i;
 
DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
@@ -93,11 +98,14 @@ static void dce4_crtc_load_lut(struct drm_crtc *crtc)
WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 
0x0007);
 
WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
+   r = crtc->gamma_store;
+   g = r + crtc->gamma_size;
+   b = g + crtc->gamma_size;
for (i = 0; i < 256; i++) {
WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
-  (radeon_crtc->lut_r[i] << 20) |
-  (radeon_crtc->lut_g[i] << 10) |
-  (radeon_crtc->lut_b[i] << 0));
+  ((*r++ & 0xffc0) << 14) |
+  ((*g++ & 0xffc0) << 4) |
+  (*b++ >> 6));
}
 }
 
@@ -106,6 +114,7 @@ static void dce5_crtc_load_lut(struct drm_crtc *crtc)
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct radeon_device *rdev = dev->dev_private;
+   u16 *r, *g, *b;
int i;
 
DRM_DEBUG_KMS("%d\n", 

[PATCH v4 00/14] improve the fb_setcmap helper

[Peter Rosin]

Hi!

While trying to get CLUT support for the atmel_hlcdc driver, and
specifically for the emulated fbdev interface, I received some
push-back that my feeble in-driver attempts should be solved
by the core. This is my attempt to do it right.

I have obviously not tested all of this with more than a compile,
but patches 1 and 3 are enough to make the atmel-hlcdc driver
do what I need. The rest is just lots of removals and cleanup made
possible by the other improvements.

Please test, I would not be surprised if I have fouled up some
bit-manipulation somewhere, or if I have misunderstood something
about atomics...

Changes since v3:
- Rebased onto drm-misc-next and dropped patches 1-3 from v3, since
  they are already merged.
- Dropped the v3 patch 4/16 ("drm/color-mgmt: move atomic state/commit
  out from .gamma_set") since the atomic setcmap no longer uses
  the crtc .gamma_set callback.
- Added patch 1/14 which exports drm_atomic_replace_property_blob...
- ...and patch 2/14 which uses this new export to simplify
  drm_atomic_helper_legacy_gamma_set.
- Big changes to patch 3/14 (was 5/16 in v3). It had various locking
  issues and the atomic setcmap is rather different.

Changes since v2:
- Added patch 1/16 which factors out pseudo-palette handling.
- Removed the if (cmap->start + cmap->len < cmap->start)
  sanity check on the assumption that the fbdev core handles it.
- Added patch 4/16 which factors out atomic state and commit
  handling from drm_atomic_helper_legacy_gamma_set to
  drm_mode_gamma_set_ioctl.
- Do one atomic commit for all affected crtc.
- Removed a now obsolete note in include/drm/drm_crtc.h (ammended
  the last patch).
- Cc list is getting long, so I have redused the list for the
  individual patches. If you would like to get the full series
  (or nothing at all) for the next round (if that is needed) just
  say so.

Changes since v1:

- Rebased to next-20170621
- Split 1/11 into a preparatory patch, a cleanup patch and then
  the meat in 3/14.
- Handle pseudo-palette for FB_VISUAL_TRUECOLOR.
- Removed the empty .gamma_get/.gamma_set fb helpers from the
  armada driver that I had somehow managed to ignore but which
  0day found real quick.
- Be less judgemental on drivers only providing .gamma_get and
  .gamma_set, but no .load_lut. That's actually a valid thing
  to do if you only need pseudo-palette for FB_VISUAL_TRUECOLOR.
- Add a comment about colliding bitfields in the nouveau driver.
- Remove gamma_set/gamma_get declarations from the radeon driver
  (the definitions were removed in v1).

Cheers,
peda

Peter Rosin (14):
  drm/atomic: export drm_atomic_replace_property_blob
  drm/atomic-helper: update lut props directly in ..._legacy_gamma_set
  drm/fb-helper: separate the fb_setcmap helper into atomic and legacy
paths
  drm: amd: remove dead code and pointless local lut storage
  drm: armada: remove dead empty functions
  drm: ast: remove dead code and pointless local lut storage
  drm: cirrus: remove dead code and pointless local lut storage
  drm: gma500: remove dead code and pointless local lut storage
  drm: i915: remove dead code and pointless local lut storage
  drm: mgag200: remove dead code and pointless local lut storage
  drm: nouveau: remove dead code and pointless local lut storage
  drm: radeon: remove dead code and pointless local lut storage
  drm: stm: remove dead code and pointless local lut storage
  drm: remove unused and redundant callbacks

 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c  |  24 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h|   1 -
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c  |  27 +---
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c  |  27 +---
 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c   |  27 +---
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c   |  27 +---
 drivers/gpu/drm/amd/amdgpu/dce_virtual.c|  23 ---
 drivers/gpu/drm/armada/armada_crtc.c|  10 --
 drivers/gpu/drm/armada/armada_crtc.h|   2 -
 drivers/gpu/drm/armada/armada_fbdev.c   |   2 -
 drivers/gpu/drm/ast/ast_drv.h   |   1 -
 drivers/gpu/drm/ast/ast_fb.c|  20 ---
 drivers/gpu/drm/ast/ast_mode.c  |  26 +---
 drivers/gpu/drm/cirrus/cirrus_drv.h |   8 -
 drivers/gpu/drm/cirrus/cirrus_fbdev.c   |   2 -
 drivers/gpu/drm/cirrus/cirrus_mode.c|  71 ++---
 drivers/gpu/drm/drm_atomic.c|  17 +-
 drivers/gpu/drm/drm_atomic_helper.c |  23 +--
 drivers/gpu/drm/drm_fb_helper.c | 232 +++-
 drivers/gpu/drm/gma500/framebuffer.c|  22 ---
 drivers/gpu/drm/gma500/gma_display.c|  32 ++--
 drivers/gpu/drm/gma500/psb_intel_display.c  |   7 +-
 drivers/gpu/drm/gma500/psb_intel_drv.h  |   1 -
 drivers/gpu/drm/i915/intel_drv.h|   1 -
 drivers/gpu/drm/i915/intel_fbdev.c  |  31 
 drivers/gpu/drm/mgag200/mgag200_drv.h   |   5 -
 drivers/gpu/drm/mgag200/mgag200_fb.c|   2 -
 drivers/gpu/drm/mgag200/mgag200_mode.c  | 

[PATCH umr] Add ability to import new asic from script file (v2)

[Tom St Denis]

This is meant for NPI support only as publicly released designs
can simply add to the static definitions.

This is used by using the --force (-f) option with a filename that has
a @ prefixed on, e.g.

umr -O bits -f @demo/npi/newchip -lr gfx10

Will read the file 'newchip' and import the ip/reg/bit definitions and then
can proceed as normal producing this output:

[WARNING]: Should use --pci when using create_asic_from_script()
new_chip.gfx10.mmSUPER_SECRET => 0x12345670
new_chip.gfx10.mmSUPER_SECRET.enable[0:0]

You will need to use --pci to specify a precise device otherwise it won't be
able to talk to it.

Signed-off-by: Tom St Denis 

(v2): Added fakerizo demo and updated PCI detection logic to be more robust
---
 demo/npi/README   |   2 +
 demo/npi/fakerizo |  26 
 demo/npi/new_chip |   2 +
 src/app/main.c|   1 +
 src/lib/CMakeLists.txt|   1 +
 src/lib/create_asic_from_script.c | 286 ++
 src/lib/discover.c|  18 ++-
 src/lib/discover_by_name.c|   3 +
 src/umr.h |   3 +
 9 files changed, 338 insertions(+), 4 deletions(-)
 create mode 100644 demo/npi/README
 create mode 100644 demo/npi/fakerizo
 create mode 100644 demo/npi/new_chip
 create mode 100644 src/lib/create_asic_from_script.c

diff --git a/demo/npi/README b/demo/npi/README
new file mode 100644
index ..4ada3e57a0f1
--- /dev/null
+++ b/demo/npi/README
@@ -0,0 +1,2 @@
+Added fakerizo which is a "fake" Carrizo so I could test the new
+PCI detection logic which should be somewhat more future proof.
diff --git a/demo/npi/fakerizo b/demo/npi/fakerizo
new file mode 100644
index ..8ec3a18f7c57
--- /dev/null
+++ b/demo/npi/fakerizo
@@ -0,0 +1,26 @@
+reg gfx80 mmGRBM_STATUS mmio 0x801
+bit gfx80 mmGRBM_STATUS ME0PIPE0_CMDFIFO_AVAIL 0 3 
+bit gfx80 mmGRBM_STATUS SRBM_RQ_PENDING 5 5 
+bit gfx80 mmGRBM_STATUS ME0PIPE0_CF_RQ_PENDING 7 7 
+bit gfx80 mmGRBM_STATUS ME0PIPE0_PF_RQ_PENDING 8 8 
+bit gfx80 mmGRBM_STATUS GDS_DMA_RQ_PENDING 9 9 
+bit gfx80 mmGRBM_STATUS DB_CLEAN 12 12 
+bit gfx80 mmGRBM_STATUS CB_CLEAN 13 13 
+bit gfx80 mmGRBM_STATUS TA_BUSY 14 14 
+bit gfx80 mmGRBM_STATUS GDS_BUSY 15 15 
+bit gfx80 mmGRBM_STATUS WD_BUSY_NO_DMA 16 16 
+bit gfx80 mmGRBM_STATUS VGT_BUSY 17 17 
+bit gfx80 mmGRBM_STATUS IA_BUSY_NO_DMA 18 18 
+bit gfx80 mmGRBM_STATUS IA_BUSY 19 19 
+bit gfx80 mmGRBM_STATUS SX_BUSY 20 20 
+bit gfx80 mmGRBM_STATUS WD_BUSY 21 21 
+bit gfx80 mmGRBM_STATUS SPI_BUSY 22 22 
+bit gfx80 mmGRBM_STATUS BCI_BUSY 23 23 
+bit gfx80 mmGRBM_STATUS SC_BUSY 24 24 
+bit gfx80 mmGRBM_STATUS PA_BUSY 25 25 
+bit gfx80 mmGRBM_STATUS DB_BUSY 26 26 
+bit gfx80 mmGRBM_STATUS CP_COHERENCY_BUSY 28 28 
+bit gfx80 mmGRBM_STATUS CP_BUSY 29 29 
+bit gfx80 mmGRBM_STATUS CB_BUSY 30 30 
+bit gfx80 mmGRBM_STATUS GUI_ACTIVE 31 31 
+
diff --git a/demo/npi/new_chip b/demo/npi/new_chip
new file mode 100644
index ..deb4148b12d6
--- /dev/null
+++ b/demo/npi/new_chip
@@ -0,0 +1,2 @@
+reg gfx10 mmSUPER_SECRET mmio 0x12345670
+bit gfx10 mmSUPER_SECRET enable 0 0
diff --git a/src/app/main.c b/src/app/main.c
index ac3c25e2937e..4fc26510be32 100644
--- a/src/app/main.c
+++ b/src/app/main.c
@@ -178,6 +178,7 @@ int main(int argc, char **argv)
if (i + 1 < argc && sscanf(argv[i+1], 
"%04x:%02x:%02x.%01x",
, , 
,
 ) >= 4) {
+   options.use_pci = 1; // implied by the --pci 
option
++i;
} else {
printf("--pci requires 
domain:bus:slot.function\n");
diff --git a/src/lib/CMakeLists.txt b/src/lib/CMakeLists.txt
index dfdf44cf4ad2..217ae80cdfd7 100644
--- a/src/lib/CMakeLists.txt
+++ b/src/lib/CMakeLists.txt
@@ -7,6 +7,7 @@ add_library(umrcore STATIC
   bitfield_print.c
   close_asic.c
   create_asic_helper.c
+  create_asic_from_script.c
   create_mmio_accel.c
   discover_by_did.c
   discover_by_name.c
diff --git a/src/lib/create_asic_from_script.c 
b/src/lib/create_asic_from_script.c
new file mode 100644
index ..34c77870ec1c
--- /dev/null
+++ b/src/lib/create_asic_from_script.c
@@ -0,0 +1,286 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *

RE: [PATCH libdrm 2/2] radeon: use asic id table to get chipset name

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Emil Velikov
> Sent: Thursday, July 06, 2017 5:21 AM
> To: Li, Samuel
> Cc: ML dri-devel; amd-gfx mailing list
> Subject: Re: [PATCH libdrm 2/2] radeon: use asic id table to get chipset name
> 
> On 5 July 2017 at 22:31, Li, Samuel  wrote:
> >>  - above all, as-is make check will fail
> > Right, I did not check that.
> >
> >>  - keeping the radeon API symmetrical to the amdgpu one would a good
> idea
> > The issue is Radeon does not have a struct similar to
> amdgpu_device_handle.
> Attach it to analogous primitive?

Radeon libdrm is much different than amdgpu.  There is no analog.

> 
> > I think the current radeon API is simpler. Maybe a follow up change can
> change amdgpu's API similar to radeon.
> >
> Exposing 3 entry points instead of 1 is _not_simpler. Also you cannot
> change the existing API, since it also breaks the ABI.
> Leading to crash/cause memory corruption when using existing binaries.
> 
> >>  - is adding yet another header really justified?
> > radeon_asic_id.h? That is going to be used by ddx/mesa.
> >
> Where it's used is orthogonal. You don't need a separate _public_
> header for nearly every entry point ;-)

Actually having a separate header makes sense for radeon.  We currently expose 
a separate header for each set of functionality (one for buffer management, one 
for command submission, one for surface management).  Adding the asic names to 
any of the existing ones doesn’t really make sense from a functional standpoint.

Alex

> 
> Thanks
> Emil
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH 4/5] drm/amdgpu: check scratch registers to see if we need post

[Deucher, Alexander]

> -Original Message-
> From: Zhang, Jerry
> Sent: Thursday, July 06, 2017 2:08 AM
> To: Alex Deucher; amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander
> Subject: Re: [PATCH 4/5] drm/amdgpu: check scratch registers to see if we
> need post
> 
> On 07/01/2017 05:32 AM, Alex Deucher wrote:
> > Rather than checking the CONGIG_MEMSIZE register as that may
> > not be reliable on some APUs.
> >
> > Signed-off-by: Alex Deucher 
> > ---
> >   drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +-
> >   1 file changed, 1 insertion(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index 63f4bed..9d08f53 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -716,20 +716,12 @@ void amdgpu_gtt_location(struct amdgpu_device
> *adev, struct amdgpu_mc *mc)
> >*/
> >   bool amdgpu_need_post(struct amdgpu_device *adev)
> >   {
> > -   uint32_t reg;
> > -
> > if (adev->has_hw_reset) {
> > adev->has_hw_reset = false;
> > return true;
> > }
> > -   /* then check MEM_SIZE, in case the crtcs are off */
> > -   reg = amdgpu_asic_get_config_memsize(adev);
> 
> Do we still need it for SI?

Yes, I sent out a v2 of the patch.

Alex

> 
> Jerry
> 
> > -
> > -   if ((reg != 0) && (reg != 0x))
> > -   return false;
> > -
> > -   return true;
> >
> > +   return amdgpu_atombios_scratch_need_asic_init(adev);
> >   }
> >
> >   static bool amdgpu_vpost_needed(struct amdgpu_device *adev)
> >
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH umr] Add ability to import new asic from script file

[Tom St Denis]

This is meant for NPI support only as publicly released designs
can simply add to the static definitions.

This is used by using the --force (-f) option with a filename that has
a @ prefixed on, e.g.

umr -O bits -f @demo/npi/newchip -lr gfx10

Will read the file 'newchip' and import the ip/reg/bit definitions and then
can proceed as normal producing this output:

[WARNING]: Should use --pci when using create_asic_from_script()
new_chip.gfx10.mmSUPER_SECRET => 0x12345670
new_chip.gfx10.mmSUPER_SECRET.enable[0:0]

You will need to use --pci to specify a precise device otherwise it won't be
able to talk to it.

Signed-off-by: Tom St Denis 
---
 demo/npi/new_chip |   2 +
 src/app/main.c|   1 +
 src/lib/CMakeLists.txt|   1 +
 src/lib/create_asic_from_script.c | 286 ++
 src/lib/discover.c|   9 +-
 src/lib/discover_by_name.c|   3 +
 src/umr.h |   3 +
 7 files changed, 304 insertions(+), 1 deletion(-)
 create mode 100644 demo/npi/new_chip
 create mode 100644 src/lib/create_asic_from_script.c

diff --git a/demo/npi/new_chip b/demo/npi/new_chip
new file mode 100644
index ..deb4148b12d6
--- /dev/null
+++ b/demo/npi/new_chip
@@ -0,0 +1,2 @@
+reg gfx10 mmSUPER_SECRET mmio 0x12345670
+bit gfx10 mmSUPER_SECRET enable 0 0
diff --git a/src/app/main.c b/src/app/main.c
index ac3c25e2937e..4fc26510be32 100644
--- a/src/app/main.c
+++ b/src/app/main.c
@@ -178,6 +178,7 @@ int main(int argc, char **argv)
if (i + 1 < argc && sscanf(argv[i+1], 
"%04x:%02x:%02x.%01x",
, , 
,
 ) >= 4) {
+   options.use_pci = 1; // implied by the --pci 
option
++i;
} else {
printf("--pci requires 
domain:bus:slot.function\n");
diff --git a/src/lib/CMakeLists.txt b/src/lib/CMakeLists.txt
index dfdf44cf4ad2..217ae80cdfd7 100644
--- a/src/lib/CMakeLists.txt
+++ b/src/lib/CMakeLists.txt
@@ -7,6 +7,7 @@ add_library(umrcore STATIC
   bitfield_print.c
   close_asic.c
   create_asic_helper.c
+  create_asic_from_script.c
   create_mmio_accel.c
   discover_by_did.c
   discover_by_name.c
diff --git a/src/lib/create_asic_from_script.c 
b/src/lib/create_asic_from_script.c
new file mode 100644
index ..34c77870ec1c
--- /dev/null
+++ b/src/lib/create_asic_from_script.c
@@ -0,0 +1,286 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Tom St Denis 
+ *
+ */
+#include "umr.h"
+
+static void skip_whitespace(char **t)
+{
+   while (*t[0] == ' ' || *t[0] == '\t' ||
+  *t[0] == '\n' || *t[0] == '\r')
+  ++*t;
+}
+
+static void grab_word(char *dst, char **t)
+{
+   skip_whitespace(t);
+   while (*t[0] && !(*t[0] == ' ' || *t[0] == '\t' ||
+*t[0] == '\n' || *t[0] == '\r')) {
+   *dst++ = *t[0];
+   ++*t;
+   }
+   *dst = 0;
+}
+
+static int add_reg(struct umr_asic *asic, char **t)
+{
+   char ipname[512], regname[512], type[512], offset[512];
+   int i, j, itype;
+   uint64_t addr;
+   void *tmp;
+
+   memset(ipname, 0, sizeof ipname);
+   memset(regname, 0, sizeof regname);
+   memset(type, 0, sizeof type);
+   memset(offset, 0, sizeof offset);
+   grab_word(ipname, t);
+   grab_word(regname, t);
+   grab_word(type, t);
+   grab_word(offset, t);
+
+   // convert type to integer
+   if (!strcmp(type, "mmio")) {
+   itype = REG_MMIO;
+   } else if (!strcmp(type, "smc")) {
+   itype = REG_SMC;
+   } else if (!strcmp(type, "didt")) {
+   itype = REG_DIDT;
+   } else if 

Re: [PATCH v2 5/5] drm/amdgpu: Try evicting from CPU visible to invisible VRAM first

[Christian König]

Am 06.07.2017 um 12:51 schrieb Michel Dänzer:

From: Michel Dänzer 

This gives BOs which haven't been accessed by the CPU since they were
moved to visible VRAM another chance to stay in VRAM when another BO
needs to go to visible VRAM.

This should allow BOs to stay in VRAM longer in some cases.

v2:
* Only do this for BOs which don't have the
   AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED flag set.

Signed-off-by: Michel Dänzer 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 28 
  1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 58576375b91c..2a9906dd7637 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -207,7 +207,35 @@ static void amdgpu_evict_flags(struct ttm_buffer_object 
*bo,
adev->mman.buffer_funcs_ring &&
adev->mman.buffer_funcs_ring->ready == false) {
amdgpu_ttm_placement_from_domain(abo, 
AMDGPU_GEM_DOMAIN_CPU);
+   } else if (adev->mc.visible_vram_size < adev->mc.real_vram_size 
&&
+  !(abo->flags & 
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
+   unsigned fpfn = adev->mc.visible_vram_size >> 
PAGE_SHIFT;
+   struct drm_mm_node *node = bo->mem.mm_node;
+   unsigned long pages_left;
+
+   for (pages_left = bo->mem.num_pages;
+pages_left;
+pages_left -= node->size, node++) {
+   if (node->start < fpfn)
+   break;
+   }
+
+   if (!pages_left)
+   goto gtt;
+
+   /* Try evicting to the CPU inaccessible part of VRAM
+* first, but only set GTT as busy placement, so this
+* BO will be evicted to GTT rather than causing other
+* BOs to be evicted from VRAM
+*/
+   amdgpu_ttm_placement_from_domain(abo, 
AMDGPU_GEM_DOMAIN_VRAM |
+AMDGPU_GEM_DOMAIN_GTT);
+   abo->placements[0].fpfn = fpfn;
+   abo->placements[0].lpfn = 0;
+   abo->placement.busy_placement = >placements[1];
+   abo->placement.num_busy_placement = 1;
} else {
+gtt:
amdgpu_ttm_placement_from_domain(abo, 
AMDGPU_GEM_DOMAIN_GTT);
for (i = 0; i < abo->placement.num_placement; ++i) {
if (!(abo->placements[i].flags &



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 4/5] drm/amdgpu: Don't force BOs into visible VRAM for page faults

[Christian König]

Am 06.07.2017 um 12:51 schrieb Michel Dänzer:

From: John Brooks 

There is no need for page faults to force BOs into visible VRAM if it's
full, and the time it takes to do so is great enough to cause noticeable
stuttering. Add GTT as a possible placement so that if visible VRAM is
full, page faults move BOs to GTT instead of evicting other BOs from VRAM.

Suggested-by: Michel Dänzer 
Signed-off-by: John Brooks 
Reviewed-by: Michel Dänzer 
Signed-off-by: Michel Dänzer 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 17 ++---
  1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 93601fbea695..6e24339ecc46 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -974,18 +974,21 @@ int amdgpu_bo_fault_reserve_notify(struct 
ttm_buffer_object *bo)
  
  	/* hurrah the memory is not visible ! */

atomic64_inc(>num_vram_cpu_page_faults);
-   amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
+   amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
+AMDGPU_GEM_DOMAIN_GTT);
+
+   /* Avoid costly evictions; only set GTT as a busy placement */
+   abo->placement.num_busy_placement = 1;
+   abo->placement.busy_placement = >placements[1];
+
r = ttm_bo_validate(bo, >placement, false, false);
-   if (unlikely(r == -ENOMEM)) {
-   amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
-   return ttm_bo_validate(bo, >placement, false, false);
-   } else if (unlikely(r != 0)) {
+   if (unlikely(r != 0))
return r;
-   }
  
  	offset = bo->mem.start << PAGE_SHIFT;

/* this should never happen */
-   if ((offset + size) > adev->mc.visible_vram_size)
+   if (bo->mem.mem_type == TTM_PL_VRAM &&
+   (offset + size) > adev->mc.visible_vram_size)
return -EINVAL;
  
  	return 0;



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v3 3/5] drm/amdgpu: Set/clear CPU_ACCESS flag on page fault and move to VRAM

[Christian König]

Am 06.07.2017 um 12:51 schrieb Michel Dänzer:

From: John Brooks 

When a BO is moved to VRAM, clear AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED.
This allows it to potentially later move to invisible VRAM if the CPU
does not access it again.

Setting the CPU_ACCESS flag in amdgpu_bo_fault_reserve_notify() also means
that we can remove the loop to restrict lpfn to the end of visible VRAM,
because amdgpu_ttm_placement_init() will do it for us.

v3 [Michel Dänzer]
* Use AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED instead of a new flag
   (Christian König)
* Explicitly mention amdgpu_bo_fault_reserve_notify in amdgpu_bo_move

Suggested-by: Michel Dänzer 
Signed-off-by: John Brooks 
Signed-off-by: Michel Dänzer 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 20 ++--
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  9 +
  2 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index e429829ae93d..93601fbea695 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -432,6 +432,10 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
  
  	trace_amdgpu_bo_create(bo);
  
+	/* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */

+   if (type == ttm_bo_type_device)
+   bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+
return 0;
  
  fail_unreserve:

@@ -945,13 +949,17 @@ int amdgpu_bo_fault_reserve_notify(struct 
ttm_buffer_object *bo)
  {
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct amdgpu_bo *abo;
-   unsigned long offset, size, lpfn;
-   int i, r;
+   unsigned long offset, size;
+   int r;
  
  	if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))

return 0;
  
  	abo = container_of(bo, struct amdgpu_bo, tbo);

+
+   /* Remember that this BO was accessed by the CPU */
+   abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+
if (bo->mem.mem_type != TTM_PL_VRAM)
return 0;
  
@@ -967,14 +975,6 @@ int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)

/* hurrah the memory is not visible ! */
atomic64_inc(>num_vram_cpu_page_faults);
amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
-   lpfn =  adev->mc.visible_vram_size >> PAGE_SHIFT;
-   for (i = 0; i < abo->placement.num_placement; i++) {
-   /* Force into visible VRAM */
-   if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
-   (!abo->placements[i].lpfn ||
-abo->placements[i].lpfn > lpfn))
-   abo->placements[i].lpfn = lpfn;
-   }
r = ttm_bo_validate(bo, >placement, false, false);
if (unlikely(r == -ENOMEM)) {
amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 9d4861aea18a..58576375b91c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -493,6 +493,15 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo,
}
}
  
+	if (bo->type == ttm_bo_type_device &&

+   new_mem->mem_type == TTM_PL_VRAM &&
+   old_mem->mem_type != TTM_PL_VRAM) {
+   /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
+* accesses the BO after it's moved.
+*/
+   abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+   }
+
/* update statistics */
atomic64_add((u64)bo->num_pages << PAGE_SHIFT, >num_bytes_moved);
return 0;



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH v3 2/5] drm/amdgpu: Throttle visible VRAM moves separately

[Christian König]

Am 06.07.2017 um 12:51 schrieb Michel Dänzer:

From: John Brooks 

The BO move throttling code is designed to allow VRAM to fill quickly if it
is relatively empty. However, this does not take into account situations
where the visible VRAM is smaller than total VRAM, and total VRAM may not
be close to full but the visible VRAM segment is under pressure. In such
situations, visible VRAM would experience unrestricted swapping and
performance would drop.

Add a separate counter specifically for moves involving visible VRAM, and
check it before moving BOs there.

v2: Only perform calculations for separate counter if visible VRAM is
 smaller than total VRAM. (Michel Dänzer)
v3: [Michel Dänzer]
* Use BO's location rather than the AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
   flag to determine whether to account a move for visible VRAM in most
   cases.
* Use a single

if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {

   block in amdgpu_cs_get_threshold_for_moves.

Fixes: 95844d20ae02 (drm/amdgpu: throttle buffer migrations at CS using a fixed 
MBps limit (v2))
Signed-off-by: John Brooks 
Signed-off-by: Michel Dänzer 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  6 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 92 --
  drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 12 +++-
  3 files changed, 87 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index b95c1074d42c..463d6c241157 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1162,7 +1162,9 @@ struct amdgpu_cs_parser {
struct list_headvalidated;
struct dma_fence*fence;
uint64_tbytes_moved_threshold;
+   uint64_tbytes_moved_vis_threshold;
uint64_tbytes_moved;
+   uint64_tbytes_moved_vis;
struct amdgpu_bo_list_entry *evictable;
  
  	/* user fence */

@@ -1596,6 +1598,7 @@ struct amdgpu_device {
spinlock_t  lock;
s64 last_update_us;
s64 accum_us; /* accumulated microseconds */
+   s64 accum_us_vis; /* for visible VRAM */
u32 log2_max_MBps;
} mm_stats;
  
@@ -1892,7 +1895,8 @@ void amdgpu_pci_config_reset(struct amdgpu_device *adev);

  bool amdgpu_need_post(struct amdgpu_device *adev);
  void amdgpu_update_display_priority(struct amdgpu_device *adev);
  
-void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes);

+void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
+ u64 num_vis_bytes);
  void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
  bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
  int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 82131d70a06b..44ec11d4d733 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -220,10 +220,11 @@ static s64 bytes_to_us(struct amdgpu_device *adev, u64 
bytes)
   * ticks. The accumulated microseconds (us) are converted to bytes and
   * returned.
   */
-static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
+static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
+ u64 *max_bytes,
+ u64 *max_vis_bytes)
  {
s64 time_us, increment_us;
-   u64 max_bytes;
u64 free_vram, total_vram, used_vram;
  
  	/* Allow a maximum of 200 accumulated ms. This is basically per-IB

@@ -235,8 +236,11 @@ static u64 amdgpu_cs_get_threshold_for_moves(struct 
amdgpu_device *adev)
 */
const s64 us_upper_bound = 20;
  
-	if (!adev->mm_stats.log2_max_MBps)

-   return 0;
+   if (!adev->mm_stats.log2_max_MBps) {
+   *max_bytes = 0;
+   *max_vis_bytes = 0;
+   return;
+   }
  
  	total_vram = adev->mc.real_vram_size - adev->vram_pin_size;

used_vram = atomic64_read(>vram_usage);
@@ -277,23 +281,45 @@ static u64 amdgpu_cs_get_threshold_for_moves(struct 
amdgpu_device *adev)
adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
}
  
-	/* This returns 0 if the driver is in debt to disallow (optional)

+   /* This is set to 0 if the driver is in debt to disallow (optional)
 * buffer moves.
 */
-   max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
+   

[PATCH v2 1/5] drm/amdgpu: Add vis_vramlimit module parameter

[Michel Dänzer]

From: John Brooks 

Allow specifying a limit on visible VRAM via a module parameter. This is
helpful for testing performance under visible VRAM pressure.

v2: Add cast to 64-bit (Christian König)

Signed-off-by: John Brooks 
Reviewed-by: Michel Dänzer 
Reviewed-by: Christian König 
Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 
 3 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8b4e8ed9e9dc..b95c1074d42c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -75,6 +75,7 @@
  */
 extern int amdgpu_modeset;
 extern int amdgpu_vram_limit;
+extern int amdgpu_vis_vram_limit;
 extern int amdgpu_gart_size;
 extern int amdgpu_moverate;
 extern int amdgpu_benchmarking;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 271c9d528af6..72ff7223447e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -74,6 +74,7 @@
 #define KMS_DRIVER_PATCHLEVEL  0
 
 int amdgpu_vram_limit = 0;
+int amdgpu_vis_vram_limit = 0;
 int amdgpu_gart_size = -1; /* auto */
 int amdgpu_moverate = -1; /* auto */
 int amdgpu_benchmarking = 0;
@@ -121,6 +122,9 @@ int amdgpu_lbpw = -1;
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
 
+MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in 
megabytes");
+module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
+
 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 
64, etc., -1 = auto)");
 module_param_named(gartsize, amdgpu_gart_size, int, 0600);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index a81c4e5e9f6b..9d4861aea18a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1092,6 +1092,7 @@ static struct ttm_bo_driver amdgpu_bo_driver = {
 int amdgpu_ttm_init(struct amdgpu_device *adev)
 {
int r;
+   u64 vis_vram_limit;
 
r = amdgpu_ttm_global_init(adev);
if (r) {
@@ -1115,6 +1116,13 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
DRM_ERROR("Failed initializing VRAM heap.\n");
return r;
}
+
+   /* Reduce size of CPU-visible VRAM if requested */
+   vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
+   if (amdgpu_vis_vram_limit > 0 &&
+   vis_vram_limit <= adev->mc.visible_vram_size)
+   adev->mc.visible_vram_size = vis_vram_limit;
+
/* Change the size here instead of the init above so only lpfn is 
affected */
amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 
-- 
2.13.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v2 5/5] drm/amdgpu: Try evicting from CPU visible to invisible VRAM first

[Michel Dänzer]

From: Michel Dänzer 

This gives BOs which haven't been accessed by the CPU since they were
moved to visible VRAM another chance to stay in VRAM when another BO
needs to go to visible VRAM.

This should allow BOs to stay in VRAM longer in some cases.

v2:
* Only do this for BOs which don't have the
  AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED flag set.

Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 28 
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 58576375b91c..2a9906dd7637 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -207,7 +207,35 @@ static void amdgpu_evict_flags(struct ttm_buffer_object 
*bo,
adev->mman.buffer_funcs_ring &&
adev->mman.buffer_funcs_ring->ready == false) {
amdgpu_ttm_placement_from_domain(abo, 
AMDGPU_GEM_DOMAIN_CPU);
+   } else if (adev->mc.visible_vram_size < adev->mc.real_vram_size 
&&
+  !(abo->flags & 
AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
+   unsigned fpfn = adev->mc.visible_vram_size >> 
PAGE_SHIFT;
+   struct drm_mm_node *node = bo->mem.mm_node;
+   unsigned long pages_left;
+
+   for (pages_left = bo->mem.num_pages;
+pages_left;
+pages_left -= node->size, node++) {
+   if (node->start < fpfn)
+   break;
+   }
+
+   if (!pages_left)
+   goto gtt;
+
+   /* Try evicting to the CPU inaccessible part of VRAM
+* first, but only set GTT as busy placement, so this
+* BO will be evicted to GTT rather than causing other
+* BOs to be evicted from VRAM
+*/
+   amdgpu_ttm_placement_from_domain(abo, 
AMDGPU_GEM_DOMAIN_VRAM |
+AMDGPU_GEM_DOMAIN_GTT);
+   abo->placements[0].fpfn = fpfn;
+   abo->placements[0].lpfn = 0;
+   abo->placement.busy_placement = >placements[1];
+   abo->placement.num_busy_placement = 1;
} else {
+gtt:
amdgpu_ttm_placement_from_domain(abo, 
AMDGPU_GEM_DOMAIN_GTT);
for (i = 0; i < abo->placement.num_placement; ++i) {
if (!(abo->placements[i].flags &
-- 
2.13.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 4/5] drm/amdgpu: Don't force BOs into visible VRAM for page faults

[Michel Dänzer]

From: John Brooks 

There is no need for page faults to force BOs into visible VRAM if it's
full, and the time it takes to do so is great enough to cause noticeable
stuttering. Add GTT as a possible placement so that if visible VRAM is
full, page faults move BOs to GTT instead of evicting other BOs from VRAM.

Suggested-by: Michel Dänzer 
Signed-off-by: John Brooks 
Reviewed-by: Michel Dänzer 
Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 93601fbea695..6e24339ecc46 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -974,18 +974,21 @@ int amdgpu_bo_fault_reserve_notify(struct 
ttm_buffer_object *bo)
 
/* hurrah the memory is not visible ! */
atomic64_inc(>num_vram_cpu_page_faults);
-   amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
+   amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
+AMDGPU_GEM_DOMAIN_GTT);
+
+   /* Avoid costly evictions; only set GTT as a busy placement */
+   abo->placement.num_busy_placement = 1;
+   abo->placement.busy_placement = >placements[1];
+
r = ttm_bo_validate(bo, >placement, false, false);
-   if (unlikely(r == -ENOMEM)) {
-   amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
-   return ttm_bo_validate(bo, >placement, false, false);
-   } else if (unlikely(r != 0)) {
+   if (unlikely(r != 0))
return r;
-   }
 
offset = bo->mem.start << PAGE_SHIFT;
/* this should never happen */
-   if ((offset + size) > adev->mc.visible_vram_size)
+   if (bo->mem.mem_type == TTM_PL_VRAM &&
+   (offset + size) > adev->mc.visible_vram_size)
return -EINVAL;
 
return 0;
-- 
2.13.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH 0/5] amdgpu: Visible VRAM Management Improvements, next take

[Michel Dänzer]

From: Michel Dänzer 

This is a rearrangement of some patches of John's, with some improvements
of mine, and a patch of mine, rebased on current amd-staging-4.11.
Details about changes in the individual patches.

John Brooks (4):
  drm/amdgpu: Add vis_vramlimit module parameter
  drm/amdgpu: Throttle visible VRAM moves separately
  drm/amdgpu: Set/clear CPU_ACCESS flag on page fault and move to VRAM
  drm/amdgpu: Don't force BOs into visible VRAM for page faults

Michel Dänzer (1):
  drm/amdgpu: Try evicting from CPU visible to invisible VRAM first

 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  7 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 92 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|  4 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 49 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 45 +++
 5 files changed, 157 insertions(+), 40 deletions(-)

-- 
2.13.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH v3 3/5] drm/amdgpu: Set/clear CPU_ACCESS flag on page fault and move to VRAM

[Michel Dänzer]

From: John Brooks 

When a BO is moved to VRAM, clear AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED.
This allows it to potentially later move to invisible VRAM if the CPU
does not access it again.

Setting the CPU_ACCESS flag in amdgpu_bo_fault_reserve_notify() also means
that we can remove the loop to restrict lpfn to the end of visible VRAM,
because amdgpu_ttm_placement_init() will do it for us.

v3 [Michel Dänzer]
* Use AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED instead of a new flag
  (Christian König)
* Explicitly mention amdgpu_bo_fault_reserve_notify in amdgpu_bo_move

Suggested-by: Michel Dänzer 
Signed-off-by: John Brooks 
Signed-off-by: Michel Dänzer 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 20 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|  9 +
 2 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index e429829ae93d..93601fbea695 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -432,6 +432,10 @@ int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
 
trace_amdgpu_bo_create(bo);
 
+   /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
+   if (type == ttm_bo_type_device)
+   bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+
return 0;
 
 fail_unreserve:
@@ -945,13 +949,17 @@ int amdgpu_bo_fault_reserve_notify(struct 
ttm_buffer_object *bo)
 {
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct amdgpu_bo *abo;
-   unsigned long offset, size, lpfn;
-   int i, r;
+   unsigned long offset, size;
+   int r;
 
if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
return 0;
 
abo = container_of(bo, struct amdgpu_bo, tbo);
+
+   /* Remember that this BO was accessed by the CPU */
+   abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+
if (bo->mem.mem_type != TTM_PL_VRAM)
return 0;
 
@@ -967,14 +975,6 @@ int amdgpu_bo_fault_reserve_notify(struct 
ttm_buffer_object *bo)
/* hurrah the memory is not visible ! */
atomic64_inc(>num_vram_cpu_page_faults);
amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM);
-   lpfn =  adev->mc.visible_vram_size >> PAGE_SHIFT;
-   for (i = 0; i < abo->placement.num_placement; i++) {
-   /* Force into visible VRAM */
-   if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
-   (!abo->placements[i].lpfn ||
-abo->placements[i].lpfn > lpfn))
-   abo->placements[i].lpfn = lpfn;
-   }
r = ttm_bo_validate(bo, >placement, false, false);
if (unlikely(r == -ENOMEM)) {
amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 9d4861aea18a..58576375b91c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -493,6 +493,15 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo,
}
}
 
+   if (bo->type == ttm_bo_type_device &&
+   new_mem->mem_type == TTM_PL_VRAM &&
+   old_mem->mem_type != TTM_PL_VRAM) {
+   /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
+* accesses the BO after it's moved.
+*/
+   abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+   }
+
/* update statistics */
atomic64_add((u64)bo->num_pages << PAGE_SHIFT, >num_bytes_moved);
return 0;
-- 
2.13.2

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH libdrm 2/2] radeon: use asic id table to get chipset name

[Emil Velikov]

On 5 July 2017 at 22:31, Li, Samuel  wrote:
>>  - above all, as-is make check will fail
> Right, I did not check that.
>
>>  - keeping the radeon API symmetrical to the amdgpu one would a good idea
> The issue is Radeon does not have a struct similar to amdgpu_device_handle.
Attach it to analogous primitive?

> I think the current radeon API is simpler. Maybe a follow up change can 
> change amdgpu's API similar to radeon.
>
Exposing 3 entry points instead of 1 is _not_simpler. Also you cannot
change the existing API, since it also breaks the ABI.
Leading to crash/cause memory corruption when using existing binaries.

>>  - is adding yet another header really justified?
> radeon_asic_id.h? That is going to be used by ddx/mesa.
>
Where it's used is orthogonal. You don't need a separate _public_
header for nearly every entry point ;-)

Thanks
Emil
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amd/powerplay: fixed wrong data type declaration for ppfeaturemask

[Christian König]

Reviewed-by: Christian König .

Am 06.07.2017 um 04:38 schrieb Zhu, Rex:

Reviewed-by: Rex Zhu 

Best Regards
Rex
-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Evan 
Quan
Sent: Thursday, July 06, 2017 10:02 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan
Subject: [PATCH] drm/amd/powerplay: fixed wrong data type declaration for 
ppfeaturemask

Change-Id: Icbe9fa02e653edf365880fc03089e5cf01716d52
Signed-off-by: Evan Quan 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 9644dd1..271c9d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -203,7 +203,7 @@ MODULE_PARM_DESC(sched_hw_submission, "the max number of HW 
submissions (default  module_param_named(sched_hw_submission, 
amdgpu_sched_hw_submission, int, 0444);
  
  MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); -module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, int, 0444);

+module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
  
  MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))");  module_param_named(no_evict, amdgpu_no_evict, int, 0444);

--
2.7.4

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 1/3] drm/amdgpu/atom: fix atom_fw check

[Christian König]

Am 05.07.2017 um 21:51 schrieb Alex Deucher:

Not all vbios images seem to set the version appropriately.
Switch the check based on asic type instead.

Signed-off-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 15 +--
  1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index 365e735..ea3a250 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -86,19 +86,6 @@ static bool check_atom_bios(uint8_t *bios, size_t size)
return false;
  }
  
-static bool is_atom_fw(uint8_t *bios)

-{
-   uint16_t bios_header_start = bios[0x48] | (bios[0x49] << 8);
-   uint8_t frev = bios[bios_header_start + 2];
-   uint8_t crev = bios[bios_header_start + 3];
-
-   if ((frev < 3) ||
-   ((frev == 3) && (crev < 3)))
-   return false;
-
-   return true;
-}
-
  /* If you boot an IGP board with a discrete card as the primary,
   * the IGP rom is not accessible via the rom bar as the IGP rom is
   * part of the system bios.  On boot, the system bios puts a
@@ -455,6 +442,6 @@ bool amdgpu_get_bios(struct amdgpu_device *adev)
return false;
  
  success:

-   adev->is_atom_fw = is_atom_fw(adev->bios);
+   adev->is_atom_fw = (adev->asic_type >= CHIP_VEGA10) ? true : false;


The "? true : false" part looks a bit superfluous.

Apart from that the series is Acked-by: Christian König 
.


Regards,
Christian.


return true;
  }



___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH 4/5] drm/amdgpu: check scratch registers to see if we need post

[Zhang, Jerry (Junwei)]

On 07/01/2017 05:32 AM, Alex Deucher wrote:

Rather than checking the CONGIG_MEMSIZE register as that may
not be reliable on some APUs.

Signed-off-by: Alex Deucher 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +-
  1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 63f4bed..9d08f53 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -716,20 +716,12 @@ void amdgpu_gtt_location(struct amdgpu_device *adev, 
struct amdgpu_mc *mc)
   */
  bool amdgpu_need_post(struct amdgpu_device *adev)
  {
-   uint32_t reg;
-
if (adev->has_hw_reset) {
adev->has_hw_reset = false;
return true;
}
-   /* then check MEM_SIZE, in case the crtcs are off */
-   reg = amdgpu_asic_get_config_memsize(adev);


Do we still need it for SI?

Jerry


-
-   if ((reg != 0) && (reg != 0x))
-   return false;
-
-   return true;

+   return amdgpu_atombios_scratch_need_asic_init(adev);
  }

  static bool amdgpu_vpost_needed(struct amdgpu_device *adev)


___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx