RE: [PATCH] drm/amd/amdgpu: fix over-bound accessing in amdgpu_cs_wait_any_fence

[Zhou, David(ChunMing)]

Reviewed-by: Chunming Zhou 

-Original Message-
From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf Of Roger 
He
Sent: Friday, November 17, 2017 2:09 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou, David(ChunMing) ; He, Roger ; 
Koenig, Christian ; Qu, Jim 
Subject: [PATCH] drm/amd/amdgpu: fix over-bound accessing in 
amdgpu_cs_wait_any_fence

fix the following issue:

Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.712090] Oops:  [#2] SMP Nov 
15 17:40:25 jenkins-MS-7984 kernel: [  146.712481] Modules linked in: 
amdgpu(OE) chash ttm(OE) drm_kms_helper(OE) drm(OE) i2c_algo_bit fb_sys_fops 
syscopyarea sysfillrect sysimgblt intel_rapl snd_hda_codec_realtek 
snd_hda_codec_generic x86_pkg_temp_thermal intel_powerclamp snd_hda_codec_hdmi 
coretemp snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm kvm 
snd_seq_midi snd_seq_midi_event snd_rawmidi snd_seq irqbypass crct10dif_pclmul 
crc32_pclmul ghash_clmulni_intel pcbc snd_seq_device snd_timer aesni_intel snd 
mei_me mei aes_x86_64 crypto_simd serio_raw eeepc_wmi glue_helper asus_wmi 
sparse_keymap cryptd soundcore shpchp wmi_bmof lpc_ich mac_hid tpm_infineon 
nfsd auth_rpcgss nfs_acl lockd parport_pc grace ppdev sunrpc lp parport autofs4 
hid_generic usbhid ahci mxm_wmi r8169 libahci hid mii wmi video
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715120] CPU: 1 PID: 1330 Comm: 
deqp-vk Tainted: G  DOE   4.13.0-custom #1
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715879] Hardware name: ASUS All 
Series/Z87-A, BIOS 1802 01/28/2014 Nov 15 17:40:25 jenkins-MS-7984 kernel: [  
146.716658] task: 9b7115728000 task.stack: b178016e Nov 15 17:40:25 
jenkins-MS-7984 kernel: [  146.717494] RIP: 
0010:amdgpu_cs_wait_fences_ioctl+0x20b/0x2e0 [amdgpu] Nov 15 17:40:25 
jenkins-MS-7984 kernel: [  146.718312] RSP: 0018:b178016e3cb0 EFLAGS: 
00010246 Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.719270] RAX: 
 RBX: b178016e3d90 RCX:  Nov 15 17:40:25 
jenkins-MS-7984 kernel: [  146.720247] RDX:  RSI: 
0001 RDI: 9b7116a1d8a8 Nov 15 17:40:25 jenkins-MS-7984 kernel: 
[  146.721246] RBP: b178016e3d00 R08:  R09: 
 Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.722262] R10: 
ed00 R11: b178016e3d90 R12: 9b7116a1d8a8 Nov 15 17:40:25 
jenkins-MS-7984 kernel: [  146.723299] R13: 9b7000707020 R14: 
0001 R15:  Nov 15 17:40:25 jenkins-MS-7984 kernel: 
[  146.724358] FS:  7f89f3af4740() GS:9b712ec8() 
knlGS: Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.725447] 
CS:  0010 DS:  ES:  CR0: 80050033 Nov 15 17:40:25 
jenkins-MS-7984 kernel: [  146.726550] CR2: 9b7916a1d8a0 CR3: 
00022042e000 CR4: 001406e0 Nov 15 17:40:25 jenkins-MS-7984 kernel: 
[  146.727687] DR0:  DR1:  DR2: 
 Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.728837] DR3: 
 DR6: fffe0ff0 DR7: 0400 Nov 15 17:40:25 
jenkins-MS-7984 kernel: [  146.729992] Call Trace:
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.731193]  ? 
amdgpu_cs_fence_to_handle_ioctl+0x1c0/0x1c0 [amdgpu] Nov 15 17:40:25 
jenkins-MS-7984 kernel: [  146.732406]  drm_ioctl_kernel+0x69/0xb0 [drm] Nov 15 
17:40:25 jenkins-MS-7984 kernel: [  146.733626]  drm_ioctl+0x2d2/0x390 [drm] 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.734883]  ? 
amdgpu_cs_fence_to_handle_ioctl+0x1c0/0x1c0 [amdgpu] Nov 15 17:40:25 
jenkins-MS-7984 kernel: [  146.736135]  ? __do_fault+0x1e/0x70 Nov 15 17:40:25 
jenkins-MS-7984 kernel: [  146.737392]  ? __handle_mm_fault+0x8ae/0x10f0 Nov 15 
17:40:25 jenkins-MS-7984 kernel: [  146.738665]  ? apparmor_mmap_file+0x18/0x20 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.739980]  
amdgpu_drm_ioctl+0x4c/0x80 [amdgpu] Nov 15 17:40:25 jenkins-MS-7984 kernel: [  
146.741277]  do_vfs_ioctl+0x96/0x5b0 Nov 15 17:40:25 jenkins-MS-7984 kernel: [  
146.742582]  ? handle_mm_fault+0xd3/0x1f0 Nov 15 17:40:25 jenkins-MS-7984 
kernel: [  146.743899]  ? sched_clock+0x9/0x10 Nov 15 17:40:25 jenkins-MS-7984 
kernel: [  146.745224]  SyS_ioctl+0x79/0x90 Nov 15 17:40:25 jenkins-MS-7984 
kernel: [  146.746553]  ? vtime_user_exit+0x29/0x70 Nov 15 17:40:25 
jenkins-MS-7984 kernel: [  146.747897]  do_syscall_64+0x6e/0x160 Nov 15 
17:40:25 jenkins-MS-7984 kernel: [  146.749247]  
entry_SYSCALL64_slow_path+0x25/0x25
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.750614] RIP: 0033:0x7f89f1fdff07 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.751987] RSP: 
002b:7ffd4c6262d8 EFLAGS: 0202 ORIG_RAX: 0010 Nov 15 
17:40:25 jenkins-MS-7984 kernel: [  146.753407] RAX: ffda RBX: 
0001 RCX: 7f89f1fdff07 Nov 15 17:40:25 jenkins-MS-7984 kernel: 
[  146.754847] RDX: 

RE: [PATCH] drm/amdgpu: fix rmmod KCQ disable failed error

[Zhu, Rex]

Reviewed-by: Rex Zhu 

Best Regards
Rex
-Original Message-
From: Wang Hongcheng [mailto:annie.w...@amd.com] 
Sent: Friday, November 17, 2017 2:24 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex; Wang, Annie
Subject: [PATCH] drm/amdgpu: fix rmmod KCQ disable failed error

If  gfx_v8_0_hw_fini is called after amdgpu_ucode_fini_bo, we will hit KCQ 
disabled failed. Let amdgpu_ucode_fini_bo run after gfx_v8_0_hw_fini.

BUG: SWDEV-135547
Signed-off-by: Wang Hongcheng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 3 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c | 3 ---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   | 2 --
 3 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3dcdee5..ad2ef41 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1892,6 +1892,9 @@ static int amdgpu_fini(struct amdgpu_device *adev)
adev->ip_blocks[i].status.hw = false;
}
 
+   if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
+   amdgpu_ucode_fini_bo(adev);
+
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.sw)
continue;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index 5f5aa5f..033fba2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -164,9 +164,6 @@ static int amdgpu_pp_hw_fini(void *handle)
ret = adev->powerplay.ip_funcs->hw_fini(
adev->powerplay.pp_handle);
 
-   if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
-   amdgpu_ucode_fini_bo(adev);
-
return ret;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 2157d45..f95a200 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -446,8 +446,6 @@ static int psp_hw_fini(void *handle)
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
return 0;
 
-   amdgpu_ucode_fini_bo(adev);
-
psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 
amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, >tmr_buf);
--
2.7.4

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RE: 答复: [PATCH] drm/amd/amdgpu: fix over-bound accessing in amdgpu_cs_wait_any_fence

[Deng, Emily]

Hi Roger,
Not the same. When the fence already signaled, the array[first] will be 
NULL.

Best Wishes,
Emily Deng



> -Original Message-
> From: He, Roger
> Sent: Friday, November 17, 2017 1:32 PM
> To: Zhou, David(ChunMing) ; Qu, Jim
> ; amd-gfx@lists.freedesktop.org
> Cc: Koenig, Christian ; Deng, Emily
> 
> Subject: RE: 答复: [PATCH] drm/amd/amdgpu: fix over-bound accessing in
> amdgpu_cs_wait_any_fence
> 
> Theoretically, if first < fence_count, array[first] will not be NULL.
> 
> Hi Emily:
> 
> do you remember the  issue you fixed has same error log?
> 
> 
> Thanks
> Roger(Hongbo.He)
> -Original Message-
> From: Zhou, David(ChunMing)
> Sent: Friday, November 17, 2017 1:24 PM
> To: Qu, Jim ; He, Roger ; amd-
> g...@lists.freedesktop.org
> Cc: Zhou, David(ChunMing) ; Koenig, Christian
> 
> Subject: Re: 答复: [PATCH] drm/amd/amdgpu: fix over-bound accessing in
> amdgpu_cs_wait_any_fence
> 
> Yes,  As Jim pointed out, you lacks the array[] checking.
> 
> you can just change to if (first < fence_count && array[first]), otherwise 
> it's a
> good fix for regression.
> 
> 
> Regards,
> 
> David Zhou
> 
> 
> On 2017年11月17日 13:16, Qu, Jim wrote:
> > Hi Roger:
> >
> > -   if (array[first])
> > -   r = array[first]->error;
> > -   else
> > +   if (first == ~0)
> >  r = 0;
> > +   else
> > +   r = array[first]->error;
> >
> > // The patch looks like change original logic that miss to check 
> > array[first].
> >
> > Thanks
> > JimQu
> >
> > 
> > 发件人: amd-gfx  代表 Roger
> He
> > 
> > 发送时间: 2017年11月17日 13:04
> > 收件人: amd-gfx@lists.freedesktop.org
> > 抄送: Zhou, David(ChunMing); He, Roger; Koenig, Christian
> > 主题: [PATCH] drm/amd/amdgpu: fix over-bound accessing in
> > amdgpu_cs_wait_any_fence
> >
> > fix the following issue:
> >
> > Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.712090] Oops:  [#2]
> > SMP Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.712481] Modules
> linked in: amdgpu(OE) chash ttm(OE) drm_kms_helper(OE) drm(OE)
> i2c_algo_bit fb_sys_fops syscopyarea sysfillrect sysimgblt intel_rapl
> snd_hda_codec_realtek snd_hda_codec_generic x86_pkg_temp_thermal
> intel_powerclamp snd_hda_codec_hdmi coretemp snd_hda_intel
> snd_hda_codec snd_hda_core snd_hwdep snd_pcm kvm snd_seq_midi
> snd_seq_midi_event snd_rawmidi snd_seq irqbypass crct10dif_pclmul
> crc32_pclmul ghash_clmulni_intel pcbc snd_seq_device snd_timer aesni_intel
> snd mei_me mei aes_x86_64 crypto_simd serio_raw eeepc_wmi glue_helper
> asus_wmi sparse_keymap cryptd soundcore shpchp wmi_bmof lpc_ich
> mac_hid tpm_infineon nfsd auth_rpcgss nfs_acl lockd parport_pc grace
> ppdev sunrpc lp parport autofs4 hid_generic usbhid ahci mxm_wmi r8169
> libahci hid mii wmi video
> > Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715120] CPU: 1 PID: 1330
> Comm: deqp-vk Tainted: G  DOE   4.13.0-custom #1
> > Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715879] Hardware name:
> > ASUS All Series/Z87-A, BIOS 1802 01/28/2014 Nov 15 17:40:25
> > jenkins-MS-7984 kernel: [  146.716658] task: 9b7115728000
> > task.stack: b178016e Nov 15 17:40:25 jenkins-MS-7984 kernel: [
> > 146.717494] RIP: 0010:amdgpu_cs_wait_fences_ioctl+0x20b/0x2e0
> [amdgpu]
> > Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.718312] RSP:
> > 0018:b178016e3cb0 EFLAGS: 00010246 Nov 15 17:40:25 jenkins-MS-
> 7984
> > kernel: [  146.719270] RAX:  RBX: b178016e3d90
> > RCX:  Nov 15 17:40:25 jenkins-MS-7984 kernel: [
> > 146.720247] RDX:  RSI: 0001 RDI:
> > 9b7116a1d8a8 Nov 15 17:40:25 jenkins-MS-7984 kernel: [
> > 146.721246] RBP: b178016e3d00 R08:  R09:
> >  Nov 15 17:40:25 jenkins-MS-7984 kernel: [
> > 146.722262] R10: ed00 R11: b178016e3d90 R12:
> > 9b7116a1d8a8 Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.723299]
> R13: 9b7000707020 R14: 0001 R15: 
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.724358] FS:
> 7f89f3af4740() GS:9b712ec8()
> knlGS: Nov 15 17:40:25 jenkins-MS-7984 kernel:
> [  146.725447] CS:  0010 DS:  ES:  CR0: 80050033 Nov 15
> 17:40:25 jenkins-MS-7984 kernel: [  146.726550] CR2: 9b7916a1d8a0 CR3:
> 00022042e000 CR4: 001406e0 Nov 15 17:40:25 jenkins-MS-
> 7984 kernel: [  146.727687] DR0:  DR1:
>  DR2:  Nov 15 17:40:25 jenkins-MS-
> 7984 kernel: [  146.728837] DR3:  DR6: fffe0ff0
> DR7: 0400 Nov 15 17:40:25 jenkins-MS-7984 kernel:
> [  146.729992] Call Trace:
> > Nov 15 17:40:25 jenkins-MS-7984 kernel: [  

[PATCH] drm/amd/amdgpu: fix over-bound accessing in amdgpu_cs_wait_any_fence

[Roger He]

fix the following issue:

Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.712090] Oops:  [#2] SMP
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.712481] Modules linked in: 
amdgpu(OE) chash ttm(OE) drm_kms_helper(OE) drm(OE) i2c_algo_bit fb_sys_fops 
syscopyarea sysfillrect sysimgblt intel_rapl snd_hda_codec_realtek 
snd_hda_codec_generic x86_pkg_temp_thermal intel_powerclamp snd_hda_codec_hdmi 
coretemp snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm kvm 
snd_seq_midi snd_seq_midi_event snd_rawmidi snd_seq irqbypass crct10dif_pclmul 
crc32_pclmul ghash_clmulni_intel pcbc snd_seq_device snd_timer aesni_intel snd 
mei_me mei aes_x86_64 crypto_simd serio_raw eeepc_wmi glue_helper asus_wmi 
sparse_keymap cryptd soundcore shpchp wmi_bmof lpc_ich mac_hid tpm_infineon 
nfsd auth_rpcgss nfs_acl lockd parport_pc grace ppdev sunrpc lp parport autofs4 
hid_generic usbhid ahci mxm_wmi r8169 libahci hid mii wmi video
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715120] CPU: 1 PID: 1330 Comm: 
deqp-vk Tainted: G  DOE   4.13.0-custom #1
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715879] Hardware name: ASUS All 
Series/Z87-A, BIOS 1802 01/28/2014
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.716658] task: 9b7115728000 
task.stack: b178016e
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.717494] RIP: 
0010:amdgpu_cs_wait_fences_ioctl+0x20b/0x2e0 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.718312] RSP: 
0018:b178016e3cb0 EFLAGS: 00010246
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.719270] RAX:  
RBX: b178016e3d90 RCX: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.720247] RDX:  
RSI: 0001 RDI: 9b7116a1d8a8
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.721246] RBP: b178016e3d00 
R08:  R09: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.722262] R10: ed00 
R11: b178016e3d90 R12: 9b7116a1d8a8
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.723299] R13: 9b7000707020 
R14: 0001 R15: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.724358] FS:  
7f89f3af4740() GS:9b712ec8() knlGS:
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.725447] CS:  0010 DS:  ES: 
 CR0: 80050033
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.726550] CR2: 9b7916a1d8a0 
CR3: 00022042e000 CR4: 001406e0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.727687] DR0:  
DR1:  DR2: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.728837] DR3:  
DR6: fffe0ff0 DR7: 0400
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.729992] Call Trace:
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.731193]  ? 
amdgpu_cs_fence_to_handle_ioctl+0x1c0/0x1c0 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.732406]  
drm_ioctl_kernel+0x69/0xb0 [drm]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.733626]  drm_ioctl+0x2d2/0x390 
[drm]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.734883]  ? 
amdgpu_cs_fence_to_handle_ioctl+0x1c0/0x1c0 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.736135]  ? __do_fault+0x1e/0x70
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.737392]  ? 
__handle_mm_fault+0x8ae/0x10f0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.738665]  ? 
apparmor_mmap_file+0x18/0x20
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.739980]  
amdgpu_drm_ioctl+0x4c/0x80 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.741277]  do_vfs_ioctl+0x96/0x5b0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.742582]  ? 
handle_mm_fault+0xd3/0x1f0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.743899]  ? sched_clock+0x9/0x10
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.745224]  SyS_ioctl+0x79/0x90
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.746553]  ? 
vtime_user_exit+0x29/0x70
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.747897]  do_syscall_64+0x6e/0x160
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.749247]  
entry_SYSCALL64_slow_path+0x25/0x25
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.750614] RIP: 0033:0x7f89f1fdff07
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.751987] RSP: 
002b:7ffd4c6262d8 EFLAGS: 0202 ORIG_RAX: 0010
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.753407] RAX: ffda 
RBX: 0001 RCX: 7f89f1fdff07
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.754847] RDX: 7ffd4c6263a0 
RSI: c0186452 RDI: 0005
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.756302] RBP: 7ffd4c626310 
R08: 0001 R09: 7ffd4c62642c
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.757768] R10: edf2 
R11: 0202 R12: 7ffd4c6264b0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.759243] R13: 000186a0 
R14:  R15: 7ffd4c626700
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.760725] Code: ff ff ff 

Re: [PATCH 1/2] drm/amdgpu:fix virtual dce bug

[Jan Vesely]

On Fri, 2017-11-17 at 04:26 +, Liu, Monk wrote:
> I think it's already clear enough 

nice. what a friendly response. good job!

"fix a bug" is definitely not descriptive of the change, and the commit
message does not even parse as a sentence.


Jan

> 
> -Original Message-
> From: Jan Vesely [mailto:jv...@scarletmail.rutgers.edu] On Behalf Of Jan 
> Vesely
> Sent: 2017年11月17日 0:40
> To: Liu, Monk ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH 1/2] drm/amdgpu:fix virtual dce bug
> 
> On Thu, 2017-11-16 at 11:14 +0800, Monk Liu wrote:
> > this fix the issue that access memory after freed after driver 
> > unloaded.
> 
> can you please change the patch subject and commit message to something more 
> descriptive?
> 
> Jan
> 
> > 
> > Change-Id: I64e2488c18f5dc044b57c74567785da21fc028da
> > Signed-off-by: Monk Liu 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
> > b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> > index a8829af..39460eb 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> > @@ -437,6 +437,8 @@ static int dce_virtual_sw_fini(void *handle)
> > drm_kms_helper_poll_fini(adev->ddev);
> >  
> > drm_mode_config_cleanup(adev->ddev);
> > +   /* clear crtcs pointer to avoid dce irq finish routine access freed 
> > data */
> > +   memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * 
> > +AMDGPU_MAX_CRTCS);
> > adev->mode_info.mode_config_initialized = false;
> > return 0;
> >  }
> > @@ -723,7 +725,7 @@ static void 
> > dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *ad
> > int crtc,
> > enum 
> > amdgpu_interrupt_state state)  {
> > -   if (crtc >= adev->mode_info.num_crtc) {
> > +   if (crtc >= adev->mode_info.num_crtc || 
> > +!adev->mode_info.crtcs[crtc]) {
> > DRM_DEBUG("invalid crtc %d\n", crtc);
> > return;
> > }

-- 
Jan Vesely 

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RE: 答复: [PATCH] drm/amd/amdgpu: fix over-bound accessing in amdgpu_cs_wait_any_fence

[He, Roger]

Theoretically, if first < fence_count, array[first] will not be NULL.

Hi Emily:

do you remember the  issue you fixed has same error log?


Thanks
Roger(Hongbo.He)
-Original Message-
From: Zhou, David(ChunMing) 
Sent: Friday, November 17, 2017 1:24 PM
To: Qu, Jim ; He, Roger ; 
amd-gfx@lists.freedesktop.org
Cc: Zhou, David(ChunMing) ; Koenig, Christian 

Subject: Re: 答复: [PATCH] drm/amd/amdgpu: fix over-bound accessing in 
amdgpu_cs_wait_any_fence

Yes,  As Jim pointed out, you lacks the array[] checking.

you can just change to if (first < fence_count && array[first]), otherwise it's 
a good fix for regression.


Regards,

David Zhou


On 2017年11月17日 13:16, Qu, Jim wrote:
> Hi Roger:
>
> -   if (array[first])
> -   r = array[first]->error;
> -   else
> +   if (first == ~0)
>  r = 0;
> +   else
> +   r = array[first]->error;
>
> // The patch looks like change original logic that miss to check array[first].
>
> Thanks
> JimQu
>
> 
> 发件人: amd-gfx  代表 Roger He 
> 
> 发送时间: 2017年11月17日 13:04
> 收件人: amd-gfx@lists.freedesktop.org
> 抄送: Zhou, David(ChunMing); He, Roger; Koenig, Christian
> 主题: [PATCH] drm/amd/amdgpu: fix over-bound accessing in 
> amdgpu_cs_wait_any_fence
>
> fix the following issue:
>
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.712090] Oops:  [#2] SMP
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.712481] Modules linked in: 
> amdgpu(OE) chash ttm(OE) drm_kms_helper(OE) drm(OE) i2c_algo_bit fb_sys_fops 
> syscopyarea sysfillrect sysimgblt intel_rapl snd_hda_codec_realtek 
> snd_hda_codec_generic x86_pkg_temp_thermal intel_powerclamp 
> snd_hda_codec_hdmi coretemp snd_hda_intel snd_hda_codec snd_hda_core 
> snd_hwdep snd_pcm kvm snd_seq_midi snd_seq_midi_event snd_rawmidi snd_seq 
> irqbypass crct10dif_pclmul crc32_pclmul ghash_clmulni_intel pcbc 
> snd_seq_device snd_timer aesni_intel snd mei_me mei aes_x86_64 crypto_simd 
> serio_raw eeepc_wmi glue_helper asus_wmi sparse_keymap cryptd soundcore 
> shpchp wmi_bmof lpc_ich mac_hid tpm_infineon nfsd auth_rpcgss nfs_acl lockd 
> parport_pc grace ppdev sunrpc lp parport autofs4 hid_generic usbhid ahci 
> mxm_wmi r8169 libahci hid mii wmi video
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715120] CPU: 1 PID: 1330 Comm: 
> deqp-vk Tainted: G  DOE   4.13.0-custom #1
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715879] Hardware name: ASUS 
> All Series/Z87-A, BIOS 1802 01/28/2014
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.716658] task: 9b7115728000 
> task.stack: b178016e
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.717494] RIP: 
> 0010:amdgpu_cs_wait_fences_ioctl+0x20b/0x2e0 [amdgpu]
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.718312] RSP: 
> 0018:b178016e3cb0 EFLAGS: 00010246
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.719270] RAX:  
> RBX: b178016e3d90 RCX: 
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.720247] RDX:  
> RSI: 0001 RDI: 9b7116a1d8a8
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.721246] RBP: b178016e3d00 
> R08:  R09: 
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.722262] R10: ed00 
> R11: b178016e3d90 R12: 9b7116a1d8a8
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.723299] R13: 9b7000707020 
> R14: 0001 R15: 
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.724358] FS:  
> 7f89f3af4740() GS:9b712ec8() knlGS:
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.725447] CS:  0010 DS:  ES: 
>  CR0: 80050033
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.726550] CR2: 9b7916a1d8a0 
> CR3: 00022042e000 CR4: 001406e0
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.727687] DR0:  
> DR1:  DR2: 
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.728837] DR3:  
> DR6: fffe0ff0 DR7: 0400
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.729992] Call Trace:
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.731193]  ? 
> amdgpu_cs_fence_to_handle_ioctl+0x1c0/0x1c0 [amdgpu]
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.732406]  
> drm_ioctl_kernel+0x69/0xb0 [drm]
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.733626]  drm_ioctl+0x2d2/0x390 
> [drm]
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.734883]  ? 
> amdgpu_cs_fence_to_handle_ioctl+0x1c0/0x1c0 [amdgpu]
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.736135]  ? __do_fault+0x1e/0x70
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.737392]  ? 
> __handle_mm_fault+0x8ae/0x10f0
> Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.738665]  ? 
> apparmor_mmap_file+0x18/0x20
> Nov 15 

Re: 答复: [PATCH] drm/amd/amdgpu: fix over-bound accessing in amdgpu_cs_wait_any_fence

[Chunming Zhou]

On 2017年11月17日 13:31, He, Roger wrote:

Theoretically, if first < fence_count, array[first] will not be NULL.

that's what I mean:

   if (first < fence_count && array[first])
   r = array[first]->error;
   else
   r = 0;

Regards,
David Zhou



Hi Emily:

do you remember the  issue you fixed has same error log?


Thanks
Roger(Hongbo.He)
-Original Message-
From: Zhou, David(ChunMing)
Sent: Friday, November 17, 2017 1:24 PM
To: Qu, Jim ; He, Roger ; 
amd-gfx@lists.freedesktop.org
Cc: Zhou, David(ChunMing) ; Koenig, Christian 

Subject: Re: 答复: [PATCH] drm/amd/amdgpu: fix over-bound accessing in 
amdgpu_cs_wait_any_fence

Yes,  As Jim pointed out, you lacks the array[] checking.

you can just change to if (first < fence_count && array[first]), otherwise it's 
a good fix for regression.


Regards,

David Zhou


On 2017年11月17日 13:16, Qu, Jim wrote:

Hi Roger:

-   if (array[first])
-   r = array[first]->error;
-   else
+   if (first == ~0)
  r = 0;
+   else
+   r = array[first]->error;

// The patch looks like change original logic that miss to check array[first].

Thanks
JimQu


发件人: amd-gfx  代表 Roger He 

发送时间: 2017年11月17日 13:04
收件人: amd-gfx@lists.freedesktop.org
抄送: Zhou, David(ChunMing); He, Roger; Koenig, Christian
主题: [PATCH] drm/amd/amdgpu: fix over-bound accessing in amdgpu_cs_wait_any_fence

fix the following issue:

Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.712090] Oops:  [#2] SMP
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.712481] Modules linked in: 
amdgpu(OE) chash ttm(OE) drm_kms_helper(OE) drm(OE) i2c_algo_bit fb_sys_fops 
syscopyarea sysfillrect sysimgblt intel_rapl snd_hda_codec_realtek 
snd_hda_codec_generic x86_pkg_temp_thermal intel_powerclamp snd_hda_codec_hdmi 
coretemp snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm kvm 
snd_seq_midi snd_seq_midi_event snd_rawmidi snd_seq irqbypass crct10dif_pclmul 
crc32_pclmul ghash_clmulni_intel pcbc snd_seq_device snd_timer aesni_intel snd 
mei_me mei aes_x86_64 crypto_simd serio_raw eeepc_wmi glue_helper asus_wmi 
sparse_keymap cryptd soundcore shpchp wmi_bmof lpc_ich mac_hid tpm_infineon 
nfsd auth_rpcgss nfs_acl lockd parport_pc grace ppdev sunrpc lp parport autofs4 
hid_generic usbhid ahci mxm_wmi r8169 libahci hid mii wmi video
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715120] CPU: 1 PID: 1330 Comm: 
deqp-vk Tainted: G  DOE   4.13.0-custom #1
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715879] Hardware name: ASUS All 
Series/Z87-A, BIOS 1802 01/28/2014
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.716658] task: 9b7115728000 
task.stack: b178016e
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.717494] RIP: 
0010:amdgpu_cs_wait_fences_ioctl+0x20b/0x2e0 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.718312] RSP: 
0018:b178016e3cb0 EFLAGS: 00010246
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.719270] RAX:  
RBX: b178016e3d90 RCX: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.720247] RDX:  
RSI: 0001 RDI: 9b7116a1d8a8
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.721246] RBP: b178016e3d00 
R08:  R09: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.722262] R10: ed00 
R11: b178016e3d90 R12: 9b7116a1d8a8
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.723299] R13: 9b7000707020 
R14: 0001 R15: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.724358] FS:  
7f89f3af4740() GS:9b712ec8() knlGS:
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.725447] CS:  0010 DS:  ES: 
 CR0: 80050033
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.726550] CR2: 9b7916a1d8a0 
CR3: 00022042e000 CR4: 001406e0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.727687] DR0:  
DR1:  DR2: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.728837] DR3:  
DR6: fffe0ff0 DR7: 0400
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.729992] Call Trace:
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.731193]  ? 
amdgpu_cs_fence_to_handle_ioctl+0x1c0/0x1c0 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.732406]  
drm_ioctl_kernel+0x69/0xb0 [drm]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.733626]  drm_ioctl+0x2d2/0x390 
[drm]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.734883]  ? 
amdgpu_cs_fence_to_handle_ioctl+0x1c0/0x1c0 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.736135]  ? __do_fault+0x1e/0x70
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.737392]  ? 
__handle_mm_fault+0x8ae/0x10f0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  

答复: [PATCH] drm/amd/amdgpu: fix over-bound accessing in amdgpu_cs_wait_any_fence

[Qu, Jim]

Hi Roger:

-   if (array[first])
-   r = array[first]->error;
-   else
+   if (first == ~0)
r = 0;
+   else
+   r = array[first]->error;

// The patch looks like change original logic that miss to check array[first].

Thanks
JimQu


发件人: amd-gfx  代表 Roger He 

发送时间: 2017年11月17日 13:04
收件人: amd-gfx@lists.freedesktop.org
抄送: Zhou, David(ChunMing); He, Roger; Koenig, Christian
主题: [PATCH] drm/amd/amdgpu: fix over-bound accessing in amdgpu_cs_wait_any_fence

fix the following issue:

Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.712090] Oops:  [#2] SMP
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.712481] Modules linked in: 
amdgpu(OE) chash ttm(OE) drm_kms_helper(OE) drm(OE) i2c_algo_bit fb_sys_fops 
syscopyarea sysfillrect sysimgblt intel_rapl snd_hda_codec_realtek 
snd_hda_codec_generic x86_pkg_temp_thermal intel_powerclamp snd_hda_codec_hdmi 
coretemp snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm kvm 
snd_seq_midi snd_seq_midi_event snd_rawmidi snd_seq irqbypass crct10dif_pclmul 
crc32_pclmul ghash_clmulni_intel pcbc snd_seq_device snd_timer aesni_intel snd 
mei_me mei aes_x86_64 crypto_simd serio_raw eeepc_wmi glue_helper asus_wmi 
sparse_keymap cryptd soundcore shpchp wmi_bmof lpc_ich mac_hid tpm_infineon 
nfsd auth_rpcgss nfs_acl lockd parport_pc grace ppdev sunrpc lp parport autofs4 
hid_generic usbhid ahci mxm_wmi r8169 libahci hid mii wmi video
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715120] CPU: 1 PID: 1330 Comm: 
deqp-vk Tainted: G  DOE   4.13.0-custom #1
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715879] Hardware name: ASUS All 
Series/Z87-A, BIOS 1802 01/28/2014
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.716658] task: 9b7115728000 
task.stack: b178016e
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.717494] RIP: 
0010:amdgpu_cs_wait_fences_ioctl+0x20b/0x2e0 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.718312] RSP: 
0018:b178016e3cb0 EFLAGS: 00010246
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.719270] RAX:  
RBX: b178016e3d90 RCX: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.720247] RDX:  
RSI: 0001 RDI: 9b7116a1d8a8
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.721246] RBP: b178016e3d00 
R08:  R09: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.722262] R10: ed00 
R11: b178016e3d90 R12: 9b7116a1d8a8
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.723299] R13: 9b7000707020 
R14: 0001 R15: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.724358] FS:  
7f89f3af4740() GS:9b712ec8() knlGS:
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.725447] CS:  0010 DS:  ES: 
 CR0: 80050033
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.726550] CR2: 9b7916a1d8a0 
CR3: 00022042e000 CR4: 001406e0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.727687] DR0:  
DR1:  DR2: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.728837] DR3:  
DR6: fffe0ff0 DR7: 0400
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.729992] Call Trace:
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.731193]  ? 
amdgpu_cs_fence_to_handle_ioctl+0x1c0/0x1c0 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.732406]  
drm_ioctl_kernel+0x69/0xb0 [drm]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.733626]  drm_ioctl+0x2d2/0x390 
[drm]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.734883]  ? 
amdgpu_cs_fence_to_handle_ioctl+0x1c0/0x1c0 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.736135]  ? __do_fault+0x1e/0x70
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.737392]  ? 
__handle_mm_fault+0x8ae/0x10f0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.738665]  ? 
apparmor_mmap_file+0x18/0x20
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.739980]  
amdgpu_drm_ioctl+0x4c/0x80 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.741277]  do_vfs_ioctl+0x96/0x5b0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.742582]  ? 
handle_mm_fault+0xd3/0x1f0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.743899]  ? sched_clock+0x9/0x10
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.745224]  SyS_ioctl+0x79/0x90
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.746553]  ? 
vtime_user_exit+0x29/0x70
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.747897]  do_syscall_64+0x6e/0x160
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.749247]  
entry_SYSCALL64_slow_path+0x25/0x25
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.750614] RIP: 0033:0x7f89f1fdff07
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.751987] RSP: 
002b:7ffd4c6262d8 EFLAGS: 0202 ORIG_RAX: 0010
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.753407] RAX: 

Re: 答复: [PATCH] drm/amd/amdgpu: fix over-bound accessing in amdgpu_cs_wait_any_fence

[Chunming Zhou]

Yes,  As Jim pointed out, you lacks the array[] checking.

you can just change to if (first < fence_count && array[first]), 
otherwise it's a good fix for regression.



Regards,

David Zhou


On 2017年11月17日 13:16, Qu, Jim wrote:

Hi Roger:

-   if (array[first])
-   r = array[first]->error;
-   else
+   if (first == ~0)
 r = 0;
+   else
+   r = array[first]->error;

// The patch looks like change original logic that miss to check array[first].

Thanks
JimQu


发件人: amd-gfx  代表 Roger He 

发送时间: 2017年11月17日 13:04
收件人: amd-gfx@lists.freedesktop.org
抄送: Zhou, David(ChunMing); He, Roger; Koenig, Christian
主题: [PATCH] drm/amd/amdgpu: fix over-bound accessing in amdgpu_cs_wait_any_fence

fix the following issue:

Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.712090] Oops:  [#2] SMP
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.712481] Modules linked in: 
amdgpu(OE) chash ttm(OE) drm_kms_helper(OE) drm(OE) i2c_algo_bit fb_sys_fops 
syscopyarea sysfillrect sysimgblt intel_rapl snd_hda_codec_realtek 
snd_hda_codec_generic x86_pkg_temp_thermal intel_powerclamp snd_hda_codec_hdmi 
coretemp snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm kvm 
snd_seq_midi snd_seq_midi_event snd_rawmidi snd_seq irqbypass crct10dif_pclmul 
crc32_pclmul ghash_clmulni_intel pcbc snd_seq_device snd_timer aesni_intel snd 
mei_me mei aes_x86_64 crypto_simd serio_raw eeepc_wmi glue_helper asus_wmi 
sparse_keymap cryptd soundcore shpchp wmi_bmof lpc_ich mac_hid tpm_infineon 
nfsd auth_rpcgss nfs_acl lockd parport_pc grace ppdev sunrpc lp parport autofs4 
hid_generic usbhid ahci mxm_wmi r8169 libahci hid mii wmi video
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715120] CPU: 1 PID: 1330 Comm: 
deqp-vk Tainted: G  DOE   4.13.0-custom #1
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715879] Hardware name: ASUS All 
Series/Z87-A, BIOS 1802 01/28/2014
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.716658] task: 9b7115728000 
task.stack: b178016e
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.717494] RIP: 
0010:amdgpu_cs_wait_fences_ioctl+0x20b/0x2e0 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.718312] RSP: 
0018:b178016e3cb0 EFLAGS: 00010246
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.719270] RAX:  
RBX: b178016e3d90 RCX: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.720247] RDX:  
RSI: 0001 RDI: 9b7116a1d8a8
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.721246] RBP: b178016e3d00 
R08:  R09: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.722262] R10: ed00 
R11: b178016e3d90 R12: 9b7116a1d8a8
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.723299] R13: 9b7000707020 
R14: 0001 R15: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.724358] FS:  
7f89f3af4740() GS:9b712ec8() knlGS:
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.725447] CS:  0010 DS:  ES: 
 CR0: 80050033
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.726550] CR2: 9b7916a1d8a0 
CR3: 00022042e000 CR4: 001406e0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.727687] DR0:  
DR1:  DR2: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.728837] DR3:  
DR6: fffe0ff0 DR7: 0400
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.729992] Call Trace:
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.731193]  ? 
amdgpu_cs_fence_to_handle_ioctl+0x1c0/0x1c0 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.732406]  
drm_ioctl_kernel+0x69/0xb0 [drm]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.733626]  drm_ioctl+0x2d2/0x390 
[drm]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.734883]  ? 
amdgpu_cs_fence_to_handle_ioctl+0x1c0/0x1c0 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.736135]  ? __do_fault+0x1e/0x70
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.737392]  ? 
__handle_mm_fault+0x8ae/0x10f0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.738665]  ? 
apparmor_mmap_file+0x18/0x20
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.739980]  
amdgpu_drm_ioctl+0x4c/0x80 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.741277]  do_vfs_ioctl+0x96/0x5b0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.742582]  ? 
handle_mm_fault+0xd3/0x1f0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.743899]  ? sched_clock+0x9/0x10
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.745224]  SyS_ioctl+0x79/0x90
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.746553]  ? 
vtime_user_exit+0x29/0x70
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.747897]  do_syscall_64+0x6e/0x160
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.749247]  
entry_SYSCALL64_slow_path+0x25/0x25
Nov 15 17:40:25 jenkins-MS-7984 kernel: [ 

[PATCH] drm/amd/amdgpu: fix over-bound accessing in amdgpu_cs_wait_any_fence

[Roger He]

fix the following issue:

Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.712090] Oops:  [#2] SMP
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.712481] Modules linked in: 
amdgpu(OE) chash ttm(OE) drm_kms_helper(OE) drm(OE) i2c_algo_bit fb_sys_fops 
syscopyarea sysfillrect sysimgblt intel_rapl snd_hda_codec_realtek 
snd_hda_codec_generic x86_pkg_temp_thermal intel_powerclamp snd_hda_codec_hdmi 
coretemp snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm kvm 
snd_seq_midi snd_seq_midi_event snd_rawmidi snd_seq irqbypass crct10dif_pclmul 
crc32_pclmul ghash_clmulni_intel pcbc snd_seq_device snd_timer aesni_intel snd 
mei_me mei aes_x86_64 crypto_simd serio_raw eeepc_wmi glue_helper asus_wmi 
sparse_keymap cryptd soundcore shpchp wmi_bmof lpc_ich mac_hid tpm_infineon 
nfsd auth_rpcgss nfs_acl lockd parport_pc grace ppdev sunrpc lp parport autofs4 
hid_generic usbhid ahci mxm_wmi r8169 libahci hid mii wmi video
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715120] CPU: 1 PID: 1330 Comm: 
deqp-vk Tainted: G  DOE   4.13.0-custom #1
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.715879] Hardware name: ASUS All 
Series/Z87-A, BIOS 1802 01/28/2014
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.716658] task: 9b7115728000 
task.stack: b178016e
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.717494] RIP: 
0010:amdgpu_cs_wait_fences_ioctl+0x20b/0x2e0 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.718312] RSP: 
0018:b178016e3cb0 EFLAGS: 00010246
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.719270] RAX:  
RBX: b178016e3d90 RCX: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.720247] RDX:  
RSI: 0001 RDI: 9b7116a1d8a8
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.721246] RBP: b178016e3d00 
R08:  R09: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.722262] R10: ed00 
R11: b178016e3d90 R12: 9b7116a1d8a8
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.723299] R13: 9b7000707020 
R14: 0001 R15: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.724358] FS:  
7f89f3af4740() GS:9b712ec8() knlGS:
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.725447] CS:  0010 DS:  ES: 
 CR0: 80050033
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.726550] CR2: 9b7916a1d8a0 
CR3: 00022042e000 CR4: 001406e0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.727687] DR0:  
DR1:  DR2: 
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.728837] DR3:  
DR6: fffe0ff0 DR7: 0400
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.729992] Call Trace:
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.731193]  ? 
amdgpu_cs_fence_to_handle_ioctl+0x1c0/0x1c0 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.732406]  
drm_ioctl_kernel+0x69/0xb0 [drm]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.733626]  drm_ioctl+0x2d2/0x390 
[drm]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.734883]  ? 
amdgpu_cs_fence_to_handle_ioctl+0x1c0/0x1c0 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.736135]  ? __do_fault+0x1e/0x70
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.737392]  ? 
__handle_mm_fault+0x8ae/0x10f0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.738665]  ? 
apparmor_mmap_file+0x18/0x20
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.739980]  
amdgpu_drm_ioctl+0x4c/0x80 [amdgpu]
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.741277]  do_vfs_ioctl+0x96/0x5b0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.742582]  ? 
handle_mm_fault+0xd3/0x1f0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.743899]  ? sched_clock+0x9/0x10
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.745224]  SyS_ioctl+0x79/0x90
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.746553]  ? 
vtime_user_exit+0x29/0x70
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.747897]  do_syscall_64+0x6e/0x160
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.749247]  
entry_SYSCALL64_slow_path+0x25/0x25
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.750614] RIP: 0033:0x7f89f1fdff07
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.751987] RSP: 
002b:7ffd4c6262d8 EFLAGS: 0202 ORIG_RAX: 0010
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.753407] RAX: ffda 
RBX: 0001 RCX: 7f89f1fdff07
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.754847] RDX: 7ffd4c6263a0 
RSI: c0186452 RDI: 0005
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.756302] RBP: 7ffd4c626310 
R08: 0001 R09: 7ffd4c62642c
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.757768] R10: edf2 
R11: 0202 R12: 7ffd4c6264b0
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.759243] R13: 000186a0 
R14:  R15: 7ffd4c626700
Nov 15 17:40:25 jenkins-MS-7984 kernel: [  146.760725] Code: ff ff ff 

Re: [PATCH 2/3] drm/amd/include:cleanup vega10 hdp header files.

[Feifei Xu]

On 11/17/2017 12:01 AM, Michel Dänzer wrote:

On 16/11/17 11:29 AM, Xu, Feifei wrote:

Resent the patch #1, yes, it is too large due to the header file movement.
And I will send the coming cleanup patches separately to avoid message dropping.

There's no need for anybody to download megabytes of e-mail for patches
which just (re)move files. Please try flags such as --find-renames /
--irreversible-delete with git format-patch.


Thanks. To avoid duplication of header files, a lot of header files will 
be re/moved.
I will send out following cleanup patches as suggested to avoid huge 
patches flush.


--
-Feifei

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RE: [PATCH 1/2] drm/amdgpu:fix virtual dce bug

[Liu, Monk]

I think it's already clear enough 

-Original Message-
From: Jan Vesely [mailto:jv...@scarletmail.rutgers.edu] On Behalf Of Jan Vesely
Sent: 2017年11月17日 0:40
To: Liu, Monk ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/amdgpu:fix virtual dce bug

On Thu, 2017-11-16 at 11:14 +0800, Monk Liu wrote:
> this fix the issue that access memory after freed after driver 
> unloaded.

can you please change the patch subject and commit message to something more 
descriptive?

Jan

> 
> Change-Id: I64e2488c18f5dc044b57c74567785da21fc028da
> Signed-off-by: Monk Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
> b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> index a8829af..39460eb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> @@ -437,6 +437,8 @@ static int dce_virtual_sw_fini(void *handle)
>   drm_kms_helper_poll_fini(adev->ddev);
>  
>   drm_mode_config_cleanup(adev->ddev);
> + /* clear crtcs pointer to avoid dce irq finish routine access freed 
> data */
> + memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * 
> +AMDGPU_MAX_CRTCS);
>   adev->mode_info.mode_config_initialized = false;
>   return 0;
>  }
> @@ -723,7 +725,7 @@ static void 
> dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *ad
>   int crtc,
>   enum 
> amdgpu_interrupt_state state)  {
> - if (crtc >= adev->mode_info.num_crtc) {
> + if (crtc >= adev->mode_info.num_crtc || 
> +!adev->mode_info.crtcs[crtc]) {
>   DRM_DEBUG("invalid crtc %d\n", crtc);
>   return;
>   }
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Re: [PATCH 2/3] drm/amd/include:cleanup vega10 hdp header files.

[Feifei Xu]

On 11/16/2017 10:59 PM, Alex Deucher wrote:

On Thu, Nov 16, 2017 at 3:03 AM, Feifei Xu  wrote:

Cleanup asic_reg/vega10/HDP folder, remove hdp_4_0_default.h

Change-Id: Ia7cd2e660ceb89a1096c195c6a67677714ccbd69
Signed-off-by: Feifei Xu
Reviewed-by: Alex Deucher
---
  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |   2 +-
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |   4 +-
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |   2 +-
  drivers/gpu/drm/amd/amdgpu/soc15.c |   4 +-
  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  |   2 +-
  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  |   2 +-
  .../drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h  | 209 +++
  .../drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h | 601 +
  .../include/asic_reg/vega10/HDP/hdp_4_0_default.h  | 117 
  .../include/asic_reg/vega10/HDP/hdp_4_0_offset.h   | 209 ---
  .../include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h  | 601 -
  11 files changed, 818 insertions(+), 935 deletions(-)
  create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h
  create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
  delete mode 100644 
drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h
  delete mode 100644 
drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h
  delete mode 100644 
drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h

Is there a reason to remove hdp_4_0_default.h?  It's useful if we ever
need to get the default values of the registers.  I think we should
try and keep the register headers consistent.  If we aren't using any
of the default headers, that's fine, we can remove them.

Alex

I remove it because we aren't using any of the default headers in this file.
When cleaning up vega10's header files, I found some header files are 
never used though we included them somewhere.
hdp_4_0_default.h is one of them. Checked vega10, raven and other asics, 
we don't get the hdp registers' default values

from this header file. So I remove it, and test it on vega board.

Thanks
Feifei
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Re: [PATCH] drm/amd/display: remove unnecessary cast and use kcalloc instead of kzalloc

[Alex Deucher]

On Wed, Nov 15, 2017 at 10:45 AM, Colin King  wrote:
> From: Colin Ian King 
>
> Use kcalloc instead of kzalloc and the cast on the return from kzalloc is
> unnecessary and can be removed.
>
> Signed-off-by: Colin Ian King 

Reviewed and pushed.

Thanks!

Alex

> ---
>  drivers/gpu/drm/amd/display/dc/basics/logger.c | 5 ++---
>  1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c 
> b/drivers/gpu/drm/amd/display/dc/basics/logger.c
> index e04e8ecd4874..2ff5b467603d 100644
> --- a/drivers/gpu/drm/amd/display/dc/basics/logger.c
> +++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c
> @@ -70,9 +70,8 @@ static bool construct(struct dc_context *ctx, struct 
> dal_logger *logger,
>  {
> /* malloc buffer and init offsets */
> logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE;
> -   logger->log_buffer = (char *)kzalloc(logger->log_buffer_size * 
> sizeof(char),
> -GFP_KERNEL);
> -
> +   logger->log_buffer = kcalloc(logger->log_buffer_size, sizeof(char),
> +GFP_KERNEL);
> if (!logger->log_buffer)
> return false;
>
> --
> 2.14.1
>
> ___
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> dri-de...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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[PATCH 1/1] drm/amdkfd: Do not ignore requested queue size during allocation

[Jan Vesely]

Signed-off-by: Jan Vesely 
---
 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
index f1d48281e322..b3bee39661ab 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
@@ -37,15 +37,16 @@ static bool initialize_vi(struct kernel_queue *kq, struct 
kfd_dev *dev,
enum kfd_queue_type type, unsigned int queue_size)
 {
int retval;
+   unsigned int size = ALIGN(queue_size, PAGE_SIZE);
 
-   retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, >eop_mem);
+   retval = kfd_gtt_sa_allocate(dev, size, >eop_mem);
if (retval != 0)
return false;
 
kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
 
-   memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
+   memset(kq->eop_kernel_addr, 0, size);
 
return true;
 }
-- 
2.13.6

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Applied "ASoC: AMD: Make the driver name consistent across files" to the asoc tree

[Mark Brown]

The patch

   ASoC: AMD: Make the driver name consistent across files

has been applied to the asoc tree at

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git 

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.  

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

From a76d7f5454c688b52dc849e832cc4c6dd0975723 Mon Sep 17 00:00:00 2001
From: Akshu Agrawal 
Date: Fri, 3 Nov 2017 16:35:44 -0400
Subject: [PATCH] ASoC: AMD: Make the driver name consistent across files

This fixes the issue of driver not getting auto loaded with
MODULE_ALIAS.
find /sys/devices -name modalias -print0 | xargs -0 grep 'audio'
/sys/devices/pci:00/:00:01.0/acp_audio_dma.0.auto/modalias:platform:acp_audio_dma

BUG=b:62103837
TEST=boot and check for device in lsmod

Signed-off-by: Akshu Agrawal 
Reviewed-on: https://chromium-review.googlesource.com/678278
Tested-by: Jason Clinton 
Reviewed-by: Jason Clinton 
Signed-off-by: Alex Deucher 
Signed-off-by: Mark Brown 
---
 sound/soc/amd/Makefile  | 4 ++--
 sound/soc/amd/acp-pcm-dma.c | 6 --
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/sound/soc/amd/Makefile b/sound/soc/amd/Makefile
index eed64ff6c73e..f07fd2e2870a 100644
--- a/sound/soc/amd/Makefile
+++ b/sound/soc/amd/Makefile
@@ -1,5 +1,5 @@
-snd-soc-acp-pcm-objs   := acp-pcm-dma.o
+acp_audio_dma-objs := acp-pcm-dma.o
 snd-soc-acp-rt5645-mach-objs := acp-rt5645.o
 
-obj-$(CONFIG_SND_SOC_AMD_ACP) += snd-soc-acp-pcm.o
+obj-$(CONFIG_SND_SOC_AMD_ACP) += acp_audio_dma.o
 obj-$(CONFIG_SND_SOC_AMD_CZ_RT5645_MACH) += snd-soc-acp-rt5645-mach.o
diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c
index 73b58ee00383..95c61ecdd1dd 100644
--- a/sound/soc/amd/acp-pcm-dma.c
+++ b/sound/soc/amd/acp-pcm-dma.c
@@ -40,6 +40,8 @@
 #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS)
 #define ST_MIN_BUFFER ST_MAX_BUFFER
 
+#define DRV_NAME "acp_audio_dma"
+
 static const struct snd_pcm_hardware acp_pcm_hardware_playback = {
.info = SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP |
@@ -1170,7 +1172,7 @@ static struct platform_driver acp_dma_driver = {
.probe = acp_audio_probe,
.remove = acp_audio_remove,
.driver = {
-   .name = "acp_audio_dma",
+   .name = DRV_NAME,
.pm = _pm_ops,
},
 };
@@ -1181,4 +1183,4 @@ MODULE_AUTHOR("vijendar.muku...@amd.com");
 MODULE_AUTHOR("maruthi.bayyavar...@amd.com");
 MODULE_DESCRIPTION("AMD ACP PCM Driver");
 MODULE_LICENSE("GPL v2");
-MODULE_ALIAS("platform:acp-dma-audio");
+MODULE_ALIAS("platform:"DRV_NAME);
-- 
2.14.1

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Re: [PATCH 0/4] treewide: Fix line continuation formats

[Mimi Zohar]

On Thu, 2017-11-16 at 09:17 -0800, Joe Perches wrote:
> On Thu, 2017-11-16 at 12:11 -0500, Mimi Zohar wrote:
> > On Thu, 2017-11-16 at 07:27 -0800, Joe Perches wrote:
> > > Avoid using line continations in formats as that causes unexpected
> > > output.
> > 
> > Is having lines greater than 80 characters the preferred method?
> 
> yes.
> 
> >  Could you add quotes before the backlash and before the first word on
> > the next line instead?
> 
> coalesced formats are preferred.

In the future, please reference the commit 6f76b6fcaa60 "CodingStyle:
Document the exception of not splitting user-visible strings, for
grepping"

thanks,

Mimi

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dirty suspend after piglit run

[Tom St Denis]

On my Carrizo with the tip of drm-next as of today I get VM faults near 
the end of the piglit tests (with "-x max.*size") which then manifest 
UVD problems when decoding with a system suspend in the middle.


Attached is the dmesg log.

Suspend works fine if I don't trigger the VM faults first.

I'll see if I can bisect down the VM faults since I think this is a 
relatively new regression (with max.*size excluded).


Tom
[0.00] Linux version 4.14.0-rc3+ (root@carrizo) (gcc version 7.2.1 20170915 (Red Hat 7.2.1-2) (GCC)) #21 SMP Thu Nov 16 10:52:30 EST 2017
[0.00] Command line: BOOT_IMAGE=/vmlinuz-4.14.0-rc3+ root=UUID=66163c80-0ca1-4beb-aeba-5cc130b813e6 ro rhgb quiet LANG=en_CA.UTF-8 rdblacklist=amdgpu
[0.00] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
[0.00] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
[0.00] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
[0.00] x86/fpu: xstate_offset[2]:  576, xstate_sizes[2]:  256
[0.00] x86/fpu: Enabled xstate features 0x7, context size is 832 bytes, using 'standard' format.
[0.00] e820: BIOS-provided physical RAM map:
[0.00] BIOS-e820: [mem 0x-0x0009d3ff] usable
[0.00] BIOS-e820: [mem 0x0009d400-0x0009] reserved
[0.00] BIOS-e820: [mem 0x000e-0x000f] reserved
[0.00] BIOS-e820: [mem 0x0010-0xd6cf1fff] usable
[0.00] BIOS-e820: [mem 0xd6cf2000-0xd6d0bfff] ACPI data
[0.00] BIOS-e820: [mem 0xd6d0c000-0xdac18fff] usable
[0.00] BIOS-e820: [mem 0xdac19000-0xdada0fff] reserved
[0.00] BIOS-e820: [mem 0xdada1000-0xdadb3fff] ACPI data
[0.00] BIOS-e820: [mem 0xdadb4000-0xdaeadfff] usable
[0.00] BIOS-e820: [mem 0xdaeae000-0xdb25] ACPI NVS
[0.00] BIOS-e820: [mem 0xdb26-0xdbb6cfff] reserved
[0.00] BIOS-e820: [mem 0xdbb6d000-0xddff] usable
[0.00] BIOS-e820: [mem 0xde00-0xdfff] reserved
[0.00] BIOS-e820: [mem 0xf800-0xfbff] reserved
[0.00] BIOS-e820: [mem 0xfe50-0xfe5f] reserved
[0.00] BIOS-e820: [mem 0xfea0-0xfea0] reserved
[0.00] BIOS-e820: [mem 0xfeb8-0xfec01fff] reserved
[0.00] BIOS-e820: [mem 0xfec1-0xfec10fff] reserved
[0.00] BIOS-e820: [mem 0xfec3-0xfec30fff] reserved
[0.00] BIOS-e820: [mem 0xfed0-0xfed00fff] reserved
[0.00] BIOS-e820: [mem 0xfed4-0xfed44fff] reserved
[0.00] BIOS-e820: [mem 0xfed8-0xfed8] reserved
[0.00] BIOS-e820: [mem 0xfedc-0xfedc0fff] reserved
[0.00] BIOS-e820: [mem 0xfedc2000-0xfedc8fff] reserved
[0.00] BIOS-e820: [mem 0xfee0-0xfeef] reserved
[0.00] BIOS-e820: [mem 0xff00-0x] reserved
[0.00] BIOS-e820: [mem 0x0001-0x0001feff] usable
[0.00] BIOS-e820: [mem 0x0001ff00-0x00021eff] reserved
[0.00] NX (Execute Disable) protection: active
[0.00] random: fast init done
[0.00] SMBIOS 3.0.0 present.
[0.00] DMI: System manufacturer System Product Name/TUF B350M-PLUS GAMING, BIOS 0902 09/08/2017
[0.00] tsc: Fast TSC calibration failed
[0.00] tsc: Using PIT calibration value
[0.00] e820: update [mem 0x-0x0fff] usable ==> reserved
[0.00] e820: remove [mem 0x000a-0x000f] usable
[0.00] e820: last_pfn = 0x1ff000 max_arch_pfn = 0x4
[0.00] MTRR default type: uncachable
[0.00] MTRR fixed ranges enabled:
[0.00]   0-9 write-back
[0.00]   A-B write-through
[0.00]   C-F write-protect
[0.00] MTRR variable ranges enabled:
[0.00]   0 base  mask 8000 write-back
[0.00]   1 base 8000 mask C000 write-back
[0.00]   2 base C000 mask E000 write-back
[0.00]   3 base DE00 mask FE00 uncachable
[0.00]   4 disabled
[0.00]   5 disabled
[0.00]   6 disabled
[0.00]   7 disabled
[0.00] TOM2: 00021f00 aka 8688M
[0.00] x86/PAT: Configuration [0-7]: WB  WC  UC- UC  WB  WP  UC- WT  
[0.00] e820: update [mem 0xde00-0x] usable ==> reserved
[0.00] e820: last_pfn = 0xde000 max_arch_pfn = 0x4
[0.00] Base memory trampoline at [88097000] 97000 size 24576
[0.00] Using GB pages for direct mapping
[0.00] BRK [0x1fea2000, 

Re: [PATCH] Revert "drm/radeon: dont switch vt on suspend"

[Alex Deucher]

Ping?


On Tue, Nov 14, 2017 at 5:33 PM, Alex Deucher  wrote:
> Fixes distorted colors on some cards on resume from suspend.
>
> This reverts commit b9729b17a414f99c61f4db9ac9f9ed987fa0cbfe.
>
> Bug: https://bugs.freedesktop.org/show_bug.cgi?id=98832
> Signed-off-by: Alex Deucher 
> Cc: sta...@vger.kernel.org
> ---
>  drivers/gpu/drm/radeon/radeon_fb.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_fb.c 
> b/drivers/gpu/drm/radeon/radeon_fb.c
> index 2fcf805d3a16..33b821d6d018 100644
> --- a/drivers/gpu/drm/radeon/radeon_fb.c
> +++ b/drivers/gpu/drm/radeon/radeon_fb.c
> @@ -245,7 +245,6 @@ static int radeonfb_create(struct drm_fb_helper *helper,
> }
>
> info->par = rfbdev;
> -   info->skip_vt_switch = true;
>
> ret = radeon_framebuffer_init(rdev->ddev, >rfb, _cmd, 
> gobj);
> if (ret) {
> --
> 2.13.6
>
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Re: [PATCH] drm/amdgpu: always make gart.table_addr 64bit

[Alex Deucher]

On Thu, Nov 16, 2017 at 12:31 PM, Christian König
 wrote:
> Fixing warning/compile errors on 32bit kernels.
>
> Signed-off-by: Christian König 

Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> index f15e319580ec..5eb1a6800f72 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> @@ -39,7 +39,7 @@ struct amdgpu_gart_funcs;
>  #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & 
> ~AMDGPU_GPU_PAGE_MASK)
>
>  struct amdgpu_gart {
> -   dma_addr_t  table_addr;
> +   u64 table_addr;
> struct amdgpu_bo*robj;
> void*ptr;
> unsignednum_gpu_pages;
> --
> 2.11.0
>
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Re: [PATCH 0/4] treewide: Fix line continuation formats

[Mimi Zohar]

On Thu, 2017-11-16 at 07:27 -0800, Joe Perches wrote:
> Avoid using line continations in formats as that causes unexpected
> output.

Is having lines greater than 80 characters the preferred method?
 Could you add quotes before the backlash and before the first word on
the next line instead?

Mimi

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Re: [PATCH 0/4] treewide: Fix line continuation formats

[Joe Perches]

On Thu, 2017-11-16 at 12:11 -0500, Mimi Zohar wrote:
> On Thu, 2017-11-16 at 07:27 -0800, Joe Perches wrote:
> > Avoid using line continations in formats as that causes unexpected
> > output.
> 
> Is having lines greater than 80 characters the preferred method?

yes.

>  Could you add quotes before the backlash and before the first word on
> the next line instead?

coalesced formats are preferred.

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[PATCH] drm/amdgpu: always make gart.table_addr 64bit

[Christian König]

Fixing warning/compile errors on 32bit kernels.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
index f15e319580ec..5eb1a6800f72 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
@@ -39,7 +39,7 @@ struct amdgpu_gart_funcs;
 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & 
~AMDGPU_GPU_PAGE_MASK)
 
 struct amdgpu_gart {
-   dma_addr_t  table_addr;
+   u64 table_addr;
struct amdgpu_bo*robj;
void*ptr;
unsignednum_gpu_pages;
-- 
2.11.0

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[PATCH] drm/amd/powerplay: fix unfreeze level smc message for smu7

[Eric Huang]

Signed-off-by: Eric Huang 
Change-Id: I215e49b3cae43c8ba6df0bd40db8b2b07ffc4fed
---
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index ed17af4..8edb0c4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -3778,7 +3778,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct pp_hwmgr 
*hwmgr)
"Trying to Unfreeze MCLK DPM when DPM is 
disabled",
);
PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr,
-   PPSMC_MSG_SCLKDPM_UnfreezeLevel),
+   PPSMC_MSG_MCLKDPM_UnfreezeLevel),
"Failed to unfreeze MCLK DPM during UnFreezeSclkMclkDPM 
Function!",
return -EINVAL);
}
-- 
2.7.4

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Re: [PATCH 1/2] drm/amdgpu:fix virtual dce bug

[Jan Vesely]

On Thu, 2017-11-16 at 11:14 +0800, Monk Liu wrote:
> this fix the issue that access memory after freed
> after driver unloaded.

can you please change the patch subject and commit message to something
more descriptive?

Jan

> 
> Change-Id: I64e2488c18f5dc044b57c74567785da21fc028da
> Signed-off-by: Monk Liu 
> ---
>  drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
> b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> index a8829af..39460eb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> +++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
> @@ -437,6 +437,8 @@ static int dce_virtual_sw_fini(void *handle)
>   drm_kms_helper_poll_fini(adev->ddev);
>  
>   drm_mode_config_cleanup(adev->ddev);
> + /* clear crtcs pointer to avoid dce irq finish routine access freed 
> data */
> + memset(adev->mode_info.crtcs, 0, sizeof(adev->mode_info.crtcs[0]) * 
> AMDGPU_MAX_CRTCS);
>   adev->mode_info.mode_config_initialized = false;
>   return 0;
>  }
> @@ -723,7 +725,7 @@ static void 
> dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device *ad
>   int crtc,
>   enum 
> amdgpu_interrupt_state state)
>  {
> - if (crtc >= adev->mode_info.num_crtc) {
> + if (crtc >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[crtc]) {
>   DRM_DEBUG("invalid crtc %d\n", crtc);
>   return;
>   }


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RE: [PATCH] drm/amd/powerplay: fix unfreeze level smc message for smu7

[Deucher, Alexander]

> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Eric Huang
> Sent: Thursday, November 16, 2017 11:22 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Huang, JinHuiEric
> Subject: [PATCH] drm/amd/powerplay: fix unfreeze level smc message for
> smu7
> 
> Signed-off-by: Eric Huang 
> Change-Id: I215e49b3cae43c8ba6df0bd40db8b2b07ffc4fed

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index ed17af4..8edb0c4 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -3778,7 +3778,7 @@ static int smu7_unfreeze_sclk_mclk_dpm(struct
> pp_hwmgr *hwmgr)
>   "Trying to Unfreeze MCLK DPM when DPM is
> disabled",
>   );
>   PP_ASSERT_WITH_CODE(0 ==
> smum_send_msg_to_smc(hwmgr,
> - PPSMC_MSG_SCLKDPM_UnfreezeLevel),
> + PPSMC_MSG_MCLKDPM_UnfreezeLevel),
>   "Failed to unfreeze MCLK DPM during
> UnFreezeSclkMclkDPM Function!",
>   return -EINVAL);
>   }
> --
> 2.7.4
> 
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Re: [PATCH 2/3] drm/amd/include:cleanup vega10 hdp header files.

[Michel Dänzer]

On 16/11/17 11:29 AM, Xu, Feifei wrote:
> Resent the patch #1, yes, it is too large due to the header file movement.
> And I will send the coming cleanup patches separately to avoid message 
> dropping.

There's no need for anybody to download megabytes of e-mail for patches
which just (re)move files. Please try flags such as --find-renames /
--irreversible-delete with git format-patch.


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Libre software enthusiast | Mesa and X developer
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[PATCH 2/4] drm: amd: Fix line continuation formats

[Joe Perches]

Line continuations with excess spacing causes unexpected output.

Miscellanea:

o Added missing '\n' to a few of the coalesced pr_ formats

Signed-off-by: Joe Perches 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   | 11 -
 .../amd/powerplay/hwmgr/process_pptables_v1_0.c|  6 ++---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 27 --
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c   |  6 ++---
 .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c  |  9 +++-
 .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c   |  6 ++---
 6 files changed, 22 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index ced42484dcfc..6743786afcce 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -220,8 +220,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
size_in_bytes);
 
dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
-   "%s:\n %x VS set = %x  PE set = %x \
-   max VS Reached = %x  max PE Reached = %x\n",
+   "%s:\n %x VS set = %x  PE set = %x max VS Reached = %x  max PE 
Reached = %x\n",
__func__,
DP_TRAINING_LANE0_SET,
dpcd_lane[0].bits.VOLTAGE_SWING_SET,
@@ -558,8 +557,7 @@ static void dpcd_set_lane_settings(
*/
 
dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
-   "%s\n %x VS set = %x  PE set = %x \
-   max VS Reached = %x  max PE Reached = %x\n",
+   "%s\n %x VS set = %x  PE set = %x max VS Reached = %x  max PE 
Reached = %x\n",
__func__,
DP_TRAINING_LANE0_SET,
dpcd_lane[0].bits.VOLTAGE_SWING_SET,
@@ -872,9 +870,8 @@ static bool perform_clock_recovery_sequence(
if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
ASSERT(0);
dm_logger_write(link->ctx->logger, LOG_ERROR,
-   "%s: Link Training Error, could not \
-get CR after %d tries. \
-   Possibly voltage swing issue", __func__,
+   "%s: Link Training Error, could not get CR after %d 
tries. Possibly voltage swing issue",
+   __func__,
LINK_TRAINING_MAX_CR_RETRY);
 
}
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
index d1af1483c69b..813f827e4270 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
@@ -523,8 +523,7 @@ static int get_pcie_table(
if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
else
-   pr_err("Number of Pcie Entries exceed the number of 
SCLK Dpm Levels! \
-   Disregarding the excess entries... \n");
+   pr_err("Number of Pcie Entries exceed the number of 
SCLK Dpm Levels! Disregarding the excess entries...\n");
 
pcie_table->count = pcie_count;
for (i = 0; i < pcie_count; i++) {
@@ -563,8 +562,7 @@ static int get_pcie_table(
if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
else
-   pr_err("Number of Pcie Entries exceed the number of 
SCLK Dpm Levels! \
-   Disregarding the excess entries... \n");
+   pr_err("Number of Pcie Entries exceed the number of 
SCLK Dpm Levels! Disregarding the excess entries...\n");
 
pcie_table->count = pcie_count;
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 4f79c21f27ed..9599fe0ba779 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -546,8 +546,7 @@ static void vega10_patch_with_vdd_leakage(struct pp_hwmgr 
*hwmgr,
}
 
if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
-   pr_info("Voltage value looks like a Leakage ID \
-   but it's not patched\n");
+   pr_info("Voltage value looks like a Leakage ID but it's not 
patched\n");
 }
 
 /**
@@ -701,18 +700,14 @@ static int 
vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
table_info->vdd_dep_on_mclk;
 
PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
-   "VDD dependency on SCLK table is missing. \
-   This table is mandatory", return -EINVAL);
+   "VDD dependency on SCLK table is missing. This 

Re: [PATCH 2/4] drm: amd: Fix line continuation formats

[Joe Perches]

On Thu, 2017-11-16 at 10:38 -0500, Harry Wentland wrote:
> On 2017-11-16 10:27 AM, Joe Perches wrote:
> > Line continuations with excess spacing causes unexpected output.
[]
> > @@ -872,9 +870,8 @@ static bool perform_clock_recovery_sequence(
> > if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
> > ASSERT(0);
> > dm_logger_write(link->ctx->logger, LOG_ERROR,
> > -   "%s: Link Training Error, could not \
> > -get CR after %d tries. \
> > -   Possibly voltage swing issue", __func__,
> > +   "%s: Link Training Error, could not get CR after %d 
> > tries. Possibly voltage swing issue",
> 
> Would probably be good to add a '\n' here as well but that's not the main 
> intention of this patch.

About 1/4 of the dm_logger_write calls are missing
newlines and I think it should be a separate patch.

I encourage you to fix them one day.

> Reviewed-by: Harry Wentland 

cheers, Joe
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[PATCH 17/25] drm/amd/display: Do DC mode-change check when adding CRTCs

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

Within atomic check, dm_update_crtcs_state is called twice. First to
remove from the dc_state, and subsequently to add to it.

In both calls, a secondary mode-change check is done using dc-level
states. We shouldn't be doing this while removing, since a new
dc_stream_state has not been created to do the necessary comparison.
Because of this, the mode_changed flag within the DRM state can be
mistakenly set to false. Doing so only when adding prevents this.

We are also guaranteed that a call to add will come after remove, or
else the atomic check fails (and a commit will not happen).

Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d10f8c09469b..05bc98d74a33 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4535,7 +4535,7 @@ static int dm_update_crtcs_state(struct dc *dc,
}
}
 
-   if (dc_is_stream_unchanged(new_stream, 
dm_old_crtc_state->stream) &&
+   if (enable && dc_is_stream_unchanged(new_stream, 
dm_old_crtc_state->stream) &&
dc_is_stream_scaling_unchanged(new_stream, 
dm_old_crtc_state->stream)) {
 
new_crtc_state->mode_changed = false;
-- 
2.14.1

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[PATCH 22/25] drm/amd/display: DMCU and ABM maintenance and refactor

[Harry Wentland]

From: Anthony Koo 

Remove some globals that should really be per block state.

Signed-off-by: Anthony Koo 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c  | 32 +++
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 18 ---
 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h   | 10 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h  |  4 +++-
 4 files changed, 36 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
index 0e0336c5af4e..3fe8e697483f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c
@@ -51,16 +51,6 @@
 
 #define MCP_DISABLE_ABM_IMMEDIATELY 255
 
-struct abm_backlight_registers {
-   unsigned int BL_PWM_CNTL;
-   unsigned int BL_PWM_CNTL2;
-   unsigned int BL_PWM_PERIOD_CNTL;
-   unsigned int LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV;
-};
-
-/* registers setting needs to be save and restored used at InitBacklight */
-static struct abm_backlight_registers stored_backlight_registers = {0};
-
 
 static unsigned int get_current_backlight_16_bit(struct dce_abm *abm_dce)
 {
@@ -347,16 +337,16 @@ static bool dce_abm_init_backlight(struct abm *abm)
 */
REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, );
if (value == 0 || value == 1) {
-   if (stored_backlight_registers.BL_PWM_CNTL != 0) {
+   if (abm->stored_backlight_registers.BL_PWM_CNTL != 0) {
REG_WRITE(BL_PWM_CNTL,
-   stored_backlight_registers.BL_PWM_CNTL);
+   abm->stored_backlight_registers.BL_PWM_CNTL);
REG_WRITE(BL_PWM_CNTL2,
-   stored_backlight_registers.BL_PWM_CNTL2);
+   abm->stored_backlight_registers.BL_PWM_CNTL2);
REG_WRITE(BL_PWM_PERIOD_CNTL,
-   stored_backlight_registers.BL_PWM_PERIOD_CNTL);
+   
abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL);
REG_UPDATE(LVTMA_PWRSEQ_REF_DIV,
BL_PWM_REF_DIV,
-   stored_backlight_registers.
+   abm->stored_backlight_registers.
LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
} else {
/* TODO: Note: This should not really happen since VBIOS
@@ -366,15 +356,15 @@ static bool dce_abm_init_backlight(struct abm *abm)
REG_WRITE(BL_PWM_PERIOD_CNTL, 0x000C0FA0);
}
} else {
-   stored_backlight_registers.BL_PWM_CNTL =
+   abm->stored_backlight_registers.BL_PWM_CNTL =
REG_READ(BL_PWM_CNTL);
-   stored_backlight_registers.BL_PWM_CNTL2 =
+   abm->stored_backlight_registers.BL_PWM_CNTL2 =
REG_READ(BL_PWM_CNTL2);
-   stored_backlight_registers.BL_PWM_PERIOD_CNTL =
+   abm->stored_backlight_registers.BL_PWM_PERIOD_CNTL =
REG_READ(BL_PWM_PERIOD_CNTL);
 
REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV,
-   _backlight_registers.
+   >stored_backlight_registers.
LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV);
}
 
@@ -450,6 +440,10 @@ static void dce_abm_construct(
 
base->ctx = ctx;
base->funcs = _funcs;
+   base->stored_backlight_registers.BL_PWM_CNTL = 0;
+   base->stored_backlight_registers.BL_PWM_CNTL2 = 0;
+   base->stored_backlight_registers.BL_PWM_PERIOD_CNTL = 0;
+   base->stored_backlight_registers.LVTMA_PWRSEQ_REF_DIV_BL_PWM_REF_DIV = 
0;
 
abm_dce->regs = regs;
abm_dce->abm_shift = abm_shift;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
index 508c1aa4a775..a6de99db0444 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c
@@ -53,7 +53,6 @@
 #define MCP_INIT_IRAM 0x89
 #define MCP_DMCU_VERSION 0x90
 #define MASTER_COMM_CNTL_REG__MASTER_COMM_INTERRUPT_MASK   0x0001L
-unsigned int cached_wait_loop_number = 0;
 
 static bool dce_dmcu_init(struct dmcu *dmcu)
 {
@@ -270,7 +269,7 @@ static void dce_psr_wait_loop(
 {
struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu);
union dce_dmcu_psr_config_data_wait_loop_reg1 masterCmdData1;
-   if (cached_wait_loop_number == wait_loop_number)
+   if (dmcu->cached_wait_loop_number == wait_loop_number)
return;
 
/* waitDMCUReadyForCmd */
@@ -278,7 +277,7 @@ static void 

[PATCH 21/25] drm/amd/display: Only program watermark for full update.

[Harry Wentland]

From: Yongqiang Sun 

For scaling and position change, it isn't necessary to program
watermark and check P-State as well.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c   |  4 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c  |  3 ++
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 46 +-
 3 files changed, 23 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 683fb5e111dc..ad65f62075ed 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1172,9 +1172,7 @@ static void commit_planes_for_stream(struct dc *dc,
if (update_type == UPDATE_TYPE_FULL) {
dc->hwss.set_bandwidth(dc, context, false);
context_clock_trace(dc, context);
-   }
 
-   if (update_type > UPDATE_TYPE_FAST) {
for (j = 0; j < dc->res_pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = 
>res_ctx.pipe_ctx[j];
 
@@ -1209,7 +1207,7 @@ static void commit_planes_for_stream(struct dc *dc,
}
}
 
-   if (update_type > UPDATE_TYPE_FAST)
+   if (update_type == UPDATE_TYPE_FULL)
context_timing_trace(dc, >res_ctx);
 
/* Perform requested Updates */
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
index 4b5b70907202..3eb824debf43 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
@@ -651,6 +651,8 @@ void dpp1_dscl_set_scaler_manual_scale(
if (memcmp(>scl_data, scl_data, sizeof(*scl_data)) == 0)
return;
 
+   PERF_TRACE();
+
dpp->scl_data = *scl_data;
 
/* Recout */
@@ -704,4 +706,5 @@ void dpp1_dscl_set_scaler_manual_scale(
SCL_H_NUM_TAPS_C, scl_data->taps.h_taps_c - 1);
 
dpp1_dscl_set_scl_filter(dpp, scl_data, ycbcr);
+   PERF_TRACE();
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 9641b36cbad4..522adceaf5d0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -2056,11 +2056,6 @@ static void program_all_pipe_in_tree(
 {
if (pipe_ctx->top_pipe == NULL) {
 
-   if (dc->debug.sanity_checks) {
-   /* pstate stuck check after watermark update */
-   dcn10_verify_allow_pstate_change_high(dc);
-   }
-
pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = 
pipe_ctx->pipe_dlg_param.vready_offset;
pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = 
pipe_ctx->pipe_dlg_param.vstartup_start;
pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = 
pipe_ctx->pipe_dlg_param.vupdate_offset;
@@ -2094,11 +2089,6 @@ static void program_all_pipe_in_tree(
dc->hwss.set_output_transfer_func(pipe_ctx, 
pipe_ctx->stream);
}
 
-   if (dc->debug.sanity_checks) {
-   /* pstate stuck check after each pipe is programmed */
-   dcn10_verify_allow_pstate_change_high(dc);
-   }
-
if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
 }
@@ -2183,6 +2173,7 @@ static void dcn10_apply_ctx_for_surface(
struct timing_generator *tg;
bool removed_pipe[4] = { false };
unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000;
+   bool program_water_mark = false;
 
struct pipe_ctx *top_pipe_to_program =
find_top_pipe_for_stream(dc, context, stream);
@@ -2192,9 +2183,6 @@ static void dcn10_apply_ctx_for_surface(
 
tg = top_pipe_to_program->stream_res.tg;
 
-   if (dc->debug.sanity_checks)
-   dcn10_verify_allow_pstate_change_high(dc);
-
tg->funcs->lock(tg);
 
if (num_planes == 0) {
@@ -2261,24 +2249,31 @@ static void dcn10_apply_ctx_for_surface(
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *old_pipe_ctx =
>current_state->res_ctx.pipe_ctx[i];
+   struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[i];
+
+   if (pipe_ctx->stream == stream &&
+   pipe_ctx->plane_state &&
+   pipe_ctx->plane_state->update_flags.bits.full_update)
+   program_water_mark = true;
 
if (removed_pipe[i] && num_planes == 0)
dcn10_disable_plane(dc, old_pipe_ctx);
   

[PATCH 18/25] drm/amd/display: Do not program front-end twice

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

The sequence of front-end > back-end > front-end programming will
program the front-end more than once. Add a mode_changed flag, and use
it to determine whether the front-end should be programmed before, or
after back-end.

Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 
 drivers/gpu/drm/amd/display/dc/core/dc.c  | 12 +---
 drivers/gpu/drm/amd/display/dc/dc_stream.h|  3 +++
 3 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 05bc98d74a33..19e00ec37db3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4049,6 +4049,19 @@ static void amdgpu_dm_commit_planes(struct 
drm_atomic_state *state,
}
 }
 
+/**
+ * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC
+ * @crtc_state: the DRM CRTC state
+ * @stream_state: the DC stream state.
+ *
+ * Copy the mirrored transient state flags from DRM, to DC. It is used to bring
+ * a dc_stream_state's flags in sync with a drm_crtc_state's flags.
+ */
+static void amdgpu_dm_crtc_copy_transient_flags(struct drm_crtc_state 
*crtc_state,
+   struct dc_stream_state 
*stream_state)
+{
+   stream_state->mode_changed = crtc_state->mode_changed;
+}
 
 static int amdgpu_dm_atomic_commit(struct drm_device *dev,
   struct drm_atomic_state *state,
@@ -4119,6 +4132,12 @@ static void amdgpu_dm_atomic_commit_tail(struct 
drm_atomic_state *state)
new_crtc_state->active_changed,
new_crtc_state->connectors_changed);
 
+   /* Copy all transient state flags into dc state */
+   if (dm_new_crtc_state->stream) {
+   
amdgpu_dm_crtc_copy_transient_flags(_new_crtc_state->base,
+   
dm_new_crtc_state->stream);
+   }
+
/* handles headless hotplug case, updating new_state and
 * aconnector as needed
 */
@@ -4601,6 +4620,7 @@ static int dm_update_crtcs_state(struct dc *dc,
WARN_ON(dm_new_crtc_state->stream);
 
dm_new_crtc_state->stream = new_stream;
+
dc_stream_retain(new_stream);
 
DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n",
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 199dfdc93263..683fb5e111dc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -666,10 +666,13 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
/* re-program planes for existing stream, in case we need to
 * free up plane resource for later use
 */
-   for (i = 0; i < dc->current_state->stream_count; i++) {
+   for (i = 0; i < context->stream_count; i++) {
+   if (context->streams[i]->mode_changed)
+   continue;
+
dc->hwss.apply_ctx_for_surface(
-   dc, dc->current_state->streams[i],
-   dc->current_state->stream_status[i].plane_count,
+   dc, context->streams[i],
+   context->stream_status[i].plane_count,
context); /* use new pipe config in new context */
}
 
@@ -695,6 +698,9 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
for (i = 0; i < context->stream_count; i++) {
const struct dc_sink *sink = context->streams[i]->sink;
 
+   if (!context->streams[i]->mode_changed)
+   continue;
+
dc->hwss.apply_ctx_for_surface(
dc, context->streams[i],
context->stream_status[i].plane_count,
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h 
b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 9a64cf16c798..fed0e5ea9625 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -92,6 +92,9 @@ struct dc_stream_state {
 
struct crtc_trigger_info triggered_crtc_reset;
 
+   /* Computed state bits */
+   bool mode_changed : 1;
+
 };
 
 struct dc_stream_update {
-- 
2.14.1

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[PATCH 09/25] drm/amd/display: fix split viewport rounding error

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c  |  4 
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 10 --
 2 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 88a004cc2690..45f358d88e7e 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -890,6 +890,10 @@ bool dcn_validate_bandwidth(
+ 
pipe->bottom_pipe->plane_res.scl_data.recout.width;
}
 
+   ASSERT(pipe->plane_res.scl_data.ratios.horz.value != 
dal_fixed31_32_one.value
+   || v->scaler_rec_out_width[input_idx] == 
v->viewport_width[input_idx]);
+   ASSERT(pipe->plane_res.scl_data.ratios.vert.value != 
dal_fixed31_32_one.value
+   || v->scaler_recout_height[input_idx] == 
v->viewport_height[input_idx]);
v->dcc_enable[input_idx] = 
pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
v->source_pixel_format[input_idx] = 
tl_pixel_format_to_bw_defs(
pipe->plane_state->format);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 8a823422896a..213f36d848fc 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -516,13 +516,11 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx)
right_view = (plane_state->rotation == 
ROTATION_ANGLE_270) != sec_split;
 
if (right_view) {
-   data->viewport.width /= 2;
-   data->viewport_c.width /= 2;
-   data->viewport.x +=  data->viewport.width;
-   data->viewport_c.x +=  data->viewport_c.width;
+   data->viewport.x +=  data->viewport.width / 2;
+   data->viewport_c.x +=  data->viewport_c.width / 2;
/* Ceil offset pipe */
-   data->viewport.width += data->viewport.width % 2;
-   data->viewport_c.width += data->viewport_c.width % 2;
+   data->viewport.width = (data->viewport.width + 1) / 2;
+   data->viewport_c.width = (data->viewport_c.width + 1) / 
2;
} else {
data->viewport.width /= 2;
data->viewport_c.width /= 2;
-- 
2.14.1

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[PATCH 19/25] drm/amd/display: Set full update flag in dcn_validate_bandwidth

[Harry Wentland]

From: Andrew Jiang 

Doing bandwidth validation implies that this is a full update. Set the
flag inside the function in case whatever is calling
dcn_validate_bandwidth doesn't set it.

Signed-off-by: Andrew Jiang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index f37fb7c3bf7d..a4fbca34bcdf 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -1013,6 +1013,8 @@ bool dcn_validate_bandwidth(
if (pipe->plane_state) {
struct pipe_ctx *hsplit_pipe = 
pipe->bottom_pipe;
 
+   
pipe->plane_state->update_flags.bits.full_update = 1;
+
if (v->dpp_per_plane[input_idx] == 2 ||
((pipe->stream->view_format ==
  VIEW_3D_FORMAT_SIDE_BY_SIDE ||
-- 
2.14.1

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[PATCH 07/25] drm/amd/display: Only update output transfer function for full type.

[Harry Wentland]

From: Yongqiang Sun 

dcn10_translate_regamma_to_hw_format costs 750us to run, it cannot be
called within isr, check update flag before calling, only do it for
full update.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 23 +++---
 1 file changed, 16 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index ad0e3b9be055..39869d379e3f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1211,9 +1211,17 @@ dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, 
OPP_REGAMMA_SRGB);
-   else if 
(dcn10_translate_regamma_to_hw_format(stream->out_transfer_func, 
>regamma_params))
-   dpp->funcs->dpp_program_regamma_pwl(dpp, >regamma_params, 
OPP_REGAMMA_USER);
-   else
+
+   /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when 
full
+* update.
+*/
+   else if (dcn10_translate_regamma_to_hw_format(
+   stream->out_transfer_func,
+   >regamma_params)) {
+   dpp->funcs->dpp_program_regamma_pwl(
+   dpp,
+   >regamma_params, OPP_REGAMMA_USER);
+   } else
dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, 
OPP_REGAMMA_BYPASS);
 
return true;
@@ -2076,16 +2084,17 @@ static void program_all_pipe_in_tree(
 
update_dchubp_dpp(dc, pipe_ctx, context);
 
-   if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state) {
+   if (cur_pipe_ctx->plane_state != pipe_ctx->plane_state)
dc->hwss.set_input_transfer_func(pipe_ctx, 
pipe_ctx->plane_state);
-   }
 
-   /*
+   /* dcn10_translate_regamma_to_hw_format takes 750us to finish
+* only do gamma programming for full update.
 * TODO: This can be further optimized/cleaned up
 * Always call this for now since it does memcmp inside before
 * doing heavy calculation and programming
 */
-   dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
+   if (pipe_ctx->plane_state->update_flags.bits.full_update)
+   dc->hwss.set_output_transfer_func(pipe_ctx, 
pipe_ctx->stream);
}
 
if (dc->debug.sanity_checks) {
-- 
2.14.1

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[PATCH 05/25] drm/amd/display: Remove unnecessary dc_link vtable

[Harry Wentland]

None of this needs to be a function table or dynamic in any way.

Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 89 
 drivers/gpu/drm/amd/display/dc/dc.h  | 20 ---
 2 files changed, 109 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 52fdd76811e8..199dfdc93263 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -233,93 +233,6 @@ void dc_stream_set_static_screen_events(struct dc *dc,
dc->hwss.set_static_screen_control(pipes_affected, num_pipes_affected, 
events);
 }
 
-static void set_drive_settings(struct dc *dc,
-   struct link_training_settings *lt_settings,
-   const struct dc_link *link)
-{
-
-   int i;
-
-   for (i = 0; i < dc->link_count; i++) {
-   if (dc->links[i] == link)
-   break;
-   }
-
-   if (i >= dc->link_count)
-   ASSERT_CRITICAL(false);
-
-   dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
-}
-
-static void perform_link_training(struct dc *dc,
-   struct dc_link_settings *link_setting,
-   bool skip_video_pattern)
-{
-   int i;
-
-   for (i = 0; i < dc->link_count; i++)
-   dc_link_dp_perform_link_training(
-   dc->links[i],
-   link_setting,
-   skip_video_pattern);
-}
-
-static void set_preferred_link_settings(struct dc *dc,
-   struct dc_link_settings *link_setting,
-   struct dc_link *link)
-{
-   link->preferred_link_setting = *link_setting;
-   dp_retrain_link_dp_test(link, link_setting, false);
-}
-
-static void enable_hpd(const struct dc_link *link)
-{
-   dc_link_dp_enable_hpd(link);
-}
-
-static void disable_hpd(const struct dc_link *link)
-{
-   dc_link_dp_disable_hpd(link);
-}
-
-
-static void set_test_pattern(
-   struct dc_link *link,
-   enum dp_test_pattern test_pattern,
-   const struct link_training_settings *p_link_settings,
-   const unsigned char *p_custom_pattern,
-   unsigned int cust_pattern_size)
-{
-   if (link != NULL)
-   dc_link_dp_set_test_pattern(
-   link,
-   test_pattern,
-   p_link_settings,
-   p_custom_pattern,
-   cust_pattern_size);
-}
-
-static void allocate_dc_stream_funcs(struct dc  *dc)
-{
-   dc->link_funcs.set_drive_settings =
-   set_drive_settings;
-
-   dc->link_funcs.perform_link_training =
-   perform_link_training;
-
-   dc->link_funcs.set_preferred_link_settings =
-   set_preferred_link_settings;
-
-   dc->link_funcs.enable_hpd =
-   enable_hpd;
-
-   dc->link_funcs.disable_hpd =
-   disable_hpd;
-
-   dc->link_funcs.set_test_pattern =
-   set_test_pattern;
-}
-
 static void destruct(struct dc *dc)
 {
dc_release_state(dc->current_state);
@@ -496,8 +409,6 @@ static bool construct(struct dc *dc,
if (!create_links(dc, init_params->num_virtual_links))
goto fail;
 
-   allocate_dc_stream_funcs(dc);
-
return true;
 
 fail:
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index dbb03b3e2c23..95d9406b0a6a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -146,25 +146,6 @@ struct dc_cap_funcs {
 
 struct link_training_settings;
 
-struct dc_link_funcs {
-   void (*set_drive_settings)(struct dc *dc,
-   struct link_training_settings *lt_settings,
-   const struct dc_link *link);
-   void (*perform_link_training)(struct dc *dc,
-   struct dc_link_settings *link_setting,
-   bool skip_video_pattern);
-   void (*set_preferred_link_settings)(struct dc *dc,
-   struct dc_link_settings *link_setting,
-   struct dc_link *link);
-   void (*enable_hpd)(const struct dc_link *link);
-   void (*disable_hpd)(const struct dc_link *link);
-   void (*set_test_pattern)(
-   struct dc_link *link,
-   enum dp_test_pattern test_pattern,
-   const struct link_training_settings *p_link_settings,
-   const unsigned char *p_custom_pattern,
-   unsigned int cust_pattern_size);
-};
 
 /* Structure to hold configuration flags set by dm at dc creation. */
 struct dc_config {
@@ -237,7 +218,6 @@ struct dce_hwseq;
 struct dc {
struct 

[PATCH 12/25] drm/amd/display: move csc matrix to hw_shared

[Harry Wentland]

From: Yue Hin Lau 

Signed-off-by: Yue Hin Lau 
Reviewed-by: Eric Bernstein 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c| 26 --
 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h  | 26 ++
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index b601a00fff74..4c90043e7b8c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -117,32 +117,6 @@ static const struct dcn10_input_csc_matrix 
dcn10_input_csc_matrix[] = {
0x2568, 0x43ee, 0xdbb2} }
 };
 
-struct output_csc_matrix {
-   enum dc_color_space color_space;
-   uint16_t regval[12];
-};
-
-static const struct output_csc_matrix output_csc_matrix[] = {
-   { COLOR_SPACE_SRGB,
-   { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
-   { COLOR_SPACE_SRGB_LIMITED,
-   { 0x1B67, 0, 0, 0x201, 0, 0x1B67, 0, 0x201, 0, 0, 0x1B67, 
0x201} },
-   { COLOR_SPACE_YCBCR601,
-   { 0xE04, 0xF444, 0xFDB9, 0x1004, 0x831, 0x1016, 0x320, 0x201, 
0xFB45,
-   0xF6B7, 0xE04, 0x1004} },
-   { COLOR_SPACE_YCBCR709,
-   { 0xE04, 0xF345, 0xFEB7, 0x1004, 0x5D3, 0x1399, 0x1FA,
-   0x201, 0xFCCA, 0xF533, 0xE04, 0x1004} },
-
-   /* TODO: correct values below */
-   { COLOR_SPACE_YCBCR601_LIMITED,
-   { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
-   0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 
0x1000} },
-   { COLOR_SPACE_YCBCR709_LIMITED,
-   { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
-   0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
-};
-
 static void program_gamut_remap(
struct dcn10_dpp *dpp,
const uint16_t *regval,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index a650ede413d1..ddc56700109b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -131,6 +131,32 @@ struct out_csc_color_matrix {
uint16_t regval[12];
 };
 
+struct output_csc_matrix {
+   enum dc_color_space color_space;
+   uint16_t regval[12];
+};
+
+static const struct output_csc_matrix output_csc_matrix[] = {
+   { COLOR_SPACE_SRGB,
+   { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
+   { COLOR_SPACE_SRGB_LIMITED,
+   { 0x1B67, 0, 0, 0x201, 0, 0x1B67, 0, 0x201, 0, 0, 0x1B67, 
0x201} },
+   { COLOR_SPACE_YCBCR601,
+   { 0xE04, 0xF444, 0xFDB9, 0x1004, 0x831, 0x1016, 0x320, 0x201, 
0xFB45,
+   0xF6B7, 0xE04, 0x1004} },
+   { COLOR_SPACE_YCBCR709,
+   { 0xE04, 0xF345, 0xFEB7, 0x1004, 0x5D3, 0x1399, 0x1FA,
+   0x201, 0xFCCA, 0xF533, 0xE04, 0x1004} },
+
+   /* TODO: correct values below */
+   { COLOR_SPACE_YCBCR601_LIMITED,
+   { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
+   0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 
0x1000} },
+   { COLOR_SPACE_YCBCR709_LIMITED,
+   { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
+   0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
+};
+
 enum opp_regamma {
OPP_REGAMMA_BYPASS = 0,
OPP_REGAMMA_SRGB,
-- 
2.14.1

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[PATCH 25/25] drm/amd/display: dal 3.1.20

[Harry Wentland]

From: Tony Cheng 

Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 33590c02265e..c99ed85ba9a2 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.19"
+#define DC_VER "3.1.20"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 23/25] drm/amd/display: dal 3.1.19

[Harry Wentland]

From: Tony Cheng 

Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 4a15f9c7068a..33590c02265e 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.18"
+#define DC_VER "3.1.19"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 13/25] drm/amd/display: fix mpo validation failure

[Harry Wentland]

From: Dmytro Laktyushkin 

There was an error in translation of mode support check.
"N/A" is a failure condition while "" was a special case.
This change will differentiate between the two by using a
define.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dml/display_mode_vba.c  | 120 +++--
 1 file changed, 36 insertions(+), 84 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index ea661ee44674..a02c69d10399 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -28,6 +28,8 @@
 
 #include "dml_inline_defs.h"
 
+#define BPP_INVALID 0
+#define BPP_BLENDED_PIPE 0x
 static const unsigned int NumberOfStates = DC__VOLTAGE_STATES;
 
 static void fetch_socbb_params(struct display_mode_lib *mode_lib);
@@ -3928,7 +3930,7 @@ static unsigned int TruncToValidBPP(
else if (DecimalBPP >= 12)
return 12;
else
-   return 0;
+   return BPP_INVALID;
} else if (Format == dm_444) {
if (DecimalBPP >= 36)
return 36;
@@ -3937,7 +3939,7 @@ static unsigned int TruncToValidBPP(
else if (DecimalBPP >= 24)
return 24;
else
-   return 0;
+   return BPP_INVALID;
} else {
if (DecimalBPP / 1.5 >= 24)
return 24;
@@ -3946,27 +3948,27 @@ static unsigned int TruncToValidBPP(
else if (DecimalBPP / 1.5 >= 16)
return 16;
else
-   return 0;
+   return BPP_INVALID;
}
} else {
if (DSCEnabled) {
if (Format == dm_420) {
if (DecimalBPP < 6)
-   return 0;
+   return BPP_INVALID;
else if (DecimalBPP >= 1.5 * 
DSCInputBitPerComponent - 1 / 16)
return 1.5 * DSCInputBitPerComponent - 
1 / 16;
else
return dml_floor(16 * DecimalBPP, 1) / 
16;
} else if (Format == dm_n422) {
if (DecimalBPP < 7)
-   return 0;
+   return BPP_INVALID;
else if (DecimalBPP >= 2 * 
DSCInputBitPerComponent - 1 / 16)
return 2 * DSCInputBitPerComponent - 1 
/ 16;
else
return dml_floor(16 * DecimalBPP, 1) / 
16;
} else {
if (DecimalBPP < 8)
-   return 0;
+   return BPP_INVALID;
else if (DecimalBPP >= 3 * 
DSCInputBitPerComponent - 1 / 16)
return 3 * DSCInputBitPerComponent - 1 
/ 16;
else
@@ -3980,7 +3982,7 @@ static unsigned int TruncToValidBPP(
else if (DecimalBPP >= 12)
return 12;
else
-   return 0;
+   return BPP_INVALID;
} else if (Format == dm_s422 || Format == dm_n422) {
if (DecimalBPP >= 24)
return 24;
@@ -3989,7 +3991,7 @@ static unsigned int TruncToValidBPP(
else if (DecimalBPP >= 16)
return 16;
else
-   return 0;
+   return BPP_INVALID;
} else {
if (DecimalBPP >= 36)
return 36;
@@ -3998,7 +4000,7 @@ static unsigned int TruncToValidBPP(
else if (DecimalBPP >= 24)
return 24;
else
-   return 0;
+   return BPP_INVALID;
}
}
 }
@@ -4922,11 +4924,7 @@ static void ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_
mode_lib->vba.ViewportSizeSupport[i] = true;
for (k = 0; k <= 

[PATCH 16/25] drm/amd/display: Trigger full update on plane change

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

With the optimized DCN10 frontend programming code, things are
programmed only when requested. For now, trigger a full update on all
plane changes.

Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8638f1c6764d..d10f8c09469b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4741,6 +4741,11 @@ static int dm_update_planes_state(struct dc *dc,
return ret;
}
 
+   /* Tell DC to do a full surface update every time there
+* is a plane change. Inefficient, but works for now.
+*/
+   
dm_new_plane_state->dc_state->update_flags.bits.full_update = 1;
+
*lock_and_validation_needed = true;
}
}
-- 
2.14.1

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[PATCH 15/25] drm/amd/display: Rename output_bpc to opp_input_bpc

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c  | 12 
 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h |  2 +-
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c |  2 +-
 3 files changed, 2 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index b6b0872f50dd..f37fb7c3bf7d 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -439,18 +439,6 @@ static void dcn_bw_calc_rq_dlg_ttu(
input.dout.output_format = (v->output_format[in_idx] == dcn_bw_420) ? 
dm_420 : dm_444;
input.dout.output_type  = (v->output[in_idx] == dcn_bw_hdmi) ? dm_hdmi 
: dm_dp;
//input[in_idx].dout.output_standard;
-   switch (v->output_deep_color[in_idx]) {
-   case dcn_bw_encoder_12bpc:
-   input.dout.output_bpc = dm_out_12;
-   break;
-   case dcn_bw_encoder_10bpc:
-   input.dout.output_bpc = dm_out_10;
-   break;
-   case dcn_bw_encoder_8bpc:
-   default:
-   input.dout.output_bpc = dm_out_8;
-   break;
-   }
 
/*todo: soc->sr_enter_plus_exit_time??*/
dlg_sys_param.t_srx_delay_us = dc->dcn_ip->dcfclk_cstate_latency / 
v->dcf_clk_deep_sleep;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
index baf182177736..2d9d6298f0d3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h
@@ -229,7 +229,7 @@ struct  _vcs_dpi_display_output_params_st   {
int output_bpp;
int dsc_enable;
int wb_enable;
-   int output_bpc;
+   int opp_input_bpc;
int output_type;
int output_format;
int output_standard;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index a02c69d10399..1f337ecfeab0 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -589,7 +589,7 @@ static void fetch_pipe_params(struct display_mode_lib 
*mode_lib)

mode_lib->vba.NumberOfDSCSlices[mode_lib->vba.NumberOfActivePlanes] =
dout->dsc_slices;

mode_lib->vba.DSCInputBitPerComponent[mode_lib->vba.NumberOfActivePlanes] =
-   dout->output_bpc == 0 ? 12 : dout->output_bpc;
+   dout->opp_input_bpc == 0 ? 12 : 
dout->opp_input_bpc;

mode_lib->vba.WritebackEnable[mode_lib->vba.NumberOfActivePlanes] = 
dout->wb_enable;

mode_lib->vba.WritebackSourceHeight[mode_lib->vba.NumberOfActivePlanes] =
dout->wb.wb_src_height;
-- 
2.14.1

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[PATCH 14/25] drm/amd/display: fix refclk conversion from khz int to mhz float

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 88a004cc2690..b6b0872f50dd 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -432,7 +432,7 @@ static void dcn_bw_calc_rq_dlg_ttu(
input.clks_cfg.dcfclk_mhz = v->dcfclk;
input.clks_cfg.dispclk_mhz = v->dispclk;
input.clks_cfg.dppclk_mhz = v->dppclk;
-   input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz/1000;
+   input.clks_cfg.refclk_mhz = dc->res_pool->ref_clock_inKhz / 1000.0;
input.clks_cfg.socclk_mhz = v->socclk;
input.clks_cfg.voltage = v->voltage_level;
 // dc->dml.logger = pool->base.logger;
-- 
2.14.1

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[PATCH 10/25] drm/amd/display: dal 3.1.17

[Harry Wentland]

From: Tony Cheng 

Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 95d9406b0a6a..8951c11882d9 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.16"
+#define DC_VER "3.1.17"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 24/25] drm/amd/display: Set OPP default values in init_hw

[Harry Wentland]

From: Andrew Jiang 

On S3 resume, we do not reconstruct OPP, but we do need to
reinitialize some of its values to the default ones.
Therefore, move those lines out of the OPP constructor and
into init_hw.

Also reset the hubp power gated flag, since nothing is
power gated at init_hw.

Signed-off-by: Andrew Jiang 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c| 16 
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c |  7 ---
 2 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 522adceaf5d0..8e2ddbc2129c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -743,13 +743,21 @@ static void dcn10_init_hw(struct dc *dc)
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct timing_generator *tg = 
dc->res_pool->timing_generators[i];
struct pipe_ctx *pipe_ctx = >res_ctx.pipe_ctx[i];
+   struct output_pixel_processor *opp = dc->res_pool->opps[i];
+   struct mpc_tree_cfg *mpc_tree = >mpc_tree;
+   struct hubp *hubp = dc->res_pool->hubps[i];
+
+   mpc_tree->dpp[0] = i;
+   mpc_tree->mpcc[0] = i;
+   mpc_tree->num_pipes = 1;
 
pipe_ctx->stream_res.tg = tg;
pipe_ctx->pipe_idx = i;
-   pipe_ctx->plane_res.hubp = dc->res_pool->hubps[i];
-   pipe_ctx->plane_res.hubp->mpcc_id = i;
-   pipe_ctx->plane_res.hubp->opp_id =
-   
dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i);
+
+   pipe_ctx->plane_res.hubp = hubp;
+   hubp->mpcc_id = i;
+   hubp->opp_id = 
dc->res_pool->mpc->funcs->get_opp_id(dc->res_pool->mpc, i);
+   hubp->power_gated = false;
 
plane_atomic_disconnect(dc, pipe_ctx);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index 341210060cf7..6d6f67b7d30e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -330,17 +330,10 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10,
const struct dcn10_opp_shift *opp_shift,
const struct dcn10_opp_mask *opp_mask)
 {
-   int i;
oppn10->base.ctx = ctx;
oppn10->base.inst = inst;
oppn10->base.funcs = _opp_funcs;
 
-   oppn10->base.mpc_tree.dpp[0] = inst;
-   oppn10->base.mpc_tree.mpcc[0] = inst;
-   oppn10->base.mpc_tree.num_pipes = 1;
-   for (i = 0; i < MAX_PIPES; i++)
-   oppn10->base.mpcc_disconnect_pending[i] = false;
-
oppn10->regs = regs;
oppn10->opp_shift = opp_shift;
oppn10->opp_mask = opp_mask;
-- 
2.14.1

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[PATCH 11/25] drm/amd/display: Revert noisy assert messages

[Harry Wentland]

From: Jordan Lazare 

This partially reverts
commit 4fb48bb66211 ("dc: fix split viewport rounding error").

Signed-off-by: Jordan Lazare 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 45f358d88e7e..88a004cc2690 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -890,10 +890,6 @@ bool dcn_validate_bandwidth(
+ 
pipe->bottom_pipe->plane_res.scl_data.recout.width;
}
 
-   ASSERT(pipe->plane_res.scl_data.ratios.horz.value != 
dal_fixed31_32_one.value
-   || v->scaler_rec_out_width[input_idx] == 
v->viewport_width[input_idx]);
-   ASSERT(pipe->plane_res.scl_data.ratios.vert.value != 
dal_fixed31_32_one.value
-   || v->scaler_recout_height[input_idx] == 
v->viewport_height[input_idx]);
v->dcc_enable[input_idx] = 
pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
v->source_pixel_format[input_idx] = 
tl_pixel_format_to_bw_defs(
pipe->plane_state->format);
-- 
2.14.1

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[PATCH 20/25] drm/amd/display: dal 3.1.18

[Harry Wentland]

From: Tony Cheng 

Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 8951c11882d9..4a15f9c7068a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.17"
+#define DC_VER "3.1.18"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
2.14.1

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[PATCH 01/25] drm/amd/display: call set_mpc_output_csc from hwsequencer

[Harry Wentland]

From: Yue Hin Lau 

Signed-off-by: Yue Hin Lau 
Reviewed-by: Eric Bernstein 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c| 140 -
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  67 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h|  16 +++
 3 files changed, 156 insertions(+), 67 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index b4892f43cd77..b5541985e0d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -117,6 +117,33 @@ static const struct dcn10_input_csc_matrix 
dcn10_input_csc_matrix[] = {
0x2568, 0x43ee, 0xdbb2} }
 };
 
+struct output_csc_matrix {
+   enum dc_color_space color_space;
+   uint16_t regval[12];
+};
+
+static const struct output_csc_matrix output_csc_matrix[] = {
+   { COLOR_SPACE_SRGB,
+   { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
+   { COLOR_SPACE_SRGB_LIMITED,
+   { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 
0x200} },
+   { COLOR_SPACE_YCBCR601,
+   { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 
0xFB47,
+   0xF6B9, 0xE00, 0x1000} },
+   { COLOR_SPACE_YCBCR709,
+   { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
+   0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
+
+   /* TODO: correct values below */
+   { COLOR_SPACE_YCBCR601_LIMITED,
+   { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
+   0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
+   { COLOR_SPACE_YCBCR709_LIMITED,
+   { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
+   0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
+   { COLOR_SPACE_UNKNOWN,
+   { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }
+};
 
 
 static void program_gamut_remap(
@@ -223,68 +250,6 @@ void dpp1_cm_set_gamut_remap(
}
 }
 
-void dpp1_cm_set_output_csc_default(
-   struct dpp *dpp_base,
-   enum dc_color_space colorspace)
-{
-
-   struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
-   uint32_t ocsc_mode = 0;
-
-   switch (colorspace) {
-   case COLOR_SPACE_SRGB:
-   case COLOR_SPACE_2020_RGB_FULLRANGE:
-   ocsc_mode = 0;
-   break;
-   case COLOR_SPACE_SRGB_LIMITED:
-   case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
-   ocsc_mode = 1;
-   break;
-   case COLOR_SPACE_YCBCR601:
-   case COLOR_SPACE_YCBCR601_LIMITED:
-   ocsc_mode = 2;
-   break;
-   case COLOR_SPACE_YCBCR709:
-   case COLOR_SPACE_YCBCR709_LIMITED:
-   case COLOR_SPACE_2020_YCBCR:
-   ocsc_mode = 3;
-   break;
-   case COLOR_SPACE_UNKNOWN:
-   default:
-   break;
-   }
-
-   REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
-
-}
-
-static void dpp1_cm_get_reg_field(
-   struct dcn10_dpp *dpp,
-   struct xfer_func_reg *reg)
-{
-   reg->shifts.exp_region0_lut_offset = 
dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
-   reg->masks.exp_region0_lut_offset = 
dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET;
-   reg->shifts.exp_region0_num_segments = 
dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
-   reg->masks.exp_region0_num_segments = 
dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS;
-   reg->shifts.exp_region1_lut_offset = 
dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
-   reg->masks.exp_region1_lut_offset = 
dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET;
-   reg->shifts.exp_region1_num_segments = 
dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
-   reg->masks.exp_region1_num_segments = 
dpp->tf_mask->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS;
-
-   reg->shifts.field_region_end = 
dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B;
-   reg->masks.field_region_end = 
dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_B;
-   reg->shifts.field_region_end_slope = 
dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
-   reg->masks.field_region_end_slope = 
dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B;
-   reg->shifts.field_region_end_base = 
dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
-   reg->masks.field_region_end_base = 
dpp->tf_mask->CM_RGAM_RAMB_EXP_REGION_END_BASE_B;
-   reg->shifts.field_region_linear_slope = 
dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B;
-   

[PATCH 03/25] drm/amd/display: Update dchub and dpp as per update flags.

[Harry Wentland]

From: Yongqiang Sun 

Check update flags and update dchub and dpp as per flags,
reduce reg access from 347 to 200, duration time reduce
to 170us.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 191 +
 1 file changed, 117 insertions(+), 74 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index e08ad585b7b9..c92eba0f0df8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1878,47 +1878,10 @@ void build_prescale_params(struct  dc_bias_and_scale 
*bias_and_scale,
}
 }
 
-static void update_dchubp_dpp(
-   struct dc *dc,
-   struct pipe_ctx *pipe_ctx,
-   struct dc_state *context)
+static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
 {
-   struct dce_hwseq *hws = dc->hwseq;
-   struct hubp *hubp = pipe_ctx->plane_res.hubp;
-   struct dpp *dpp = pipe_ctx->plane_res.dpp;
-   struct dc_plane_state *plane_state = pipe_ctx->plane_state;
-   union plane_size size = plane_state->plane_size;
-   struct mpcc_cfg mpcc_cfg = {0};
-   struct pipe_ctx *top_pipe;
-   bool per_pixel_alpha = plane_state->per_pixel_alpha && 
pipe_ctx->bottom_pipe;
struct dc_bias_and_scale bns_params = {0};
 
-   /* TODO: proper fix once fpga works */
-   /* depends on DML calculation, DPP clock value may change dynamically */
-   enable_dppclk(
-   dc->hwseq,
-   pipe_ctx->pipe_idx,
-   pipe_ctx->stream_res.pix_clk_params.requested_pix_clk,
-   context->bw.dcn.calc_clk.dppclk_div);
-   dc->current_state->bw.dcn.cur_clk.dppclk_div =
-   context->bw.dcn.calc_clk.dppclk_div;
-   context->bw.dcn.cur_clk.dppclk_div = 
context->bw.dcn.calc_clk.dppclk_div;
-
-   /* TODO: Need input parameter to tell current DCHUB pipe tie to which 
OTG
-* VTG is within DCHUBBUB which is commond block share by each pipe 
HUBP.
-* VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
-*/
-   REG_UPDATE(DCHUBP_CNTL[pipe_ctx->pipe_idx], HUBP_VTG_SEL, 
pipe_ctx->stream_res.tg->inst);
-
-   hubp->funcs->hubp_setup(
-   hubp,
-   _ctx->dlg_regs,
-   _ctx->ttu_regs,
-   _ctx->rq_regs,
-   _ctx->pipe_dlg_param);
-
-   size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
-
// program the input csc
dpp->funcs->dpp_setup(dpp,
plane_state->format,
@@ -1930,6 +1893,17 @@ static void update_dchubp_dpp(
build_prescale_params(_params, plane_state);
if (dpp->funcs->dpp_program_bias_and_scale)
dpp->funcs->dpp_program_bias_and_scale(dpp, _params);
+}
+
+static void update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
+{
+   struct mpcc_cfg mpcc_cfg = {0};
+   struct hubp *hubp = pipe_ctx->plane_res.hubp;
+   struct pipe_ctx *top_pipe;
+   bool per_pixel_alpha =
+   pipe_ctx->plane_state->per_pixel_alpha && 
pipe_ctx->bottom_pipe;
+
+   /* TODO: proper fix once fpga works */
 
mpcc_cfg.dpp_id = hubp->inst;
mpcc_cfg.opp_id = pipe_ctx->stream_res.opp->inst;
@@ -1952,33 +1926,110 @@ static void update_dchubp_dpp(
&& per_pixel_alpha;
hubp->mpcc_id = dc->res_pool->mpc->funcs->add(dc->res_pool->mpc, 
_cfg);
hubp->opp_id = mpcc_cfg.opp_id;
+}
+
+static void update_scaler(struct pipe_ctx *pipe_ctx)
+{
+   bool per_pixel_alpha =
+   pipe_ctx->plane_state->per_pixel_alpha && 
pipe_ctx->bottom_pipe;
+
+   /* TODO: proper fix once fpga works */
 
pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
/* scaler configuration */
pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
pipe_ctx->plane_res.dpp, _ctx->plane_res.scl_data);
+}
 
-   hubp->funcs->mem_program_viewport(hubp,
-   _ctx->plane_res.scl_data.viewport, 
_ctx->plane_res.scl_data.viewport_c);
+static void update_dchubp_dpp(
+   struct dc *dc,
+   struct pipe_ctx *pipe_ctx,
+   struct dc_state *context)
+{
+   struct dce_hwseq *hws = dc->hwseq;
+   struct hubp *hubp = pipe_ctx->plane_res.hubp;
+   struct dpp *dpp = pipe_ctx->plane_res.dpp;
+   struct dc_plane_state *plane_state = pipe_ctx->plane_state;
+   union plane_size size = plane_state->plane_size;
 
-   /*gamut remap*/
-   program_gamut_remap(pipe_ctx);
+   /* depends on DML calculation, DPP clock value may 

[PATCH 08/25] drm/amd/display: update output csc matrix values

[Harry Wentland]

From: Yue Hin Lau 

Signed-off-by: Yue Hin Lau 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c| 33 ++
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  5 +---
 2 files changed, 16 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index b5541985e0d8..b601a00fff74 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -123,29 +123,26 @@ struct output_csc_matrix {
 };
 
 static const struct output_csc_matrix output_csc_matrix[] = {
-   { COLOR_SPACE_SRGB,
+   { COLOR_SPACE_SRGB,
{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
-   { COLOR_SPACE_SRGB_LIMITED,
-   { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 
0x200} },
-   { COLOR_SPACE_YCBCR601,
-   { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 
0xFB47,
-   0xF6B9, 0xE00, 0x1000} },
-   { COLOR_SPACE_YCBCR709,
-   { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
-   0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
-
-   /* TODO: correct values below */
-   { COLOR_SPACE_YCBCR601_LIMITED,
+   { COLOR_SPACE_SRGB_LIMITED,
+   { 0x1B67, 0, 0, 0x201, 0, 0x1B67, 0, 0x201, 0, 0, 0x1B67, 
0x201} },
+   { COLOR_SPACE_YCBCR601,
+   { 0xE04, 0xF444, 0xFDB9, 0x1004, 0x831, 0x1016, 0x320, 0x201, 
0xFB45,
+   0xF6B7, 0xE04, 0x1004} },
+   { COLOR_SPACE_YCBCR709,
+   { 0xE04, 0xF345, 0xFEB7, 0x1004, 0x5D3, 0x1399, 0x1FA,
+   0x201, 0xFCCA, 0xF533, 0xE04, 0x1004} },
+
+   /* TODO: correct values below */
+   { COLOR_SPACE_YCBCR601_LIMITED,
{ 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
-   0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
-   { COLOR_SPACE_YCBCR709_LIMITED,
+   0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 
0x1000} },
+   { COLOR_SPACE_YCBCR709_LIMITED,
{ 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
-   0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
-   { COLOR_SPACE_UNKNOWN,
-   { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} }
+   0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
 };
 
-
 static void program_gamut_remap(
struct dcn10_dpp *dpp,
const uint16_t *regval,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 39869d379e3f..9641b36cbad4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1686,7 +1686,6 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
}
 }
 
-//program ocsc matrix for dcn 2
 static void set_mpc_output_csc(struct dc *dc,
struct pipe_ctx *pipe_ctx,
enum dc_color_space colorspace,
@@ -1710,9 +1709,7 @@ static void set_mpc_output_csc(struct dc *dc,
opp_id,
_entry,
ocsc_mode);
-   }
-
-   else {
+   } else {
if (mpc->funcs->set_ocsc_default != NULL)
mpc->funcs->set_ocsc_default(mpc,
opp_id,
-- 
2.14.1

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[PATCH 04/25] drm/amd/display: fix opp header register define

[Harry Wentland]

From: Yue Hin Lau 

Signed-off-by: Yue Hin Lau 
Reviewed-by: Eric Bernstein 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h | 25 +---
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
index 4b1e51050d33..f3c298ec37fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h
@@ -46,6 +46,16 @@
 #define OPP_REG_LIST_DCN10(id) \
OPP_REG_LIST_DCN(id)
 
+#define OPP_COMMON_REG_VARIABLE_LIST \
+   uint32_t FMT_BIT_DEPTH_CONTROL; \
+   uint32_t FMT_CONTROL; \
+   uint32_t FMT_DITHER_RAND_R_SEED; \
+   uint32_t FMT_DITHER_RAND_G_SEED; \
+   uint32_t FMT_DITHER_RAND_B_SEED; \
+   uint32_t FMT_CLAMP_CNTL; \
+   uint32_t FMT_DYNAMIC_EXP_CNTL; \
+   uint32_t FMT_MAP420_MEMORY_CONTROL;
+
 #define OPP_MASK_SH_LIST_DCN(mask_sh) \
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \
OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \
@@ -97,6 +107,10 @@
type FMT_MAP420MEM_PWR_FORCE; \
type FMT_STEREOSYNC_OVERRIDE;
 
+struct dcn10_opp_registers {
+   OPP_COMMON_REG_VARIABLE_LIST
+};
+
 struct dcn10_opp_shift {
OPP_DCN10_REG_FIELD_LIST(uint8_t)
 };
@@ -105,17 +119,6 @@ struct dcn10_opp_mask {
OPP_DCN10_REG_FIELD_LIST(uint32_t)
 };
 
-struct dcn10_opp_registers {
-   uint32_t FMT_BIT_DEPTH_CONTROL;
-   uint32_t FMT_CONTROL;
-   uint32_t FMT_DITHER_RAND_R_SEED;
-   uint32_t FMT_DITHER_RAND_G_SEED;
-   uint32_t FMT_DITHER_RAND_B_SEED;
-   uint32_t FMT_CLAMP_CNTL;
-   uint32_t FMT_DYNAMIC_EXP_CNTL;
-   uint32_t FMT_MAP420_MEMORY_CONTROL;
-};
-
 struct dcn10_opp {
struct output_pixel_processor base;
 
-- 
2.14.1

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[PATCH 02/25] drm/amd/display: Move update_plane_addr to apply_ctx_for_surface for dce.

[Harry Wentland]

From: Yongqiang Sun 

Move update_plane_addr to apply_ctx_for_surface, address update will
just be called once, not twice for updat type is full and medium.
This will reduce some reg access and duration time.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c| 4 ++--
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +++
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index b71422d636ac..52fdd76811e8 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1308,8 +1308,8 @@ static void commit_planes_for_stream(struct dc *dc,
if (pipe_ctx->plane_state != plane_state)
continue;
 
-   if (srf_updates[i].flip_addr)
-   dc->hwss.update_plane_addr(dc, pipe_ctx);
+   if (update_type == UPDATE_TYPE_FAST && 
srf_updates[i].flip_addr)
+   dc->hwss.update_plane_addr(dc, 
pipe_ctx);
}
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index ee3b9441e460..637624580b81 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2879,6 +2879,9 @@ static void dce110_apply_ctx_for_surface(
context->stream_count);
 
dce110_program_front_end_for_pipe(dc, pipe_ctx);
+
+   dc->hwss.update_plane_addr(dc, pipe_ctx);
+
program_surface_visibility(dc, pipe_ctx);
 
}
-- 
2.14.1

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[PATCH 06/25] drm/amd/display: performance profiling instrumentation

[Harry Wentland]

From: Tony Cheng 

Signed-off-by: Tony Cheng 
Reviewed-by: Yongqiang Sun 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 4 
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 4 
 drivers/gpu/drm/amd/display/dc/dm_services.h   | 7 +++
 3 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 82269caedc07..56e549249134 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -41,6 +41,10 @@ unsigned long long dm_get_timestamp(struct dc_context *ctx)
return 0;
 }
 
+void dm_perf_trace_timestamp(const char *func_name, unsigned int line)
+{
+}
+
 bool dm_write_persistent_data(struct dc_context *ctx,
const struct dc_sink *sink,
const char *module_name,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index c92eba0f0df8..ad0e3b9be055 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1047,6 +1047,8 @@ dcn10_translate_regamma_to_hw_format(const struct 
dc_transfer_func *output_tf,
if (output_tf == NULL || regamma_params == NULL || output_tf->type == 
TF_TYPE_BYPASS)
return false;
 
+   PERF_TRACE();
+
arr_points = regamma_params->arr_points;
rgb_resulted = regamma_params->rgb_resulted;
hw_points = 0;
@@ -1189,6 +1191,8 @@ dcn10_translate_regamma_to_hw_format(const struct 
dc_transfer_func *output_tf,
 
convert_to_custom_float(rgb_resulted, arr_points, hw_points);
 
+   PERF_TRACE();
+
return true;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h 
b/drivers/gpu/drm/amd/display/dc/dm_services.h
index d4917037ac42..225b7bfb09a9 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -372,6 +372,13 @@ bool dm_dmcu_set_pipe(struct dc_context *ctx, unsigned int 
controller_id);
 
 unsigned long long dm_get_timestamp(struct dc_context *ctx);
 
+/*
+ * performance tracing
+ */
+void dm_perf_trace_timestamp(const char *func_name, unsigned int line);
+#define PERF_TRACE()   dm_perf_trace_timestamp(__func__, __LINE__)
+
+
 /*
  * Debug and verification hooks
  */
-- 
2.14.1

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[PATCH 00/25] DC Patches Nov 15, 2017

[Harry Wentland]

 * Bunch of changes to get frontend/backend programming right on DCN
 * Some more fixes for DCN
 * Bunch of minor cleanups

Some smatch fixups are still in the pipeline and just missed this set.

Andrew Jiang (2):
  drm/amd/display: Set full update flag in dcn_validate_bandwidth
  drm/amd/display: Set OPP default values in init_hw

Anthony Koo (1):
  drm/amd/display: DMCU and ABM maintenance and refactor

Dmytro Laktyushkin (4):
  drm/amd/display: fix split viewport rounding error
  drm/amd/display: fix mpo validation failure
  drm/amd/display: fix refclk conversion from khz int to mhz float
  drm/amd/display: Rename output_bpc to opp_input_bpc

Harry Wentland (1):
  drm/amd/display: Remove unnecessary dc_link vtable

Jordan Lazare (1):
  drm/amd/display: Revert noisy assert messages

Leo (Sunpeng) Li (3):
  drm/amd/display: Trigger full update on plane change
  drm/amd/display: Do DC mode-change check when adding CRTCs
  drm/amd/display: Do not program front-end twice

Tony Cheng (5):
  drm/amd/display: performance profiling instrumentation
  drm/amd/display: dal 3.1.17
  drm/amd/display: dal 3.1.18
  drm/amd/display: dal 3.1.19
  drm/amd/display: dal 3.1.20

Yongqiang Sun (4):
  drm/amd/display: Move update_plane_addr to apply_ctx_for_surface for
dce.
  drm/amd/display: Update dchub and dpp as per update flags.
  drm/amd/display: Only update output transfer function for full type.
  drm/amd/display: Only program watermark for full update.

Yue Hin Lau (4):
  drm/amd/display: call set_mpc_output_csc from hwsequencer
  drm/amd/display: fix opp header register define
  drm/amd/display: update output csc matrix values
  drm/amd/display: move csc matrix to hw_shared

 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |  27 +-
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c |   4 +
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |  16 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c   | 109 +--
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |  10 +-
 drivers/gpu/drm/amd/display/dc/dc.h|  22 +-
 drivers/gpu/drm/amd/display/dc/dc_stream.h |   3 +
 drivers/gpu/drm/amd/display/dc/dce/dce_abm.c   |  32 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c  |  18 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|   3 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c| 115 ---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c  |   3 +
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  | 332 ++---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c   |   7 -
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.h   |  25 +-
 drivers/gpu/drm/amd/display/dc/dm_services.h   |   7 +
 .../drm/amd/display/dc/dml/display_mode_structs.h  |   2 +-
 .../gpu/drm/amd/display/dc/dml/display_mode_vba.c  | 122 +++-
 drivers/gpu/drm/amd/display/dc/inc/hw/abm.h|  10 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h   |   4 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h  |  26 ++
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h|  16 +
 22 files changed, 468 insertions(+), 445 deletions(-)

-- 
2.14.1

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Re: [PATCH 2/3] drm/amd/include:cleanup vega10 hdp header files.

[Alex Deucher]

On Thu, Nov 16, 2017 at 3:03 AM, Feifei Xu  wrote:
> Cleanup asic_reg/vega10/HDP folder, remove hdp_4_0_default.h
>
> Change-Id: Ia7cd2e660ceb89a1096c195c6a67677714ccbd69
> Signed-off-by: Feifei Xu 
> Reviewed-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  |   2 +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |   4 +-
>  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c |   2 +-
>  drivers/gpu/drm/amd/amdgpu/soc15.c |   4 +-
>  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  |   2 +-
>  drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c  |   2 +-
>  .../drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h  | 209 +++
>  .../drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h | 601 
> +
>  .../include/asic_reg/vega10/HDP/hdp_4_0_default.h  | 117 
>  .../include/asic_reg/vega10/HDP/hdp_4_0_offset.h   | 209 ---
>  .../include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h  | 601 
> -
>  11 files changed, 818 insertions(+), 935 deletions(-)
>  create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_offset.h
>  create mode 100644 drivers/gpu/drm/amd/include/asic_reg/hdp/hdp_4_0_sh_mask.h
>  delete mode 100644 
> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_default.h
>  delete mode 100644 
> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_offset.h
>  delete mode 100644 
> drivers/gpu/drm/amd/include/asic_reg/vega10/HDP/hdp_4_0_sh_mask.h

Is there a reason to remove hdp_4_0_default.h?  It's useful if we ever
need to get the default values of the registers.  I think we should
try and keep the register headers consistent.  If we aren't using any
of the default headers, that's fine, we can remove them.

Alex
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[PATCH] drm/amd/display: no distinct handling of cursor required

[S, Shirish]

From: Shirish S 

Currently the atomic check code uses legacy_cursor_update to differnetiate if 
the cursor plane is being requested by the user, which is not required as we 
shall be updating plane only if modeset is requested/required.

Have tested cursor plane and underlay get updated seamlessly, without any lag 
or frame drops.

Signed-off-by: Shirish S 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 41 +++
 1 file changed, 12 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 8638f1c..2df2e32 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4752,8 +4752,6 @@ static int dm_update_planes_state(struct dc *dc,  static 
int amdgpu_dm_atomic_check(struct drm_device *dev,
  struct drm_atomic_state *state)
 {
-   int i;
-   int ret;
struct amdgpu_device *adev = dev->dev_private;
struct dc *dc = adev->dm.dc;
struct dm_atomic_state *dm_state = to_dm_atomic_state(state); @@ 
-4761,6 +4759,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
struct drm_connector_state *old_con_state, *new_con_state;
struct drm_crtc *crtc;
struct drm_crtc_state *old_crtc_state, *new_crtc_state;
+   int ret, i;
 
/*
 * This bool will be set for true for any modeset/reset @@ -4772,36 
+4771,20 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
 
-   /*
-* legacy_cursor_update should be made false for SoC's having
-* a dedicated hardware plane for cursor in amdgpu_dm_atomic_commit(),
-* otherwise for software cursor plane,
-* we should not add it to list of affected planes.
-*/
-   if (state->legacy_cursor_update) {
-   for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
-   if (new_crtc_state->color_mgmt_changed) {
-   ret = drm_atomic_add_affected_planes(state, 
crtc);
-   if (ret)
-   goto fail;
-   }
-   }
-   } else {
-   for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 
new_crtc_state, i) {
-   if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
-   continue;
+   for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, 
new_crtc_state, i) {
+   if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
+   continue;
 
-   if (!new_crtc_state->enable)
-   continue;
+   if (!new_crtc_state->enable)
+   continue;
 
-   ret = drm_atomic_add_affected_connectors(state, crtc);
-   if (ret)
-   return ret;
+   ret = drm_atomic_add_affected_connectors(state, crtc);
+   if (ret)
+   return ret;
 
-   ret = drm_atomic_add_affected_planes(state, crtc);
-   if (ret)
-   goto fail;
-   }
+   ret = drm_atomic_add_affected_planes(state, crtc);
+   if (ret)
+   goto fail;
}
 
dm_state->context = dc_create_state();
--
2.7.4

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[PATCH libdrm 2/3] headers: sync up amdgpu_drm.h with proposed change

[Christian König]

Sync up the not yet upstream change for the next patch.

Signed-off-by: Christian König 
---
 include/drm/amdgpu_drm.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index 919248fb..a023b476 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -869,6 +869,10 @@ struct drm_amdgpu_info_device {
__u32 _pad1;
/* always on cu bitmap */
__u32 cu_ao_bitmap[4][4];
+   /** Starting high virtual address for UMDs. */
+   __u64 high_va_offset;
+   /** The maximum high virtual address */
+   __u64 high_va_max;
 };
 
 struct drm_amdgpu_info_hw_ip {
-- 
2.11.0

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[PATCH libdrm 3/3] amdgpu: use the high VA range if possible

[Christian König]

Retire the 32bit range and the low range on Vega10. AFAIK THe 32bit
range was never used by any open source component and this frees up
everything below 0x8000 for HMM.

Signed-off-by: Christian König 
---
 amdgpu/amdgpu_device.c | 21 ++---
 1 file changed, 14 insertions(+), 7 deletions(-)

diff --git a/amdgpu/amdgpu_device.c b/amdgpu/amdgpu_device.c
index fa4ab0e7..6a7af011 100644
--- a/amdgpu/amdgpu_device.c
+++ b/amdgpu/amdgpu_device.c
@@ -270,13 +270,20 @@ int amdgpu_device_initialize(int fd,
goto cleanup;
}
 
-   start = dev->dev_info.virtual_address_offset;
-   max = MIN2(dev->dev_info.virtual_address_max, 0x1ULL);
-   amdgpu_vamgr_init(>vamgr_32, start, max,
- dev->dev_info.virtual_address_alignment);
-
-   start = MAX2(dev->dev_info.virtual_address_offset, 0x1ULL);
-   max = MAX2(dev->dev_info.virtual_address_max, 0x1ULL);
+   if (dev->dev_info.high_va_offset && dev->dev_info.high_va_max) {
+   amdgpu_vamgr_init(>vamgr_32, 0, 0, 0);
+
+   start = dev->dev_info.high_va_offset;
+   max = dev->dev_info.high_va_max;
+   } else {
+   start = dev->dev_info.virtual_address_offset;
+   max = MIN2(dev->dev_info.virtual_address_max, 0x1ULL);
+   amdgpu_vamgr_init(>vamgr_32, start, max,
+ dev->dev_info.virtual_address_alignment);
+
+   start = MAX2(dev->dev_info.virtual_address_offset, 
0x1ULL);
+   max = MAX2(dev->dev_info.virtual_address_max, 0x1ULL);
+   }
amdgpu_vamgr_init(>vamgr, start, max,
  dev->dev_info.virtual_address_alignment);
 
-- 
2.11.0

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[PATCH 2/3] drm/amdgpu: use dev_dbg instead of dev_err in the VA IOCTL

[Christian König]

Userspace buggy userspace can spam the logs.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 432ec2924dc5..a8dc7b95f29a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -560,7 +560,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
int r = 0;
 
if (args->va_address < AMDGPU_VA_RESERVED_SIZE) {
-   dev_err(>pdev->dev,
+   dev_dbg(>pdev->dev,
"va_address 0x%LX is in reserved area 0x%LX\n",
args->va_address, AMDGPU_VA_RESERVED_SIZE);
return -EINVAL;
@@ -578,7 +578,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
args->va_address &= AMDGPU_VA_HOLE_MASK;
 
if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
-   dev_err(>pdev->dev, "invalid flags combination 0x%08X\n",
+   dev_dbg(>pdev->dev, "invalid flags combination 0x%08X\n",
args->flags);
return -EINVAL;
}
@@ -590,7 +590,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
case AMDGPU_VA_OP_REPLACE:
break;
default:
-   dev_err(>pdev->dev, "unsupported operation %d\n",
+   dev_dbg(>pdev->dev, "unsupported operation %d\n",
args->operation);
return -EINVAL;
}
-- 
2.11.0

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[PATCH 3/3] drm/amdgpu: expose the VA above the hole to userspace

[Christian König]

Let userspace know how much area we have above the 48bit VA hole on
Vega10.

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 12 ++--
 include/uapi/drm/amdgpu_drm.h   |  4 
 2 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index e84a7f7f642e..9875d64ae7d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -550,6 +550,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
}
case AMDGPU_INFO_DEV_INFO: {
struct drm_amdgpu_info_device dev_info = {};
+   uint64_t vm_size;
 
dev_info.device_id = dev->pdev->device;
dev_info.chip_rev = adev->rev_id;
@@ -577,10 +578,17 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
if (amdgpu_sriov_vf(adev))
dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
+
+   vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
dev_info.virtual_address_max =
-   min(adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE,
-   AMDGPU_VA_HOLE_START);
+   min(vm_size, AMDGPU_VA_HOLE_START);
+
+   vm_size -= AMDGPU_VA_RESERVED_SIZE;
+   if (vm_size > AMDGPU_VA_HOLE_START) {
+   dev_info.high_va_offset = AMDGPU_VA_HOLE_END;
+   dev_info.high_va_max = AMDGPU_VA_HOLE_END | vm_size;
+   }
dev_info.virtual_address_alignment = max((int)PAGE_SIZE, 
AMDGPU_GPU_PAGE_SIZE);
dev_info.pte_fragment_size = (1 << 
adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
index f7a4cf1b6ef6..1dc8089b480a 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -880,6 +880,10 @@ struct drm_amdgpu_info_device {
__u32 _pad1;
/* always on cu bitmap */
__u32 cu_ao_bitmap[4][4];
+   /** Starting high virtual address for UMDs. */
+   __u64 high_va_offset;
+   /** The maximum high virtual address */
+   __u64 high_va_max;
 };
 
 struct drm_amdgpu_info_hw_ip {
-- 
2.11.0

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[PATCH 1/3] drm/amdgpu: fix VA hole handling on Vega10 v2

[Christian König]

Similar to the CPU address space the VA on Vega10 has a hole in it.

v2: use dev_dbg instead of dev_err

Signed-off-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  | 10 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 11 +++
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c |  4 +++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h  |  5 +
 4 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index ee7736419411..fea4429d3f72 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -869,8 +869,8 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
struct amdgpu_bo_va_mapping *m;
struct amdgpu_bo *aobj = NULL;
struct amdgpu_cs_chunk *chunk;
+   uint64_t offset, va_start;
struct amdgpu_ib *ib;
-   uint64_t offset;
uint8_t *kptr;
 
chunk = >chunks[i];
@@ -880,14 +880,14 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device 
*adev,
if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
continue;
 
-   r = amdgpu_cs_find_mapping(p, chunk_ib->va_start,
-  , );
+   va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
+   r = amdgpu_cs_find_mapping(p, va_start, , );
if (r) {
DRM_ERROR("IB va_start is invalid\n");
return r;
}
 
-   if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
+   if ((va_start + chunk_ib->ib_bytes) >
(m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
DRM_ERROR("IB va_start+ib_bytes is invalid\n");
return -EINVAL;
@@ -900,7 +900,7 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
}
 
offset = m->start * AMDGPU_GPU_PAGE_SIZE;
-   kptr += chunk_ib->va_start - offset;
+   kptr += va_start - offset;
 
memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
amdgpu_bo_kunmap(aobj);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 04ddd782bf6d..432ec2924dc5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -566,6 +566,17 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
return -EINVAL;
}
 
+   if (args->va_address >= AMDGPU_VA_HOLE_START &&
+   args->va_address < AMDGPU_VA_HOLE_END) {
+   dev_dbg(>pdev->dev,
+   "va_address 0x%LX is in VA hole 0x%LX-0x%LX\n",
+   args->va_address, AMDGPU_VA_HOLE_START,
+   AMDGPU_VA_HOLE_END);
+   return -EINVAL;
+   }
+
+   args->va_address &= AMDGPU_VA_HOLE_MASK;
+
if ((args->flags & ~valid_flags) && (args->flags & ~prt_flags)) {
dev_err(>pdev->dev, "invalid flags combination 0x%08X\n",
args->flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 65360cde5342..e84a7f7f642e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -578,7 +578,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void 
*data, struct drm_file
if (amdgpu_sriov_vf(adev))
dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
-   dev_info.virtual_address_max = 
(uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
+   dev_info.virtual_address_max =
+   min(adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE,
+   AMDGPU_VA_HOLE_START);
dev_info.virtual_address_alignment = max((int)PAGE_SIZE, 
AMDGPU_GPU_PAGE_SIZE);
dev_info.pte_fragment_size = (1 << 
adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index e8f8896d18db..31cd57592546 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -96,6 +96,11 @@ struct amdgpu_bo_list_entry;
 /* hardcode that limit for now */
 #define AMDGPU_VA_RESERVED_SIZE(8ULL << 20)
 
+/* VA hole for 48bit addresses on Vega10 */
+#define AMDGPU_VA_HOLE_START   

Re: [PATCH] drm/amdgpu:cancel timer of virtual DCE(v2)

[Ding, Pixel]

I got it, the IH sw_fini is done later than DCE while your other patch cleans 
up timer in DCE sw_fini.
Maybe you can call amdgpu_irq_put() here, anyway your patch is already in:)
— 
Sincerely Yours,
Pixel







On 16/11/2017, 5:28 PM, "Ding, Pixel"  wrote:

>Hi Monk,
>
>I’m not for sure what issue you are fixing. The timer should be cancelled 
>while the IRQ is put to disable vblank . However there is a known rmmod issue 
>fixed with “02d319e drm/amdgpu/virtual_dce: Remove the rmmod error message”.
>
>Can you take a look at that patch or tell why or in which case the timer is 
>not cancelled during IRQ put?
>
>— 
>Sincerely Yours,
>Pixel
>
>
>
>
>
>
>
>On 16/11/2017, 2:06 PM, "amd-gfx on behalf of Monk Liu" 
> wrote:
>
>>virtual DCE Timer structure is already released
>>after its sw_fini(), so we need to cancel the
>>its Timer in hw_fini() otherwise the Timer canceling
>>is missed.
>>
>>v2:
>>use for loop and num_crtc to replace original code
>>
>>Change-Id: I03d6ca7aa07591d287da379ef4fe008f06edaff6
>>Signed-off-by: Monk Liu 
>>Reviewed-by: Alex Deucher 
>>---
>> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 10 ++
>> 1 file changed, 10 insertions(+)
>>
>>diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
>>b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
>>index cd4895b4..943efc3 100644
>>--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
>>+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
>>@@ -44,6 +44,9 @@ static void dce_virtual_set_display_funcs(struct 
>>amdgpu_device *adev);
>> static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
>> static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
>>int index);
>>+static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device 
>>*adev,
>>+ int crtc,
>>+ enum 
>>amdgpu_interrupt_state state);
>> 
>> /**
>>  * dce_virtual_vblank_wait - vblank wait asic callback.
>>@@ -550,6 +553,13 @@ static int dce_virtual_hw_init(void *handle)
>> 
>> static int dce_virtual_hw_fini(void *handle)
>> {
>>+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>>+ int i = 0;
>>+
>>+ for (i = 0; imode_info.num_crtc; i++)
>>+ if (adev->mode_info.crtcs[i])
>>+ dce_virtual_set_crtc_vblank_interrupt_state(adev, i, 
>>AMDGPU_IRQ_STATE_DISABLE);
>>+
>>  return 0;
>> }
>> 
>>-- 
>>2.7.4
>>
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RE: [PATCH] drm/amd/display: fix static checker warning

[S, Shirish]

Done, applied to amd-staging-drm-next.

Thanks.

Regards,
Shirish S


-Original Message-
From: Wentland, Harry 
Sent: Tuesday, November 14, 2017 8:56 PM
To: S, Shirish ; amd-gfx@lists.freedesktop.org
Cc: Dan Carpenter 
Subject: Re: [PATCH] drm/amd/display: fix static checker warning

On 2017-11-10 04:14 AM, S, Shirish wrote:
> From: Shirish S 
> 
> This patch fixes static checker warning of
> "warn: cast after binop" introduced by
> 56087b31 drm/amd/display: fix high part address in 
> dm_plane_helper_prepare_fb()
> 
> Signed-off-by: Shirish S 

Reviewed-by: Harry Wentland 

Feel free to push to amd-staging-drm-next at your leisure.

Harry

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index ed8b7524..0537523e 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -2955,7 +2955,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane 
> *plane,
>   = 
> lower_32_bits(afb->address);
>   
> plane_state->address.video_progressive.luma_addr.high_part
>   = 
> upper_32_bits(afb->address);
> - chroma_addr = afb->address + (u64)(awidth * 
> new_state->fb->height);
> + chroma_addr = afb->address + (u64)awidth * 
> new_state->fb->height;
>   
> plane_state->address.video_progressive.chroma_addr.low_part
>   = 
> lower_32_bits(chroma_addr);
>   
> plane_state->address.video_progressive.chroma_addr.high_part
> 
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Re: [PATCH] drm/amdgpu:cancel timer of virtual DCE(v2)

[Ding, Pixel]

Hi Monk,

I’m not for sure what issue you are fixing. The timer should be cancelled while 
the IRQ is put to disable vblank . However there is a known rmmod issue fixed 
with “02d319e drm/amdgpu/virtual_dce: Remove the rmmod error message”.

Can you take a look at that patch or tell why or in which case the timer is not 
cancelled during IRQ put?

— 
Sincerely Yours,
Pixel







On 16/11/2017, 2:06 PM, "amd-gfx on behalf of Monk Liu" 
 wrote:

>virtual DCE Timer structure is already released
>after its sw_fini(), so we need to cancel the
>its Timer in hw_fini() otherwise the Timer canceling
>is missed.
>
>v2:
>use for loop and num_crtc to replace original code
>
>Change-Id: I03d6ca7aa07591d287da379ef4fe008f06edaff6
>Signed-off-by: Monk Liu 
>Reviewed-by: Alex Deucher 
>---
> drivers/gpu/drm/amd/amdgpu/dce_virtual.c | 10 ++
> 1 file changed, 10 insertions(+)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c 
>b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
>index cd4895b4..943efc3 100644
>--- a/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
>+++ b/drivers/gpu/drm/amd/amdgpu/dce_virtual.c
>@@ -44,6 +44,9 @@ static void dce_virtual_set_display_funcs(struct 
>amdgpu_device *adev);
> static void dce_virtual_set_irq_funcs(struct amdgpu_device *adev);
> static int dce_virtual_connector_encoder_init(struct amdgpu_device *adev,
> int index);
>+static void dce_virtual_set_crtc_vblank_interrupt_state(struct amdgpu_device 
>*adev,
>+  int crtc,
>+  enum 
>amdgpu_interrupt_state state);
> 
> /**
>  * dce_virtual_vblank_wait - vblank wait asic callback.
>@@ -550,6 +553,13 @@ static int dce_virtual_hw_init(void *handle)
> 
> static int dce_virtual_hw_fini(void *handle)
> {
>+  struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>+  int i = 0;
>+
>+  for (i = 0; imode_info.num_crtc; i++)
>+  if (adev->mode_info.crtcs[i])
>+  dce_virtual_set_crtc_vblank_interrupt_state(adev, i, 
>AMDGPU_IRQ_STATE_DISABLE);
>+
>   return 0;
> }
> 
>-- 
>2.7.4
>
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Re: [PATCH libdrm] amdgpu: Disable deadlock test suite for Vega 10

[Christian König]

do I also need to push to our local tree ? 

No, I only push to the master branch all the time as well.

AMD local trees are only cherry picked from upstream as far as I know.

Regards,
Christian.

Am 16.11.2017 um 06:06 schrieb Andrey Grodzovsky:
Pushed to master branch of git.freedesktop.org/git/mesa/drm, do I also 
need to push to our local tree ?


Thanks,

Andrey

On 2017-11-15 04:31 AM, Christian König wrote:

Am 14.11.2017 um 15:07 schrieb Andrey Grodzovsky:

The suite stalls the CP, until RCA is done the suite is
disabled to not disrupt regression testing.

Signed-off-by: Andrey Grodzovsky 


Reviewed-by: Christian König 

Since you now have commit rights please try to push by yourself.

Thanks,
Christian.


---
  tests/amdgpu/amdgpu_test.c    |  2 +-
  tests/amdgpu/amdgpu_test.h    |  5 +
  tests/amdgpu/deadlock_tests.c | 19 +++
  3 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index 91010dc..ee64152 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -162,7 +162,7 @@ static Suites_Active_Status suites_active_stat[] 
= {

  },
  {
  .pName = DEADLOCK_TESTS_STR,
-    .pActive = always_active,
+    .pActive = suite_deadlock_tests_enable,
  },
  {
  .pName = VM_TESTS_STR,
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index dd236ed..414fcb8 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -160,6 +160,11 @@ int suite_deadlock_tests_init();
  int suite_deadlock_tests_clean();
    /**
+ * Decide if the suite is enabled by default or not.
+ */
+CU_BOOL suite_deadlock_tests_enable(void);
+
+/**
   * Tests in uvd enc test suite
   */
  extern CU_TestInfo deadlock_tests[];
diff --git a/tests/amdgpu/deadlock_tests.c 
b/tests/amdgpu/deadlock_tests.c

index f5c4552..84f4deb 100644
--- a/tests/amdgpu/deadlock_tests.c
+++ b/tests/amdgpu/deadlock_tests.c
@@ -36,6 +36,7 @@
    #include "amdgpu_test.h"
  #include "amdgpu_drm.h"
+#include "amdgpu_internal.h"
    #include 
  @@ -87,6 +88,24 @@ static void amdgpu_deadlock_helper(unsigned 
ip_type);

  static void amdgpu_deadlock_gfx(void);
  static void amdgpu_deadlock_compute(void);
  +CU_BOOL suite_deadlock_tests_enable(void)
+{
+    if (amdgpu_device_initialize(drm_amdgpu[0], _version,
+ _version, _handle))
+    return CU_FALSE;
+
+    if (amdgpu_device_deinitialize(device_handle))
+    return CU_FALSE;
+
+
+    if (device_handle->info.family_id == AMDGPU_FAMILY_AI) {
+    printf("\n\nCurrently hangs the CP on this ASIC, deadlock 
suite disabled\n");

+    return CU_FALSE;
+    }
+
+    return CU_TRUE;
+}
+
  int suite_deadlock_tests_init(void)
  {
  struct amdgpu_gpu_info gpu_info = {0};







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