Re: [PATCH 10/14] drm/amdkfd: Use ref count to prevent kfd_process destruction

[Felix Kuehling]

On 2017-11-28 04:52 AM, Christian König wrote:
> Am 28.11.2017 um 00:29 schrieb Felix Kuehling:
>> Use a reference counter instead of a lock to prevent process
>> destruction while functions running out of process context are using
>> the kfd_process structure. In many cases these functions don't need
>> the structure to be locked. In the few cases that really do need the
>> process lock, take it explicitly.
>>
>> This helps simplify lock dependencies between the process lock and
>> other locks, particularly amdgpu and mm_struct locks. This will be
>> important when amdgpu calls back to amdkfd for memory evictions.
>
> Actually that is not only an optimization or cleanup, but a rather
> important bug fix.
>
> Using a mutex as protection to prevent object deletion is illegal
> because mutex_unlock() can accesses the mutex object even after it is
> unlocked.
>
> See this LWN article as well https://lwn.net/Articles/575460/.
>
> If you have other use cases like this in the KFD it should better be
> fixed as well.

I'm not aware of other misuses of Mutexes in KFD.

The article sounded like this was likely to get fixed in the mutex
rather than hoping to track down all incorrect uses of Mutexes. Quote:
>
> As of this writing, no patches have been posted. It would be
> surprising, though, if a fix for this particular problem did not
> surface by the time the 3.14 merge window opens. Locking problems are
> hard enough to deal with when the locking primitives have simple and
> easily understood behavior; having subtle traps built into that layer
> of the kernel is a recipe for a lot of long-term pain.
>
I haven't found such a fix. That said, in the discussion under that
article some argued that the example would be broken even with a
spinlock. So maybe there is no such general fix.

Regards,
  Felix


>
>> Signed-off-by: Felix Kuehling 
>
> Acked-by: Christian König 
>
> Regards,
> Christian.
>
>> ---
>>   drivers/gpu/drm/amd/amdkfd/kfd_events.c  | 14 +++---
>>   drivers/gpu/drm/amd/amdkfd/kfd_priv.h    |  1 +
>>   drivers/gpu/drm/amd/amdkfd/kfd_process.c | 16 +---
>>   3 files changed, 21 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
>> b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
>> index cb92d4b..93aae5c 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c
>> @@ -441,7 +441,7 @@ void kfd_signal_event_interrupt(unsigned int
>> pasid, uint32_t partial_id,
>>   /*
>>    * Because we are called from arbitrary context (workqueue) as
>> opposed
>>    * to process context, kfd_process could attempt to exit while
>> we are
>> - * running so the lookup function returns a locked process.
>> + * running so the lookup function increments the process ref count.
>>    */
>>   struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
>>   @@ -493,7 +493,7 @@ void kfd_signal_event_interrupt(unsigned int
>> pasid, uint32_t partial_id,
>>   }
>>     mutex_unlock(>event_mutex);
>> -    mutex_unlock(>mutex);
>> +    kfd_unref_process(p);
>>   }
>>     static struct kfd_event_waiter *alloc_event_waiters(uint32_t
>> num_events)
>> @@ -847,7 +847,7 @@ void kfd_signal_iommu_event(struct kfd_dev *dev,
>> unsigned int pasid,
>>   /*
>>    * Because we are called from arbitrary context (workqueue) as
>> opposed
>>    * to process context, kfd_process could attempt to exit while
>> we are
>> - * running so the lookup function returns a locked process.
>> + * running so the lookup function increments the process ref count.
>>    */
>>   struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
>>   struct mm_struct *mm;
>> @@ -860,7 +860,7 @@ void kfd_signal_iommu_event(struct kfd_dev *dev,
>> unsigned int pasid,
>>    */
>>   mm = get_task_mm(p->lead_thread);
>>   if (!mm) {
>> -    mutex_unlock(>mutex);
>> +    kfd_unref_process(p);
>>   return; /* Process is exiting */
>>   }
>>   @@ -903,7 +903,7 @@ void kfd_signal_iommu_event(struct kfd_dev
>> *dev, unsigned int pasid,
>>   _exception_data);
>>     mutex_unlock(>event_mutex);
>> -    mutex_unlock(>mutex);
>> +    kfd_unref_process(p);
>>   }
>>     void kfd_signal_hw_exception_event(unsigned int pasid)
>> @@ -911,7 +911,7 @@ void kfd_signal_hw_exception_event(unsigned int
>> pasid)
>>   /*
>>    * Because we are called from arbitrary context (workqueue) as
>> opposed
>>    * to process context, kfd_process could attempt to exit while
>> we are
>> - * running so the lookup function returns a locked process.
>> + * running so the lookup function increments the process ref count.
>>    */
>>   struct kfd_process *p = kfd_lookup_process_by_pasid(pasid);
>>   @@ -924,5 +924,5 @@ void kfd_signal_hw_exception_event(unsigned int
>> pasid)
>>   lookup_events_by_type_and_signal(p,
>> 

Re: [PATCH v2] drm/amdgpu: Get rid of dep_sync as a seperate object.

[Andrey Grodzovsky]

On 12/01/2017 02:59 PM, Christian König wrote:

Am 01.12.2017 um 20:39 schrieb Andrey Grodzovsky:

Instead mark fence as explicit in it's amdgpu_sync_entry.

v2:
Fix use after free bug and add new parameter description.
Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  1 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c   | 14 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c  | 26 
--

  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 23 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h |  6 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 16 
  7 files changed, 48 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h

index f8657c3..c56a986 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1121,7 +1121,6 @@ struct amdgpu_job {
  struct amdgpu_vm    *vm;
  struct amdgpu_ring    *ring;
  struct amdgpu_sync    sync;
-    struct amdgpu_sync    dep_sync;
  struct amdgpu_sync    sched_sync;
  struct amdgpu_ib    *ibs;
  struct dma_fence    *fence; /* the hw fence */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

index d15836b..b694d35 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -788,7 +788,7 @@ static int amdgpu_bo_vm_update_pte(struct 
amdgpu_cs_parser *p)

  return r;
    r = amdgpu_sync_fence(adev, >job->sync,
-  fpriv->prt_va->last_pt_update);
+  fpriv->prt_va->last_pt_update, false);
  if (r)
  return r;
  @@ -802,7 +802,7 @@ static int amdgpu_bo_vm_update_pte(struct 
amdgpu_cs_parser *p)

  return r;
    f = bo_va->last_pt_update;
-    r = amdgpu_sync_fence(adev, >job->sync, f);
+    r = amdgpu_sync_fence(adev, >job->sync, f, false);
  if (r)
  return r;
  }
@@ -825,7 +825,7 @@ static int amdgpu_bo_vm_update_pte(struct 
amdgpu_cs_parser *p)

  return r;
    f = bo_va->last_pt_update;
-    r = amdgpu_sync_fence(adev, >job->sync, f);
+    r = amdgpu_sync_fence(adev, >job->sync, f, false);
  if (r)
  return r;
  }
@@ -836,7 +836,7 @@ static int amdgpu_bo_vm_update_pte(struct 
amdgpu_cs_parser *p)

  if (r)
  return r;
  -    r = amdgpu_sync_fence(adev, >job->sync, vm->last_update);
+    r = amdgpu_sync_fence(adev, >job->sync, vm->last_update, false);
  if (r)
  return r;
  @@ -1040,8 +1040,8 @@ static int amdgpu_cs_process_fence_dep(struct 
amdgpu_cs_parser *p,

  amdgpu_ctx_put(ctx);
  return r;
  } else if (fence) {
-    r = amdgpu_sync_fence(p->adev, >job->dep_sync,
-  fence);
+    r = amdgpu_sync_fence(p->adev, >job->sync, fence,
+    true);
  dma_fence_put(fence);
  amdgpu_ctx_put(ctx);
  if (r)
@@ -1060,7 +1060,7 @@ static int 
amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,

  if (r)
  return r;
  -    r = amdgpu_sync_fence(p->adev, >job->dep_sync, fence);
+    r = amdgpu_sync_fence(p->adev, >job->sync, fence, true);
  dma_fence_put(fence);
    return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c

index 659997b..0cf86eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -164,7 +164,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, 
unsigned num_ibs,

  }
    if (ring->funcs->emit_pipeline_sync && job &&
-    ((tmp = amdgpu_sync_get_fence(>sched_sync)) ||
+    ((tmp = amdgpu_sync_get_fence(>sched_sync, NULL)) ||
   amdgpu_vm_need_pipeline_sync(ring, job))) {
  need_pipe_sync = true;
  dma_fence_put(tmp);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c

index 18770a8..61fb934 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -60,7 +60,6 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, 
unsigned num_ibs,

  (*job)->num_ibs = num_ibs;
    amdgpu_sync_create(&(*job)->sync);
-    amdgpu_sync_create(&(*job)->dep_sync);
  amdgpu_sync_create(&(*job)->sched_sync);
  (*job)->vram_lost_counter = atomic_read(>vram_lost_counter);
  @@ -104,7 +103,6 @@ static void amdgpu_job_free_cb(struct 
amd_sched_job *s_job)

  amdgpu_ring_priority_put(job->ring, s_job->s_priority);
  dma_fence_put(job->fence);
  amdgpu_sync_free(>sync);
-    amdgpu_sync_free(>dep_sync);
  amdgpu_sync_free(>sched_sync);
  kfree(job);
  }
@@ -115,7 +113,6 @@ void amdgpu_job_free(struct amdgpu_job 

[PATCH 3/5] drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array

[Shaoyun Liu]

Change-Id: I59828a9a10652988e22b50d87dd1ec9df8ae7a1d
Signed-off-by: Shaoyun Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  19 +++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 233 +++---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  20 +--
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c|  45 --
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h|   3 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c|  45 --
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h|   3 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 101 ++---
 drivers/gpu/drm/amd/amdgpu/soc15.c| 115 ++-
 drivers/gpu/drm/amd/amdgpu/soc15.h|  18 +++
 drivers/gpu/drm/amd/amdgpu/soc15_common.h |   6 -
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c |  13 +-
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c |  14 +-
 13 files changed, 352 insertions(+), 283 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1625e41..1d0e109 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1438,6 +1438,23 @@ struct amdgpu_fw_vram_usage {
 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, 
uint32_t);
 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, 
uint32_t);
 
+
+/*
+ * amdgpu nbio functions
+ *
+ * Fix me :
+ * Put more NBIO specifc func wraper here , for now just try to minimize 
the
+ * change to avoid use SOC15_REG_OFFSET in the constant array
+ */
+
+struct amdgpu_nbio_funcs {
+   u32 (*get_hdp_flush_req_offset)(struct amdgpu_device*);
+   u32 (*get_hdp_flush_done_offset)(struct amdgpu_device*);
+   u32 (*get_pcie_index_offset)(struct amdgpu_device*);
+   u32 (*get_pcie_data_offset)(struct amdgpu_device*);
+};
+
+
 /* Define the HW IP blocks will be used in driver , add more if necessary */
 enum amd_hw_ip_block_type {
GC_HWIP = 1,
@@ -1657,6 +1674,8 @@ struct amdgpu_device {
/* soc15 register offset based on ip, instance and  segment */
uint32_t*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
 
+   const struct amdgpu_nbio_funcs  *nbio_funcs;
+
/* delayed work_func for deferring clockgating during resume */
struct delayed_work late_init_work;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5497ed6..c39c50a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -65,152 +65,84 @@
 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
 
-static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
-{
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
- 

RE: [PATCH 3/5] drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array

[Liu, Shaoyun]

Please ignore this change , forgot to include uvd related changes as suggested 
. 

Regards
Shaoayun.liu

-Original Message-
From: Liu, Shaoyun 
Sent: Friday, December 01, 2017 2:58 PM
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Shaoyun
Subject: [PATCH 3/5] drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const 
array

Change-Id: I59828a9a10652988e22b50d87dd1ec9df8ae7a1d
Signed-off-by: Shaoyun Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  19 +++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 233 +++---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  20 +--
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c|  45 --
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h|   3 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c|  45 --
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h|   3 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 101 ++---
 drivers/gpu/drm/amd/amdgpu/soc15.c| 115 ++-
 drivers/gpu/drm/amd/amdgpu/soc15.h|  18 +++
 drivers/gpu/drm/amd/amdgpu/soc15_common.h |   6 -
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c |   2 +-
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c |   2 +-
 13 files changed, 331 insertions(+), 281 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1625e41..1d0e109 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1438,6 +1438,23 @@ struct amdgpu_fw_vram_usage {  typedef uint32_t 
(*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);  typedef 
void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, 
uint32_t);
 
+
+/*
+ * amdgpu nbio functions
+ *
+ * Fix me :
+ * Put more NBIO specifc func wraper here , for now just try to minimize 
the
+ * change to avoid use SOC15_REG_OFFSET in the constant array
+ */
+
+struct amdgpu_nbio_funcs {
+   u32 (*get_hdp_flush_req_offset)(struct amdgpu_device*);
+   u32 (*get_hdp_flush_done_offset)(struct amdgpu_device*);
+   u32 (*get_pcie_index_offset)(struct amdgpu_device*);
+   u32 (*get_pcie_data_offset)(struct amdgpu_device*); };
+
+
 /* Define the HW IP blocks will be used in driver , add more if necessary */  
enum amd_hw_ip_block_type {
GC_HWIP = 1,
@@ -1657,6 +1674,8 @@ struct amdgpu_device {
/* soc15 register offset based on ip, instance and  segment */
uint32_t*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
 
+   const struct amdgpu_nbio_funcs  *nbio_funcs;
+
/* delayed work_func for deferring clockgating during resume */
struct delayed_work late_init_work;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5497ed6..c39c50a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -65,152 +65,84 @@
 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
 
-static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = -{
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
-   

[PATCH 3/5] drm/amdgpu: Avoid use SOC15_REG_OFFSET in static const array

[Shaoyun Liu]

Change-Id: I59828a9a10652988e22b50d87dd1ec9df8ae7a1d
Signed-off-by: Shaoyun Liu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  19 +++
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 233 +++---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c |  20 +--
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c|  45 --
 drivers/gpu/drm/amd/amdgpu/nbio_v6_1.h|   3 +-
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c|  45 --
 drivers/gpu/drm/amd/amdgpu/nbio_v7_0.h|   3 +-
 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 101 ++---
 drivers/gpu/drm/amd/amdgpu/soc15.c| 115 ++-
 drivers/gpu/drm/amd/amdgpu/soc15.h|  18 +++
 drivers/gpu/drm/amd/amdgpu/soc15_common.h |   6 -
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c |   2 +-
 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c |   2 +-
 13 files changed, 331 insertions(+), 281 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 1625e41..1d0e109 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1438,6 +1438,23 @@ struct amdgpu_fw_vram_usage {
 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, 
uint32_t);
 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, 
uint32_t);
 
+
+/*
+ * amdgpu nbio functions
+ *
+ * Fix me :
+ * Put more NBIO specifc func wraper here , for now just try to minimize 
the
+ * change to avoid use SOC15_REG_OFFSET in the constant array
+ */
+
+struct amdgpu_nbio_funcs {
+   u32 (*get_hdp_flush_req_offset)(struct amdgpu_device*);
+   u32 (*get_hdp_flush_done_offset)(struct amdgpu_device*);
+   u32 (*get_pcie_index_offset)(struct amdgpu_device*);
+   u32 (*get_pcie_data_offset)(struct amdgpu_device*);
+};
+
+
 /* Define the HW IP blocks will be used in driver , add more if necessary */
 enum amd_hw_ip_block_type {
GC_HWIP = 1,
@@ -1657,6 +1674,8 @@ struct amdgpu_device {
/* soc15 register offset based on ip, instance and  segment */
uint32_t*reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
 
+   const struct amdgpu_nbio_funcs  *nbio_funcs;
+
/* delayed work_func for deferring clockgating during resume */
struct delayed_work late_init_work;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5497ed6..c39c50a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -65,152 +65,84 @@
 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
 
-static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] =
-{
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID1_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID1),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID1) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID2_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID2),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID2) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID3_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID3),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID3) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID4_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID4),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID4) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID5_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID5),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID5) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID6_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID6),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID6) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID7_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID7),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID7) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID8_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID8),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID8) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID9_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID9),
- SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID9) },
-   { SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_BASE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_VMID10_SIZE),
- SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID10),
- 

Re: [PATCH 1/2] drm/amdgpu: add license to Makefiles

[Felix Kuehling]

Thanks Alex. The series is Acked-by: Felix Kuehling 


On 2017-11-30 09:30 PM, Alex Deucher wrote:
> Was missing license text.
>
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/acp/Makefile   | 21 
>  drivers/gpu/drm/amd/amdgpu/Makefile| 21 
>  drivers/gpu/drm/amd/amdkfd/Makefile| 21 
>  drivers/gpu/drm/amd/display/Makefile   | 21 
>  drivers/gpu/drm/amd/display/amdgpu_dm/Makefile | 21 
>  drivers/gpu/drm/amd/display/dc/Makefile| 21 
>  drivers/gpu/drm/amd/display/dc/basics/Makefile | 21 
>  drivers/gpu/drm/amd/display/dc/bios/Makefile   | 21 
>  drivers/gpu/drm/amd/display/dc/calcs/Makefile  | 21 
>  drivers/gpu/drm/amd/display/dc/dce/Makefile| 21 
>  drivers/gpu/drm/amd/display/dc/dce100/Makefile | 21 
>  drivers/gpu/drm/amd/display/dc/dce110/Makefile | 21 
>  drivers/gpu/drm/amd/display/dc/dce112/Makefile | 21 
>  drivers/gpu/drm/amd/display/dc/dce120/Makefile | 23 
> +-
>  drivers/gpu/drm/amd/display/dc/dce80/Makefile  | 21 
>  drivers/gpu/drm/amd/display/dc/dcn10/Makefile  | 21 
>  drivers/gpu/drm/amd/display/dc/dml/Makefile| 21 
>  drivers/gpu/drm/amd/display/dc/gpio/Makefile   | 21 
>  drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 21 
>  drivers/gpu/drm/amd/display/dc/irq/Makefile| 21 
>  drivers/gpu/drm/amd/display/dc/virtual/Makefile| 21 
>  .../gpu/drm/amd/display/modules/freesync/Makefile  | 21 
>  drivers/gpu/drm/amd/lib/Makefile   | 21 
>  drivers/gpu/drm/amd/powerplay/Makefile | 21 
>  drivers/gpu/drm/amd/powerplay/hwmgr/Makefile   | 21 
>  drivers/gpu/drm/amd/powerplay/smumgr/Makefile  | 21 
>  26 files changed, 547 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/acp/Makefile 
> b/drivers/gpu/drm/amd/acp/Makefile
> index 8a08e81ee90d..d4176a3fb706 100644
> --- a/drivers/gpu/drm/amd/acp/Makefile
> +++ b/drivers/gpu/drm/amd/acp/Makefile
> @@ -1,4 +1,25 @@
>  #
> +# Copyright 2017 Advanced Micro Devices, Inc.
> +#
> +# Permission is hereby granted, free of charge, to any person obtaining a
> +# copy of this software and associated documentation files (the "Software"),
> +# to deal in the Software without restriction, including without limitation
> +# the rights to use, copy, modify, merge, publish, distribute, sublicense,
> +# and/or sell copies of the Software, and to permit persons to whom the
> +# Software is furnished to do so, subject to the following conditions:
> +#
> +# The above copyright notice and this permission notice shall be included in
> +# all copies or substantial portions of the Software.
> +#
> +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> +# OTHER DEALINGS IN THE SOFTWARE.
> +#
> +#
>  # Makefile for the ACP, which is a sub-component
>  # of AMDSOC/AMDGPU drm driver.
>  # It provides the HW control for ACP related functionalities.
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
> b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 6a025c476b37..90202cf4cd1e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -1,4 +1,25 @@
>  #
> +# Copyright 2017 Advanced Micro Devices, Inc.
> +#
> +# Permission is hereby granted, free of charge, to any person obtaining a
> +# copy of this software and associated documentation files (the "Software"),
> +# to deal in the Software without restriction, including without limitation
> +# the rights to use, copy, modify, merge, publish, distribute, sublicense,
> +# and/or sell copies of the Software, and to permit persons to whom the
> +# Software is furnished to do so, subject to the following conditions:
> +#
> +# The above copyright notice and this permission notice shall be included in
> +# all copies or substantial portions of the Software.
> +#
> +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> +# FITNESS 

[PATCH v2] drm/amdgpu: Get rid of dep_sync as a seperate object.

[Andrey Grodzovsky]

Instead mark fence as explicit in it's amdgpu_sync_entry.

v2:
Fix use after free bug and add new parameter description.
Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c   | 14 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c  | 26 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 23 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h |  6 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 16 
 7 files changed, 48 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f8657c3..c56a986 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1121,7 +1121,6 @@ struct amdgpu_job {
struct amdgpu_vm*vm;
struct amdgpu_ring  *ring;
struct amdgpu_sync  sync;
-   struct amdgpu_sync  dep_sync;
struct amdgpu_sync  sched_sync;
struct amdgpu_ib*ibs;
struct dma_fence*fence; /* the hw fence */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index d15836b..b694d35 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -788,7 +788,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser 
*p)
return r;
 
r = amdgpu_sync_fence(adev, >job->sync,
- fpriv->prt_va->last_pt_update);
+ fpriv->prt_va->last_pt_update, false);
if (r)
return r;
 
@@ -802,7 +802,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser 
*p)
return r;
 
f = bo_va->last_pt_update;
-   r = amdgpu_sync_fence(adev, >job->sync, f);
+   r = amdgpu_sync_fence(adev, >job->sync, f, false);
if (r)
return r;
}
@@ -825,7 +825,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser 
*p)
return r;
 
f = bo_va->last_pt_update;
-   r = amdgpu_sync_fence(adev, >job->sync, f);
+   r = amdgpu_sync_fence(adev, >job->sync, f, false);
if (r)
return r;
}
@@ -836,7 +836,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser 
*p)
if (r)
return r;
 
-   r = amdgpu_sync_fence(adev, >job->sync, vm->last_update);
+   r = amdgpu_sync_fence(adev, >job->sync, vm->last_update, false);
if (r)
return r;
 
@@ -1040,8 +1040,8 @@ static int amdgpu_cs_process_fence_dep(struct 
amdgpu_cs_parser *p,
amdgpu_ctx_put(ctx);
return r;
} else if (fence) {
-   r = amdgpu_sync_fence(p->adev, >job->dep_sync,
- fence);
+   r = amdgpu_sync_fence(p->adev, >job->sync, fence,
+   true);
dma_fence_put(fence);
amdgpu_ctx_put(ctx);
if (r)
@@ -1060,7 +1060,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct 
amdgpu_cs_parser *p,
if (r)
return r;
 
-   r = amdgpu_sync_fence(p->adev, >job->dep_sync, fence);
+   r = amdgpu_sync_fence(p->adev, >job->sync, fence, true);
dma_fence_put(fence);
 
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 659997b..0cf86eb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -164,7 +164,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned 
num_ibs,
}
 
if (ring->funcs->emit_pipeline_sync && job &&
-   ((tmp = amdgpu_sync_get_fence(>sched_sync)) ||
+   ((tmp = amdgpu_sync_get_fence(>sched_sync, NULL)) ||
 amdgpu_vm_need_pipeline_sync(ring, job))) {
need_pipe_sync = true;
dma_fence_put(tmp);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 18770a8..61fb934 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -60,7 +60,6 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned 
num_ibs,
(*job)->num_ibs = num_ibs;
 
amdgpu_sync_create(&(*job)->sync);
-   amdgpu_sync_create(&(*job)->dep_sync);
amdgpu_sync_create(&(*job)->sched_sync);
(*job)->vram_lost_counter = atomic_read(>vram_lost_counter);
 
@@ -104,7 +103,6 @@ static void amdgpu_job_free_cb(struct amd_sched_job *s_job)

Re: [PATCH 1/1] drm/amdkfd: Do not ignore requested queue size during allocation

[Felix Kuehling]

On 2017-11-30 06:51 PM, Jan Vesely wrote:
>
> It's not a userspace queue that stops. I'm using kernel dbgdev to issue
> wave_resume commands. (waves are halted after executing
> s_sendmsg_halt).
> I bumped KFD_KERNEL_QUEUE_SIZE to 16KB to make sure all 320 resume
> commads fit (otherwise I get spurious ENOMEM when the queue is full but
> still advancing).

Sorry, didn't see this part of your message before.

To see the actual state of the DIQ in the hardware, you should look at
the HQD. You can find the matching HQD by looking at the queue base
address (cp_hqd_pq_base) which is at offset 0x220 in the MQD and offset
0xc934 in the register space (HQD).

I've debugged some obscure CP hangs involving the DIQ and wave control
commands before, that required help from the firmware team. The fix was
to remove synchronization with release_mem packets that could hang in
combination with wave control. It turned out the synchronization wasn't
really needed anyway. But it had some implications for how memory was
managed. I had to add code to allocate the IB on the queue (using a NOP
command), so I wouldn't have to free it explicitly (which would require
synchronization). I think that code is still not 100% correct. When the
queue is nearly full, an IB may get overwritten. I'd have to restructure
the code to allocate the IB after the commands that submit the IB, so
that the IB can't get overwritten until after the IB execution is finished.

Regards,
  Felix

>
> thanks,
> Jan
>
>> Regards,
>>   Felix
>>
>>
>> On 2017-11-29 04:43 PM, Jan Vesely wrote:
>>> On Mon, 2017-11-20 at 14:22 -0500, Felix Kuehling wrote:
 I think this patch is not correct. The EOP-mem is not associated with
 the queue size. The EOP buffer is a separate buffer used by the firmware
 to handle command completion. As I understand it, this allows more
 concurrency, while still making it look like all commands in the queue
 are completing in order.
>>> thanks for the explanation. I was looking for a source of a CP hang
>>> (rptr stops advancing), but bumping the eop size actually mode things
>>> worse. Is there a way to find out if a queue got disabled and for what
>>> reason? (I'm running ROCK-1.6.x based kernel)
>>>
>>> thanks,
>>> Jan
>>>
 Regards,
   Felix


 On 2017-11-19 03:19 AM, Oded Gabbay wrote:
> On Thu, Nov 16, 2017 at 11:36 PM, Jan Vesely  
> wrote:
>> Signed-off-by: Jan Vesely 
>> ---
>>  drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c 
>> b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
>> index f1d48281e322..b3bee39661ab 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
>> @@ -37,15 +37,16 @@ static bool initialize_vi(struct kernel_queue *kq, 
>> struct kfd_dev *dev,
>> enum kfd_queue_type type, unsigned int 
>> queue_size)
>>  {
>> int retval;
>> +   unsigned int size = ALIGN(queue_size, PAGE_SIZE);
>>
>> -   retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, >eop_mem);
>> +   retval = kfd_gtt_sa_allocate(dev, size, >eop_mem);
>> if (retval != 0)
>> return false;
>>
>> kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
>> kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
>>
>> -   memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
>> +   memset(kq->eop_kernel_addr, 0, size);
>>
>> return true;
>>  }
>> --
>> 2.13.6
>>
>> ___
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> Thanks!
> Applied to -next tree
> Oded
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

Re: [PATCH] drm/amdgpu: Get rid of dep_sync as a seperate object.

[Andrey Grodzovsky]

Please ignore this patch, there is a bug in this patch which I will fix 
and resend the patch soon.


Thanks,

Andrey


On 12/01/2017 01:59 PM, Andrey Grodzovsky wrote:

Instead mark fence as explicit in it's amdgpu_sync_entry.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  1 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c   | 14 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   |  2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c  | 26 --
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 27 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h |  6 +++---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 16 
  7 files changed, 52 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f8657c3..c56a986 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1121,7 +1121,6 @@ struct amdgpu_job {
struct amdgpu_vm*vm;
struct amdgpu_ring  *ring;
struct amdgpu_sync  sync;
-   struct amdgpu_sync  dep_sync;
struct amdgpu_sync  sched_sync;
struct amdgpu_ib*ibs;
struct dma_fence*fence; /* the hw fence */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index d15836b..b694d35 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -788,7 +788,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser 
*p)
return r;
  
  	r = amdgpu_sync_fence(adev, >job->sync,

- fpriv->prt_va->last_pt_update);
+ fpriv->prt_va->last_pt_update, false);
if (r)
return r;
  
@@ -802,7 +802,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)

return r;
  
  		f = bo_va->last_pt_update;

-   r = amdgpu_sync_fence(adev, >job->sync, f);
+   r = amdgpu_sync_fence(adev, >job->sync, f, false);
if (r)
return r;
}
@@ -825,7 +825,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser 
*p)
return r;
  
  			f = bo_va->last_pt_update;

-   r = amdgpu_sync_fence(adev, >job->sync, f);
+   r = amdgpu_sync_fence(adev, >job->sync, f, false);
if (r)
return r;
}
@@ -836,7 +836,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser 
*p)
if (r)
return r;
  
-	r = amdgpu_sync_fence(adev, >job->sync, vm->last_update);

+   r = amdgpu_sync_fence(adev, >job->sync, vm->last_update, false);
if (r)
return r;
  
@@ -1040,8 +1040,8 @@ static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,

amdgpu_ctx_put(ctx);
return r;
} else if (fence) {
-   r = amdgpu_sync_fence(p->adev, >job->dep_sync,
- fence);
+   r = amdgpu_sync_fence(p->adev, >job->sync, fence,
+   true);
dma_fence_put(fence);
amdgpu_ctx_put(ctx);
if (r)
@@ -1060,7 +1060,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct 
amdgpu_cs_parser *p,
if (r)
return r;
  
-	r = amdgpu_sync_fence(p->adev, >job->dep_sync, fence);

+   r = amdgpu_sync_fence(p->adev, >job->sync, fence, true);
dma_fence_put(fence);
  
  	return r;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 659997b..21086bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -164,7 +164,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned 
num_ibs,
}
  
  	if (ring->funcs->emit_pipeline_sync && job &&

-   ((tmp = amdgpu_sync_get_fence(>sched_sync)) ||
+   ((tmp = amdgpu_sync_get_fence(>sched_sync, false)) ||
 amdgpu_vm_need_pipeline_sync(ring, job))) {
need_pipe_sync = true;
dma_fence_put(tmp);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 18770a8..1d65590 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -60,7 +60,6 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned 
num_ibs,
(*job)->num_ibs = num_ibs;
  
  	amdgpu_sync_create(&(*job)->sync);

-   amdgpu_sync_create(&(*job)->dep_sync);
amdgpu_sync_create(&(*job)->sched_sync);
(*job)->vram_lost_counter = atomic_read(>vram_lost_counter);
  
@@ -104,7 +103,6 @@ 

Re: [PATCH libdrm 0/3] amdgpu: amdgpu_get_marketing_name cleanups

[Slava Abramov]

On 2017-12-01 11:56 AM, Michel Dänzer wrote:

From: Michel Dänzer 

The first two patches are preparatory for patch 3, which is the meat of
the series.

Michel Dänzer (3):
   amdgpu: Clean up amdgpu_parse_asic_ids error handling
   amdgpu: Simplify error handling in parse_one_line
   amdgpu: Only remember the device's marketing name

  amdgpu/Android.mk|   3 +-
  amdgpu/Makefile.am   |   5 +-
  amdgpu/amdgpu_asic_id.c  | 139 ++-
  amdgpu/amdgpu_device.c   |  27 +
  amdgpu/amdgpu_internal.h |  11 +---
  5 files changed, 49 insertions(+), 136 deletions(-)



Series
Acked-by: Slava Abramov 
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[PATCH] drm/amdgpu: Get rid of dep_sync as a seperate object.

[Andrey Grodzovsky]

Instead mark fence as explicit in it's amdgpu_sync_entry.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  |  1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c   | 14 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c   |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c  | 26 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 27 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h |  6 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 16 
 7 files changed, 52 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index f8657c3..c56a986 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1121,7 +1121,6 @@ struct amdgpu_job {
struct amdgpu_vm*vm;
struct amdgpu_ring  *ring;
struct amdgpu_sync  sync;
-   struct amdgpu_sync  dep_sync;
struct amdgpu_sync  sched_sync;
struct amdgpu_ib*ibs;
struct dma_fence*fence; /* the hw fence */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index d15836b..b694d35 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -788,7 +788,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser 
*p)
return r;
 
r = amdgpu_sync_fence(adev, >job->sync,
- fpriv->prt_va->last_pt_update);
+ fpriv->prt_va->last_pt_update, false);
if (r)
return r;
 
@@ -802,7 +802,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser 
*p)
return r;
 
f = bo_va->last_pt_update;
-   r = amdgpu_sync_fence(adev, >job->sync, f);
+   r = amdgpu_sync_fence(adev, >job->sync, f, false);
if (r)
return r;
}
@@ -825,7 +825,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser 
*p)
return r;
 
f = bo_va->last_pt_update;
-   r = amdgpu_sync_fence(adev, >job->sync, f);
+   r = amdgpu_sync_fence(adev, >job->sync, f, false);
if (r)
return r;
}
@@ -836,7 +836,7 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser 
*p)
if (r)
return r;
 
-   r = amdgpu_sync_fence(adev, >job->sync, vm->last_update);
+   r = amdgpu_sync_fence(adev, >job->sync, vm->last_update, false);
if (r)
return r;
 
@@ -1040,8 +1040,8 @@ static int amdgpu_cs_process_fence_dep(struct 
amdgpu_cs_parser *p,
amdgpu_ctx_put(ctx);
return r;
} else if (fence) {
-   r = amdgpu_sync_fence(p->adev, >job->dep_sync,
- fence);
+   r = amdgpu_sync_fence(p->adev, >job->sync, fence,
+   true);
dma_fence_put(fence);
amdgpu_ctx_put(ctx);
if (r)
@@ -1060,7 +1060,7 @@ static int amdgpu_syncobj_lookup_and_add_to_sync(struct 
amdgpu_cs_parser *p,
if (r)
return r;
 
-   r = amdgpu_sync_fence(p->adev, >job->dep_sync, fence);
+   r = amdgpu_sync_fence(p->adev, >job->sync, fence, true);
dma_fence_put(fence);
 
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 659997b..21086bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -164,7 +164,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned 
num_ibs,
}
 
if (ring->funcs->emit_pipeline_sync && job &&
-   ((tmp = amdgpu_sync_get_fence(>sched_sync)) ||
+   ((tmp = amdgpu_sync_get_fence(>sched_sync, false)) ||
 amdgpu_vm_need_pipeline_sync(ring, job))) {
need_pipe_sync = true;
dma_fence_put(tmp);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 18770a8..1d65590 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -60,7 +60,6 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned 
num_ibs,
(*job)->num_ibs = num_ibs;
 
amdgpu_sync_create(&(*job)->sync);
-   amdgpu_sync_create(&(*job)->dep_sync);
amdgpu_sync_create(&(*job)->sched_sync);
(*job)->vram_lost_counter = atomic_read(>vram_lost_counter);
 
@@ -104,7 +103,6 @@ static void amdgpu_job_free_cb(struct amd_sched_job *s_job)
amdgpu_ring_priority_put(job->ring, s_job->s_priority);

Re: [PATCH 1/1] drm/amdkfd: Do not ignore requested queue size during allocation

[Felix Kuehling]

To answer your questions about decoding MQDs, take a look at struct
vi_mqd in drivers/gpu/drm/amd/include/vi_structs.h. What you're looking
at is a binary dump of that structure, one per queue.

The information in the MQD may not always be up to date, because the MQD
represents an unmapped queue. It mostly gets updated when queues are
unmapped. So you would need to correlate the MQD of the queue you're
interested in with an HQD to see the current HW state.

Regards,
  Felix


On 2017-11-30 06:51 PM, Jan Vesely wrote:
> On Wed, 2017-11-29 at 16:58 -0500, Felix Kuehling wrote:
>> You can see the state of the queues in debugfs:
>> /sys/kernel/debug/kfd/... You can look at MQDs and HQDs.
> thanks. how do I decode the information?
> The rptr always stops at pos 60 which looks like this in mqds:
>
>  DIQ on device 45a2
> : c0310800 4000      
> 
> 0020:    0001    
> 
> 0040:        
> 
> 0060:        
> 
>
> If I understood correctly that's the queue dump, so those fs look
> wrong
>
>> If your application isn't stopping queues deliberately, queues get
>> disabled by evictions, usually temporarily. You'll see kernel messages
>> when that happens.
>>
>> A VM fault will result in queues of the offending process getting
>> disabled permanently. Again, you'll see messages about that in the
>> kernel log.
>>
>> The RPTR can also stop advancing if you have an infinite loop in a
>> shader program, or just a shader that takes a very long time to execute.
>> Or maybe if you have some dependencies (barriers) in your AQL packets
>> that never get satisfied.
>>
>> The function you changed only affects the HIQ, the queue that KFD uses
>> to control the HWS. It does not affect user mode queues. If your problem
>> is with a user mode queue, your change should have no effect at all.
> It's not a userspace queue that stops. I'm using kernel dbgdev to issue
> wave_resume commands. (waves are halted after executing
> s_sendmsg_halt).
> I bumped KFD_KERNEL_QUEUE_SIZE to 16KB to make sure all 320 resume
> commads fit (otherwise I get spurious ENOMEM when the queue is full but
> still advancing).
>
> thanks,
> Jan
>
>> Regards,
>>   Felix
>>
>>
>> On 2017-11-29 04:43 PM, Jan Vesely wrote:
>>> On Mon, 2017-11-20 at 14:22 -0500, Felix Kuehling wrote:
 I think this patch is not correct. The EOP-mem is not associated with
 the queue size. The EOP buffer is a separate buffer used by the firmware
 to handle command completion. As I understand it, this allows more
 concurrency, while still making it look like all commands in the queue
 are completing in order.
>>> thanks for the explanation. I was looking for a source of a CP hang
>>> (rptr stops advancing), but bumping the eop size actually mode things
>>> worse. Is there a way to find out if a queue got disabled and for what
>>> reason? (I'm running ROCK-1.6.x based kernel)
>>>
>>> thanks,
>>> Jan
>>>
 Regards,
   Felix


 On 2017-11-19 03:19 AM, Oded Gabbay wrote:
> On Thu, Nov 16, 2017 at 11:36 PM, Jan Vesely  
> wrote:
>> Signed-off-by: Jan Vesely 
>> ---
>>  drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c 
>> b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
>> index f1d48281e322..b3bee39661ab 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
>> @@ -37,15 +37,16 @@ static bool initialize_vi(struct kernel_queue *kq, 
>> struct kfd_dev *dev,
>> enum kfd_queue_type type, unsigned int 
>> queue_size)
>>  {
>> int retval;
>> +   unsigned int size = ALIGN(queue_size, PAGE_SIZE);
>>
>> -   retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, >eop_mem);
>> +   retval = kfd_gtt_sa_allocate(dev, size, >eop_mem);
>> if (retval != 0)
>> return false;
>>
>> kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
>> kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
>>
>> -   memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
>> +   memset(kq->eop_kernel_addr, 0, size);
>>
>> return true;
>>  }
>> --
>> 2.13.6
>>
>> ___
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>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> Thanks!
> Applied to -next tree
> Oded
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> 

Re: [PATCH 1/1] drm/amdkfd: Do not ignore requested queue size during allocation

[Felix Kuehling]

DIQ is the debug interface queue. Are you running a GPU debugger?
Otherwise I would not expect to even see a DIQ.

Are you not seeing any compute queues in mqds? If there are no compute
queues in mqds, that means your queue has been destroyed. That would
explain why the read pointer is not advancing.

Regards,
  Felix


On 2017-11-30 06:51 PM, Jan Vesely wrote:
> On Wed, 2017-11-29 at 16:58 -0500, Felix Kuehling wrote:
>> You can see the state of the queues in debugfs:
>> /sys/kernel/debug/kfd/... You can look at MQDs and HQDs.
> thanks. how do I decode the information?
> The rptr always stops at pos 60 which looks like this in mqds:
>
>  DIQ on device 45a2
> : c0310800 4000      
> 
> 0020:    0001    
> 
> 0040:        
> 
> 0060:        
> 
>
> If I understood correctly that's the queue dump, so those fs look
> wrong
>
>> If your application isn't stopping queues deliberately, queues get
>> disabled by evictions, usually temporarily. You'll see kernel messages
>> when that happens.
>>
>> A VM fault will result in queues of the offending process getting
>> disabled permanently. Again, you'll see messages about that in the
>> kernel log.
>>
>> The RPTR can also stop advancing if you have an infinite loop in a
>> shader program, or just a shader that takes a very long time to execute.
>> Or maybe if you have some dependencies (barriers) in your AQL packets
>> that never get satisfied.
>>
>> The function you changed only affects the HIQ, the queue that KFD uses
>> to control the HWS. It does not affect user mode queues. If your problem
>> is with a user mode queue, your change should have no effect at all.
> It's not a userspace queue that stops. I'm using kernel dbgdev to issue
> wave_resume commands. (waves are halted after executing
> s_sendmsg_halt).
> I bumped KFD_KERNEL_QUEUE_SIZE to 16KB to make sure all 320 resume
> commads fit (otherwise I get spurious ENOMEM when the queue is full but
> still advancing).
>
> thanks,
> Jan
>
>> Regards,
>>   Felix
>>
>>
>> On 2017-11-29 04:43 PM, Jan Vesely wrote:
>>> On Mon, 2017-11-20 at 14:22 -0500, Felix Kuehling wrote:
 I think this patch is not correct. The EOP-mem is not associated with
 the queue size. The EOP buffer is a separate buffer used by the firmware
 to handle command completion. As I understand it, this allows more
 concurrency, while still making it look like all commands in the queue
 are completing in order.
>>> thanks for the explanation. I was looking for a source of a CP hang
>>> (rptr stops advancing), but bumping the eop size actually mode things
>>> worse. Is there a way to find out if a queue got disabled and for what
>>> reason? (I'm running ROCK-1.6.x based kernel)
>>>
>>> thanks,
>>> Jan
>>>
 Regards,
   Felix


 On 2017-11-19 03:19 AM, Oded Gabbay wrote:
> On Thu, Nov 16, 2017 at 11:36 PM, Jan Vesely  
> wrote:
>> Signed-off-by: Jan Vesely 
>> ---
>>  drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c 
>> b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
>> index f1d48281e322..b3bee39661ab 100644
>> --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
>> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue_vi.c
>> @@ -37,15 +37,16 @@ static bool initialize_vi(struct kernel_queue *kq, 
>> struct kfd_dev *dev,
>> enum kfd_queue_type type, unsigned int 
>> queue_size)
>>  {
>> int retval;
>> +   unsigned int size = ALIGN(queue_size, PAGE_SIZE);
>>
>> -   retval = kfd_gtt_sa_allocate(dev, PAGE_SIZE, >eop_mem);
>> +   retval = kfd_gtt_sa_allocate(dev, size, >eop_mem);
>> if (retval != 0)
>> return false;
>>
>> kq->eop_gpu_addr = kq->eop_mem->gpu_addr;
>> kq->eop_kernel_addr = kq->eop_mem->cpu_ptr;
>>
>> -   memset(kq->eop_kernel_addr, 0, PAGE_SIZE);
>> +   memset(kq->eop_kernel_addr, 0, size);
>>
>> return true;
>>  }
>> --
>> 2.13.6
>>
>> ___
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> Thanks!
> Applied to -next tree
> Oded
> ___
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> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>>

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[PATCH libdrm 0/3] amdgpu: amdgpu_get_marketing_name cleanups

[Michel Dänzer]

From: Michel Dänzer 

The first two patches are preparatory for patch 3, which is the meat of
the series.

Michel Dänzer (3):
  amdgpu: Clean up amdgpu_parse_asic_ids error handling
  amdgpu: Simplify error handling in parse_one_line
  amdgpu: Only remember the device's marketing name

 amdgpu/Android.mk|   3 +-
 amdgpu/Makefile.am   |   5 +-
 amdgpu/amdgpu_asic_id.c  | 139 ++-
 amdgpu/amdgpu_device.c   |  27 +
 amdgpu/amdgpu_internal.h |  11 +---
 5 files changed, 49 insertions(+), 136 deletions(-)

-- 
2.15.0

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[PATCH libdrm 2/3] amdgpu: Simplify error handling in parse_one_line

[Michel Dänzer]

From: Michel Dänzer 

* Move empty/commented line check before the strdup and return -EAGAIN
  directly
* Initialize r = -EAGAIN and remove redundant assignments
* Set r = -ENOMEM if last strdup fails, and remove redundant goto

Signed-off-by: Michel Dänzer 
---
 amdgpu/amdgpu_asic_id.c | 45 -
 1 file changed, 16 insertions(+), 29 deletions(-)

diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c
index eb42bbc2..0b5f2962 100644
--- a/amdgpu/amdgpu_asic_id.c
+++ b/amdgpu/amdgpu_asic_id.c
@@ -45,63 +45,50 @@ static int parse_one_line(const char *line, struct 
amdgpu_asic_id *id)
char *s_rid;
char *s_name;
char *endptr;
-   int r = 0;
+   int r = -EINVAL;
+
+   /* ignore empty line and commented line */
+   if (strlen(line) == 0 || line[0] == '#')
+   return -EAGAIN;
 
buf = strdup(line);
if (!buf)
return -ENOMEM;
 
-   /* ignore empty line and commented line */
-   if (strlen(line) == 0 || line[0] == '#') {
-   r = -EAGAIN;
-   goto out;
-   }
-
/* device id */
s_did = strtok_r(buf, ",", );
-   if (!s_did) {
-   r = -EINVAL;
+   if (!s_did)
goto out;
-   }
 
id->did = strtol(s_did, , 16);
-   if (*endptr) {
-   r = -EINVAL;
+   if (*endptr)
goto out;
-   }
 
/* revision id */
s_rid = strtok_r(NULL, ",", );
-   if (!s_rid) {
-   r = -EINVAL;
+   if (!s_rid)
goto out;
-   }
 
id->rid = strtol(s_rid, , 16);
-   if (*endptr) {
-   r = -EINVAL;
+   if (*endptr)
goto out;
-   }
 
/* marketing name */
s_name = strtok_r(NULL, ",", );
-   if (!s_name) {
-   r = -EINVAL;
+   if (!s_name)
goto out;
-   }
+
/* trim leading whitespaces or tabs */
while (isblank(*s_name))
s_name++;
-   if (strlen(s_name) == 0) {
-   r = -EINVAL;
+   if (strlen(s_name) == 0)
goto out;
-   }
 
id->marketing_name = strdup(s_name);
-   if (id->marketing_name == NULL) {
-   r = -EINVAL;
-   goto out;
-   }
+   if (id->marketing_name)
+   r = 0;
+   else
+   r = -ENOMEM;
 
 out:
free(buf);
-- 
2.15.0

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[PATCH libdrm 3/3] amdgpu: Only remember the device's marketing name

[Michel Dänzer]

From: Michel Dänzer 

There's no point in keeping around the full table of marketing names,
when amdgpu_get_marketing_name only ever returns the device's marketing
name.

Signed-off-by: Michel Dänzer 
---
 amdgpu/Android.mk|  3 +-
 amdgpu/Makefile.am   |  5 +--
 amdgpu/amdgpu_asic_id.c  | 88 
 amdgpu/amdgpu_device.c   | 23 ++---
 amdgpu/amdgpu_internal.h | 11 ++
 5 files changed, 28 insertions(+), 102 deletions(-)

diff --git a/amdgpu/Android.mk b/amdgpu/Android.mk
index ce273019..1f028d0b 100644
--- a/amdgpu/Android.mk
+++ b/amdgpu/Android.mk
@@ -11,8 +11,7 @@ LOCAL_SHARED_LIBRARIES := libdrm
 LOCAL_SRC_FILES := $(LIBDRM_AMDGPU_FILES)
 
 LOCAL_CFLAGS := \
-   -DAMDGPU_ASIC_ID_TABLE=\"/vendor/etc/hwdata/amdgpu.ids\" \
-   -DAMDGPU_ASIC_ID_TABLE_NUM_ENTRIES=$(shell egrep -ci 
'^[0-9a-f]{4},.*[0-9a-f]+,' $(LIBDRM_TOP)/data/amdgpu.ids)
+   -DAMDGPU_ASIC_ID_TABLE=\"/vendor/etc/hwdata/amdgpu.ids\"
 
 LOCAL_REQUIRED_MODULES := amdgpu.ids
 
diff --git a/amdgpu/Makefile.am b/amdgpu/Makefile.am
index 66f6f676..a1b0d05c 100644
--- a/amdgpu/Makefile.am
+++ b/amdgpu/Makefile.am
@@ -31,10 +31,7 @@ AM_CFLAGS = \
-I$(top_srcdir)/include/drm
 
 libdrmdatadir = @libdrmdatadir@
-ASIC_ID_TABLE_NUM_ENTRIES := $(shell egrep -ci '^[0-9a-f]{4},.*[0-9a-f]+,' \
-   $(top_srcdir)/data/amdgpu.ids)
-AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${libdrmdatadir}/amdgpu.ids\" \
-   -DAMDGPU_ASIC_ID_TABLE_NUM_ENTRIES=$(ASIC_ID_TABLE_NUM_ENTRIES)
+AM_CPPFLAGS = -DAMDGPU_ASIC_ID_TABLE=\"${libdrmdatadir}/amdgpu.ids\"
 
 libdrm_amdgpu_la_LTLIBRARIES = libdrm_amdgpu.la
 libdrm_amdgpu_ladir = $(libdir)
diff --git a/amdgpu/amdgpu_asic_id.c b/amdgpu/amdgpu_asic_id.c
index 0b5f2962..0c8925e5 100644
--- a/amdgpu/amdgpu_asic_id.c
+++ b/amdgpu/amdgpu_asic_id.c
@@ -38,11 +38,13 @@
 #include "amdgpu_drm.h"
 #include "amdgpu_internal.h"
 
-static int parse_one_line(const char *line, struct amdgpu_asic_id *id)
+static int parse_one_line(struct amdgpu_device *dev, const char *line)
 {
char *buf, *saveptr;
char *s_did;
+   uint32_t did;
char *s_rid;
+   uint32_t rid;
char *s_name;
char *endptr;
int r = -EINVAL;
@@ -60,19 +62,29 @@ static int parse_one_line(const char *line, struct 
amdgpu_asic_id *id)
if (!s_did)
goto out;
 
-   id->did = strtol(s_did, , 16);
+   did = strtol(s_did, , 16);
if (*endptr)
goto out;
 
+   if (did != dev->info.asic_id) {
+   r = -EAGAIN;
+   goto out;
+   }
+
/* revision id */
s_rid = strtok_r(NULL, ",", );
if (!s_rid)
goto out;
 
-   id->rid = strtol(s_rid, , 16);
+   rid = strtol(s_rid, , 16);
if (*endptr)
goto out;
 
+   if (rid != dev->info.pci_rev_id) {
+   r = -EAGAIN;
+   goto out;
+   }
+
/* marketing name */
s_name = strtok_r(NULL, ",", );
if (!s_name)
@@ -84,8 +96,8 @@ static int parse_one_line(const char *line, struct 
amdgpu_asic_id *id)
if (strlen(s_name) == 0)
goto out;
 
-   id->marketing_name = strdup(s_name);
-   if (id->marketing_name)
+   dev->marketing_name = strdup(s_name);
+   if (dev->marketing_name)
r = 0;
else
r = -ENOMEM;
@@ -96,17 +108,13 @@ out:
return r;
 }
 
-void amdgpu_parse_asic_ids(struct amdgpu_asic_id **p_asic_id_table)
+void amdgpu_parse_asic_ids(struct amdgpu_device *dev)
 {
-   struct amdgpu_asic_id *asic_id_table;
-   struct amdgpu_asic_id *id;
FILE *fp;
char *line = NULL;
size_t len = 0;
ssize_t n;
int line_num = 1;
-   size_t table_size = 0;
-   size_t table_max_size = AMDGPU_ASIC_ID_TABLE_NUM_ENTRIES;
int r = 0;
 
fp = fopen(AMDGPU_ASIC_ID_TABLE, "r");
@@ -116,13 +124,6 @@ void amdgpu_parse_asic_ids(struct amdgpu_asic_id 
**p_asic_id_table)
return;
}
 
-   asic_id_table = calloc(table_max_size + 1,
-  sizeof(struct amdgpu_asic_id));
-   if (!asic_id_table) {
-   r = -ENOMEM;
-   goto close;
-   }
-
/* 1st valid line is file version */
while ((n = getline(, , fp)) != -1) {
/* trim trailing newline */
@@ -140,52 +141,17 @@ void amdgpu_parse_asic_ids(struct amdgpu_asic_id 
**p_asic_id_table)
}
 
while ((n = getline(, , fp)) != -1) {
-   if (table_size > table_max_size) {
-   /* double table size */
-   table_max_size *= 2;
-   id = realloc(asic_id_table, (table_max_size + 1) *
-sizeof(struct amdgpu_asic_id));
-   if (!id) {
-   r = 

Re: [PATCH 1/2] drm/amdgpu: add license to Makefiles

[Harry Wentland]

On 2017-12-01 03:31 AM, Christian König wrote:
> Am 01.12.2017 um 03:30 schrieb Alex Deucher:
>> Was missing license text.
>>
>> Signed-off-by: Alex Deucher 
> 
> We need copyright text on the Makefiles as well? Well, yeah makes sense. 
> Going to keep that in mind.
> 

Yes, this is something I never thought of as well, but I guess it makes sense.

> Acked-by: Christian König  for both patches.
> 

Acked-by: Harry Wentland  for the series.

Harry

> Regards,
> Christian.
> 
>> ---
>>   drivers/gpu/drm/amd/acp/Makefile   | 21 
>> 
>>   drivers/gpu/drm/amd/amdgpu/Makefile    | 21 
>> 
>>   drivers/gpu/drm/amd/amdkfd/Makefile    | 21 
>> 
>>   drivers/gpu/drm/amd/display/Makefile   | 21 
>> 
>>   drivers/gpu/drm/amd/display/amdgpu_dm/Makefile | 21 
>> 
>>   drivers/gpu/drm/amd/display/dc/Makefile    | 21 
>> 
>>   drivers/gpu/drm/amd/display/dc/basics/Makefile | 21 
>> 
>>   drivers/gpu/drm/amd/display/dc/bios/Makefile   | 21 
>> 
>>   drivers/gpu/drm/amd/display/dc/calcs/Makefile  | 21 
>> 
>>   drivers/gpu/drm/amd/display/dc/dce/Makefile    | 21 
>> 
>>   drivers/gpu/drm/amd/display/dc/dce100/Makefile | 21 
>> 
>>   drivers/gpu/drm/amd/display/dc/dce110/Makefile | 21 
>> 
>>   drivers/gpu/drm/amd/display/dc/dce112/Makefile | 21 
>> 
>>   drivers/gpu/drm/amd/display/dc/dce120/Makefile | 23 
>> +-
>>   drivers/gpu/drm/amd/display/dc/dce80/Makefile  | 21 
>> 
>>   drivers/gpu/drm/amd/display/dc/dcn10/Makefile  | 21 
>> 
>>   drivers/gpu/drm/amd/display/dc/dml/Makefile    | 21 
>> 
>>   drivers/gpu/drm/amd/display/dc/gpio/Makefile   | 21 
>> 
>>   drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 21 
>> 
>>   drivers/gpu/drm/amd/display/dc/irq/Makefile    | 21 
>> 
>>   drivers/gpu/drm/amd/display/dc/virtual/Makefile    | 21 
>> 
>>   .../gpu/drm/amd/display/modules/freesync/Makefile  | 21 
>> 
>>   drivers/gpu/drm/amd/lib/Makefile   | 21 
>> 
>>   drivers/gpu/drm/amd/powerplay/Makefile | 21 
>> 
>>   drivers/gpu/drm/amd/powerplay/hwmgr/Makefile   | 21 
>> 
>>   drivers/gpu/drm/amd/powerplay/smumgr/Makefile  | 21 
>> 
>>   26 files changed, 547 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/acp/Makefile 
>> b/drivers/gpu/drm/amd/acp/Makefile
>> index 8a08e81ee90d..d4176a3fb706 100644
>> --- a/drivers/gpu/drm/amd/acp/Makefile
>> +++ b/drivers/gpu/drm/amd/acp/Makefile
>> @@ -1,4 +1,25 @@
>>   #
>> +# Copyright 2017 Advanced Micro Devices, Inc.
>> +#
>> +# Permission is hereby granted, free of charge, to any person obtaining a
>> +# copy of this software and associated documentation files (the "Software"),
>> +# to deal in the Software without restriction, including without limitation
>> +# the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> +# and/or sell copies of the Software, and to permit persons to whom the
>> +# Software is furnished to do so, subject to the following conditions:
>> +#
>> +# The above copyright notice and this permission notice shall be included in
>> +# all copies or substantial portions of the Software.
>> +#
>> +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
>> +# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> +# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> +# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> +# OTHER DEALINGS IN THE SOFTWARE.
>> +#
>> +#
>>   # Makefile for the ACP, which is a sub-component
>>   # of AMDSOC/AMDGPU drm driver.
>>   # It provides the HW control for ACP related functionalities.
>> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
>> b/drivers/gpu/drm/amd/amdgpu/Makefile
>> index 6a025c476b37..90202cf4cd1e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
>> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
>> @@ -1,4 +1,25 @@
>>   #
>> +# Copyright 2017 Advanced Micro Devices, Inc.
>> +#
>> +# Permission is hereby granted, free of charge, to any person obtaining a
>> +# copy of this software and associated documentation files (the "Software"),
>> +# to deal in the Software without restriction, including without 

Re: [PATCH 0/2] Move scheduler out of AMDGPU

[Lucas Stach]

Am Freitag, den 01.12.2017, 16:55 +0100 schrieb Christian König:
> Am 01.12.2017 um 16:28 schrieb Lucas Stach:
> > Hi all,
> > 
> > so this is the first step to make the marvelous AMDGPU scheduler
> > useable
> > for other drivers. I have a (mostly) working prototype of Etnaviv
> > using
> > the scheduler, but those patches need to keep baking for a while.
> > 
> > I'm sending this out as I want to avoid rebasing this change too
> > much
> > and don't want to take people by surprise when the Etnaviv
> > implementation
> > surfaces. Also this might need some coordination between AMDGPU and
> > Etnaviv, which might be good to get going now.
> > 
> > Please speak up now if you have any objections or comments.
> 
> Looks good to me, but question is what is this based upon?
> 
> I strongly assume drm-next, so question is now if we have any
> patches 
> inside amd branches we should apply before doing this.

For now this is based on 4.15-rc1, where the only difference to drm-
next in the scheduler code is currently this:

>8--

diff --git a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h 
b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h
index 8bd38102b58e..283a0dc25e84 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h
+++ b/drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 #if !defined(_GPU_SCHED_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
 #define _GPU_SCHED_TRACE_H_
 
diff --git a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c 
b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
index e4d3b4ec4e92..92ec663fdada 100644
--- a/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
+++ b/drivers/gpu/drm/amd/scheduler/gpu_scheduler.c
@@ -188,7 +188,7 @@ static bool amd_sched_entity_is_ready(struct 
amd_sched_entity *entity)
if (kfifo_is_empty(>job_queue))
return false;
 
-   if (ACCESS_ONCE(entity->dependency))
+   if (READ_ONCE(entity->dependency))
return false;
 
return true;

--->8--

I'm fine with rebasing this on whatever AMDGPU guys prefer, but this
requires a stable branch with all relevant patches included, so we can
use this as a synchronization point for the move.

> CCing Andrey as well cause he has some tasks assigned around the 
> scheduler as well.

Thanks,
Lucas
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Re: [PATCH 0/2] Move scheduler out of AMDGPU

[Christian König]

Am 01.12.2017 um 16:28 schrieb Lucas Stach:

Hi all,

so this is the first step to make the marvelous AMDGPU scheduler useable
for other drivers. I have a (mostly) working prototype of Etnaviv using
the scheduler, but those patches need to keep baking for a while.

I'm sending this out as I want to avoid rebasing this change too much
and don't want to take people by surprise when the Etnaviv implementation
surfaces. Also this might need some coordination between AMDGPU and
Etnaviv, which might be good to get going now.

Please speak up now if you have any objections or comments.


Looks good to me, but question is what is this based upon?

I strongly assume drm-next, so question is now if we have any patches 
inside amd branches we should apply before doing this.


CCing Andrey as well cause he has some tasks assigned around the 
scheduler as well.


Regards,
Christian.



Regards,
Lucas

Lucas Stach (2):
   drm: move amd_gpu_scheduler into common location
   drm/sched: move fence slab handling to module init/exit

  drivers/gpu/drm/Kconfig|   5 +
  drivers/gpu/drm/Makefile   |   1 +
  drivers/gpu/drm/amd/amdgpu/Makefile|   5 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  16 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |   8 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c|  38 +--
  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  12 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|   8 -
  drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  |   4 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c|  22 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  14 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h   |  12 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c  |  20 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h  |   2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c   |   6 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|   8 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h|   4 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c|   8 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h|   4 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c|   8 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h|   2 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c|  14 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h|   4 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c |  10 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |   4 +-
  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |   4 +-
  drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c  |   8 +-
  drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  |   8 +-
  drivers/gpu/drm/amd/scheduler/gpu_scheduler.h  | 185 --
  drivers/gpu/drm/scheduler/Makefile |   4 +
  .../gpu/drm/{amd => }/scheduler/gpu_scheduler.c| 281 +++--
  drivers/gpu/drm/{amd => }/scheduler/sched_fence.c  | 122 +
  include/drm/gpu_scheduler.h| 171 +
  .../drm/gpu_scheduler_trace.h  |  14 +-
  34 files changed, 525 insertions(+), 511 deletions(-)
  delete mode 100644 drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
  create mode 100644 drivers/gpu/drm/scheduler/Makefile
  rename drivers/gpu/drm/{amd => }/scheduler/gpu_scheduler.c (64%)
  rename drivers/gpu/drm/{amd => }/scheduler/sched_fence.c (58%)
  create mode 100644 include/drm/gpu_scheduler.h
  rename drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h => 
include/drm/gpu_scheduler_trace.h (83%)



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[PATCH 1/2] drm: move amd_gpu_scheduler into common location

[Lucas Stach]

This moves and renames the AMDGPU scheduler to a common location in DRM
in order to facilitate re-use by other drivers. This is mostly a straight
forward rename with no code changes.

One notable exception is the function to_drm_sched_fence(), which is no
longer a inline header function to avoid the need to export the
drm_sched_fence_ops_scheduled and drm_sched_fence_ops_finished structures.

Signed-off-by: Lucas Stach 
---
 drivers/gpu/drm/Kconfig|   5 +
 drivers/gpu/drm/Makefile   |   1 +
 drivers/gpu/drm/amd/amdgpu/Makefile|   5 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  16 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c|  38 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  12 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  |   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c|  22 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  14 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h   |  12 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c  |  20 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h  |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c   |   6 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h|   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c|   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h|   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c|   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h|   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c|  14 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h|   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c |  10 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |   4 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |   4 +-
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c  |   8 +-
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  |   8 +-
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.h  | 185 --
 drivers/gpu/drm/scheduler/Makefile |   4 +
 .../gpu/drm/{amd => }/scheduler/gpu_scheduler.c| 281 +++--
 drivers/gpu/drm/{amd => }/scheduler/sched_fence.c  | 118 +
 include/drm/gpu_scheduler.h| 174 +
 .../drm/gpu_scheduler_trace.h  |  14 +-
 34 files changed, 526 insertions(+), 505 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
 create mode 100644 drivers/gpu/drm/scheduler/Makefile
 rename drivers/gpu/drm/{amd => }/scheduler/gpu_scheduler.c (64%)
 rename drivers/gpu/drm/{amd => }/scheduler/sched_fence.c (59%)
 create mode 100644 include/drm/gpu_scheduler.h
 rename drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h => 
include/drm/gpu_scheduler_trace.h (83%)

diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 4d9f21831741..ee38a3db1890 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -149,6 +149,10 @@ config DRM_VM
bool
depends on DRM && MMU
 
+config DRM_SCHED
+   tristate
+   depends on DRM
+
 source "drivers/gpu/drm/i2c/Kconfig"
 
 source "drivers/gpu/drm/arm/Kconfig"
@@ -178,6 +182,7 @@ config DRM_AMDGPU
depends on DRM && PCI && MMU
select FW_LOADER
 select DRM_KMS_HELPER
+   select DRM_SCHED
 select DRM_TTM
select POWER_SUPPLY
select HWMON
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index e9500844333e..1f6ba9e34e31 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -101,3 +101,4 @@ obj-$(CONFIG_DRM_MXSFB) += mxsfb/
 obj-$(CONFIG_DRM_TINYDRM) += tinydrm/
 obj-$(CONFIG_DRM_PL111) += pl111/
 obj-$(CONFIG_DRM_TVE200) += tve200/
+obj-$(CONFIG_DRM_SCHED)+= scheduler/
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 78d609123420..5f690f023e75 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -115,10 +115,7 @@ amdgpu-y += \
 amdgpu-y += amdgpu_cgs.o
 
 # GPU scheduler
-amdgpu-y += \
-   ../scheduler/gpu_scheduler.o \
-   ../scheduler/sched_fence.o \
-   amdgpu_job.o
+amdgpu-y += amdgpu_job.o
 
 # ACP componet
 ifneq ($(CONFIG_DRM_AMD_ACP),)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 5afaf6016b4a..f17882b87cf5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -45,6 +45,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -68,7 +69,6 @@
 #include "amdgpu_mn.h"
 #include "amdgpu_dm.h"
 
-#include "gpu_scheduler.h"
 #include "amdgpu_virt.h"
 #include "amdgpu_gart.h"
 
@@ -684,7 +684,7 @@ struct amdgpu_ib {
uint32_t 

[PATCH 0/2] Move scheduler out of AMDGPU

[Lucas Stach]

Hi all,

so this is the first step to make the marvelous AMDGPU scheduler useable
for other drivers. I have a (mostly) working prototype of Etnaviv using
the scheduler, but those patches need to keep baking for a while.

I'm sending this out as I want to avoid rebasing this change too much
and don't want to take people by surprise when the Etnaviv implementation
surfaces. Also this might need some coordination between AMDGPU and
Etnaviv, which might be good to get going now.

Please speak up now if you have any objections or comments.

Regards,
Lucas

Lucas Stach (2):
  drm: move amd_gpu_scheduler into common location
  drm/sched: move fence slab handling to module init/exit

 drivers/gpu/drm/Kconfig|   5 +
 drivers/gpu/drm/Makefile   |   1 +
 drivers/gpu/drm/amd/amdgpu/Makefile|   5 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  16 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c|  38 +--
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c |  12 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c|   8 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c  |   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c|  22 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c   |  14 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h   |  12 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c  |  20 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_sched.h  |   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c   |   6 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c|   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h|   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c|   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h|   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c|   8 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h|   2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c|  14 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h|   4 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c |  10 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h |   4 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  |   4 +-
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c  |   8 +-
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c  |   8 +-
 drivers/gpu/drm/amd/scheduler/gpu_scheduler.h  | 185 --
 drivers/gpu/drm/scheduler/Makefile |   4 +
 .../gpu/drm/{amd => }/scheduler/gpu_scheduler.c| 281 +++--
 drivers/gpu/drm/{amd => }/scheduler/sched_fence.c  | 122 +
 include/drm/gpu_scheduler.h| 171 +
 .../drm/gpu_scheduler_trace.h  |  14 +-
 34 files changed, 525 insertions(+), 511 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/scheduler/gpu_scheduler.h
 create mode 100644 drivers/gpu/drm/scheduler/Makefile
 rename drivers/gpu/drm/{amd => }/scheduler/gpu_scheduler.c (64%)
 rename drivers/gpu/drm/{amd => }/scheduler/sched_fence.c (58%)
 create mode 100644 include/drm/gpu_scheduler.h
 rename drivers/gpu/drm/amd/scheduler/gpu_sched_trace.h => 
include/drm/gpu_scheduler_trace.h (83%)

-- 
2.11.0

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[PATCH 2/2] drm/sched: move fence slab handling to module init/exit

[Lucas Stach]

This is the only part of the scheduler which must not be called from
different drivers. Move it to module init/exit so it is done a single
time when loading the scheduler.

Signed-off-by: Lucas Stach 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |  8 
 drivers/gpu/drm/scheduler/sched_fence.c | 12 
 include/drm/gpu_scheduler.h |  3 ---
 3 files changed, 8 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index b23c83c59725..18b7fce2fb27 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -906,10 +906,6 @@ static int __init amdgpu_init(void)
if (r)
goto error_fence;
 
-   r = drm_sched_fence_slab_init();
-   if (r)
-   goto error_sched;
-
if (vgacon_text_force()) {
DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
return -EINVAL;
@@ -922,9 +918,6 @@ static int __init amdgpu_init(void)
/* let modprobe override vga console setting */
return pci_register_driver(pdriver);
 
-error_sched:
-   amdgpu_fence_slab_fini();
-
 error_fence:
amdgpu_sync_fini();
 
@@ -938,7 +931,6 @@ static void __exit amdgpu_exit(void)
pci_unregister_driver(pdriver);
amdgpu_unregister_atpx_handler();
amdgpu_sync_fini();
-   drm_sched_fence_slab_fini();
amdgpu_fence_slab_fini();
 }
 
diff --git a/drivers/gpu/drm/scheduler/sched_fence.c 
b/drivers/gpu/drm/scheduler/sched_fence.c
index f6f2955890c4..69aab086b913 100644
--- a/drivers/gpu/drm/scheduler/sched_fence.c
+++ b/drivers/gpu/drm/scheduler/sched_fence.c
@@ -29,7 +29,7 @@
 
 static struct kmem_cache *sched_fence_slab;
 
-int drm_sched_fence_slab_init(void)
+static int __init drm_sched_fence_slab_init(void)
 {
sched_fence_slab = kmem_cache_create(
"drm_sched_fence", sizeof(struct drm_sched_fence), 0,
@@ -39,14 +39,12 @@ int drm_sched_fence_slab_init(void)
 
return 0;
 }
-EXPORT_SYMBOL_GPL(drm_sched_fence_slab_init);
 
-void drm_sched_fence_slab_fini(void)
+static void __exit drm_sched_fence_slab_fini(void)
 {
rcu_barrier();
kmem_cache_destroy(sched_fence_slab);
 }
-EXPORT_SYMBOL_GPL(drm_sched_fence_slab_fini);
 
 void drm_sched_fence_scheduled(struct drm_sched_fence *fence)
 {
@@ -185,3 +183,9 @@ struct drm_sched_fence *drm_sched_fence_create(struct 
drm_sched_entity *entity,
 
return fence;
 }
+
+module_init(drm_sched_fence_slab_init);
+module_exit(drm_sched_fence_slab_fini);
+
+MODULE_DESCRIPTION("DRM GPU scheduler");
+MODULE_LICENSE("GPL and additional rights");
diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h
index 870ce9a693d3..2e165093a789 100644
--- a/include/drm/gpu_scheduler.h
+++ b/include/drm/gpu_scheduler.h
@@ -149,9 +149,6 @@ void drm_sched_entity_push_job(struct drm_sched_job 
*sched_job);
 void drm_sched_entity_set_rq(struct drm_sched_entity *entity,
 struct drm_sched_rq *rq);
 
-int drm_sched_fence_slab_init(void);
-void drm_sched_fence_slab_fini(void);
-
 struct drm_sched_fence *drm_sched_fence_create(
struct drm_sched_entity *s_entity, void *owner);
 void drm_sched_fence_scheduled(struct drm_sched_fence *fence);
-- 
2.11.0

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Re: [PATCH 02/13] fbdev: add remove_conflicting_pci_framebuffers()

[Sudip Mukherjee]

On Fri, Dec 01, 2017 at 08:19:16AM +0100, Daniel Vetter wrote:
> On Thu, Nov 30, 2017 at 11:49:53PM +, Sudip Mukherjee wrote:
> > Hi Daniel,
> > 
> > 
> > 
> > > > > > 
> > > > > > Greg?
> > > > > 
> > > > > Yes, if no one is working to get it out of staging, that means no one
> > > > > cares about it, and it needs to be removed from the tree.
> > > > 
> > > > Agreed. I was not working on getting it out of staging as there is no
> > > > place for it to go.
> > > > But, Teddy Wang told me that they have a working drm driver for it, but
> > > > it is not atomic like Daniel was asking for. If it is ok, then I can 
> > > > send
> > > > in a patch to remove the existing sm750 from staging and add the new 
> > > > sm750
> > > > drm driver to staging. And after it is ready, we can go ahead with 
> > > > moving
> > > > it out of staging to drm.
> > > 
> > > Please keep the todo item that it needs to be converted to atomic. And
> > > tbh, it's probably faster if you just submit it to dri-devel, assuming you
> > > have time to work on it. For small drivers we tend to be fairly quick in
> > > getting them into good enough shape.
> > 
> > I have received the driver from Teddy and pushed it to
> > https://github.com/sudipm-mukherjee/parport/tree/drm_smi for your first
> > look into it. It is not even building with next-20171130 and has lots of
> > build warnings. I will have to do a lot of work on it before I can even
> > submit it to dri-devel.
> > 
> > Time will be the problem, as this is not part of my day job.
> > 
> > > 
> > > Staging is also a major pain for drm subsystem refactorings, I really,
> > > really, really prefer we don't add more than the vbox pain we have
> > > already.
> > 
> > I am hoping that after seeing it, you will agree to have it in staging. :)
> 
> So I know Greg is willing to take anything into staging, but I'm no fan.
> We refactor and improve drm a lot, with a lot of cross-driver changes
> necessary to move things forward. We can do that since we have a generally
> rather active development community, and we try hard to keep most drivers
> in reasonable good shape and so easy to maintain.
> 
> If you know throw a pile of unmaintainable stuff into staging, but without
> working on it, then that's just cost, no benefit to the dri-devel
> community. On top, staging tree is separate from drm trees, so more pain
> to synchronize trees (and we have to do that a few times per release cycle
> or drivers simply stop compiling). Where's the upside of taking this
> driver into staging?
> 
> One is users, but ime for soc display drivers usually everything else is
> in worse shape (e.g. even great drivers like the one for qualcom must be
> tested on some vendor tree because critical core bits are missing in
> upstream), so "more users" is not the good reason. And it's clearly not
> "more developers", because no time to clean things up. So what exactly is
> the good reason to put this into staging instead of just waiting until
> someone has the time to clean it up quickly?

Ok, I will not try to give any more reasons now. :)

I will cleanup the basic things I can and then submit it to dri-devel.

Greg - Please keep the SM750 driver in staging for now. I will send
a patch later to add in TODO the git location where the drm driver is
being developed. And when that drm driver is ready, I will send a patch
to remove the sm750fb driver from staging.

--
Regards
Sudip
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Re: [PATCH xf86-video-ati] Add radeon_dirty_src_drawable helper

[Deucher, Alexander]

From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: Friday, December 1, 2017 9:56 AM
To: amd-gfx@lists.freedesktop.org
Subject: [PATCH xf86-video-ati] Add radeon_dirty_src_drawable helper

From: Michel Dänzer 

Allows tidying up radeon_dirty_src_equals and redisplay_dirty slightly.

(Cherry picked from amdgpu commit 1d65ac395971571094df21ca0408d5972c6b56ec)

Signed-off-by: Michel Dänzer 

Acked-by: Alex Deucher 

---
 src/radeon.h | 18 +-
 src/radeon_kms.c |  7 ++-
 2 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/src/radeon.h b/src/radeon.h
index 3e04101c2..cc5dc09f1 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -191,24 +191,24 @@ radeon_master_screen(ScreenPtr screen)

 static inline ScreenPtr
 radeon_dirty_master(PixmapDirtyUpdatePtr dirty)
+{
+return radeon_master_screen(dirty->slave_dst->drawable.pScreen);
+}
+
+static inline DrawablePtr
+radeon_dirty_src_drawable(PixmapDirtyUpdatePtr dirty)
 {
 #ifdef HAS_DIRTYTRACKING_DRAWABLE_SRC
-ScreenPtr screen = dirty->src->pScreen;
+return dirty->src;
 #else
-ScreenPtr screen = dirty->src->drawable.pScreen;
+return >src->drawable;
 #endif
-
-return radeon_master_screen(screen);
 }

 static inline Bool
 radeon_dirty_src_equals(PixmapDirtyUpdatePtr dirty, PixmapPtr pixmap)
 {
-#ifdef HAS_DIRTYTRACKING_DRAWABLE_SRC
-return dirty->src == >drawable;
-#else
-return dirty->src == pixmap;
-#endif
+return radeon_dirty_src_drawable(dirty) == >drawable;
 }


diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 5fcd8f0b7..a9300d400 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -570,11 +570,8 @@ dirty_region(PixmapDirtyUpdatePtr dirty)
 static void
 redisplay_dirty(PixmapDirtyUpdatePtr dirty, RegionPtr region)
 {
-#ifdef HAS_DIRTYTRACKING_DRAWABLE_SRC
-   ScrnInfoPtr src_scrn = xf86ScreenToScrn(dirty->src->pScreen);
-#else
-   ScrnInfoPtr src_scrn = xf86ScreenToScrn(dirty->src->drawable.pScreen);
-#endif
+   ScrnInfoPtr src_scrn =
+   xf86ScreenToScrn(radeon_dirty_src_drawable(dirty)->pScreen);

 if (RegionNil(region))
 goto out;
--
2.15.0

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[PATCH xf86-video-ati] Add radeon_dirty_src_drawable helper

[Michel Dänzer]

From: Michel Dänzer 

Allows tidying up radeon_dirty_src_equals and redisplay_dirty slightly.

(Cherry picked from amdgpu commit 1d65ac395971571094df21ca0408d5972c6b56ec)

Signed-off-by: Michel Dänzer 
---
 src/radeon.h | 18 +-
 src/radeon_kms.c |  7 ++-
 2 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/src/radeon.h b/src/radeon.h
index 3e04101c2..cc5dc09f1 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -191,24 +191,24 @@ radeon_master_screen(ScreenPtr screen)
 
 static inline ScreenPtr
 radeon_dirty_master(PixmapDirtyUpdatePtr dirty)
+{
+return radeon_master_screen(dirty->slave_dst->drawable.pScreen);
+}
+
+static inline DrawablePtr
+radeon_dirty_src_drawable(PixmapDirtyUpdatePtr dirty)
 {
 #ifdef HAS_DIRTYTRACKING_DRAWABLE_SRC
-ScreenPtr screen = dirty->src->pScreen;
+return dirty->src;
 #else
-ScreenPtr screen = dirty->src->drawable.pScreen;
+return >src->drawable;
 #endif
-
-return radeon_master_screen(screen);
 }
 
 static inline Bool
 radeon_dirty_src_equals(PixmapDirtyUpdatePtr dirty, PixmapPtr pixmap)
 {
-#ifdef HAS_DIRTYTRACKING_DRAWABLE_SRC
-return dirty->src == >drawable;
-#else
-return dirty->src == pixmap;
-#endif
+return radeon_dirty_src_drawable(dirty) == >drawable;
 }
 
 
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 5fcd8f0b7..a9300d400 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -570,11 +570,8 @@ dirty_region(PixmapDirtyUpdatePtr dirty)
 static void
 redisplay_dirty(PixmapDirtyUpdatePtr dirty, RegionPtr region)
 {
-#ifdef HAS_DIRTYTRACKING_DRAWABLE_SRC
-   ScrnInfoPtr src_scrn = xf86ScreenToScrn(dirty->src->pScreen);
-#else
-   ScrnInfoPtr src_scrn = xf86ScreenToScrn(dirty->src->drawable.pScreen);
-#endif
+   ScrnInfoPtr src_scrn =
+   xf86ScreenToScrn(radeon_dirty_src_drawable(dirty)->pScreen);
 
if (RegionNil(region))
goto out;
-- 
2.15.0

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Re: [PATCH 02/13] fbdev: add remove_conflicting_pci_framebuffers()

[Emil Velikov]

On 30 November 2017 at 23:49, Sudip Mukherjee
 wrote:
> Hi Daniel,
>
> On Wed, Nov 29, 2017 at 10:56:34AM +0100, Daniel Vetter wrote:
>> On Tue, Nov 28, 2017 at 12:30:30PM +, Sudip Mukherjee wrote:
>> > On Tue, Nov 28, 2017 at 12:32:38PM +0100, Greg KH wrote:
>> > > On Tue, Nov 28, 2017 at 11:22:17AM +0100, Daniel Vetter wrote:
>> > > > On Mon, Nov 27, 2017 at 08:52:19PM +, Sudip Mukherjee wrote:
>> > > > > On Mon, Nov 27, 2017 at 11:27:59AM +0100, Daniel Vetter wrote:
>> > > > > > On Fri, Nov 24, 2017 at 06:53:31PM +0100, Michał Mirosław wrote:
>> > > > > > > Almost all drivers using remove_conflicting_framebuffers() wrap 
>> > > > > > > it with
>> > > > > > > the same code. Extract common part from PCI drivers into separate
>> > > > > > > remove_conflicting_pci_framebuffers().
>> > > > > > >
>
> 
>
>> > > >
>> > > > Greg?
>> > >
>> > > Yes, if no one is working to get it out of staging, that means no one
>> > > cares about it, and it needs to be removed from the tree.
>> >
>> > Agreed. I was not working on getting it out of staging as there is no
>> > place for it to go.
>> > But, Teddy Wang told me that they have a working drm driver for it, but
>> > it is not atomic like Daniel was asking for. If it is ok, then I can send
>> > in a patch to remove the existing sm750 from staging and add the new sm750
>> > drm driver to staging. And after it is ready, we can go ahead with moving
>> > it out of staging to drm.
>>
>> Please keep the todo item that it needs to be converted to atomic. And
>> tbh, it's probably faster if you just submit it to dri-devel, assuming you
>> have time to work on it. For small drivers we tend to be fairly quick in
>> getting them into good enough shape.
>
> I have received the driver from Teddy and pushed it to
> https://github.com/sudipm-mukherjee/parport/tree/drm_smi for your first
> look into it. It is not even building with next-20171130 and has lots of
> build warnings. I will have to do a lot of work on it before I can even
> submit it to dri-devel.
>
A crazy idea, mostly towards Tedd and Sudip:

Start small and build gradually. An example split for separate patch series:

 - one HW, basic setup + atomic KMS
 - add second HW
 - more KMS features
 - fancy memory management
 - 2D/3D/other acceleration

The driver as seen above tries to do all of the above (almost, it's not atomic)
at once - 40k loc.

Someone familiar with the code can quickly split it up and while doing
so, feed it through checkpatch.
Current code is _very_ far from kernel coding style, plus the
copyright blurp is very disturbing:

* All rights are reserved. Reproduction or in part is prohibited
* without the written consent of the copyright owner.

HTH
Emil
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[PATCH 06/20] drm/amd/display: add assert to verify dcn_calc input validity

[Harry Wentland]

From: Dmytro Laktyushkin 

This reverts commit 978482d0de86 Revert noisy assert messages

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index 453ec1c6c181..47dbc953a3a9 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -887,6 +887,17 @@ bool dcn_validate_bandwidth(
+ 
pipe->bottom_pipe->plane_res.scl_data.recout.width;
}
 
+   if (pipe->plane_state->rotation % 2 == 0) {
+   
ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dal_fixed31_32_one.value
+   || v->scaler_rec_out_width[input_idx] 
== v->viewport_width[input_idx]);
+   
ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dal_fixed31_32_one.value
+   || v->scaler_recout_height[input_idx] 
== v->viewport_height[input_idx]);
+   } else {
+   
ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dal_fixed31_32_one.value
+   || v->scaler_recout_height[input_idx] 
== v->viewport_width[input_idx]);
+   
ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dal_fixed31_32_one.value
+   || v->scaler_rec_out_width[input_idx] 
== v->viewport_height[input_idx]);
+   }
v->dcc_enable[input_idx] = 
pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no;
v->source_pixel_format[input_idx] = 
tl_pixel_format_to_bw_defs(
pipe->plane_state->format);
-- 
2.14.1

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[PATCH 07/20] drm/amd/display: dpp clean up

[Harry Wentland]

From: Yue Hin Lau 

Signed-off-by: Yue Hin Lau 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 4 +++-
 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h   | 7 +--
 2 files changed, 4 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index 4c90043e7b8c..4f5125398bbc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -49,6 +49,8 @@
 #define FN(reg_name, field_name) \
dpp->tf_shift->field_name, dpp->tf_mask->field_name
 
+#define NUM_ELEMENTS(a) (sizeof(a) / sizeof((a)[0]))
+
 struct dcn10_input_csc_matrix {
enum dc_color_space color_space;
uint16_t regval[12];
@@ -270,7 +272,7 @@ void dpp1_cm_set_output_csc_default(
struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
struct out_csc_color_matrix tbl_entry;
int i, j;
-   int arr_size = sizeof(output_csc_matrix) / sizeof(struct 
output_csc_matrix);
+   int arr_size = NUM_ELEMENTS(output_csc_matrix);
uint32_t ocsc_mode = 4;
 
tbl_entry.color_space = colorspace;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index d7d027c7ae51..0f70f36a3ebe 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -131,12 +131,7 @@ struct out_csc_color_matrix {
uint16_t regval[12];
 };
 
-struct output_csc_matrix {
-   enum dc_color_space color_space;
-   uint16_t regval[12];
-};
-
-static const struct output_csc_matrix output_csc_matrix[] = {
+static const struct out_csc_color_matrix output_csc_matrix[] = {
{ COLOR_SPACE_SRGB,
{ 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
{ COLOR_SPACE_SRGB_LIMITED,
-- 
2.14.1

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[PATCH 02/20] drm/amd/display: Print DC_VER at DC init

[Harry Wentland]

This has proven helpful on other OSes to give a quick state of the
DC driver when a bug is reported.

Signed-off-by: Harry Wentland 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index fd7f6c5df73d..d2d9cf5e0cfc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -431,9 +431,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
adev->dm.dc = dc_create(_data);
 
if (adev->dm.dc) {
-   DRM_INFO("Display Core initialized!\n");
+   DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
} else {
-   DRM_INFO("Display Core failed to initialize!\n");
+   DRM_INFO("Display Core failed to initialize with v%s!\n", 
DC_VER);
goto error;
}
 
-- 
2.14.1

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[PATCH 05/20] drm/amd/display: Add dppclk to dcn_bw_clocks

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h| 3 ++-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 1 -
 drivers/gpu/drm/amd/display/dc/inc/core_types.h   | 1 +
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 3b0db253ac22..b73db9e78437 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -582,7 +582,8 @@ struct dce_hwseq_registers {
type DOMAIN7_PGFSM_PWR_STATUS; \
type DCFCLK_GATE_DIS; \
type DCHUBBUB_GLOBAL_TIMER_REFDIV; \
-   type DENTIST_DPPCLK_WDIVIDER;
+   type DENTIST_DPPCLK_WDIVIDER; \
+   type DENTIST_DISPCLK_WDIVIDER;
 
 struct dce_hwseq_shift {
HWSEQ_REG_FIELD_LIST(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index a4d756c1b97a..39a4d1a86583 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1335,7 +1335,6 @@ static void dcn10_enable_plane(
/* make sure OPP_PIPE_CLOCK_EN = 1 */
REG_UPDATE(OPP_PIPE_CONTROL[pipe_ctx->stream_res.tg->inst],
OPP_PIPE_CLOCK_EN, 1);
-   /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 
0x1f);*/
 
 /* TODO: enable/disable in dm as per update type.
if (plane_state) {
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h 
b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index d680b565af6f..9cc6bbb20714 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -241,6 +241,7 @@ struct dce_bw_output {
 
 struct dcn_bw_clocks {
int dispclk_khz;
+   int dppclk_khz;
bool dppclk_div;
int dcfclk_khz;
int dcfclk_deep_sleep_khz;
-- 
2.14.1

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[PATCH 12/20] drm/amd/display: Move OPP mpc tree initialization to hw_init

[Harry Wentland]

From: Eric Bernstein 

Move OPP initialization of mpc tree parameters to hw_init function.

Signed-off-by: Eric Bernstein 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 2 ++
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c  | 7 ---
 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h   | 1 +
 3 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 7ec87fcb22be..f0be2b872668 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -782,6 +782,8 @@ static void dcn10_init_hw(struct dc *dc)
hubp->opp_id = 0xf;
hubp->power_gated = false;
 
+   dc->res_pool->opps[i]->mpc_tree_params.opp_id = 
dc->res_pool->opps[i]->inst;
+   dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
dc->res_pool->opps[i]->mpcc_disconnect_pending[i] = true;
pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index 20d78cf46ab0..5f078868676c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -330,18 +330,11 @@ void dcn10_opp_construct(struct dcn10_opp *oppn10,
const struct dcn10_opp_shift *opp_shift,
const struct dcn10_opp_mask *opp_mask)
 {
-   int i;
 
oppn10->base.ctx = ctx;
oppn10->base.inst = inst;
oppn10->base.funcs = _opp_funcs;
 
-   oppn10->base.mpc_tree_params.opp_id = inst;
-   oppn10->base.mpc_tree_params.opp_list = NULL;
-
-   for (i = 0; i < MAX_PIPES; i++)
-   oppn10->base.mpcc_disconnect_pending[i] = false;
-
oppn10->regs = regs;
oppn10->opp_shift = opp_shift;
oppn10->opp_mask = opp_mask;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
index 42f2bb29a5fc..6da125de9507 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
@@ -300,6 +300,7 @@ struct opp_funcs {
struct output_pixel_processor *opp,
bool enable,
bool polarity);
+
 };
 
 #endif
-- 
2.14.1

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[PATCH 20/20] drm/amd/display: dal 3.1.25

[Harry Wentland]

From: Tony Cheng 

Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 939fa6f85826..3b49ca3027b6 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -38,7 +38,7 @@
 #include "inc/compressor.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.1.24"
+#define DC_VER "3.1.25"
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
-- 
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[PATCH 14/20] drm/amd/display: Move wait for hpd ready out from edp power control.

[Harry Wentland]

From: Yongqiang Sun 

It may take over 200ms for wait hpd ready. To optimize the resume time,
we can power on eDP in init_hw, wait for hpd ready when doing link
training.

also create separate eDP enable function to make sure eDP is powered up
before doing and DPCD access, as HPD low will result in DPDC transaction
failure.

After optimization,
setpowerstate 145ms -> 9.8ms,
DPMS 387ms -> 18.9ms

Signed-off-by: Yongqiang Sun 
Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  | 25 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 11 +-
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  | 15 -
 .../amd/display/dc/dce110/dce110_hw_sequencer.c| 16 --
 .../amd/display/dc/dce110/dce110_hw_sequencer.h|  4 
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |  3 ++-
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |  1 +
 7 files changed, 36 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 13995893cac5..00130152f366 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1271,6 +1271,24 @@ static enum dc_status enable_link_dp(
return status;
 }
 
+static enum dc_status enable_link_edp(
+   struct dc_state *state,
+   struct pipe_ctx *pipe_ctx)
+{
+   enum dc_status status;
+   struct dc_stream_state *stream = pipe_ctx->stream;
+   struct dc_link *link = stream->sink->link;
+
+   link->dc->hwss.edp_power_control(link, true);
+   link->dc->hwss.edp_wait_for_hpd_ready(link, true);
+
+   status = enable_link_dp(state, pipe_ctx);
+
+   link->dc->hwss.edp_backlight_control(link, true);
+
+   return status;
+}
+
 static enum dc_status enable_link_dp_mst(
struct dc_state *state,
struct pipe_ctx *pipe_ctx)
@@ -1746,9 +1764,11 @@ static enum dc_status enable_link(
enum dc_status status = DC_ERROR_UNEXPECTED;
switch (pipe_ctx->stream->signal) {
case SIGNAL_TYPE_DISPLAY_PORT:
-   case SIGNAL_TYPE_EDP:
status = enable_link_dp(state, pipe_ctx);
break;
+   case SIGNAL_TYPE_EDP:
+   status = enable_link_edp(state, pipe_ctx);
+   break;
case SIGNAL_TYPE_DISPLAY_PORT_MST:
status = enable_link_dp_mst(state, pipe_ctx);
msleep(200);
@@ -2282,6 +2302,9 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx, 
int option)
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
deallocate_mst_payload(pipe_ctx);
 
+   if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
+   
core_dc->hwss.edp_backlight_control(pipe_ctx->stream->sink->link, false);
+
core_dc->hwss.disable_stream(pipe_ctx, option);
 
disable_link(pipe_ctx->stream->sink->link, pipe_ctx->stream->signal);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index f2902569be2e..2096f2a179f2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -88,15 +88,7 @@ void dp_enable_link_phy(
}
 
if (dc_is_dp_sst_signal(signal)) {
-   if (signal == SIGNAL_TYPE_EDP) {
-   link->dc->hwss.edp_power_control(link, true);
-   link_enc->funcs->enable_dp_output(
-   link_enc,
-   link_settings,
-   clock_source);
-   link->dc->hwss.edp_backlight_control(link, true);
-   } else
-   link_enc->funcs->enable_dp_output(
+   link_enc->funcs->enable_dp_output(
link_enc,
link_settings,
clock_source);
@@ -138,7 +130,6 @@ void dp_disable_link_phy(struct dc_link *link, enum 
signal_type signal)
dp_receiver_power_ctrl(link, false);
 
if (signal == SIGNAL_TYPE_EDP) {
-   link->dc->hwss.edp_backlight_control(link, false);
edp_receiver_ready_T9(link);
link->link_enc->funcs->disable_output(link->link_enc, signal);
link->dc->hwss.edp_power_control(link, false);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index bad70c6b3aad..a266e3f5e75f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ 

[PATCH 11/20] drm/amd/display: use REG_UPDATE for MPC mux

[Harry Wentland]

From: Eric Bernstein 

Use REG_UPDATE instead of REG_SET for programming MPC out mux.

Signed-off-by: Eric Bernstein 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
index 1e72bd42dca4..179890b1a8c4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c
@@ -218,7 +218,7 @@ struct mpcc *mpc1_insert_plane(
if (tree->opp_list == insert_above_mpcc) {
/* insert the toppest mpcc */
tree->opp_list = new_mpcc;
-   REG_SET(MUX[tree->opp_id], 0, MPC_OUT_MUX, mpcc_id);
+   REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, mpcc_id);
} else {
/* find insert position */
struct mpcc *temp_mpcc = tree->opp_list;
@@ -275,11 +275,11 @@ void mpc1_remove_mpcc(
if (mpcc_to_remove->mpcc_bot) {
/* set the next MPCC in list to be the top MPCC */
tree->opp_list = mpcc_to_remove->mpcc_bot;
-   REG_SET(MUX[tree->opp_id], 0, MPC_OUT_MUX, 
tree->opp_list->mpcc_id);
+   REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 
tree->opp_list->mpcc_id);
} else {
/* there are no other MPCC is list */
tree->opp_list = NULL;
-   REG_SET(MUX[tree->opp_id], 0, MPC_OUT_MUX, 0xf);
+   REG_UPDATE(MUX[tree->opp_id], MPC_OUT_MUX, 0xf);
}
} else {
/* find mpcc to remove MPCC list */
@@ -359,7 +359,7 @@ void mpc1_mpc_init(struct mpc *mpc)
 
for (opp_id = 0; opp_id < MAX_OPP; opp_id++) {
if (REG(MUX[opp_id]))
-   REG_SET(MUX[opp_id], 0, MPC_OUT_MUX, 0xf);
+   REG_UPDATE(MUX[opp_id], MPC_OUT_MUX, 0xf);
}
 }
 
-- 
2.14.1

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[PATCH 19/20] drm/amd/display: Add TODO item to remove vector.c

[Harry Wentland]

Signed-off-by: Harry Wentland 
Reviewed-by: Jordan Lazare 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/TODO | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/TODO b/drivers/gpu/drm/amd/display/TODO
index 46464678f2b3..357d59648401 100644
--- a/drivers/gpu/drm/amd/display/TODO
+++ b/drivers/gpu/drm/amd/display/TODO
@@ -105,3 +105,6 @@ useless with filtering output. dynamic debug printing might 
be an option.
 20. Use kernel i2c device to program HDMI retimer. Some boards have an HDMI
 retimer that we need to program to pass PHY compliance. Currently that's
 bypassing the i2c device and goes directly to HW. This should be changed.
+
+21. Remove vector.c from dc/basics. It's used in DDC code which can probably
+be simplified enough to no longer need a vector implementation.
-- 
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[PATCH 01/20] drm/amd/display: really fix time out in init sequence

[Harry Wentland]

From: Tony Cheng 

REG_UPDATE_2 return the reg value it write out through MMIO
we need to do a REG_READ to confirm the value is written out

Signed-off-by: Tony Cheng 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 1984ac2eb740..2d843b2d5f86 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -42,13 +42,14 @@ void hubp1_set_blank(struct hubp *hubp, bool blank)
 {
struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
uint32_t blank_en = blank ? 1 : 0;
-   uint32_t reg_val = 0;
 
-   reg_val = REG_UPDATE_2(DCHUBP_CNTL,
+   REG_UPDATE_2(DCHUBP_CNTL,
HUBP_BLANK_EN, blank_en,
HUBP_TTU_DISABLE, blank_en);
 
if (blank) {
+   uint32_t reg_val = REG_READ(DCHUBP_CNTL);
+
if (reg_val) {
/* init sequence workaround: in case HUBP is
 * power gated, this wait would timeout.
-- 
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[PATCH 16/20] drm/amd/display: use clamping rather than truncation for CM fp conversions

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c | 24 ++
 .../gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 14 ++---
 drivers/gpu/drm/amd/display/include/fixed31_32.h   |  4 ++--
 3 files changed, 29 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c 
b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
index 13f8b8c02212..011a97f82fb6 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
@@ -554,6 +554,22 @@ static inline uint32_t ux_dy(
return result | fractional_part;
 }
 
+static inline uint32_t clamp_ux_dy(
+   int64_t value,
+   uint32_t integer_bits,
+   uint32_t fractional_bits,
+   uint32_t min_clamp)
+{
+   uint32_t truncated_val = ux_dy(value, integer_bits, fractional_bits);
+
+   if (value >= (1LL << (integer_bits + 
FIXED31_32_BITS_PER_FRACTIONAL_PART)))
+   return (1 << (integer_bits + fractional_bits)) - 1;
+   else if (truncated_val > min_clamp)
+   return truncated_val;
+   else
+   return min_clamp;
+}
+
 uint32_t dal_fixed31_32_u2d19(
struct fixed31_32 arg)
 {
@@ -566,14 +582,14 @@ uint32_t dal_fixed31_32_u0d19(
return ux_dy(arg.value, 0, 19);
 }
 
-uint32_t dal_fixed31_32_u0d14(
+uint32_t dal_fixed31_32_clamp_u0d14(
struct fixed31_32 arg)
 {
-   return ux_dy(arg.value, 1, 14);
+   return clamp_ux_dy(arg.value, 0, 14, 1);
 }
 
-uint32_t dal_fixed31_32_u0d10(
+uint32_t dal_fixed31_32_clamp_u0d10(
struct fixed31_32 arg)
 {
-   return ux_dy(arg.value, 1, 10);
+   return clamp_ux_dy(arg.value, 0, 10, 1);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index 352ae7bf9a3f..53ba3600ee6a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -169,7 +169,7 @@ bool cm_helper_convert_to_custom_float(
}
 
if (fixpoint == true)
-   arr_points[1].custom_float_y = 
dal_fixed31_32_u0d14(arr_points[1].y);
+   arr_points[1].custom_float_y = 
dal_fixed31_32_clamp_u0d14(arr_points[1].y);
else if (!convert_to_custom_float_format(arr_points[1].y, ,
_points[1].custom_float_y)) {
BREAK_TO_DEBUGGER();
@@ -395,12 +395,12 @@ bool cm_helper_translate_curve_to_hw_format(
rgb->delta_blue  = dal_fixed31_32_sub(rgb_plus_1->blue,  
rgb->blue);
 
if (fixpoint == true) {
-   rgb->delta_red_reg   = 
dal_fixed31_32_u0d10(rgb->delta_red);
-   rgb->delta_green_reg = 
dal_fixed31_32_u0d10(rgb->delta_green);
-   rgb->delta_blue_reg  = 
dal_fixed31_32_u0d10(rgb->delta_blue);
-   rgb->red_reg = dal_fixed31_32_u0d14(rgb->red);
-   rgb->green_reg   = dal_fixed31_32_u0d14(rgb->green);
-   rgb->blue_reg= dal_fixed31_32_u0d14(rgb->blue);
+   rgb->delta_red_reg   = 
dal_fixed31_32_clamp_u0d10(rgb->delta_red);
+   rgb->delta_green_reg = 
dal_fixed31_32_clamp_u0d10(rgb->delta_green);
+   rgb->delta_blue_reg  = 
dal_fixed31_32_clamp_u0d10(rgb->delta_blue);
+   rgb->red_reg = 
dal_fixed31_32_clamp_u0d14(rgb->red);
+   rgb->green_reg   = 
dal_fixed31_32_clamp_u0d14(rgb->green);
+   rgb->blue_reg= 
dal_fixed31_32_clamp_u0d14(rgb->blue);
}
 
++rgb_plus_1;
diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h 
b/drivers/gpu/drm/amd/display/include/fixed31_32.h
index c4848fadc70e..4badaedbaadd 100644
--- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
+++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
@@ -464,10 +464,10 @@ uint32_t dal_fixed31_32_u0d19(
struct fixed31_32 arg);
 
 
-uint32_t dal_fixed31_32_u0d14(
+uint32_t dal_fixed31_32_clamp_u0d14(
struct fixed31_32 arg);
 
-uint32_t dal_fixed31_32_u0d10(
+uint32_t dal_fixed31_32_clamp_u0d10(
struct fixed31_32 arg);
 
 #endif
-- 
2.14.1

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[PATCH 10/20] drm/amd/display: Correct fixed point calculation.

[Harry Wentland]

From: Vitaly Prosyak 

When convert from fixed31_32 to other fixed point
format use math operation round instead of floor.

Signed-off-by: Vitaly Prosyak 
Reviewed-by: Roman Li 
Reviewed-by: Krunoslav Kovac 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/basics/conversion.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/basics/conversion.c 
b/drivers/gpu/drm/amd/display/dc/basics/conversion.c
index 23c9a0ec0181..310964915a83 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/conversion.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/conversion.c
@@ -46,7 +46,7 @@ uint16_t fixed_point_to_int_frac(
arg));
 
if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
-   numerator = (uint16_t)dal_fixed31_32_floor(
+   numerator = (uint16_t)dal_fixed31_32_round(
dal_fixed31_32_mul_int(
arg,
divisor));
-- 
2.14.1

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[PATCH 00/20] DC Patches Dec 1, 2017

[Harry Wentland]

 * Bunch of fixes for DCN BW
 * DCN programming sequence optimizations
 * Leave Freesync disabled unless usermode turns it on
 * Print DC version at initialization

Dmytro Laktyushkin (4):
  drm/amd/display: set chroma taps to 1 when not scaling
  drm/amd/display: Add dppclk to dcn_bw_clocks
  drm/amd/display: add assert to verify dcn_calc input validity
  drm/amd/display: use clamping rather than truncation for CM fp
conversions

Eric Bernstein (2):
  drm/amd/display: use REG_UPDATE for MPC mux
  drm/amd/display: Move OPP mpc tree initialization to hw_init

Eric Yang (1):
  drm/amd/display: fix missing pixel clock adjustment for dongle

Harry Wentland (4):
  drm/amd/display: Print DC_VER at DC init
  drm/amd/display: Remove redundant NULL check in DCE11 HWSS
  drm/amd/display: Remove grph_object_id.c and move function to
bios_parser
  drm/amd/display: Add TODO item to remove vector.c

Leo (Sunpeng) Li (1):
  drm/amd/display: Disable freesync by default

Tony Cheng (2):
  drm/amd/display: really fix time out in init sequence
  drm/amd/display: dal 3.1.25

Vitaly Prosyak (2):
  drm/amd/display: Move unity TF type to predefined types
  drm/amd/display: Correct fixed point calculation.

Yongqiang Sun (1):
  drm/amd/display: Move wait for hpd ready out from edp power control.

Yue Hin Lau (3):
  drm/amd/display: dpp clean up
  drm/amd/display: OPTC cleanup/implementation
  drm/amd/display: remove format_control from set_cursor_attributes

 drivers/gpu/drm/amd/display/TODO   |   3 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |   8 +-
 drivers/gpu/drm/amd/display/dc/basics/Makefile |   2 +-
 drivers/gpu/drm/amd/display/dc/basics/conversion.c |   2 +-
 drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c |  24 +-
 .../gpu/drm/amd/display/dc/basics/grph_object_id.c |  75 -
 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c  |  46 +++
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c   |  20 ++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c  |  29 +-
 drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c |  11 +-
 drivers/gpu/drm/amd/display/dc/dc.h|   4 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h |   3 +-
 .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c  |  15 -
 .../amd/display/dc/dce110/dce110_hw_sequencer.c|  19 +-
 .../amd/display/dc/dce110/dce110_hw_sequencer.h|   4 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c |  18 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c   |  16 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   |   3 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c|   4 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c  |   5 +-
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |   8 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c   |   8 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c   |   7 -
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  10 +-
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  | 316 ++---
 .../amd/display/dc/dcn10/dcn10_timing_generator.h  |  90 +-
 drivers/gpu/drm/amd/display/dc/inc/core_types.h|   1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h  |   7 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/opp.h|   1 +
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h  |   1 +
 drivers/gpu/drm/amd/display/include/fixed31_32.h   |   4 +-
 .../gpu/drm/amd/display/include/grph_object_id.h   |   4 -
 32 files changed, 413 insertions(+), 355 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/display/dc/basics/grph_object_id.c

-- 
2.14.1

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[PATCH 17/20] drm/amd/display: Remove redundant NULL check in DCE11 HWSS

[Harry Wentland]

We already check this a couple lines earlier.

Signed-off-by: Harry Wentland 
Reviewed-by: Jordan Lazare 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index dd8386778361..80d36610c302 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -2017,8 +2017,7 @@ enum dc_status dce110_apply_ctx_to_hw(
if (pipe_ctx->stream == pipe_ctx_old->stream)
continue;
 
-   if (pipe_ctx->stream && pipe_ctx_old->stream
-   && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
+   if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, 
pipe_ctx))
continue;
 
if (pipe_ctx->top_pipe)
-- 
2.14.1

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[PATCH 15/20] drm/amd/display: remove format_control from set_cursor_attributes

[Harry Wentland]

From: Yue Hin Lau 

Signed-off-by: Yue Hin Lau 
Reviewed-by: Eric Bernstein 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 6db1839d7155..f2a08b156cf0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -400,13 +400,6 @@ void dpp1_set_cursor_attributes(
REG_UPDATE(CURSOR0_COLOR1,
CUR0_COLOR1, 0x);
}
-
-   /* TODO: Fixed vs float */
-
-   REG_UPDATE_3(FORMAT_CONTROL,
-   CNVC_BYPASS, 0,
-   FORMAT_CONTROL__ALPHA_EN, 1,
-   FORMAT_EXPANSION_MODE, 0);
 }
 
 
-- 
2.14.1

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[PATCH 18/20] drm/amd/display: Remove grph_object_id.c and move function to bios_parser

[Harry Wentland]

Signed-off-by: Harry Wentland 
Reviewed-by: Jordan Lazare 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/basics/Makefile |  2 +-
 .../gpu/drm/amd/display/dc/basics/grph_object_id.c | 75 --
 drivers/gpu/drm/amd/display/dc/bios/bios_parser.c  | 46 +
 .../gpu/drm/amd/display/include/grph_object_id.h   |  4 --
 4 files changed, 47 insertions(+), 80 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/display/dc/basics/grph_object_id.c

diff --git a/drivers/gpu/drm/amd/display/dc/basics/Makefile 
b/drivers/gpu/drm/amd/display/dc/basics/Makefile
index 43c5ccdeeb72..ddc7fabedd94 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/basics/Makefile
@@ -3,7 +3,7 @@
 # It provides the general basic services required by other DAL
 # subcomponents.
 
-BASICS = conversion.o fixpt31_32.o fixpt32_32.o grph_object_id.o \
+BASICS = conversion.o fixpt31_32.o fixpt32_32.o \
logger.o log_helpers.o vector.o
 
 AMD_DAL_BASICS = $(addprefix $(AMDDALPATH)/dc/basics/,$(BASICS))
diff --git a/drivers/gpu/drm/amd/display/dc/basics/grph_object_id.c 
b/drivers/gpu/drm/amd/display/dc/basics/grph_object_id.c
deleted file mode 100644
index 147822545252..
--- a/drivers/gpu/drm/amd/display/dc/basics/grph_object_id.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright 2012-15 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
-#include "dm_services.h"
-#include "include/grph_object_id.h"
-
-static bool dal_graphics_object_id_is_valid(struct graphics_object_id id)
-{
-   bool rc = true;
-
-   switch (id.type) {
-   case OBJECT_TYPE_UNKNOWN:
-   rc = false;
-   break;
-   case OBJECT_TYPE_GPU:
-   case OBJECT_TYPE_ENGINE:
-   /* do NOT check for id.id == 0 */
-   if (id.enum_id == ENUM_ID_UNKNOWN)
-   rc = false;
-   break;
-   default:
-   if (id.id == 0 || id.enum_id == ENUM_ID_UNKNOWN)
-   rc = false;
-   break;
-   }
-
-   return rc;
-}
-
-bool dal_graphics_object_id_is_equal(
-   struct graphics_object_id id1,
-   struct graphics_object_id id2)
-{
-   if (false == dal_graphics_object_id_is_valid(id1)) {
-   dm_output_to_console(
-   "%s: Warning: comparing invalid object 'id1'!\n", __func__);
-   return false;
-   }
-
-   if (false == dal_graphics_object_id_is_valid(id2)) {
-   dm_output_to_console(
-   "%s: Warning: comparing invalid object 'id2'!\n", __func__);
-   return false;
-   }
-
-   if (id1.id == id2.id && id1.enum_id == id2.enum_id
-   && id1.type == id2.type)
-   return true;
-
-   return false;
-}
-
-
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c 
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index 86e6438c5cf3..21fb78e8048d 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -2254,6 +2254,52 @@ static enum bp_result get_gpio_i2c_info(struct 
bios_parser *bp,
return BP_RESULT_OK;
 }
 
+static bool dal_graphics_object_id_is_valid(struct graphics_object_id id)
+{
+   bool rc = true;
+
+   switch (id.type) {
+   case OBJECT_TYPE_UNKNOWN:
+   rc = false;
+   break;
+   case OBJECT_TYPE_GPU:
+   case OBJECT_TYPE_ENGINE:
+   /* do NOT check for id.id == 0 */
+   if (id.enum_id == ENUM_ID_UNKNOWN)
+   rc = false;
+   break;
+   default:
+   if (id.id == 0 || id.enum_id == ENUM_ID_UNKNOWN)
+   rc = false;
+   break;
+   }
+
+   return 

[PATCH 13/20] drm/amd/display: fix missing pixel clock adjustment for dongle

[Harry Wentland]

From: Eric Yang 

Signed-off-by: Eric Yang 
Reviewed-by: Tony Cheng 
Reviewed-by: Andrew Jiang 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 0b7058fddc2e..13995893cac5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1801,7 +1801,7 @@ static void disable_link(struct dc_link *link, enum 
signal_type signal)
link->link_enc->funcs->disable_output(link->link_enc, signal);
 }
 
-bool dp_active_dongle_validate_timing(
+static bool dp_active_dongle_validate_timing(
const struct dc_crtc_timing *timing,
const struct dc_dongle_caps *dongle_caps)
 {
@@ -1833,6 +1833,8 @@ bool dp_active_dongle_validate_timing(
/* Check Color Depth and Pixel Clock */
if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
required_pix_clk /= 2;
+   else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
+   required_pix_clk = required_pix_clk * 2 / 3;
 
switch (timing->display_color_depth) {
case COLOR_DEPTH_666:
-- 
2.14.1

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[PATCH 09/20] drm/amd/display: OPTC cleanup/implementation

[Harry Wentland]

From: Yue Hin Lau 

Signed-off-by: Yue Hin Lau 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c  |   2 +-
 .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c  |  10 +-
 .../amd/display/dc/dcn10/dcn10_timing_generator.c  | 316 ++---
 .../amd/display/dc/dcn10/dcn10_timing_generator.h  |  90 +-
 4 files changed, 244 insertions(+), 174 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 39a4d1a86583..7ec87fcb22be 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -159,7 +159,7 @@ void dcn10_log_hw_state(struct dc *dc)
struct timing_generator *tg = pool->timing_generators[i];
struct dcn_otg_state s = {0};
 
-   tgn10_read_otg_state(DCN10TG_FROM_TG(tg), );
+   optc1_read_otg_state(DCN10TG_FROM_TG(tg), );
 
//only print if OTG master is enabled
if ((s.otg_enabled & 1) == 0)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index a9a5d176cb70..65ce96ba6443 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -348,18 +348,18 @@ static const struct dcn_mpc_mask mpc_mask = {
 #define tg_regs(id)\
 [id] = {TG_COMMON_REG_LIST_DCN1_0(id)}
 
-static const struct dcn_tg_registers tg_regs[] = {
+static const struct dcn_optc_registers tg_regs[] = {
tg_regs(0),
tg_regs(1),
tg_regs(2),
tg_regs(3),
 };
 
-static const struct dcn_tg_shift tg_shift = {
+static const struct dcn_optc_shift tg_shift = {
TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT)
 };
 
-static const struct dcn_tg_mask tg_mask = {
+static const struct dcn_optc_mask tg_mask = {
TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK)
 };
 
@@ -553,8 +553,8 @@ static struct timing_generator 
*dcn10_timing_generator_create(
struct dc_context *ctx,
uint32_t instance)
 {
-   struct dcn10_timing_generator *tgn10 =
-   kzalloc(sizeof(struct dcn10_timing_generator), GFP_KERNEL);
+   struct optc *tgn10 =
+   kzalloc(sizeof(struct optc), GFP_KERNEL);
 
if (!tgn10)
return NULL;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
index 4940fdbc6e80..f73752c7de1a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_timing_generator.c
@@ -28,14 +28,14 @@
 #include "dc.h"
 
 #define REG(reg)\
-   tgn10->tg_regs->reg
+   optc1->tg_regs->reg
 
 #define CTX \
-   tgn10->base.ctx
+   optc1->base.ctx
 
 #undef FN
 #define FN(reg_name, field_name) \
-   tgn10->tg_shift->field_name, tgn10->tg_mask->field_name
+   optc1->tg_shift->field_name, optc1->tg_mask->field_name
 
 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
 
@@ -45,8 +45,8 @@
 * This is a workaround for a bug that has existed since R5xx and has not been
 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
 */
-static void tgn10_apply_front_porch_workaround(
-   struct timing_generator *tg,
+static void optc1_apply_front_porch_workaround(
+   struct timing_generator *optc,
struct dc_crtc_timing *timing)
 {
if (timing->flags.INTERLACE == 1) {
@@ -58,30 +58,30 @@ static void tgn10_apply_front_porch_workaround(
}
 }
 
-static void tgn10_program_global_sync(
-   struct timing_generator *tg)
+void optc1_program_global_sync(
+   struct timing_generator *optc)
 {
-   struct dcn10_timing_generator *tgn10 = DCN10TG_FROM_TG(tg);
+   struct optc *optc1 = DCN10TG_FROM_TG(optc);
 
-   if (tg->dlg_otg_param.vstartup_start == 0) {
+   if (optc->dlg_otg_param.vstartup_start == 0) {
BREAK_TO_DEBUGGER();
return;
}
 
REG_SET(OTG_VSTARTUP_PARAM, 0,
-   VSTARTUP_START, tg->dlg_otg_param.vstartup_start);
+   VSTARTUP_START, optc->dlg_otg_param.vstartup_start);
 
REG_SET_2(OTG_VUPDATE_PARAM, 0,
-   VUPDATE_OFFSET, tg->dlg_otg_param.vupdate_offset,
-   VUPDATE_WIDTH, tg->dlg_otg_param.vupdate_width);
+   VUPDATE_OFFSET, optc->dlg_otg_param.vupdate_offset,
+   VUPDATE_WIDTH, optc->dlg_otg_param.vupdate_width);
 
REG_SET(OTG_VREADY_PARAM, 0,
-   VREADY_OFFSET, tg->dlg_otg_param.vready_offset);
+   VREADY_OFFSET, optc->dlg_otg_param.vready_offset);
 }
 

[PATCH 04/20] drm/amd/display: set chroma taps to 1 when not scaling

[Harry Wentland]

From: Dmytro Laktyushkin 

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 9 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 9 -
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index b5bc9159f48e..453ec1c6c181 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -897,6 +897,15 @@ bool dcn_validate_bandwidth(
v->override_vta_ps[input_idx] = 
pipe->plane_res.scl_data.taps.v_taps;
v->override_hta_pschroma[input_idx] = 
pipe->plane_res.scl_data.taps.h_taps_c;
v->override_vta_pschroma[input_idx] = 
pipe->plane_res.scl_data.taps.v_taps_c;
+   /*
+* Spreadsheet doesn't handle taps_c is one properly,
+* need to force Chroma to always be scaled to pass
+* bandwidth validation.
+*/
+   if (v->override_hta_pschroma[input_idx] == 1)
+   v->override_hta_pschroma[input_idx] = 2;
+   if (v->override_vta_pschroma[input_idx] == 1)
+   v->override_vta_pschroma[input_idx] = 2;
v->source_scan[input_idx] = 
(pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor;
}
if (v->is_line_buffer_bpp_fixed == dcn_bw_yes)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 5a95fa03bc17..6db1839d7155 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -159,11 +159,10 @@ bool dpp_get_optimal_number_of_taps(
scl_data->taps.h_taps = 1;
if (IDENTITY_RATIO(scl_data->ratios.vert))
scl_data->taps.v_taps = 1;
-   /*
-* Spreadsheet doesn't handle taps_c is one properly,
-* need to force Chroma to always be scaled to pass
-* bandwidth validation.
-*/
+   if (IDENTITY_RATIO(scl_data->ratios.horz_c))
+   scl_data->taps.h_taps_c = 1;
+   if (IDENTITY_RATIO(scl_data->ratios.vert_c))
+   scl_data->taps.v_taps_c = 1;
}
 
return true;
-- 
2.14.1

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[PATCH 08/20] drm/amd/display: Move unity TF type to predefined types

[Harry Wentland]

From: Vitaly Prosyak 

Also handle fixpoint y values for CM curves

Signed-off-by: Vitaly Prosyak 
Reviewed-by: Tony Cheng 
Acked-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/dc/dc.h| 2 +-
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c | 6 --
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h   | 3 +--
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 74286d3001ae..939fa6f85826 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -343,7 +343,6 @@ enum dc_transfer_func_type {
TF_TYPE_PREDEFINED,
TF_TYPE_DISTRIBUTED_POINTS,
TF_TYPE_BYPASS,
-   TF_TYPE_UNITY
 };
 
 struct dc_transfer_func_distributed_points {
@@ -362,6 +361,7 @@ enum dc_transfer_func_predefined {
TRANSFER_FUNCTION_BT709,
TRANSFER_FUNCTION_PQ,
TRANSFER_FUNCTION_LINEAR,
+   TRANSFER_FUNCTION_UNITY,
 };
 
 struct dc_transfer_func {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index e132d0163787..352ae7bf9a3f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -168,8 +168,10 @@ bool cm_helper_convert_to_custom_float(
return false;
}
 
-   if (!convert_to_custom_float_format(arr_points[1].y, ,
-   _points[1].custom_float_y)) {
+   if (fixpoint == true)
+   arr_points[1].custom_float_y = 
dal_fixed31_32_u0d14(arr_points[1].y);
+   else if (!convert_to_custom_float_format(arr_points[1].y, ,
+   _points[1].custom_float_y)) {
BREAK_TO_DEBUGGER();
return false;
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 41f0c84bfa09..b6d526067cb5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -731,7 +731,7 @@
type CM_BLNDGAM_LUT_WRITE_EN_MASK; \
type CM_BLNDGAM_LUT_WRITE_SEL; \
type CM_BLNDGAM_LUT_INDEX; \
-   type CM_BLNDGAM_LUT_DATA; \
+   type BLNDGAM_MEM_PWR_FORCE; \
type CM_3DLUT_MODE; \
type CM_3DLUT_SIZE; \
type CM_3DLUT_INDEX; \
@@ -1147,7 +1147,6 @@ struct dcn_dpp_mask {
uint32_t CM_BLNDGAM_RAMA_REGION_30_31; \
uint32_t CM_BLNDGAM_RAMA_REGION_32_33; \
uint32_t CM_BLNDGAM_LUT_INDEX; \
-   uint32_t CM_BLNDGAM_LUT_DATA; \
uint32_t CM_3DLUT_MODE; \
uint32_t CM_3DLUT_INDEX; \
uint32_t CM_3DLUT_DATA; \
-- 
2.14.1

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[PATCH 03/20] drm/amd/display: Disable freesync by default

[Harry Wentland]

From: "Leo (Sunpeng) Li" 

Freesync properties are being set to the 'freesync_capable' flag,
which will enable freesync on all freesync capable displays. Don't do
this, since freesync should be disabled by default regardless of
capabilities.

Signed-off-by: Leo (Sunpeng) Li 
Reviewed-by: Harry Wentland 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index d2d9cf5e0cfc..7d86c9850b7a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5005,10 +5005,6 @@ void amdgpu_dm_add_sink_to_freesync_module(struct 
drm_connector *connector,
dm_con_state->freesync_capable = true;
}
}
-
-   dm_con_state->user_enable.enable_for_gaming = 
dm_con_state->freesync_capable;
-   dm_con_state->user_enable.enable_for_static = 
dm_con_state->freesync_capable;
-   dm_con_state->user_enable.enable_for_video = 
dm_con_state->freesync_capable;
 }
 
 void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector 
*connector)
-- 
2.14.1

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Re: [PATCH 1/2] drm/amdgpu: add license to Makefiles

[Christian König]

Am 01.12.2017 um 03:30 schrieb Alex Deucher:

Was missing license text.

Signed-off-by: Alex Deucher 


We need copyright text on the Makefiles as well? Well, yeah makes sense. 
Going to keep that in mind.


Acked-by: Christian König  for both patches.

Regards,
Christian.


---
  drivers/gpu/drm/amd/acp/Makefile   | 21 
  drivers/gpu/drm/amd/amdgpu/Makefile| 21 
  drivers/gpu/drm/amd/amdkfd/Makefile| 21 
  drivers/gpu/drm/amd/display/Makefile   | 21 
  drivers/gpu/drm/amd/display/amdgpu_dm/Makefile | 21 
  drivers/gpu/drm/amd/display/dc/Makefile| 21 
  drivers/gpu/drm/amd/display/dc/basics/Makefile | 21 
  drivers/gpu/drm/amd/display/dc/bios/Makefile   | 21 
  drivers/gpu/drm/amd/display/dc/calcs/Makefile  | 21 
  drivers/gpu/drm/amd/display/dc/dce/Makefile| 21 
  drivers/gpu/drm/amd/display/dc/dce100/Makefile | 21 
  drivers/gpu/drm/amd/display/dc/dce110/Makefile | 21 
  drivers/gpu/drm/amd/display/dc/dce112/Makefile | 21 
  drivers/gpu/drm/amd/display/dc/dce120/Makefile | 23 +-
  drivers/gpu/drm/amd/display/dc/dce80/Makefile  | 21 
  drivers/gpu/drm/amd/display/dc/dcn10/Makefile  | 21 
  drivers/gpu/drm/amd/display/dc/dml/Makefile| 21 
  drivers/gpu/drm/amd/display/dc/gpio/Makefile   | 21 
  drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 21 
  drivers/gpu/drm/amd/display/dc/irq/Makefile| 21 
  drivers/gpu/drm/amd/display/dc/virtual/Makefile| 21 
  .../gpu/drm/amd/display/modules/freesync/Makefile  | 21 
  drivers/gpu/drm/amd/lib/Makefile   | 21 
  drivers/gpu/drm/amd/powerplay/Makefile | 21 
  drivers/gpu/drm/amd/powerplay/hwmgr/Makefile   | 21 
  drivers/gpu/drm/amd/powerplay/smumgr/Makefile  | 21 
  26 files changed, 547 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/acp/Makefile b/drivers/gpu/drm/amd/acp/Makefile
index 8a08e81ee90d..d4176a3fb706 100644
--- a/drivers/gpu/drm/amd/acp/Makefile
+++ b/drivers/gpu/drm/amd/acp/Makefile
@@ -1,4 +1,25 @@
  #
+# Copyright 2017 Advanced Micro Devices, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+# OTHER DEALINGS IN THE SOFTWARE.
+#
+#
  # Makefile for the ACP, which is a sub-component
  # of AMDSOC/AMDGPU drm driver.
  # It provides the HW control for ACP related functionalities.
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
b/drivers/gpu/drm/amd/amdgpu/Makefile
index 6a025c476b37..90202cf4cd1e 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -1,4 +1,25 @@
  #
+# Copyright 2017 Advanced Micro Devices, Inc.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A 

Re: [PATCH 0/4] Backported amdgpu ttm deadlock fixes for 4.14

[Christian König]

Am 01.12.2017 um 01:23 schrieb Lyude Paul:

I haven't gone to see where it started, but as of late a good number of
pretty nasty deadlock issues have appeared with the kernel. Easy
reproduction recipe on a laptop with i915/amdgpu prime with lockdep enabled:

DRI_PRIME=1 glxinfo


Acked-by: Christian König 

Thanks for taking care of this,
Christian.



Additionally, some more race conditions exist that I've managed to
trigger with piglit and lockdep enabled after applying these patches:

 =
 WARNING: suspicious RCU usage
 4.14.3Lyude-Test+ #2 Not tainted
 -
 ./include/linux/reservation.h:216 suspicious rcu_dereference_protected() 
usage!

 other info that might help us debug this:

 rcu_scheduler_active = 2, debug_locks = 1
 1 lock held by ext_image_dma_b/27451:
  #0:  (reservation_ww_class_mutex){+.+.}, at: [] 
ttm_bo_unref+0x9f/0x3c0 [ttm]

 stack backtrace:
 CPU: 0 PID: 27451 Comm: ext_image_dma_b Not tainted 4.14.3Lyude-Test+ #2
 Hardware name: HP HP ZBook 15 G4/8275, BIOS P70 Ver. 01.02 06/09/2017
 Call Trace:
  dump_stack+0x8e/0xce
  lockdep_rcu_suspicious+0xc5/0x100
  reservation_object_copy_fences+0x292/0x2b0
  ? ttm_bo_unref+0x9f/0x3c0 [ttm]
  ttm_bo_unref+0xbd/0x3c0 [ttm]
  amdgpu_bo_unref+0x2a/0x50 [amdgpu]
  amdgpu_gem_object_free+0x4b/0x50 [amdgpu]
  drm_gem_object_free+0x1f/0x40 [drm]
  drm_gem_object_put_unlocked+0x40/0xb0 [drm]
  drm_gem_object_handle_put_unlocked+0x6c/0xb0 [drm]
  drm_gem_object_release_handle+0x51/0x90 [drm]
  drm_gem_handle_delete+0x5e/0x90 [drm]
  ? drm_gem_handle_create+0x40/0x40 [drm]
  drm_gem_close_ioctl+0x20/0x30 [drm]
  drm_ioctl_kernel+0x5d/0xb0 [drm]
  drm_ioctl+0x2f7/0x3b0 [drm]
  ? drm_gem_handle_create+0x40/0x40 [drm]
  ? trace_hardirqs_on_caller+0xf4/0x190
  ? trace_hardirqs_on+0xd/0x10
  amdgpu_drm_ioctl+0x4f/0x90 [amdgpu]
  do_vfs_ioctl+0x93/0x670
  ? __fget+0x108/0x1f0
  SyS_ioctl+0x79/0x90
  entry_SYSCALL_64_fastpath+0x23/0xc2

I've also added the relevant fixes for the issue mentioned above.

Christian König (3):
   drm/ttm: fix ttm_bo_cleanup_refs_or_queue once more
   dma-buf: make reservation_object_copy_fences rcu save
   drm/amdgpu: reserve root PD while releasing it

Michel Dänzer (1):
   drm/ttm: Always and only destroy bo->ttm_resv in ttm_bo_release_list

  drivers/dma-buf/reservation.c  | 56 +-
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 13 ++--
  drivers/gpu/drm/ttm/ttm_bo.c   | 43 +-
  3 files changed, 74 insertions(+), 38 deletions(-)

--
2.14.3

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Re: [PATCH 2/5] drm/amdgpu: Use the dynamic IP based offset for register access for SOC15

[Christian König]

Am 30.11.2017 um 23:53 schrieb Shaoyun Liu:

Change-Id: I29f33ee3b4bbd6737f3426385a9e8452fb528a67
Signed-off-by: Shaoyun Liu 


Reviewed-by: Christian König 


---
  drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c| 126 ++
  drivers/gpu/drm/amd/amdgpu/soc15_common.h |  34 ++--
  2 files changed, 65 insertions(+), 95 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 4c55f21..458667d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -107,23 +107,11 @@
SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ), 0x0018773f, 
0x0002
  };
  
-static u32 sdma_v4_0_get_reg_offset(u32 instance, u32 internal_offset)

+static u32 sdma_v4_0_get_reg_offset(struct amdgpu_device *adev,
+   u32 instance, u32 offset)
  {
-   u32 base = 0;
-
-   switch (instance) {
-   case 0:
-   base = SDMA0_BASE.instance[0].segment[0];
-   break;
-   case 1:
-   base = SDMA1_BASE.instance[0].segment[0];
-   break;
-   default:
-   BUG();
-   break;
-   }
-
-   return base + internal_offset;
+   return ( 0 == instance ? (adev->reg_offset[SDMA0_HWIP][0][0] + offset) :
+   (adev->reg_offset[SDMA1_HWIP][0][0] + offset));
  }
  
  static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)

@@ -265,8 +253,8 @@ static uint64_t sdma_v4_0_ring_get_wptr(struct amdgpu_ring 
*ring)
int me = (ring == >sdma.instance[0].ring) ? 0 : 1;
  
  		wptr = _wptr;

-   lowbit = RREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR)) 
>> 2;
-   highbit = RREG32(sdma_v4_0_get_reg_offset(me, 
mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
+   lowbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, 
mmSDMA0_GFX_RB_WPTR)) >> 2;
+   highbit = RREG32(sdma_v4_0_get_reg_offset(adev, me, 
mmSDMA0_GFX_RB_WPTR_HI)) >> 2;
  
  		DRM_DEBUG("wptr [%i]high== 0x%08x low==0x%08x\n",

me, highbit, lowbit);
@@ -315,8 +303,8 @@ static void sdma_v4_0_ring_set_wptr(struct amdgpu_ring 
*ring)
lower_32_bits(ring->wptr << 2),
me,
upper_32_bits(ring->wptr << 2));
-   WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR), 
lower_32_bits(ring->wptr << 2));
-   WREG32(sdma_v4_0_get_reg_offset(me, mmSDMA0_GFX_RB_WPTR_HI), 
upper_32_bits(ring->wptr << 2));
+   WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR), 
lower_32_bits(ring->wptr << 2));
+   WREG32(sdma_v4_0_get_reg_offset(adev, me, mmSDMA0_GFX_RB_WPTR_HI), 
upper_32_bits(ring->wptr << 2));
}
  }
  
@@ -460,12 +448,12 @@ static void sdma_v4_0_gfx_stop(struct amdgpu_device *adev)

amdgpu_ttm_set_active_vram_size(adev, 
adev->mc.visible_vram_size);
  
  	for (i = 0; i < adev->sdma.num_instances; i++) {

-   rb_cntl = RREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_RB_CNTL));
+   rb_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, 
mmSDMA0_GFX_RB_CNTL));
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 
0);
-   WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_RB_CNTL), 
rb_cntl);
-   ib_cntl = RREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_GFX_IB_CNTL));
+   WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), 
rb_cntl);
+   ib_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, 
mmSDMA0_GFX_IB_CNTL));
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 
0);
-   WREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_GFX_IB_CNTL), 
ib_cntl);
+   WREG32(sdma_v4_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), 
ib_cntl);
}
  
  	sdma0->ready = false;

@@ -522,18 +510,18 @@ static void sdma_v4_0_ctx_switch_enable(struct 
amdgpu_device *adev, bool enable)
}
  
  	for (i = 0; i < adev->sdma.num_instances; i++) {

-   f32_cntl = RREG32(sdma_v4_0_get_reg_offset(i, mmSDMA0_CNTL));
+   f32_cntl = RREG32(sdma_v4_0_get_reg_offset(adev, i, 
mmSDMA0_CNTL));
f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
AUTO_CTXSW_ENABLE, enable ? 1 : 0);
if (enable && amdgpu_sdma_phase_quantum) {
-   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_PHASE0_QUANTUM),
+   WREG32(sdma_v4_0_get_reg_offset(adev, i, 
mmSDMA0_PHASE0_QUANTUM),
   phase_quantum);
-   WREG32(sdma_v4_0_get_reg_offset(i, 
mmSDMA0_PHASE1_QUANTUM),
+   WREG32(sdma_v4_0_get_reg_offset(adev, i, 
mmSDMA0_PHASE1_QUANTUM),
   phase_quantum);

Re: [PATCH 3/5] drm/amdgpu: Avoid to use SOC15_REG_OFFSET in static const array

[Christian König]

static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
.type = AMDGPU_RING_TYPE_UVD,
.align_mask = 0xf,
.nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),

That one is trivial. There is an .insert_nop callback a bit further down:

.insert_nop = amdgpu_ring_insert_nop,


When you override this the .nop member isn't used any more. See 
amdgpu_ring_insert_nop() as well.



How to change the SOC15_REG_OFFSET used in the following  case :
const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ),
.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, 
mmGPU_HDP_FLUSH_DONE),
...

That one looks more tricky, but probably doable as well.

And taking a look at how this is used in gfx_v9_0_ring_emit_hdp_flush() 
for example:

    if (ring->adev->flags & AMD_IS_APU)
    nbio_hf_reg = _v7_0_hdp_flush_reg;
    else
    nbio_hf_reg = _v6_1_hdp_flush_reg;

...

That looks like a good candidate for a cleanup anyway.

Probably best approach is to put some hdp_funcs into adev. This can then 
be used to cleanup similar code in the gmc_v9_0.c as well:

    /* After HDP is initialized, flush HDP.*/
    if (adev->flags & AMD_IS_APU)
    nbio_v7_0_hdp_flush(adev);
    else
    nbio_v6_1_hdp_flush(adev);


Thanks for taking care of this,
Christian.

Am 30.11.2017 um 22:17 schrieb Liu, Shaoyun:

Ok ,  I  think can make the change . It involved logic change , please 
carefully review it .

How to change the SOC15_REG_OFFSET used in the following  case :
const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
.hdp_flush_req_offset = SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ),
.hdp_flush_done_offset = SOC15_REG_OFFSET(NBIO, 0, 
mmGPU_HDP_FLUSH_DONE),
...


and similar :
static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
.type = AMDGPU_RING_TYPE_UVD,
.align_mask = 0xf,
.nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),
...

Can we avoid use fixed  IP_BASE_INST*_SEG*  + mmReg  for them ?

Regards
Shaoyun.liu

-Original Message-
From: Koenig, Christian
Sent: Thursday, November 30, 2017 3:00 PM
To: Liu, Shaoyun; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/5] drm/amdgpu: Avoid to use SOC15_REG_OFFSET in static 
const array


Like static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[]

Actually those could be completely nuked instead.

We added those because we feared that the GDS registers similar to the VMID 
base registers aren't continuously for older hardware generations.

But somebody just copy & pasted the code from gfx8 over to gfx9 and here it 
doesn't make to much sense any more.

Please just remove those arrays and replace them with register offsets directly 
in the code.

E.g. instead of amdgpu_gds_reg_offset[vmid].mem_base use SOC15_REG_OFFSET(GC, 
0, mmGDS_VMID0_BASE) + 2 * vmid. etc..

Thanks,
Christian.

Am 30.11.2017 um 19:58 schrieb Liu, Shaoyun:

I think what you are talking is the  golden setting registers as such as   
golden_settings_gc_9_0[]   etc .  I can change them as suggested (Use  
SOC15_REG_GOLDEN_VALUE  and define a structure for the golden register values).

There are some places that requires directly use the register offset  in the 
constant array .  Like
   static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[]
The structure amdgpu_gds_reg_offset require driver directly put the offset in 
the array .  It will introduce a lot other un-clean and unnecessary  changes  
if we change the structure . For this kind of case , I would rather add the 
fixed base  + reg offset as  mentioned before :#define  
VG10_GC_BASE0_OFFSET(reg)  (0x2000 + reg) ,  since all of these GDS register  
are based on same  GC_BASE0.

Regards
Shaoyun.liu

-Original Message-
From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
Sent: Thursday, November 30, 2017 3:42 AM
To: Liu, Shaoyun; Koenig, Christian; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/5] drm/amdgpu: Avoid to use SOC15_REG_OFFSET in
static const array

I would rather go with something like this:

#define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, value, mask) {
ip##_HWIP, inst, reg##_BASE_IDX, reg, value, mask }

And please define a structure for the golden register values instead of just 
using an u32 array.

Regards,
Christian.

Am 29.11.2017 um 21:52 schrieb Liu, Shaoyun:

There are other place of the golden register setting where I already replace 
the SOC15_REG_OFFSET with SOC15_REG_ENTRY.   All these GDS register offset are 
based on GC_BASE0 (0x2000) so how about I use following defines

#define  VG10_GC_BASE0_OFFSET(reg)  (0x2000 + reg)

And use it to replace the SOC15_REG_OFFSET used in
amdgpu_gds_reg_offset[]

Regards
Shaoyun.liu

-Original Message-
From: Christian König [mailto:ckoenig.leichtzumer...@gmail.com]
Sent: