答复: [PATCH] drm/amdgpu/gmc7: simplify logic in firmware message

[Qu, Jim]

Reviewed-by: Jim Qu 

Thanks
JimQu


发件人: amd-gfx  代表 Alex Deucher 

发送时间: 2018年7月6日 4:46:33
收件人: amd-gfx@lists.freedesktop.org
抄送: Deucher, Alexander
主题: [PATCH] drm/amdgpu/gmc7: simplify logic in firmware message

Switching the firmware paths for CIK parts resulted
in no need for this anymore.

Fixes: "drm/amdgpu: switch firmware path for CIK parts"
Noticed-by: Julia Lawall 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 2c2b93d4d63b..78339309a00c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -147,10 +147,7 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device 
*adev)
default: BUG();
}

-   if (adev->asic_type == CHIP_TOPAZ)
-   snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", 
chip_name);
-   else
-   snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", 
chip_name);
+   snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);

err = request_firmware(>gmc.fw, fw_name, adev->dev);
if (err)
--
2.13.6

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答复: [PATCH v3 2/2] drm/admgpu: Present amdgpu_task_info in VM_FAULTS.

[Qu, Jim]

Look good to me. there is a small typo error about title admgpu->amdgpu

Acked-by: Jim Qu 

Thanks
JimQu


发件人: amd-gfx  代表 Andrey Grodzovsky 

发送时间: 2018年7月6日 3:27:00
收件人: amd-gfx@lists.freedesktop.org
抄送: Grodzovsky, Andrey; Zhou, David(ChunMing); Koenig, Christian
主题: [PATCH v3 2/2] drm/admgpu: Present amdgpu_task_info in VM_FAULTS.

Extract and present the reposnsible process and thread when
VM_FAULT happens.

v2: Use getter and setter functions.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |  4 
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  | 10 +++---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |  9 +++--
 3 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 7a625f3..609c8f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -187,6 +187,10 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser 
*p, void *data)
if (p->uf_entry.robj)
p->job->uf_addr = uf_offset;
kfree(chunk_array);
+
+   /* Use this opportunity to fill in task info for the vm */
+   amdgpu_vm_set_task_info(vm);
+
return 0;

 free_all_kdata:
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 08753e7..75f3ffb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -46,7 +46,6 @@

 #include "ivsrcid/ivsrcid_vislands30.h"

-
 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 static int gmc_v8_0_wait_for_idle(void *handle);
@@ -1449,8 +1448,13 @@ static int gmc_v8_0_process_interrupt(struct 
amdgpu_device *adev,
gmc_v8_0_set_fault_enable_default(adev, false);

if (printk_ratelimit()) {
-   dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
-   entry->src_id, entry->src_data[0]);
+   struct amdgpu_task_info task_info = { 0 };
+
+   amdgpu_vm_get_task_info(adev, entry->pasid, _info);
+
+   dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process 
%s pid %d thread %s pid %d\n",
+   entry->src_id, entry->src_data[0], 
task_info.process_name,
+   task_info.tgid, task_info.task_name, task_info.pid);
dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   
0x%08X\n",
addr);
dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 
0x%08X\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 691a659..9df94b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -259,11 +259,16 @@ static int gmc_v9_0_process_interrupt(struct 
amdgpu_device *adev,
}

if (printk_ratelimit()) {
+   struct amdgpu_task_info task_info = { 0 };
+
+   amdgpu_vm_get_task_info(adev, entry->pasid, _info);
+
dev_err(adev->dev,
-   "[%s] VMC page fault (src_id:%u ring:%u vmid:%u 
pasid:%u)\n",
+   "[%s] VMC page fault (src_id:%u ring:%u vmid:%u 
pasid:%u, for process %s pid %d thread %s pid %d\n)\n",
entry->vmid_src ? "mmhub" : "gfxhub",
entry->src_id, entry->ring_id, entry->vmid,
-   entry->pasid);
+   entry->pasid, task_info.process_name, task_info.tgid,
+   task_info.task_name, task_info.pid);
dev_err(adev->dev, "  at page 0x%016llx from %d\n",
addr, entry->client_id);
if (!amdgpu_sriov_vf(adev))
--
2.7.4

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[pull] amdgpu, radeon, scheduler drm-next-4.19

[Alex Deucher]

Hi Dave,

More features for 4.19:
- Use core pcie functionality rather than duplicating our own for pcie
  gens and lanes
- Scheduler function naming cleanups
- More documentation
- Reworked DC/Powerplay interfaces to improve power savings
- Initial stutter mode support for RV (power feature)
- Vega12 powerplay updates
- GFXOFF fixes
- Misc fixes

The following changes since commit f29135ee4e0d4e01911ed569f731bfdb841cea6d:

  Merge v4.18-rc3 into drm-next (2018-07-04 10:27:12 +1000)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-next-4.19

for you to fetch changes up to 43911fb68b19f7c37ab69eff8e6a3c1370bc0cb5:

  drm/amd: Add sphinx documentation for amd_ip_funcs (2018-07-05 16:57:54 -0500)


Alex Deucher (17):
  Revert "drm/amdgpu: avoid sleep while executing atombios table (V2)"
  drm/amdgpu: fix swapped emit_ib_size in vce3
  drm/amdgpu/pm: fix display count in non-DC path
  drm/amdgpu/pp: add missing byte swapping in process_pptables_v1_0.c
  drm/amdgpu/pp: fix endian swapping in atomctrl_get_voltage_range
  drm/amdgpu/pp: fix copy paste typo in smu7_init_dpm_defaults
  drm/amdgpu/pp: fix copy paste typo in 
smu7_get_pp_table_entry_callback_func_v1
  drm/amdgpu/sdma: simplify sdma instance setup
  drm/amdgpu/vce: simplify vce instance setup
  drm/amdgpu: update uvd_v6_0_ring_vm_funcs to use new nop packet
  drm/amdgpu: switch firmware path for CIK parts (v2)
  drm/amdgpu: switch firmware path for SI parts
  PCI: Export pcie_get_speed_cap and pcie_get_width_cap
  drm/amdgpu: update amd_pcie.h to include gen4 speeds
  drm/amdgpu: use pcie functions for link width and speed
  drm/radeon: use pcie functions for link width
  drm: drop drm_pcie_get_speed_cap_mask and drm_pcie_get_max_link_width

Andrey Grodzovsky (4):
  drm/amdgpu: Polish SQ IH.
  drm/amdgpu: Add parsing SQ_EDC_INFO to SQ IH v3.
  drm/scheduler: Rename cleanup functions v2.
  drm/amdgpu: Rename entity cleanup finctions.

Charlene Liu (2):
  drm/amd/display: Define dp_alt_mode
  drm/amd/display: add valid regoffset and NULL pointer check

Christian König (1):
  drm/amdgpu: band aid validating VM PTs

Dan Carpenter (1):
  drm/amd/display: off by one in find_irq_source_info()

Darren Powell (2):
  drm/amd: Remove errors from sphinx documentation
  drm/amd: Add sphinx documentation for amd_ip_funcs

David Francis (1):
  drm/amd/display: Add front end for dp debugfs files

Dirk Hohndel (VMware) (2):
  drm/amd: add SPDX identifier and clarify license
  drm/radeon: add SPDX identifier and clarify license

Dmytro Laktyushkin (23):
  drm/amd/display: replace clocks_value struct with dc_clocks
  drm/amd/display: redesign dce/dcn clock voltage update request
  drm/amd/display: rename display clock block to dccg
  drm/amd/display: move clock programming from set_bandwidth to dccg
  drm/amd/display: remove invalid assert when no max_pixel_clk is found
  drm/amd/display: get rid of cur_clks from dcn_bw_output
  drm/amd/display: move dcn1 dispclk programming to dccg
  drm/amd/display: clean up dccg divider calc and dcn constructor
  drm/amd/display: rename dce_disp_clk to dccg
  drm/amd/display: clean up set_bandwidth usage
  drm/amd/display: remove unnecessary pplib volage requests that are 
asserting
  drm/amd/display: fix dccg dcn1 ifdef
  drm/amd/display: fix pplib voltage request
  drm/amd/display: add CHG_DONE mash/sh defines for dentist
  drm/amd/display: change dentist DID enum values to uppercase
  drm/amd/display: add safe_to_lower support to dcn wm programming
  drm/amd/display: clean rq/dlg/ttu reg structs before calculations
  drm/amd/display: move dml defaults to respective dcn resource files
  drm/amd/display: fix dcn1 watermark range reporting
  drm/amd/display: remove dcn1 watermark sets b, c and d
  drm/amd/display: separate out wm change request dcn workaround
  drm/amd/display: move dcn watermark programming to set_bandwidth
  drm/amd/display: remove soc_bounding_box.c

Evan Quan (14):
  drm/amd/powerplay: correct vega12 bootup values settings
  drm/amd/powerplay: smc_dpm_info structure change
  drm/amd/powerplay: drop the acg fix
  drm/amd/powerplay: revise default dpm tables setup
  drm/amd/powerplay: retrieve all clock ranges on startup
  drm/amd/powerplay: revise clock level setup
  drm/amd/powerplay: initialize uvd/vce powergate status v4
  drm/amd/powerplay: correct smc display config for multi monitor
  drm/amd/powerplay: drop unnecessary uclk hard min setting
  drm/amd/powerplay: correct vega12 max num of dpm level
  drm/amd/powerplay: apply clocks adjust rules on power state change
  drm/amd/powerplay: set vega12 pre display configurations
  drm/amd/powerplay: 

[PATCH] drm/amdgpu/gmc7: simplify logic in firmware message

[Alex Deucher]

Switching the firmware paths for CIK parts resulted
in no need for this anymore.

Fixes: "drm/amdgpu: switch firmware path for CIK parts"
Noticed-by: Julia Lawall 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 2c2b93d4d63b..78339309a00c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -147,10 +147,7 @@ static int gmc_v7_0_init_microcode(struct amdgpu_device 
*adev)
default: BUG();
}
 
-   if (adev->asic_type == CHIP_TOPAZ)
-   snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", 
chip_name);
-   else
-   snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", 
chip_name);
+   snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mc.bin", chip_name);
 
err = request_firmware(>gmc.fw, fw_name, adev->dev);
if (err)
-- 
2.13.6

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Re: BUG: *ERROR* No EDID read

[Daniel Andersson]

[0.00] Command line: BOOT_IMAGE=/vmlinuz-linuxtest
root=UUID=27247597-a354-42f3-8040-caff9592a297 drm.debug=0x4 rw quiet
[0.00] Kernel command line: BOOT_IMAGE=/vmlinuz-linuxtest
root=UUID=27247597-a354-42f3-8040-caff9592a297 drm.debug=0x4 rw quiet
[5.674793] [drm:bios_parser_get_firmware_info [amdgpu]] At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.674833] [drm:bios_parser_get_firmware_info [amdgpu]] *ERROR* At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.674887] [drm:bios_parser_get_firmware_info [amdgpu]] At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.674930] [drm:bios_parser_get_firmware_info [amdgpu]] *ERROR* At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.674974] [drm:bios_parser_get_firmware_info [amdgpu]] At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.675014] [drm:bios_parser_get_firmware_info [amdgpu]] *ERROR* At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.675056] [drm:bios_parser_get_firmware_info [amdgpu]] At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.675095] [drm:bios_parser_get_firmware_info [amdgpu]] *ERROR* At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.675138] [drm:bios_parser_get_firmware_info [amdgpu]] At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.675178] [drm:bios_parser_get_firmware_info [amdgpu]] *ERROR* At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.675221] [drm:bios_parser_get_firmware_info [amdgpu]] At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.675260] [drm:bios_parser_get_firmware_info [amdgpu]] *ERROR* At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.675304] [drm:bios_parser_get_firmware_info [amdgpu]] At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.675342] [drm:bios_parser_get_firmware_info [amdgpu]] *ERROR* At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.675384] [drm:bios_parser_get_firmware_info [amdgpu]] At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.675422] [drm:bios_parser_get_firmware_info [amdgpu]] *ERROR* At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.675465] [drm:bios_parser_get_firmware_info [amdgpu]] At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.675503] [drm:bios_parser_get_firmware_info [amdgpu]] *ERROR* At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.675587] [drm:bios_parser_get_firmware_info [amdgpu]] At
bios_parser_get_firmware_info switch, got major 3 minor 1
[5.675626] [drm:bios_parser_get_firmware_info [amdgpu]] *ERROR* At
bios_parser_get_firmware_info switch, got major 3 minor 1

I don't really know what is going on. If I go back to 4.17 and apply
my "fix". It doesn't work. I suppose my bisect didn't get me the right
commit. I probably never tested that the commit, from the bisect, was
actually bad. I was also a little lazy and did "bisect start
29dcea88779c856c7dc92040a0c01233263101d4
6da6c0db5316275015e8cc2959f12a17584aeb64 -- drivers/gpu/drm/amd".

I guess I'll try another bisect tomorrow on the entire tree, sorry for
the extra work.

// Daniel

On 5 July 2018 at 20:22, Harry Wentland  wrote:
> On 2018-07-05 01:43 PM, Daniel Andersson wrote:
>> Well, this workaround:
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
>> b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
>> index 10a5807a7e8b..d0f5910c906c 100644
>> --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
>> +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
>> @@ -1321,6 +1321,8 @@ static enum bp_result bios_parser_get_firmware_info(
>>   header = GET_IMAGE(struct atom_common_table_header,
>>   DATA_TABLES(firmwareinfo));
>>   get_atom_data_table_revision(header, );
>> +dm_output_to_console("At bios_parser_get_firmware_info switch,
>> got major %d minor %d", revision.major, revision.minor);
>> +dm_error("At bios_parser_get_firmware_info switch, got major %d
>> minor %d", revision.major, revision.minor);
>>   switch (revision.major) {
>>   case 3:
>>   switch (revision.minor) {
>> @@ -1328,7 +1330,7 @@ static enum bp_result bios_parser_get_firmware_info(
>>   result = get_firmware_info_v3_1(bp, info);
>>   break;
>>   case 2:
>> - result = get_firmware_info_v3_2(bp, info);
>> + result = get_firmware_info_v3_1(bp, info);
>>   break;
>>   default:
>>   break;
>>
>> "works":
>> [engy][~/devel/3pp/linux] ((6e65fb862064...)|BISECTING)$ xrandr
>> Screen 0: minimum 320 x 200, current 2560 x 1440, maximum 16384 x 16384
>> DisplayPort-0 connected 2560x1440+0+0 (normal left inverted right x
>> axis y axis) 598mm x 336mm
>>2560x1440 59.95*+ 120.0099.9584.9823.97
>>1920x1200 59.95
>>1920x1080 59.95
>>1600x1200 59.95
>>1680x1050 59.95
>>1280x1024 59.95
>>1440x900  59.95
>>1280x800  59.95
>>1280x720   

[PATCH v3 2/2] drm/admgpu: Present amdgpu_task_info in VM_FAULTS.

[Andrey Grodzovsky]

Extract and present the reposnsible process and thread when
VM_FAULT happens.

v2: Use getter and setter functions.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |  4 
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c  | 10 +++---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  |  9 +++--
 3 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 7a625f3..609c8f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -187,6 +187,10 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser 
*p, void *data)
if (p->uf_entry.robj)
p->job->uf_addr = uf_offset;
kfree(chunk_array);
+
+   /* Use this opportunity to fill in task info for the vm */
+   amdgpu_vm_set_task_info(vm);
+
return 0;
 
 free_all_kdata:
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 08753e7..75f3ffb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -46,7 +46,6 @@
 
 #include "ivsrcid/ivsrcid_vislands30.h"
 
-
 static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev);
 static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 static int gmc_v8_0_wait_for_idle(void *handle);
@@ -1449,8 +1448,13 @@ static int gmc_v8_0_process_interrupt(struct 
amdgpu_device *adev,
gmc_v8_0_set_fault_enable_default(adev, false);
 
if (printk_ratelimit()) {
-   dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
-   entry->src_id, entry->src_data[0]);
+   struct amdgpu_task_info task_info = { 0 };
+
+   amdgpu_vm_get_task_info(adev, entry->pasid, _info);
+
+   dev_err(adev->dev, "GPU fault detected: %d 0x%08x for process 
%s pid %d thread %s pid %d\n",
+   entry->src_id, entry->src_data[0], 
task_info.process_name,
+   task_info.tgid, task_info.task_name, task_info.pid);
dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   
0x%08X\n",
addr);
dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 
0x%08X\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 691a659..9df94b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -259,11 +259,16 @@ static int gmc_v9_0_process_interrupt(struct 
amdgpu_device *adev,
}
 
if (printk_ratelimit()) {
+   struct amdgpu_task_info task_info = { 0 };
+
+   amdgpu_vm_get_task_info(adev, entry->pasid, _info);
+
dev_err(adev->dev,
-   "[%s] VMC page fault (src_id:%u ring:%u vmid:%u 
pasid:%u)\n",
+   "[%s] VMC page fault (src_id:%u ring:%u vmid:%u 
pasid:%u, for process %s pid %d thread %s pid %d\n)\n",
entry->vmid_src ? "mmhub" : "gfxhub",
entry->src_id, entry->ring_id, entry->vmid,
-   entry->pasid);
+   entry->pasid, task_info.process_name, task_info.tgid,
+   task_info.task_name, task_info.pid);
dev_err(adev->dev, "  at page 0x%016llx from %d\n",
addr, entry->client_id);
if (!amdgpu_sriov_vf(adev))
-- 
2.7.4

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[PATCH v3 1/2] drm/amdgpu: Add support for logging process info in amdgpu_vm.

[Andrey Grodzovsky]

Add process and thread names and pids and a function to extract
this info from relevant amdgpu_vm.

v2: Add documentation and fix identation.

v3: Add getter and setter functions for amdgpu_task_info.

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 39 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 16 ++
 2 files changed, 55 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 712af5c..d18f247 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2942,3 +2942,42 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
 
return 0;
 }
+
+/**
+ * amdgpu_vm_get_task_info - Extracts task info for a PASID.
+ *
+ * @dev: drm device pointer
+ * @pasid: PASID identifier for VM
+ * @task_info: task_info to fill.
+ */
+void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
+struct amdgpu_task_info *task_info)
+{
+   struct amdgpu_vm *vm;
+
+   spin_lock(>vm_manager.pasid_lock);
+
+   vm = idr_find(>vm_manager.pasid_idr, pasid);
+   if (vm)
+   *task_info = vm->task_info;
+
+   spin_unlock(>vm_manager.pasid_lock);
+}
+
+/**
+ * amdgpu_vm_set_task_info - Sets VMs task info.
+ *
+ * @vm: vm for which to set the info
+ */
+void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
+{
+   if (!vm->task_info.pid) {
+   vm->task_info.pid = current->pid;
+   get_task_comm(vm->task_info.task_name, current);
+
+   if (current->group_leader->mm == current->mm) {
+   vm->task_info.tgid = current->group_leader->pid;
+   get_task_comm(vm->task_info.process_name, 
current->group_leader);
+   }
+   }
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 061b99a..d416f89 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -164,6 +164,14 @@ struct amdgpu_vm_pt {
 #define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
 #define AMDGPU_VM_FAULT_ADDR(fault)  ((u64)(fault) & 0xf000ULL)
 
+
+struct amdgpu_task_info {
+   charprocess_name[TASK_COMM_LEN];
+   chartask_name[TASK_COMM_LEN];
+   pid_t   pid;
+   pid_t   tgid;
+};
+
 struct amdgpu_vm {
/* tree of virtual addresses mapped */
struct rb_root_cached   va;
@@ -215,6 +223,9 @@ struct amdgpu_vm {
 
/* Valid while the PD is reserved or fenced */
uint64_tpd_phys_addr;
+
+   /* Some basic info about the task */
+   struct amdgpu_task_info task_info;
 };
 
 struct amdgpu_vm_manager {
@@ -317,4 +328,9 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
  struct amdgpu_job *job);
 void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
 
+void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
+struct amdgpu_task_info *task_info);
+
+void amdgpu_vm_set_task_info(struct amdgpu_vm *vm);
+
 #endif
-- 
2.7.4

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Re: Raven Ridge Ryzen 2500U hang reproduced

[Bráulio Bhavamitra]

Suspend/resume are working fine now.

There is big chance idle=nomwait fixed all hangs (from
https://community.amd.com/thread/224000). Couldn't reproduce a hang since
using it.

CPU max. frequency is limited to 2000mhz, by firmware or linux 4.17, maybe
due to overheating? It goes beyond 3hz on windows.

Best regards,
Bráulio

On Mon, Mar 26, 2018 at 8:30 PM Bráulio Bhavamitra 
wrote:

> Hi all,
>
> Following the random crashes happenning with many users (e.g.
> https://www.phoronix.com/scan.php?page=news_item=Raven-Ridge-March-Update),
> not only on Linux but also Windows, I've been struggling to reproduce and
> generate any error log.
>
> After discovering that the error only happenned with KDE and games (at
> least for me, see https://bugs.kde.org/show_bug.cgi?id=392378), I could
> reproduce after a failing suspend.
>
> The crash most of the times allows the mouse to keep moving, but anything
> else works. Except for this time the keyboard worked so I could switch the
> tty and save the dmesg messages. After this I had to force reboot as it got
> stuck trying to kill the lightdm service (gpu hanged?).
>
> The errors are, see attached the full dmesg:
> [ 2899.525650] amdgpu :03:00.0: couldn't schedule ib on ring 
> [ 2899.525769] [drm:amdgpu_job_run [amdgpu]] *ERROR* Error scheduling IBs
> (-22)
> [ 2909.125047] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx
> timeout, last signaled seq=174624, last emitted seq=174627
> [ 2909.125060] [drm] IP block:psp is hung!
> [ 2909.125063] [drm] GPU recovery disabled.
> [ 2914.756931] [drm:amdgpu_cs_ioctl [amdgpu]] *ERROR*
> amdgpu_cs_list_validate(validated) failed.
> [ 2914.756997] [drm:amdgpu_cs_ioctl [amdgpu]] *ERROR* Failed to process
> the buffer list -16!
> [ 2914.997372] amdgpu :03:00.0: couldn't schedule ib on ring 
> [ 2914.997498] [drm:amdgpu_job_run [amdgpu]] *ERROR* Error scheduling IBs
> (-22)
> [ 2930.117275] [drm:amdgpu_cs_ioctl [amdgpu]] *ERROR*
> amdgpu_cs_list_validate(validated) failed.
> [ 2930.117405] [drm:amdgpu_cs_ioctl [amdgpu]] *ERROR* Failed to process
> the buffer list -16!
> [ 2930.152015] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear
> memory with ring turned off.
> [ 2930.157940] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear
> memory with ring turned off.
> [ 2930.180535] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear
> memory with ring turned off.
> [ 2933.781692] IPv6: ADDRCONF(NETDEV_CHANGE): wlp2s0: link becomes ready
> [ 2945.477205] [drm:amdgpu_cs_ioctl [amdgpu]] *ERROR*
> amdgpu_cs_list_validate(validated) failed.
> [ 2945.477348] [drm:amdgpu_cs_ioctl [amdgpu]] *ERROR* Failed to process
> the buffer list -16!
>
> System details:
> HP Envy x360 Ryzen 2500U
> ArchLinux, kernel 4.16rc6 and 4.15.12
>
> Cheers,
> bráulio
>
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[PATCH v2] drm/amdgpu: Verify root PD is mapped into kernel address space.

[Andrey Grodzovsky]

Problem: When PD/PT update made by CPU root PD was not yet mapped causing
page fault.

Fix: Verify root PD is mapped into CPU address space.

v2:
Make sure that we add the root PD to the relocated list
since then it's get mapped into CPU address space bt default
in amdgpu_vm_update_directories.

Link: https://bugs.freedesktop.org/show_bug.cgi?id=107065
Signed-off-by: Andrey Grodzovsky 

Signed-off-by: Andrey Grodzovsky 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 845f73a..1a8caf1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -156,6 +156,9 @@ static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base 
*base,
return;
list_add_tail(>bo_list, >va);
 
+   if (bo->tbo.type == ttm_bo_type_kernel)
+   list_move(>vm_status, >relocated);
+
if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
return;
 
@@ -168,7 +171,8 @@ static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base 
*base,
 * is currently evicted. add the bo to the evicted list to make sure it
 * is validated on next vm use to avoid fault.
 * */
-   list_move_tail(>vm_status, >evicted);
+   if (bo->tbo.type != ttm_bo_type_kernel)
+   list_move_tail(>vm_status, >evicted);
 }
 
 /**
-- 
2.7.4

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[PATCH v5] drm/amdgpu: update documentation for amdgpu_drv.c

[Sonny Jiang]

Signed-off-by: Sonny Jiang 
Acked-by: Junwei Zhang 
Acked-by: Christian König 
---
 Documentation/gpu/amdgpu.rst|   7 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 230 +++-
 2 files changed, 230 insertions(+), 7 deletions(-)

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 765c2a3..a740e49 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -5,6 +5,13 @@
 The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics Core
 Next (GCN) architecture.
 
+Module Parameters
+=
+
+The amdgpu driver supports the following module parameters:
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+
 Core Driver Infrastructure
 ==
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 963578c..aa73040 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1,10 +1,3 @@
-/**
- * \file amdgpu_drv.c
- * AMD Amdgpu driver
- *
- * \author Gareth Hughes 
- */
-
 /*
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All Rights Reserved.
@@ -136,102 +129,239 @@ int amdgpu_gpu_recovery = -1; /* auto */
 int amdgpu_emu_mode = 0;
 uint amdgpu_smu_memory_pool_size = 0;
 
+/**
+ * DOC: vramlimit (int)
+ * Restrict the total amount of VRAM in MiB for testing.  The default is 0 
(Use full VRAM).
+ */
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
 
+/**
+ * DOC: vis_vramlimit (int)
+ * Restrict the amount of CPU visible VRAM in MiB for testing.  The default is 
0 (Use full CPU visible VRAM).
+ */
 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in 
megabytes");
 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
 
+/**
+ * DOC: gartsize (uint)
+ * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is 
-1 (The size depends on asic).
+ */
 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., 
-1=auto)");
 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
 
+/**
+ * DOC: gttsize (int)
+ * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's 
VRAM size if 3GB < VRAM < 3/4 RAM,
+ * otherwise 3/4 RAM size).
+ */
 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
 
+/**
+ * DOC: moverate (int)
+ * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
+ */
 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, 
etc., -1=auto, 0=1=disabled)");
 module_param_named(moverate, amdgpu_moverate, int, 0600);
 
+/**
+ * DOC: benchmark (int)
+ * Run benchmarks. The default is 0 (Skip benchmarks).
+ */
 MODULE_PARM_DESC(benchmark, "Run benchmark");
 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
 
+/**
+ * DOC: test (int)
+ * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, 
only set 1 to run test).
+ */
 MODULE_PARM_DESC(test, "Run tests");
 module_param_named(test, amdgpu_testing, int, 0444);
 
+/**
+ * DOC: audio (int)
+ * Set Audio. The default is -1 (Enabled), set 0 to disabled it.
+ */
 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
 module_param_named(audio, amdgpu_audio, int, 0444);
 
+/**
+ * DOC: disp_priority (int)
+ * Set display Priority (1 = normal, 2 = high). Only affects non-DC display 
handling. The default is 0 (auto).
+ */
 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = 
high)");
 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
 
+/**
+ * DOC: hw_i2c (int)
+ * To enable hw i2c engine. Only affects non-DC display handling. The default 
is 0 (Disabled).
+ */
 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
 
+/**
+ * DOC: pcie_gen2 (int)
+ * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 
(auto, enabled).
+ */
 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = 
enable)");
 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
 
+/**
+ * DOC: msi (int)
+ * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = 
disable). The default is -1 (auto, enabled).
+ */
 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
 module_param_named(msi, amdgpu_msi, int, 0444);
 
+/**
+ * DOC: lockup_timeout (int)
+ * Set GPU scheduler timeout value in ms. Value 0 is invalidated, will be 
adjusted to 1.
+ * Negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET). The default is 
1.
+ */
 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 
1)");
 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
 
+/**
+ * DOC: dpm (int)
+ * 

Re: BUG: *ERROR* No EDID read

[Harry Wentland]

On 2018-07-05 01:43 PM, Daniel Andersson wrote:
> Well, this workaround:
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
> b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
> index 10a5807a7e8b..d0f5910c906c 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
> @@ -1321,6 +1321,8 @@ static enum bp_result bios_parser_get_firmware_info(
>   header = GET_IMAGE(struct atom_common_table_header,
>   DATA_TABLES(firmwareinfo));
>   get_atom_data_table_revision(header, );
> +dm_output_to_console("At bios_parser_get_firmware_info switch,
> got major %d minor %d", revision.major, revision.minor);
> +dm_error("At bios_parser_get_firmware_info switch, got major %d
> minor %d", revision.major, revision.minor);
>   switch (revision.major) {
>   case 3:
>   switch (revision.minor) {
> @@ -1328,7 +1330,7 @@ static enum bp_result bios_parser_get_firmware_info(
>   result = get_firmware_info_v3_1(bp, info);
>   break;
>   case 2:
> - result = get_firmware_info_v3_2(bp, info);
> + result = get_firmware_info_v3_1(bp, info);
>   break;
>   default:
>   break;
> 
> "works":
> [engy][~/devel/3pp/linux] ((6e65fb862064...)|BISECTING)$ xrandr
> Screen 0: minimum 320 x 200, current 2560 x 1440, maximum 16384 x 16384
> DisplayPort-0 connected 2560x1440+0+0 (normal left inverted right x
> axis y axis) 598mm x 336mm
>2560x1440 59.95*+ 120.0099.9584.9823.97
>1920x1200 59.95
>1920x1080 59.95
>1600x1200 59.95
>1680x1050 59.95
>1280x1024 59.95
>1440x900  59.95
>1280x800  59.95
>1280x720  59.95
>1024x768  59.95
>800x600   59.95
>640x480   59.95
> DisplayPort-1 disconnected (normal left inverted right x axis y axis)
> HDMI-A-0 disconnected (normal left inverted right x axis y axis)
> HDMI-A-1 disconnected (normal left inverted right x axis y axis)
> 
> Where does dm_error and dm_output_to_console end up?
> 

dm_error -> DRM_ERROR will end up in dmesg as an error message
dm_output_to_console -> DRM_DEBUG_KMS will end up in dmesg as a normal log 
message if drm.debug=0x4 is set on the kernel command line

I'd be curious what the driver thinks the major and minor are.

Harry

> // Daniel
> 
> On 5 July 2018 at 18:42, Deucher, Alexander  wrote:
>> So your vbios has table v3.1 so it should not be affected by that patch.
>> Does reverting that patch actually fix the issue?
>>
>>
>> Alex
>>
>> 
>> From: amd-gfx  on behalf of Daniel
>> Andersson 
>> Sent: Thursday, July 5, 2018 12:22:17 PM
>> To: Alex Deucher
>> Cc: amd-gfx@lists.freedesktop.org
>> Subject: Re: BUG: *ERROR* No EDID read
>>
>> I have not flashed any GPU BIOS. It's not a reference Vega though,
>> Sapphire something. Maybe they made changes?
>>
>> vbios is attached.
>>
>> // Daniel
>>
>> On 5 July 2018 at 15:38, Alex Deucher  wrote:
>>> On Mon, Jul 2, 2018 at 5:39 PM, Daniel Andersson 
>>> wrote:
 Sure, bisecting gets me 6e65fb862064663ad3a08f964af1e8f3f2abf688 .

 In drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c,
 get_firmware_info_v3_1() works but get_firmware_info_v3_2() does not
 do the right thing for my Vega.

 Could I break my GPU if I were to set some bad/wrong frequency there?
>>>
>>> vega10 should not hit that new path at all.  Have you edited your
>>> vbios?  Can you send us a copy?  To get a copy of the vbios:
>>>
>>> Without the driver loaded:
>>> (as root)
>>> (use lspci to get the bus id)
>>> cd /sys/bus/pci/devices/
>>> echo 1 > rom
>>> cat rom > /tmp/vbios.rom
>>> echo 0 > rom
>>>
>>> If the driver is loaded:
>>> (as root)
>>> cat /sys/kernel/debug/dri/0/amdgpu_vbios > /tmp/vbios.rom
>>>
>>> Alex
>>>

 lspci:
 43:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
 [AMD/ATI] Vega 10 XT [Radeon RX Vega 64] (rev c1) (prog-if 00 [VGA
 controller])
   Subsystem: Sapphire Technology Limited Vega 10 XT [Radeon RX Vega
 64]
   Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
 Stepping- SERR- FastB2B- DisINTx+
   Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
 SERR- >>>   Latency: 0, Cache Line Size: 64 bytes
   Interrupt: pin A routed to IRQ 85
   Region 0: Memory at d000 (64-bit, prefetchable) [size=256M]
   Region 2: Memory at e000 (64-bit, prefetchable) [size=2M]
   Region 4: I/O ports at f000 [size=256]
   Region 5: Memory at ed40 (32-bit, non-prefetchable) [size=512K]
   Expansion ROM at ed48 [disabled] [size=128K]
   Capabilities: [48] Vendor Specific Information: Len=08 
   Capabilities: [50] Power Management version 3
 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
 PME(D0-,D1+,D2+,D3hot+,D3cold+)
 Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
   Capabilities: [64] Express (v2) Legacy Endpoint, MSI 00
 DevCap: MaxPayload 256 

Re: BUG: *ERROR* No EDID read

[Daniel Andersson]

Well, this workaround:

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 10a5807a7e8b..d0f5910c906c 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -1321,6 +1321,8 @@ static enum bp_result bios_parser_get_firmware_info(
  header = GET_IMAGE(struct atom_common_table_header,
  DATA_TABLES(firmwareinfo));
  get_atom_data_table_revision(header, );
+dm_output_to_console("At bios_parser_get_firmware_info switch,
got major %d minor %d", revision.major, revision.minor);
+dm_error("At bios_parser_get_firmware_info switch, got major %d
minor %d", revision.major, revision.minor);
  switch (revision.major) {
  case 3:
  switch (revision.minor) {
@@ -1328,7 +1330,7 @@ static enum bp_result bios_parser_get_firmware_info(
  result = get_firmware_info_v3_1(bp, info);
  break;
  case 2:
- result = get_firmware_info_v3_2(bp, info);
+ result = get_firmware_info_v3_1(bp, info);
  break;
  default:
  break;

"works":
[engy][~/devel/3pp/linux] ((6e65fb862064...)|BISECTING)$ xrandr
Screen 0: minimum 320 x 200, current 2560 x 1440, maximum 16384 x 16384
DisplayPort-0 connected 2560x1440+0+0 (normal left inverted right x
axis y axis) 598mm x 336mm
   2560x1440 59.95*+ 120.0099.9584.9823.97
   1920x1200 59.95
   1920x1080 59.95
   1600x1200 59.95
   1680x1050 59.95
   1280x1024 59.95
   1440x900  59.95
   1280x800  59.95
   1280x720  59.95
   1024x768  59.95
   800x600   59.95
   640x480   59.95
DisplayPort-1 disconnected (normal left inverted right x axis y axis)
HDMI-A-0 disconnected (normal left inverted right x axis y axis)
HDMI-A-1 disconnected (normal left inverted right x axis y axis)

Where does dm_error and dm_output_to_console end up?

// Daniel

On 5 July 2018 at 18:42, Deucher, Alexander  wrote:
> So your vbios has table v3.1 so it should not be affected by that patch.
> Does reverting that patch actually fix the issue?
>
>
> Alex
>
> 
> From: amd-gfx  on behalf of Daniel
> Andersson 
> Sent: Thursday, July 5, 2018 12:22:17 PM
> To: Alex Deucher
> Cc: amd-gfx@lists.freedesktop.org
> Subject: Re: BUG: *ERROR* No EDID read
>
> I have not flashed any GPU BIOS. It's not a reference Vega though,
> Sapphire something. Maybe they made changes?
>
> vbios is attached.
>
> // Daniel
>
> On 5 July 2018 at 15:38, Alex Deucher  wrote:
>> On Mon, Jul 2, 2018 at 5:39 PM, Daniel Andersson 
>> wrote:
>>> Sure, bisecting gets me 6e65fb862064663ad3a08f964af1e8f3f2abf688 .
>>>
>>> In drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c,
>>> get_firmware_info_v3_1() works but get_firmware_info_v3_2() does not
>>> do the right thing for my Vega.
>>>
>>> Could I break my GPU if I were to set some bad/wrong frequency there?
>>
>> vega10 should not hit that new path at all.  Have you edited your
>> vbios?  Can you send us a copy?  To get a copy of the vbios:
>>
>> Without the driver loaded:
>> (as root)
>> (use lspci to get the bus id)
>> cd /sys/bus/pci/devices/
>> echo 1 > rom
>> cat rom > /tmp/vbios.rom
>> echo 0 > rom
>>
>> If the driver is loaded:
>> (as root)
>> cat /sys/kernel/debug/dri/0/amdgpu_vbios > /tmp/vbios.rom
>>
>> Alex
>>
>>>
>>> lspci:
>>> 43:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
>>> [AMD/ATI] Vega 10 XT [Radeon RX Vega 64] (rev c1) (prog-if 00 [VGA
>>> controller])
>>>   Subsystem: Sapphire Technology Limited Vega 10 XT [Radeon RX Vega
>>> 64]
>>>   Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
>>> Stepping- SERR- FastB2B- DisINTx+
>>>   Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
>>> SERR- >>   Latency: 0, Cache Line Size: 64 bytes
>>>   Interrupt: pin A routed to IRQ 85
>>>   Region 0: Memory at d000 (64-bit, prefetchable) [size=256M]
>>>   Region 2: Memory at e000 (64-bit, prefetchable) [size=2M]
>>>   Region 4: I/O ports at f000 [size=256]
>>>   Region 5: Memory at ed40 (32-bit, non-prefetchable) [size=512K]
>>>   Expansion ROM at ed48 [disabled] [size=128K]
>>>   Capabilities: [48] Vendor Specific Information: Len=08 
>>>   Capabilities: [50] Power Management version 3
>>> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
>>> PME(D0-,D1+,D2+,D3hot+,D3cold+)
>>> Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
>>>   Capabilities: [64] Express (v2) Legacy Endpoint, MSI 00
>>> DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1
>>> unlimited
>>>   ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
>>> DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
>>>   RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
>>>   MaxPayload 256 bytes, MaxReadReq 512 bytes
>>> DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr-
>>> TransPend-
>>> LnkCap: Port #0, Speed 8GT/s, Width x16, ASPM L0s L1, Exit Latency
>>> L0s <64ns, L1 <1us
>>>   ClockPM- 

Re: BUG: *ERROR* No EDID read

[Deucher, Alexander]

So your vbios has table v3.1 so it should not be affected by that patch.  Does 
reverting that patch actually fix the issue?


Alex


From: amd-gfx  on behalf of Daniel 
Andersson 
Sent: Thursday, July 5, 2018 12:22:17 PM
To: Alex Deucher
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: BUG: *ERROR* No EDID read

I have not flashed any GPU BIOS. It's not a reference Vega though,
Sapphire something. Maybe they made changes?

vbios is attached.

// Daniel

On 5 July 2018 at 15:38, Alex Deucher  wrote:
> On Mon, Jul 2, 2018 at 5:39 PM, Daniel Andersson  wrote:
>> Sure, bisecting gets me 6e65fb862064663ad3a08f964af1e8f3f2abf688 .
>>
>> In drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c,
>> get_firmware_info_v3_1() works but get_firmware_info_v3_2() does not
>> do the right thing for my Vega.
>>
>> Could I break my GPU if I were to set some bad/wrong frequency there?
>
> vega10 should not hit that new path at all.  Have you edited your
> vbios?  Can you send us a copy?  To get a copy of the vbios:
>
> Without the driver loaded:
> (as root)
> (use lspci to get the bus id)
> cd /sys/bus/pci/devices/
> echo 1 > rom
> cat rom > /tmp/vbios.rom
> echo 0 > rom
>
> If the driver is loaded:
> (as root)
> cat /sys/kernel/debug/dri/0/amdgpu_vbios > /tmp/vbios.rom
>
> Alex
>
>>
>> lspci:
>> 43:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
>> [AMD/ATI] Vega 10 XT [Radeon RX Vega 64] (rev c1) (prog-if 00 [VGA
>> controller])
>>   Subsystem: Sapphire Technology Limited Vega 10 XT [Radeon RX Vega
>> 64]
>>   Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
>> Stepping- SERR- FastB2B- DisINTx+
>>   Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
>> SERR- >   Latency: 0, Cache Line Size: 64 bytes
>>   Interrupt: pin A routed to IRQ 85
>>   Region 0: Memory at d000 (64-bit, prefetchable) [size=256M]
>>   Region 2: Memory at e000 (64-bit, prefetchable) [size=2M]
>>   Region 4: I/O ports at f000 [size=256]
>>   Region 5: Memory at ed40 (32-bit, non-prefetchable) [size=512K]
>>   Expansion ROM at ed48 [disabled] [size=128K]
>>   Capabilities: [48] Vendor Specific Information: Len=08 
>>   Capabilities: [50] Power Management version 3
>> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
>> PME(D0-,D1+,D2+,D3hot+,D3cold+)
>> Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
>>   Capabilities: [64] Express (v2) Legacy Endpoint, MSI 00
>> DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1
>> unlimited
>>   ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
>> DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
>>   RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
>>   MaxPayload 256 bytes, MaxReadReq 512 bytes
>> DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr-
>> TransPend-
>> LnkCap: Port #0, Speed 8GT/s, Width x16, ASPM L0s L1, Exit Latency
>> L0s <64ns, L1 <1us
>>   ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
>> LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- CommClk+
>>   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
>> LnkSta: Speed 8GT/s, Width x16, TrErr- Train- SlotClk+ DLActive-
>> BWMgmt- ABWMgmt-
>> DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+,
>> OBFF Not Supported
>>AtomicOpsCap: 32bit- 64bit- 128bitCAS-
>> DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF
>> Disabled
>>AtomicOpsCtl: ReqEn-
>> LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
>>Transmit Margin: Normal Operating Range,
>> EnterModifiedCompliance- ComplianceSOS-
>>Compliance De-emphasis: -6dB
>> LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+,
>> EqualizationPhase1+
>>EqualizationPhase2+, EqualizationPhase3+,
>> LinkEqualizationRequest-
>>   Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
>> Address: fee0  Data: 
>>   Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1
>> Len=010 
>>   Capabilities: [150 v2] Advanced Error Reporting
>> UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF-
>> MalfTLP- ECRC- UnsupReq- ACSViol-
>> UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF-
>> MalfTLP- ECRC- UnsupReq- ACSViol-
>> UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+
>> MalfTLP+ ECRC- UnsupReq- ACSViol-
>> CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
>> CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
>> AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn-
>> ECRCChkCap+ ECRCChkEn-
>>   MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
>> HeaderLog:    
>>   Capabilities: [200 v1] #15
>>   Capabilities: [270 v1] #19
>>   Capabilities: [2a0 v1] Access Control Services
>> ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd-
>> EgressCtrl- DirectTrans-
>> 

Re: [PATCH] drm/amdgpu/acp: Fix slab-out-of-bounds in mfd_add_device in acp_hw_init

[Alex Deucher]

On Wed, Jul 4, 2018 at 4:48 AM, Mukunda,Vijendar
 wrote:
>
>
> On Tuesday 03 July 2018 09:50 PM, Alex Deucher wrote:
>>
>> On Mon, Jul 2, 2018 at 5:48 PM, Daniel Kurtz  wrote:
>>>
>>> Hi Alex,
>>>
>>> On Sun, Apr 15, 2018 at 9:48 PM Agrawal, Akshu 
>>> wrote:




 On 4/13/2018 9:45 PM, Daniel Kurtz wrote:
>
> Commit 51f7415039d4 ("drm/amd/amdgpu: creating two I2S instances for
> stoney/cz") added support for the "BT_I2S" ACP i2s channel.  As part of
> this change, one additional acp resource was added, but the
> "num_resource"
> count was accidentally incremented by 2.
>
> This incorrect count eventually causes mfd_add_device() to try to
> access
> an invalid memory address (the location of non-existent resource 5.
>
> This fault was detected by running a KASAN enabled kernel, which
> produced
> the following splat at boot:
>
> [6.612987]
> ==
> [6.613509] BUG: KASAN: slab-out-of-bounds in
> mfd_add_device+0x4bc/0x7a7
> [6.613509] Read of size 8 at addr 880107d4dc58 by task
> swapper/0/1
> [6.613509]
> [6.613509] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.14.33 #349
> [6.613509] Hardware name: Google Grunt/Grunt, BIOS
> Google_Grunt.10543.0.2018_04_03_1812 04/02/2018
> [6.613509] Call Trace:
> [6.613509]  dump_stack+0x4d/0x63
> [6.613509]  print_address_description+0x80/0x2d6
> [6.613509]  ? mfd_add_device+0x4bc/0x7a7
> [6.613509]  kasan_report+0x255/0x295
> [6.613509]  mfd_add_device+0x4bc/0x7a7
> [6.613509]  ? kasan_kmalloc+0x99/0xa8
> [6.613509]  ? mfd_add_devices+0x58/0xe4
> [6.613509]  ? __kmalloc+0x154/0x178
> [6.613509]  mfd_add_devices+0xa5/0xe4
> [6.613509]  acp_hw_init+0x92e/0xc4a
> [6.613509]  amdgpu_device_init+0x1dfb/0x22a2
> [6.613509]  ? kmalloc_order+0x53/0x5d
> [6.613509]  ? kmalloc_order_trace+0x23/0xb3
> [6.613509]  amdgpu_driver_load_kms+0xce/0x267
> [6.613509]  drm_dev_register+0x169/0x2fb
> [6.613509]  amdgpu_pci_probe+0x217/0x242
> [6.613509]  pci_device_probe+0x101/0x18e
> [6.613509]  driver_probe_device+0x1dd/0x419
> [6.613509]  ? ___might_sleep+0x80/0x1b6
> [6.613509]  __driver_attach+0x9f/0xc9
> [6.613509]  ? driver_probe_device+0x419/0x419
> [6.613509]  bus_for_each_dev+0xbc/0xe1
> [6.613509]  bus_add_driver+0x189/0x2c0
> [6.613509]  driver_register+0x108/0x156
> [6.613509]  ? ttm_init+0x67/0x67
> [6.613509]  do_one_initcall+0xb2/0x161
> [6.613509]  kernel_init_freeable+0x25a/0x308
> [6.613509]  ? rest_init+0xcc/0xcc
> [6.613509]  kernel_init+0x11/0x10d
> [6.613509]  ? rest_init+0xcc/0xcc
> [6.613509]  ret_from_fork+0x22/0x40
> [6.613509]
> [6.613509] Allocated by task 1:
> [6.613509]  save_stack+0x46/0xce
> [6.613509]  kasan_kmalloc+0x99/0xa8
> [6.613509]  kmem_cache_alloc_trace+0x11a/0x13e
> [6.613509]  acp_hw_init+0x210/0xc4a
> [6.613509]  amdgpu_device_init+0x1dfb/0x22a2
> [6.613509]  amdgpu_driver_load_kms+0xce/0x267
> [6.613509]  drm_dev_register+0x169/0x2fb
> [6.613509]  amdgpu_pci_probe+0x217/0x242
> [6.613509]  pci_device_probe+0x101/0x18e
> [6.613509]  driver_probe_device+0x1dd/0x419
> [6.613509]  __driver_attach+0x9f/0xc9
> [6.613509]  bus_for_each_dev+0xbc/0xe1
> [6.613509]  bus_add_driver+0x189/0x2c0
> [6.613509]  driver_register+0x108/0x156
> [6.613509]  do_one_initcall+0xb2/0x161
> [6.613509]  kernel_init_freeable+0x25a/0x308
> [6.613509]  kernel_init+0x11/0x10d
> [6.613509]  ret_from_fork+0x22/0x40
> [6.613509]
> [6.613509] Freed by task 0:
> [6.613509] (stack is not available)
> [6.613509]
> [6.613509] The buggy address belongs to the object at
> 880107d4db08
> [6.613509]  which belongs to the cache kmalloc-512 of size 512
> [6.613509] The buggy address is located 336 bytes inside of
> [6.613509]  512-byte region [880107d4db08, 880107d4dd08)
> [6.613509] The buggy address belongs to the page:
> [6.613509] page:ea00041f5300 count:1 mapcount:0 mapping:
> (null) index:0x0 compound_mapcount: 0
> [6.613509] flags: 0x80008100(slab|head)
> [6.613509] raw: 80008100  
> 000100120012
> [6.613509] raw: ea0004208520 88010b001680 88010b002cc0
> 
> [6.613509] page dumped because: kasan: bad access detected
> [6.613509]
> [6.613509] Memory state around the buggy address:
> [6.613509]  880107d4db00: fc 00 00 00 

Re: BUG: *ERROR* No EDID read

[Daniel Andersson]

I have not flashed any GPU BIOS. It's not a reference Vega though,
Sapphire something. Maybe they made changes?

vbios is attached.

// Daniel

On 5 July 2018 at 15:38, Alex Deucher  wrote:
> On Mon, Jul 2, 2018 at 5:39 PM, Daniel Andersson  wrote:
>> Sure, bisecting gets me 6e65fb862064663ad3a08f964af1e8f3f2abf688 .
>>
>> In drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c,
>> get_firmware_info_v3_1() works but get_firmware_info_v3_2() does not
>> do the right thing for my Vega.
>>
>> Could I break my GPU if I were to set some bad/wrong frequency there?
>
> vega10 should not hit that new path at all.  Have you edited your
> vbios?  Can you send us a copy?  To get a copy of the vbios:
>
> Without the driver loaded:
> (as root)
> (use lspci to get the bus id)
> cd /sys/bus/pci/devices/
> echo 1 > rom
> cat rom > /tmp/vbios.rom
> echo 0 > rom
>
> If the driver is loaded:
> (as root)
> cat /sys/kernel/debug/dri/0/amdgpu_vbios > /tmp/vbios.rom
>
> Alex
>
>>
>> lspci:
>> 43:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
>> [AMD/ATI] Vega 10 XT [Radeon RX Vega 64] (rev c1) (prog-if 00 [VGA
>> controller])
>>   Subsystem: Sapphire Technology Limited Vega 10 XT [Radeon RX Vega
>> 64]
>>   Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
>> Stepping- SERR- FastB2B- DisINTx+
>>   Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
>> SERR- >   Latency: 0, Cache Line Size: 64 bytes
>>   Interrupt: pin A routed to IRQ 85
>>   Region 0: Memory at d000 (64-bit, prefetchable) [size=256M]
>>   Region 2: Memory at e000 (64-bit, prefetchable) [size=2M]
>>   Region 4: I/O ports at f000 [size=256]
>>   Region 5: Memory at ed40 (32-bit, non-prefetchable) [size=512K]
>>   Expansion ROM at ed48 [disabled] [size=128K]
>>   Capabilities: [48] Vendor Specific Information: Len=08 
>>   Capabilities: [50] Power Management version 3
>> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
>> PME(D0-,D1+,D2+,D3hot+,D3cold+)
>> Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
>>   Capabilities: [64] Express (v2) Legacy Endpoint, MSI 00
>> DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1
>> unlimited
>>   ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
>> DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
>>   RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
>>   MaxPayload 256 bytes, MaxReadReq 512 bytes
>> DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr-
>> TransPend-
>> LnkCap: Port #0, Speed 8GT/s, Width x16, ASPM L0s L1, Exit Latency
>> L0s <64ns, L1 <1us
>>   ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
>> LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- CommClk+
>>   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
>> LnkSta: Speed 8GT/s, Width x16, TrErr- Train- SlotClk+ DLActive-
>> BWMgmt- ABWMgmt-
>> DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+,
>> OBFF Not Supported
>>AtomicOpsCap: 32bit- 64bit- 128bitCAS-
>> DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF
>> Disabled
>>AtomicOpsCtl: ReqEn-
>> LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
>>Transmit Margin: Normal Operating Range,
>> EnterModifiedCompliance- ComplianceSOS-
>>Compliance De-emphasis: -6dB
>> LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+,
>> EqualizationPhase1+
>>EqualizationPhase2+, EqualizationPhase3+,
>> LinkEqualizationRequest-
>>   Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
>> Address: fee0  Data: 
>>   Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1
>> Len=010 
>>   Capabilities: [150 v2] Advanced Error Reporting
>> UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF-
>> MalfTLP- ECRC- UnsupReq- ACSViol-
>> UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF-
>> MalfTLP- ECRC- UnsupReq- ACSViol-
>> UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+
>> MalfTLP+ ECRC- UnsupReq- ACSViol-
>> CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
>> CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
>> AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn-
>> ECRCChkCap+ ECRCChkEn-
>>   MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
>> HeaderLog:    
>>   Capabilities: [200 v1] #15
>>   Capabilities: [270 v1] #19
>>   Capabilities: [2a0 v1] Access Control Services
>> ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd-
>> EgressCtrl- DirectTrans-
>> ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd-
>> EgressCtrl- DirectTrans-
>>   Capabilities: [2b0 v1] Address Translation Service (ATS)
>> ATSCap: Invalidate Queue Depth: 00
>> ATSCtl: Enable+, Smallest Translation Unit: 00
>>   Capabilities: [2c0 v1] Page Request Interface (PRI)
>> PRICtl: Enable- Reset-
>> 

Re: [PATCH] drm/amd/display: Use 2-factor allocator calls

[Kees Cook]

On Thu, Jul 5, 2018 at 6:37 AM, Michel Dänzer  wrote:
> On 2018-07-04 07:27 PM, Kees Cook wrote:
>> As already done treewide, switch from open-coded multiplication to
>> 2-factor allocation helper.
>>
>> Signed-off-by: Kees Cook 
>> ---
>>  drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 8 
>>  1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 
>> b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
>> index 98edaefa2b47..ee69c949bfbf 100644
>> --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
>> +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
>> @@ -1723,8 +1723,8 @@ bool  mod_color_calculate_curve(enum 
>> dc_transfer_func_predefined trans,
>>   kvfree(rgb_regamma);
>>   } else if (trans == TRANSFER_FUNCTION_HLG ||
>>   trans == TRANSFER_FUNCTION_HLG12) {
>> - rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
>> -(MAX_HW_POINTS + _EXTRA_POINTS),
>> + rgb_regamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
>> +sizeof(*rgb_regamma),
>>  GFP_KERNEL);
>>   if (!rgb_regamma)
>>   goto rgb_regamma_alloc_fail;
>> @@ -1802,8 +1802,8 @@ bool  mod_color_calculate_degamma_curve(enum 
>> dc_transfer_func_predefined trans,
>>   kvfree(rgb_degamma);
>>   } else if (trans == TRANSFER_FUNCTION_HLG ||
>>   trans == TRANSFER_FUNCTION_HLG12) {
>> - rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
>> -(MAX_HW_POINTS + _EXTRA_POINTS),
>> + rgb_degamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
>> +sizeof(*rgb_degamma),
>>  GFP_KERNEL);
>>   if (!rgb_degamma)
>>   goto rgb_degamma_alloc_fail;
>>
>
> Since the values are constant, kvcalloc incurs the overflow checking
> overhead for no gain.

The way the macros are designed, they'll get entirely optimized away
in that case:
http://lkml.kernel.org/r/cagxu5jlw9kmzrkzl_q7jdyyprnthf6bdvse_vjyzect3cen...@mail.gmail.com

Using this patch means if the code ever changes away from constants,
it'll still be safe. And static checkers won't yell about the
open-coded multiplication here. So it's only up-sides. :)

-Kees

-- 
Kees Cook
Pixel Security
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[pull] amdgpu drm-fixes-4.18

[Alex Deucher]

Hi Dave,

Fixes for 4.18.  Highlights:
- Fix an HDMI 2.0 4k@60 regression
- Hotplug fixes for PX/HG laptops
- Fixes for vbios changes in vega12
- Fix a race in the user fence code
- Fix a couple of misc typos

The following changes since commit 4de9f38bb2cce3a4821ffb8a83d6b08f6e37d905:

  drm/amd/display: release spinlock before committing updates to stream 
(2018-06-27 14:35:53 -0500)

are available in the git repository at:

  git://people.freedesktop.org/~agd5f/linux drm-fixes-4.18

for you to fetch changes up to 413ff0b942481c7ac2e800abbbac5af318a65e61:

  drm/amd/display: add a check for display depth validity (2018-07-05 10:19:53 
-0500)


Alex Deucher (2):
  drm/amdgpu: fix swapped emit_ib_size in vce3
  drm/amdgpu/pm: fix display count in non-DC path

Evan Quan (3):
  drm/amd/powerplay: correct vega12 thermal support as true
  drm/amd/powerplay: correct vega12 bootup values settings
  drm/amd/powerplay: smc_dpm_info structure change

Lyude Paul (3):
  drm/amdgpu: Make struct amdgpu_atif private to amdgpu_acpi.c
  drm/amdgpu: Add amdgpu_atpx_get_dhandle()
  drm/amdgpu: Dynamically probe for ATIF handle (v2)

Mikita Lipski (2):
  drm/amd/display: adding ycbcr420 pixel encoding for hdmi
  drm/amd/display: add a check for display depth validity

Nicolai Hähnle (1):
  drm/amdgpu: fix user fence write race condition

 drivers/gpu/drm/amd/amdgpu/amdgpu.h|  46 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c   | 131 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c   |   6 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c |  12 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c |   2 +-
 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c  |   4 +-
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |  49 +++-
 drivers/gpu/drm/amd/include/atomfirmware.h |   5 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c |  96 +--
 drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.h |   5 +
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c |   4 +
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.h |   3 +
 .../amd/powerplay/hwmgr/vega12_processpptables.c   |   2 +
 .../drm/amd/powerplay/inc/vega12/smu9_driver_if.h  |   5 +-
 14 files changed, 284 insertions(+), 86 deletions(-)
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Re: [PATCH] drm/amd/pp: Implement get_performance_level for legacy dgpu

[Alex Deucher]

On Thu, Jul 5, 2018 at 10:00 AM, Rex Zhu  wrote:
> display can get clock info through this function.
> implement this function for vega10 and old asics.
> from vega12, there is no power state management. so need other
> interface to notify display the clock info
>
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  |  2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 24 
> ++
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 24 
> ++
>  3 files changed, 49 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> index 53207e7..b05b153 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
> @@ -357,7 +357,7 @@ int phm_get_clock_info(struct pp_hwmgr *hwmgr, const 
> struct pp_hw_power_state *s
> PHM_PerformanceLevelDesignation designation)
>  {
> int result;
> -   PHM_PerformanceLevel performance_level;
> +   PHM_PerformanceLevel performance_level = {0};
>
> PHM_FUNC_CHECK(hwmgr);
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 077b799..8eaaa6b 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -5006,6 +5006,29 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr 
> *hwmgr, long *input, uint
> return 0;
>  }
>
> +static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct 
> pp_hw_power_state *state,
> +   PHM_PerformanceLevelDesignation designation, 
> uint32_t index,
> +   PHM_PerformanceLevel *level)
> +{
> +   const struct smu7_power_state *ps;
> +   struct smu7_hwmgr *data;
> +   uint32_t i;
> +
> +   if (level == NULL || hwmgr == NULL || state == NULL)
> +   return -EINVAL;
> +
> +   data = hwmgr->backend;
> +   ps = cast_const_phw_smu7_power_state(state);
> +
> +   i = index > ps->performance_level_count - 1 ?
> +   ps->performance_level_count - 1 : index;
> +
> +   level->coreClock = ps->performance_levels[i].engine_clock;
> +   level->memory_clock = ps->performance_levels[i].memory_clock;
> +
> +   return 0;
> +}
> +
>  static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
> .backend_init = _hwmgr_backend_init,
> .backend_fini = _hwmgr_backend_fini,
> @@ -5062,6 +5085,7 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr 
> *hwmgr, long *input, uint
> .set_power_limit = smu7_set_power_limit,
> .get_power_profile_mode = smu7_get_power_profile_mode,
> .set_power_profile_mode = smu7_set_power_profile_mode,
> +   .get_performance_level = smu7_get_performance_level,
>  };
>
>  uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index eb37316..5c03df4 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -4837,6 +4837,29 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr 
> *hwmgr,
> return 0;
>  }
>
> +static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct 
> pp_hw_power_state *state,
> +   PHM_PerformanceLevelDesignation designation, 
> uint32_t index,
> +   PHM_PerformanceLevel *level)
> +{
> +   const struct vega10_power_state *ps;
> +   struct vega10_hwmgr *data;
> +   uint32_t i;
> +
> +   if (level == NULL || hwmgr == NULL || state == NULL)
> +   return -EINVAL;
> +
> +   data = hwmgr->backend;
> +   ps = cast_const_phw_vega10_power_state(state);
> +
> +   i = index > ps->performance_level_count - 1 ?
> +   ps->performance_level_count - 1 : index;
> +
> +   level->coreClock = ps->performance_levels[i].gfx_clock;
> +   level->memory_clock = ps->performance_levels[i].mem_clock;
> +
> +   return 0;
> +}
> +
>  static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
> .backend_init = vega10_hwmgr_backend_init,
> .backend_fini = vega10_hwmgr_backend_fini,
> @@ -4896,6 +4919,7 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr 
> *hwmgr,
> .set_power_profile_mode = vega10_set_power_profile_mode,
> .set_power_limit = vega10_set_power_limit,
> .odn_edit_dpm_table = vega10_odn_edit_dpm_table,
> +   .get_performance_level = vega10_get_performance_level,
>  };
>
>  int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
> --
> 1.9.1
>
> ___
> amd-gfx 

Re: [PATCH] drm/amd/pp: Convert 10KHz to KHz as variable name

[Alex Deucher]

On Thu, Jul 5, 2018 at 9:59 AM, Rex Zhu  wrote:
> The default clock unit in powerplay is 10KHz.
>
> Signed-off-by: Rex Zhu 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 3 +--
>  2 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 5e771bc119..eb37316 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -3801,7 +3801,7 @@ static int 
> vega10_notify_smc_display_config_after_ps_adjustment(
>
> if (i < dpm_table->count) {
> clock_req.clock_type = amd_pp_dcef_clock;
> -   clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value;
> +   clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value 
> * 10;
> if (!vega10_display_clock_voltage_request(hwmgr, _req)) 
> {
> smum_send_msg_to_smc_with_parameter(
> hwmgr, 
> PPSMC_MSG_SetMinDeepSleepDcefclk,
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 5749287..ed17c56 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -1361,7 +1361,6 @@ int vega12_display_clock_voltage_request(struct 
> pp_hwmgr *hwmgr,
> if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
> switch (clk_type) {
> case amd_pp_dcef_clock:
> -   clk_freq = clock_req->clock_freq_in_khz / 100;
> clk_select = PPCLK_DCEFCLK;
> break;
> case amd_pp_disp_clock:
> @@ -1410,7 +1409,7 @@ static int 
> vega12_notify_smc_display_config_after_ps_adjustment(
>
> if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
> clock_req.clock_type = amd_pp_dcef_clock;
> -   clock_req.clock_freq_in_khz = min_clocks.dcefClock;
> +   clock_req.clock_freq_in_khz = min_clocks.dcefClock/10;
> if (!vega12_display_clock_voltage_request(hwmgr, _req)) 
> {
> if (data->smu_features[GNLD_DS_DCEFCLK].supported)
> PP_ASSERT_WITH_CODE(
> --
> 1.9.1
>
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Re: [PATCH 05/10] drm/amdgpu: drop mmRLC_PG_CNTL clear

[Alex Deucher]

On Thu, Jul 5, 2018 at 5:09 AM, Evan Quan  wrote:
> This may break gfxoff support since this register will
> be set by smc fw(for vega12, that's the case).
>

It took me a second to understand what you meant here.  Might be
worthwhile to clarify with something like:
SMU owns this register so the driver should not set it to avoid breaking gfxoff.

With that fixed up:
Reviewed-by: Alex Deucher 

Alex

> Change-Id: Id3108c63634a2f941289021bfbd78588c0f6c4d6
> Signed-off-by: Evan Quan 
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ---
>  1 file changed, 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 8d870d4f8414..3a75641a071d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2290,9 +2290,6 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device 
> *adev)
> /* disable CG */
> WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
>
> -   /* disable PG */
> -   WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
> -
> gfx_v9_0_rlc_reset(adev);
>
> gfx_v9_0_init_pg(adev);
> --
> 2.18.0
>
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Re: [PATCH 01/10] drm/amdgpu: pin the csb buffer on hw init

[Alex Deucher]

On Thu, Jul 5, 2018 at 11:25 AM, Huang Rui  wrote:
> On Thu, Jul 05, 2018 at 05:09:26PM +0800, Evan Quan wrote:
>> Without this pin, the csb buffer will be filled with inconsistent
>> data after S3 resume. And that will causes gfx hang on gfxoff
>> exit since this csb will be executed then.
>>
>> Change-Id: I1ae1f2eed096eaba5f601cf2a3e2650c8e583dc9
>> Signed-off-by: Evan Quan 
>
> It is nice to have the comments behind of csb_vram_pin function to explain
> why we need "pin" here during resume phase.
>
> Reviewed-by: Huang Rui 

Do the save restore buffers in gfx7 and 8 need a similar fix?

Alex

>
>> ---
>>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40 +++
>>  1 file changed, 40 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index ac46eabe3bcd..65cc30766658 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -943,6 +943,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
>>   dst_ptr = adev->gfx.rlc.cs_ptr;
>>   gfx_v9_0_get_csb_buffer(adev, dst_ptr);
>>   amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
>> + amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
>>   amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
>>   }
>>
>> @@ -971,6 +972,39 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
>>   return 0;
>>  }
>>
>> +static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
>> +{
>> + uint64_t gpu_addr;
>> + int r;
>> +
>> + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
>> + if (unlikely(r != 0))
>> + return r;
>> +
>> + r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
>> + AMDGPU_GEM_DOMAIN_VRAM, _addr);
>> + if (!r)
>> + adev->gfx.rlc.clear_state_gpu_addr = gpu_addr;
>> +
>> + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
>> +
>> + return r;
>> +}
>> +
>> +static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
>> +{
>> + int r;
>> +
>> + if (!adev->gfx.rlc.clear_state_obj)
>> + return;
>> +
>> + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
>> + if (likely(r == 0)) {
>> + amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
>> + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
>> + }
>> +}
>> +
>>  static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
>>  {
>>   amdgpu_bo_free_kernel(>gfx.mec.hpd_eop_obj, NULL, NULL);
>> @@ -3116,6 +3150,10 @@ static int gfx_v9_0_hw_init(void *handle)
>>
>>   gfx_v9_0_gpu_init(adev);
>>
>> + r = gfx_v9_0_csb_vram_pin(adev);
>> + if (r)
>> + return r;
>> +
>>   r = gfx_v9_0_rlc_resume(adev);
>>   if (r)
>>   return r;
>> @@ -3224,6 +3262,8 @@ static int gfx_v9_0_hw_fini(void *handle)
>>   gfx_v9_0_cp_enable(adev, false);
>>   gfx_v9_0_rlc_stop(adev);
>>
>> + gfx_v9_0_csb_vram_unpin(adev);
>> +
>>   return 0;
>>  }
>>
>> --
>> 2.18.0
>>
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Re: [PATCH 01/10] drm/amdgpu: pin the csb buffer on hw init

[Huang Rui]

On Thu, Jul 05, 2018 at 05:09:26PM +0800, Evan Quan wrote:
> Without this pin, the csb buffer will be filled with inconsistent
> data after S3 resume. And that will causes gfx hang on gfxoff
> exit since this csb will be executed then.
> 
> Change-Id: I1ae1f2eed096eaba5f601cf2a3e2650c8e583dc9
> Signed-off-by: Evan Quan 

It is nice to have the comments behind of csb_vram_pin function to explain
why we need "pin" here during resume phase.

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40 +++
>  1 file changed, 40 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index ac46eabe3bcd..65cc30766658 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -943,6 +943,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
>   dst_ptr = adev->gfx.rlc.cs_ptr;
>   gfx_v9_0_get_csb_buffer(adev, dst_ptr);
>   amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
> + amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
>   amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
>   }
>  
> @@ -971,6 +972,39 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
>   return 0;
>  }
>  
> +static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
> +{
> + uint64_t gpu_addr;
> + int r;
> +
> + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
> + if (unlikely(r != 0))
> + return r;
> +
> + r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
> + AMDGPU_GEM_DOMAIN_VRAM, _addr);
> + if (!r)
> + adev->gfx.rlc.clear_state_gpu_addr = gpu_addr;
> +
> + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> +
> + return r;
> +}
> +
> +static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
> +{
> + int r;
> +
> + if (!adev->gfx.rlc.clear_state_obj)
> + return;
> +
> + r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
> + if (likely(r == 0)) {
> + amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
> + amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
> + }
> +}
> +
>  static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
>  {
>   amdgpu_bo_free_kernel(>gfx.mec.hpd_eop_obj, NULL, NULL);
> @@ -3116,6 +3150,10 @@ static int gfx_v9_0_hw_init(void *handle)
>  
>   gfx_v9_0_gpu_init(adev);
>  
> + r = gfx_v9_0_csb_vram_pin(adev);
> + if (r)
> + return r;
> +
>   r = gfx_v9_0_rlc_resume(adev);
>   if (r)
>   return r;
> @@ -3224,6 +3262,8 @@ static int gfx_v9_0_hw_fini(void *handle)
>   gfx_v9_0_cp_enable(adev, false);
>   gfx_v9_0_rlc_stop(adev);
>  
> + gfx_v9_0_csb_vram_unpin(adev);
> +
>   return 0;
>  }
>  
> -- 
> 2.18.0
> 
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Re: [PATCH v4] drm/amdgpu: update documentation for amdgpu_drv.c

[Alex Deucher]

On Thu, Jul 5, 2018 at 10:45 AM, Sonny Jiang  wrote:
> Signed-off-by: Sonny Jiang 
> Acked-by: Junwei Zhang 
> Acked-by: Christian König 
> ---
>  Documentation/gpu/amdgpu.rst|   7 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 371 
> +++-
>  2 files changed, 371 insertions(+), 7 deletions(-)
>
> diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
> index 765c2a3..a740e49 100644
> --- a/Documentation/gpu/amdgpu.rst
> +++ b/Documentation/gpu/amdgpu.rst
> @@ -5,6 +5,13 @@
>  The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics Core
>  Next (GCN) architecture.
>
> +Module Parameters
> +=
> +
> +The amdgpu driver supports the following module parameters:
> +
> +.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +
>  Core Driver Infrastructure
>  ==
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 963578c..8dbdf98 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1,10 +1,3 @@
> -/**
> - * \file amdgpu_drv.c
> - * AMD Amdgpu driver
> - *
> - * \author Gareth Hughes 
> - */
> -
>  /*
>   * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
>   * All Rights Reserved.
> @@ -136,102 +129,300 @@ int amdgpu_gpu_recovery = -1; /* auto */
>  int amdgpu_emu_mode = 0;
>  uint amdgpu_smu_memory_pool_size = 0;
>
> +/**
> + * DOC: vramlimit (int)
> + * Restrict the total amount of VRAM in MiB for testing.  The default is 0 
> (Use full VRAM).
> + */
>  MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
>  module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
>
> +/**
> + * DOC: vis_vramlimit (int)
> + * Restrict the amount of CPU visible VRAM in MiB for testing.  The default 
> is 0 (Use full CPU visible VRAM).
> + */
>  MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in 
> megabytes");
>  module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
>
> +/**
> + * DOC: gartsize (uint)
> + * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default 
> is -1 (The size depends on asic).
> + */
>  MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, 
> etc., -1=auto)");
>  module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
>
> +/**
> + * DOC: gttsize (int)
> + * Restrict the size of GTT domain in MiB for testing. The default is -1 
> (It's VRAM size if 3GB < VRAM < 3/4 RAM,
> + * otherwise 3/4 RAM size).
> + */
>  MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
>  module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
>
> +/**
> + * DOC: moverate (int)
> + * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
> + */
>  MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, 
> etc., -1=auto, 0=1=disabled)");
>  module_param_named(moverate, amdgpu_moverate, int, 0600);
>
> +/**
> + * DOC: benchmark (int)
> + * Run benchmarks. The default is 0 (Skip benchmarks).
> + */
>  MODULE_PARM_DESC(benchmark, "Run benchmark");
>  module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
>
> +/**
> + * DOC: test (int)
> + * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, 
> only set 1 to run test).
> + */
>  MODULE_PARM_DESC(test, "Run tests");
>  module_param_named(test, amdgpu_testing, int, 0444);
>
> +/**
> + * DOC: audio (int)
> + * Set Audio. The default is -1 (Enabled), set 0 to disabled it.
> + */
>  MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
>  module_param_named(audio, amdgpu_audio, int, 0444);
>
> +/**
> + * DOC: disp_priority (int)
> + * Set display Priority (0 = auto, 1 = normal, 2 = high). The default is 0.
> + */

Only affects non-DC display handling.


>  MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = 
> high)");
>  module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
>
> +/**
> + * DOC: hw_i2c (int)
> + * To enable hw i2c engine. The default is 0 (Disabled).
> + */

Only affects non-DC display handling.

>  MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
>  module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
>
> +/**
> + * DOC: pcie_gen2 (int)
> + * To disable PCIE Gen2 mode (0 = disable, 1 = enable). The default is -1 
> (auto, enabled).
> + */

PCIE Gen2/3

>  MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = 
> enable)");
>  module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
>
> +/**
> + * DOC: msi (int)
> + * To disable MSI functionality (1 = enable, 0 = disable). The default is -1 
> (auto, enabled).
> + */

MSI = Message Signaled Interrupts


>  MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
>  module_param_named(msi, amdgpu_msi, int, 0444);
>
> +/**
> + * DOC: lockup_timeout (int)
> + * Set GPU scheduler timeout 

Re: [PATCH 09/10] drm/amd/powerplay: add vega12 SMU gfxoff support

[Huang Rui]

On Thu, Jul 05, 2018 at 05:09:34PM +0800, Evan Quan wrote:
> Export apis for enabling/disabling SMU gfxoff support.
> 
> Change-Id: Idcea1db9f3dbe15edda1b76e1ff05435865af2a1
> Signed-off-by: Evan Quan 

Reviewed-by: Huang Rui 

> ---
>  .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 19 +++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> index 57492878874f..8efa983c41de 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
> @@ -2329,6 +2329,24 @@ static int vega12_get_thermal_temperature_range(struct 
> pp_hwmgr *hwmgr,
>   return 0;
>  }
>  
> +static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
> +{
> + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff);
> +}
> +
> +static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr)
> +{
> + return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff);
> +}
> +
> +static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
> +{
> + if (enable)
> + return vega12_enable_gfx_off(hwmgr);
> + else
> + return vega12_disable_gfx_off(hwmgr);
> +}
> +
>  static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
>   .backend_init = vega12_hwmgr_backend_init,
>   .backend_fini = vega12_hwmgr_backend_fini,
> @@ -2378,6 +2396,7 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
>   .get_thermal_temperature_range = vega12_get_thermal_temperature_range,
>   .register_irq_handlers = smu9_register_irq_handlers,
>   .start_thermal_controller = vega12_start_thermal_controller,
> + .gfx_off_control = vega12_gfx_off_control,
>  };
>  
>  int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
> -- 
> 2.18.0
> 
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Re: [PATCH 03/10] drm/amdgpu: init rlc save restore as long as the lists exist

[Huang Rui]

On Thu, Jul 05, 2018 at 05:09:28PM +0800, Evan Quan wrote:
> It does not have to be rlc v2_1 and pg enabled. For rlc v2_0, rlc
> save restore is also needed. And pg support is definitely not a
> must for rlc save restore.
> 
> Change-Id: I85c0e3525ca7fb385c3d0b9e5abc13708c91e795
> Signed-off-by: Evan Quan 
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++-
>  1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 2f6ac255203f..8d895afa6c69 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2184,8 +2184,13 @@ static void gfx_v9_0_init_pg(struct amdgpu_device 
> *adev)
>  {
>   gfx_v9_0_init_csb(adev);
>  
> - if (!adev->gfx.rlc.is_rlc_v2_1)
> - return;
> + /* init rlc save restore as long as the lists exist */

Is there any case if the save restore list not exist?
As far as I know, it should be always existed.

Thanks,
Ray

> + if (adev->gfx.rlc.reg_list_format_size_bytes &&
> + adev->gfx.rlc.reg_list_size_bytes &&
> + adev->gfx.rlc.reg_restore_list_size) {
> + gfx_v9_1_init_rlc_save_restore_list(adev);
> + gfx_v9_0_enable_save_restore_machine(adev);
> + }
>  
>   if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
> AMD_PG_SUPPORT_GFX_SMG |
> @@ -2193,9 +2198,6 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
> AMD_PG_SUPPORT_CP |
> AMD_PG_SUPPORT_GDS |
> AMD_PG_SUPPORT_RLC_SMU_HS)) {
> - gfx_v9_1_init_rlc_save_restore_list(adev);
> - gfx_v9_0_enable_save_restore_machine(adev);
> -
>   WREG32(mmRLC_JUMP_TABLE_RESTORE,
>  adev->gfx.rlc.cp_table_gpu_addr >> 8);
>   gfx_v9_0_init_gfx_power_gating(adev);
> -- 
> 2.18.0
> 
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Re: [PATCH v2] drm/amd/display: adding ycbcr420 pixel encoding for hdmi

[Harry Wentland]

On 2018-07-04 05:26 PM, mikita.lip...@amd.com wrote:
> From: Mikita Lipski 
> 
> [why]
> HDMI EDID's VSDB contains spectial timings for specifically
> YCbCr 4:2:0 colour space. In those cases we need to verify
> if the mode provided is one of the special ones has to use
> YCbCr 4:2:0 pixel encoding for display info.
> [how]
> Verify if the mode is using specific ycbcr420 colour space with
> the help of DRM helper function and assign the mode to use
> ycbcr420 pixel encoding.
> 
> Signed-off-by: Mikita Lipski 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 01d14d8..9529043 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -2226,6 +2226,7 @@ fill_stream_properties_from_drm_display_mode(struct 
> dc_stream_state *stream,
>const struct drm_connector 
> *connector)
>  {
>   struct dc_crtc_timing *timing_out = >timing;
> + const struct drm_display_info *info = >display_info;
>  
>   memset(timing_out, 0, sizeof(struct dc_crtc_timing));
>  
> @@ -2234,8 +2235,10 @@ fill_stream_properties_from_drm_display_mode(struct 
> dc_stream_state *stream,
>   timing_out->v_border_top = 0;
>   timing_out->v_border_bottom = 0;
>   /* TODO: un-hardcode */
> -
> - if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
> + if (drm_mode_is_420_only(info, mode_in)
> + && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
> + timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
> + else if ((connector->display_info.color_formats & 
> DRM_COLOR_FORMAT_YCRCB444)
>   && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
>   timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
>   else
> 
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Re: [PATCH v2] drm/amd/display: add a check for display depth validity

[Harry Wentland]

On 2018-07-04 05:27 PM, mikita.lip...@amd.com wrote:
> From: Mikita Lipski 
> 
> [why]
> HDMI 2.0 fails to validate 4K@60 timing with 10 bpc
> [how]
> Adding a helper function that would verify if the display depth
> assigned would pass a bandwidth validation.
> Drop the display depth by one level till calculated pixel clk
> is lower than maximum TMDS clk.
> 

It'd be good to include a brief description what changed in v2. Something like

v2: check_if_display_depth_is_supported -> adjust_colour_depth_from_display_info

> Bugzilla: https://bugs.freedesktop.org/106959
> 
> Signed-off-by: Mikita Lipski 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 42 
> +++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 9529043..a0f1b1d 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -2218,6 +2218,46 @@ get_output_color_space(const struct dc_crtc_timing 
> *dc_crtc_timing)
>   return color_space;
>  }
>  
> +static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
> +{
> + if (timing_out->display_color_depth <= COLOR_DEPTH_888)
> + return;
> +
> + timing_out->display_color_depth--;
> +}
> +
> +static void adjust_colour_depth_from_display_info(struct dc_crtc_timing 
> *timing_out,
> + const struct drm_display_info 
> *info)
> +{
> + int normalized_clk;
> + if (timing_out->display_color_depth <= COLOR_DEPTH_888)
> + return;
> + do {
> + normalized_clk = timing_out->pix_clk_khz;
> + /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
> + if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
> + normalized_clk /= 2;
> + /* Adjusting pix clock following on HDMI spec based on colour 
> depth */
> + switch (timing_out->display_color_depth) {
> + case COLOR_DEPTH_101010:
> + normalized_clk = (normalized_clk * 30) / 24;
> + break;
> + case COLOR_DEPTH_121212:
> + normalized_clk = (normalized_clk * 36) / 24;
> + break;
> + case COLOR_DEPTH_161616:
> + normalized_clk = (normalized_clk * 48) / 24;
> + break;
> + default:
> + return;
> + }
> + if (normalized_clk <= info->max_tmds_clock)
> + return;
> + reduce_mode_colour_depth(timing_out);
> +
> + } while (timing_out->display_color_depth > COLOR_DEPTH_888);
> +
> +}
>  
> /*/
>  
>  static void
> @@ -2274,6 +2314,8 @@ fill_stream_properties_from_drm_display_mode(struct 
> dc_stream_state *stream,
>  
>   stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
>   stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
> + if (stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A)
> + adjust_colour_depth_from_display_info(timing_out, info);
>  }
>  
>  static void fill_audio_info(struct audio_info *audio_info,
> 
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Re: [PATCH 05/10] drm/amdgpu: drop mmRLC_PG_CNTL clear

[Huang Rui]

On Thu, Jul 05, 2018 at 05:09:30PM +0800, Evan Quan wrote:
> This may break gfxoff support since this register will
> be set by smc fw(for vega12, that's the case).
> 
> Change-Id: Id3108c63634a2f941289021bfbd78588c0f6c4d6
> Signed-off-by: Evan Quan 

Reviewed-by: Huang Rui 

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 8d870d4f8414..3a75641a071d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -2290,9 +2290,6 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device 
> *adev)
>   /* disable CG */
>   WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
>  
> - /* disable PG */
> - WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
> -
>   gfx_v9_0_rlc_reset(adev);
>  
>   gfx_v9_0_init_pg(adev);
> -- 
> 2.18.0
> 
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Re: [PATCH v3] drm/amdgpu: update documentation for amdgpu_drv.c

[Christian König]

Mhm, double checking that I now knew why my memory fooled me: We use 0 
as infinite timeout in radeon.


Maybe we should change amdgpu to do the same and reject negative values.

Christian.

Am 05.07.2018 um 16:54 schrieb Christian König:

Sounds like my memory fooled me, but we should document that as well.

Christian.

Am 05.07.2018 um 16:47 schrieb Jiang, Sonny:


Change it to,

Value 0 is invalidated, will be adjusted to 1. Negative values 
mean 'infinite timeout' (MAX_JIFFY_OFFSET).



Thanks,

Sonny


*From:* Christian König 
*Sent:* Thursday, July 5, 2018 3:30:28 AM
*To:* Jiang, Sonny; amd-gfx@lists.freedesktop.org
*Subject:* Re: [PATCH v3] drm/amdgpu: update documentation for 
amdgpu_drv.c

Am 04.07.2018 um 20:20 schrieb Sonny Jiang:
> [SNIP]
>
> +/**
> + * DOC: lockup_timeout (int)
> + * Set GPU scheduler timeout value in ms. It must be > 0.  The 
default is 1.

> + */
>   MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 
(default 1)");

>   module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);

Actually the description here is incorrect, a value of 0 is handled as
infinite timeout IIRC. Please fix while at it.

Apart from that the patch is Acked-by: Christian König
.

Christian.




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Re: [PATCH 04/10] drm/amdgpu: correct direct reg list length for v2_0 rlc

[Huang Rui]

On Thu, Jul 05, 2018 at 05:09:29PM +0800, Evan Quan wrote:
> For v2_0 rlc, rlc save restore list also needs to be initialized.
> However, there is no reg_list_format_direct_reg_list_length
> member(v2_1 spefic) for it.
> 
> Change-Id: I29bfe441c4f4b4726a7dd61b315347fea057163b
> Signed-off-by: Evan Quan 
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 8d895afa6c69..8d870d4f8414 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -42,6 +42,7 @@
>  #define GFX9_MEC_HPD_SIZE 2048
>  #define RLCG_UCODE_LOADING_START_ADDRESS 0x2000L
>  #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0xL
> +#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
>  
>  #define mmPWR_MISC_CNTL_STATUS   0x0183
>  #define mmPWR_MISC_CNTL_STATUS_BASE_IDX  0
> @@ -1927,7 +1928,7 @@ static int gfx_v9_1_init_rlc_save_restore_list(struct 
> amdgpu_device *adev)
>   /* setup unique_indirect_regs array and indirect_start_offsets array */
>   unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
>   gfx_v9_1_parse_ind_reg_list(register_list_format,
> - 
> adev->gfx.rlc.reg_list_format_direct_reg_list_length,
> + GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
>   adev->gfx.rlc.reg_list_format_size_bytes >> 
> 2,
>   unique_indirect_regs,
>   unique_indirect_reg_count,
> @@ -1952,7 +1953,7 @@ static int gfx_v9_1_init_rlc_save_restore_list(struct 
> amdgpu_device *adev)
>   adev->gfx.rlc.reg_list_format_start);
>  
>   /* direct register portion */
> - for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; 
> i++)
> + for (i = 0; i < GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH; i++)

This definition is actually defined on register_list_format.h in the ucode.
So we would better to put it in firmware header.

Thanks,
Ray

>   WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
>   register_list_format[i]);
>  
> -- 
> 2.18.0
> 
> ___
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Re: [PATCH v2] drm/amdgpu: update documentation for amdgpu_drv.c

[Alex Deucher]

On Wed, Jul 4, 2018 at 12:12 PM, Jiang, Sonny  wrote:
> Hi Alex,
>
>
> IP blocks indexes are not fixed. What's your idea to list them? By asic
> family?
>
>
> enum amd_ip_block_type {
> AMD_IP_BLOCK_TYPE_COMMON,
> AMD_IP_BLOCK_TYPE_GMC,
> AMD_IP_BLOCK_TYPE_IH,
> AMD_IP_BLOCK_TYPE_SMC,
> AMD_IP_BLOCK_TYPE_PSP,
> AMD_IP_BLOCK_TYPE_DCE,
> AMD_IP_BLOCK_TYPE_GFX,
> AMD_IP_BLOCK_TYPE_SDMA,
> AMD_IP_BLOCK_TYPE_UVD,
> AMD_IP_BLOCK_TYPE_VCE,
> AMD_IP_BLOCK_TYPE_ACP,
> AMD_IP_BLOCK_TYPE_VCN
> };
>

The order is not fixed and due to instancing, there may be more than
one of a particular block for each asic, so the order is asic
specific.  The driver prints out the list for each asic when it loads.
E.g.,
[4.204408] [drm] add ip block number 0 
[4.204408] [drm] add ip block number 1 
[4.204409] [drm] add ip block number 2 
[4.204409] [drm] add ip block number 3 
[4.204410] [drm] add ip block number 4 
[4.204411] [drm] add ip block number 5 
[4.204412] [drm] add ip block number 6 
[4.204412] [drm] add ip block number 7 
[4.204413] [drm] add ip block number 8 

So, for the patch, I would just say something like:
"Some asics may not have some IPs or may include multiple instances of
an IP so the ordering various from asic to asic.  See the driver
output in the kernel log for the list of IPs on the asic."

Alex


> Thanks,
>
> Sonny
>
>
> 
> From: Deucher, Alexander
> Sent: Wednesday, July 4, 2018 2:49:17 AM
> To: Qu, Jim; Zhang, Jerry; Jiang, Sonny; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH v2] drm/amdgpu: update documentation for amdgpu_drv.c
>
>
> yeah, that's a good idea.
>
>
> Alex
> 
> From: amd-gfx  on behalf of Qu, Jim
> 
> Sent: Wednesday, July 4, 2018 1:14 AM
> To: Zhang, Jerry; Jiang, Sonny; amd-gfx@lists.freedesktop.org
> Subject: 答复: [PATCH v2] drm/amdgpu: update documentation for amdgpu_drv.c
>
> I always confuse any bits definiation about some feature mask. such as
> ip_block_mask, pg_mask, cg_mask, pp_feature_mask. I think other people who
> is not familiar with amdgpu driver may have the same problem.
>
> So, is it possible to detail every bit mask of features?
>
> Thanks
> JimQu
>
> 
> 发件人: amd-gfx  代表 Zhang, Jerry
> (Junwei) 
> 发送时间: 2018年7月4日 12:57:01
> 收件人: Jiang, Sonny; amd-gfx@lists.freedesktop.org
> 主题: Re: [PATCH v2] drm/amdgpu: update documentation for amdgpu_drv.c
>
> On 07/04/2018 04:06 AM, Sonny Jiang wrote:
>> Signed-off-by: Sonny Jiang 
> Acked-by: Junwei Zhang 
>
>> ---
>>   Documentation/gpu/amdgpu.rst|   7 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 222
>> +++-
>>   2 files changed, 222 insertions(+), 7 deletions(-)
>>
>> diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
>> index 765c2a3..a740e49 100644
>> --- a/Documentation/gpu/amdgpu.rst
>> +++ b/Documentation/gpu/amdgpu.rst
>> @@ -5,6 +5,13 @@
>>   The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics
>> Core
>>   Next (GCN) architecture.
>>
>> +Module Parameters
>> +=
>> +
>> +The amdgpu driver supports the following module parameters:
>> +
>> +.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +
>>   Core Driver Infrastructure
>>   ==
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> index 963578c..caf81ce 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>> @@ -1,10 +1,3 @@
>> -/**
>> - * \file amdgpu_drv.c
>> - * AMD Amdgpu driver
>> - *
>> - * \author Gareth Hughes 
>> - */
>> -
>>   /*
>>* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
>>* All Rights Reserved.
>> @@ -136,102 +129,235 @@ int amdgpu_gpu_recovery = -1; /* auto */
>>   int amdgpu_emu_mode = 0;
>>   uint amdgpu_smu_memory_pool_size = 0;
>>
>> +/**
>> + * DOC: vramlimit (int)
>> + * Restrict the total amount of VRAM in MiB for testing.  The default is
>> 0 (Use full VRAM).
>> + */
>>   MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
>>   module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
>>
>> +/**
>> + * DOC: vis_vramlimit (int)
>> + * Restrict the amount of CPU visible VRAM in MiB for testing.  The
>> default is 0 (Use full CPU visible VRAM).
>> + */
>>   MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in
>> megabytes");
>>   module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
>>
>> +/**
>> + * DOC: gartsize (uint)
>> + * Restrict the size of GART in Mib (32, 64, etc.) for testing. The
>> default is -1 (The size depends on asic).
>> + */
>>   MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64,
>> etc., -1=auto)");
>>   module_param_named(gartsize, amdgpu_gart_size, uint, 

Re: [PATCH v3] drm/amdgpu: update documentation for amdgpu_drv.c

[Christian König]

Sounds like my memory fooled me, but we should document that as well.

Christian.

Am 05.07.2018 um 16:47 schrieb Jiang, Sonny:


Change it to,

Value 0 is invalidated, will be adjusted to 1. Negative values 
mean 'infinite timeout' (MAX_JIFFY_OFFSET).



Thanks,

Sonny


*From:* Christian König 
*Sent:* Thursday, July 5, 2018 3:30:28 AM
*To:* Jiang, Sonny; amd-gfx@lists.freedesktop.org
*Subject:* Re: [PATCH v3] drm/amdgpu: update documentation for 
amdgpu_drv.c

Am 04.07.2018 um 20:20 schrieb Sonny Jiang:
> [SNIP]
>
> +/**
> + * DOC: lockup_timeout (int)
> + * Set GPU scheduler timeout value in ms. It must be > 0.  The 
default is 1.

> + */
>   MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 
(default 1)");

>   module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);

Actually the description here is incorrect, a value of 0 is handled as
infinite timeout IIRC. Please fix while at it.

Apart from that the patch is Acked-by: Christian König
.

Christian.


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Re: [PATCH v3] drm/amdgpu: update documentation for amdgpu_drv.c

[Jiang, Sonny]

Change it to,

Value 0 is invalidated, will be adjusted to 1.  Negative values mean 
'infinite timeout' (MAX_JIFFY_OFFSET).


Thanks,

Sonny


From: Christian König 
Sent: Thursday, July 5, 2018 3:30:28 AM
To: Jiang, Sonny; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3] drm/amdgpu: update documentation for amdgpu_drv.c

Am 04.07.2018 um 20:20 schrieb Sonny Jiang:
> [SNIP]
>
> +/**
> + * DOC: lockup_timeout (int)
> + * Set GPU scheduler timeout value in ms. It must be > 0.  The default is 
> 1.
> + */
>   MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 
> 1)");
>   module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);

Actually the description here is incorrect, a value of 0 is handled as
infinite timeout IIRC. Please fix while at it.

Apart from that the patch is Acked-by: Christian König
.

Christian.
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[PATCH v4] drm/amdgpu: update documentation for amdgpu_drv.c

[Sonny Jiang]

Signed-off-by: Sonny Jiang 
Acked-by: Junwei Zhang 
Acked-by: Christian König 
---
 Documentation/gpu/amdgpu.rst|   7 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 371 +++-
 2 files changed, 371 insertions(+), 7 deletions(-)

diff --git a/Documentation/gpu/amdgpu.rst b/Documentation/gpu/amdgpu.rst
index 765c2a3..a740e49 100644
--- a/Documentation/gpu/amdgpu.rst
+++ b/Documentation/gpu/amdgpu.rst
@@ -5,6 +5,13 @@
 The drm/amdgpu driver supports all AMD Radeon GPUs based on the Graphics Core
 Next (GCN) architecture.
 
+Module Parameters
+=
+
+The amdgpu driver supports the following module parameters:
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+
 Core Driver Infrastructure
 ==
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 963578c..8dbdf98 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1,10 +1,3 @@
-/**
- * \file amdgpu_drv.c
- * AMD Amdgpu driver
- *
- * \author Gareth Hughes 
- */
-
 /*
  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  * All Rights Reserved.
@@ -136,102 +129,300 @@ int amdgpu_gpu_recovery = -1; /* auto */
 int amdgpu_emu_mode = 0;
 uint amdgpu_smu_memory_pool_size = 0;
 
+/**
+ * DOC: vramlimit (int)
+ * Restrict the total amount of VRAM in MiB for testing.  The default is 0 
(Use full VRAM).
+ */
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
 
+/**
+ * DOC: vis_vramlimit (int)
+ * Restrict the amount of CPU visible VRAM in MiB for testing.  The default is 
0 (Use full CPU visible VRAM).
+ */
 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in 
megabytes");
 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
 
+/**
+ * DOC: gartsize (uint)
+ * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is 
-1 (The size depends on asic).
+ */
 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., 
-1=auto)");
 module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
 
+/**
+ * DOC: gttsize (int)
+ * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's 
VRAM size if 3GB < VRAM < 3/4 RAM,
+ * otherwise 3/4 RAM size).
+ */
 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
 module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
 
+/**
+ * DOC: moverate (int)
+ * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s).
+ */
 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, 
etc., -1=auto, 0=1=disabled)");
 module_param_named(moverate, amdgpu_moverate, int, 0600);
 
+/**
+ * DOC: benchmark (int)
+ * Run benchmarks. The default is 0 (Skip benchmarks).
+ */
 MODULE_PARM_DESC(benchmark, "Run benchmark");
 module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
 
+/**
+ * DOC: test (int)
+ * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, 
only set 1 to run test).
+ */
 MODULE_PARM_DESC(test, "Run tests");
 module_param_named(test, amdgpu_testing, int, 0444);
 
+/**
+ * DOC: audio (int)
+ * Set Audio. The default is -1 (Enabled), set 0 to disabled it.
+ */
 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
 module_param_named(audio, amdgpu_audio, int, 0444);
 
+/**
+ * DOC: disp_priority (int)
+ * Set display Priority (0 = auto, 1 = normal, 2 = high). The default is 0.
+ */
 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = 
high)");
 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
 
+/**
+ * DOC: hw_i2c (int)
+ * To enable hw i2c engine. The default is 0 (Disabled).
+ */
 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
 
+/**
+ * DOC: pcie_gen2 (int)
+ * To disable PCIE Gen2 mode (0 = disable, 1 = enable). The default is -1 
(auto, enabled).
+ */
 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = 
enable)");
 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
 
+/**
+ * DOC: msi (int)
+ * To disable MSI functionality (1 = enable, 0 = disable). The default is -1 
(auto, enabled).
+ */
 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
 module_param_named(msi, amdgpu_msi, int, 0444);
 
+/**
+ * DOC: lockup_timeout (int)
+ * Set GPU scheduler timeout value in ms. Value 0 is invalidated, will be 
adjusted to 1.
+ * Negative values mean 'infinite timeout' (MAX_JIFFY_OFFSET). The default is 
1.
+ */
 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 
1)");
 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);
 
+/**
+ * DOC: dpm (int)
+ * Override for dynamic power management setting (1 = enable, 0 = disable). 
The default is -1 (auto).
+ */
 

[PATCH] drm/amd/pp: Implement get_performance_level for legacy dgpu

[Rex Zhu]

display can get clock info through this function.
implement this function for vega10 and old asics.
from vega12, there is no power state management. so need other
interface to notify display the clock info

Signed-off-by: Rex Zhu 
---
 .../gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c  |  2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c   | 24 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 24 ++
 3 files changed, 49 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 53207e7..b05b153 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -357,7 +357,7 @@ int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct 
pp_hw_power_state *s
PHM_PerformanceLevelDesignation designation)
 {
int result;
-   PHM_PerformanceLevel performance_level;
+   PHM_PerformanceLevel performance_level = {0};
 
PHM_FUNC_CHECK(hwmgr);
 
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 077b799..8eaaa6b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -5006,6 +5006,29 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr 
*hwmgr, long *input, uint
return 0;
 }
 
+static int smu7_get_performance_level(struct pp_hwmgr *hwmgr, const struct 
pp_hw_power_state *state,
+   PHM_PerformanceLevelDesignation designation, 
uint32_t index,
+   PHM_PerformanceLevel *level)
+{
+   const struct smu7_power_state *ps;
+   struct smu7_hwmgr *data;
+   uint32_t i;
+
+   if (level == NULL || hwmgr == NULL || state == NULL)
+   return -EINVAL;
+
+   data = hwmgr->backend;
+   ps = cast_const_phw_smu7_power_state(state);
+
+   i = index > ps->performance_level_count - 1 ?
+   ps->performance_level_count - 1 : index;
+
+   level->coreClock = ps->performance_levels[i].engine_clock;
+   level->memory_clock = ps->performance_levels[i].memory_clock;
+
+   return 0;
+}
+
 static const struct pp_hwmgr_func smu7_hwmgr_funcs = {
.backend_init = _hwmgr_backend_init,
.backend_fini = _hwmgr_backend_fini,
@@ -5062,6 +5085,7 @@ static int smu7_set_power_profile_mode(struct pp_hwmgr 
*hwmgr, long *input, uint
.set_power_limit = smu7_set_power_limit,
.get_power_profile_mode = smu7_get_power_profile_mode,
.set_power_profile_mode = smu7_set_power_profile_mode,
+   .get_performance_level = smu7_get_performance_level,
 };
 
 uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index eb37316..5c03df4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -4837,6 +4837,29 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr 
*hwmgr,
return 0;
 }
 
+static int vega10_get_performance_level(struct pp_hwmgr *hwmgr, const struct 
pp_hw_power_state *state,
+   PHM_PerformanceLevelDesignation designation, 
uint32_t index,
+   PHM_PerformanceLevel *level)
+{
+   const struct vega10_power_state *ps;
+   struct vega10_hwmgr *data;
+   uint32_t i;
+
+   if (level == NULL || hwmgr == NULL || state == NULL)
+   return -EINVAL;
+
+   data = hwmgr->backend;
+   ps = cast_const_phw_vega10_power_state(state);
+
+   i = index > ps->performance_level_count - 1 ?
+   ps->performance_level_count - 1 : index;
+
+   level->coreClock = ps->performance_levels[i].gfx_clock;
+   level->memory_clock = ps->performance_levels[i].mem_clock;
+
+   return 0;
+}
+
 static const struct pp_hwmgr_func vega10_hwmgr_funcs = {
.backend_init = vega10_hwmgr_backend_init,
.backend_fini = vega10_hwmgr_backend_fini,
@@ -4896,6 +4919,7 @@ static int vega10_odn_edit_dpm_table(struct pp_hwmgr 
*hwmgr,
.set_power_profile_mode = vega10_set_power_profile_mode,
.set_power_limit = vega10_set_power_limit,
.odn_edit_dpm_table = vega10_odn_edit_dpm_table,
+   .get_performance_level = vega10_get_performance_level,
 };
 
 int vega10_enable_smc_features(struct pp_hwmgr *hwmgr,
-- 
1.9.1

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[PATCH] drm/amd/pp: Convert 10KHz to KHz as variable name

[Rex Zhu]

The default clock unit in powerplay is 10KHz.

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 2 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c | 3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 5e771bc119..eb37316 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3801,7 +3801,7 @@ static int 
vega10_notify_smc_display_config_after_ps_adjustment(
 
if (i < dpm_table->count) {
clock_req.clock_type = amd_pp_dcef_clock;
-   clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value;
+   clock_req.clock_freq_in_khz = dpm_table->dpm_levels[i].value * 
10;
if (!vega10_display_clock_voltage_request(hwmgr, _req)) {
smum_send_msg_to_smc_with_parameter(
hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 5749287..ed17c56 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -1361,7 +1361,6 @@ int vega12_display_clock_voltage_request(struct pp_hwmgr 
*hwmgr,
if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
switch (clk_type) {
case amd_pp_dcef_clock:
-   clk_freq = clock_req->clock_freq_in_khz / 100;
clk_select = PPCLK_DCEFCLK;
break;
case amd_pp_disp_clock:
@@ -1410,7 +1409,7 @@ static int 
vega12_notify_smc_display_config_after_ps_adjustment(
 
if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
clock_req.clock_type = amd_pp_dcef_clock;
-   clock_req.clock_freq_in_khz = min_clocks.dcefClock;
+   clock_req.clock_freq_in_khz = min_clocks.dcefClock/10;
if (!vega12_display_clock_voltage_request(hwmgr, _req)) {
if (data->smu_features[GNLD_DS_DCEFCLK].supported)
PP_ASSERT_WITH_CODE(
-- 
1.9.1

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Re: Proposal to merge KFD into amdgpu

[Michel Dänzer]

On 2018-07-04 11:36 PM, Felix Kuehling wrote:
> Since KFD is only supported by a single GPU driver now (amdgpu), it
> makes sense to merge the two. This has been raised on the amd-gfx list
> before and I've been putting it off to avoid more churn while I was
> working on upstreaming KFD. Now seems a good time to pick this up again.
> 
> At this stage there are some things that I don't expect to change
> significantly:
> 
>   * Directory structure
>   * KFD function naming conventions
>   * KFD device and sysfs interfaces
> 
> This is a rough overview of the changes I have in mind. We should be
> able to implement these step-by-step and minimize disruption:
> 
> 1. Change the build system to build KFD into amdgpu.ko
> 
> This should make KFD similar to DAL or powerplay. It's still a mostly
> separate code base and Makefile with its own directory, but gets linked
> into amdgpu.ko.
> 
> In the kernel configuration HSA_AMD would become a boolean option under
> DRM_AMDGPU that controls whether KFD functionality gets built into amdgpu.
> 
> Any code inside #if defined(CONFIG_HSA_AMD_MODULE) can be removed.
> 
> 2. Simplify the kfd2kgd and kgd2kfg interfaces
> 
> Function pointers in struct kgd2kfd_calls are no longer needed. These
> functions can be called directly from amdgpu.
> 
> Hardware-independent function pointers in kfd2kgd_calls are no longer
> needed. These function can be called directly from amdkfd. Some of the
> function pointers in kfd2kgd_calls are used for hardware abstraction
> with different implementations for each GFX HW generation. These will
> need to remain function pointers.
> 
> At some later stage, the HW-specific functions could be moved into
> gfx_v*.c and the function pointers added to struct amdgpu_gfx. But at
> this stage I think I'd leave them where they are.
> 
> 3. Reduce duplicate tracking of device and BO structures
> 
> Currently KFD and AMDGPU pretend to not know each other's data
> structures. If both are in the same module, we could allow KFD to access
> some amdgpu structures directly (e.g. amdgpu_device and amdgpu_bo). This
> way some of the duplicate tracking of devices and buffer objects could
> be eliminated.
> 
> This may present opportunities to simplify some functionality that's
> currently split across both modules, such as suspend/resume, memory
> management and evictions.
> 
> Some interfaces that just query information from amdgpu could be removed
> if KFD can access that information directly (e.g. firmware versions, CU
> info, ...).
> 
> Please let me know if you have any objections, suggestions, ideas ...

Thumbs up from me! :)


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Re: BUG: *ERROR* No EDID read

[Alex Deucher]

On Mon, Jul 2, 2018 at 5:39 PM, Daniel Andersson  wrote:
> Sure, bisecting gets me 6e65fb862064663ad3a08f964af1e8f3f2abf688 .
>
> In drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c,
> get_firmware_info_v3_1() works but get_firmware_info_v3_2() does not
> do the right thing for my Vega.
>
> Could I break my GPU if I were to set some bad/wrong frequency there?

vega10 should not hit that new path at all.  Have you edited your
vbios?  Can you send us a copy?  To get a copy of the vbios:

Without the driver loaded:
(as root)
(use lspci to get the bus id)
cd /sys/bus/pci/devices/
echo 1 > rom
cat rom > /tmp/vbios.rom
echo 0 > rom

If the driver is loaded:
(as root)
cat /sys/kernel/debug/dri/0/amdgpu_vbios > /tmp/vbios.rom

Alex

>
> lspci:
> 43:00.0 VGA compatible controller: Advanced Micro Devices, Inc.
> [AMD/ATI] Vega 10 XT [Radeon RX Vega 64] (rev c1) (prog-if 00 [VGA
> controller])
>   Subsystem: Sapphire Technology Limited Vega 10 XT [Radeon RX Vega
> 64]
>   Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B- DisINTx+
>   Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort-
> SERR-Latency: 0, Cache Line Size: 64 bytes
>   Interrupt: pin A routed to IRQ 85
>   Region 0: Memory at d000 (64-bit, prefetchable) [size=256M]
>   Region 2: Memory at e000 (64-bit, prefetchable) [size=2M]
>   Region 4: I/O ports at f000 [size=256]
>   Region 5: Memory at ed40 (32-bit, non-prefetchable) [size=512K]
>   Expansion ROM at ed48 [disabled] [size=128K]
>   Capabilities: [48] Vendor Specific Information: Len=08 
>   Capabilities: [50] Power Management version 3
> Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA
> PME(D0-,D1+,D2+,D3hot+,D3cold+)
> Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
>   Capabilities: [64] Express (v2) Legacy Endpoint, MSI 00
> DevCap: MaxPayload 256 bytes, PhantFunc 0, Latency L0s <4us, L1
> unlimited
>   ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
> DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
>   RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
>   MaxPayload 256 bytes, MaxReadReq 512 bytes
> DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq+ AuxPwr-
> TransPend-
> LnkCap: Port #0, Speed 8GT/s, Width x16, ASPM L0s L1, Exit Latency
> L0s <64ns, L1 <1us
>   ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
> LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- CommClk+
>   ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
> LnkSta: Speed 8GT/s, Width x16, TrErr- Train- SlotClk+ DLActive-
> BWMgmt- ABWMgmt-
> DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR+,
> OBFF Not Supported
>AtomicOpsCap: 32bit- 64bit- 128bitCAS-
> DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF
> Disabled
>AtomicOpsCtl: ReqEn-
> LnkCtl2: Target Link Speed: 8GT/s, EnterCompliance- SpeedDis-
>Transmit Margin: Normal Operating Range,
> EnterModifiedCompliance- ComplianceSOS-
>Compliance De-emphasis: -6dB
> LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete+,
> EqualizationPhase1+
>EqualizationPhase2+, EqualizationPhase3+,
> LinkEqualizationRequest-
>   Capabilities: [a0] MSI: Enable+ Count=1/1 Maskable- 64bit+
> Address: fee0  Data: 
>   Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1
> Len=010 
>   Capabilities: [150 v2] Advanced Error Reporting
> UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF-
> MalfTLP- ECRC- UnsupReq- ACSViol-
> UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF-
> MalfTLP- ECRC- UnsupReq- ACSViol-
> UESvrt: DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+
> MalfTLP+ ECRC- UnsupReq- ACSViol-
> CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
> CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
> AERCap: First Error Pointer: 00, ECRCGenCap+ ECRCGenEn-
> ECRCChkCap+ ECRCChkEn-
>   MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
> HeaderLog:    
>   Capabilities: [200 v1] #15
>   Capabilities: [270 v1] #19
>   Capabilities: [2a0 v1] Access Control Services
> ACSCap: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd-
> EgressCtrl- DirectTrans-
> ACSCtl: SrcValid- TransBlk- ReqRedir- CmpltRedir- UpstreamFwd-
> EgressCtrl- DirectTrans-
>   Capabilities: [2b0 v1] Address Translation Service (ATS)
> ATSCap: Invalidate Queue Depth: 00
> ATSCtl: Enable+, Smallest Translation Unit: 00
>   Capabilities: [2c0 v1] Page Request Interface (PRI)
> PRICtl: Enable- Reset-
> PRISta: RF- UPRGI- Stopped+
> Page Request Capacity: 0020, Page Request Allocation: 
>   Capabilities: [2d0 v1] Process Address Space ID (PASID)
> PASIDCap: Exec+ Priv+, Max PASID Width: 10
> PASIDCtl: Enable- Exec- Priv-
>   Capabilities: [320 v1] Latency Tolerance Reporting
> Max snoop 

Re: [PATCH] drm/amd/display: Use 2-factor allocator calls

[Michel Dänzer]

On 2018-07-04 07:27 PM, Kees Cook wrote:
> As already done treewide, switch from open-coded multiplication to
> 2-factor allocation helper.
> 
> Signed-off-by: Kees Cook 
> ---
>  drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 
> b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> index 98edaefa2b47..ee69c949bfbf 100644
> --- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> +++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
> @@ -1723,8 +1723,8 @@ bool  mod_color_calculate_curve(enum 
> dc_transfer_func_predefined trans,
>   kvfree(rgb_regamma);
>   } else if (trans == TRANSFER_FUNCTION_HLG ||
>   trans == TRANSFER_FUNCTION_HLG12) {
> - rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
> -(MAX_HW_POINTS + _EXTRA_POINTS),
> + rgb_regamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
> +sizeof(*rgb_regamma),
>  GFP_KERNEL);
>   if (!rgb_regamma)
>   goto rgb_regamma_alloc_fail;
> @@ -1802,8 +1802,8 @@ bool  mod_color_calculate_degamma_curve(enum 
> dc_transfer_func_predefined trans,
>   kvfree(rgb_degamma);
>   } else if (trans == TRANSFER_FUNCTION_HLG ||
>   trans == TRANSFER_FUNCTION_HLG12) {
> - rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
> -(MAX_HW_POINTS + _EXTRA_POINTS),
> + rgb_degamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
> +sizeof(*rgb_degamma),
>  GFP_KERNEL);
>   if (!rgb_degamma)
>   goto rgb_degamma_alloc_fail;
> 

Since the values are constant, kvcalloc incurs the overflow checking
overhead for no gain.


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[PATCH] drm/amd/display: Use 2-factor allocator calls

[Kees Cook]

As already done treewide, switch from open-coded multiplication to
2-factor allocation helper.

Signed-off-by: Kees Cook 
---
 drivers/gpu/drm/amd/display/modules/color/color_gamma.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 98edaefa2b47..ee69c949bfbf 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -1723,8 +1723,8 @@ bool  mod_color_calculate_curve(enum 
dc_transfer_func_predefined trans,
kvfree(rgb_regamma);
} else if (trans == TRANSFER_FUNCTION_HLG ||
trans == TRANSFER_FUNCTION_HLG12) {
-   rgb_regamma = kvzalloc(sizeof(*rgb_regamma) *
-  (MAX_HW_POINTS + _EXTRA_POINTS),
+   rgb_regamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
+  sizeof(*rgb_regamma),
   GFP_KERNEL);
if (!rgb_regamma)
goto rgb_regamma_alloc_fail;
@@ -1802,8 +1802,8 @@ bool  mod_color_calculate_degamma_curve(enum 
dc_transfer_func_predefined trans,
kvfree(rgb_degamma);
} else if (trans == TRANSFER_FUNCTION_HLG ||
trans == TRANSFER_FUNCTION_HLG12) {
-   rgb_degamma = kvzalloc(sizeof(*rgb_degamma) *
-  (MAX_HW_POINTS + _EXTRA_POINTS),
+   rgb_degamma = kvcalloc(MAX_HW_POINTS + _EXTRA_POINTS,
+  sizeof(*rgb_degamma),
   GFP_KERNEL);
if (!rgb_degamma)
goto rgb_degamma_alloc_fail;
-- 
2.17.1


-- 
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Pixel Security
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Re: [PATCH] drm/amd/display/dc/dce: Fix multiple potential integer overflows

[Gustavo A. R. Silva]

On 07/04/2018 12:51 PM, Harry Wentland wrote:
[..]
>>>  
>>> @@ -145,8 +145,8 @@ static bool calculate_fb_and_fractional_fb_divider(
>>>   * of fractional feedback decimal point and the fractional FB Divider 
>>> precision
>>>   * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / 
>>> (10*100))*/
>>>  
>>> -   feedback_divider += (uint64_t)
>>> -   (5 * calc_pll_cs->fract_fb_divider_precision_factor);
>>> +   feedback_divider += 5UL *
>>> +   calc_pll_cs->fract_fb_divider_precision_factor;
>>
>> This should be 5ULL, as the commit log says, otherwise it's still only
>> 32 bits on 32-bit platforms.
>>
> 
> Agreed.
> 
> Otherwise this looks good.
> 
> With that fixed this patch is
> Reviewed-by: Harry Wentland 
> 

Hi Harry,

I already sent v2: https://patchwork.kernel.org/patch/10506897/

Thanks
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Re: [PATCH] drm/amd/display/dc/dce: Fix multiple potential integer overflows

[Gustavo A. R. Silva]

Hi Michel,

On 07/04/2018 02:38 AM, Michel Dänzer wrote:
> On 2018-07-04 03:13 AM, Gustavo A. R. Silva wrote:
>> Add suffix ULL to constant 5 and cast variables target_pix_clk_khz and
>> feedback_divider to uint64_t in order to avoid multiple potential integer
>> overflows and give the compiler complete information about the proper
>> arithmetic to use.
>>
>> Notice that such constant and variables are used in contexts that
>> expect expressions of type uint64_t (64 bits, unsigned). The current
>> casts to uint64_t effectively apply to each expression as a whole,
>> but they do not prevent them from being evaluated using 32-bit
>> arithmetic instead of 64-bit arithmetic.
>>
>> Also, once the expressions are properly evaluated using 64-bit
>> arithmentic, there is no need for the parentheses that enclose
>> them.
>>
>> Addresses-Coverity-ID: 1460245 ("Unintentional integer overflow")
>> Addresses-Coverity-ID: 1460286 ("Unintentional integer overflow")
>> Addresses-Coverity-ID: 1460401 ("Unintentional integer overflow")
>> Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
>> Signed-off-by: Gustavo A. R. Silva 
>>
>> [...]
>>  
>> @@ -145,8 +145,8 @@ static bool calculate_fb_and_fractional_fb_divider(
>>   * of fractional feedback decimal point and the fractional FB Divider 
>> precision
>>   * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/
>>  
>> -feedback_divider += (uint64_t)
>> -(5 * calc_pll_cs->fract_fb_divider_precision_factor);
>> +feedback_divider += 5UL *
>> +calc_pll_cs->fract_fb_divider_precision_factor;
> 
> This should be 5ULL, as the commit log says, otherwise it's still only
> 32 bits on 32-bit platforms.
> 

That's correct. Thanks for the report.

I'll send v2 shortly.

Thanks
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[PATCH v2] drm/amd/display/dc/dce: Fix multiple potential integer overflows

[Gustavo A. R. Silva]

Add suffix ULL to constant 5 and cast variables target_pix_clk_khz and
feedback_divider to uint64_t in order to avoid multiple potential integer
overflows and give the compiler complete information about the proper
arithmetic to use.

Notice that such constant and variables are used in contexts that
expect expressions of type uint64_t (64 bits, unsigned). The current
casts to uint64_t effectively apply to each expression as a whole,
but they do not prevent them from being evaluated using 32-bit
arithmetic instead of 64-bit arithmetic.

Also, once the expressions are properly evaluated using 64-bit
arithmentic, there is no need for the parentheses that enclose
them.

Addresses-Coverity-ID: 1460245 ("Unintentional integer overflow")
Addresses-Coverity-ID: 1460286 ("Unintentional integer overflow")
Addresses-Coverity-ID: 1460401 ("Unintentional integer overflow")
Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)")
Signed-off-by: Gustavo A. R. Silva 
---
Changes in v2:
 - Add suffix ULL to constant 5 instead of UL. Thanks to Michel Dänzer
   for pointing this out.

 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 88b09dd..ca13775 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -133,7 +133,7 @@ static bool calculate_fb_and_fractional_fb_divider(
uint64_t feedback_divider;
 
feedback_divider =
-   (uint64_t)(target_pix_clk_khz * ref_divider * post_divider);
+   (uint64_t)target_pix_clk_khz * ref_divider * post_divider;
feedback_divider *= 10;
/* additional factor, since we divide by 10 afterwards */
feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor);
@@ -145,8 +145,8 @@ static bool calculate_fb_and_fractional_fb_divider(
  * of fractional feedback decimal point and the fractional FB Divider precision
  * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/
 
-   feedback_divider += (uint64_t)
-   (5 * calc_pll_cs->fract_fb_divider_precision_factor);
+   feedback_divider += 5ULL *
+   calc_pll_cs->fract_fb_divider_precision_factor;
feedback_divider =
div_u64(feedback_divider,
calc_pll_cs->fract_fb_divider_precision_factor * 10);
@@ -203,8 +203,8 @@ static bool calc_fb_divider_checking_tolerance(
_feedback_divider);
 
/*Actual calculated value*/
-   actual_calc_clk_khz = (uint64_t)(feedback_divider *
-   calc_pll_cs->fract_fb_divider_factor) +
+   actual_calc_clk_khz = (uint64_t)feedback_divider *
+   calc_pll_cs->fract_fb_divider_factor +
fract_feedback_divider;
actual_calc_clk_khz *= calc_pll_cs->ref_freq_khz;
actual_calc_clk_khz =
-- 
2.7.4

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[PATCH xf86-video-ati 09/10] Add struct radeon_buffer

[Michel Dänzer]

From: Michel Dänzer 

Inspired by amdgpu, preparation for the following change. For now, this
is mostly a wrapper around struct radeon_bo, no functional change
intended.

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c   | 123 ++--
 src/drmmode_display.h   |   2 +-
 src/evergreen_exa.c |  40 -
 src/evergreen_state.h   |   1 -
 src/evergreen_textured_videofuncs.c |   2 +-
 src/r600_exa.c  |  40 -
 src/r600_state.h|   1 -
 src/r600_textured_videofuncs.c  |   2 +-
 src/radeon.h|  31 ---
 src/radeon_bo_helper.c  |  34 +---
 src/radeon_bo_helper.h  |  38 -
 src/radeon_dri2.c   |  22 ++---
 src/radeon_dri3.c   |   4 +-
 src/radeon_exa.c|  17 ++--
 src/radeon_exa_funcs.c  |  43 +-
 src/radeon_exa_shared.c |   2 +-
 src/radeon_exa_shared.h |   3 +-
 src/radeon_glamor.c |  10 +--
 src/radeon_glamor_wrappers.c|   6 +-
 src/radeon_kms.c| 104 ---
 src/radeon_present.c|   2 +-
 src/radeon_textured_videofuncs.c|  24 --
 22 files changed, 267 insertions(+), 284 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 3c4d94fd9..c91f5bb20 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -111,7 +111,7 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
  int width, int height,
  int depth, int bpp,
  int pitch,
- struct radeon_bo *bo)
+ struct radeon_buffer *bo)
 {
RADEONInfoPtr info = RADEONPTR(pScrn);
ScreenPtr pScreen = pScrn->pScreen;
@@ -379,7 +379,7 @@ create_pixmap_for_fbcon(drmmode_ptr drmmode,
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONInfoPtr info = RADEONPTR(pScrn);
PixmapPtr pixmap = info->fbcon_pixmap;
-   struct radeon_bo *bo;
+   struct radeon_buffer *bo;
drmModeFBPtr fbcon;
struct drm_gem_flink flink;
 
@@ -402,10 +402,18 @@ create_pixmap_for_fbcon(drmmode_ptr drmmode,
goto out_free_fb;
}
 
-   bo = radeon_bo_open(drmmode->bufmgr, flink.name, 0, 0, 0, 0);
+   bo = calloc(1, sizeof(struct radeon_buffer));
+   if (!bo) {
+   xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+  "Couldn't allocate BO for fbcon handle\n");
+   goto out_free_fb;
+   }
+   bo->ref_count = 1;
+
+   bo->bo.radeon = radeon_bo_open(drmmode->bufmgr, flink.name, 0, 0, 0, 0);
if (bo == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
-  "Couldn't allocate bo for fbcon handle\n");
+  "Couldn't open BO for fbcon handle\n");
goto out_free_fb;
}
 
@@ -413,7 +421,7 @@ create_pixmap_for_fbcon(drmmode_ptr drmmode,
  fbcon->depth, fbcon->bpp, 
fbcon->pitch,
  bo);
info->fbcon_pixmap = pixmap;
-   radeon_bo_unref(bo);
+   radeon_buffer_unref();
 out_free_fb:
drmModeFreeFB(fbcon);
return pixmap;
@@ -496,11 +504,7 @@ drmmode_crtc_scanout_destroy(drmmode_ptr drmmode,
scanout->pixmap = NULL;
}
 
-   if (scanout->bo) {
-   radeon_bo_unmap(scanout->bo);
-   radeon_bo_unref(scanout->bo);
-   scanout->bo = NULL;
-   }
+   radeon_buffer_unref(>bo);
 }
 
 void
@@ -913,7 +917,7 @@ drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr 
mode,
fb = radeon_fb_create(pScrn, pRADEONEnt->fd,
  pScrn->virtualX, pScrn->virtualY,
  pScrn->displayWidth * 
info->pixel_bytes,
- info->front_bo->handle);
+ 
info->front_buffer->bo.radeon->handle);
/* Prevent refcnt of ad-hoc FBs from reaching 2 */
drmmode_fb_reference(pRADEONEnt->fd, _crtc->fb, 
NULL);
drmmode_crtc->fb = fb;
@@ -2232,14 +2236,12 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, 
int height)
 {
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(scrn);
RADEONInfoPtr info = RADEONPTR(scrn);
-   struct radeon_bo *old_front = NULL;
+   struct radeon_buffer *old_front = NULL;
ScreenPtr   screen = xf86ScrnToScreen(scrn);
int i, pitch, old_width, old_height, old_pitch;
-   int aligned_height;
-   uint32_t screen_size;
+   

[PATCH xf86-video-ati 01/10] Drop unused drmmode_create_bo_pixmap surface parameter

[Michel Dänzer]

From: Michel Dänzer 

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index f056bf3b4..958532fb6 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -111,7 +111,7 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
  int width, int height,
  int depth, int bpp,
  int pitch,
- struct radeon_bo *bo, struct 
radeon_surface *psurf)
+ struct radeon_bo *bo)
 {
RADEONInfoPtr info = RADEONPTR(pScrn);
ScreenPtr pScreen = pScrn->pScreen;
@@ -137,9 +137,7 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
 
if (info->ChipFamily >= CHIP_FAMILY_R600) {
surface = radeon_get_pixmap_surface(pixmap);
-   if (surface && psurf) 
-   *surface = *psurf;
-   else if (surface) {
+   if (surface) {
memset(surface, 0, sizeof(struct radeon_surface));
surface->npix_x = width;
surface->npix_y = height;
@@ -444,7 +442,7 @@ create_pixmap_for_fbcon(drmmode_ptr drmmode,
 
pixmap = drmmode_create_bo_pixmap(pScrn, fbcon->width, fbcon->height,
  fbcon->depth, fbcon->bpp, 
fbcon->pitch,
- bo, NULL);
+ bo);
info->fbcon_pixmap = pixmap;
radeon_bo_unref(bo);
 out_free_fb:
@@ -581,7 +579,7 @@ drmmode_crtc_scanout_create(xf86CrtcPtr crtc, struct 
drmmode_scanout *scanout,
 width, height,
 pScrn->depth,
 pScrn->bitsPerPixel,
-pitch, scanout->bo, NULL);
+pitch, scanout->bo);
if (!scanout->pixmap) {
ErrorF("failed to create CRTC scanout pixmap\n");
goto error;
-- 
2.18.0

___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

[PATCH xf86-video-ati 04/10] glamor: Don't store radeon_surfaces in pixmaps

[Michel Dänzer]

From: Michel Dänzer 

Only EXA needs them.

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c  | 77 +-
 src/radeon.h   | 19 ++-
 src/radeon_bo_helper.c | 22 +---
 src/radeon_glamor.c|  8 ++---
 src/radeon_kms.c   | 11 +++---
 5 files changed, 55 insertions(+), 82 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index f99667fb1..8dc776fa5 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -116,7 +116,6 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
RADEONInfoPtr info = RADEONPTR(pScrn);
ScreenPtr pScreen = pScrn->pScreen;
PixmapPtr pixmap;
-   struct radeon_surface *surface;
uint32_t tiling;
 
pixmap = (*pScreen->CreatePixmap)(pScreen, 0, 0, depth,
@@ -135,41 +134,41 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr 
pScrn,
if (!radeon_set_pixmap_bo(pixmap, bo))
goto fail;
 
-   if (info->surf_man) {
-   surface = radeon_get_pixmap_surface(pixmap);
-   if (surface) {
-   memset(surface, 0, sizeof(struct radeon_surface));
-   surface->npix_x = width;
-   surface->npix_y = height;
-   surface->npix_z = 1;
-   surface->blk_w = 1;
-   surface->blk_h = 1;
-   surface->blk_d = 1;
-   surface->array_size = 1;
-   surface->last_level = 0;
-   surface->bpe = bpp / 8;
-   surface->nsamples = 1;
-   surface->flags = RADEON_SURF_SCANOUT;
-   /* we are requiring a recent enough libdrm version */
-   surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-   surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, 
TYPE);
-   surface->flags |= 
RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
-   tiling = radeon_get_pixmap_tiling_flags(pixmap);
-   if (tiling & RADEON_TILING_MICRO) {
-   surface->flags = 
RADEON_SURF_CLR(surface->flags, MODE);
-   surface->flags |= 
RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
-   }
-   if (tiling & RADEON_TILING_MACRO) {
-   surface->flags = 
RADEON_SURF_CLR(surface->flags, MODE);
-   surface->flags |= 
RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
-   }
-   if (radeon_surface_best(info->surf_man, surface)) {
-   goto fail;
-   }
-   if (radeon_surface_init(info->surf_man, surface)) {
-   goto fail;
-   }
+   if (info->surf_man && !info->use_glamor) {
+   struct radeon_surface *surface = 
radeon_get_pixmap_surface(pixmap);
+
+   memset(surface, 0, sizeof(struct radeon_surface));
+   surface->npix_x = width;
+   surface->npix_y = height;
+   surface->npix_z = 1;
+   surface->blk_w = 1;
+   surface->blk_h = 1;
+   surface->blk_d = 1;
+   surface->array_size = 1;
+   surface->last_level = 0;
+   surface->bpe = bpp / 8;
+   surface->nsamples = 1;
+   surface->flags = RADEON_SURF_SCANOUT;
+   /* we are requiring a recent enough libdrm version */
+   surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
+   surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
+   surface->flags |= 
RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
+   tiling = radeon_get_pixmap_tiling_flags(pixmap);
+
+   if (tiling & RADEON_TILING_MICRO) {
+   surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
+   surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, 
MODE);
}
+   if (tiling & RADEON_TILING_MACRO) {
+   surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
+   surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, 
MODE);
+   }
+
+   if (radeon_surface_best(info->surf_man, surface))
+   goto fail;
+
+   if (radeon_surface_init(info->surf_man, surface))
+   goto fail;
}
 
if (!info->use_glamor ||
@@ -2272,7 +2271,6 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int 
height)
int cpp = info->pixel_bytes;
struct radeon_bo *front_bo;
struct radeon_surface surface;
-   struct radeon_surface *psurface;
uint32_t tiling_flags = 0, 

[PATCH xf86-video-ati 08/10] Refactor radeon_finish helper

[Michel Dänzer]

From: Michel Dänzer 

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c| 16 +++-
 src/radeon.h |  1 +
 src/radeon_bo_helper.c   | 10 ++
 src/radeon_bo_helper.h   |  3 +++
 src/radeon_glamor_wrappers.c | 21 ++---
 src/radeon_kms.c |  6 ++
 src/radeon_present.c |  4 +---
 7 files changed, 30 insertions(+), 31 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 54b09730d..3c4d94fd9 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -726,8 +726,7 @@ drmmode_crtc_prime_scanout_update(xf86CrtcPtr crtc, 
DisplayModePtr mode,
  gc, 0, 0, mode->HDisplay, 
mode->VDisplay,
  0, 0);
FreeScratchGC(gc);
-   radeon_cs_flush_indirect(scrn);
-   radeon_bo_wait(drmmode_crtc->scanout[0].bo);
+   radeon_finish(scrn, drmmode_crtc->scanout[0].bo);
}
}
 
@@ -785,8 +784,7 @@ drmmode_crtc_scanout_update(xf86CrtcPtr crtc, 
DisplayModePtr mode,
radeon_scanout_do_update(crtc, scanout_id,
 screen->GetWindowPixmap(screen->root),
 *box);
-   radeon_cs_flush_indirect(scrn);
-   radeon_bo_wait(drmmode_crtc->scanout[scanout_id].bo);
+   radeon_finish(scrn, drmmode_crtc->scanout[scanout_id].bo);
}
 }
 
@@ -2240,7 +2238,6 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int 
height)
int aligned_height;
uint32_t screen_size;
int cpp = info->pixel_bytes;
-   struct radeon_bo *front_bo;
struct radeon_surface surface;
uint32_t tiling_flags = 0, base_align;
PixmapPtr ppix = screen->GetScreenPixmap(screen);
@@ -2249,12 +2246,6 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, 
int height)
if (scrn->virtualX == width && scrn->virtualY == height)
return TRUE;
 
-   front_bo = info->front_bo;
-   radeon_cs_flush_indirect(scrn);
-
-   if (front_bo)
-   radeon_bo_wait(front_bo);
-
if (info->allowColorTiling && !info->shadow_primary) {
if (info->ChipFamily >= CHIP_FAMILY_R600) {
if (info->allowColorTiling2D) {
@@ -2364,8 +2355,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int 
height)
}
 
radeon_pixmap_clear(ppix);
-   radeon_cs_flush_indirect(scrn);
-   radeon_bo_wait(info->front_bo);
+   radeon_finish(scrn, info->front_bo);
 
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
diff --git a/src/radeon.h b/src/radeon.h
index c2ae6606e..499e89f92 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -895,6 +895,7 @@ radeon_pixmap_get_fb(PixmapPtr pix)
 return *fb_ptr;
 }
 
+
 #define CP_PACKET0(reg, n) \
(RADEON_CP_PACKET0 | ((n) << 16) | ((reg) >> 2))
 #define CP_PACKET1(reg0, reg1) \
diff --git a/src/radeon_bo_helper.c b/src/radeon_bo_helper.c
index 376589427..7cfe91265 100644
--- a/src/radeon_bo_helper.c
+++ b/src/radeon_bo_helper.c
@@ -235,6 +235,16 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int 
height, int depth,
 return bo;
 }
 
+
+/* Flush and wait for the BO to become idle */
+void
+radeon_finish(ScrnInfoPtr scrn, struct radeon_bo *bo)
+{
+radeon_cs_flush_indirect(scrn);
+radeon_bo_wait(bo);
+}
+
+
 /* Clear the pixmap contents to black */
 void
 radeon_pixmap_clear(PixmapPtr pixmap)
diff --git a/src/radeon_bo_helper.h b/src/radeon_bo_helper.h
index e1856adb1..fa99201b2 100644
--- a/src/radeon_bo_helper.h
+++ b/src/radeon_bo_helper.h
@@ -28,6 +28,9 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int 
height, int depth,
   int usage_hint, int bitsPerPixel, int *new_pitch,
   struct radeon_surface *new_surface, uint32_t 
*new_tiling);
 
+extern void
+radeon_finish(ScrnInfoPtr scrn, struct radeon_bo *bo);
+
 extern void
 radeon_pixmap_clear(PixmapPtr pixmap);
 
diff --git a/src/radeon_glamor_wrappers.c b/src/radeon_glamor_wrappers.c
index d73742528..94700a7b9 100644
--- a/src/radeon_glamor_wrappers.c
+++ b/src/radeon_glamor_wrappers.c
@@ -58,13 +58,13 @@ radeon_glamor_prepare_access_cpu(ScrnInfoPtr scrn, 
RADEONInfoPtr info,
struct radeon_bo *bo = priv->bo;
int ret;
 
-   /* When falling back to swrast, flush all pending operations */
-   if (need_sync) {
-   glamor_block_handler(scrn->pScreen);
-   info->gpu_flushed++;
-   }
-
if (!pixmap->devPrivate.ptr) {
+   /* When falling back to swrast, flush all pending operations */
+   if (need_sync) {
+   

[PATCH xf86-video-ati 05/10] Factor out radeon_surface_initialize helper

[Michel Dänzer]

From: Michel Dänzer 

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c  |  66 +---
 src/radeon.h   |   5 +
 src/radeon_bo_helper.c | 231 +
 src/radeon_kms.c   |  35 +--
 4 files changed, 131 insertions(+), 206 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 8dc776fa5..c7bec59c8 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -116,7 +116,6 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
RADEONInfoPtr info = RADEONPTR(pScrn);
ScreenPtr pScreen = pScrn->pScreen;
PixmapPtr pixmap;
-   uint32_t tiling;
 
pixmap = (*pScreen->CreatePixmap)(pScreen, 0, 0, depth,
  RADEON_CREATE_PIXMAP_SCANOUT);
@@ -137,37 +136,8 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr 
pScrn,
if (info->surf_man && !info->use_glamor) {
struct radeon_surface *surface = 
radeon_get_pixmap_surface(pixmap);
 
-   memset(surface, 0, sizeof(struct radeon_surface));
-   surface->npix_x = width;
-   surface->npix_y = height;
-   surface->npix_z = 1;
-   surface->blk_w = 1;
-   surface->blk_h = 1;
-   surface->blk_d = 1;
-   surface->array_size = 1;
-   surface->last_level = 0;
-   surface->bpe = bpp / 8;
-   surface->nsamples = 1;
-   surface->flags = RADEON_SURF_SCANOUT;
-   /* we are requiring a recent enough libdrm version */
-   surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-   surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
-   surface->flags |= 
RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
-   tiling = radeon_get_pixmap_tiling_flags(pixmap);
-
-   if (tiling & RADEON_TILING_MICRO) {
-   surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
-   surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, 
MODE);
-   }
-   if (tiling & RADEON_TILING_MACRO) {
-   surface->flags = RADEON_SURF_CLR(surface->flags, MODE);
-   surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, 
MODE);
-   }
-
-   if (radeon_surface_best(info->surf_man, surface))
-   goto fail;
-
-   if (radeon_surface_init(info->surf_man, surface))
+   if (!radeon_surface_initialize(info, surface, width, height, 
bpp / 8,
+  
radeon_get_pixmap_tiling_flags(pixmap), 0))
goto fail;
}
 
@@ -2301,36 +2271,10 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, 
int height)
base_align = 4096;
 
if (info->surf_man) {
-   memset(, 0, sizeof(struct radeon_surface));
-   surface.npix_x = width;
-   surface.npix_y = height;
-   surface.npix_z = 1;
-   surface.blk_w = 1;
-   surface.blk_h = 1;
-   surface.blk_d = 1;
-   surface.array_size = 1;
-   surface.last_level = 0;
-   surface.bpe = cpp;
-   surface.nsamples = 1;
-   surface.flags = RADEON_SURF_SCANOUT;
-   /* we are requiring a recent enough libdrm version */
-   surface.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-   surface.flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
-   surface.flags |= 
RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
-   if (tiling_flags & RADEON_TILING_MICRO) {
-   surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
-   surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, 
MODE);
-   }
-   if (tiling_flags & RADEON_TILING_MACRO) {
-   surface.flags = RADEON_SURF_CLR(surface.flags, MODE);
-   surface.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, 
MODE);
-   }
-   if (radeon_surface_best(info->surf_man, )) {
-   return FALSE;
-   }
-   if (radeon_surface_init(info->surf_man, )) {
+   if (!radeon_surface_initialize(info, , width, height,
+  cpp, tiling_flags, 0))
return FALSE;
-   }
+
screen_size = surface.bo_size;
base_align = surface.bo_alignment;
pitch = surface.level[0].pitch_bytes;
diff --git a/src/radeon.h b/src/radeon.h
index 63b6cf1ff..c2ae6606e 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -643,6 +643,11 @@ extern void RADEONInit3DEngine(ScrnInfoPtr pScrn);
 extern int radeon_cs_space_remaining(ScrnInfoPtr pScrn);
 
 /* radeon_bo_helper.c 

[PATCH xf86-video-ati 10/10] glamor: Use GBM for BO allocation when possible

[Michel Dänzer]

From: Michel Dänzer 

Inspired by amdgpu. This avoids various issues due to a GEM handle
lifetime conflict between us and Mesa with current glamor.

Bugzilla: https://bugs.freedesktop.org/105381
Signed-off-by: Michel Dänzer 
---
 configure.ac   |  10 
 src/Makefile.am|   4 +-
 src/drmmode_display.c  |  39 --
 src/radeon.h   |   7 ++-
 src/radeon_bo_helper.c | 118 -
 src/radeon_bo_helper.h |  20 ++-
 src/radeon_dri2.c  |   7 +--
 src/radeon_dri3.c  |  13 +++--
 src/radeon_glamor.c|  47 ++--
 src/radeon_glamor.h|  28 +-
 src/radeon_kms.c   |  40 +-
 11 files changed, 266 insertions(+), 67 deletions(-)

diff --git a/configure.ac b/configure.ac
index 11efdf0ae..f5614749f 100644
--- a/configure.ac
+++ b/configure.ac
@@ -138,12 +138,22 @@ if test "x$GLAMOR" != "xno"; then
 [Have 
glamor_egl_destroy_textured_pixmap API])], [],
  [#include "xorg-server.h"
   #include "glamor.h"])
+
+   AC_CHECK_DECL(glamor_finish,
+ [AC_DEFINE(HAVE_GLAMOR_FINISH, 1,
+[Have glamor_finish API])],
+[PKG_CHECK_MODULES(LIBGL, [gl])],
+ [#include "xorg-server.h"
+  #include "glamor.h"])
fi
 
if test "x$GLAMOR_XSERVER" != xyes; then
PKG_CHECK_MODULES(LIBGLAMOR, [glamor >= 0.6.0])
PKG_CHECK_MODULES(LIBGLAMOR_EGL, [glamor-egl])
fi
+
+   PKG_CHECK_MODULES(GBM, [gbm >= 10.6])
+
AC_DEFINE(USE_GLAMOR, 1, [Enable glamor acceleration])
 else
AC_MSG_RESULT([$GLAMOR])
diff --git a/src/Makefile.am b/src/Makefile.am
index ed1bfa9e6..df4a95e4f 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -62,8 +62,8 @@ radeon_drv_la_SOURCES = \
$(RADEON_KMS_SRCS)
 
 if GLAMOR
-AM_CFLAGS += @LIBGLAMOR_CFLAGS@
-radeon_drv_la_LIBADD += @LIBGLAMOR_LIBS@
+AM_CFLAGS += @LIBGLAMOR_CFLAGS@ @GBM_CFLAGS@
+radeon_drv_la_LIBADD += @LIBGLAMOR_LIBS@ @GBM_LIBS@
 radeon_drv_la_SOURCES += \
 radeon_glamor_wrappers.c \
 radeon_glamor.c
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index c91f5bb20..2773ce672 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -142,8 +142,7 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
}
 
if (!info->use_glamor ||
-   radeon_glamor_create_textured_pixmap(pixmap,
-
radeon_get_pixmap_private(pixmap)))
+   radeon_glamor_create_textured_pixmap(pixmap, bo))
return pixmap;
 
 fail:
@@ -435,8 +434,14 @@ destroy_pixmap_for_fbcon(ScrnInfoPtr pScrn)
/* XXX: The current GPUVM support in the kernel doesn't allow removing
 * the virtual address range for this BO, so we need to keep around
 * the pixmap to avoid breaking glamor with GPUVM
+*
+* Similarly, need to keep around the pixmap with current glamor, to
+* avoid issues due to a GEM handle lifetime conflict between us and
+* Mesa
 */
-   if (info->use_glamor && info->ChipFamily >= CHIP_FAMILY_CAYMAN)
+   if (info->use_glamor &&
+   (info->ChipFamily >= CHIP_FAMILY_CAYMAN ||
+xorgGetVersion() >= XORG_VERSION_NUMERIC(1,19,99,1,0)))
return;
 
if (info->fbcon_pixmap)
@@ -2277,21 +2282,23 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, 
int height)
 
scrn->displayWidth = pitch / cpp;
 
+   if (!info->use_glamor) {
 #if X_BYTE_ORDER == X_BIG_ENDIAN
-   switch (cpp) {
-   case 4:
-   tiling_flags |= RADEON_TILING_SWAP_32BIT;
-   break;
-   case 2:
-   tiling_flags |= RADEON_TILING_SWAP_16BIT;
-   break;
-   }
-   if (info->ChipFamily < CHIP_FAMILY_R600 &&
-   info->r600_shadow_fb && tiling_flags)
-   tiling_flags |= RADEON_TILING_SURFACE;
+   switch (cpp) {
+   case 4:
+   tiling_flags |= RADEON_TILING_SWAP_32BIT;
+   break;
+   case 2:
+   tiling_flags |= RADEON_TILING_SWAP_16BIT;
+   break;
+   }
+   if (info->ChipFamily < CHIP_FAMILY_R600 &&
+   info->r600_shadow_fb && tiling_flags)
+   tiling_flags |= RADEON_TILING_SURFACE;
 #endif
-   if (tiling_flags)
-   radeon_bo_set_tiling(info->front_buffer->bo.radeon, tiling_flags, 
pitch);
+   if (tiling_flags)
+   radeon_bo_set_tiling(info->front_buffer->bo.radeon, 
tiling_flags, pitch);
+   }
 
if (!info->r600_shadow_fb) {
if (info->surf_man && !info->use_glamor)
diff --git 

[PATCH xf86-video-ati 06/10] Move flush from radeon_scanout_do_update to its callers

[Michel Dänzer]

From: Michel Dänzer 

No functional change intended.

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c | 2 ++
 src/radeon_kms.c  | 8 +---
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index c7bec59c8..54b09730d 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -785,6 +785,7 @@ drmmode_crtc_scanout_update(xf86CrtcPtr crtc, 
DisplayModePtr mode,
radeon_scanout_do_update(crtc, scanout_id,
 screen->GetWindowPixmap(screen->root),
 *box);
+   radeon_cs_flush_indirect(scrn);
radeon_bo_wait(drmmode_crtc->scanout[scanout_id].bo);
}
 }
@@ -3225,6 +3226,7 @@ Bool radeon_do_pageflip(ScrnInfoPtr scrn, ClientPtr 
client,
 
radeon_scanout_do_update(crtc, scanout_id, new_front,
 extents);
+   radeon_cs_flush_indirect(crtc->scrn);
 
drmmode_crtc_wait_pending_event(drmmode_crtc, 
pRADEONEnt->fd,

drmmode_crtc->scanout_update_pending);
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 7ff66bf3c..8579aaf81 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -985,8 +985,6 @@ radeon_scanout_do_update(xf86CrtcPtr xf86_crtc, int 
scanout_id,
FreeScratchGC(gc);
 }
 
-radeon_cs_flush_indirect(scrn);
-
 info->accel_state->force = force;
 
 return TRUE;
@@ -1013,8 +1011,10 @@ radeon_scanout_update_handler(xf86CrtcPtr crtc, uint32_t 
frame, uint64_t usec,
drmmode_crtc->dpms_mode == DPMSModeOn) {
if (radeon_scanout_do_update(crtc, drmmode_crtc->scanout_id,
 screen->GetWindowPixmap(screen->root),
-region->extents))
+region->extents)) {
+   radeon_cs_flush_indirect(crtc->scrn);
RegionEmpty(region);
+   }
 }
 
 radeon_scanout_update_abort(crtc, event_data);
@@ -1096,6 +1096,8 @@ radeon_scanout_flip(ScreenPtr pScreen, RADEONInfoPtr info,
  pScreen->GetWindowPixmap(pScreen->root),
  region->extents))
return;
+
+radeon_cs_flush_indirect(scrn);
 RegionEmpty(region);
 
 drm_queue_seq = radeon_drm_queue_alloc(xf86_crtc,
-- 
2.18.0

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[PATCH xf86-video-ati 03/10] Only initialize libdrm_radeon surface manager for >= R600

[Michel Dänzer]

From: Michel Dänzer 

Not used with older GPUs.

Signed-off-by: Michel Dänzer 
---
 src/drmmode_display.c  |  5 +++--
 src/radeon_bo_helper.c |  7 ---
 src/radeon_kms.c   | 18 +++---
 3 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 958532fb6..f99667fb1 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -135,7 +135,7 @@ static PixmapPtr drmmode_create_bo_pixmap(ScrnInfoPtr pScrn,
if (!radeon_set_pixmap_bo(pixmap, bo))
goto fail;
 
-   if (info->ChipFamily >= CHIP_FAMILY_R600) {
+   if (info->surf_man) {
surface = radeon_get_pixmap_surface(pixmap);
if (surface) {
memset(surface, 0, sizeof(struct radeon_surface));
@@ -2301,7 +2301,8 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int 
height)
aligned_height = RADEON_ALIGN(height, drmmode_get_height_align(scrn, 
tiling_flags));
screen_size = RADEON_ALIGN(pitch * aligned_height, 
RADEON_GPU_PAGE_SIZE);
base_align = 4096;
-   if (info->ChipFamily >= CHIP_FAMILY_R600) {
+
+   if (info->surf_man) {
memset(, 0, sizeof(struct radeon_surface));
surface.npix_x = width;
surface.npix_y = height;
diff --git a/src/radeon_bo_helper.c b/src/radeon_bo_helper.c
index 0366f613b..8245d6247 100644
--- a/src/radeon_bo_helper.c
+++ b/src/radeon_bo_helper.c
@@ -107,9 +107,10 @@ radeon_alloc_pixmap_bo(ScrnInfoPtr pScrn, int width, int 
height, int depth,
 pitch = RADEON_ALIGN(width, drmmode_get_pitch_align(pScrn, cpp, tiling)) * 
cpp;
 base_align = drmmode_get_base_align(pScrn, cpp, tiling);
 size = RADEON_ALIGN(heighta * pitch, RADEON_GPU_PAGE_SIZE);
-memset(, 0, sizeof(struct radeon_surface));
 
-if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) {
+if (info->surf_man) {
+   memset(, 0, sizeof(struct radeon_surface));
+
if (width) {
surface.npix_x = width;
/* need to align height to 8 for old kernel */
@@ -340,7 +341,7 @@ Bool radeon_set_shared_pixmap_backing(PixmapPtr ppix, void 
*fd_handle,
 if (!ret)
goto error;
 
-if (info->ChipFamily >= CHIP_FAMILY_R600 && info->surf_man) {
+if (info->surf_man) {
uint32_t tiling_flags;
 
 #ifdef USE_GLAMOR
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 26810e084..861fbf97c 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -2228,7 +2228,16 @@ Bool RADEONScreenInit_KMS(ScreenPtr pScreen, int argc, 
char **argv)
 if (info->r600_shadow_fb == FALSE)
 info->directRenderingEnabled = radeon_dri2_screen_init(pScreen);
 
-info->surf_man = radeon_surface_manager_new(pRADEONEnt->fd);
+if (info->ChipFamily >= CHIP_FAMILY_R600) {
+   info->surf_man = radeon_surface_manager_new(pRADEONEnt->fd);
+
+   if (!info->surf_man) {
+   xf86DrvMsg(pScreen->myNum, X_ERROR,
+  "Failed to initialize surface manager\n");
+   return FALSE;
+   }
+}
+
 if (!info->bufmgr)
 info->bufmgr = radeon_bo_manager_gem_ctor(pRADEONEnt->fd);
 if (!info->bufmgr) {
@@ -2694,12 +2703,7 @@ static Bool radeon_setup_kernel_mem(ScreenPtr pScreen)
 pitch = RADEON_ALIGN(pScrn->virtualX, drmmode_get_pitch_align(pScrn, cpp, 
tiling_flags)) * cpp;
 screen_size = RADEON_ALIGN(pScrn->virtualY, 
drmmode_get_height_align(pScrn, tiling_flags)) * pitch;
 base_align = drmmode_get_base_align(pScrn, cpp, tiling_flags);
-   if (info->ChipFamily >= CHIP_FAMILY_R600) {
-   if(!info->surf_man) {
-   xf86DrvMsg(pScreen->myNum, X_ERROR,
-  "failed to initialise surface manager\n");
-   return FALSE;
-   }
+   if (info->surf_man) {
memset(, 0, sizeof(struct radeon_surface));
surface.npix_x = pScrn->virtualX;
surface.npix_y = pScrn->virtualY;
-- 
2.18.0

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[PATCH xf86-video-ati 02/10] EXA: Remove old RADEONEXACreatePixmap hook

[Michel Dänzer]

From: Michel Dänzer 

Not used by any supported version of xserver.

Signed-off-by: Michel Dänzer 
---
 src/evergreen_exa.c|  1 -
 src/evergreen_state.h  |  1 -
 src/r600_exa.c |  1 -
 src/r600_state.h   |  1 -
 src/radeon_exa.c   | 29 -
 src/radeon_exa_funcs.c |  1 -
 6 files changed, 34 deletions(-)

diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index 858481333..41edd3453 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -2065,7 +2065,6 @@ EVERGREENDrawInit(ScreenPtr pScreen)
 info->accel_state->exa->MarkSync = EVERGREENMarkSync;
 info->accel_state->exa->WaitMarker = EVERGREENSync;
 
-info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap;
 info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap;
 info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen;
 info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS;
diff --git a/src/evergreen_state.h b/src/evergreen_state.h
index 795d44720..ef3310025 100644
--- a/src/evergreen_state.h
+++ b/src/evergreen_state.h
@@ -345,7 +345,6 @@ R600SetAccelState(ScrnInfoPtr pScrn,
 
 extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
 extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
-extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
 extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
int depth, int usage_hint, int bitsPerPixel,
int *new_pitch);
diff --git a/src/r600_exa.c b/src/r600_exa.c
index c69b8fce7..a111dd456 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -2044,7 +2044,6 @@ R600DrawInit(ScreenPtr pScreen)
 info->accel_state->exa->MarkSync = R600MarkSync;
 info->accel_state->exa->WaitMarker = R600Sync;
 
-info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap;
 info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap;
 info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen;
 info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS;
diff --git a/src/r600_state.h b/src/r600_state.h
index fda297d31..4898e8de8 100644
--- a/src/r600_state.h
+++ b/src/r600_state.h
@@ -316,7 +316,6 @@ R600SetAccelState(ScrnInfoPtr pScrn,
 
 extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
 extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
-extern void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align);
 extern void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
int depth, int usage_hint, int bitsPerPixel,
int *new_pitch);
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 9106d5c65..ef60bc0c1 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -235,35 +235,6 @@ void RADEONFinishAccess_CS(PixmapPtr pPix, int index)
 }
 
 
-void *RADEONEXACreatePixmap(ScreenPtr pScreen, int size, int align)
-{
-ScrnInfoPtr pScrn = xf86ScreenToScrn(pScreen);
-RADEONInfoPtr info = RADEONPTR(pScrn);
-struct radeon_exa_pixmap_priv *new_priv;
-
-if (size != 0 && !info->exa_force_create &&
-   info->exa_pixmaps == FALSE)
-return NULL;
-   
-new_priv = calloc(1, sizeof(struct radeon_exa_pixmap_priv));
-if (!new_priv)
-   return NULL;
-
-if (size == 0)
-   return new_priv;
-
-new_priv->bo = radeon_bo_open(info->bufmgr, 0, size, align,
- RADEON_GEM_DOMAIN_VRAM, 0);
-if (!new_priv->bo) {
-   free(new_priv);
-   ErrorF("Failed to alloc memory\n");
-   return NULL;
-}
-
-return new_priv;
-
-}
-
 void *RADEONEXACreatePixmap2(ScreenPtr pScreen, int width, int height,
 int depth, int usage_hint, int bitsPerPixel,
 int *new_pitch)
diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
index da0524ede..add89458f 100644
--- a/src/radeon_exa_funcs.c
+++ b/src/radeon_exa_funcs.c
@@ -638,7 +638,6 @@ Bool RADEONDrawInit(ScreenPtr pScreen)
 }
 #endif
 
-info->accel_state->exa->CreatePixmap = RADEONEXACreatePixmap;
 info->accel_state->exa->DestroyPixmap = RADEONEXADestroyPixmap;
 info->accel_state->exa->PixmapIsOffscreen = RADEONEXAPixmapIsOffscreen;
 info->accel_state->exa->PrepareAccess = RADEONPrepareAccess_CS;
-- 
2.18.0

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[PATCH xf86-video-ati 07/10] Remove throttling from radeon_dri2_copy_region2

[Michel Dänzer]

From: Jammy Zhou 

Throttling should be handled by the client-side drivers.

Signed-off-by: Jammy Zhou 
(Ported from amdgpu commit 8a34a8149860ac15e83ccdbd8d9a527d8d3e5997)
Signed-off-by: Michel Dänzer 
---
 src/radeon_dri2.c | 22 --
 1 file changed, 22 deletions(-)

diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index 3b75f66f3..6f4691276 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -336,9 +336,7 @@ radeon_dri2_copy_region2(ScreenPtr pScreen,
 Bool vsync;
 Bool translate = FALSE;
 int off_x = 0, off_y = 0;
-PixmapPtr dst_ppix;
 
-dst_ppix = dst_private->pixmap;
 src_drawable = _private->pixmap->drawable;
 dst_drawable = _private->pixmap->drawable;
 
@@ -355,7 +353,6 @@ radeon_dri2_copy_region2(ScreenPtr pScreen,
dst_drawable = DRI2UpdatePrime(drawable, dest_buffer);
if (!dst_drawable)
return;
-   dst_ppix = (PixmapPtr)dst_drawable;
if (dst_drawable != drawable)
translate = TRUE;
} else
@@ -379,26 +376,7 @@ radeon_dri2_copy_region2(ScreenPtr pScreen,
 (*gc->funcs->ChangeClip) (gc, CT_REGION, copy_clip, 0);
 ValidateGC(dst_drawable, gc);
 
-/* If this is a full buffer swap or frontbuffer flush, throttle on the
- * previous one
- */
-if (dst_private->attachment == DRI2BufferFrontLeft) {
-   if (REGION_NUM_RECTS(region) == 1) {
-   BoxPtr extents = REGION_EXTENTS(pScreen, region);
-
-   if (extents->x1 == 0 && extents->y1 == 0 &&
-   extents->x2 == drawable->width &&
-   extents->y2 == drawable->height) {
-   struct radeon_bo *bo = radeon_get_pixmap_bo(dst_ppix);
-
-   if (bo)
-   radeon_bo_wait(bo);
-   }
-   }
-}
-
 vsync = info->accel_state->vsync;
-
 /* Driver option "SwapbuffersWait" defines if we vsync DRI2 copy-swaps. */ 
 info->accel_state->vsync = info->swapBuffersWait;
 info->accel_state->force = TRUE;
-- 
2.18.0

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[PATCH xf86-video-ati 00/10] glamor: Use GBM for BO allocation when possible

[Michel Dänzer]

From: Michel Dänzer 

This series addresses https://bugs.freedesktop.org/105381 and is mostly
inspired by the amdgpu driver.

Patches 1 & 2 clean up things I noticed being unused while working on
this series.

Patches 3-5 are struct radeon_surface related cleanups.

Patches 6-8 are flush/finish related preparations.

Patch 9 lays the ground work for patch 10, which finally switches the
glamor code to using GBM for BO allocation when possible.

Jammy Zhou (1):
  Remove throttling from radeon_dri2_copy_region2

Michel Dänzer (9):
  Drop unused drmmode_create_bo_pixmap surface parameter
  EXA: Remove old RADEONEXACreatePixmap hook
  Only initialize libdrm_radeon surface manager for >= R600
  glamor: Don't store radeon_surfaces in pixmaps
  Factor out radeon_surface_initialize helper
  Move flush from radeon_scanout_do_update to its callers
  Refactor radeon_finish helper
  Add struct radeon_buffer
  glamor: Use GBM for BO allocation when possible

 configure.ac|  10 +
 src/Makefile.am |   4 +-
 src/drmmode_display.c   | 252 ++---
 src/drmmode_display.h   |   2 +-
 src/evergreen_exa.c |  41 ++-
 src/evergreen_state.h   |   2 -
 src/evergreen_textured_videofuncs.c |   2 +-
 src/r600_exa.c  |  41 ++-
 src/r600_state.h|   2 -
 src/r600_textured_videofuncs.c  |   2 +-
 src/radeon.h|  61 ++---
 src/radeon_bo_helper.c  | 404 ++--
 src/radeon_bo_helper.h  |  55 +++-
 src/radeon_dri2.c   |  49 +---
 src/radeon_dri3.c   |  15 +-
 src/radeon_exa.c|  46 +---
 src/radeon_exa_funcs.c  |  44 +--
 src/radeon_exa_shared.c |   2 +-
 src/radeon_exa_shared.h |   3 +-
 src/radeon_glamor.c |  57 ++--
 src/radeon_glamor.h |  28 +-
 src/radeon_glamor_wrappers.c|  27 +-
 src/radeon_kms.c| 202 ++
 src/radeon_present.c|   4 +-
 src/radeon_textured_videofuncs.c|  24 +-
 25 files changed, 705 insertions(+), 674 deletions(-)

-- 
2.18.0

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Re: [PATCH] drm/amdgpu: Add CLK IP base offset

[Quan, Evan]

Reviewed-by: Evan Quan 


From: amd-gfx  on behalf of Rex Zhu 

Sent: Thursday, July 5, 2018 4:39:44 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhu, Rex
Subject: [PATCH] drm/amdgpu: Add CLK IP base offset

so we can read/write the registers in CLK domain
through RREG32/WREG32_SOC15

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  | 1 +
 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 44bcc3e..8eaba0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1401,6 +1401,7 @@ enum amd_hw_ip_block_type {
 PWR_HWIP,
 NBIF_HWIP,
 THM_HWIP,
+   CLK_HWIP,
 MAX_HWIP
 };

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 
b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index 45aafca..c5c9b2b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -51,6 +51,7 @@ int vega10_reg_base_init(struct amdgpu_device *adev)
 adev->reg_offset[PWR_HWIP][i] = (uint32_t 
*)(&(PWR_BASE.instance[i]));
 adev->reg_offset[NBIF_HWIP][i] = (uint32_t 
*)(&(NBIF_BASE.instance[i]));
 adev->reg_offset[THM_HWIP][i] = (uint32_t 
*)(&(THM_BASE.instance[i]));
+   adev->reg_offset[CLK_HWIP][i] = (uint32_t 
*)(&(CLK_BASE.instance[i]));
 }
 return 0;
 }
--
1.9.1

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[PATCH 10/10] drm/amd/powerplay: no need to mask workable gfxoff feature for vega12

[Evan Quan]

Gfxoff feature for vega12 is workable. So, there is no need to
mask it any more.

Change-Id: I7e4d05c5c0acc2aa2b077eaaaf6f13589c87114b
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
index 9b675d9bd162..8994aa5c8cf8 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c
@@ -147,10 +147,10 @@ int hwmgr_early_init(struct pp_hwmgr *hwmgr)
smu7_init_function_pointers(hwmgr);
break;
case AMDGPU_FAMILY_AI:
-   hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
switch (hwmgr->chip_id) {
case CHIP_VEGA10:
case CHIP_VEGA20:
+   hwmgr->feature_mask &= ~PP_GFXOFF_MASK;
hwmgr->smumgr_funcs = _smu_funcs;
vega10_hwmgr_init(hwmgr);
break;
-- 
2.18.0

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[PATCH 09/10] drm/amd/powerplay: add vega12 SMU gfxoff support

[Evan Quan]

Export apis for enabling/disabling SMU gfxoff support.

Change-Id: Idcea1db9f3dbe15edda1b76e1ff05435865af2a1
Signed-off-by: Evan Quan 
---
 .../drm/amd/powerplay/hwmgr/vega12_hwmgr.c| 19 +++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
index 57492878874f..8efa983c41de 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega12_hwmgr.c
@@ -2329,6 +2329,24 @@ static int vega12_get_thermal_temperature_range(struct 
pp_hwmgr *hwmgr,
return 0;
 }
 
+static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
+{
+   return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff);
+}
+
+static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr)
+{
+   return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff);
+}
+
+static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
+{
+   if (enable)
+   return vega12_enable_gfx_off(hwmgr);
+   else
+   return vega12_disable_gfx_off(hwmgr);
+}
+
 static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
.backend_init = vega12_hwmgr_backend_init,
.backend_fini = vega12_hwmgr_backend_fini,
@@ -2378,6 +2396,7 @@ static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
.get_thermal_temperature_range = vega12_get_thermal_temperature_range,
.register_irq_handlers = smu9_register_irq_handlers,
.start_thermal_controller = vega12_start_thermal_controller,
+   .gfx_off_control = vega12_gfx_off_control,
 };
 
 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
-- 
2.18.0

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[PATCH 08/10] drm/amdgpu: use the accessible target rlc safe mode Apis directly

[Evan Quan]

No need to do double dereference to reach the Apis. They are
accessible directly.

Change-Id: I4b810c5e1981e0810df36a701b20edaf1f6af207
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index cb7f2efa9882..9679bdc0ea2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3618,7 +3618,7 @@ static void gfx_v9_0_update_3d_clock_gating(struct 
amdgpu_device *adev,
 {
uint32_t data, def;
 
-   adev->gfx.rlc.funcs->enter_safe_mode(adev);
+   gfx_v9_0_enter_rlc_safe_mode(adev);
 
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
@@ -3658,7 +3658,7 @@ static void gfx_v9_0_update_3d_clock_gating(struct 
amdgpu_device *adev,
WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
}
 
-   adev->gfx.rlc.funcs->exit_safe_mode(adev);
+   gfx_v9_0_exit_rlc_safe_mode(adev);
 }
 
 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device 
*adev,
@@ -3666,7 +3666,7 @@ static void 
gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
 {
uint32_t def, data;
 
-   adev->gfx.rlc.funcs->enter_safe_mode(adev);
+   gfx_v9_0_enter_rlc_safe_mode(adev);
 
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
@@ -3706,7 +3706,7 @@ static void 
gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
}
 
-   adev->gfx.rlc.funcs->exit_safe_mode(adev);
+   gfx_v9_0_exit_rlc_safe_mode(adev);
 }
 
 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
-- 
2.18.0

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[PATCH 07/10] drm/amdgpu: reduce the idle period that RLC has to wait before request CGCG

[Evan Quan]

Gfxoff feature may depends on the CGCG(on vega12, that's the case). This
change will help to enable gfxoff feature more frequently.

Change-Id: I021577e331b7beb19796bd6f5465b867f6038974
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ee537423af11..cb7f2efa9882 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3629,9 +3629,11 @@ static void gfx_v9_0_update_3d_clock_gating(struct 
amdgpu_device *adev,
/* update CGCG and CGLS override bits */
if (def != data)
WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
-   /* enable 3Dcgcg FSM(0x0020003f) */
+
+   /* enable 3Dcgcg FSM(0x363f) */
def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
-   data = (0x2000 << 
RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
+
+   data = (0x36 << 
RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
data |= (0x000F << 
RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
@@ -3678,9 +3680,10 @@ static void 
gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
if (def != data)
WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
 
-   /* enable cgcg FSM(0x0020003F) */
+   /* enable cgcg FSM(0x363F) */
def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
-   data = (0x2000 << 
RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
+
+   data = (0x36 << 
RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
data |= (0x000F << 
RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
-- 
2.18.0

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[PATCH 05/10] drm/amdgpu: drop mmRLC_PG_CNTL clear

[Evan Quan]

This may break gfxoff support since this register will
be set by smc fw(for vega12, that's the case).

Change-Id: Id3108c63634a2f941289021bfbd78588c0f6c4d6
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 8d870d4f8414..3a75641a071d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2290,9 +2290,6 @@ static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
/* disable CG */
WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
 
-   /* disable PG */
-   WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
-
gfx_v9_0_rlc_reset(adev);
 
gfx_v9_0_init_pg(adev);
-- 
2.18.0

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[PATCH 06/10] drm/amdgpu: no touch for the reserved bit of RLC_CGTT_MGCG_OVERRIDE

[Evan Quan]

On vega12, the bit0 of RLC_CGTT_MGCG_OVERRIDE is reserved.

Change-Id: I9042a8c89db16f220da5a589264937b51870c187
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 +++
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 3a75641a071d..ee537423af11 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3551,8 +3551,11 @@ static void 
gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 1 - RLC_CGTT_MGCG_OVERRIDE */
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
-   data &= ~(RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
- RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
+
+   if (adev->asic_type != CHIP_VEGA12)
+   data &= 
~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
+
+   data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
 
@@ -3582,11 +3585,15 @@ static void 
gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev
} else {
/* 1 - MGCG_OVERRIDE */
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
-   data |= (RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK |
-RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
+
+   if (adev->asic_type != CHIP_VEGA12)
+   data |= 
RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
+
+   data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
+
if (def != data)
WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
 
-- 
2.18.0

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[PATCH 04/10] drm/amdgpu: correct direct reg list length for v2_0 rlc

[Evan Quan]

For v2_0 rlc, rlc save restore list also needs to be initialized.
However, there is no reg_list_format_direct_reg_list_length
member(v2_1 spefic) for it.

Change-Id: I29bfe441c4f4b4726a7dd61b315347fea057163b
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 8d895afa6c69..8d870d4f8414 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -42,6 +42,7 @@
 #define GFX9_MEC_HPD_SIZE 2048
 #define RLCG_UCODE_LOADING_START_ADDRESS 0x2000L
 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0xL
+#define GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH 34
 
 #define mmPWR_MISC_CNTL_STATUS 0x0183
 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX0
@@ -1927,7 +1928,7 @@ static int gfx_v9_1_init_rlc_save_restore_list(struct 
amdgpu_device *adev)
/* setup unique_indirect_regs array and indirect_start_offsets array */
unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
gfx_v9_1_parse_ind_reg_list(register_list_format,
-   
adev->gfx.rlc.reg_list_format_direct_reg_list_length,
+   GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH,
adev->gfx.rlc.reg_list_format_size_bytes >> 
2,
unique_indirect_regs,
unique_indirect_reg_count,
@@ -1952,7 +1953,7 @@ static int gfx_v9_1_init_rlc_save_restore_list(struct 
amdgpu_device *adev)
adev->gfx.rlc.reg_list_format_start);
 
/* direct register portion */
-   for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; 
i++)
+   for (i = 0; i < GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH; i++)
WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
register_list_format[i]);
 
-- 
2.18.0

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[PATCH 02/10] drm/amdgpu: init CSIB regardless of rlc version and pg status

[Evan Quan]

CSIB init has no relation with rlc version and pg status. It should be
needed regardless of them.

Change-Id: Iccd12e1015f41c7e2bc3fe02472dc979015514d4
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 65cc30766658..2f6ac255203f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2182,6 +2182,8 @@ static void 
gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *ad
 
 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
 {
+   gfx_v9_0_init_csb(adev);
+
if (!adev->gfx.rlc.is_rlc_v2_1)
return;
 
@@ -2191,7 +2193,6 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
  AMD_PG_SUPPORT_CP |
  AMD_PG_SUPPORT_GDS |
  AMD_PG_SUPPORT_RLC_SMU_HS)) {
-   gfx_v9_0_init_csb(adev);
gfx_v9_1_init_rlc_save_restore_list(adev);
gfx_v9_0_enable_save_restore_machine(adev);
 
-- 
2.18.0

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[PATCH 03/10] drm/amdgpu: init rlc save restore as long as the lists exist

[Evan Quan]

It does not have to be rlc v2_1 and pg enabled. For rlc v2_0, rlc
save restore is also needed. And pg support is definitely not a
must for rlc save restore.

Change-Id: I85c0e3525ca7fb385c3d0b9e5abc13708c91e795
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2f6ac255203f..8d895afa6c69 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2184,8 +2184,13 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
 {
gfx_v9_0_init_csb(adev);
 
-   if (!adev->gfx.rlc.is_rlc_v2_1)
-   return;
+   /* init rlc save restore as long as the lists exist */
+   if (adev->gfx.rlc.reg_list_format_size_bytes &&
+   adev->gfx.rlc.reg_list_size_bytes &&
+   adev->gfx.rlc.reg_restore_list_size) {
+   gfx_v9_1_init_rlc_save_restore_list(adev);
+   gfx_v9_0_enable_save_restore_machine(adev);
+   }
 
if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
  AMD_PG_SUPPORT_GFX_SMG |
@@ -2193,9 +2198,6 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
  AMD_PG_SUPPORT_CP |
  AMD_PG_SUPPORT_GDS |
  AMD_PG_SUPPORT_RLC_SMU_HS)) {
-   gfx_v9_1_init_rlc_save_restore_list(adev);
-   gfx_v9_0_enable_save_restore_machine(adev);
-
WREG32(mmRLC_JUMP_TABLE_RESTORE,
   adev->gfx.rlc.cp_table_gpu_addr >> 8);
gfx_v9_0_init_gfx_power_gating(adev);
-- 
2.18.0

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[PATCH 01/10] drm/amdgpu: pin the csb buffer on hw init

[Evan Quan]

Without this pin, the csb buffer will be filled with inconsistent
data after S3 resume. And that will causes gfx hang on gfxoff
exit since this csb will be executed then.

Change-Id: I1ae1f2eed096eaba5f601cf2a3e2650c8e583dc9
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 40 +++
 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index ac46eabe3bcd..65cc30766658 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -943,6 +943,7 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
dst_ptr = adev->gfx.rlc.cs_ptr;
gfx_v9_0_get_csb_buffer(adev, dst_ptr);
amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
+   amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
}
 
@@ -971,6 +972,39 @@ static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
return 0;
 }
 
+static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
+{
+   uint64_t gpu_addr;
+   int r;
+
+   r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
+   if (unlikely(r != 0))
+   return r;
+
+   r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
+   AMDGPU_GEM_DOMAIN_VRAM, _addr);
+   if (!r)
+   adev->gfx.rlc.clear_state_gpu_addr = gpu_addr;
+
+   amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+
+   return r;
+}
+
+static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
+{
+   int r;
+
+   if (!adev->gfx.rlc.clear_state_obj)
+   return;
+
+   r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
+   if (likely(r == 0)) {
+   amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
+   amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
+   }
+}
+
 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
 {
amdgpu_bo_free_kernel(>gfx.mec.hpd_eop_obj, NULL, NULL);
@@ -3116,6 +3150,10 @@ static int gfx_v9_0_hw_init(void *handle)
 
gfx_v9_0_gpu_init(adev);
 
+   r = gfx_v9_0_csb_vram_pin(adev);
+   if (r)
+   return r;
+
r = gfx_v9_0_rlc_resume(adev);
if (r)
return r;
@@ -3224,6 +3262,8 @@ static int gfx_v9_0_hw_fini(void *handle)
gfx_v9_0_cp_enable(adev, false);
gfx_v9_0_rlc_stop(adev);
 
+   gfx_v9_0_csb_vram_unpin(adev);
+
return 0;
 }
 
-- 
2.18.0

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[PATCH] drm/amdgpu: Add CLK IP base offset

[Rex Zhu]

so we can read/write the registers in CLK domain
through RREG32/WREG32_SOC15

Signed-off-by: Rex Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h  | 1 +
 drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 44bcc3e..8eaba0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1401,6 +1401,7 @@ enum amd_hw_ip_block_type {
PWR_HWIP,
NBIF_HWIP,
THM_HWIP,
+   CLK_HWIP,
MAX_HWIP
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c 
b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
index 45aafca..c5c9b2b 100644
--- a/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_reg_init.c
@@ -51,6 +51,7 @@ int vega10_reg_base_init(struct amdgpu_device *adev)
adev->reg_offset[PWR_HWIP][i] = (uint32_t 
*)(&(PWR_BASE.instance[i]));
adev->reg_offset[NBIF_HWIP][i] = (uint32_t 
*)(&(NBIF_BASE.instance[i]));
adev->reg_offset[THM_HWIP][i] = (uint32_t 
*)(&(THM_BASE.instance[i]));
+   adev->reg_offset[CLK_HWIP][i] = (uint32_t 
*)(&(CLK_BASE.instance[i]));
}
return 0;
 }
-- 
1.9.1

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Re: [PATCH v3] drm/amdgpu: update documentation for amdgpu_drv.c

[Christian König]

Am 04.07.2018 um 20:20 schrieb Sonny Jiang:

[SNIP]
  
+/**

+ * DOC: lockup_timeout (int)
+ * Set GPU scheduler timeout value in ms. It must be > 0.  The default is 
1.
+ */
  MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms > 0 (default 
1)");
  module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444);


Actually the description here is incorrect, a value of 0 is handled as 
infinite timeout IIRC. Please fix while at it.


Apart from that the patch is Acked-by: Christian König 
.


Christian.
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Re: [PATCH v2 1/2] drm/amdgpu: Add support for logging process info in amdgpu_vm.

[Christian König]

Am 04.07.2018 um 17:04 schrieb Andrey Grodzovsky:

Add process and thread names and pids and a function to extract
this info from relevant amdgpu_vm.

v2: Add documentation and fix identation.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 21 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 14 ++
  2 files changed, 35 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 712af5c..845f73a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2942,3 +2942,24 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, 
struct drm_file *filp)
  
  	return 0;

  }
+
+/**
+ * amdgpu_vm_task_info - Extracts task info for a PASID.
+ *
+ * @dev: drm device pointer
+ * @pasid: PASID identifier for VM
+ * @task_info: task_info to fill.
+ */
+void amdgpu_vm_task_info(struct amdgpu_device *adev, unsigned int pasid,
+struct amdgpu_task_info *task_info)
+{
+   struct amdgpu_vm *vm;
+
+   spin_lock(>vm_manager.pasid_lock);
+
+   vm = idr_find(>vm_manager.pasid_idr, pasid);
+   if (vm)
+   *task_info = vm->task_info;
+
+   spin_unlock(>vm_manager.pasid_lock);
+}


As David suggested as well I would both add the 
amdgpu_vm_get_task_info() and amdgpu_vm_set_task_info() calls in this 
patch and then wire up everything in the second path.


Apart from that looks good to me,
Christian.


diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 061b99a..cd4025e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -164,6 +164,14 @@ struct amdgpu_vm_pt {
  #define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
  #define AMDGPU_VM_FAULT_ADDR(fault)  ((u64)(fault) & 0xf000ULL)
  
+

+struct amdgpu_task_info {
+   charprocess_name[TASK_COMM_LEN];
+   chartask_name[TASK_COMM_LEN];
+   pid_t   pid;
+   pid_t   tgid;
+};
+
  struct amdgpu_vm {
/* tree of virtual addresses mapped */
struct rb_root_cached   va;
@@ -215,6 +223,9 @@ struct amdgpu_vm {
  
  	/* Valid while the PD is reserved or fenced */

uint64_tpd_phys_addr;
+
+   /* Some basic info about the task */
+   struct amdgpu_task_info task_info;
  };
  
  struct amdgpu_vm_manager {

@@ -317,4 +328,7 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
  struct amdgpu_job *job);
  void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
  
+void amdgpu_vm_task_info(struct amdgpu_device *adev, unsigned int pasid,

+struct amdgpu_task_info *task_info);
+
  #endif


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Re: [PATCH 1/2] drm/amdgpu: Add support for logging process info in amdgpu_vm.

[Christian König]

Am 04.07.2018 um 16:22 schrieb Andrey Grodzovsky:



On 07/04/2018 10:17 AM, Christian König wrote:

Am 04.07.2018 um 16:10 schrieb Andrey Grodzovsky:

Add process and thread names and pids and a function to extract
this info from relevant amdgpu_vm.

Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 ++
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 14 ++
  2 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

index 8370660..8ec459e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2942,3 +2942,17 @@ int amdgpu_vm_ioctl(struct drm_device *dev, 
void *data, struct drm_file *filp)

    return 0;
  }
+


Please add some sphinx documentation here.


+void amdgpu_vm_task_info(struct amdgpu_device *adev,
+  unsigned int pasid, struct amdgpu_task_info *task_info)


What editor/settings do you use?

When I trow those lines into vim's auto-formater it comes up with the 
following:


void amdgpu_vm_task_info(struct amdgpu_device *adev, unsigned int pasid,
 struct amdgpu_task_info *task_info)


I am using eclipse with CDT, I am not very into configuring the editor 
settings so not sure.
How can I use vim to vim autoformat to fix these indentation issues ? 
Do i need to install

some extra plug-in and configure it for kernel style indentation ?


I'm using vim with linuxsty.vim. It's not much of an issue anyway.

I just want to avoid that one editor automatically changes code into one 
style while another one changes it automatically into another style.


Well, you probably know what I mean :)

Christian.



Andrey



Not an issue at all, but I would like to know where that comes from 
cause it is a repeating pattern from multiple people.


Apart from that whole set looks like a nice addition to me,
Christian.


+{
+    struct amdgpu_vm *vm;
+
+    spin_lock(>vm_manager.pasid_lock);
+
+    vm = idr_find(>vm_manager.pasid_idr, pasid);
+    if (vm)
+    *task_info = vm->task_info;
+
+    spin_unlock(>vm_manager.pasid_lock);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

index 061b99a..88a1d18 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -164,6 +164,14 @@ struct amdgpu_vm_pt {
  #define AMDGPU_VM_FAULT_PASID(fault) ((u64)(fault) >> 48)
  #define AMDGPU_VM_FAULT_ADDR(fault)  ((u64)(fault) & 
0xf000ULL)

  +
+struct amdgpu_task_info {
+    char    process_name[TASK_COMM_LEN];
+    char    task_name[TASK_COMM_LEN];
+    pid_t    pid;
+    pid_t    tgid;
+};
+
  struct amdgpu_vm {
  /* tree of virtual addresses mapped */
  struct rb_root_cached    va;
@@ -215,6 +223,9 @@ struct amdgpu_vm {
    /* Valid while the PD is reserved or fenced */
  uint64_t    pd_phys_addr;
+
+    /* Some basic info about the task */
+    struct amdgpu_task_info task_info;
  };
    struct amdgpu_vm_manager {
@@ -317,4 +328,7 @@ bool amdgpu_vm_need_pipeline_sync(struct 
amdgpu_ring *ring,

    struct amdgpu_job *job);
  void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev);
  +void amdgpu_vm_task_info(struct amdgpu_device *adev,
+  unsigned int pasid, struct amdgpu_task_info *task_info);
+
  #endif




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Re: [PATCH] drm/amdgpu: Verify root PD is mapped into kernel address space.

[Christian König]

Am 05.07.2018 um 04:09 schrieb zhoucm1:



On 2018年07月05日 03:49, Andrey Grodzovsky wrote:
Problem: When PD/PT update made by CPU root PD was not yet mapped 
causing

page fault.

Fix: Move amdgpu_bo_kmap into amdgpu_vm_bo_base_init to cover
all cases and avoid code duplication with amdgpu_vm_alloc_levels.

Link: https://bugs.freedesktop.org/show_bug.cgi?id=107065
Signed-off-by: Andrey Grodzovsky 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 47 
++

  1 file changed, 31 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

index 845f73a..f546afa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -143,25 +143,36 @@ struct amdgpu_prt_cb {
   * Initialize a bo_va_base structure and add it to the appropriate 
lists

   *
   */
-static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
+static int amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
 struct amdgpu_vm *vm,
 struct amdgpu_bo *bo)
  {
+    int r = 0;
  base->vm = vm;
  base->bo = bo;
  INIT_LIST_HEAD(>bo_list);
  INIT_LIST_HEAD(>vm_status);
    if (!bo)
-    return;
+    return r;
+
  list_add_tail(>bo_list, >va);
  +    if (vm->use_cpu_for_update && bo->tbo.type == 
ttm_bo_type_kernel) {

+    r = amdgpu_bo_kmap(bo, NULL);
+    if (r) {
+    amdgpu_bo_unref(>shadow);
+    amdgpu_bo_unref();
I feel these two lines should move out of helper function, ref/unref 
should appear in where used with pair.


Yeah agree, but there is an approach which is even cleaner I think.



Regards,
David Zhou

+    return r;
+    }
+    }
+
  if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
-    return;
+    return r;
    if (bo->preferred_domains &
  amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
-    return;
+    return r;
    /*
   * we checked all the prerequisites, but it looks like this per 
vm bo
@@ -169,6 +180,8 @@ static void amdgpu_vm_bo_base_init(struct 
amdgpu_vm_bo_base *base,

   * is validated on next vm use to avoid fault.
   * */
  list_move_tail(>vm_status, >evicted);
+
+    return r;


Here we move it into the evicted status when the placement isn't ok.

Now for PDs/PTs the caller moves it immediately into the relocated 
status to make sure that the parent entries are updated:

amdgpu_vm_bo_base_init(>base, vm, pt);
    list_move(>base.vm_status, >relocated);


And amdgpu_vm_update_directories() maps all relocated BOs anyway before 
it begins:

    list_for_each_entry(bo_base, >relocated, vm_status) {
    r = amdgpu_bo_kmap(bo_base->bo, NULL);
    if (unlikely(r))
    return r;
    }


So all we need to do is to make sure that we add the root PD to the 
relocated list as well.


Cleanest approach would probably be to move the 
"list_move(>base.vm_status, >relocated);" into 
amdgpu_vm_bo_base_init().


Regards,
Christian.


  }
    /**
@@ -525,21 +538,15 @@ static int amdgpu_vm_alloc_levels(struct 
amdgpu_device *adev,

  return r;
  }
  -    if (vm->use_cpu_for_update) {
-    r = amdgpu_bo_kmap(pt, NULL);
-    if (r) {
-    amdgpu_bo_unref(>shadow);
-    amdgpu_bo_unref();
-    return r;
-    }
-    }
-
  /* Keep a reference to the root directory to avoid
  * freeing them up in the wrong order.
  */
  pt->parent = amdgpu_bo_ref(parent->base.bo);
  -    amdgpu_vm_bo_base_init(>base, vm, pt);
+    r = amdgpu_vm_bo_base_init(>base, vm, pt);
+    if (r)
+    return r;
+
  list_move(>base.vm_status, >relocated);
  }
  @@ -1992,12 +1999,17 @@ struct amdgpu_bo_va 
*amdgpu_vm_bo_add(struct amdgpu_device *adev,

    struct amdgpu_bo *bo)
  {
  struct amdgpu_bo_va *bo_va;
+    int r;
    bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
  if (bo_va == NULL) {
  return NULL;
  }
-    amdgpu_vm_bo_base_init(_va->base, vm, bo);
+
+    if ((r = amdgpu_vm_bo_base_init(_va->base, vm, bo))) {
+    WARN_ONCE(1,"r = %d\n", r);
+    return NULL;
+    }
    bo_va->ref_count = 1;
  INIT_LIST_HEAD(_va->valids);
@@ -2613,7 +2625,10 @@ int amdgpu_vm_init(struct amdgpu_device *adev, 
struct amdgpu_vm *vm,

  if (r)
  goto error_unreserve;
  -    amdgpu_vm_bo_base_init(>root.base, vm, root);
+    r = amdgpu_vm_bo_base_init(>root.base, vm, root);
+    if (r)
+    goto error_unreserve;
+
  amdgpu_bo_unreserve(vm->root.base.bo);
    if (pasid) {




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