RE: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
This series patches seems to make AGP aperture allowed to access any system memory (16GB) bypass GPU VM protection. If someone made a wrong logic requesting an illegal address which occasionally was located inside AGP aperture, but without any VM protection, the illegal address would be finally translated into a system memory address; if GPU read/wrote such system memory address, the system memory address might belong to kernel or any user application, the r/w operation would result in any unpredictable issue. The most important is that such kind of issue is so hard to be addressed. Is it worth doing this, but exposing risk? Regards, Jack -Original Message- From: amd-gfx On Behalf Of Felix Kuehling Sent: Tuesday, August 28, 2018 3:03 AM To: Christian König ; amd-gfx@lists.freedesktop.org; Koenig, Christian Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9 The point of this series seems to be to allow access to small system memory BOs (one page) without a GART mapping. I'm guessing that reduces pressure on the GART and removes the need for HDP and TLB flushes. Why does Patch 10 only enable that on GFXv9? Is there less benefit on older chips? Is this related to your recent changes to allow page tables in system memory? See my replies to patch 6 and 8. Other than that, the series is Acked-by: Felix Kuehling Regards, Felix On 2018-08-27 12:53 PM, Christian König wrote: > Only use the lower address space on GMC9 for the system domain. > Otherwise we would need to sign extend GMC addresses. > > Signed-off-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index e44b5191735d..d982956c8329 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) > if (r) > return r; > > - /* Set the internal MC address mask > - * This is the max address of the GPU's > - * internal address space. > + /* Use only the lower range for the internal MC address mask. This is > + * the max address of the GPU's internal address space. >*/ > - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ > + adev->gmc.mc_mask = 0x7fffULL; > > /* set DMA mask + need_dma32 flags. >* PCIE - can handle 44-bits. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
On 2018年08月28日 03:03, Felix Kuehling wrote: The point of this series seems to be to allow access to small system memory BOs (one page) without a GART mapping. I'm guessing that reduces pressure on the GART and removes the need for HDP and TLB flushes. I think if adding these explain/reason to comments are better to enable AGP apperture. If that's true, it's really a clever idea. Regards, David Zhou Why does Patch 10 only enable that on GFXv9? Is there less benefit on older chips? Is this related to your recent changes to allow page tables in system memory? See my replies to patch 6 and 8. Other than that, the series is Acked-by: Felix Kuehling Regards, Felix On 2018-08-27 12:53 PM, Christian König wrote: Only use the lower address space on GMC9 for the system domain. Otherwise we would need to sign extend GMC addresses. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e44b5191735d..d982956c8329 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; - /* Set the internal MC address mask -* This is the max address of the GPU's -* internal address space. + /* Use only the lower range for the internal MC address mask. This is +* the max address of the GPU's internal address space. */ - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ + adev->gmc.mc_mask = 0x7fffULL; /* set DMA mask + need_dma32 flags. * PCIE - can handle 44-bits. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: remove extra newline when printing VM faults
On 08/27/2018 10:04 PM, Alex Deucher wrote: On Mon, Aug 27, 2018 at 9:45 AM Christian König wrote: Looks like a copy error to me. Signed-off-by: Christian König Reviewed-by: Alex Deucher Reviewed-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 66abfcf87ad0..ad40acb236bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -265,7 +265,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, amdgpu_vm_get_task_info(adev, entry->pasid, _info); dev_err(adev->dev, - "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d\n)\n", + "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n", entry->vmid_src ? "mmhub" : "gfxhub", entry->src_id, entry->ring_id, entry->vmid, entry->pasid, task_info.process_name, task_info.tgid, -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 09/10] drm/amdgpu: use the AGP aperture for system memory access
On 08/28/2018 12:53 AM, Christian König wrote:
Start to use the old AGP aperture for system memory access.
Signed-off-by: Christian König
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 24 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 9
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 21 ++
4 files changed, 46 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index eed5352f3136..54d353951e21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -79,6 +79,30 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
return pd_addr;
}
+/**
+ * amdgpu_gmc_agp_addr - return the address in the AGP address space
+ *
+ * @tbo: TTM BO which needs the address, must be in GTT domain
+ *
+ * Tries to figure out how to access the BO through the AGP aperture. Returns
+ * AMDGPU_BO_INVALID_OFFSET if that is not possible.
+ */
+uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *tbo)
+{
+ struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
+ struct ttm_dma_tt *ttm;
+
+ if (tbo->num_pages != 1 || !tbo->ttm ||
+ tbo->ttm->caching_state == tt_cached)
+ return AMDGPU_BO_INVALID_OFFSET;
+
+ ttm = container_of(tbo->ttm, struct ttm_dma_tt, ttm);
+ if (ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
+ return AMDGPU_BO_INVALID_OFFSET;
+
+ return adev->gmc.agp_start + ttm->dma_address[0];
+}
+
/**
* amdgpu_gmc_vram_location - try to find VRAM location
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 163110fe375d..6e8432fd3309 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -137,6 +137,7 @@ static inline bool amdgpu_gmc_vram_full_visible(struct
amdgpu_gmc *gmc)
void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
uint64_t *addr, uint64_t *flags);
uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
+uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *tbo);
void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc
*mc,
u64 base);
void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index c2539f6821c0..deaea11eb39a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -132,6 +132,15 @@ static int amdgpu_gtt_mgr_alloc(struct
ttm_mem_type_manager *man,
else
lpfn = adev->gart.num_cpu_pages;
+ if (fpfn == 0 && lpfn == adev->gart.num_cpu_pages) {
+ uint64_t addr = amdgpu_gmc_agp_addr(tbo);
+
+ if (addr != AMDGPU_BO_INVALID_OFFSET) {
+ mem->start = addr >> PAGE_SHIFT;
+ return 0;
+ }
+ }
+
mode = DRM_MM_INSERT_BEST;
if (place && place->flags & TTM_PL_FLAG_TOPDOWN)
mode = DRM_MM_INSERT_HIGH;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index d9f3201c9e5c..281611f6bcd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1103,15 +1103,18 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
if (unlikely(r))
return r;
- /* compute PTE flags for this buffer object */
- flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, );
-
- /* Bind pages */
- gtt->offset = ((u64)tmp.start << PAGE_SHIFT) - adev->gmc.gart_start;
- r = amdgpu_ttm_gart_bind(adev, bo, flags);
- if (unlikely(r)) {
- ttm_bo_mem_put(bo, );
- return r;
+ if (amdgpu_gtt_mgr_has_gart_addr()) {
+ /* compute PTE flags for this buffer object */
+ flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, );
+
+ /* Bind pages */
+ gtt->offset = ((u64)tmp.start << PAGE_SHIFT) -
+ adev->gmc.gart_start;
+ r = amdgpu_ttm_gart_bind(adev, bo, flags);
+ if (unlikely(r)) {
+ ttm_bo_mem_put(bo, );
+ return r;
+ }
}
ttm_bo_mem_put(bo, >mem);
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Re: [PATCH 06/10] drm/amdgpu: add amdgpu_gmc_agp_location
On 08/28/2018 12:53 AM, Christian König wrote:
Helper to figure out the location of the AGP BAR.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 42 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 5 +++
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 4331a0e25cdc..eed5352f3136 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -141,3 +141,45 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
mc->gart_size >> 20, mc->gart_start, mc->gart_end);
}
+
+/**
+ * amdgpu_gmc_agp_location - try to find AGP location
+ * @adev: amdgpu device structure holding all necessary informations
+ * @mc: memory controller structure holding memory informations
+ *
+ * Function will place try to fina a place for the AGP BAR in the MC address
+ * space.
+ *
+ * AGP BAR will be assigned the largest available hole in the address space.
+ */
+void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
+{
+ const uint64_t sixteen_gb = 1ULL << 34;
+ u64 size_af, size_bf;
+
+ if (mc->vram_start > mc->gart_start) {
+ size_bf = mc->vram_start - mc->gart_end + 1;
+ size_af = mc->mc_mask - mc->vram_end;
+ } else {
+ size_bf = mc->vram_start;
+ size_af = mc->mc_mask - mc->gart_end;
+ }
+
+ size_bf &= ~(sixteen_gb - 1);
+ size_af &= ~(sixteen_gb - 1);
+
+ if (size_bf > size_af) {
+ mc->agp_start = mc->vram_start > mc->gart_start ?
+ mc->gart_start : 0;
Here looks mc->gart_end?
+ mc->agp_size = size_bf;
+ } else {
+ mc->agp_start = (mc->vram_start > mc->gart_start ?
+ mc->vram_end : mc->gart_end) + 1,
+ mc->agp_size = size_af;
+ }
+
+ mc->agp_start = ALIGN(mc->agp_start, sixteen_gb);
still needs mc->apg_start + 1 for alignment?
+ mc->agp_end = mc->agp_start + mc->agp_size - 1;
+ dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",
+ mc->agp_size >> 20, mc->agp_start, mc->agp_end);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 72fcc9338f5e..163110fe375d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -81,6 +81,9 @@ struct amdgpu_gmc {
* about vram size near mc fb location */
u64 mc_vram_size;
u64 visible_vram_size;
+ u64 agp_size;
+ u64 agp_start;
+ u64 agp_end;
u64 gart_size;
u64 gart_start;
u64 gart_end;
@@ -138,5 +141,7 @@ void amdgpu_gmc_vram_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc,
u64 base);
void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc);
+void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
+struct amdgpu_gmc *mc);
#endif
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Re: [PATCH 08/10] drm/amdgpu: distinct between allocated GART space and GMC addr
On 08/28/2018 12:53 AM, Christian König wrote:
Most of the time we only need to know if the BO has a valid GMC addr.
Signed-off-by: Christian König
good to see this cleanup :)
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 --
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 13 +
3 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 5ddd4e87480b..b5f20b42439e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1362,8 +1362,6 @@ void amdgpu_bo_fence(struct amdgpu_bo *bo, struct
dma_fence *fence,
u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
{
WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
- WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
-!amdgpu_gtt_mgr_has_gart_addr(>tbo.mem));
WARN_ON_ONCE(!ww_mutex_is_locked(>tbo.resv->lock) &&
!bo->pin_count);
WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 18945dd6982d..37c79ae3574e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -200,7 +200,7 @@ static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo
*bo)
static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
{
switch (bo->tbo.mem.mem_type) {
- case TTM_PL_TT: return amdgpu_gtt_mgr_has_gart_addr(>tbo.mem);
+ case TTM_PL_TT: return bo->tbo.mem.start != AMDGPU_BO_INVALID_OFFSET;
case TTM_PL_VRAM: return true;
default: return false;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 5cadf4f1ee2c..d9f3201c9e5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -345,7 +345,7 @@ static uint64_t amdgpu_mm_node_addr(struct
ttm_buffer_object *bo,
{
uint64_t addr = 0;
- if (mem->mem_type != TTM_PL_TT || amdgpu_gtt_mgr_has_gart_addr(mem)) {
+ if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
addr = mm_node->start << PAGE_SHIFT;
addr += bo->bdev->man[mem->mem_type].gpu_offset;
}
@@ -433,8 +433,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
/* Map only what needs to be accessed. Map src to window 0 and
* dst to window 1
*/
- if (src->mem->mem_type == TTM_PL_TT &&
- !amdgpu_gtt_mgr_has_gart_addr(src->mem)) {
+ if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
r = amdgpu_map_buffer(src->bo, src->mem,
PFN_UP(cur_size + src_page_offset),
src_node_start, 0, ring,
@@ -447,8 +446,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
from += src_page_offset;
}
- if (dst->mem->mem_type == TTM_PL_TT &&
- !amdgpu_gtt_mgr_has_gart_addr(dst->mem)) {
+ if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
r = amdgpu_map_buffer(dst->bo, dst->mem,
PFN_UP(cur_size + dst_page_offset),
dst_node_start, 1, ring,
@@ -1086,11 +1084,10 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
uint64_t flags;
int r;
- if (bo->mem.mem_type != TTM_PL_TT ||
- amdgpu_gtt_mgr_has_gart_addr(>mem))
+ if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
return 0;
- /* allocate GTT space */
+ /* allocate GART space */
tmp = bo->mem;
tmp.mm_node = NULL;
placement.num_placement = 1;
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Re: [PATCH 07/10] drm/amdgpu: stop using gart_start as offset for the GTT domain
On 08/28/2018 03:07 AM, Alex Deucher wrote:
On Mon, Aug 27, 2018 at 12:56 PM Christian König
wrote:
Further separate GART and GTT domain.
Signed-off-by: Christian König
Reviewed-by: Alex Deucher
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 +++---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index da7b1b92d9cf..c2539f6821c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -143,7 +143,8 @@ static int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager
*man,
spin_unlock(>lock);
if (!r)
- mem->start = node->node.start;
+ mem->start = node->node.start +
+ (adev->gmc.gart_start >> PAGE_SHIFT);
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2f304f9dd543..5cadf4f1ee2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -188,7 +188,7 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev,
uint32_t type,
case TTM_PL_TT:
/* GTT memory */
man->func = _gtt_mgr_func;
- man->gpu_offset = adev->gmc.gart_start;
+ man->gpu_offset = 0;
man->available_caching = TTM_PL_MASK_CACHING;
man->default_caching = TTM_PL_FLAG_CACHED;
man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
@@ -1062,7 +1062,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
/* bind pages into GART page tables */
- gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
+ gtt->offset = ((u64)bo_mem->start << PAGE_SHIFT) - adev->gmc.gart_start;
r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
ttm->pages, gtt->ttm.dma_address, flags);
@@ -1110,7 +1110,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, );
/* Bind pages */
- gtt->offset = (u64)tmp.start << PAGE_SHIFT;
+ gtt->offset = ((u64)tmp.start << PAGE_SHIFT) - adev->gmc.gart_start;
r = amdgpu_ttm_gart_bind(adev, bo, flags);
if (unlikely(r)) {
ttm_bo_mem_put(bo, );
--
2.17.1
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Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
On 08/28/2018 09:56 AM, Zhang, Jerry (Junwei) wrote: On 08/28/2018 12:53 AM, Christian König wrote: Only use the lower address space on GMC9 for the system domain. Otherwise we would need to sign extend GMC addresses. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e44b5191735d..d982956c8329 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; -/* Set the internal MC address mask - * This is the max address of the GPU's - * internal address space. +/* Use only the lower range for the internal MC address mask. This is + * the max address of the GPU's internal address space. */ -adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ +adev->gmc.mc_mask = 0x7fffULL; do we need to update vm_size as 128T at the same time? Likely no, since we use that for system domain only. BTW, how do we decide it's size limitation. looks we always use that less than 40bit? Jerry Jerry /* set DMA mask + need_dma32 flags. * PCIE - can handle 44-bits. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 05/10] drm/amdgpu: put GART away from VRAM
On 08/28/2018 12:53 AM, Christian König wrote: Always try to put the GART away from where VRAM is. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 265ec6807130..4331a0e25cdc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -136,7 +136,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) (size_af < mc->gart_size)) mc->gart_start = 0; else - mc->gart_start = ALIGN(mc->vram_end + 1, 0x1ULL); + mc->gart_start = mc->mc_mask - mc->gart_size + 1; it seems to break the VCE limitation about 4G alignment? Jerry mc->gart_end = mc->gart_start + mc->gart_size - 1; dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", mc->gart_size >> 20, mc->gart_start, mc->gart_end); ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 04/10] drm/amdgpu: use the smaller hole for GART
On 08/28/2018 03:05 AM, Alex Deucher wrote: On Mon, Aug 27, 2018 at 12:55 PM Christian König wrote: Instead of the larger one use the smaller hole in the MC address space for the GART mappings. Signed-off-by: Christian König Reviewed-by: Alex Deucher Reviewed-by: Junwei Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 8269197df8e0..265ec6807130 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -132,7 +132,8 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) mc->gart_size = max(size_bf, size_af); } - if (size_bf > size_af) + if ((size_bf >= mc->gart_size && size_bf < size_af) || + (size_af < mc->gart_size)) mc->gart_start = 0; else mc->gart_start = ALIGN(mc->vram_end + 1, 0x1ULL); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 03/10] drm/amdgpu: fix amdgpu_gmc_gart_location a little bit
On 08/28/2018 12:53 AM, Christian König wrote:
Improve the VCE limitation handling.
Signed-off-by: Christian König
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 28 -
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 72dffa3fd194..8269197df8e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -120,24 +120,22 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
mc->gart_size += adev->pm.smu_prv_buffer_size;
- size_af = adev->gmc.mc_mask - mc->vram_end;
+ /* VCE doesn't like it when BOs cross a 4GB segment, so align
+* the GART base on a 4GB boundary as well.
+*/
size_bf = mc->vram_start;
- if (size_bf > size_af) {
- if (mc->gart_size > size_bf) {
- dev_warn(adev->dev, "limiting GART\n");
- mc->gart_size = size_bf;
- }
+ size_af = adev->gmc.mc_mask + 1 -
+ ALIGN(mc->vram_end + 1, 0x1ULL);
+
+ if (mc->gart_size > max(size_bf, size_af)) {
+ dev_warn(adev->dev, "limiting GART\n");
+ mc->gart_size = max(size_bf, size_af);
+ }
+
+ if (size_bf > size_af)
mc->gart_start = 0;
- } else {
- if (mc->gart_size > size_af) {
- dev_warn(adev->dev, "limiting GART\n");
- mc->gart_size = size_af;
- }
- /* VCE doesn't like it when BOs cross a 4GB segment, so align
-* the GART base on a 4GB boundary as well.
-*/
+ else
mc->gart_start = ALIGN(mc->vram_end + 1, 0x1ULL);
- }
mc->gart_end = mc->gart_start + mc->gart_size - 1;
dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
mc->gart_size >> 20, mc->gart_start, mc->gart_end);
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Re: [PATCH 02/10] drm/amdgpu: move amdgpu_device_(vram|gtt)_location
On 08/28/2018 02:59 AM, Alex Deucher wrote:
On Mon, Aug 27, 2018 at 12:56 PM Christian König
wrote:
Move that into amdgpu_gmc.c since we are really deadling with GMC
address space here.
Signed-off-by: Christian König
Reviewed-by: Alex Deucher
Reviewed-by: Junwei Zhang
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 --
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 65 --
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c| 64 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h| 4 ++
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 +-
8 files changed, 76 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 340e40d03d54..09bdedfc91c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1166,10 +1166,6 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev);
void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
u64 num_vis_bytes);
-void amdgpu_device_vram_location(struct amdgpu_device *adev,
-struct amdgpu_gmc *mc, u64 base);
-void amdgpu_device_gart_location(struct amdgpu_device *adev,
-struct amdgpu_gmc *mc);
int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
const u32 *registers,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9f5e4be76d5e..0afc5e599683 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -651,71 +651,6 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32
wb)
__clear_bit(wb, adev->wb.used);
}
-/**
- * amdgpu_device_vram_location - try to find VRAM location
- *
- * @adev: amdgpu device structure holding all necessary informations
- * @mc: memory controller structure holding memory informations
- * @base: base address at which to put VRAM
- *
- * Function will try to place VRAM at base address provided
- * as parameter.
- */
-void amdgpu_device_vram_location(struct amdgpu_device *adev,
-struct amdgpu_gmc *mc, u64 base)
-{
- uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
-
- mc->vram_start = base;
- mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
- if (limit && limit < mc->real_vram_size)
- mc->real_vram_size = limit;
- dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
- mc->mc_vram_size >> 20, mc->vram_start,
- mc->vram_end, mc->real_vram_size >> 20);
-}
-
-/**
- * amdgpu_device_gart_location - try to find GART location
- *
- * @adev: amdgpu device structure holding all necessary informations
- * @mc: memory controller structure holding memory informations
- *
- * Function will place try to place GART before or after VRAM.
- *
- * If GART size is bigger than space left then we ajust GART size.
- * Thus function will never fails.
- */
-void amdgpu_device_gart_location(struct amdgpu_device *adev,
-struct amdgpu_gmc *mc)
-{
- u64 size_af, size_bf;
-
- mc->gart_size += adev->pm.smu_prv_buffer_size;
-
- size_af = adev->gmc.mc_mask - mc->vram_end;
- size_bf = mc->vram_start;
- if (size_bf > size_af) {
- if (mc->gart_size > size_bf) {
- dev_warn(adev->dev, "limiting GART\n");
- mc->gart_size = size_bf;
- }
- mc->gart_start = 0;
- } else {
- if (mc->gart_size > size_af) {
- dev_warn(adev->dev, "limiting GART\n");
- mc->gart_size = size_af;
- }
- /* VCE doesn't like it when BOs cross a 4GB segment, so align
-* the GART base on a 4GB boundary as well.
-*/
- mc->gart_start = ALIGN(mc->vram_end + 1, 0x1ULL);
- }
- mc->gart_end = mc->gart_start + mc->gart_size - 1;
- dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
- mc->gart_size >> 20, mc->gart_start, mc->gart_end);
-}
-
/**
* amdgpu_device_resize_fb_bar - try to resize FB BAR
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index a249931ef512..72dffa3fd194 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -78,3 +78,67 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
}
return pd_addr;
}
+
+/**
+ *
Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
On 08/28/2018 12:53 AM, Christian König wrote: Only use the lower address space on GMC9 for the system domain. Otherwise we would need to sign extend GMC addresses. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e44b5191735d..d982956c8329 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; - /* Set the internal MC address mask -* This is the max address of the GPU's -* internal address space. + /* Use only the lower range for the internal MC address mask. This is +* the max address of the GPU's internal address space. */ - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ + adev->gmc.mc_mask = 0x7fffULL; do we need to update vm_size as 128T at the same time? Jerry /* set DMA mask + need_dma32 flags. * PCIE - can handle 44-bits. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 0/4] drm/dp_mst: Add DP MST debugfs nodes for all drivers
This is the next version of my patch series for teaching DRM how to automatically create debugfs nodes for drivers with MST topologies. This was originally intended just for nouveau, but has since been expanded to all DRM drivers. Cc: Maarten Lankhorst Cc: Daniel Stone Lyude Paul (4): drm/debugfs: Add support for dynamic debugfs initialization drm/dp_mst: Pass entire connector to drm_dp_mst_topology_mgr_init() drm/dp_mst: Add dp_mst_status debugfs node for all drivers drm/i915: Remove i915_drm_dp_mst_status .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +- drivers/gpu/drm/drm_debugfs.c | 173 +- drivers/gpu/drm/drm_dp_mst_topology.c | 114 +++- drivers/gpu/drm/drm_drv.c | 3 + drivers/gpu/drm/drm_internal.h| 5 + drivers/gpu/drm/i915/i915_debugfs.c | 32 drivers/gpu/drm/i915/intel_dp.c | 2 +- drivers/gpu/drm/i915/intel_dp_mst.c | 6 +- drivers/gpu/drm/i915/intel_drv.h | 3 +- drivers/gpu/drm/nouveau/dispnv50/disp.c | 6 +- drivers/gpu/drm/radeon/radeon_dp_mst.c| 2 +- include/drm/drm_debugfs.h | 27 +++ include/drm/drm_dp_mst_helper.h | 17 +- include/drm/drm_file.h| 4 + 14 files changed, 342 insertions(+), 54 deletions(-) -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 2/4] drm/dp_mst: Pass entire connector to drm_dp_mst_topology_mgr_init()
There's no actual reason we pass the connector ID instead of a pointer
to the connector itself, and we're going to need the entire connector
(but only temporarily) in order to name MST debugfs folders properly
since connector IDs can't be looked up until the driver has been
registered with userspace which happens after debugfs init.
So, just pass the entire drm_connector struct instead of just it's id.
Signed-off-by: Lyude Paul
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
drivers/gpu/drm/drm_dp_mst_topology.c | 8 +---
drivers/gpu/drm/i915/intel_dp.c | 2 +-
drivers/gpu/drm/i915/intel_dp_mst.c | 6 --
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
drivers/gpu/drm/nouveau/dispnv50/disp.c | 6 +++---
drivers/gpu/drm/radeon/radeon_dp_mst.c| 2 +-
include/drm/drm_dp_mst_helper.h | 3 ++-
8 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 9a300732ba37..60da7e8fcca7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -503,6 +503,6 @@ void amdgpu_dm_initialize_dp_connector(struct
amdgpu_display_manager *dm,
>dm_dp_aux.aux,
16,
4,
- aconnector->connector_id);
+ >base);
}
diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
b/drivers/gpu/drm/drm_dp_mst_topology.c
index 7780567aa669..edba17073c7a 100644
--- a/drivers/gpu/drm/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/drm_dp_mst_topology.c
@@ -3166,9 +3166,11 @@ EXPORT_SYMBOL(drm_atomic_get_mst_topology_state);
* Return 0 for success, or negative error code on failure
*/
int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr,
-struct drm_device *dev, struct drm_dp_aux *aux,
+struct drm_device *dev,
+struct drm_dp_aux *aux,
int max_dpcd_transaction_bytes,
-int max_payloads, int conn_base_id)
+int max_payloads,
+struct drm_connector *connector)
{
struct drm_dp_mst_topology_state *mst_state;
@@ -3186,7 +3188,7 @@ int drm_dp_mst_topology_mgr_init(struct
drm_dp_mst_topology_mgr *mgr,
mgr->aux = aux;
mgr->max_dpcd_transaction_bytes = max_dpcd_transaction_bytes;
mgr->max_payloads = max_payloads;
- mgr->conn_base_id = conn_base_id;
+ mgr->conn_base_id = connector->base.id;
if (max_payloads + 1 > sizeof(mgr->payload_mask) * 8 ||
max_payloads + 1 > sizeof(mgr->vcpi_mask) * 8)
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index cd0f649b57a5..3688df38dbe7 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6247,7 +6247,7 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
(port == PORT_B || port == PORT_C ||
port == PORT_D || port == PORT_F))
intel_dp_mst_encoder_init(intel_dig_port,
- intel_connector->base.base.id);
+ _connector->base);
if (!intel_edp_init_connector(intel_dp, intel_connector)) {
intel_dp_aux_fini(intel_dp);
diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
b/drivers/gpu/drm/i915/intel_dp_mst.c
index 7e3e01607643..6c07c29235df 100644
--- a/drivers/gpu/drm/i915/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/intel_dp_mst.c
@@ -583,7 +583,8 @@ intel_dp_create_fake_mst_encoders(struct intel_digital_port
*intel_dig_port)
}
int
-intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int
conn_base_id)
+intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port,
+ struct drm_connector *connector)
{
struct intel_dp *intel_dp = _dig_port->dp;
struct drm_device *dev = intel_dig_port->base.base.dev;
@@ -595,7 +596,8 @@ intel_dp_mst_encoder_init(struct intel_digital_port
*intel_dig_port, int conn_ba
/* create encoders */
intel_dp_create_fake_mst_encoders(intel_dig_port);
ret = drm_dp_mst_topology_mgr_init(_dp->mst_mgr, dev,
- _dp->aux, 16, 3, conn_base_id);
+ _dp->aux, 16, 3,
+ connector);
if (ret) {
intel_dp->can_mst = false;
return ret;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 8fc61e96754f..af7a6111ff74 100644
---
RE: [PATCH 2/2] drm/amdkfd: Release an acquired process vm
Thank you Felix. That is a great point. I will update patch.
Thanks,
Oak
-Original Message-
From: Kuehling, Felix
Sent: Monday, August 27, 2018 4:05 PM
To: Oak Zeng ; amd-gfx@lists.freedesktop.org
Cc: Zeng, Oak
Subject: Re: [PATCH 2/2] drm/amdkfd: Release an acquired process vm
On 2018-08-27 03:25 PM, Oak Zeng wrote:
> For compute vm acquired from amdgpu, vm.pasid is managed by kfd.
> Decouple pasid from such vm on process destroy to avoid duplicate
> pasid release.
>
> Signed-off-by: Oak Zeng
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 18 ++
> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 +++-
> drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 1 +
> 7 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index 2895ef5..5827734 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -166,6 +166,7 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct
> kgd_dev *kgd, void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
> struct amdgpu_vm *vm);
> void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void
> *vm);
> +void amdgpu_amdkfd_gpuvm_release_process_vm(void *vm);
> uint32_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm); int
> amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
> struct kgd_dev *kgd, uint64_t va, uint64_t size, diff --git
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> index ea79908..03a83d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> @@ -204,6 +204,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
> .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
> .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
> .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
> + .release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm,
> .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
> .set_vm_context_page_table_base = set_vm_context_page_table_base,
> .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> index 19dd665..b2b9c5f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> @@ -164,6 +164,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
> .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
> .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
> .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
> + .release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm,
> .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
> .set_vm_context_page_table_base = set_vm_context_page_table_base,
> .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
> index 1db60aa..3722bbd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
> @@ -201,6 +201,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
> .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
> .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
> .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
> + .release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm,
> .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
> .set_vm_context_page_table_base = set_vm_context_page_table_base,
> .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index d60940e..7d1cdcd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -1118,6 +1118,24 @@ void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct
> kgd_dev *kgd, void *vm)
> kfree(vm);
> }
>
> +void amdgpu_amdkfd_gpuvm_release_process_vm(void *vm) {
> +struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
> +
> +if (WARN_ON(!vm))
> +return;
> +
> +pr_debug("Releasing process vm %p\n", vm);
> +
> +/* The original pasid of amdgpu vm has already been
> +
Re: [PATCH 2/2] drm/amdkfd: Release an acquired process vm
On 2018-08-27 03:25 PM, Oak Zeng wrote:
> For compute vm acquired from amdgpu, vm.pasid is managed
> by kfd. Decouple pasid from such vm on process destroy
> to avoid duplicate pasid release.
>
> Signed-off-by: Oak Zeng
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 18 ++
> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 +++-
> drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 1 +
> 7 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index 2895ef5..5827734 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -166,6 +166,7 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev
> *kgd,
> void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
> struct amdgpu_vm *vm);
> void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm);
> +void amdgpu_amdkfd_gpuvm_release_process_vm(void *vm);
> uint32_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm);
> int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
> struct kgd_dev *kgd, uint64_t va, uint64_t size,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> index ea79908..03a83d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
> @@ -204,6 +204,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
> .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
> .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
> .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
> + .release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm,
> .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
> .set_vm_context_page_table_base = set_vm_context_page_table_base,
> .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> index 19dd665..b2b9c5f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
> @@ -164,6 +164,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
> .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
> .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
> .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
> + .release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm,
> .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
> .set_vm_context_page_table_base = set_vm_context_page_table_base,
> .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
> index 1db60aa..3722bbd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
> @@ -201,6 +201,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
> .create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
> .acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
> .destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
> + .release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm,
> .get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
> .set_vm_context_page_table_base = set_vm_context_page_table_base,
> .alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index d60940e..7d1cdcd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -1118,6 +1118,24 @@ void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct
> kgd_dev *kgd, void *vm)
> kfree(vm);
> }
>
> +void amdgpu_amdkfd_gpuvm_release_process_vm(void *vm)
> +{
> +struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
> +
> +if (WARN_ON(!vm))
> +return;
> +
> +pr_debug("Releasing process vm %p\n", vm);
> +
> +/* The original pasid of amdgpu vm has already been
> + * released during making a amdgpu vm to a compute vm
> + * The current pasid is managed by kfd and will be
> + * released on kfd process destroy. Set amdgpu pasid
> + * to 0 to avoid duplicate release.
> + */
> +avm->pasid = 0;
Don't you also need
Re: [PATCH 1/2] drm/amdgpu: Set pasid for compute vm
On 2018-08-27 03:25 PM, Oak Zeng wrote:
> To make a amdgpu vm to a compute vm, the old pasid will be freed and
> replaced with a pasid managed by kfd. Kfd can't reuse original pasid
> allocated by amdgpu because kfd uses different pasid policy with amdgpu.
> For example, all graphic devices share one same pasid in a process.
>
> Signed-off-by: Oak Zeng
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 7 ++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 33
> +---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 +--
> drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 5 ++--
> 6 files changed, 41 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index a8418a3..2895ef5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -156,11 +156,12 @@ uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev
> *kgd);
>
> /* GPUVM API */
> int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, void **vm,
> - void **process_info,
> + void **process_info, unsigned int pasid,
The pasid is still in between a bunch of output parameters. Please move
it between kgd and vm.
> struct dma_fence **ef);
> int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
> struct file *filp,
> void **vm, void **process_info,
> + unsigned int pasid,
Move pasid between filp and vm.
Thanks,
Felix
> struct dma_fence **ef);
> void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
> struct amdgpu_vm *vm);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 7eadc58..d60940e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -1004,7 +1004,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void
> **process_info,
> }
>
> int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, void **vm,
> - void **process_info,
> + void **process_info, unsigned int
> pasid,
> struct dma_fence **ef)
> {
> struct amdgpu_device *adev = get_amdgpu_device(kgd);
> @@ -1016,7 +1016,7 @@ int amdgpu_amdkfd_gpuvm_create_process_vm(struct
> kgd_dev *kgd, void **vm,
> return -ENOMEM;
>
> /* Initialize AMDGPU part of the VM */
> - ret = amdgpu_vm_init(adev, new_vm, AMDGPU_VM_CONTEXT_COMPUTE, 0);
> + ret = amdgpu_vm_init(adev, new_vm, AMDGPU_VM_CONTEXT_COMPUTE, pasid);
> if (ret) {
> pr_err("Failed init vm ret %d\n", ret);
> goto amdgpu_vm_init_fail;
> @@ -1041,6 +1041,7 @@ int amdgpu_amdkfd_gpuvm_create_process_vm(struct
> kgd_dev *kgd, void **vm,
> int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
> struct file *filp,
> void **vm, void **process_info,
> +unsigned int pasid,
> struct dma_fence **ef)
> {
> struct amdgpu_device *adev = get_amdgpu_device(kgd);
> @@ -1054,7 +1055,7 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct
> kgd_dev *kgd,
> return -EINVAL;
>
> /* Convert VM into a compute VM */
> - ret = amdgpu_vm_make_compute(adev, avm);
> + ret = amdgpu_vm_make_compute(adev, avm, pasid);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 662aec5..d8a99f4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2690,7 +2690,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
> amdgpu_vm *vm,
> * Returns:
> * 0 for success, -errno for errors.
> */
> -int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
> +int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> unsigned int pasid)
> {
> bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
> int r;
> @@ -2702,7 +2702,20 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev,
> struct amdgpu_vm *vm)
> /* Sanity checks */
> if (!RB_EMPTY_ROOT(>va.rb_root) || vm->root.entries) {
> r = -EINVAL;
> - goto error;
> + goto unreserve_bo;
> + }
> +
> + if
[PATCH 1/2] drm/amdgpu: Set pasid for compute vm
To make a amdgpu vm to a compute vm, the old pasid will be freed and
replaced with a pasid managed by kfd. Kfd can't reuse original pasid
allocated by amdgpu because kfd uses different pasid policy with amdgpu.
For example, all graphic devices share one same pasid in a process.
Signed-off-by: Oak Zeng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 7 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 33 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 +--
drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 5 ++--
6 files changed, 41 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index a8418a3..2895ef5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -156,11 +156,12 @@ uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev
*kgd);
/* GPUVM API */
int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, void **vm,
- void **process_info,
+ void **process_info, unsigned int pasid,
struct dma_fence **ef);
int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
struct file *filp,
void **vm, void **process_info,
+ unsigned int pasid,
struct dma_fence **ef);
void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
struct amdgpu_vm *vm);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 7eadc58..d60940e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1004,7 +1004,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void
**process_info,
}
int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, void **vm,
- void **process_info,
+ void **process_info, unsigned int
pasid,
struct dma_fence **ef)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
@@ -1016,7 +1016,7 @@ int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev
*kgd, void **vm,
return -ENOMEM;
/* Initialize AMDGPU part of the VM */
- ret = amdgpu_vm_init(adev, new_vm, AMDGPU_VM_CONTEXT_COMPUTE, 0);
+ ret = amdgpu_vm_init(adev, new_vm, AMDGPU_VM_CONTEXT_COMPUTE, pasid);
if (ret) {
pr_err("Failed init vm ret %d\n", ret);
goto amdgpu_vm_init_fail;
@@ -1041,6 +1041,7 @@ int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev
*kgd, void **vm,
int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
struct file *filp,
void **vm, void **process_info,
+ unsigned int pasid,
struct dma_fence **ef)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
@@ -1054,7 +1055,7 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev
*kgd,
return -EINVAL;
/* Convert VM into a compute VM */
- ret = amdgpu_vm_make_compute(adev, avm);
+ ret = amdgpu_vm_make_compute(adev, avm, pasid);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 662aec5..d8a99f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2690,7 +2690,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
* Returns:
* 0 for success, -errno for errors.
*/
-int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
+int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
unsigned int pasid)
{
bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
int r;
@@ -2702,7 +2702,20 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev,
struct amdgpu_vm *vm)
/* Sanity checks */
if (!RB_EMPTY_ROOT(>va.rb_root) || vm->root.entries) {
r = -EINVAL;
- goto error;
+ goto unreserve_bo;
+ }
+
+ if (pasid) {
+ unsigned long flags;
+
+ spin_lock_irqsave(>vm_manager.pasid_lock, flags);
+ r = idr_alloc(>vm_manager.pasid_idr, vm, pasid, pasid + 1,
+ GFP_ATOMIC);
+ spin_unlock_irqrestore(>vm_manager.pasid_lock, flags);
+
+ if
[PATCH 2/2] drm/amdkfd: Release an acquired process vm
For compute vm acquired from amdgpu, vm.pasid is managed
by kfd. Decouple pasid from such vm on process destroy
to avoid duplicate pasid release.
Signed-off-by: Oak Zeng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h| 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 18 ++
drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 +++-
drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 1 +
7 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index 2895ef5..5827734 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -166,6 +166,7 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev
*kgd,
void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
struct amdgpu_vm *vm);
void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm);
+void amdgpu_amdkfd_gpuvm_release_process_vm(void *vm);
uint32_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm);
int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
struct kgd_dev *kgd, uint64_t va, uint64_t size,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index ea79908..03a83d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -204,6 +204,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
.create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
.acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
.destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
+ .release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm,
.get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
.set_vm_context_page_table_base = set_vm_context_page_table_base,
.alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index 19dd665..b2b9c5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -164,6 +164,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
.create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
.acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
.destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
+ .release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm,
.get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
.set_vm_context_page_table_base = set_vm_context_page_table_base,
.alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index 1db60aa..3722bbd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -201,6 +201,7 @@ static const struct kfd2kgd_calls kfd2kgd = {
.create_process_vm = amdgpu_amdkfd_gpuvm_create_process_vm,
.acquire_process_vm = amdgpu_amdkfd_gpuvm_acquire_process_vm,
.destroy_process_vm = amdgpu_amdkfd_gpuvm_destroy_process_vm,
+ .release_process_vm = amdgpu_amdkfd_gpuvm_release_process_vm,
.get_process_page_dir = amdgpu_amdkfd_gpuvm_get_process_page_dir,
.set_vm_context_page_table_base = set_vm_context_page_table_base,
.alloc_memory_of_gpu = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index d60940e..7d1cdcd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1118,6 +1118,24 @@ void amdgpu_amdkfd_gpuvm_destroy_process_vm(struct
kgd_dev *kgd, void *vm)
kfree(vm);
}
+void amdgpu_amdkfd_gpuvm_release_process_vm(void *vm)
+{
+struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
+
+if (WARN_ON(!vm))
+return;
+
+pr_debug("Releasing process vm %p\n", vm);
+
+/* The original pasid of amdgpu vm has already been
+ * released during making a amdgpu vm to a compute vm
+ * The current pasid is managed by kfd and will be
+ * released on kfd process destroy. Set amdgpu pasid
+ * to 0 to avoid duplicate release.
+ */
+avm->pasid = 0;
+}
+
uint32_t amdgpu_amdkfd_gpuvm_get_process_page_dir(void *vm)
{
struct amdgpu_vm *avm = (struct amdgpu_vm *)vm;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c
RE: [PATCH] drm/amdgpu: Set pasid for compute vm
Hi Alex/Felix,
I submitted a new patch to address below comments.
I also come up with another patch to release a compute vm on kfd process
destroy, to address a pasid duplicate release (from both kfd and amdgpu
side)issue.
Please help to review.
Thanks,
Oak
-Original Message-
From: Zeng, Oak
Sent: Friday, August 24, 2018 12:53 PM
To: 'Alex Deucher' ; ozeng
Cc: amd-gfx list
Subject: RE: [PATCH] drm/amdgpu: Set pasid for compute vm
Yes I will add more description. Plus some fixes to Felix's comment, I will
work out a v2.
Thanks,
Oak
-Original Message-
From: Alex Deucher
Sent: Wednesday, August 22, 2018 5:47 PM
To: ozeng
Cc: amd-gfx list ; Zeng, Oak
Subject: Re: [PATCH] drm/amdgpu: Set pasid for compute vm
On Wed, Aug 22, 2018 at 5:31 PM Oak Zeng wrote:
>
Please provide a patch description.
Alex
> Signed-off-by: Oak Zeng
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 4 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 20 +---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++--
> drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 4 ++--
> 6 files changed, 28 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> index a8418a3..8939f54 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
> @@ -157,11 +157,11 @@ uint64_t amdgpu_amdkfd_get_vram_usage(struct
> kgd_dev *kgd);
> /* GPUVM API */
> int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, void **vm,
> void **process_info,
> - struct dma_fence **ef);
> + struct dma_fence **ef,
> + unsigned int pasid);
> int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
> struct file *filp,
> void **vm, void **process_info,
> - struct dma_fence **ef);
> + struct dma_fence **ef,
> + unsigned int pasid);
> void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
> struct amdgpu_vm *vm); void
> amdgpu_amdkfd_gpuvm_destroy_process_vm(struct kgd_dev *kgd, void *vm);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 7eadc58..659c397 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -1005,7 +1005,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm,
> void **process_info,
>
> int amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, void **vm,
> void **process_info,
> - struct dma_fence **ef)
> + struct dma_fence **ef,
> + unsigned int pasid)
> {
> struct amdgpu_device *adev = get_amdgpu_device(kgd);
> struct amdgpu_vm *new_vm;
> @@ -1016,7 +1016,7 @@ int amdgpu_amdkfd_gpuvm_create_process_vm(struct
> kgd_dev *kgd, void **vm,
> return -ENOMEM;
>
> /* Initialize AMDGPU part of the VM */
> - ret = amdgpu_vm_init(adev, new_vm, AMDGPU_VM_CONTEXT_COMPUTE, 0);
> + ret = amdgpu_vm_init(adev, new_vm, AMDGPU_VM_CONTEXT_COMPUTE,
> + pasid);
> if (ret) {
> pr_err("Failed init vm ret %d\n", ret);
> goto amdgpu_vm_init_fail; @@ -1041,7 +1041,7 @@ int
> amdgpu_amdkfd_gpuvm_create_process_vm(struct kgd_dev *kgd, void **vm,
> int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev *kgd,
>struct file *filp,
>void **vm, void **process_info,
> - struct dma_fence **ef)
> + struct dma_fence **ef,
> + unsigned int pasid)
> {
> struct amdgpu_device *adev = get_amdgpu_device(kgd);
> struct drm_file *drm_priv = filp->private_data; @@ -1054,7
> +1054,7 @@ int amdgpu_amdkfd_gpuvm_acquire_process_vm(struct kgd_dev
> +*kgd,
> return -EINVAL;
>
> /* Convert VM into a compute VM */
> - ret = amdgpu_vm_make_compute(adev, avm);
> + ret = amdgpu_vm_make_compute(adev, avm, pasid);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 662aec5..0f6b304 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2690,7 +2690,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
>
Re: [PATCH v2] drm/amdgpu: Merge amdkfd into amdgpu
On 2018-08-24 10:34 AM, Amber Lin wrote: > Since KFD is only supported by single GPU driver, it makes sense to merge > amdgpu and amdkfd into one module. This patch is the initial step: merge > Kconfig and Makefile. > > v2: also remove kfd from drm Kconfig > > Change-Id: I21c996ba29d393c1bf8064bdb2f5d89541159649 > Signed-off-by: Amber Lin Reviewed-by: Felix Kuehling > --- > drivers/gpu/drm/Kconfig | 2 - > drivers/gpu/drm/amd/amdgpu/Kconfig | 1 + > drivers/gpu/drm/amd/amdgpu/Makefile | 6 ++- > drivers/gpu/drm/amd/amdkfd/Kconfig | 2 +- > drivers/gpu/drm/amd/amdkfd/Makefile | 53 ++- > drivers/gpu/drm/amd/amdkfd/kfd_module.c | 76 > ++--- > 6 files changed, 63 insertions(+), 77 deletions(-) > > diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig > index 2a72d2f..5ea1ac3 100644 > --- a/drivers/gpu/drm/Kconfig > +++ b/drivers/gpu/drm/Kconfig > @@ -264,8 +264,6 @@ source "drivers/gpu/drm/bridge/Kconfig" > > source "drivers/gpu/drm/sti/Kconfig" > > -source "drivers/gpu/drm/amd/amdkfd/Kconfig" > - > source "drivers/gpu/drm/imx/Kconfig" > > source "drivers/gpu/drm/v3d/Kconfig" > diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig > b/drivers/gpu/drm/amd/amdgpu/Kconfig > index e8af1f5..9221e54 100644 > --- a/drivers/gpu/drm/amd/amdgpu/Kconfig > +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig > @@ -42,3 +42,4 @@ config DRM_AMDGPU_GART_DEBUGFS > > source "drivers/gpu/drm/amd/acp/Kconfig" > source "drivers/gpu/drm/amd/display/Kconfig" > +source "drivers/gpu/drm/amd/amdkfd/Kconfig" > diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile > b/drivers/gpu/drm/amd/amdgpu/Makefile > index d2bafab..847536b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/Makefile > +++ b/drivers/gpu/drm/amd/amdgpu/Makefile > @@ -35,7 +35,8 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \ > -I$(FULL_AMD_DISPLAY_PATH) \ > -I$(FULL_AMD_DISPLAY_PATH)/include \ > -I$(FULL_AMD_DISPLAY_PATH)/dc \ > - -I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm > + -I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \ > + -I$(FULL_AMD_PATH)/amdkfd > > amdgpu-y := amdgpu_drv.o > > @@ -136,6 +137,9 @@ amdgpu-y += \ > amdgpu-y += amdgpu_amdkfd.o > > ifneq ($(CONFIG_HSA_AMD),) > +AMDKFD_PATH := ../amdkfd > +include $(FULL_AMD_PATH)/amdkfd/Makefile > +amdgpu-y += $(AMDKFD_FILES) > amdgpu-y += \ >amdgpu_amdkfd_fence.o \ >amdgpu_amdkfd_gpuvm.o \ > diff --git a/drivers/gpu/drm/amd/amdkfd/Kconfig > b/drivers/gpu/drm/amd/amdkfd/Kconfig > index 3858820..fbf0ee5 100644 > --- a/drivers/gpu/drm/amd/amdkfd/Kconfig > +++ b/drivers/gpu/drm/amd/amdkfd/Kconfig > @@ -3,7 +3,7 @@ > # > > config HSA_AMD > - tristate "HSA kernel driver for AMD GPU devices" > + bool "HSA kernel driver for AMD GPU devices" > depends on DRM_AMDGPU && X86_64 > imply AMD_IOMMU_V2 > select MMU_NOTIFIER > diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile > b/drivers/gpu/drm/amd/amdkfd/Makefile > index ffd096f..69ec969 100644 > --- a/drivers/gpu/drm/amd/amdkfd/Makefile > +++ b/drivers/gpu/drm/amd/amdkfd/Makefile > @@ -23,26 +23,41 @@ > # Makefile for Heterogenous System Architecture support for AMD GPU devices > # > > -ccflags-y := -Idrivers/gpu/drm/amd/include/ \ > - -Idrivers/gpu/drm/amd/include/asic_reg > - > -amdkfd-y := kfd_module.o kfd_device.o kfd_chardev.o kfd_topology.o \ > - kfd_pasid.o kfd_doorbell.o kfd_flat_memory.o \ > - kfd_process.o kfd_queue.o kfd_mqd_manager.o \ > - kfd_mqd_manager_cik.o kfd_mqd_manager_vi.o \ > - kfd_mqd_manager_v9.o \ > - kfd_kernel_queue.o kfd_kernel_queue_cik.o \ > - kfd_kernel_queue_vi.o kfd_kernel_queue_v9.o \ > - kfd_packet_manager.o kfd_process_queue_manager.o \ > - kfd_device_queue_manager.o kfd_device_queue_manager_cik.o \ > - kfd_device_queue_manager_vi.o kfd_device_queue_manager_v9.o \ > - kfd_interrupt.o kfd_events.o cik_event_interrupt.o \ > - kfd_int_process_v9.o kfd_dbgdev.o kfd_dbgmgr.o kfd_crat.o > +AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ > + $(AMDKFD_PATH)/kfd_device.o \ > + $(AMDKFD_PATH)/kfd_chardev.o \ > + $(AMDKFD_PATH)/kfd_topology.o \ > + $(AMDKFD_PATH)/kfd_pasid.o \ > + $(AMDKFD_PATH)/kfd_doorbell.o \ > + $(AMDKFD_PATH)/kfd_flat_memory.o \ > + $(AMDKFD_PATH)/kfd_process.o \ > + $(AMDKFD_PATH)/kfd_queue.o \ > + $(AMDKFD_PATH)/kfd_mqd_manager.o \ > + $(AMDKFD_PATH)/kfd_mqd_manager_cik.o \ > + $(AMDKFD_PATH)/kfd_mqd_manager_vi.o \ > + $(AMDKFD_PATH)/kfd_mqd_manager_v9.o \ > + $(AMDKFD_PATH)/kfd_kernel_queue.o \ > + $(AMDKFD_PATH)/kfd_kernel_queue_cik.o \ > + $(AMDKFD_PATH)/kfd_kernel_queue_vi.o \ > + $(AMDKFD_PATH)/kfd_kernel_queue_v9.o \ > +
Re: [PATCH v2] drm/amdgpu: Move KFD parameters to amdgpu
On 2018-08-24 11:08 AM, Amber Lin wrote: > After merging KFD into amdgpu, move module parameters defined in KFD to > amdgpu_drv.c, where other module parameters are declared. > > v2: add kernel-doc comments > > Change-Id: I2de8d6c96bb49554c028bbc84bdb194f974c9278 > Signed-off-by: Amber Lin Reviewed-by: Felix Kuehling > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 87 > + > drivers/gpu/drm/amd/amdkfd/kfd_module.c | 40 --- > 2 files changed, 87 insertions(+), 40 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > index 2221f6b..dd6d8b1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c > @@ -39,6 +39,7 @@ > #include "amdgpu_gem.h" > > #include "amdgpu_amdkfd.h" > +#include "kfd_priv.h" > > /* > * KMS wrapper. > @@ -127,6 +128,15 @@ int amdgpu_compute_multipipe = -1; > int amdgpu_gpu_recovery = -1; /* auto */ > int amdgpu_emu_mode = 0; > uint amdgpu_smu_memory_pool_size = 0; > +/* KFD parameters */ > +int sched_policy = KFD_SCHED_POLICY_HWS; > +int hws_max_conc_proc = 8; > +int cwsr_enable = 1; > +int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; > +int send_sigterm; > +int debug_largebar; > +int ignore_crat; > +int vega10_noretry; > > /** > * DOC: vramlimit (int) > @@ -532,6 +542,83 @@ MODULE_PARM_DESC(smu_memory_pool_size, > "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); > module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, > 0444); > > +/** > + * DOC: sched_policy (int) > + * Set scheduling policy. Default is HWS(hardware scheduling) with > over-subscription. > + * Setting 1 disables over-subscription. Setting 2 disables HWS and > statically > + * assigns queues to HQDs. > + */ > +module_param(sched_policy, int, 0444); > +MODULE_PARM_DESC(sched_policy, > + "Scheduling policy (0 = HWS (Default), 1 = HWS without > over-subscription, 2 = Non-HWS (Used for debugging only)"); > + > +/** > + * DOC: hws_max_conc_proc (int) > + * Maximum number of processes that HWS can schedule concurrently. The > maximum is the > + * number of VMIDs assigned to the HWS, which is also the default. > + */ > +module_param(hws_max_conc_proc, int, 0444); > +MODULE_PARM_DESC(hws_max_conc_proc, > + "Max # processes HWS can execute concurrently when sched_policy=0 (0 = > no concurrency, #VMIDs for KFD = Maximum(default))"); > + > +/** > + * DOC: cwsr_enable (int) > + * CWSR(compute wave store and resume) allows the GPU to preempt shader > execution in > + * the middle of a compute wave. Default is 1 to enable this feature. > Setting 0 > + * disables it. > + */ > +module_param(cwsr_enable, int, 0444); > +MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); > + > +/** > + * DOC: max_num_of_queues_per_device (int) > + * Maximum number of queues per device. Valid setting is between 1 and 4096. > Default > + * is 4096. > + */ > +module_param(max_num_of_queues_per_device, int, 0444); > +MODULE_PARM_DESC(max_num_of_queues_per_device, > + "Maximum number of supported queues per device (1 = Minimum, 4096 = > default)"); > + > +/** > + * DOC: send_sigterm (int) > + * Send sigterm to HSA process on unhandled exceptions. Default is not to > send sigterm > + * but just print errors on dmesg. Setting 1 enables sending sigterm. > + */ > +module_param(send_sigterm, int, 0444); > +MODULE_PARM_DESC(send_sigterm, > + "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = > enable)"); > + > +/** > + * DOC: debug_largebar (int) > + * Set debug_largebar as 1 to enable simulating large-bar capability on > non-large bar > + * system. This limits the VRAM size reported to ROCm applications to the > visible > + * size, usually 256MB. > + * Default value is 0, diabled. > + */ > +module_param(debug_largebar, int, 0444); > +MODULE_PARM_DESC(debug_largebar, > + "Debug large-bar flag used to simulate large-bar capability on > non-large bar machine (0 = disable, 1 = enable)"); > + > +/** > + * DOC: ignore_crat (int) > + * Ignore CRAT table during KFD initialization. By default, KFD uses the > ACPI CRAT > + * table to get information about AMD APUs. This option can serve as a > workaround on > + * systems with a broken CRAT table. > + */ > +module_param(ignore_crat, int, 0444); > +MODULE_PARM_DESC(ignore_crat, > + "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 > = ignore CRAT)"); > + > +/** > + * DOC: noretry (int) > + * This parameter sets sh_mem_config.retry_disable. Default value, 0, > enables retry. > + * Setting 1 disables retry. > + * Retry is needed for recoverable page faults. > + */ > +module_param_named(noretry, vega10_noretry, int, 0644); > +MODULE_PARM_DESC(noretry, > + "Set sh_mem_config.retry_disable on Vega10 (0 = retry enabled > (default), 1 = retry disabled)"); > + > static
Re: [PATCH] drm/amdgpu: Refine gmc9 VM fault print.
Reviewed-by: Marek Olšák Marek On Mon, Aug 27, 2018 at 2:55 PM, Alex Deucher wrote: > On Mon, Aug 27, 2018 at 2:23 PM Andrey Grodzovsky > wrote: >> >> The fault reports the page number where the fault happend and not >> the exact faulty address. Update the print message to reflect that. >> >> Signed-off-by: Andrey Grodzovsky > > Reviewed-by: Alex Deucher > >> --- >> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> index 6763570..d44c5e2 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> @@ -270,7 +270,7 @@ static int gmc_v9_0_process_interrupt(struct >> amdgpu_device *adev, >> entry->src_id, entry->ring_id, entry->vmid, >> entry->pasid, task_info.process_name, task_info.tgid, >> task_info.task_name, task_info.pid); >> - dev_err(adev->dev, " at address 0x%016llx from %d\n", >> + dev_err(adev->dev, " in page starting at address 0x%016llx >> from %d\n", >> addr, entry->client_id); >> if (!amdgpu_sriov_vf(adev)) >> dev_err(adev->dev, >> -- >> 2.7.4 >> >> ___ >> amd-gfx mailing list >> amd-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 07/10] drm/amdgpu: stop using gart_start as offset for the GTT domain
On Mon, Aug 27, 2018 at 12:56 PM Christian König
wrote:
>
> Further separate GART and GTT domain.
>
> Signed-off-by: Christian König
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 +++---
> 2 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> index da7b1b92d9cf..c2539f6821c0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
> @@ -143,7 +143,8 @@ static int amdgpu_gtt_mgr_alloc(struct
> ttm_mem_type_manager *man,
> spin_unlock(>lock);
>
> if (!r)
> - mem->start = node->node.start;
> + mem->start = node->node.start +
> + (adev->gmc.gart_start >> PAGE_SHIFT);
>
> return r;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 2f304f9dd543..5cadf4f1ee2c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -188,7 +188,7 @@ static int amdgpu_init_mem_type(struct ttm_bo_device
> *bdev, uint32_t type,
> case TTM_PL_TT:
> /* GTT memory */
> man->func = _gtt_mgr_func;
> - man->gpu_offset = adev->gmc.gart_start;
> + man->gpu_offset = 0;
> man->available_caching = TTM_PL_MASK_CACHING;
> man->default_caching = TTM_PL_FLAG_CACHED;
> man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
> @@ -1062,7 +1062,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
> flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
>
> /* bind pages into GART page tables */
> - gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
> + gtt->offset = ((u64)bo_mem->start << PAGE_SHIFT) -
> adev->gmc.gart_start;
> r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
> ttm->pages, gtt->ttm.dma_address, flags);
>
> @@ -1110,7 +1110,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
> flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, );
>
> /* Bind pages */
> - gtt->offset = (u64)tmp.start << PAGE_SHIFT;
> + gtt->offset = ((u64)tmp.start << PAGE_SHIFT) - adev->gmc.gart_start;
> r = amdgpu_ttm_gart_bind(adev, bo, flags);
> if (unlikely(r)) {
> ttm_bo_mem_put(bo, );
> --
> 2.17.1
>
> ___
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Re: [PATCH 04/10] drm/amdgpu: use the smaller hole for GART
On Mon, Aug 27, 2018 at 12:55 PM Christian König wrote: > > Instead of the larger one use the smaller hole in the MC address > space for the GART mappings. > > Signed-off-by: Christian König Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c > index 8269197df8e0..265ec6807130 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c > @@ -132,7 +132,8 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, > struct amdgpu_gmc *mc) > mc->gart_size = max(size_bf, size_af); > } > > - if (size_bf > size_af) > + if ((size_bf >= mc->gart_size && size_bf < size_af) || > + (size_af < mc->gart_size)) > mc->gart_start = 0; > else > mc->gart_start = ALIGN(mc->vram_end + 1, 0x1ULL); > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
The point of this series seems to be to allow access to small system memory BOs (one page) without a GART mapping. I'm guessing that reduces pressure on the GART and removes the need for HDP and TLB flushes. Why does Patch 10 only enable that on GFXv9? Is there less benefit on older chips? Is this related to your recent changes to allow page tables in system memory? See my replies to patch 6 and 8. Other than that, the series is Acked-by: Felix Kuehling Regards, Felix On 2018-08-27 12:53 PM, Christian König wrote: > Only use the lower address space on GMC9 for the system domain. > Otherwise we would need to sign extend GMC addresses. > > Signed-off-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index e44b5191735d..d982956c8329 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) > if (r) > return r; > > - /* Set the internal MC address mask > - * This is the max address of the GPU's > - * internal address space. > + /* Use only the lower range for the internal MC address mask. This is > + * the max address of the GPU's internal address space. >*/ > - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ > + adev->gmc.mc_mask = 0x7fffULL; > > /* set DMA mask + need_dma32 flags. >* PCIE - can handle 44-bits. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 03/10] drm/amdgpu: fix amdgpu_gmc_gart_location a little bit
On Mon, Aug 27, 2018 at 12:55 PM Christian König
wrote:
>
> Improve the VCE limitation handling.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 28 -
> 1 file changed, 13 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 72dffa3fd194..8269197df8e0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -120,24 +120,22 @@ void amdgpu_gmc_gart_location(struct amdgpu_device
> *adev, struct amdgpu_gmc *mc)
>
> mc->gart_size += adev->pm.smu_prv_buffer_size;
>
> - size_af = adev->gmc.mc_mask - mc->vram_end;
> + /* VCE doesn't like it when BOs cross a 4GB segment, so align
> +* the GART base on a 4GB boundary as well.
> +*/
> size_bf = mc->vram_start;
> - if (size_bf > size_af) {
> - if (mc->gart_size > size_bf) {
> - dev_warn(adev->dev, "limiting GART\n");
> - mc->gart_size = size_bf;
> - }
> + size_af = adev->gmc.mc_mask + 1 -
> + ALIGN(mc->vram_end + 1, 0x1ULL);
Is it worth limiting this to asics with VCE support? Probably not a
big deal either way.
Reviewed-by: Alex Deucher
> +
> + if (mc->gart_size > max(size_bf, size_af)) {
> + dev_warn(adev->dev, "limiting GART\n");
> + mc->gart_size = max(size_bf, size_af);
> + }
> +
> + if (size_bf > size_af)
> mc->gart_start = 0;
> - } else {
> - if (mc->gart_size > size_af) {
> - dev_warn(adev->dev, "limiting GART\n");
> - mc->gart_size = size_af;
> - }
> - /* VCE doesn't like it when BOs cross a 4GB segment, so align
> -* the GART base on a 4GB boundary as well.
> -*/
> + else
> mc->gart_start = ALIGN(mc->vram_end + 1, 0x1ULL);
> - }
> mc->gart_end = mc->gart_start + mc->gart_size - 1;
> dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
> mc->gart_size >> 20, mc->gart_start, mc->gart_end);
> --
> 2.17.1
>
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Re: [PATCH 02/10] drm/amdgpu: move amdgpu_device_(vram|gtt)_location
On Mon, Aug 27, 2018 at 12:56 PM Christian König
wrote:
>
> Move that into amdgpu_gmc.c since we are really deadling with GMC
> address space here.
>
> Signed-off-by: Christian König
Reviewed-by: Alex Deucher
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 65 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c| 64 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h| 4 ++
> drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 +-
> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 +-
> 8 files changed, 76 insertions(+), 77 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 340e40d03d54..09bdedfc91c7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1166,10 +1166,6 @@ bool amdgpu_device_need_post(struct amdgpu_device
> *adev);
>
> void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
> u64 num_vis_bytes);
> -void amdgpu_device_vram_location(struct amdgpu_device *adev,
> -struct amdgpu_gmc *mc, u64 base);
> -void amdgpu_device_gart_location(struct amdgpu_device *adev,
> -struct amdgpu_gmc *mc);
> int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
> void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
> const u32 *registers,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 9f5e4be76d5e..0afc5e599683 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -651,71 +651,6 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev,
> u32 wb)
> __clear_bit(wb, adev->wb.used);
> }
>
> -/**
> - * amdgpu_device_vram_location - try to find VRAM location
> - *
> - * @adev: amdgpu device structure holding all necessary informations
> - * @mc: memory controller structure holding memory informations
> - * @base: base address at which to put VRAM
> - *
> - * Function will try to place VRAM at base address provided
> - * as parameter.
> - */
> -void amdgpu_device_vram_location(struct amdgpu_device *adev,
> -struct amdgpu_gmc *mc, u64 base)
> -{
> - uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
> -
> - mc->vram_start = base;
> - mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
> - if (limit && limit < mc->real_vram_size)
> - mc->real_vram_size = limit;
> - dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM
> used)\n",
> - mc->mc_vram_size >> 20, mc->vram_start,
> - mc->vram_end, mc->real_vram_size >> 20);
> -}
> -
> -/**
> - * amdgpu_device_gart_location - try to find GART location
> - *
> - * @adev: amdgpu device structure holding all necessary informations
> - * @mc: memory controller structure holding memory informations
> - *
> - * Function will place try to place GART before or after VRAM.
> - *
> - * If GART size is bigger than space left then we ajust GART size.
> - * Thus function will never fails.
> - */
> -void amdgpu_device_gart_location(struct amdgpu_device *adev,
> -struct amdgpu_gmc *mc)
> -{
> - u64 size_af, size_bf;
> -
> - mc->gart_size += adev->pm.smu_prv_buffer_size;
> -
> - size_af = adev->gmc.mc_mask - mc->vram_end;
> - size_bf = mc->vram_start;
> - if (size_bf > size_af) {
> - if (mc->gart_size > size_bf) {
> - dev_warn(adev->dev, "limiting GART\n");
> - mc->gart_size = size_bf;
> - }
> - mc->gart_start = 0;
> - } else {
> - if (mc->gart_size > size_af) {
> - dev_warn(adev->dev, "limiting GART\n");
> - mc->gart_size = size_af;
> - }
> - /* VCE doesn't like it when BOs cross a 4GB segment, so align
> -* the GART base on a 4GB boundary as well.
> -*/
> - mc->gart_start = ALIGN(mc->vram_end + 1, 0x1ULL);
> - }
> - mc->gart_end = mc->gart_start + mc->gart_size - 1;
> - dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
> - mc->gart_size >> 20, mc->gart_start, mc->gart_end);
> -}
> -
> /**
> * amdgpu_device_resize_fb_bar - try to resize FB BAR
> *
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index a249931ef512..72dffa3fd194 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>
Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
On Mon, Aug 27, 2018 at 12:56 PM Christian König wrote: > > Only use the lower address space on GMC9 for the system domain. > Otherwise we would need to sign extend GMC addresses. > > Signed-off-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index e44b5191735d..d982956c8329 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) > if (r) > return r; > > - /* Set the internal MC address mask > -* This is the max address of the GPU's > -* internal address space. > + /* Use only the lower range for the internal MC address mask. This is > +* the max address of the GPU's internal address space. > */ Update this comment to note the sign extension requirements and note that this max address is only for the system context (vmid 0). With that fixed: Reviewed-by: Alex Deucher Alex > - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ > + adev->gmc.mc_mask = 0x7fffULL; > > /* set DMA mask + need_dma32 flags. > * PCIE - can handle 44-bits. > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 08/10] drm/amdgpu: distinct between allocated GART space and GMC addr
On 2018-08-27 12:53 PM, Christian König wrote:
> Most of the time we only need to know if the BO has a valid GMC addr.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 --
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 13 +
> 3 files changed, 6 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 5ddd4e87480b..b5f20b42439e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -1362,8 +1362,6 @@ void amdgpu_bo_fence(struct amdgpu_bo *bo, struct
> dma_fence *fence,
> u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
> {
> WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
> - WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
> - !amdgpu_gtt_mgr_has_gart_addr(>tbo.mem));
> WARN_ON_ONCE(!ww_mutex_is_locked(>tbo.resv->lock) &&
>!bo->pin_count);
> WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> index 18945dd6982d..37c79ae3574e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
> @@ -200,7 +200,7 @@ static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo
> *bo)
> static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
As far as I can tell, this function is completely unused. So your change
here has no effect.
Other than that Acked-by: Felix Kuehling
Regards,
Felix
> {
> switch (bo->tbo.mem.mem_type) {
> - case TTM_PL_TT: return amdgpu_gtt_mgr_has_gart_addr(>tbo.mem);
> + case TTM_PL_TT: return bo->tbo.mem.start != AMDGPU_BO_INVALID_OFFSET;
> case TTM_PL_VRAM: return true;
> default: return false;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 5cadf4f1ee2c..d9f3201c9e5c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -345,7 +345,7 @@ static uint64_t amdgpu_mm_node_addr(struct
> ttm_buffer_object *bo,
> {
> uint64_t addr = 0;
>
> - if (mem->mem_type != TTM_PL_TT || amdgpu_gtt_mgr_has_gart_addr(mem)) {
> + if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
> addr = mm_node->start << PAGE_SHIFT;
> addr += bo->bdev->man[mem->mem_type].gpu_offset;
> }
> @@ -433,8 +433,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
> /* Map only what needs to be accessed. Map src to window 0 and
>* dst to window 1
>*/
> - if (src->mem->mem_type == TTM_PL_TT &&
> - !amdgpu_gtt_mgr_has_gart_addr(src->mem)) {
> + if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
> r = amdgpu_map_buffer(src->bo, src->mem,
> PFN_UP(cur_size + src_page_offset),
> src_node_start, 0, ring,
> @@ -447,8 +446,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
> from += src_page_offset;
> }
>
> - if (dst->mem->mem_type == TTM_PL_TT &&
> - !amdgpu_gtt_mgr_has_gart_addr(dst->mem)) {
> + if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
> r = amdgpu_map_buffer(dst->bo, dst->mem,
> PFN_UP(cur_size + dst_page_offset),
> dst_node_start, 1, ring,
> @@ -1086,11 +1084,10 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object
> *bo)
> uint64_t flags;
> int r;
>
> - if (bo->mem.mem_type != TTM_PL_TT ||
> - amdgpu_gtt_mgr_has_gart_addr(>mem))
> + if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
> return 0;
>
> - /* allocate GTT space */
> + /* allocate GART space */
> tmp = bo->mem;
> tmp.mm_node = NULL;
> placement.num_placement = 1;
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Re: [PATCH] drm/amdgpu: Refine gmc9 VM fault print.
On Mon, Aug 27, 2018 at 2:23 PM Andrey Grodzovsky wrote: > > The fault reports the page number where the fault happend and not > the exact faulty address. Update the print message to reflect that. > > Signed-off-by: Andrey Grodzovsky Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index 6763570..d44c5e2 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -270,7 +270,7 @@ static int gmc_v9_0_process_interrupt(struct > amdgpu_device *adev, > entry->src_id, entry->ring_id, entry->vmid, > entry->pasid, task_info.process_name, task_info.tgid, > task_info.task_name, task_info.pid); > - dev_err(adev->dev, " at address 0x%016llx from %d\n", > + dev_err(adev->dev, " in page starting at address 0x%016llx > from %d\n", > addr, entry->client_id); > if (!amdgpu_sriov_vf(adev)) > dev_err(adev->dev, > -- > 2.7.4 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 06/10] drm/amdgpu: add amdgpu_gmc_agp_location
On 2018-08-27 12:53 PM, Christian König wrote:
> Helper to figure out the location of the AGP BAR.
>
> Signed-off-by: Christian König
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 42 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 5 +++
> 2 files changed, 47 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 4331a0e25cdc..eed5352f3136 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -141,3 +141,45 @@ void amdgpu_gmc_gart_location(struct amdgpu_device
> *adev, struct amdgpu_gmc *mc)
> dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
> mc->gart_size >> 20, mc->gart_start, mc->gart_end);
> }
> +
> +/**
> + * amdgpu_gmc_agp_location - try to find AGP location
> + * @adev: amdgpu device structure holding all necessary informations
> + * @mc: memory controller structure holding memory informations
> + *
> + * Function will place try to fina a place for the AGP BAR in the MC address
s/fina/find
> + * space.
> + *
> + * AGP BAR will be assigned the largest available hole in the address space.
I'd add a comment that this function must be called after
amdgpu_gmc_vram_location and amdgpu_gmc_gart_location.
> + */
> +void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc
> *mc)
> +{
> + const uint64_t sixteen_gb = 1ULL << 34;
> + u64 size_af, size_bf;
> +
> + if (mc->vram_start > mc->gart_start) {
> + size_bf = mc->vram_start - mc->gart_end + 1;
> + size_af = mc->mc_mask - mc->vram_end;
> + } else {
> + size_bf = mc->vram_start;
> + size_af = mc->mc_mask - mc->gart_end;
> + }
> +
> + size_bf &= ~(sixteen_gb - 1);
> + size_af &= ~(sixteen_gb - 1);
This is not correct. E.g. vram_end = 12GB, gart_start = 28GB, size =
16GB. agp_start will be rounded up to 16GB and AGP will run into the
GART aperture.
You need to align the addresses before calculating the sizes.
Regards,
Felix
> +
> + if (size_bf > size_af) {
> + mc->agp_start = mc->vram_start > mc->gart_start ?
> + mc->gart_start : 0;
> + mc->agp_size = size_bf;
> + } else {
> + mc->agp_start = (mc->vram_start > mc->gart_start ?
> + mc->vram_end : mc->gart_end) + 1,
> + mc->agp_size = size_af;
> + }
> +
> + mc->agp_start = ALIGN(mc->agp_start, sixteen_gb);
> + mc->agp_end = mc->agp_start + mc->agp_size - 1;
> + dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",
> + mc->agp_size >> 20, mc->agp_start, mc->agp_end);
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index 72fcc9338f5e..163110fe375d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -81,6 +81,9 @@ struct amdgpu_gmc {
>* about vram size near mc fb location */
> u64 mc_vram_size;
> u64 visible_vram_size;
> + u64 agp_size;
> + u64 agp_start;
> + u64 agp_end;
> u64 gart_size;
> u64 gart_start;
> u64 gart_end;
> @@ -138,5 +141,7 @@ void amdgpu_gmc_vram_location(struct amdgpu_device *adev,
> struct amdgpu_gmc *mc,
> u64 base);
> void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
> struct amdgpu_gmc *mc);
> +void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
> + struct amdgpu_gmc *mc);
>
> #endif
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[PATCH] drm/amdgpu: Refine gmc9 VM fault print.
The fault reports the page number where the fault happend and not the exact faulty address. Update the print message to reflect that. Signed-off-by: Andrey Grodzovsky --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 6763570..d44c5e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -270,7 +270,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, entry->src_id, entry->ring_id, entry->vmid, entry->pasid, task_info.process_name, task_info.tgid, task_info.task_name, task_info.pid); - dev_err(adev->dev, " at address 0x%016llx from %d\n", + dev_err(adev->dev, " in page starting at address 0x%016llx from %d\n", addr, entry->client_id); if (!amdgpu_sriov_vf(adev)) dev_err(adev->dev, -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: System freezes on Shutdown [amdgpu] [drm]
Looks like you resume from suspend went bad and hence you have latter trouble in shutting down. Please open FDO ticket for this (https://bugs.freedesktop.org/) + attach full dmesg log without grep. S3 was working before so looks like regression. Try maybe 4.17 kernel and if you find it working you can try bisecting. Andrey On 08/26/2018 04:32 AM, John Smith wrote: Common shutdown seems to be ok. After any suspend (pressing stand-by button or close lit), I am not able to shutdown successful. The system hangs on shutdown. First some hw-info, then the bad error log. Please let me know, if you need further infos. Best, john. inxi -Fx System:Host: bang Kernel: 4.18.0-ARCH+ x86_64 bits: 64 compiler: gcc v: 8.2.0 Desktop: Gnome 3.28.3 Distro: Arch Linux Machine: Type: Laptop System: HP product: HP ZBook 15u G5 v: N/A serial: N/A Mobo: HP model: 83B2 v: KBC Version 04.45.00 serial: N/A UEFI: HP v: Q78 Ver. 01.00.05 date: 01/25/2018 Battery: ID-1: BAT0 charge: 46.3 Wh condition: 53.9/53.9 Wh (100%) model: Hewlett-Packard Primary status: Discharging CPU: Topology: Quad Core model: Intel Core i7-8550U bits: 64 type: MT MCP arch: Kaby Lake rev: 10 L2 cache: 8192 KiB flags: lm nx pae sse sse2 sse3 sse4_1 sse4_2 ssse3 vmx bogomips: 31880 Speed: 800 MHz min/max: 400/4000 MHz Core speeds (MHz): 1: 800 2: 800 3: 800 4: 800 5: 800 6: 800 7: 800 8: 800 Graphics: Card-1: Intel UHD Graphics 620 driver: i915 v: kernel bus ID: 00:02.0 Card-2: Advanced Micro Devices [AMD/ATI] Lexa XT [Radeon PRO WX 3100] driver: amdgpu v: kernel bus ID: 01:00.0 Display: wayland server: X.Org 1.20.1 driver: amdgpu resolution: 1920x1080~60Hz OpenGL: renderer: Mesa DRI Intel UHD Graphics 620 (Kabylake GT2) v: 4.5 Mesa 18.1.6 direct render: Yes Audio: Card-1: Intel Sunrise Point-LP HD Audio driver: snd_hda_intel v: kernel bus ID: 00:1f.3 Sound Server: ALSA v: k4.18.0-ARCH+ Network: Card-1: Intel Ethernet Connection I219-V driver: e1000e v: 3.2.6-k port: N/A bus ID: 00:1f.6 IF: enp0s31f6 state: down mac: b4:b6:86:1c:73:17 Card-2: Intel Wireless 8265 / 8275 driver: iwlwifi v: kernel bus ID: 02:00.0 IF: wlp2s0 state: up mac: 00:1c:bf:fe:24:0f Drives:HDD Total Size: 476.94 GiB used: 41.80 GiB (8.8%) ID-1: /dev/nvme0n1 model: KXG50ZNV512G_TOSHIBA size: 476.94 GiB Partition: ID-1: / size: 48.97 GiB used: 17.92 GiB (36.6%) fs: ext4 dev: /dev/nvme0n1p3 ID-2: /boot size: 2.00 GiB used: 130.6 MiB (6.4%) fs: vfat dev: /dev/nvme0n1p1 ID-3: /home size: 415.30 GiB used: 23.75 GiB (5.7%) fs: ext4 dev: /dev/nvme0n1p4 ID-4: swap-1 size: 2.00 GiB used: 0 KiB (0.0%) fs: swap dev: /dev/nvme0n1p2 Sensors: System Temperatures: cpu: 42.0 C mobo: N/A gpu: amdgpu temp: 37 C Fan Speeds (RPM): N/A Info: Processes: 259 Uptime: 15m Memory: 15.52 GiB used: 1.95 GiB (12.6%) Init: systemd Compilers: gcc: 8.2.0 clang: 6.0.1 Shell: bash v: 4.4.23 inxi: 3.0.07 uname -a Linux bang 4.18.0-ARCH+ #1 SMP PREEMPT Fri Aug 24 18:37:45 CEST 2018 x86_64 GNU/Linux dmesg | grep amdgpu [4.110050] [drm] amdgpu kernel modesetting enabled. [4.125300] amdgpu :01:00.0: enabling device (0006 -> 0007) [4.125687] amdgpu :01:00.0: kfd not supported on this ASIC [4.155751] amdgpu :01:00.0: BAR 2: releasing [mem 0xd000-0xd01f 64bit pref] [4.155752] amdgpu :01:00.0: BAR 0: releasing [mem 0xc000-0xcfff 64bit pref] [4.155762] amdgpu :01:00.0: BAR 0: assigned [mem 0xc000-0xcfff 64bit pref] [4.155771] amdgpu :01:00.0: BAR 2: assigned [mem 0xd000-0xd01f 64bit pref] [4.155807] amdgpu :01:00.0: VRAM: 2048M 0x00F4 - 0x00F47FFF (2048M used) [4.155808] amdgpu :01:00.0: GART: 256M 0x - 0x0FFF [4.155925] [drm] amdgpu: 2048M of VRAM memory ready [4.155926] [drm] amdgpu: 3072M of GTT memory ready. [4.223253] amdgpu: [powerplay] Voltage value looks like a Leakage ID but it's not patched [4.224590] amdgpu: [powerplay] Voltage value looks like a Leakage ID but it's not patched [4.225873] amdgpu: [powerplay] Voltage value looks like a Leakage ID but it's not patched [4.226831] amdgpu: [powerplay] Voltage value looks like a Leakage ID but it's not patched [4.227538] amdgpu: [powerplay] Voltage value looks like a Leakage ID but it's not patched [4.228249] amdgpu: [powerplay] Voltage value looks like a Leakage ID but it's not patched [4.228950] amdgpu: [powerplay] Voltage value looks like a Leakage ID but it's not patched [4.249592] amdgpu: [powerplay] Failed to retrieve minimum clocks. [4.249593] amdgpu: [powerplay] Error in phm_get_clock_info [4.249714] [drm:dc_create
[PATCH 10/10] drm/amdgpu: enable AGP aperture for GMC9
Enable the old AGP aperture to avoid GART mappings.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 10 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c| 1 +
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c | 10 +-
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 3403ded39d13..ffd0ec9586d1 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -65,16 +65,16 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct
amdgpu_device *adev)
{
uint64_t value;
- /* Disable AGP. */
+ /* Program the AGP BAR */
WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
- WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, 0);
- WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, 0x);
+ WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+ WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
/* Program the system aperture low logical page number. */
WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
+min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);
WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
+max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
/* Set default page address. */
value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 60c8f848c102..3f40c153039f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -751,6 +751,7 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device
*adev,
base = mmhub_v1_0_get_fb_location(adev);
amdgpu_gmc_vram_location(adev, >gmc, base);
amdgpu_gmc_gart_location(adev, mc);
+ amdgpu_gmc_agp_location(adev, mc);
/* base offset of vram pages */
adev->vm_manager.vram_base_offset = gfxhub_v1_0_get_mc_fb_offset(adev);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 5f6a9c85488f..73d7c075dd33 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -76,16 +76,16 @@ static void mmhub_v1_0_init_system_aperture_regs(struct
amdgpu_device *adev)
uint64_t value;
uint32_t tmp;
- /* Disable AGP. */
+ /* Program the AGP BAR */
WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BASE, 0);
- WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, 0);
- WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, 0x00FF);
+ WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+ WREG32_SOC15(MMHUB, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
/* Program the system aperture low logical page number. */
WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
-adev->gmc.vram_start >> 18);
+min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);
WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
-adev->gmc.vram_end >> 18);
+max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
/* Set default page address. */
value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
--
2.17.1
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[PATCH 09/10] drm/amdgpu: use the AGP aperture for system memory access
Start to use the old AGP aperture for system memory access.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 24 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 9
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 21 ++
4 files changed, 46 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index eed5352f3136..54d353951e21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -79,6 +79,30 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
return pd_addr;
}
+/**
+ * amdgpu_gmc_agp_addr - return the address in the AGP address space
+ *
+ * @tbo: TTM BO which needs the address, must be in GTT domain
+ *
+ * Tries to figure out how to access the BO through the AGP aperture. Returns
+ * AMDGPU_BO_INVALID_OFFSET if that is not possible.
+ */
+uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *tbo)
+{
+ struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
+ struct ttm_dma_tt *ttm;
+
+ if (tbo->num_pages != 1 || !tbo->ttm ||
+ tbo->ttm->caching_state == tt_cached)
+ return AMDGPU_BO_INVALID_OFFSET;
+
+ ttm = container_of(tbo->ttm, struct ttm_dma_tt, ttm);
+ if (ttm->dma_address[0] + PAGE_SIZE >= adev->gmc.agp_size)
+ return AMDGPU_BO_INVALID_OFFSET;
+
+ return adev->gmc.agp_start + ttm->dma_address[0];
+}
+
/**
* amdgpu_gmc_vram_location - try to find VRAM location
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 163110fe375d..6e8432fd3309 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -137,6 +137,7 @@ static inline bool amdgpu_gmc_vram_full_visible(struct
amdgpu_gmc *gmc)
void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
uint64_t *addr, uint64_t *flags);
uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
+uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *tbo);
void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc
*mc,
u64 base);
void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index c2539f6821c0..deaea11eb39a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -132,6 +132,15 @@ static int amdgpu_gtt_mgr_alloc(struct
ttm_mem_type_manager *man,
else
lpfn = adev->gart.num_cpu_pages;
+ if (fpfn == 0 && lpfn == adev->gart.num_cpu_pages) {
+ uint64_t addr = amdgpu_gmc_agp_addr(tbo);
+
+ if (addr != AMDGPU_BO_INVALID_OFFSET) {
+ mem->start = addr >> PAGE_SHIFT;
+ return 0;
+ }
+ }
+
mode = DRM_MM_INSERT_BEST;
if (place && place->flags & TTM_PL_FLAG_TOPDOWN)
mode = DRM_MM_INSERT_HIGH;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index d9f3201c9e5c..281611f6bcd4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1103,15 +1103,18 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
if (unlikely(r))
return r;
- /* compute PTE flags for this buffer object */
- flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, );
-
- /* Bind pages */
- gtt->offset = ((u64)tmp.start << PAGE_SHIFT) - adev->gmc.gart_start;
- r = amdgpu_ttm_gart_bind(adev, bo, flags);
- if (unlikely(r)) {
- ttm_bo_mem_put(bo, );
- return r;
+ if (amdgpu_gtt_mgr_has_gart_addr()) {
+ /* compute PTE flags for this buffer object */
+ flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, );
+
+ /* Bind pages */
+ gtt->offset = ((u64)tmp.start << PAGE_SHIFT) -
+ adev->gmc.gart_start;
+ r = amdgpu_ttm_gart_bind(adev, bo, flags);
+ if (unlikely(r)) {
+ ttm_bo_mem_put(bo, );
+ return r;
+ }
}
ttm_bo_mem_put(bo, >mem);
--
2.17.1
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[PATCH 07/10] drm/amdgpu: stop using gart_start as offset for the GTT domain
Further separate GART and GTT domain.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 +++---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index da7b1b92d9cf..c2539f6821c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -143,7 +143,8 @@ static int amdgpu_gtt_mgr_alloc(struct ttm_mem_type_manager
*man,
spin_unlock(>lock);
if (!r)
- mem->start = node->node.start;
+ mem->start = node->node.start +
+ (adev->gmc.gart_start >> PAGE_SHIFT);
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 2f304f9dd543..5cadf4f1ee2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -188,7 +188,7 @@ static int amdgpu_init_mem_type(struct ttm_bo_device *bdev,
uint32_t type,
case TTM_PL_TT:
/* GTT memory */
man->func = _gtt_mgr_func;
- man->gpu_offset = adev->gmc.gart_start;
+ man->gpu_offset = 0;
man->available_caching = TTM_PL_MASK_CACHING;
man->default_caching = TTM_PL_FLAG_CACHED;
man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
@@ -1062,7 +1062,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
/* bind pages into GART page tables */
- gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
+ gtt->offset = ((u64)bo_mem->start << PAGE_SHIFT) - adev->gmc.gart_start;
r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
ttm->pages, gtt->ttm.dma_address, flags);
@@ -1110,7 +1110,7 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, );
/* Bind pages */
- gtt->offset = (u64)tmp.start << PAGE_SHIFT;
+ gtt->offset = ((u64)tmp.start << PAGE_SHIFT) - adev->gmc.gart_start;
r = amdgpu_ttm_gart_bind(adev, bo, flags);
if (unlikely(r)) {
ttm_bo_mem_put(bo, );
--
2.17.1
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[PATCH 06/10] drm/amdgpu: add amdgpu_gmc_agp_location
Helper to figure out the location of the AGP BAR.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 42 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 5 +++
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 4331a0e25cdc..eed5352f3136 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -141,3 +141,45 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
mc->gart_size >> 20, mc->gart_start, mc->gart_end);
}
+
+/**
+ * amdgpu_gmc_agp_location - try to find AGP location
+ * @adev: amdgpu device structure holding all necessary informations
+ * @mc: memory controller structure holding memory informations
+ *
+ * Function will place try to fina a place for the AGP BAR in the MC address
+ * space.
+ *
+ * AGP BAR will be assigned the largest available hole in the address space.
+ */
+void amdgpu_gmc_agp_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc)
+{
+ const uint64_t sixteen_gb = 1ULL << 34;
+ u64 size_af, size_bf;
+
+ if (mc->vram_start > mc->gart_start) {
+ size_bf = mc->vram_start - mc->gart_end + 1;
+ size_af = mc->mc_mask - mc->vram_end;
+ } else {
+ size_bf = mc->vram_start;
+ size_af = mc->mc_mask - mc->gart_end;
+ }
+
+ size_bf &= ~(sixteen_gb - 1);
+ size_af &= ~(sixteen_gb - 1);
+
+ if (size_bf > size_af) {
+ mc->agp_start = mc->vram_start > mc->gart_start ?
+ mc->gart_start : 0;
+ mc->agp_size = size_bf;
+ } else {
+ mc->agp_start = (mc->vram_start > mc->gart_start ?
+ mc->vram_end : mc->gart_end) + 1,
+ mc->agp_size = size_af;
+ }
+
+ mc->agp_start = ALIGN(mc->agp_start, sixteen_gb);
+ mc->agp_end = mc->agp_start + mc->agp_size - 1;
+ dev_info(adev->dev, "AGP: %lluM 0x%016llX - 0x%016llX\n",
+ mc->agp_size >> 20, mc->agp_start, mc->agp_end);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 72fcc9338f5e..163110fe375d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -81,6 +81,9 @@ struct amdgpu_gmc {
* about vram size near mc fb location */
u64 mc_vram_size;
u64 visible_vram_size;
+ u64 agp_size;
+ u64 agp_start;
+ u64 agp_end;
u64 gart_size;
u64 gart_start;
u64 gart_end;
@@ -138,5 +141,7 @@ void amdgpu_gmc_vram_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc,
u64 base);
void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc);
+void amdgpu_gmc_agp_location(struct amdgpu_device *adev,
+struct amdgpu_gmc *mc);
#endif
--
2.17.1
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[PATCH 04/10] drm/amdgpu: use the smaller hole for GART
Instead of the larger one use the smaller hole in the MC address space for the GART mappings. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 8269197df8e0..265ec6807130 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -132,7 +132,8 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) mc->gart_size = max(size_bf, size_af); } - if (size_bf > size_af) + if ((size_bf >= mc->gart_size && size_bf < size_af) || + (size_af < mc->gart_size)) mc->gart_start = 0; else mc->gart_start = ALIGN(mc->vram_end + 1, 0x1ULL); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 08/10] drm/amdgpu: distinct between allocated GART space and GMC addr
Most of the time we only need to know if the BO has a valid GMC addr.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 --
drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c| 13 +
3 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 5ddd4e87480b..b5f20b42439e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1362,8 +1362,6 @@ void amdgpu_bo_fence(struct amdgpu_bo *bo, struct
dma_fence *fence,
u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
{
WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
- WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
-!amdgpu_gtt_mgr_has_gart_addr(>tbo.mem));
WARN_ON_ONCE(!ww_mutex_is_locked(>tbo.resv->lock) &&
!bo->pin_count);
WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
index 18945dd6982d..37c79ae3574e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
@@ -200,7 +200,7 @@ static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo
*bo)
static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
{
switch (bo->tbo.mem.mem_type) {
- case TTM_PL_TT: return amdgpu_gtt_mgr_has_gart_addr(>tbo.mem);
+ case TTM_PL_TT: return bo->tbo.mem.start != AMDGPU_BO_INVALID_OFFSET;
case TTM_PL_VRAM: return true;
default: return false;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 5cadf4f1ee2c..d9f3201c9e5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -345,7 +345,7 @@ static uint64_t amdgpu_mm_node_addr(struct
ttm_buffer_object *bo,
{
uint64_t addr = 0;
- if (mem->mem_type != TTM_PL_TT || amdgpu_gtt_mgr_has_gart_addr(mem)) {
+ if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
addr = mm_node->start << PAGE_SHIFT;
addr += bo->bdev->man[mem->mem_type].gpu_offset;
}
@@ -433,8 +433,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
/* Map only what needs to be accessed. Map src to window 0 and
* dst to window 1
*/
- if (src->mem->mem_type == TTM_PL_TT &&
- !amdgpu_gtt_mgr_has_gart_addr(src->mem)) {
+ if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
r = amdgpu_map_buffer(src->bo, src->mem,
PFN_UP(cur_size + src_page_offset),
src_node_start, 0, ring,
@@ -447,8 +446,7 @@ int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
from += src_page_offset;
}
- if (dst->mem->mem_type == TTM_PL_TT &&
- !amdgpu_gtt_mgr_has_gart_addr(dst->mem)) {
+ if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
r = amdgpu_map_buffer(dst->bo, dst->mem,
PFN_UP(cur_size + dst_page_offset),
dst_node_start, 1, ring,
@@ -1086,11 +1084,10 @@ int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
uint64_t flags;
int r;
- if (bo->mem.mem_type != TTM_PL_TT ||
- amdgpu_gtt_mgr_has_gart_addr(>mem))
+ if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
return 0;
- /* allocate GTT space */
+ /* allocate GART space */
tmp = bo->mem;
tmp.mm_node = NULL;
placement.num_placement = 1;
--
2.17.1
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[PATCH 03/10] drm/amdgpu: fix amdgpu_gmc_gart_location a little bit
Improve the VCE limitation handling.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 28 -
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 72dffa3fd194..8269197df8e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -120,24 +120,22 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev,
struct amdgpu_gmc *mc)
mc->gart_size += adev->pm.smu_prv_buffer_size;
- size_af = adev->gmc.mc_mask - mc->vram_end;
+ /* VCE doesn't like it when BOs cross a 4GB segment, so align
+* the GART base on a 4GB boundary as well.
+*/
size_bf = mc->vram_start;
- if (size_bf > size_af) {
- if (mc->gart_size > size_bf) {
- dev_warn(adev->dev, "limiting GART\n");
- mc->gart_size = size_bf;
- }
+ size_af = adev->gmc.mc_mask + 1 -
+ ALIGN(mc->vram_end + 1, 0x1ULL);
+
+ if (mc->gart_size > max(size_bf, size_af)) {
+ dev_warn(adev->dev, "limiting GART\n");
+ mc->gart_size = max(size_bf, size_af);
+ }
+
+ if (size_bf > size_af)
mc->gart_start = 0;
- } else {
- if (mc->gart_size > size_af) {
- dev_warn(adev->dev, "limiting GART\n");
- mc->gart_size = size_af;
- }
- /* VCE doesn't like it when BOs cross a 4GB segment, so align
-* the GART base on a 4GB boundary as well.
-*/
+ else
mc->gart_start = ALIGN(mc->vram_end + 1, 0x1ULL);
- }
mc->gart_end = mc->gart_start + mc->gart_size - 1;
dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
mc->gart_size >> 20, mc->gart_start, mc->gart_end);
--
2.17.1
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[PATCH 05/10] drm/amdgpu: put GART away from VRAM
Always try to put the GART away from where VRAM is. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 265ec6807130..4331a0e25cdc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -136,7 +136,7 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc) (size_af < mc->gart_size)) mc->gart_start = 0; else - mc->gart_start = ALIGN(mc->vram_end + 1, 0x1ULL); + mc->gart_start = mc->mc_mask - mc->gart_size + 1; mc->gart_end = mc->gart_start + mc->gart_size - 1; dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", mc->gart_size >> 20, mc->gart_start, mc->gart_end); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 02/10] drm/amdgpu: move amdgpu_device_(vram|gtt)_location
Move that into amdgpu_gmc.c since we are really deadling with GMC
address space here.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 4 --
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 65 --
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c| 64 +
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h| 4 ++
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 +-
8 files changed, 76 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 340e40d03d54..09bdedfc91c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1166,10 +1166,6 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev);
void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
u64 num_vis_bytes);
-void amdgpu_device_vram_location(struct amdgpu_device *adev,
-struct amdgpu_gmc *mc, u64 base);
-void amdgpu_device_gart_location(struct amdgpu_device *adev,
-struct amdgpu_gmc *mc);
int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
const u32 *registers,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 9f5e4be76d5e..0afc5e599683 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -651,71 +651,6 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32
wb)
__clear_bit(wb, adev->wb.used);
}
-/**
- * amdgpu_device_vram_location - try to find VRAM location
- *
- * @adev: amdgpu device structure holding all necessary informations
- * @mc: memory controller structure holding memory informations
- * @base: base address at which to put VRAM
- *
- * Function will try to place VRAM at base address provided
- * as parameter.
- */
-void amdgpu_device_vram_location(struct amdgpu_device *adev,
-struct amdgpu_gmc *mc, u64 base)
-{
- uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
-
- mc->vram_start = base;
- mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
- if (limit && limit < mc->real_vram_size)
- mc->real_vram_size = limit;
- dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
- mc->mc_vram_size >> 20, mc->vram_start,
- mc->vram_end, mc->real_vram_size >> 20);
-}
-
-/**
- * amdgpu_device_gart_location - try to find GART location
- *
- * @adev: amdgpu device structure holding all necessary informations
- * @mc: memory controller structure holding memory informations
- *
- * Function will place try to place GART before or after VRAM.
- *
- * If GART size is bigger than space left then we ajust GART size.
- * Thus function will never fails.
- */
-void amdgpu_device_gart_location(struct amdgpu_device *adev,
-struct amdgpu_gmc *mc)
-{
- u64 size_af, size_bf;
-
- mc->gart_size += adev->pm.smu_prv_buffer_size;
-
- size_af = adev->gmc.mc_mask - mc->vram_end;
- size_bf = mc->vram_start;
- if (size_bf > size_af) {
- if (mc->gart_size > size_bf) {
- dev_warn(adev->dev, "limiting GART\n");
- mc->gart_size = size_bf;
- }
- mc->gart_start = 0;
- } else {
- if (mc->gart_size > size_af) {
- dev_warn(adev->dev, "limiting GART\n");
- mc->gart_size = size_af;
- }
- /* VCE doesn't like it when BOs cross a 4GB segment, so align
-* the GART base on a 4GB boundary as well.
-*/
- mc->gart_start = ALIGN(mc->vram_end + 1, 0x1ULL);
- }
- mc->gart_end = mc->gart_start + mc->gart_size - 1;
- dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n",
- mc->gart_size >> 20, mc->gart_start, mc->gart_end);
-}
-
/**
* amdgpu_device_resize_fb_bar - try to resize FB BAR
*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index a249931ef512..72dffa3fd194 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -78,3 +78,67 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
}
return pd_addr;
}
+
+/**
+ * amdgpu_gmc_vram_location - try to find VRAM location
+ *
+ * @adev: amdgpu device structure holding all necessary informations
+ * @mc: memory controller structure holding memory informations
+ *
[PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
Only use the lower address space on GMC9 for the system domain. Otherwise we would need to sign extend GMC addresses. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e44b5191735d..d982956c8329 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; - /* Set the internal MC address mask -* This is the max address of the GPU's -* internal address space. + /* Use only the lower range for the internal MC address mask. This is +* the max address of the GPU's internal address space. */ - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ + adev->gmc.mc_mask = 0x7fffULL; /* set DMA mask + need_dma32 flags. * PCIE - can handle 44-bits. -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
How to gracefully handle pci remove
Hi everybody , I am trying to resolve various problems I observe when logically removing AMDGPU device from pci - echo 1 > /sys/class/drm/card0/device/remove One of the problems I encountered was hitting WARNs in amdgpu_gem_force_release. It complaints about still open client FDs and BOs allocations which is obvious since we didn't let user space clients know about the device removal and hence they won't release allocations and won't close their FDs. Question - how other drivers handle this use case, especially eGPUs since they indeed may be extracted in any moment, is there any way to notify Xorg and other clients about this so they may have a chance to release all their allocations and probably terminate ? Maybe some kind of uevent ? Andrey ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: KFD co-maintainership and branch model
> -Original Message- > From: amd-gfx On Behalf Of Felix > Kuehling > Sent: Friday, August 24, 2018 5:58 PM > To: Deucher, Alexander ; Koenig, Christian > ; Oded Gabbay ; > Dave Airlie > Cc: amd-gfx list > Subject: Re: KFD co-maintainership and branch model > > On 2018-08-23 08:38 AM, Deucher, Alexander wrote: > >> -Original Message- > >> From: Christian König > >> Sent: Thursday, August 23, 2018 3:01 AM > >> To: Oded Gabbay ; Dave Airlie > >> > >> Cc: Deucher, Alexander ; Kuehling, Felix > >> ; amd-gfx list > >> > >> Subject: Re: KFD co-maintainership and branch model > >> > >> Am 23.08.2018 um 08:54 schrieb Oded Gabbay: > >>> On Thu, Aug 23, 2018 at 4:34 AM David Airlie > wrote: > On Thu, Aug 23, 2018 at 8:25 AM, Felix Kuehling > >> wrote: > > Hi all, > > > > Oded has offered to make me co-maintainer of KFD, as he's super > > busy at work and less responsive than he used to be. > > > > At the same time we're about to send out the first patches to > > merge KFD and AMDGPU into a single kernel module. > > > > With that in mind I'd like to propose to upstream KFD through > > Alex's branch in the future. It would avoid conflicts in shared > > code (amdgpu_vm.c is most active at the moment) when merging > > branches, and make the code flow and testing easier. > > > > Please let me know what you think? > > > Works for me. > > Thanks, > Dave. > >>> Works for me as well. > >> Sounds good to me as well. > > Works for me as well. > > Thank you. We have agreement. > > Right now KFD in amd-staging-drm-next is a bit behind what's drm-next. > Alex, are you planning to rebase amd-staging-drm-next soon? If not, I'd like > to cherry-pick the missing commits before applying anything new. > Yes. I can update it this week. Alex > Regards, > Felix > > > > > Alex > > > >> Christian. > >> > >>> Oded > >>> ___ > >>> amd-gfx mailing list > >>> amd-gfx@lists.freedesktop.org > >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amdgpu: remove extra newline when printing VM faults
On Mon, Aug 27, 2018 at 9:45 AM Christian König wrote: > > Looks like a copy error to me. > > Signed-off-by: Christian König Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index 66abfcf87ad0..ad40acb236bc 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -265,7 +265,7 @@ static int gmc_v9_0_process_interrupt(struct > amdgpu_device *adev, > amdgpu_vm_get_task_info(adev, entry->pasid, _info); > > dev_err(adev->dev, > - "[%s] VMC page fault (src_id:%u ring:%u vmid:%u > pasid:%u, for process %s pid %d thread %s pid %d\n)\n", > + "[%s] VMC page fault (src_id:%u ring:%u vmid:%u > pasid:%u, for process %s pid %d thread %s pid %d)\n", > entry->vmid_src ? "mmhub" : "gfxhub", > entry->src_id, entry->ring_id, entry->vmid, > entry->pasid, task_info.process_name, task_info.tgid, > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/powerplay: expose vega20 OD features
On Mon, Aug 27, 2018 at 12:04 AM Quan, Evan wrote:
>
> Hi @Deucher, Alexander & @Zhu, Rex,
>
>
> I can remove the od setings for power limit and fan speed related since they
> seem redundant with other sysfs apis.
>
> But for the clock/voltage related, i can not see how to reuse old
> pp_od_clk_voltage APIs.
>
>
> For the old pp_od_clk_voltage APIs,
>
> 1. they output/input the voltages in their exact values. E.g. "s 1 500 820"
> will update sclk level 1 to be 500 MHz at 820 mV
>
> But for vega20, we did not know its original voltage value. The
> output/input for voltage are just offest from its original value.
>
> So, if to reuse these APIs, we will make them have two different
> explanations(
>
> on vega20 or later, the voltage is offset. On previous ASICs, the
> voltage is exact value). I think that will confuse the users.
>
>
> 2. they support voltage set for each level. But for vega20, it supports only
> three pairs of clock/voltage set. And per suggestion,
>
> these three pairs should be: voltage offset of minimum clock level,
> voltage offset for middle clock level and voltage offset
>
> for maximum clock level.
>
>
> Also, i believe the future ASICs will also take the vega20 OD ways(that is we
> need the offset, not the exact value for voltage).
>
>
> So, based on previous considerations, i decide to have new APIs instead of
> reusing existing ones.
I'm not saying to use the same API. Use the new API, but expose the
API using the same sysfs file rather than adding a new one. Same way
we handle the power profiles; E.g., the API is different between smu7
and vega10, but they both use the same sysfs file.
Alex
>
>
> Regards,
>
> Evan
>
>
> From: Zhu, Rex
> Sent: Saturday, August 25, 2018 12:32 AM
> To: Alex Deucher; Quan, Evan
> Cc: amd-gfx list; Xu, Feifei; Kuehling, Felix; Deucher, Alexander; Zhang,
> Hawking
> Subject: RE: [PATCH] drm/amd/powerplay: expose vega20 OD features
>
>
>
> > -Original Message-
> > From: Alex Deucher
> > Sent: Friday, August 24, 2018 11:48 PM
> > To: Quan, Evan
> > Cc: amd-gfx list ; Xu, Feifei
> > ; Kuehling, Felix ; Deucher,
> > Alexander ; Zhu, Rex ;
> > Zhang, Hawking
> > Subject: Re: [PATCH] drm/amd/powerplay: expose vega20 OD features
> >
> > On Fri, Aug 24, 2018 at 3:45 AM Evan Quan wrote:
> > >
> > > Vega20 simplifies the OD logics and it can not fit old OD interfaces.
> > > Thus we design new OD interfaces for vega20.
> >
> > Please split this into two patches, one to add the internal od8_settings
> > API,
> > and one to wire it up to sysfs. A few more comments below.
> >
> > >
> > > Change-Id: I888faec46a81287ae24f452ce16b42c1f6d06d7d
> > > Signed-off-by: Evan Quan
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 8 +
> > > drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 125
> > > .../gpu/drm/amd/include/kgd_pp_interface.h| 2 +
> > > drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 37
> > > .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c| 191
> > +-
> > > drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 +
> > > 6 files changed, 362 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> > > index ff24e1cc5b65..84b3e6f87abf 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
> > > @@ -357,6 +357,14 @@ enum amdgpu_pcie_gen {
> > > ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
> > > (adev)->powerplay.pp_handle, type, parameter,
> > > size))
> > >
> > > +#define amdgpu_dpm_get_od8_settings(adev, buf) \
> > > + ((adev)->powerplay.pp_funcs->get_od8_settings(\
> > > + (adev)->powerplay.pp_handle, buf))
> > > +
> > > +#define amdgpu_dpm_set_od8_settings(adev, parameter, size) \
> > > + ((adev)->powerplay.pp_funcs->set_od8_settings(\
> > > + (adev)->powerplay.pp_handle, parameter, size))
> > > +
> > > struct amdgpu_dpm {
> > > struct amdgpu_ps*ps;
> > > /* number of valid power states */ diff --git
> > > a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > index daa55fb06171..94cd7c503372 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
> > > @@ -934,6 +934,121 @@ static ssize_t amdgpu_get_busy_percent(struct
> > device *dev,
> > > return snprintf(buf, PAGE_SIZE, "%d\n", value); }
> > >
> > > +/**
> > > + * DOC: pp_od8_settings
> > > + *
> > > + * The amdgpu driver provides a sysfs API for adjusting the clocks,
> > > +voltages,
> > > + * power limit, fan speed and temperature. The pp_od8_settings is
> > > +used for
> > > + * this.
> > > + *
> > > + * Reading the file will display:
> > > + *
> > > + * - a name list of the
[PATCH] drm/amdgpu: remove extra newline when printing VM faults
Looks like a copy error to me. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 66abfcf87ad0..ad40acb236bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -265,7 +265,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, amdgpu_vm_get_task_info(adev, entry->pasid, _info); dev_err(adev->dev, - "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d\n)\n", + "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pasid:%u, for process %s pid %d thread %s pid %d)\n", entry->vmid_src ? "mmhub" : "gfxhub", entry->src_id, entry->ring_id, entry->vmid, entry->pasid, task_info.process_name, task_info.tgid, -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCHv2 5/5] drm/amdgpu: add DisplayPort CEC-Tunneling-over-AUX support
Add DisplayPort CEC-Tunneling-over-AUX support to amdgpu.
Signed-off-by: Hans Verkuil
Acked-by: Alex Deucher
Reviewed-by: Harry Wentland
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c| 9 -
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 800f481a6995..85f6c1546bff 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -896,6 +896,7 @@ amdgpu_dm_update_connector_after_detect(struct
amdgpu_dm_connector *aconnector)
aconnector->dc_sink = sink;
if (sink->dc_edid.length == 0) {
aconnector->edid = NULL;
+ drm_dp_cec_unset_edid(>dm_dp_aux.aux);
} else {
aconnector->edid =
(struct edid *) sink->dc_edid.raw_edid;
@@ -903,10 +904,13 @@ amdgpu_dm_update_connector_after_detect(struct
amdgpu_dm_connector *aconnector)
drm_connector_update_edid_property(connector,
aconnector->edid);
+ drm_dp_cec_set_edid(>dm_dp_aux.aux,
+ aconnector->edid);
}
amdgpu_dm_add_sink_to_freesync_module(connector,
aconnector->edid);
} else {
+ drm_dp_cec_unset_edid(>dm_dp_aux.aux);
amdgpu_dm_remove_sink_from_freesync_module(connector);
drm_connector_update_edid_property(connector, NULL);
aconnector->num_modes = 0;
@@ -1061,8 +1065,10 @@ static void handle_hpd_rx_irq(void *param)
(dc_link->type == dc_connection_mst_branch))
dm_handle_hpd_rx_irq(aconnector);
- if (dc_link->type != dc_connection_mst_branch)
+ if (dc_link->type != dc_connection_mst_branch) {
+ drm_dp_cec_irq(>dm_dp_aux.aux);
mutex_unlock(>hpd_lock);
+ }
}
static void register_hpd_handlers(struct amdgpu_device *adev)
@@ -2730,6 +2736,7 @@ static void amdgpu_dm_connector_destroy(struct
drm_connector *connector)
dm->backlight_dev = NULL;
}
#endif
+ drm_dp_cec_unregister_connector(>dm_dp_aux.aux);
drm_connector_unregister(connector);
drm_connector_cleanup(connector);
kfree(connector);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 9a300732ba37..18a3a6e5ffa0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -496,6 +496,8 @@ void amdgpu_dm_initialize_dp_connector(struct
amdgpu_display_manager *dm,
aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
drm_dp_aux_register(>dm_dp_aux.aux);
+ drm_dp_cec_register_connector(>dm_dp_aux.aux,
+ aconnector->base.name, dm->adev->dev);
aconnector->mst_mgr.cbs = _mst_cbs;
drm_dp_mst_topology_mgr_init(
>mst_mgr,
--
2.18.0
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[PATCHv2 3/5] drm_dp_mst_topology: fix broken drm_dp_sideband_parse_remote_dpcd_read()
When parsing the reply of a DP_REMOTE_DPCD_READ DPCD command the result is wrong due to a missing idx increment. This was never noticed since DP_REMOTE_DPCD_READ is currently not used, but if you enable it, then it is all wrong. Signed-off-by: Hans Verkuil Reviewed-by: Lyude Paul Acked-by: Alex Deucher --- drivers/gpu/drm/drm_dp_mst_topology.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 7780567aa669..5ff1d79b86c4 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -439,6 +439,7 @@ static bool drm_dp_sideband_parse_remote_dpcd_read(struct drm_dp_sideband_msg_rx if (idx > raw->curlen) goto fail_len; repmsg->u.remote_dpcd_read_ack.num_bytes = raw->msg[idx]; + idx++; if (idx > raw->curlen) goto fail_len; -- 2.18.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 4/5] drm/nouveau: add DisplayPort CEC-Tunneling-over-AUX support
Add DisplayPort CEC-Tunneling-over-AUX support to nouveau.
Signed-off-by: Hans Verkuil
Reviewed-by: Lyude Paul
Acked-by: Alex Deucher
---
drivers/gpu/drm/nouveau/nouveau_connector.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c
b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 51932c72334e..eb4f766b5958 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -400,8 +400,10 @@ nouveau_connector_destroy(struct drm_connector *connector)
kfree(nv_connector->edid);
drm_connector_unregister(connector);
drm_connector_cleanup(connector);
- if (nv_connector->aux.transfer)
+ if (nv_connector->aux.transfer) {
+ drm_dp_cec_unregister_connector(_connector->aux);
drm_dp_aux_unregister(_connector->aux);
+ }
kfree(connector);
}
@@ -608,6 +610,7 @@ nouveau_connector_detect(struct drm_connector *connector,
bool force)
nouveau_connector_set_encoder(connector, nv_encoder);
conn_status = connector_status_connected;
+ drm_dp_cec_set_edid(_connector->aux, nv_connector->edid);
goto out;
}
@@ -1108,11 +,14 @@ nouveau_connector_hotplug(struct nvif_notify *notify)
if (rep->mask & NVIF_NOTIFY_CONN_V0_IRQ) {
NV_DEBUG(drm, "service %s\n", name);
+ drm_dp_cec_irq(_connector->aux);
if ((nv_encoder = find_encoder(connector, DCB_OUTPUT_DP)))
nv50_mstm_service(nv_encoder->dp.mstm);
} else {
bool plugged = (rep->mask != NVIF_NOTIFY_CONN_V0_UNPLUG);
+ if (!plugged)
+ drm_dp_cec_unset_edid(_connector->aux);
NV_DEBUG(drm, "%splugged %s\n", plugged ? "" : "un", name);
if ((nv_encoder = find_encoder(connector, DCB_OUTPUT_DP))) {
if (!plugged)
@@ -1302,7 +1308,6 @@ nouveau_connector_create(struct drm_device *dev, int
index)
kfree(nv_connector);
return ERR_PTR(ret);
}
-
funcs = _connector_funcs;
break;
default:
@@ -1356,6 +1361,14 @@ nouveau_connector_create(struct drm_device *dev, int
index)
break;
}
+ switch (type) {
+ case DRM_MODE_CONNECTOR_DisplayPort:
+ case DRM_MODE_CONNECTOR_eDP:
+ drm_dp_cec_register_connector(_connector->aux,
+ connector->name, dev->dev);
+ break;
+ }
+
ret = nvif_notify_init(>disp.object, nouveau_connector_hotplug,
true, NV04_DISP_NTFY_CONN,
&(struct nvif_notify_conn_req_v0) {
--
2.18.0
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[PATCHv2 0/5] drm/nouveau+amdgpu: add DP CEC-Tunneling-over-AUX
From: Hans Verkuil Now that the DisplayPort CEC-Tunneling-over-AUX drm+i915 support has been merged in the mainline kernel it is time to roll this out to nouveau and amdgpu as well. The first patch is required for this: it adds checks that the drm_dp_cec functions are called with a working aux implementation. These checks weren't necessary for the i915, but nouveau and amdgpu require them. The next two patches update a comment in drm_dp_cec.c and fix a bug in sideband AUX handling that I found while researching CEC Tunneling over an MST hub. It's there to prevent others from stumbling over the same bug in the future. The fourth patch adds support for CEC to the nouveau driver. The last patch adds support for CEC to the amdgpu driver. CEC is only supported for the new DC modesetting code (thanks to Alex Deucher for explaining this to me). I have no plans to add CEC support to the old modesetting code (amd/amdgpu/dce*.c). If someone wants to, then please contact me. I can't test this myself, but I can assist. Changes since v1: - Added Acks/Reviewed-by tags - Removed a spurious non-functional change in patch 5 as pointed out by Harry Wentland. Two notes on CEC-Tunneling-over-AUX: 1) You need to be very careful about which USB-C/DP/mini-DP to HDMI adapters you buy. Only a few support this feature correctly today. Known chipsets that support this are Parade PS175 & PS176 and MegaChips 2900. Unfortunately almost all Parade-based adapters do not hook up the HDMI CEC pin to the chip, making them useless for this. The Parade reference design was only recently changed to hook up this pin, so perhaps this situation will change for new Parade-based adapters. Adapters based on the new MegaChips 2900 fare much better: it appears that their reference design *does* hook up the CEC pin. Club3D has adapters using this device for USB-C, DP and mini-DP to HDMI, and they all work fine. If anyone finds other adapters that work besides those I list in https://hverkuil.home.xs4all.nl/cec-status.txt, please let me know and I'll add them to the list. Linux is the first OS that supports this feature, so I am not surprised that HW support for this has been poor. Hopefully this will change going forward. BTW, note the irony that CEC is now supported for DP-to-HDMI adapters, but not for the native HDMI ports on NVIDIA/AMD/Intel GPUs. 2) CEC-Tunneling does not work (yet?) if there is an MST hub in between. I'm still researching this but this might be a limitation of MST. Regards, Hans PS: I've requested committer rights to drm-misc, so hopefully I can commit this series myself. Hans Verkuil (5): drm_dp_cec: check that aux has a transfer function drm_dp_cec: add note about good MegaChips 2900 CEC support drm_dp_mst_topology: fix broken drm_dp_sideband_parse_remote_dpcd_read() drm/nouveau: add DisplayPort CEC-Tunneling-over-AUX support drm/amdgpu: add DisplayPort CEC-Tunneling-over-AUX support .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 - .../display/amdgpu_dm/amdgpu_dm_mst_types.c| 2 ++ drivers/gpu/drm/drm_dp_cec.c | 18 +- drivers/gpu/drm/drm_dp_mst_topology.c | 1 + drivers/gpu/drm/nouveau/nouveau_connector.c| 17 +++-- 5 files changed, 43 insertions(+), 4 deletions(-) -- 2.18.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCHv2 2/5] drm_dp_cec: add note about good MegaChips 2900 CEC support
From: Hans Verkuil A big problem with DP CEC-Tunneling-over-AUX is that it is tricky to find adapters with a chipset that supports this AND where the manufacturer actually connected the HDMI CEC line to the chipset. Add a mention of the MegaChips 2900 chipset which seems to support this feature well. Signed-off-by: Hans Verkuil Reviewed-by: Lyude Paul Acked-by: Alex Deucher --- drivers/gpu/drm/drm_dp_cec.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/drm_dp_cec.c b/drivers/gpu/drm/drm_dp_cec.c index 1407b13a8d5d..8a718f85079a 100644 --- a/drivers/gpu/drm/drm_dp_cec.c +++ b/drivers/gpu/drm/drm_dp_cec.c @@ -16,7 +16,9 @@ * here. Quite a few active (mini-)DP-to-HDMI or USB-C-to-HDMI adapters * have a converter chip that supports CEC-Tunneling-over-AUX (usually the * Parade PS176), but they do not wire up the CEC pin, thus making CEC - * useless. + * useless. Note that MegaChips 2900-based adapters appear to have good + * support for CEC tunneling. Those adapters that I have tested using + * this chipset all have the CEC line connected. * * Sadly there is no way for this driver to know this. What happens is * that a /dev/cecX device is created that is isolated and unable to see -- 2.18.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCHv2 3/5] drm_dp_mst_topology: fix broken drm_dp_sideband_parse_remote_dpcd_read()
From: Hans Verkuil When parsing the reply of a DP_REMOTE_DPCD_READ DPCD command the result is wrong due to a missing idx increment. This was never noticed since DP_REMOTE_DPCD_READ is currently not used, but if you enable it, then it is all wrong. Signed-off-by: Hans Verkuil Reviewed-by: Lyude Paul Acked-by: Alex Deucher --- drivers/gpu/drm/drm_dp_mst_topology.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index 7780567aa669..5ff1d79b86c4 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -439,6 +439,7 @@ static bool drm_dp_sideband_parse_remote_dpcd_read(struct drm_dp_sideband_msg_rx if (idx > raw->curlen) goto fail_len; repmsg->u.remote_dpcd_read_ack.num_bytes = raw->msg[idx]; + idx++; if (idx > raw->curlen) goto fail_len; -- 2.18.0 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCHv2 1/5] drm_dp_cec: check that aux has a transfer function
From: Hans Verkuil
If aux->transfer == NULL, then just return without doing
anything. In that case the function is likely called for
a non-(e)DP connector.
This never happened for the i915 driver, but the nouveau and amdgpu
drivers need this check.
The alternative would be to add this check in those drivers before
every drm_dp_cec call, but it makes sense to check it in the
drm_dp_cec functions to prevent a kernel oops.
Signed-off-by: Hans Verkuil
Reviewed-by: Lyude Paul
Acked-by: Alex Deucher
---
drivers/gpu/drm/drm_dp_cec.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/drm_dp_cec.c b/drivers/gpu/drm/drm_dp_cec.c
index 988513346e9c..1407b13a8d5d 100644
--- a/drivers/gpu/drm/drm_dp_cec.c
+++ b/drivers/gpu/drm/drm_dp_cec.c
@@ -238,6 +238,10 @@ void drm_dp_cec_irq(struct drm_dp_aux *aux)
u8 cec_irq;
int ret;
+ /* No transfer function was set, so not a DP connector */
+ if (!aux->transfer)
+ return;
+
mutex_lock(>cec.lock);
if (!aux->cec.adap)
goto unlock;
@@ -293,6 +297,10 @@ void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const
struct edid *edid)
unsigned int num_las = 1;
u8 cap;
+ /* No transfer function was set, so not a DP connector */
+ if (!aux->transfer)
+ return;
+
#ifndef CONFIG_MEDIA_CEC_RC
/*
* CEC_CAP_RC is part of CEC_CAP_DEFAULTS, but it is stripped by
@@ -361,6 +369,10 @@ EXPORT_SYMBOL(drm_dp_cec_set_edid);
*/
void drm_dp_cec_unset_edid(struct drm_dp_aux *aux)
{
+ /* No transfer function was set, so not a DP connector */
+ if (!aux->transfer)
+ return;
+
cancel_delayed_work_sync(>cec.unregister_work);
mutex_lock(>cec.lock);
@@ -404,6 +416,8 @@ void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
const char *name,
struct device *parent)
{
WARN_ON(aux->cec.adap);
+ if (WARN_ON(!aux->transfer))
+ return;
aux->cec.name = name;
aux->cec.parent = parent;
INIT_DELAYED_WORK(>cec.unregister_work,
--
2.18.0
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Re: [PATCH] mm, oom: distinguish blockable mode for mmu notifiers
On 2018/08/24 22:52, Michal Hocko wrote:
> @@ -180,11 +180,15 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn)
> */
> static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable)
> {
> - if (blockable)
> - mutex_lock(>read_lock);
> - else if (!mutex_trylock(>read_lock))
> - return -EAGAIN;
> -
> + /*
> + * We can take sleepable lock even on !blockable mode because
> + * read_lock is only ever take from this path and the notifier
> + * lock never really sleeps. In fact the only reason why the
> + * later is sleepable is because the notifier itself might sleep
> + * in amdgpu_mn_invalidate_node but blockable mode is handled
> + * before calling into that path.
> + */
> + mutex_lock(>read_lock);
> if (atomic_inc_return(>recursion) == 1)
> down_read_non_owner(>lock);
> mutex_unlock(>read_lock);
>
I'm not following. Why don't we need to do like below (given that
nobody except amdgpu_mn_read_lock() holds ->read_lock) because e.g.
drm_sched_fence_create() from drm_sched_job_init() from amdgpu_cs_submit()
is doing GFP_KERNEL memory allocation with ->lock held for write?
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index e55508b..e1cb344 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -64,8 +64,6 @@
* @node: hash table node to find structure by adev and mn
* @lock: rw semaphore protecting the notifier nodes
* @objects: interval tree containing amdgpu_mn_nodes
- * @read_lock: mutex for recursive locking of @lock
- * @recursion: depth of recursion
*
* Data for each amdgpu device and process address space.
*/
@@ -85,8 +83,6 @@ struct amdgpu_mn {
/* objects protected by lock */
struct rw_semaphore lock;
struct rb_root_cached objects;
- struct mutexread_lock;
- atomic_trecursion;
};
/**
@@ -181,14 +177,9 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn)
static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable)
{
if (blockable)
- mutex_lock(>read_lock);
- else if (!mutex_trylock(>read_lock))
+ down_read(>lock);
+ else if (!down_read_trylock(>lock))
return -EAGAIN;
-
- if (atomic_inc_return(>recursion) == 1)
- down_read_non_owner(>lock);
- mutex_unlock(>read_lock);
-
return 0;
}
@@ -199,8 +190,7 @@ static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool
blockable)
*/
static void amdgpu_mn_read_unlock(struct amdgpu_mn *amn)
{
- if (atomic_dec_return(>recursion) == 0)
- up_read_non_owner(>lock);
+ up_read(>lock);
}
/**
@@ -410,8 +400,6 @@ struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev,
amn->type = type;
amn->mn.ops = _mn_ops[type];
amn->objects = RB_ROOT_CACHED;
- mutex_init(>read_lock);
- atomic_set(>recursion, 0);
r = __mmu_notifier_register(>mn, mm);
if (r)
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Re: [PATCH] mm, oom: distinguish blockable mode for mmu notifiers
Am 26.08.2018 um 10:40 schrieb Tetsuo Handa:
On 2018/08/24 22:52, Michal Hocko wrote:
@@ -180,11 +180,15 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn)
*/
static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable)
{
- if (blockable)
- mutex_lock(>read_lock);
- else if (!mutex_trylock(>read_lock))
- return -EAGAIN;
-
+ /*
+* We can take sleepable lock even on !blockable mode because
+* read_lock is only ever take from this path and the notifier
+* lock never really sleeps. In fact the only reason why the
+* later is sleepable is because the notifier itself might sleep
+* in amdgpu_mn_invalidate_node but blockable mode is handled
+* before calling into that path.
+*/
+ mutex_lock(>read_lock);
if (atomic_inc_return(>recursion) == 1)
down_read_non_owner(>lock);
mutex_unlock(>read_lock);
I'm not following. Why don't we need to do like below (given that
nobody except amdgpu_mn_read_lock() holds ->read_lock) because e.g.
drm_sched_fence_create() from drm_sched_job_init() from amdgpu_cs_submit()
is doing GFP_KERNEL memory allocation with ->lock held for write?
That's a bug which needs to be fixed separately.
Allocating memory with GFP_KERNEL while holding a lock which is also
taken in the reclaim code path is illegal not matter what you do.
Patches to fix this are already on the appropriate mailing list and will
be pushed upstream today.
Regards,
Christian.
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
index e55508b..e1cb344 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mn.c
@@ -64,8 +64,6 @@
* @node: hash table node to find structure by adev and mn
* @lock: rw semaphore protecting the notifier nodes
* @objects: interval tree containing amdgpu_mn_nodes
- * @read_lock: mutex for recursive locking of @lock
- * @recursion: depth of recursion
*
* Data for each amdgpu device and process address space.
*/
@@ -85,8 +83,6 @@ struct amdgpu_mn {
/* objects protected by lock */
struct rw_semaphore lock;
struct rb_root_cached objects;
- struct mutexread_lock;
- atomic_trecursion;
};
/**
@@ -181,14 +177,9 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn)
static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable)
{
if (blockable)
- mutex_lock(>read_lock);
- else if (!mutex_trylock(>read_lock))
+ down_read(>lock);
+ else if (!down_read_trylock(>lock))
return -EAGAIN;
-
- if (atomic_inc_return(>recursion) == 1)
- down_read_non_owner(>lock);
- mutex_unlock(>read_lock);
-
return 0;
}
@@ -199,8 +190,7 @@ static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable)
*/
static void amdgpu_mn_read_unlock(struct amdgpu_mn *amn)
{
- if (atomic_dec_return(>recursion) == 0)
- up_read_non_owner(>lock);
+ up_read(>lock);
}
/**
@@ -410,8 +400,6 @@ struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev,
amn->type = type;
amn->mn.ops = _mn_ops[type];
amn->objects = RB_ROOT_CACHED;
- mutex_init(>read_lock);
- atomic_set(>recursion, 0);
r = __mmu_notifier_register(>mn, mm);
if (r)
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