[PATCH 385/459] drm/amd/display: Properly guard display_mode_vba with DCN2
From: Leo Li
[Why]
display_mode_vba is for DCN2 and up. When building for upstream (DCN1
enabled only), there will be a build error, since display_mode_vba.c/h
is stripped out.
Note that building DCN1 only with internal dal-dev is still fine, since
display_mode_vba.h is not stripped out internally - only in upstream.
The make directives therefore stll work, and so will any #include's.
[How]
Since subsequent generations require DCN2 enabled anyways, guard the
makefile directive for display_mode_vba.o with DCN2. Guard any includes
with DCN2. In addition, guard the entire contents of display_mode_vba.h
with DCN2, to simulate the file being stripped out in upstream.
A forward declaration for 'struct display_mode_lib' also needs to be
added in display_mode_lib.h. Previously, display_mode_vba.h contained
the forward declaration, and display_mode_lib.h in turn included it.
This won't work if mode_vba.h is stripped out, requring mode_lib.h to do
so itself.
Signed-off-by: Leo Li
Reviewed-by: Harry Wentland
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dml/Makefile | 7 ---
drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h | 4
drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 3 +++
3 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile
b/drivers/gpu/drm/amd/display/dc/dml/Makefile
index 744fefb67789..0bb7a20675c4 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile
@@ -33,8 +33,9 @@ endif
dml_ccflags := -mhard-float -msse $(cc_stack_align)
CFLAGS_display_mode_lib.o := $(dml_ccflags)
-CFLAGS_display_mode_vba.o := $(dml_ccflags)
+
ifdef CONFIG_DRM_AMD_DC_DCN2_0
+CFLAGS_display_mode_vba.o := $(dml_ccflags)
CFLAGS_display_mode_vba_20.o := $(dml_ccflags)
CFLAGS_display_rq_dlg_calc_20.o := $(dml_ccflags)
endif
@@ -46,10 +47,10 @@ CFLAGS_display_rq_dlg_helpers.o := $(dml_ccflags)
CFLAGS_dml_common_defs.o := $(dml_ccflags)
DML = display_mode_lib.o display_rq_dlg_helpers.o dml1_display_rq_dlg_calc.o \
- dml_common_defs.o display_mode_vba.o
+ dml_common_defs.o
ifdef CONFIG_DRM_AMD_DC_DCN2_0
-DML += dcn20/display_rq_dlg_calc_20.o dcn20/display_mode_vba_20.o
+DML += display_mode_vba.o dcn20/display_rq_dlg_calc_20.o
dcn20/display_mode_vba_20.o
endif
AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
index f2331c09fad8..61541c431110 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h
@@ -27,7 +27,9 @@
#include "dml_common_defs.h"
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
#include "display_mode_vba.h"
+#endif
enum dml_project {
DML_PROJECT_UNDEFINED,
@@ -37,6 +39,8 @@ enum dml_project {
#endif
};
+struct display_mode_lib;
+
struct dml_funcs {
void (*rq_dlg_get_dlg_reg)(
struct display_mode_lib *mode_lib,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 38fc0ab32d7b..4e0183dd634a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -23,6 +23,8 @@
*
*/
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+
#ifndef __DML2_DISPLAY_MODE_VBA_H__
#define __DML2_DISPLAY_MODE_VBA_H__
@@ -847,3 +849,4 @@ double CalculateWriteBackDISPCLK(
unsigned int WritebackChromaLineBufferWidth);
#endif /* _DML2_DISPLAY_MODE_VBA_H_ */
+#endif
--
2.20.1
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[PATCH 360/459] drm/amd/display: enable DSC support by default
From: Hawking Zhang Signed-off-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 9cb2211edf4c..33e7efbb4ef4 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -26,7 +26,7 @@ config DRM_AMD_DC_DCN2_0 config DRM_AMD_DC_DSC_SUPPORT bool "DSC support" - default n + default y depends on DRM_AMD_DC && X86 depends on DRM_AMD_DC_DCN1_0 depends on DRM_AMD_DC_DCN2_0 -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 359/459] drm/amd/display: navi10 bring up skip dsc encoder config
From: hersen wu
Signed-off-by: hersen wu
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
index c3c218805eb1..130b01801a26 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
@@ -286,6 +286,14 @@ static void enc2_dp_set_dsc_config(struct stream_encoder
*enc,
uint8_t *dsc_packed_pps)
{
struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
+ uint32_t dsc_value = 0;
+
+ dsc_value = REG_READ(DP_DSC_CNTL);
+
+ /* dsc disable skip */
+ if ((dsc_value & 0x3) == 0x0)
+ return;
+
REG_UPDATE_2(DP_DSC_CNTL,
DP_DSC_MODE, dsc_mode,
--
2.20.1
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[PATCH 368/459] drm/amd/display: Properly set u clock
From: Aidan Wood [Why] u clk set request was being sent in units of mts, when it needed to be in units of Mhz [How] add a division by 16 to convert from mts to Mhz Signed-off-by: Aidan Wood Reviewed-by: Jun Lei Acked-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c index 6bc4b3f3301f..7aa2859b35fc 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c @@ -2132,7 +2132,7 @@ bool dcn20_validate_bandwidth(struct dc *dc, context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; - context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000; + context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000; context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; context->bw_ctx.bw.dcn.clk.p_state_change_support = -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 376/459] drm/amd/display: isolate global double buffer lock programming
From: Wenjing Liu
[why]
Global optic double buffer lock is currently disabled due to
incorrect programming sequence that affects non global lock.
[how]
Isolate global lock programming sequence out of non global lock
programming sequence, so it can be enabled without affecting
non global lock.
Signed-off-by: Wenjing Liu
Reviewed-by: Jun Lei
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/dcn20/dcn20_hwseq.c| 19 +++---
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 60 ++-
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 5 +-
.../amd/display/dc/inc/hw/timing_generator.h | 4 +-
4 files changed, 35 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 0cad51ece06e..542f144f807f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -727,10 +727,6 @@ enum dc_status dcn20_enable_stream_timing(
pipe_ctx->stream->signal,
true);
- if (pipe_ctx->stream_res.tg->funcs->setup_global_lock)
- pipe_ctx->stream_res.tg->funcs->setup_global_lock(
- pipe_ctx->stream_res.tg);
-
/* program otg blank color */
color_space = stream->output_color_space;
color_space_to_black_color(dc, color_space, _color);
@@ -1227,10 +1223,19 @@ static void dcn20_pipe_control_lock_global(
struct pipe_ctx *pipe,
bool lock)
{
- if (lock)
- pipe->stream_res.tg->funcs->lock_global(pipe->stream_res.tg);
- else
+ if (lock) {
+ pipe->stream_res.tg->funcs->lock_doublebuffer_enable(
+ pipe->stream_res.tg);
+ pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
+ } else {
pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
+ pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
+ CRTC_STATE_VACTIVE);
+ pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
+ CRTC_STATE_VBLANK);
+ pipe->stream_res.tg->funcs->lock_doublebuffer_disable(
+ pipe->stream_res.tg);
+ }
}
static void dcn20_pipe_control_lock(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 34f5a7d671b2..43e71b4ab5e8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -330,64 +330,42 @@ void optc2_triplebuffer_unlock(struct timing_generator
*optc)
}
-void optc2_setup_global_lock(struct timing_generator *optc)
+void optc2_lock_doublebuffer_enable(struct timing_generator *optc)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
uint32_t v_blank_start = 0;
- uint32_t h_blank_start = 0, h_total = 0;
+ uint32_t h_blank_start = 0;
- REG_SET(OTG_GLOBAL_CONTROL2, 0, DIG_UPDATE_LOCATION, 20);
+ REG_UPDATE(OTG_GLOBAL_CONTROL1, MASTER_UPDATE_LOCK_DB_EN, 1);
+
+ REG_UPDATE_2(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1,
+ DIG_UPDATE_LOCATION, 20);
REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START, _blank_start);
REG_GET(OTG_H_BLANK_START_END, OTG_H_BLANK_START, _blank_start);
- REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, _total);
REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
MASTER_UPDATE_LOCK_DB_X,
- 0,
+ h_blank_start - 200 - 1,
MASTER_UPDATE_LOCK_DB_Y,
v_blank_start - 1);
}
-void optc2_lock_global(struct timing_generator *optc)
+void optc2_lock_doublebuffer_disable(struct timing_generator *optc)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
- REG_SET(OTG_GLOBAL_CONTROL1, 0, MASTER_UPDATE_LOCK_DB_EN, 1);
-
- REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1);
-
- REG_SET(OTG_GLOBAL_CONTROL0, 0,
- OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
- REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
- OTG_MASTER_UPDATE_LOCK, 1);
-
- /* Should be fast, status does not update on maximus */
- if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
- REG_WAIT(OTG_MASTER_UPDATE_LOCK,
- UPDATE_LOCK_STATUS, 1,
- 1, 10);
-}
-
-void optc2_lock(struct timing_generator *optc)
-{
- struct optc *optc1 = DCN10TG_FROM_TG(optc);
-
- REG_SET(OTG_GLOBAL_CONTROL1, 0, MASTER_UPDATE_LOCK_DB_EN, 0);
+ REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
+ MASTER_UPDATE_LOCK_DB_X,
+ 0,
+
[PATCH 352/459] drm/amd/display: Refactor clk_mgr functions
From: Eric Yang
[Why]
Some HW specific implementations can be pulled out into clk_mgr.c.
[How]
- Pull get_active_display_cnt out to clk_mgr.
- Pull out shared logic in set_dispclk and set_dprefclk
Signed-off-by: Eric Yang
Reviewed-by: Tony Cheng
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 25
.../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c| 25 +---
.../dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c | 58 ++-
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 43 +-
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h | 2 +
5 files changed, 71 insertions(+), 82 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index 27d407a9b452..06e73ce45ed0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -36,6 +36,31 @@
#include "dcn10/rv2_clk_mgr.h"
#include "dcn20/dcn20_clk_mgr.h"
+
+int clk_mgr_helper_get_active_display_cnt(
+ struct dc *dc,
+ struct dc_state *context)
+{
+ int i, display_count;
+
+ display_count = 0;
+ for (i = 0; i < context->stream_count; i++) {
+ const struct dc_stream_state *stream = context->streams[i];
+
+ /*
+* Only notify active stream or virtual stream.
+* Need to notify virtual stream to work around
+* headless case. HPD does not fire when system is in
+* S0i2.
+*/
+ if (!stream->dpms_off || stream->signal == SIGNAL_TYPE_VIRTUAL)
+ display_count++;
+ }
+
+ return display_count;
+}
+
+
struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs
*pp_smu, struct dccg *dccg)
{
struct hw_asic_id asic_id = ctx->asic_id;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
index a3f953c8839d..31db9b55e11a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr.c
@@ -114,29 +114,6 @@ static void ramp_up_dispclk_with_dpp(struct
clk_mgr_internal *clk_mgr, struct dc
clk_mgr->base.clks.max_supported_dppclk_khz =
new_clocks->max_supported_dppclk_khz;
}
-static int get_active_display_cnt(
- struct dc *dc,
- struct dc_state *context)
-{
- int i, display_count;
-
- display_count = 0;
- for (i = 0; i < context->stream_count; i++) {
- const struct dc_stream_state *stream = context->streams[i];
-
- /*
-* Only notify active stream or virtual stream.
-* Need to notify virtual stream to work around
-* headless case. HPD does not fire when system is in
-* S0i2.
-*/
- if (!stream->dpms_off || stream->signal == SIGNAL_TYPE_VIRTUAL)
- display_count++;
- }
-
- return display_count;
-}
-
static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
struct dc_state *context,
bool safe_to_lower)
@@ -156,7 +133,7 @@ static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
pp_smu = _mgr->pp_smu->rv_funcs;
- display_count = get_active_display_cnt(dc, context);
+ display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
if (display_count == 0)
enter_display_off = true;
diff --git
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
index 196087072063..1897e91c8ccb 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c
@@ -68,57 +68,59 @@ static const struct IP_BASE MP1_BASE = { { { { 0x00016000,
0, 0, 0, 0 } },
#define VBIOSSMC_MSG_SetDispclkFreq 0x4
#define VBIOSSMC_MSG_SetDprefclkFreq 0x5
-int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int
requested_dispclk_khz)
+int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
unsigned int msg_id, unsigned int param)
{
-
- int actual_dispclk_set_khz = -1;
- struct dc *core_dc = clk_mgr->base.ctx->dc;
- struct dmcu *dmcu = core_dc->res_pool->dmcu;
-
/* First clear response register */
- //dm_write_reg(ctx, mmMP1_SMN_C2PMSG_91, 0);
REG_WRITE(MP1_SMN_C2PMSG_91, 0);
/* Set the parameter register for the SMU message, unit is Mhz */
- //dm_write_reg(ctx, mmMP1_SMN_C2PMSG_83, requested_dispclk_khz / 1000);
- REG_WRITE(MP1_SMN_C2PMSG_83, requested_dispclk_khz / 1000);
+ REG_WRITE(MP1_SMN_C2PMSG_83, param);
/* Trigger the
[PATCH 366/459] drm/amd/display: Calculate link bandwidth in a common function
From: Nikola Cornij
[why]
Currently link bandwidth is calculated in various places using the same
multi-step formula. Doing this in one common place makes sure the same
formula will indeed be applied to all link bandwidth calculations.
It also makes it possible to apply link-setting-specific adjustments
that affect effective link bandwidth.
[how]
Replace all implementations of link bandwidth calculation with a call
to a function.
Signed-off-by: Nikola Cornij
Reviewed-by: Nikola Cornij
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c| 5 -
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c | 3 ++-
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 14 +-
3 files changed, 7 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 2a9f4661540c..4c31930f1cdf 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2390,11 +2390,6 @@ static struct fixed31_32 get_pbn_per_slot(struct
dc_stream_state *stream)
>link->cur_link_settings);
link_rate_in_mbytes_per_sec /= 8000; /* Kbits to MBytes */
-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
- if (stream->link->fec_state != dc_link_fec_not_ready)
- link_rate_in_mbytes_per_sec = (link_rate_in_mbytes_per_sec *
970)/1000;
-#endif
-
mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
return dc_fixpt_div_int(mbytes_per_sec, 54);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
index d17accc2e009..4865cc341dec 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c
@@ -225,6 +225,7 @@ static void dsc2_disable(struct display_stream_compressor
*dsc)
static void dsc_log_pps(struct display_stream_compressor *dsc, struct
drm_dsc_config *pps)
{
int i;
+ int bits_per_pixel = pps->bits_per_pixel;
DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):");
DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major);
@@ -235,7 +236,7 @@ static void dsc_log_pps(struct display_stream_compressor
*dsc, struct drm_dsc_co
DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb);
DC_LOG_DSC("\tsimple_422 %d", pps->simple_422);
DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable);
- DC_LOG_DSC("\tbits_per_pixel %d", pps->bits_per_pixel);
+ DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel,
bits_per_pixel / 16, ((bits_per_pixel % 16) * 1) / 16);
DC_LOG_DSC("\tpic_height %d", pps->pic_height);
DC_LOG_DSC("\tpic_width %d", pps->pic_width);
DC_LOG_DSC("\tslice_height %d", pps->slice_height);
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 4ffcc2844d19..9e9c77e472e1 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -849,15 +849,11 @@ bool
dc_check_and_fit_timing_into_bandwidth_with_dsc_legacy(
{
int requiredBandwidth_Kbps;
bool stream_fits_into_bandwidth = false;
- int link_rate_kbytes_per_sec = link->verified_link_cap.link_rate *
LINK_RATE_REF_FREQ_IN_KHZ;
- int total_link_bandwdith_kbps = link->verified_link_cap.lane_count *
link_rate_kbytes_per_sec * 8;
-
- if (link->preferred_link_setting.lane_count !=
- LANE_COUNT_UNKNOWN &&
- link->preferred_link_setting.link_rate !=
- LINK_RATE_UNKNOWN) {
- link_rate_kbytes_per_sec =
link->preferred_link_setting.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
- total_link_bandwdith_kbps =
link->preferred_link_setting.lane_count * link_rate_kbytes_per_sec * 8;
+ int total_link_bandwdith_kbps = dc_link_bandwidth_kbps(link,
>verified_link_cap);
+
+ if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
+ link->preferred_link_setting.link_rate !=
LINK_RATE_UNKNOWN) {
+ total_link_bandwdith_kbps = dc_link_bandwidth_kbps(link,
>preferred_link_setting);
}
timing->flags.DSC = 0;
--
2.20.1
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[PATCH 378/459] drm/amd/display: Make sure DSC slice height is divisible by 2 for 4:2:0 color format
From: Nikola Cornij
[why] DSC spec requires this
Signed-off-by: Nikola Cornij
Reviewed-by: Wenjing Liu
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index c649f62d183d..6357325d3c90 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -658,14 +658,23 @@ static bool setup_dsc_config(
dsc_cfg->num_slices_h = num_slices_h;
slice_width = pic_width / num_slices_h;
- // Vertical number of slices: start from policy and pick the first one
that height is divisible by
+ // Vertical number of slices: start from policy and pick the first one
that height is divisible by.
+ // For 4:2:0 make sure the slice height is divisible by 2 as well.
pic_height = timing->v_addressable + timing->v_border_top +
timing->v_border_bottom;
num_slices_v = dsc_policy.num_slices_v;
if (num_slices_v < 1)
num_slices_v = 1;
- while (num_slices_v >= 1 && (pic_height % num_slices_v != 0))
+ while (num_slices_v >= 1) {
+ if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) {
+ int slice_height = pic_height / num_slices_v;
+ if (pic_height % num_slices_v == 0 && slice_height % 2
== 0)
+ break;
+ } else if (pic_height % num_slices_v == 0)
+ break;
+
num_slices_v--;
+ }
dsc_cfg->num_slices_v = num_slices_v;
--
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[PATCH 371/459] drm/amd/display: remove legacy DSC functions
From: Wenjing Liu
[why]
Clean up some dsc legacy functions that are
no longer needed.
[how]
remove two dsc functions in dc_dsc, use dc_bandwidth_in_kbps_from_timing
instead of calc_required_bandwidth_for_timing.
Signed-off-by: Wenjing Liu
Reviewed-by: Nikola Cornij
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dc_dsc.h | 10 --
drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 123 ++--
2 files changed, 9 insertions(+), 124 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index c3a277c11489..2cba6bd7937a 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -47,15 +47,5 @@ bool dc_dsc_compute_config(
int target_bandwidth,
const struct dc_crtc_timing *timing,
struct dc_dsc_config *dsc_cfg);
-
-bool dc_check_and_fit_timing_into_bandwidth_with_dsc_legacy(
- const struct dc *pDC,
- const struct dc_link *link,
- struct dc_crtc_timing *timing);
-
-bool dc_setup_dsc_in_timing_legacy(const struct dc *pDC,
- const struct dsc_dec_dpcd_caps *dsc_sink_caps,
- int available_bandwidth_kbps,
- struct dc_crtc_timing *timing);
#endif
#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 9e9c77e472e1..fe63af836f1e 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -231,66 +231,6 @@ static bool dc_intersect_dsc_caps(
return true;
}
-// TODO DSC: Can this be moved to a common helper module and replace
WindowsDM::calcRequiredBandwidthForTiming()?
-static int bpp_from_dc_color_depth(enum dc_color_depth color_depth)
-{
- int bits_per_pixel;
-
- // Get color depth in bits per pixel
- switch (color_depth) {
- case COLOR_DEPTH_UNDEFINED:
- bits_per_pixel = 0;
- break;
- case COLOR_DEPTH_666:
- bits_per_pixel = 6;
- break;
- case COLOR_DEPTH_888:
- bits_per_pixel = 8;
- break;
- case COLOR_DEPTH_101010:
- bits_per_pixel = 10;
- break;
- case COLOR_DEPTH_121212:
- bits_per_pixel = 12;
- break;
- case COLOR_DEPTH_141414:
- bits_per_pixel = 14;
- break;
- case COLOR_DEPTH_161616:
- bits_per_pixel = 16;
- break;
- case COLOR_DEPTH_999:
- bits_per_pixel = 9;
- break;
- case COLOR_DEPTH_11:
- bits_per_pixel = 11;
- break;
- case COLOR_DEPTH_COUNT:
- default:
- bits_per_pixel = 0;
- break;
- }
-
- return bits_per_pixel;
-}
-
-// TODO DSC: Can this be moved to a common helper module and replace
WindowsDM::calcRequiredBandwidthForTiming()?
-static int calc_required_bandwidth_for_timing(const struct dc_crtc_timing
*crtc_timing)
-{
- int timing_bandwidth_kbps = 0;
- int bits_per_pixel =
bpp_from_dc_color_depth(crtc_timing->display_color_depth);
-
- if (crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB ||
- crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444)
- timing_bandwidth_kbps = crtc_timing->pix_clk_100hz *
bits_per_pixel * 3 / 10;
- else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
- timing_bandwidth_kbps = crtc_timing->pix_clk_100hz * 8 * 3 / 10;
- else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
- timing_bandwidth_kbps = crtc_timing->pix_clk_100hz *
bits_per_pixel * 3 / 20;
-
- return timing_bandwidth_kbps;
-}
-
struct dc_dsc_policy {
float max_compression_ratio_legacy;
float sst_compression_legacy; // Maximum quality if 0.0
@@ -346,7 +286,7 @@ static void get_dsc_bandwidth_range(
struct dc_dsc_bw_range *range)
{
/* native stream bandwidth */
- range->stream_kbps = calc_required_bandwidth_for_timing(timing);
+ range->stream_kbps = dc_bandwidth_in_kbps_from_timing(timing);
/* max dsc target bpp */
range->max_kbps = dsc_round_up(policy->max_target_bpp *
timing->pix_clk_100hz);
@@ -367,6 +307,13 @@ static void get_dsc_bandwidth_range(
}
}
+/* Decides if DSC should be used and calculates target bpp if it should,
applying DSC policy.
+ *
+ * Returns:
+ * - 'true' if DSC was required by policy and was successfully applied
+ * - 'false' if DSC was not necessary (e.g. if uncompressed stream fits
'target_bandwidth'),
+ *or if it couldn't be applied based on DSC policy.
+ */
static bool decide_dsc_target_bpp_x16(
const struct dc_dsc_policy *policy,
const struct dsc_enc_caps
[PATCH 367/459] drm/amd/display: Properly set DCF clock
From: Aidan Wood
[Why]
If num_states == 0 we did update_bound_box which doesn't updated any max
clocks if num_states == 0, therefore we need to do cap_soc_clocks
instead, also SMU cannot set DCF clock to a higher than or equal to freq
than SOC clock
[How]
Add a num_states != 0 check for update_bounding_box to be run, and after
we run get_maximum_sustainable_clocks we now check if the reported max
value of DCF is higher than SOC and if necessary set it to 1000
(becomes 1 after division by 1000) lower than SOC
Signed-off-by: Aidan Wood
Reviewed-by: Aric Cyr
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 49114d823240..6bc4b3f3301f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2611,11 +2611,14 @@ static bool init_soc_bounding_box(struct dc *dc,
if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
{
status =
(*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
(>base.pp_smu->nv_funcs.pp_smu,
_clocks);
-
+ /* SMU cannot set DCF clock to anything equal to or
higher than SOC clock
+*/
+ if (max_clocks.dcfClockInKhz >=
max_clocks.socClockInKhz)
+ max_clocks.dcfClockInKhz =
max_clocks.socClockInKhz - 1000;
clock_limits_available = (status == PP_SMU_RESULT_OK);
}
- if (clock_limits_available && uclk_states_available)
+ if (clock_limits_available && uclk_states_available &&
num_states)
update_bounding_box(dc, _0_soc, _clocks,
uclk_states, num_states);
else if (clock_limits_available)
cap_soc_clocks(_0_soc, max_clocks);
--
2.20.1
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[PATCH 370/459] drm/amd/display: Remove dependency on pipe->plane for immedaite flip status
From: Joshua Aberback
[Why]
dcn20_apply_ctx_for_surface can be called with 0 planes, which means we
should blank the display. In this case when we get down to
dcn20_setup_gsl_group_as_lock, pipe_ctx->plane_state is NULL, but we don't
check for it. However, this function is only called by
dcn20_pipe_control_lock, and in that function we alraedy have a local for
the immediate flip status, which is what we care about in the plane state.
[How]
- pass in immediate flip status as parameter
Signed-off-by: Joshua Aberback
Reviewed-by: Krunoslav Kovac
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 9 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h | 3 ++-
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index ccb9f277911a..0cad51ece06e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1255,7 +1255,7 @@ static void dcn20_pipe_control_lock(
if (lock && pipe->bottom_pipe != NULL)
if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
(!flip_immediate && pipe->stream_res.gsl_group > 0))
- dcn20_setup_gsl_group_as_lock(dc, pipe);
+ dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips)
{
if (lock)
@@ -1890,14 +1890,15 @@ static int find_free_gsl_group(const struct dc *dc)
*/
void dcn20_setup_gsl_group_as_lock(
const struct dc *dc,
- struct pipe_ctx *pipe_ctx)
+ struct pipe_ctx *pipe_ctx,
+ bool flip_immediate)
{
struct gsl_params gsl;
int group_idx;
memset(, 0, sizeof(struct gsl_params));
- if (pipe_ctx->plane_state->flip_immediate) {
+ if (flip_immediate) {
/* return if group already assigned since GSL was set up
* for vsync flip, we would unassign so it can't be "left over"
*/
@@ -1964,7 +1965,7 @@ void dcn20_setup_gsl_group_as_lock(
pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
pipe_ctx->stream_res.tg, group_idx,
- pipe_ctx->plane_state->flip_immediate ? 4 : 0);
+ flip_immediate ? 4 : 0);
} else
BREAK_TO_DEBUGGER();
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
index aba6f87c7f2b..37699df685ee 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
@@ -85,6 +85,7 @@ void dcn20_program_tripleBuffer(
void dcn20_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx);
void dcn20_setup_gsl_group_as_lock(const struct dc *dc,
- struct pipe_ctx *pipe_ctx);
+ struct pipe_ctx *pipe_ctx,
+ bool flip_immediate);
#endif /* __DC_HWSS_DCN20_H__ */
--
2.20.1
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[PATCH 381/459] drm/amd/display: Fix DCFCLK and SOCCLK not set
From: Ilya Bakoulin
[Why]
If voltage level > 0, DCFCLK and SOCCLK could be 0 during DML
calculations, which ended up causing an assert.
[How]
Initialize dcfclk_mhz and socclk_mhz values according to the
voltage level.
Signed-off-by: Ilya Bakoulin
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index aa04df64522f..dc3aa7debad5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2136,6 +2136,10 @@ bool dcn20_validate_bandwidth(struct dc *dc,
if (pipe_cnt != pipe_idx)
pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
>res_ctx, pipes);
+ pipes[0].clks_cfg.voltage = vlevel;
+ pipes[0].clks_cfg.dcfclk_mhz =
context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
+ pipes[0].clks_cfg.socclk_mhz =
context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
+
/* only pipe 0 is read for voltage and dcf/soc clocks */
if (vlevel < 1) {
pipes[0].clks_cfg.voltage = 1;
--
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[PATCH 374/459] drm/amd/display: move dsc clock from plane_resource to stream_resource
From: Tony Cheng
Signed-off-by: Tony Cheng
Reviewed-by: Dmytro Laktyushkin
Acked-by: Bhawanpreet Lakha
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
drivers/gpu/drm/amd/display/dc/inc/core_types.h | 5 ++---
2 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 33f1a1d972a9..aa04df64522f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2204,7 +2204,7 @@ bool dcn20_validate_bandwidth(struct dc *dc,
context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
- context->res_ctx.pipe_ctx[i].plane_res.bw.dscclk_khz =
+ context->res_ctx.pipe_ctx[i].stream_res.dscclk_khz =
context->bw_ctx.dml.vba.DSCCLK_calculated[pipe_idx] * 1000;
#endif
context->res_ctx.pipe_ctx[i].pipe_dlg_param =
pipes[pipe_idx].pipe.dest;
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 2d551a6848f5..e94f3c180144 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -222,15 +222,14 @@ struct resource_pool {
struct dcn_fe_bandwidth {
int dppclk_khz;
-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
- int dscclk_khz;
-#endif
+
};
struct stream_resource {
struct output_pixel_processor *opp;
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
struct display_stream_compressor *dsc;
+ int dscclk_khz;
#endif
struct timing_generator *tg;
struct stream_encoder *stream_enc;
--
2.20.1
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[PATCH 361/459] drm/amd/display: Disconnect DCN2 mpcc when changing tg
From: Leo Li
A previous fix was done for DCN1 that needed to be ported to DCN2:
60c677534e73 ("drm/amd/display: Disconnect mpcc when changing tg")
Signed-off-by: Leo Li
Acked-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index f6e25f75a0a9..f2e5e4928119 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1323,9 +1323,10 @@ static void dcn20_apply_ctx_for_surface(
}
}
- if (!pipe_ctx->plane_state &&
- old_pipe_ctx->plane_state &&
- old_pipe_ctx->stream_res.tg == tg) {
+ if ((!pipe_ctx->plane_state ||
+pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) &&
+old_pipe_ctx->plane_state &&
+old_pipe_ctx->stream_res.tg == tg) {
dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
removed_pipe[i] = true;
--
2.20.1
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[PATCH 358/459] drm/amd/display: skip dsc config for navi10 bring up
From: hersen wu
[why] we meet a bug when program dsc register even dsc mode is not
enabled. disable dsc config for now. we will re-visit this issue.
Signed-off-by: hersen wu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 9 +
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 724b5a9e47d0..34f5a7d671b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -191,6 +191,15 @@ void optc2_set_dsc_config(struct timing_generator *optc,
uint32_t dsc_slice_width)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
+ uint32_t data_format = 0;
+ /* skip if dsc mode is not changed */
+ data_format = dm_read_reg(CTX, REG(OPTC_DATA_FORMAT_CONTROL));
+
+ data_format = data_format & 0x30; /* bit5:4 */
+ data_format = data_format >> 4;
+
+ if (data_format == dsc_mode)
+ return;
REG_UPDATE(OPTC_DATA_FORMAT_CONTROL,
OPTC_DSC_MODE, dsc_mode);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index c4fa0b9e7138..e2a6e80013f3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -670,7 +670,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.max_downscale_src_width = 5120,/*upto 5K*/
.disable_pplib_wm_range = false,
.scl_reset_length10 = true,
- .sanity_checks = true,
+ .sanity_checks = false,
.disable_tri_buf = true,
};
--
2.20.1
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[PATCH 354/459] drm/amd/display: fix pstate allow handling in dcn2
From: Jun Lei
[why]
pstate allow/block is not being handled properly on DCN2
[how]
DML needs to be updated to calculate pstate support at both min and max
mpc combine rather than just min
clock manager needs to update current to new pstate support before
sending to pplib/smu
Signed-off-by: Jun Lei
Reviewed-by: Dmytro Laktyushkin
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 7 +--
.../amd/display/dc/dml/dcn20/display_mode_vba_20.c | 12
2 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 5814cacbe1be..34402dffd2ca 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -191,10 +191,13 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
pp_smu->set_hard_min_socclk_by_freq(_smu->pp_smu,
clk_mgr_base->clks.socclk_khz / 1000);
}
- if (!safe_to_lower && pp_smu && pp_smu->set_pstate_handshake_support)
+ if (!safe_to_lower && pp_smu && pp_smu->set_pstate_handshake_support) {
+ clk_mgr_base->clks.p_state_change_support = false;
pp_smu->set_pstate_handshake_support(_smu->pp_smu, false);
- else if (safe_to_lower && pp_smu &&
pp_smu->set_pstate_handshake_support)
+ } else if (safe_to_lower && pp_smu &&
pp_smu->set_pstate_handshake_support) {
+ clk_mgr_base->clks.p_state_change_support =
new_clocks->p_state_change_support;
pp_smu->set_pstate_handshake_support(_smu->pp_smu,
clk_mgr_base->clks.p_state_change_support);
+ }
if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz,
clk_mgr_base->clks.dramclk_khz)) {
clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index b7edb39cd902..21d90c6f3c88 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -2592,8 +2592,9 @@ static void
dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
mode_lib->vba.DRAMClockChangeSupport[0][0] =
dm_dram_clock_change_unsupported;
}
}
- for (k = 1; k <= mode_lib->vba.soc.num_states; k++)
- mode_lib->vba.DRAMClockChangeSupport[k][0] =
mode_lib->vba.DRAMClockChangeSupport[0][0];
+ for (k = 0; k <= mode_lib->vba.soc.num_states; k++)
+ for (j = 0; j < 2; j++)
+ mode_lib->vba.DRAMClockChangeSupport[k][j] =
mode_lib->vba.DRAMClockChangeSupport[0][0];
//XFC Parameters:
for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
@@ -5061,12 +5062,7 @@ void dml20_ModeSupportAndSystemConfigurationFull(struct
display_mode_lib *mode_l
if (locals->ModeSupport[i][0] == true ||
locals->ModeSupport[i][1] == true) {
mode_lib->vba.VoltageLevel = i;
if (locals->ModeSupport[i][1] == true &&
(locals->ModeSupport[i][0] == false
- ||
mode_lib->vba.WhenToDoMPCCombine == dm_mpc_always_when_possible
- ||
(mode_lib->vba.WhenToDoMPCCombine == dm_mpc_reduce_voltage_and_clocks
- &&
((locals->DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vactive
- &&
locals->DRAMClockChangeSupport[i][0] != dm_dram_clock_change_vactive)
- ||
(locals->DRAMClockChangeSupport[i][1] == dm_dram_clock_change_vblank
- &&
locals->DRAMClockChangeSupport[i][0] == dm_dram_clock_change_unsupported) {
+ ||
mode_lib->vba.WhenToDoMPCCombine == dm_mpc_always_when_possible)) {
MaximumMPCCombine = 1;
} else {
MaximumMPCCombine = 0;
--
2.20.1
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[PATCH 344/459] drm/amd/display: Program VTG params after programming Global Sync for DCN2
From: Joshua Aberback
[Why]
VTG has a parameter FP2, which is defined as:
if VSTARTUP is before VSYNC:
FP2 = number of lines in between VSTARTUP and VSYNC
else
FP2 = 0
Currently, FP2 is only programmed during "program_timing". However, the
position of VSTARTUP is affected by the prefetching requirements on all pipes,
so the position might change when we do memory request control on another pipe,
so we need
to make sure that FP2 stays up-to-date whenever we adjust VSTARTUP.
[How]
- refactor VTG_CONTROL programming into a new function "set_vtg_params"
- call it after calling "program_global_sync"
- make sure it's called after because it relies on the cached dlg params
Signed-off-by: Joshua Aberback
Reviewed-by: Tony Cheng
Acked-by: Bhawanpreet Lakha
Acked-by: Jun Lei
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 6 ++
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 1 +
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 1fd89cc218a5..5bed89547410 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1206,6 +1206,9 @@ static void dcn20_program_all_pipe_in_tree(
pipe_ctx->pipe_dlg_param.vupdate_offset,
pipe_ctx->pipe_dlg_param.vupdate_width);
+ pipe_ctx->stream_res.tg->funcs->set_vtg_params(
+ pipe_ctx->stream_res.tg,
_ctx->stream->timing);
+
dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
if (dc->hwss.update_odm)
@@ -1442,6 +1445,9 @@ bool dcn20_update_bandwidth(
pipe_ctx->pipe_dlg_param.vupdate_offset,
pipe_ctx->pipe_dlg_param.vupdate_width);
+ pipe_ctx->stream_res.tg->funcs->set_vtg_params(
+ pipe_ctx->stream_res.tg,
_ctx->stream->timing);
+
dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index 875b48e450f8..cee1ed11ffe3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -434,6 +434,7 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
.get_optc_source = optc2_get_optc_source,
.set_gsl = optc2_set_gsl,
.set_gsl_source_select = optc2_set_gsl_source_select,
+ .set_vtg_params = optc1_set_vtg_params,
};
void dcn20_timing_generator_init(struct optc *optc1)
--
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[PATCH 357/459] drm/amd/display: do not need otg lock if otg is not active
From: hersen wu
[todo] need find caller bug. tempooariy fix
Signed-off-by: hersen wu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
index b3fc71648d16..a546c2bc9129 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -584,6 +584,13 @@ uint32_t optc1_get_vblank_counter(struct timing_generator
*optc)
void optc1_lock(struct timing_generator *optc)
{
struct optc *optc1 = DCN10TG_FROM_TG(optc);
+ uint32_t regval = 0;
+
+ regval = REG_READ(OTG_CONTROL);
+
+ /* otg is not running, do not need to be locked */
+ if ((regval & 0x1) == 0x0)
+ return;
REG_SET(OTG_GLOBAL_CONTROL0, 0,
OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
@@ -591,10 +598,12 @@ void optc1_lock(struct timing_generator *optc)
OTG_MASTER_UPDATE_LOCK, 1);
/* Should be fast, status does not update on maximus */
- if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS)
+ if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) {
+
REG_WAIT(OTG_MASTER_UPDATE_LOCK,
UPDATE_LOCK_STATUS, 1,
1, 10);
+ }
}
void optc1_unlock(struct timing_generator *optc)
--
2.20.1
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[PATCH 350/459] drm/amd/display: do not power on eDP power rail early
From: Anthony Koo [Why] Modern Standby may toggle display adapter state between D0 and D3 state unpredictably. But events that cause transition to D0 are not always resulting in a display light up scenario. Modern eDP panels should be able to power on panel logic quickly upon VDD going high. Based on spec, the T3 time between VDD on and HPD high can be between 0 and 80 ms. Doing any tricky sorts of optimization by powering on panel VDD early during D0 transition on can negatively impact other features due to unnecessary power drain and toggling when final system state does not intend for the panel to be lit up. We need OEMs to source higher end panels that have T3 time close to 0 if they want quick S3/Modern Standby resume times. [How] Remove panel VDD power on in init_hw Signed-off-by: Anthony Koo Reviewed-by: Tony Cheng Acked-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 2a34447112e9..f6e25f75a0a9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -547,9 +547,6 @@ static void dcn20_init_hw(struct dc *dc) */ struct dc_link *link = dc->links[i]; - if (link->link_enc->connector.id == CONNECTOR_ID_EDP) - dc->hwss.edp_power_control(link, true); - link->link_enc->funcs->hw_init(link->link_enc); } } -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 348/459] drm/amd/display: update calculated bounding box logic for NV
From: Jun Lei
[why]
Current calculation of bounding box will cause DML to increase voltage
state due to DPP or DISPCLK, this is unnecessary since from DML perspective
we can max DPP/DISP can be supported at DPM0. This is because
increasing voltage for DPP/DISP is done separately via actual minimum values
of DISP and DPP CLK
[how]
For each calculated state, DPP, DISP, PHY, and DSC clk should always be set to
maximum. FCLK, SOCCLK, and DCFCLK should be based of UCLK.
Signed-off-by: Jun Lei
Reviewed-by: Tony Cheng
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 55 ---
1 file changed, 24 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index d0c279ab0af1..c4fa0b9e7138 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2402,54 +2402,47 @@ static void update_bounding_box(struct dc *dc, struct
_vcs_dpi_soc_bounding_box_
struct pp_smu_nv_clock_table *max_clocks, unsigned int
*uclk_states, unsigned int num_states)
{
struct _vcs_dpi_voltage_scaling_st
calculated_states[MAX_CLOCK_LIMIT_STATES] = {0};
- int i, j;
+ int i;
int num_calculated_states = 0;
+ int min_dcfclk = 0;
if (num_states == 0)
return;
+ if (dc->bb_overrides.min_dcfclk_mhz > 0)
+ min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
+
for (i = 0; i < num_states; i++) {
- // Find lowest pre-silicon DPM that has equal or higher uCLK
- for (j = 0; j < bb->num_states; j++) {
- if (bb->clock_limits[j].dram_speed_mts * 1000 / 16 >=
uclk_states[i])
- break;
- }
+ int min_fclk_required_by_uclk;
+ calculated_states[i].state = i;
+ calculated_states[i].dram_speed_mts = uclk_states[i] * 16 /
1000;
- // If for some reason the available uCLK is higher than all
pre-silicon'
- // DPM targets, then we just use the highest one
- if (j >= bb->num_states)
- j = bb->num_states;
+ min_fclk_required_by_uclk = ((unsigned long
long)uclk_states[i]) * 1008 / 100;
- // Copy that state
- memcpy(_states[num_calculated_states],
>clock_limits[j],
-
sizeof(calculated_states[num_calculated_states]));
+ calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk
< min_dcfclk) ?
+ min_dcfclk : min_fclk_required_by_uclk;
- // Cap uClk to actual
- calculated_states[num_calculated_states].dram_speed_mts =
uclk_states[i] * 16 / 1000;
- // Phy clock can be set to max for all states, since there's
nothing to optimize
- // for spreadsheet and we request voltage for phy clock by
frequency anyway
- calculated_states[num_calculated_states].phyclk_mhz =
max_clocks->phyClockInKhz / 1000;
+ calculated_states[i].socclk_mhz =
(calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
+ max_clocks->socClockInKhz / 1000 :
calculated_states[i].fabricclk_mhz;
- calculated_states[num_calculated_states].state =
num_calculated_states;
+ calculated_states[i].dcfclk_mhz =
(calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
+ max_clocks->dcfClockInKhz / 1000 :
calculated_states[i].fabricclk_mhz;
- num_calculated_states++;
- }
+ calculated_states[i].dispclk_mhz =
max_clocks->displayClockInKhz / 1000;
+ calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz
/ 1000;
+ calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz
/ (1000 * 3);
- if (max_clocks->dcfClockInKhz > 0)
- calculated_states[num_calculated_states - 1].dcfclk_mhz =
max_clocks->dcfClockInKhz / 1000;
+ calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz /
1000;
- if (max_clocks->displayClockInKhz > 0) {
- calculated_states[num_calculated_states - 1].dispclk_mhz =
max_clocks->displayClockInKhz / 1000;
- calculated_states[num_calculated_states - 1].dppclk_mhz =
max_clocks->displayClockInKhz / 1000;
- // DSC always runs at 1/3 of disp clock
- calculated_states[num_calculated_states - 1].dscclk_mhz =
max_clocks->displayClockInKhz / (1000 * 3);
+ num_calculated_states++;
}
- if (max_clocks->socClockInKhz > 0)
- calculated_states[num_calculated_states - 1].socclk_mhz =
max_clocks->socClockInKhz / 1000;
-
[PATCH 356/459] drm/amd/display: disable dcn20 abm feature for bring up
From: hersen wu
[WHY] dcn20 enable usb-c dp ALT mode in dmcu. There is bug
when enable abm feature which cause system crash. dal team
will debug this bug later.
[HOW] disable dcn abm feature for dcn20.
Signed-off-by: hersen wu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 27c57267e295..d20250b181b7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -781,7 +781,7 @@ static int dm_late_init(void *handle)
unsigned int linear_lut[16];
int i;
struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
- bool ret;
+ bool ret = false;
for (i = 0; i < 16; i++)
linear_lut[i] = 0x * i / 15;
@@ -792,10 +792,13 @@ static int dm_late_init(void *handle)
params.backlight_lut_array_size = 16;
params.backlight_lut_array = linear_lut;
- ret = dmcu_load_iram(dmcu, params);
+ /* todo will enable for navi10 */
+ if (adev->asic_type <= CHIP_RAVEN) {
+ ret = dmcu_load_iram(dmcu, params);
- if (!ret)
- return -EINVAL;
+ if (!ret)
+ return -EINVAL;
+ }
return detect_mst_link_for_all_connectors(adev->ddev);
}
--
2.20.1
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[PATCH 349/459] drm/amd/display: Move link functions from dc to dc_link
From: Chris Park
[Why]
link-specific functions should reside in dc_link.c
[How]
Move them there.
Signed-off-by: Chris Park
Reviewed-by: Charlene Liu
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 1af06637fdda..2a9f4661540c 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3053,6 +3053,33 @@ uint32_t dc_link_bandwidth_kbps(
link_bw_kbps *= 8; /* 8 bits per byte*/
link_bw_kbps *= link_setting->lane_count;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+ if (link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
+ /* Account for FEC overhead.
+* We have to do it based on caps,
+* and not based on FEC being set ready,
+* because FEC is set ready too late in
+* the process to correctly be picked up
+* by mode enumeration.
+*
+* There's enough zeros at the end of 'kbps'
+* that make the below operation 100% precise
+* for our purposes.
+* 'long long' makes it work even for HDMI 2.1
+* max bandwidth (and much, much bigger bandwidths
+* than that, actually).
+*
+* NOTE: Reducing link BW by 3% may not be precise
+* because it may be a stream BT that increases by 3%, and so
+* 1/1.03 = 0.970873 factor should have been used instead,
+* but the difference is minimal and is in a safe direction,
+* which all works well around potential ambiguity of DP 1.4a
spec.
+*/
+ long long fec_link_bw_kbps = link_bw_kbps * 970LL;
+ link_bw_kbps = (uint32_t)(fec_link_bw_kbps / 1000LL);
+ }
+#endif
+
return link_bw_kbps;
}
--
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[PATCH 347/459] drm/amd/display: disable PSR/ABM before destroy DMCU struct
From: Paul Hsieh [Why] 1. DMCU is not running on some platform but driver still send ABM command. It may cause assert due to DMCU is not alive. 2. To make sure PSR disable when driver disable [How] 1. Add dmcu_is_running in ABM struct, driver can check this flag to determine driver should send ABM command or not. 2. Send PSR disable command when destroy PSR Signed-off-by: Paul Hsieh Reviewed-by: Anthony Koo Acked-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c index 5bed89547410..2a34447112e9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c @@ -657,6 +657,9 @@ static void dcn20_init_hw(struct dc *dc) if (dmcu != NULL) dmcu->funcs->dmcu_init(dmcu); + if (abm != NULL && dmcu != NULL) + abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); + /* power AFMT HDMI memory TODO: may move to dis/en output save power*/ REG_WRITE(DIO_MEM_PWR_CTRL, 0); -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 346/459] drm/amd/display: Ensure DRR triggers in BP
From: Eryk Brol
[Why]
In the previous implementation DRR event sometimes came
in during FP2 region which is a keep-out zone. This
would cause the frame not to latch until the next frame
which resulted in heavy flicker. To fix this we need
to make sure that it triggers in the BP.
[How]
1. Remove DRR programming during flip
2. Setup manual trigger for DRR event and trigger it
after surface programming is complete
Signed-off-by: Eryk Brol
Reviewed-by: Aric Cyr
Acked-by: Leo Li
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 31 +++
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 7 +++--
.../amd/display/dc/inc/hw/timing_generator.h | 1 +
3 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
index cee1ed11ffe3..724b5a9e47d0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -381,6 +381,35 @@ void optc2_lock(struct timing_generator *optc)
1, 10);
}
+void optc2_setup_manual_trigger(struct timing_generator *optc)
+{
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+ REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
+ MANUAL_FLOW_CONTROL, 1);
+
+ REG_SET(OTG_GLOBAL_CONTROL2, 0,
+ MANUAL_FLOW_CONTROL_SEL, optc->inst);
+
+ REG_SET_8(OTG_TRIGA_CNTL, 0,
+ OTG_TRIGA_SOURCE_SELECT, 22,
+ OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
+ OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
+ OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
+ OTG_TRIGA_POLARITY_SELECT, 0,
+ OTG_TRIGA_FREQUENCY_SELECT, 0,
+ OTG_TRIGA_DELAY, 0,
+ OTG_TRIGA_CLEAR, 1);
+}
+
+void optc2_program_manual_trigger(struct timing_generator *optc)
+{
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+ REG_SET(OTG_TRIGA_MANUAL_TRIG, 0,
+ OTG_TRIGA_MANUAL_TRIG, 1);
+}
+
static struct timing_generator_funcs dcn20_tg_funcs = {
.validate_timing = optc1_validate_timing,
.program_timing = optc1_program_timing,
@@ -435,6 +464,8 @@ static struct timing_generator_funcs dcn20_tg_funcs = {
.set_gsl = optc2_set_gsl,
.set_gsl_source_select = optc2_set_gsl_source_select,
.set_vtg_params = optc1_set_vtg_params,
+ .program_manual_trigger = optc2_program_manual_trigger,
+ .setup_manual_trigger = optc2_setup_manual_trigger
};
void dcn20_timing_generator_init(struct optc *optc1)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
index b936a4da1583..a00bb0d92a49 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
@@ -40,7 +40,8 @@
SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
SRI(OPTC_MEMORY_CONFIG, ODM, inst),\
- SR(DWB_SOURCE_SELECT)
+ SR(DWB_SOURCE_SELECT),\
+ SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst)
#define TG_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\
TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\
@@ -70,7 +71,8 @@
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, mask_sh),\
SF(ODM0_OPTC_WIDTH_CONTROL, OPTC_SEGMENT_WIDTH, mask_sh),\
SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\
- SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh)
+ SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh),\
+ SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh)
void dcn20_timing_generator_init(struct optc *optc);
@@ -105,5 +107,6 @@ void optc2_triplebuffer_unlock(struct timing_generator
*optc);
void optc2_lock(struct timing_generator *optc);
void optc2_lock_global(struct timing_generator *optc);
void optc2_setup_global_lock(struct timing_generator *optc);
+void optc2_program_manual_trigger(struct timing_generator *optc);
#endif /* __DC_OPTC_DCN20_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index eced6ec05899..251baebe5386 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -257,6 +257,7 @@ struct timing_generator_funcs {
void (*set_vtg_params)(struct timing_generator *optc,
const struct dc_crtc_timing *dc_crtc_timing);
+
#ifdef CONFIG_DRM_AMD_DC_DCN2_0
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
void (*set_dsc_config)(struct timing_generator *optc,
--
2.20.1
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[PATCH 336/459] drm/amd/powerplay: add interface to get uclk dpm table
From: hersen wu dc needs get uclk dpm table for bandwidth calculation Signed-off-by: hersen wu Acked-by: Alex Deucher Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index c748821ef766..2818df46481c 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -878,6 +878,8 @@ struct smu_funcs ((smu)->ppt_funcs->set_watermarks_table ? (smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0) #define smu_get_current_clk_freq_by_table(smu, clk_type, value) \ ((smu)->ppt_funcs->get_current_clk_freq_by_table ? (smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0) +#define smu_thermal_temperature_range_update(smu, range, rw) \ + ((smu)->ppt_funcs->thermal_temperature_range_update? (smu)->ppt_funcs->thermal_temperature_range_update((smu), (range), (rw)) : 0) #define smu_get_thermal_temperature_range(smu, range) \ ((smu)->ppt_funcs->get_thermal_temperature_range? (smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0) #define smu_register_irq_handler(smu) \ @@ -888,6 +890,8 @@ struct smu_funcs ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0) #define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \ ((smu)->funcs->get_max_sustainable_clocks_by_dc ? (smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0) +#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \ + ((smu)->ppt_funcs->get_uclk_dpm_states ? (smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0) extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table, uint16_t *size, uint8_t *frev, uint8_t *crev, -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 319/459] drm/amd/display: Add DCN2 BIOS parsing
From: Harry Wentland Handle BIOS parsing for DCN2 Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 4 drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c | 6 ++ 2 files changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index 12bc7ee66b18..99f40b8a231c 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -1400,6 +1400,10 @@ static enum bp_result get_integrated_info_v11( info->ma_channel_number = info_v11->umachannelnumber; info->lvds_ss_percentage = le16_to_cpu(info_v11->lvds_ss_percentage); +#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + info->dp_ss_control = + le16_to_cpu(info_v11->reserved1); +#endif info->lvds_sspread_rate_in_10hz = le16_to_cpu(info_v11->lvds_ss_rate_10hz); info->hdmi_ss_percentage = diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c index 53deba42007a..f9439dfc7b75 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c @@ -61,6 +61,12 @@ bool dal_bios_parser_init_cmd_tbl_helper2( *h = dal_cmd_tbl_helper_dce112_get_table2(); return true; #endif + +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case DCN_VERSION_2_0: + *h = dal_cmd_tbl_helper_dce112_get_table2(); + return true; +#endif case DCE_VERSION_12_0: case DCE_VERSION_12_1: *h = dal_cmd_tbl_helper_dce112_get_table2(); -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 339/459] drm/amd/display: updates for dcn20_update_bandwidth
Pass extra parameter to validate_bandwidth() callback.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 487a07cbeb93..3d5eb20ea9ba 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1345,7 +1345,7 @@ bool dcn20_update_bandwidth(
int i;
/* recalculate DML parameters */
- if (!dc->res_pool->funcs->validate_bandwidth(dc, context)) {
+ if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false)) {
return false;
}
--
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[PATCH 334/459] drm/amd/display: Add DC core changes for DCN2
From: Harry Wentland
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/Makefile | 6 +
drivers/gpu/drm/amd/display/dc/core/dc.c | 141 -
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +-
.../gpu/drm/amd/display/dc/core/dc_link_dp.c | 62 ++
.../gpu/drm/amd/display/dc/core/dc_stream.c | 185 ++
.../gpu/drm/amd/display/dc/core/dc_surface.c | 63 ++
drivers/gpu/drm/amd/display/dc/dc.h | 89 -
drivers/gpu/drm/amd/display/dc/dc_stream.h| 67 +++
drivers/gpu/drm/amd/display/dc/dm_pp_smu.h| 113 ++-
9 files changed, 728 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
b/drivers/gpu/drm/amd/display/dc/Makefile
index 6da4e4f844b2..9c0a755414de 100644
--- a/drivers/gpu/drm/amd/display/dc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/Makefile
@@ -25,6 +25,12 @@
DC_LIBS = basics bios calcs clk_mgr dce gpio irq virtual
+ifdef CONFIG_DRM_AMD_DC_DCN2_0
+DC_LIBS += dcn20
+endif
+
+
+
ifdef CONFIG_DRM_AMD_DC_DCN1_0
DC_LIBS += dcn10 dml
endif
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 08092ae57bc8..052d3c8c6b73 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -56,6 +56,10 @@
#include "dc_link_dp.h"
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+#include "vm_helper.h"
+#endif
+
#include "dce/dce_i2c.h"
#define DC_LOGGER \
@@ -528,6 +532,11 @@ static void destruct(struct dc *dc)
kfree(dc->dcn_ip);
dc->dcn_ip = NULL;
+#endif
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ kfree(dc->vm_helper);
+ dc->vm_helper = NULL;
+
#endif
}
@@ -545,6 +554,11 @@ static bool construct(struct dc *dc,
enum dce_version dc_version = DCE_VERSION_UNKNOWN;
dc->config = init_params->flags;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ // Allocate memory for the vm_helper
+ dc->vm_helper = kzalloc(sizeof(struct vm_helper), GFP_KERNEL);
+
+#endif
memcpy(>bb_overrides, _params->bb_overrides,
sizeof(dc->bb_overrides));
dc_dceip = kzalloc(sizeof(*dc_dceip), GFP_KERNEL);
@@ -578,6 +592,9 @@ static bool construct(struct dc *dc,
}
dc->dcn_ip = dcn_ip;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ dc->soc_bounding_box = init_params->soc_bounding_box;
+#endif
#endif
dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL);
@@ -674,6 +691,21 @@ static bool construct(struct dc *dc,
return false;
}
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+static bool disable_all_writeback_pipes_for_stream(
+ const struct dc *dc,
+ struct dc_stream_state *stream,
+ struct dc_state *context)
+{
+ int i;
+
+ for (i = 0; i < stream->num_wb_info; i++)
+ stream->writeback_info[i].wb_enabled = false;
+
+ return true;
+}
+#endif
+
static void disable_dangling_plane(struct dc *dc, struct dc_state *context)
{
int i, j;
@@ -698,6 +730,9 @@ static void disable_dangling_plane(struct dc *dc, struct
dc_state *context)
}
if (should_disable && old_stream) {
dc_rem_all_planes_for_stream(dc, old_stream,
dangling_context);
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ disable_all_writeback_pipes_for_stream(dc, old_stream,
dangling_context);
+#endif
dc->hwss.apply_ctx_for_surface(dc, old_stream, 0,
dangling_context);
}
}
@@ -769,6 +804,26 @@ void dc_destroy(struct dc **dc)
*dc = NULL;
}
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+bool dc_init_memory_hub(struct dc *dc, struct dc_addr_space_config *config)
+{
+ // Memory hub init isn't done as part of dc_create because in windows,
dal/dc is
+ // constructed before the vm config is setup in kmd so there's no way
+ // they can give it to us at boot/dc_create
+ bool vmSupported;
+
+ // Call HWSS to setup HUBBUB for address config
+ dc->hwss.init_dchub(dc->hwseq, dc, config);
+
+ // Pre-init system aperture start/end for all HUBP instances (if not
gating?)
+ // or cache system aperture if using power gating
+ memcpy(>vm_config, config, sizeof(struct dc_addr_space_config));
+
+ vmSupported = (dc->ctx->asic_id.chip_family == FAMILY_NV) ? true :
false;
+ return vmSupported;
+}
+
+#endif
static void enable_timing_multisync(
struct dc *dc,
struct dc_state *ctx)
@@ -1598,6 +1653,19 @@ static void copy_surface_update_to_plane(
sizeof(struct dc_transfer_func_distributed_points));
}
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ if (srf_update->func_shaper &&
+ (surface->in_shaper_func !=
+ srf_update->func_shaper))
+ memcpy(surface->in_shaper_func, srf_update->func_shaper,
+
[PATCH 340/459] drm/amd/display: update dcn2 dc_plane_cap
To deal with rebasing the code.
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/dcn20/dcn20_resource.c | 21 ---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 16be22a2091d..af4e2447a5da 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -601,10 +601,25 @@ static const struct dc_plane_cap plane_cap = {
.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
.blends_with_above = true,
.blends_with_below = true,
- .supports_argb = true,
.per_pixel_alpha = true,
- .supports_argb = true,
- .supports_nv12 = true
+
+ .pixel_format_support = {
+ .argb = true,
+ .nv12 = true,
+ .fp16 = true
+ },
+
+ .max_upscale_factor = {
+ .argb = 16000,
+ .nv12 = 16000,
+ .fp16 = 1
+ },
+
+ .max_downscale_factor = {
+ .argb = 250,
+ .nv12 = 250,
+ .fp16 = 1
+ }
};
static const struct dc_debug_options debug_defaults_drv = {
--
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[PATCH 337/459] drm/amd/display: hook navi10 pplib functions
From: hersen wu
during bring up time, before window dc-ppplib interface
design, linux dc use raven dc-pplib interface.
now nvai10 dc-pplib-smu interface is changed and verified
under window, navi10 need its specific dc-pplib-smu
interface. todo: hook set_hard_min_uclk_by_freq,
get_maximum_sustainable_clocks
Signed-off-by: hersen wu
Acked-by: Alex Deucher
Reviewed-by: Roman Li
Signed-off-by: Alex Deucher
---
.../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 279 +-
1 file changed, 271 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index f78ca2be664f..4d4531c18c14 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -647,16 +647,279 @@ void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp,
int mhz)
pp_funcs->set_hard_min_fclk_by_freq(pp_handle, mhz);
}
+enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
+ struct pp_smu_wm_range_sets *ranges)
+{
+ const struct dc_context *ctx = pp->dm;
+ struct amdgpu_device *adev = ctx->driver_context;
+ struct smu_context *smu = >smu;
+ struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
+ struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
+ wm_with_clock_ranges.wm_dmif_clocks_ranges;
+ struct dm_pp_clock_range_for_mcif_wm_set_soc15 *wm_soc_clocks =
+ wm_with_clock_ranges.wm_mcif_clocks_ranges;
+ int32_t i;
+
+ wm_with_clock_ranges.num_wm_dmif_sets = ranges->num_reader_wm_sets;
+ wm_with_clock_ranges.num_wm_mcif_sets = ranges->num_writer_wm_sets;
+
+ for (i = 0; i < wm_with_clock_ranges.num_wm_dmif_sets; i++) {
+ if (ranges->reader_wm_sets[i].wm_inst > 3)
+ wm_dce_clocks[i].wm_set_id = WM_SET_A;
+ else
+ wm_dce_clocks[i].wm_set_id =
+ ranges->reader_wm_sets[i].wm_inst;
+ wm_dce_clocks[i].wm_max_dcfclk_clk_in_khz =
+ ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000;
+ wm_dce_clocks[i].wm_min_dcfclk_clk_in_khz =
+ ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000;
+ wm_dce_clocks[i].wm_max_mem_clk_in_khz =
+ ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000;
+ wm_dce_clocks[i].wm_min_mem_clk_in_khz =
+ ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000;
+ }
+
+ for (i = 0; i < wm_with_clock_ranges.num_wm_mcif_sets; i++) {
+ if (ranges->writer_wm_sets[i].wm_inst > 3)
+ wm_soc_clocks[i].wm_set_id = WM_SET_A;
+ else
+ wm_soc_clocks[i].wm_set_id =
+ ranges->writer_wm_sets[i].wm_inst;
+ wm_soc_clocks[i].wm_max_socclk_clk_in_khz =
+ ranges->writer_wm_sets[i].max_fill_clk_mhz * 1000;
+ wm_soc_clocks[i].wm_min_socclk_clk_in_khz =
+ ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000;
+ wm_soc_clocks[i].wm_max_mem_clk_in_khz =
+ ranges->writer_wm_sets[i].max_drain_clk_mhz * 1000;
+ wm_soc_clocks[i].wm_min_mem_clk_in_khz =
+ ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
+ }
+
+ if (!smu->funcs)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+ /* 0: successful or smu.funcs->set_watermarks_for_clock_ranges = NULL;
+* 1: fail
+*/
+ if (smu_set_watermarks_for_clock_ranges(>smu,
+ _with_clock_ranges))
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+ return PP_SMU_RESULT_OK;
+}
+
+enum pp_smu_status pp_nv_set_pme_wa_enable(struct pp_smu *pp)
+{
+ const struct dc_context *ctx = pp->dm;
+ struct amdgpu_device *adev = ctx->driver_context;
+ struct smu_context *smu = >smu;
+
+ if (!smu->funcs)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+ /* 0: successful or smu.funcs->set_azalia_d3_pme = NULL; 1: fail */
+ if (smu_set_azalia_d3_pme(smu))
+ return PP_SMU_RESULT_FAIL;
+
+ return PP_SMU_RESULT_OK;
+}
+
+enum pp_smu_status pp_nv_set_display_count(struct pp_smu *pp, int count)
+{
+ const struct dc_context *ctx = pp->dm;
+ struct amdgpu_device *adev = ctx->driver_context;
+ struct smu_context *smu = >smu;
+
+ if (!smu->funcs)
+ return PP_SMU_RESULT_UNSUPPORTED;
+
+ /* 0: successful or smu.funcs->set_display_count = NULL; 1: fail */
+ if (smu_set_display_count(smu, count))
+ return PP_SMU_RESULT_FAIL;
+
+ return PP_SMU_RESULT_OK;
+}
+
+enum pp_smu_status pp_nv_set_min_deep_sleep_dcfclk(struct
[PATCH 338/459] drm/amd/display: add fast_validate parameter to dcn20_validate_bandwidth
To deal with changes from rebasing.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 +++-
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 522b85a5db33..16be22a2091d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1705,7 +1705,9 @@ void dcn20_set_mcif_arb_params(
}
}
-bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context)
+bool dcn20_validate_bandwidth(struct dc *dc,
+ struct dc_state *context,
+ bool fast_validate)
{
int pipe_cnt, i, pipe_idx, vlevel, vlevel_unsplit;
int pipe_split_from[MAX_PIPES];
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
index ab9db16f5165..c5f176fb654a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
@@ -115,7 +115,7 @@ void dcn20_set_mcif_arb_params(
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt);
-bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context);
+bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context, bool
fast_validate);
enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct
dc_state *context, struct dc_stream_state *stream);
enum dc_status dcn20_validate_global(struct dc *dc,struct dc_state
*new_ctx);
--
2.20.1
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[PATCH 342/459] drm/amdgpu: Enable DC support for Navi10
From: Harry Wentland Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++ drivers/gpu/drm/amd/amdgpu/nv.c| 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 6970d3f56c51..4d468fd6352c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2421,6 +2421,9 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) case CHIP_VEGA20: #if defined(CONFIG_DRM_AMD_DC_DCN1_0) case CHIP_RAVEN: +#endif +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case CHIP_NAVI10: #endif return amdgpu_dc != 0; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 3cfc15be6ff8..e705b453b7c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -348,6 +348,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, _v11_0_ip_block); if (adev->enable_virtual_display || amdgpu_sriov_vf(adev)) amdgpu_device_ip_block_add(adev, _virtual_ip_block); + else if (amdgpu_device_has_dc_support(adev)) + amdgpu_device_ip_block_add(adev, _ip_block); amdgpu_device_ip_block_add(adev, _v10_0_ip_block); amdgpu_device_ip_block_add(adev, _v5_0_ip_block); if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 341/459] drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2)
From: Harry Wentland
Enable DCN2 support in DM (Display Manager).
v2: fix spurious raven change (Alex)
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/Kconfig| 9 +
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++
.../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c| 2 +-
3 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/display/Kconfig
b/drivers/gpu/drm/amd/display/Kconfig
index ed654a76c76a..a2eba0d6a55f 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -15,6 +15,15 @@ config DRM_AMD_DC_DCN1_0
help
RV family support for display engine
+config DRM_AMD_DC_DCN2_0
+ bool "DCN 2.0 family"
+ default y
+ depends on DRM_AMD_DC && X86
+ depends on DRM_AMD_DC_DCN1_0
+ help
+ Choose this option if you want to have
+ Navi support for display engine
+
config DEBUG_KERNEL_DC
bool "Enable kgdb break in DC"
depends on DRM_AMD_DC
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 2313c153aaaf..27c57267e295 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -666,6 +666,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_VEGA20:
+ case CHIP_NAVI10:
return 0;
case CHIP_RAVEN:
if (ASICREV_IS_PICASSO(adev->external_rev_id))
@@ -2210,6 +2211,9 @@ static int amdgpu_dm_initialize_drm_device(struct
amdgpu_device *adev)
break;
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
case CHIP_RAVEN:
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ case CHIP_NAVI10:
+#endif
if (dcn10_register_irq_handlers(dm->adev)) {
DRM_ERROR("DM: Failed to initialize IRQ\n");
goto fail;
@@ -2435,6 +2439,13 @@ static int dm_early_init(void *handle)
adev->mode_info.num_hpd = 4;
adev->mode_info.num_dig = 4;
break;
+#endif
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ case CHIP_NAVI10:
+ adev->mode_info.num_crtc = 6;
+ adev->mode_info.num_hpd = 6;
+ adev->mode_info.num_dig = 6;
+ break;
#endif
default:
DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
@@ -2728,6 +2739,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev,
if (adev->asic_type == CHIP_VEGA10 ||
adev->asic_type == CHIP_VEGA12 ||
adev->asic_type == CHIP_VEGA20 ||
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ adev->asic_type == CHIP_NAVI10 ||
+#endif
adev->asic_type == CHIP_RAVEN) {
/* Fill GFX9 params */
tiling_info->gfx9.num_pipes =
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 7258c992a2bf..75b6a2ac910b 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -166,7 +166,7 @@ int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc)
*/
stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS;
ret = mod_color_calculate_regamma_params(stream->out_transfer_func,
- gamma, true, adev->asic_type <= CHIP_RAVEN, NULL);
+ gamma, true, adev->asic_type <= CHIP_NAVI10, NULL);
if (gamma)
dc_gamma_release();
--
2.20.1
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[PATCH 325/459] drm/amd/display: Add DCN2 OPP
From: Harry Wentland
Add support to program the DCN2 OPP (Output Plane Processing)
HW Blocks:
+---+
| OPP |
+---+
|
v
++
| OPTC |
++
|
v
++ ++
| DIO | | DCCG |
++ ++
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 8 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_opp.c | 355 ++
.../gpu/drm/amd/display/dc/dcn20/dcn20_opp.h | 158
drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 29 ++
4 files changed, 550 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.h
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
index ab958cff3b76..1168342c7190 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c
@@ -365,6 +365,11 @@ void opp1_program_oppbuf(
*/
REG_UPDATE(OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION,
oppbuf->pixel_repetition);
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* Controls the number of padded pixels at the end of a segment */
+ if (REG(OPPBUF_CONTROL1))
+ REG_UPDATE(OPPBUF_CONTROL1, OPPBUF_NUM_SEGMENT_PADDED_PIXELS,
oppbuf->num_segment_padded_pixels);
+#endif
}
void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable)
@@ -391,6 +396,9 @@ static const struct opp_funcs dcn10_opp_funcs = {
.opp_program_bit_depth_reduction =
opp1_program_bit_depth_reduction,
.opp_program_stereo = opp1_program_stereo,
.opp_pipe_clock_control = opp1_pipe_clock_control,
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ .opp_set_disp_pattern_generator = NULL,
+#endif
.opp_destroy = opp1_destroy
};
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
new file mode 100644
index ..d9e7c711a71c
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_opp.c
@@ -0,0 +1,355 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dcn20_opp.h"
+#include "reg_helper.h"
+
+#define REG(reg) \
+ (oppn20->regs->reg)
+
+#undef FN
+#define FN(reg_name, field_name) \
+ oppn20->opp_shift->field_name, oppn20->opp_mask->field_name
+
+#define CTX \
+ oppn20->base.ctx
+
+
+void opp2_set_disp_pattern_generator(
+ struct output_pixel_processor *opp,
+ enum controller_dp_test_pattern test_pattern,
+ enum dc_color_depth color_depth,
+ const struct tg_color *solid_color,
+ int width,
+ int height)
+{
+ struct dcn20_opp *oppn20 = TO_DCN20_OPP(opp);
+ enum test_pattern_color_format bit_depth;
+ enum test_pattern_dyn_range dyn_range;
+ enum test_pattern_mode mode;
+
+ /* color ramp generator mixes 16-bits color */
+ uint32_t src_bpc = 16;
+ /* requested bpc */
+ uint32_t dst_bpc;
+ uint32_t index;
+ /* RGB values of the color bars.
+* Produce two RGB colors: RGB0 - white (all Fs)
+* and RGB1 - black (all 0s)
+* (three RGB components for two colors)
+*/
+ uint16_t src_color[6] = {0x, 0x, 0x, 0x,
+ 0x, 0x};
+ /* dest color (converted to the specified color format) */
+ uint16_t dst_color[6];
+ uint32_t inc_base;
+
+ /* translate to bit depth */
+ switch (color_depth) {
+ case COLOR_DEPTH_666:
+ bit_depth =
[PATCH 318/459] drm/amd/display: Add GPIO support for DCN2
From: Harry Wentland
Adding support to program GPIO HW block of DCN2
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 +
.../display/dc/gpio/dcn20/hw_factory_dcn20.c | 212 ++
.../display/dc/gpio/dcn20/hw_factory_dcn20.h | 33 ++
.../dc/gpio/dcn20/hw_translate_dcn20.c| 382 ++
.../dc/gpio/dcn20/hw_translate_dcn20.h| 35 ++
.../gpu/drm/amd/display/dc/gpio/ddc_regs.h| 53 +++
drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c | 15 +
.../gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +
.../drm/amd/display/dc/gpio/hw_translate.c| 9 +
9 files changed, 759 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.h
create mode 100644
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
create mode 100644
drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.h
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
index 562ee189d780..c3d92878875d 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile
@@ -69,6 +69,17 @@ AMD_DAL_GPIO_DCN10 = $(addprefix
$(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10))
AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN10)
endif
+###
+# DCN 2
+###
+ifdef CONFIG_DRM_AMD_DC_DCN2_0
+GPIO_DCN20 = hw_translate_dcn20.o hw_factory_dcn20.o
+
+AMD_DAL_GPIO_DCN20 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn20/,$(GPIO_DCN20))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN20)
+endif
+
###
# Diagnostics on FPGA
###
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
new file mode 100644
index ..abd76d855375
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright 2013-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+#include "dm_services.h"
+#include "include/gpio_types.h"
+#include "../hw_factory.h"
+
+
+#include "../hw_gpio.h"
+#include "../hw_ddc.h"
+#include "../hw_hpd.h"
+
+#include "hw_factory_dcn20.h"
+
+
+#include "dcn/dcn_2_0_0_offset.h"
+#include "dcn/dcn_2_0_0_sh_mask.h"
+#include "navi10_ip_offset.h"
+
+
+#include "reg_helper.h"
+#include "../hpd_regs.h"
+/* begin *
+ * macros to expend register list macro defined in HW object header file */
+
+/* DCN */
+#define block HPD
+#define reg_num 0
+
+#undef BASE_INNER
+#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
+
+#define BASE(seg) BASE_INNER(seg)
+
+
+
+#define REG(reg_name)\
+ BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
+
+#define SF_HPD(reg_name, field_name, post_fix)\
+ .field_name = HPD0_ ## reg_name ## __ ## field_name ## post_fix
+
+#define REGI(reg_name, block, id)\
+ BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
+ mm ## block ## id ## _ ## reg_name
+
+#define SF(reg_name, field_name, post_fix)\
+ .field_name = reg_name ## __ ## field_name ## post_fix
+
+/* macros to expend register list macro defined in HW object header file
+ * end */
+
+
+
+#define hpd_regs(id) \
+{\
+ HPD_REG_LIST(id)\
+}
+
+static const struct hpd_registers hpd_regs[] = {
+ hpd_regs(0),
+ hpd_regs(1),
+ hpd_regs(2),
+ hpd_regs(3),
+ hpd_regs(4),
+ hpd_regs(5),
+};
+
[PATCH 335/459] drm/amd/powrplay: add interface for dc to get max clock values
From: hersen wu
dc (display component) needs maximum clock values of uclock,
socclk, dcefclk, to calculate display bandwidth.
Signed-off-by: hersen wu
Acked-by: Alex Deucher
Reviewed-by: Huang Rui
---
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 4 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 31 +++
2 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index a8e5f4d69861..c748821ef766 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -25,6 +25,7 @@
#include "amdgpu.h"
#include "kgd_pp_interface.h"
#include "dm_pp_interface.h"
+#include "dm_pp_smu.h"
#define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
#define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
@@ -678,6 +679,7 @@ struct smu_funcs
int (*gfx_off_control)(struct smu_context *smu, bool enable);
int (*register_irq_handler)(struct smu_context *smu);
int (*set_azalia_d3_pme)(struct smu_context *smu);
+ int (*get_max_sustainable_clocks_by_dc)(struct smu_context *smu, struct
pp_smu_nv_clock_table *max_clocks);
};
#define smu_init_microcode(smu) \
@@ -884,6 +886,8 @@ struct smu_funcs
((smu)->funcs->set_azalia_d3_pme ?
(smu)->funcs->set_azalia_d3_pme((smu)) : 0)
#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
((smu)->ppt_funcs->get_uclk_dpm_states ?
(smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
+#define smu_get_max_sustainable_clocks_by_dc(smu, max_clocks) \
+ ((smu)->funcs->get_max_sustainable_clocks_by_dc ?
(smu)->funcs->get_max_sustainable_clocks_by_dc((smu), (max_clocks)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index caf6c9847c0f..631ee8460e38 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1597,6 +1597,36 @@ static int smu_v11_0_register_irq_handler(struct
smu_context *smu)
return ret;
}
+static int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
+ struct pp_smu_nv_clock_table *max_clocks)
+{
+ struct smu_table_context *table_context = >smu_table;
+ struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
+
+ if (!max_clocks || !table_context->max_sustainable_clocks )
+ return -EINVAL;
+
+ sustainable_clocks = table_context->max_sustainable_clocks;
+
+ max_clocks->dcfClockInKhz =
+ (unsigned int) sustainable_clocks->dcef_clock * 1000;
+ max_clocks->displayClockInKhz =
+ (unsigned int) sustainable_clocks->display_clock * 1000;
+ max_clocks->phyClockInKhz =
+ (unsigned int) sustainable_clocks->phy_clock * 1000;
+ max_clocks->pixelClockInKhz =
+ (unsigned int) sustainable_clocks->pixel_clock * 1000;
+ max_clocks->uClockInKhz =
+ (unsigned int) sustainable_clocks->uclock * 1000;
+ max_clocks->socClockInKhz =
+ (unsigned int) sustainable_clocks->soc_clock * 1000;
+ max_clocks->dscClockInKhz = 0;
+ max_clocks->dppClockInKhz = 0;
+ max_clocks->fabricClockInKhz = 0;
+
+ return 0;
+}
+
static int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
{
int ret = 0;
@@ -1655,6 +1685,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.gfx_off_control = smu_v11_0_gfx_off_control,
.register_irq_handler = smu_v11_0_register_irq_handler,
.set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
+ .get_max_sustainable_clocks_by_dc =
smu_v11_0_get_max_sustainable_clocks_by_dc,
};
void smu_v11_0_set_smu_funcs(struct smu_context *smu)
--
2.20.1
___
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[PATCH 324/459] drm/amd/display: Add DCN2 OPTC
From: Harry Wentland
Add support for programming the DCN2 OPTC (Output Timing Controller)
HW Blocks:
++
| OPTC |
++
|
v
++ ++
| DIO | | DCCG |
++ ++
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 33 +-
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 415 ++
.../gpu/drm/amd/display/dc/dcn20/dcn20_optc.h | 103 +
.../gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 43 +-
.../amd/display/dc/inc/hw/timing_generator.h | 22 +
5 files changed, 614 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.h
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
index 444c56c8104f..cd9b662fbea9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
@@ -89,7 +89,6 @@
SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst)
-
#define TG_COMMON_REG_LIST_DCN1_0(inst) \
TG_COMMON_REG_LIST_DCN(inst),\
SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\
@@ -164,6 +163,13 @@ struct dcn_optc_registers {
uint32_t OTG_CRC0_WINDOWB_X_CONTROL;
uint32_t OTG_CRC0_WINDOWB_Y_CONTROL;
uint32_t GSL_SOURCE_SELECT;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ uint32_t DWB_SOURCE_SELECT;
+ uint32_t OTG_DSC_START_POSITION;
+ uint32_t OPTC_DATA_FORMAT_CONTROL;
+ uint32_t OPTC_BYTES_PER_PIXEL;
+ uint32_t OPTC_WIDTH_CONTROL;
+#endif
};
#define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\
@@ -442,10 +448,35 @@ struct dcn_optc_registers {
type MANUAL_FLOW_CONTROL;\
type MANUAL_FLOW_CONTROL_SEL;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+
+#define TG_REG_FIELD_LIST(type) \
+ TG_REG_FIELD_LIST_DCN1_0(type)\
+ type MASTER_UPDATE_LOCK_DB_X;\
+ type MASTER_UPDATE_LOCK_DB_Y;\
+ type MASTER_UPDATE_LOCK_DB_EN;\
+ type GLOBAL_UPDATE_LOCK_EN;\
+ type DIG_UPDATE_LOCATION;\
+ type OTG_DSC_START_POSITION_X;\
+ type OTG_DSC_START_POSITION_LINE_NUM;\
+ type OPTC_NUM_OF_INPUT_SEGMENT;\
+ type OPTC_SEG0_SRC_SEL;\
+ type OPTC_SEG1_SRC_SEL;\
+ type OPTC_MEM_SEL;\
+ type OPTC_DSC_MODE;\
+ type OPTC_DSC_BYTES_PER_PIXEL;\
+ type OPTC_DSC_SLICE_WIDTH;\
+ type OPTC_SEGMENT_WIDTH;\
+ type OPTC_DWB0_SOURCE_SELECT;\
+ type OPTC_DWB1_SOURCE_SELECT;
+
+#else
#define TG_REG_FIELD_LIST(type) \
TG_REG_FIELD_LIST_DCN1_0(type)
+#endif
+
struct dcn_optc_shift {
TG_REG_FIELD_LIST(uint8_t)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
new file mode 100644
index ..72d72c3a35ee
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_optc.c
@@ -0,0 +1,415 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "reg_helper.h"
+#include "dcn20_optc.h"
+#include "dc.h"
+
+#define REG(reg)\
+ optc1->tg_regs->reg
+
+#define CTX \
+ optc1->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+ optc1->tg_shift->field_name, optc1->tg_mask->field_name
+
+/**
+ * Enable CRTC
+ * Enable CRTC - call ASIC Control Object to enable Timing generator.
+ */
+bool optc2_enable_crtc(struct timing_generator *optc)
+{
+ /* TODO FPGA wait for answer
+* OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
+* OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
+*/
+ struct optc *optc1 = DCN10TG_FROM_TG(optc);
+
+ /* opp instance for OTG. For DCN1.0, ODM is remoed.
+* OPP
[PATCH 331/459] drm/amd/display: Add DCN2 IPP
From: Harry Wentland
Add support to program DCN2 cursor (IPP)
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 24 +++
.../gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h | 43 +++
2 files changed, 67 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
index 08db1e6b5166..1580f9c6d27d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c
@@ -51,6 +51,12 @@ static const struct ipp_funcs dcn10_ipp_funcs = {
.ipp_destroy= dcn10_ipp_destroy
};
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+static const struct ipp_funcs dcn20_ipp_funcs = {
+ .ipp_destroy= dcn10_ipp_destroy
+};
+#endif
+
void dcn10_ipp_construct(
struct dcn10_ipp *ippn10,
struct dc_context *ctx,
@@ -68,3 +74,21 @@ void dcn10_ipp_construct(
ippn10->ipp_mask = ipp_mask;
}
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+void dcn20_ipp_construct(
+ struct dcn10_ipp *ippn10,
+ struct dc_context *ctx,
+ int inst,
+ const struct dcn10_ipp_registers *regs,
+ const struct dcn10_ipp_shift *ipp_shift,
+ const struct dcn10_ipp_mask *ipp_mask)
+{
+ ippn10->base.ctx = ctx;
+ ippn10->base.inst = inst;
+ ippn10->base.funcs = _ipp_funcs;
+
+ ippn10->regs = regs;
+ ippn10->ipp_shift = ipp_shift;
+ ippn10->ipp_mask = ipp_mask;
+}
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
index 819b749c6e31..cfa24459242b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h
@@ -49,6 +49,19 @@
SRI(CURSOR_HOT_SPOT, CURSOR, id), \
SRI(CURSOR_DST_OFFSET, CURSOR, id)
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+#define IPP_REG_LIST_DCN20(id) \
+ IPP_REG_LIST_DCN(id), \
+ SRI(CURSOR_SETTINGS, HUBPREQ, id), \
+ SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
+ SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
+ SRI(CURSOR_SIZE, CURSOR0_, id), \
+ SRI(CURSOR_CONTROL, CURSOR0_, id), \
+ SRI(CURSOR_POSITION, CURSOR0_, id), \
+ SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \
+ SRI(CURSOR_DST_OFFSET, CURSOR0_, id)
+#endif
+
#define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
#define CURSOR0_CURSOR_CONTROL__CURSOR_2X_MAGNIFY_MASK 0x0010L
#define CURSOR1_CURSOR_CONTROL__CURSOR_2X_MAGNIFY__SHIFT 0x4
@@ -92,6 +105,27 @@
IPP_SF(CURSOR0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh), \
IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh)
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+#define IPP_MASK_SH_LIST_DCN20(mask_sh) \
+ IPP_MASK_SH_LIST_DCN(mask_sh), \
+ IPP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_DST_Y_OFFSET, mask_sh), \
+ IPP_SF(HUBPREQ0_CURSOR_SETTINGS, CURSOR0_CHUNK_HDL_ADJUST, mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS_HIGH,
CURSOR_SURFACE_ADDRESS_HIGH, mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_SURFACE_ADDRESS, CURSOR_SURFACE_ADDRESS,
mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_WIDTH, mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_SIZE, CURSOR_HEIGHT, mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_MODE, mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_2X_MAGNIFY, mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_PITCH, mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_LINES_PER_CHUNK, mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_CONTROL, CURSOR_ENABLE, mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_X_POSITION, mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_POSITION, CURSOR_Y_POSITION, mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_X, mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_HOT_SPOT, CURSOR_HOT_SPOT_Y, mask_sh), \
+ IPP_SF(CURSOR0_0_CURSOR_DST_OFFSET, CURSOR_DST_X_OFFSET, mask_sh)
+#endif
+
#define IPP_DCN10_REG_FIELD_LIST(type) \
type CNVC_SURFACE_PIXEL_FORMAT; \
type CNVC_BYPASS; \
@@ -162,4 +196,13 @@ void dcn10_ipp_construct(struct dcn10_ipp *ippn10,
const struct dcn10_ipp_shift *ipp_shift,
const struct dcn10_ipp_mask *ipp_mask);
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+void dcn20_ipp_construct(struct dcn10_ipp *ippn10,
+ struct dc_context *ctx,
+ int inst,
+ const struct dcn10_ipp_registers *regs,
+ const struct dcn10_ipp_shift *ipp_shift,
+ const struct dcn10_ipp_mask *ipp_mask);
+#endif
+
#endif /* _DCN10_IPP_H_ */
--
2.20.1
___
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[PATCH 320/459] drm/amd/display: Add DCN2 IRQ handling
From: Harry Wentland
Add support to program DCN2 IRQ handling
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 +
.../display/dc/irq/dcn20/irq_service_dcn20.c | 361 ++
.../display/dc/irq/dcn20/irq_service_dcn20.h | 34 ++
3 files changed, 405 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.h
diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile
b/drivers/gpu/drm/amd/display/dc/irq/Makefile
index 498515aad4a5..ad87c2f093e2 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
@@ -67,3 +67,13 @@ AMD_DAL_IRQ_DCN1 = $(addprefix
$(AMDDALPATH)/dc/irq/dcn10/,$(IRQ_DCN1))
AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN1)
endif
+###
+# DCN 20
+###
+ifdef CONFIG_DRM_AMD_DC_DCN2_0
+IRQ_DCN2 = irq_service_dcn20.o
+
+AMD_DAL_IRQ_DCN2 = $(addprefix $(AMDDALPATH)/dc/irq/dcn20/,$(IRQ_DCN2))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN2)
+endif
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
new file mode 100644
index ..da70cc7b24b5
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c
@@ -0,0 +1,361 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+
+#include "include/logger_interface.h"
+
+#include "../dce110/irq_service_dce110.h"
+
+#include "dcn/dcn_2_0_0_offset.h"
+#include "dcn/dcn_2_0_0_sh_mask.h"
+#include "navi10_ip_offset.h"
+
+
+#include "irq_service_dcn20.h"
+
+#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
+
+enum dc_irq_source to_dal_irq_source_dcn20(
+ struct irq_service *irq_service,
+ uint32_t src_id,
+ uint32_t ext_id)
+{
+ switch (src_id) {
+ case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
+ return DC_IRQ_SOURCE_VBLANK1;
+ case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
+ return DC_IRQ_SOURCE_VBLANK2;
+ case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
+ return DC_IRQ_SOURCE_VBLANK3;
+ case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
+ return DC_IRQ_SOURCE_VBLANK4;
+ case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
+ return DC_IRQ_SOURCE_VBLANK5;
+ case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
+ return DC_IRQ_SOURCE_VBLANK6;
+ case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
+ return DC_IRQ_SOURCE_PFLIP1;
+ case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
+ return DC_IRQ_SOURCE_PFLIP2;
+ case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
+ return DC_IRQ_SOURCE_PFLIP3;
+ case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
+ return DC_IRQ_SOURCE_PFLIP4;
+ case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
+ return DC_IRQ_SOURCE_PFLIP5;
+ case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
+ return DC_IRQ_SOURCE_PFLIP6;
+
+ case DCN_1_0__SRCID__DC_HPD1_INT:
+ /* generic src_id for all HPD and HPDRX interrupts */
+ switch (ext_id) {
+ case DCN_1_0__CTXID__DC_HPD1_INT:
+ return DC_IRQ_SOURCE_HPD1;
+ case DCN_1_0__CTXID__DC_HPD2_INT:
+ return DC_IRQ_SOURCE_HPD2;
+ case DCN_1_0__CTXID__DC_HPD3_INT:
+ return DC_IRQ_SOURCE_HPD3;
+ case DCN_1_0__CTXID__DC_HPD4_INT:
+ return DC_IRQ_SOURCE_HPD4;
+ case DCN_1_0__CTXID__DC_HPD5_INT:
+ return
[PATCH 316/459] drm/amd/display: Add DCN2 and NV ASIC ID
From: Harry Wentland
DCN2.0 (Display Core Next) is the display block in Navi10.
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/include/dal_asic_id.h | 25 +++
.../gpu/drm/amd/display/include/dal_types.h | 3 +++
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index b302ff3180a4..5ce1832ab41f 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -147,6 +147,31 @@
#define FAMILY_RV 142 /* DCN 1*/
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+
+#define FAMILY_NV 143 /* DCN 2*/
+
+enum {
+ NV_NAVI10_P_A0 = 1,
+ NV_NAVI12_P_A0 = 10,
+ NV_NAVI14_M_A0 = 20,
+ NV_NAVI21_P_A0 = 40,
+ NV_NAVI10_LITE_P_A0 = 0x80,
+ NV_NAVI10_LITE_P_B0 = 0x81,
+ NV_NAVI12_LITE_P_A0 = 0x82,
+ NV_NAVI21_LITE_P_A0 = 0x90,
+ NV_UNKNOWN = 0xFF
+};
+
+#define ASICREV_IS_NAVI10_P(eChipRev)(eChipRev < NV_NAVI12_P_A0)
+#define ASICREV_IS_NAVI12_P(eChipRev)((eChipRev >= NV_NAVI12_P_A0) &&
(eChipRev < NV_NAVI14_M_A0))
+#define ASICREV_IS_NAVI14_M(eChipRev)((eChipRev >= NV_NAVI14_M_A0) &&
(eChipRev < NV_NAVI21_P_A0))
+#define ASICREV_IS_NAVI21_M(eChipRev)((eChipRev >= NV_NAVI21_P_A0) &&
(eChipRev < NV_NAVI10_LITE_P_A0))
+#define ASICREV_IS_NAVI10_LITE_P(eChipRev) ((eChipRev >=
NV_NAVI10_LITE_P_A0) && (eChipRev < NV_NAVI12_LITE_P_A0))
+#define ASICREV_IS_NAVI12_LITE_P(eChipRev) ((eChipRev >=
NV_NAVI12_LITE_P_A0) && (eChipRev < NV_NAVI21_LITE_P_A0))
+#define ASICREV_IS_NAVI21_LITE_P(eChipRev) ((eChipRev >=
NV_NAVI21_LITE_P_A0) && (eChipRev < NV_UNKNOWN))
+#endif
+
/*
* ASIC chip ID
*/
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h
b/drivers/gpu/drm/amd/display/include/dal_types.h
index dabdbc0999d4..1e3ce4d847ae 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -46,6 +46,9 @@ enum dce_version {
DCE_VERSION_MAX,
DCN_VERSION_1_0,
DCN_VERSION_1_01,
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ DCN_VERSION_2_0,
+#endif
DCN_VERSION_MAX
};
--
2.20.1
___
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[PATCH 303/459] drm/amdgpu/gfx10: update to latest golden setting
Fix UTCL1_CGTT_CLK_CTRL Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index ae3d868de308..779597a6f33a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -100,7 +100,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_1[] = SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0x, 0x), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7, 0x0103), SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x6010, 0x479c0010), - SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0x4ff0, 0x4100), + SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x4100), SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x0080, 0x0080) }; -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 326/459] drm/amd/display: Add DCN2 MPC
From: Harry Wentland
Add support to program the DCN2 MPC (Multiple pipe and plane combine)
HW Blocks:
++
| MPC |
++
|
v
+---+
| OPP |
+---+
|
v
++
| OPTC |
++
|
v
++ ++
| DIO | | DCCG |
++ ++
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 87 ++-
.../gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c | 6 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c | 526 ++
.../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h | 285 ++
drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 52 ++
5 files changed, 955 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
index dff915df..6a9670de38f3 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h
@@ -194,6 +194,12 @@ enum surface_pixel_format {
/*swaped & float*/
SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F,
/*grow graphics here if necessary */
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ SURFACE_PIXEL_FORMAT_GRPH_RGB10_FIX,
+ SURFACE_PIXEL_FORMAT_GRPH_BGR10_FIX,
+ SURFACE_PIXEL_FORMAT_GRPH_RGB10_FLOAT,
+ SURFACE_PIXEL_FORMAT_GRPH_BGR10_FLOAT,
+#endif
SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr =
SURFACE_PIXEL_FORMAT_VIDEO_BEGIN,
@@ -201,6 +207,10 @@ enum surface_pixel_format {
SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr,
SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb,
SURFACE_PIXEL_FORMAT_SUBSAMPLE_END,
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010,
+ SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102,
+#endif
SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb,
SURFACE_PIXEL_FORMAT_INVALID
@@ -239,6 +249,13 @@ enum tile_split_values {
DC_ROTATED_MICRO_TILING = 0x3,
};
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+enum tripleBuffer_enable {
+ DC_TRIPLEBUFFER_DISABLE = 0x0,
+ DC_TRIPLEBUFFER_ENABLE = 0x1,
+};
+#endif
+
/* TODO: These values come from hardware spec. We need to readdress this
* if they ever change.
*/
@@ -437,6 +454,14 @@ struct dc_csc_transform {
bool enable_adjustment;
};
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+struct dc_rgb_fixed {
+ struct fixed31_32 red;
+ struct fixed31_32 green;
+ struct fixed31_32 blue;
+};
+#endif
+
struct dc_gamma {
struct kref refcount;
enum dc_gamma_type type;
@@ -470,7 +495,11 @@ enum dc_cursor_color_format {
CURSOR_MODE_MONO,
CURSOR_MODE_COLOR_1BIT_AND,
CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA,
- CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA
+ CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA,
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED,
+ CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED
+#endif
};
/*
@@ -616,6 +645,10 @@ enum dc_color_depth {
COLOR_DEPTH_121212,
COLOR_DEPTH_141414,
COLOR_DEPTH_161616,
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ COLOR_DEPTH_999,
+ COLOR_DEPTH_11,
+#endif
COLOR_DEPTH_COUNT
};
@@ -750,6 +783,58 @@ struct dc_crtc_timing {
struct dc_crtc_timing_flags flags;
};
+/* Passed on init */
+enum vram_type {
+ VIDEO_MEMORY_TYPE_GDDR5 = 2,
+ VIDEO_MEMORY_TYPE_DDR3 = 3,
+ VIDEO_MEMORY_TYPE_DDR4 = 4,
+ VIDEO_MEMORY_TYPE_HBM= 5,
+ VIDEO_MEMORY_TYPE_GDDR6 = 6,
+};
+
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+enum dwb_cnv_out_bpc {
+ DWB_CNV_OUT_BPC_8BPC = 0,
+ DWB_CNV_OUT_BPC_10BPC = 1,
+};
+
+enum dwb_output_depth {
+ DWB_OUTPUT_PIXEL_DEPTH_8BPC = 0,
+ DWB_OUTPUT_PIXEL_DEPTH_10BPC = 1,
+};
+
+enum dwb_capture_rate {
+ dwb_capture_rate_0 = 0, /* Every frame is captured. */
+ dwb_capture_rate_1 = 1, /* Every other frame is captured. */
+ dwb_capture_rate_2 = 2, /* Every 3rd frame is captured. */
+ dwb_capture_rate_3 = 3, /* Every 4th frame is captured. */
+};
+
+enum dwb_scaler_mode {
+ dwb_scaler_mode_bypass444 = 0,
+ dwb_scaler_mode_rgb444 = 1,
+ dwb_scaler_mode_yuv444 = 2,
+ dwb_scaler_mode_yuv420 = 3
+};
+
+enum dwb_subsample_position {
+ DWB_INTERSTITIAL_SUBSAMPLING = 0,
+ DWB_COSITED_SUBSAMPLING = 1
+};
+
+#define MCIF_BUF_COUNT 4
+
+struct mcif_buf_params {
+ unsigned long long luma_address[MCIF_BUF_COUNT];
+ unsigned long long chroma_address[MCIF_BUF_COUNT];
+ unsigned intluma_pitch;
+ unsigned intchroma_pitch;
+
[PATCH 301/459] drm/amdgpu/VCN: enable indirect DPG SRAM mode
From: Leo Liu This is default mode for VCN2.x now Signed-off-by: Leo Liu Reviewed-by: James Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 7621077378dd..c604f1504d3e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -75,6 +75,9 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) break; case CHIP_NAVI10: fw_name = FIRMWARE_NAVI10; + if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) && + (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)) + adev->vcn.indirect_sram = true; break; default: return -EINVAL; -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 317/459] drm/amd/display: add AUX and I2C for DCN2
From: Harry Wentland
Adding support to program DCN2 AUX and I2C HW.
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h | 10 ++
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.c | 32 +++
.../gpu/drm/amd/display/dc/dce/dce_i2c_hw.h | 22 +
3 files changed, 64 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
index ce6a26d189b0..ed7fec8fe253 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
@@ -29,6 +29,16 @@
#include "i2caux_interface.h"
#include "inc/hw/aux_engine.h"
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+#define AUX_COMMON_REG_LIST0(id)\
+ SRI(AUX_CONTROL, DP_AUX, id), \
+ SRI(AUX_ARB_CONTROL, DP_AUX, id), \
+ SRI(AUX_SW_DATA, DP_AUX, id), \
+ SRI(AUX_SW_CONTROL, DP_AUX, id), \
+ SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
+ SRI(AUX_SW_STATUS, DP_AUX, id)
+#endif
+
#define AUX_COMMON_REG_LIST(id)\
SRI(AUX_CONTROL, DP_AUX, id), \
SRI(AUX_ARB_CONTROL, DP_AUX, id), \
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index 7f2460caa2a6..d658b862430a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -303,6 +303,10 @@ static bool setup_engine(
struct dce_i2c_hw *dce_i2c_hw)
{
uint32_t i2c_setup_limit = I2C_SETUP_TIME_LIMIT_DCE;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ uint32_t reset_length = 0;
+#endif
+
/* we have checked I2c not used by DMCU, set SW use I2C REQ to 1 to
indicate SW using it*/
REG_UPDATE(DC_I2C_ARBITRATION, DC_I2C_SW_USE_I2C_REG_REQ, 1);
@@ -323,6 +327,14 @@ static bool setup_engine(
REG_UPDATE_N(SETUP, 2,
FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT),
i2c_setup_limit,
FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ } else {
+ reset_length = dce_i2c_hw->send_reset_length;
+ REG_UPDATE_N(SETUP, 3,
+FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_TIME_LIMIT),
i2c_setup_limit,
+FN(DC_I2C_DDC1_SETUP,
DC_I2C_DDC1_SEND_RESET_LENGTH), reset_length,
+FN(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE), 1);
+#endif
}
/* Program HW priority
* set to High - interrupt software I2C at any time
@@ -698,3 +710,23 @@ void dcn1_i2c_hw_construct(
dce_i2c_hw->setup_limit = I2C_SETUP_TIME_LIMIT_DCN;
}
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+void dcn2_i2c_hw_construct(
+ struct dce_i2c_hw *dce_i2c_hw,
+ struct dc_context *ctx,
+ uint32_t engine_id,
+ const struct dce_i2c_registers *regs,
+ const struct dce_i2c_shift *shifts,
+ const struct dce_i2c_mask *masks)
+{
+ dcn1_i2c_hw_construct(dce_i2c_hw,
+ ctx,
+ engine_id,
+ regs,
+ shifts,
+ masks);
+ dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_9;
+ if (ctx->dc->debug.scl_reset_length10)
+ dce_i2c_hw->send_reset_length = I2C_SEND_RESET_LENGTH_10;
+}
+#endif
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
index a633632f625b..cb0234e5d597 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
@@ -177,6 +177,9 @@ struct dce_i2c_shift {
uint8_t DC_I2C_INDEX;
uint8_t DC_I2C_INDEX_WRITE;
uint8_t XTAL_REF_DIV;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH;
+#endif
uint8_t DC_I2C_REG_RW_CNTL_STATUS;
};
@@ -217,9 +220,18 @@ struct dce_i2c_mask {
uint32_t DC_I2C_INDEX;
uint32_t DC_I2C_INDEX_WRITE;
uint32_t XTAL_REF_DIV;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH;
+#endif
uint32_t DC_I2C_REG_RW_CNTL_STATUS;
};
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+#define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\
+ I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh),\
+ I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH, mask_sh)
+#endif
+
struct dce_i2c_registers {
uint32_t SETUP;
uint32_t SPEED;
@@ -300,6 +312,16 @@ void dcn1_i2c_hw_construct(
const struct dce_i2c_shift *shifts,
const struct dce_i2c_mask *masks);
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+void dcn2_i2c_hw_construct(
+ struct dce_i2c_hw *dce_i2c_hw,
+ struct dc_context *ctx,
+ uint32_t engine_id,
+ const struct dce_i2c_registers *regs,
+ const struct dce_i2c_shift *shifts,
+ const struct dce_i2c_mask *masks);
+#endif
+
[PATCH 323/459] drm/amd/display: Add DCN2 clk mgr
From: Harry Wentland
Adds support for handling of clocking relevant to the DCN2 block,
including programming of the DCCG (Display Controller Clock Generator)
block:
HW Blocks:
++ ++
| DIO | | DCCG |
++ ++
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/clk_mgr/Makefile | 12 +
.../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 32 +-
.../display/dc/clk_mgr/dce100/dce_clk_mgr.h | 22 -
.../display/dc/clk_mgr/dcn10/rv1_clk_mgr.c| 25 +-
.../dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c | 58 ++-
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 384 ++
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h | 44 ++
.../drm/amd/display/dc/dce/dce_clock_source.c | 108 +
.../drm/amd/display/dc/dce/dce_clock_source.h | 42 ++
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c | 157 +++
.../gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h | 116 ++
.../amd/display/dc/inc/hw/clk_mgr_internal.h | 82 +++-
12 files changed, 999 insertions(+), 83 deletions(-)
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
index 650e2b88c917..003c27767e9c 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
@@ -73,3 +73,15 @@ AMD_DAL_CLK_MGR_DCN10 = $(addprefix
$(AMDDALPATH)/dc/clk_mgr/dcn10/,$(CLK_MGR_DC
AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN10)
endif
+
+ifdef CONFIG_DRM_AMD_DC_DCN2_0
+###
+# DCN20
+###
+CLK_MGR_DCN20 = dcn20_clk_mgr.o
+
+AMD_DAL_CLK_MGR_DCN20 = $(addprefix
$(AMDDALPATH)/dc/clk_mgr/dcn20/,$(CLK_MGR_DCN20))
+
+AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN20)
+endif
+
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
index eb2204d42337..27d407a9b452 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
@@ -34,31 +34,7 @@
#include "dce120/dce120_clk_mgr.h"
#include "dcn10/rv1_clk_mgr.h"
#include "dcn10/rv2_clk_mgr.h"
-
-
-int clk_mgr_helper_get_active_display_cnt(
- struct dc *dc,
- struct dc_state *context)
-{
- int i, display_count;
-
- display_count = 0;
- for (i = 0; i < context->stream_count; i++) {
- const struct dc_stream_state *stream = context->streams[i];
-
- /*
-* Only notify active stream or virtual stream.
-* Need to notify virtual stream to work around
-* headless case. HPD does not fire when system is in
-* S0i2.
-*/
- if (!stream->dpms_off || stream->signal == SIGNAL_TYPE_VIRTUAL)
- display_count++;
- }
-
- return display_count;
-}
-
+#include "dcn20/dcn20_clk_mgr.h"
struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs
*pp_smu, struct dccg *dccg)
{
@@ -117,6 +93,12 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx,
struct pp_smu_funcs *p
break;
#endif /* Family RV */
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ case FAMILY_NV:
+ dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
+ break;
+#endif /* Family NV */
+
default:
ASSERT(0); /* Unknown Asic */
break;
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h
index f3bc7ab68aab..f6622f58f62e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.h
@@ -29,28 +29,6 @@
#include "dc.h"
-/* Starting DID for each range */
-enum dentist_base_divider_id {
- DENTIST_BASE_DID_1 = 0x08,
- DENTIST_BASE_DID_2 = 0x40,
- DENTIST_BASE_DID_3 = 0x60,
- DENTIST_BASE_DID_4 = 0x7e,
- DENTIST_MAX_DID = 0x7f
-};
-
-/* Starting point and step size for each divider range.*/
-enum dentist_divider_range {
- DENTIST_DIVIDER_RANGE_1_START = 8, /* 2.00 */
- DENTIST_DIVIDER_RANGE_1_STEP = 1, /* 0.25 */
- DENTIST_DIVIDER_RANGE_2_START = 64, /* 16.00 */
- DENTIST_DIVIDER_RANGE_2_STEP = 2, /* 0.50 */
- DENTIST_DIVIDER_RANGE_3_START = 128, /* 32.00 */
- DENTIST_DIVIDER_RANGE_3_STEP = 4, /* 1.00 */
- DENTIST_DIVIDER_RANGE_4_START = 248, /* 62.00 */
-
[PATCH 315/459] drm/amd/display: use fixed-width data type for soc bounding box struct
From: Xiaojie Yuan
Signed-off-by: Xiaojie Yuan
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h | 30 +++
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h
index 3282dfa50433..f4176cb01790 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h
@@ -24,7 +24,7 @@
#define __AMDGPU_SOCBB_H__
struct gpu_info_voltage_scaling_v1_0 {
- int state;
+ uint32_t state;
uint32_t dscclk_mhz;
uint32_t dcfclk_mhz;
uint32_t socclk_mhz;
@@ -49,7 +49,7 @@ struct gpu_info_soc_bounding_box_v1_0 {
uint32_t pct_ideal_dram_sdp_bw_after_urgent_vm_only;
uint32_t max_avg_sdp_bw_use_normal_percent;
uint32_t max_avg_dram_bw_use_normal_percent;
- unsigned int max_request_size_bytes;
+ uint32_t max_request_size_bytes;
uint32_t downspread_percent;
uint32_t dram_page_open_time_ns;
uint32_t dram_rw_turnaround_time_ns;
@@ -59,23 +59,23 @@ struct gpu_info_soc_bounding_box_v1_0 {
uint32_t dcn_downspread_percent;
uint32_t dispclk_dppclk_vco_speed_mhz;
uint32_t dfs_vco_period_ps;
- unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
- unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
- unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
- unsigned int round_trip_ping_latency_dcfclk_cycles;
- unsigned int urgent_out_of_order_return_per_channel_bytes;
- unsigned int channel_interleave_bytes;
- unsigned int num_banks;
- unsigned int num_chans;
- unsigned int vmm_page_size_bytes;
+ uint32_t urgent_out_of_order_return_per_channel_pixel_only_bytes;
+ uint32_t urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
+ uint32_t urgent_out_of_order_return_per_channel_vm_only_bytes;
+ uint32_t round_trip_ping_latency_dcfclk_cycles;
+ uint32_t urgent_out_of_order_return_per_channel_bytes;
+ uint32_t channel_interleave_bytes;
+ uint32_t num_banks;
+ uint32_t num_chans;
+ uint32_t vmm_page_size_bytes;
uint32_t dram_clock_change_latency_us;
uint32_t writeback_dram_clock_change_latency_us;
- unsigned int return_bus_width_bytes;
- unsigned int voltage_override;
+ uint32_t return_bus_width_bytes;
+ uint32_t voltage_override;
uint32_t xfc_bus_transport_time_us;
uint32_t xfc_xbuf_latency_tolerance_us;
- int use_urgent_burst_bw;
- unsigned int num_states;
+ uint32_t use_urgent_burst_bw;
+ uint32_t num_states;
struct gpu_info_voltage_scaling_v1_0 clock_limits[8];
};
--
2.20.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 306/459] drm/amd/powerplay: use pp_feature_mask to control uclk(mclk) dpm enabled
From: Kevin Wang
the uclk dpm feature is not work well on all navi10 asic,
use pp feature mask module parameter to control it.
Signed-off-by: Kevin Wang
Reviewed-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index af0abed6169e..c4bd14ab2add 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -315,9 +315,6 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
| FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
| FEATURE_MASK(FEATURE_DPM_LINK_BIT)
- | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
- | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
- | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT)
| FEATURE_MASK(FEATURE_GFX_ULV_BIT)
| FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
@@ -336,6 +333,11 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
| FEATURE_MASK(FEATURE_ACDC_BIT);
+ if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
+ | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
+ | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
+
if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
| FEATURE_MASK(FEATURE_GFXOFF_BIT);
--
2.20.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 330/459] drm/amd/display: Add DCN2 DWB
From: Harry Wentland
Add support to program the DCN2 DWB (Display Writeback)
HW Blocks:
+++--+ +--+
| HUBBUB || HUBP | <-- | MMHUBBUB |
+++--+ +--+
| ^
v |
++++
| DPP || DWB |
++++
|
v ^
++ |
| MPC | |
++ |
| |
v |
+---+ |
| OPP | |
+---+ |
| |
v |
++/
| OPTC | --
++
|
v
++ ++
| DIO | | DCCG |
++ ++
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/display/dc/dc_types.h | 26 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c | 136 +++
.../gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h | 271 ++
.../gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c | 315 +++
.../gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h | 458 +
.../drm/amd/display/dc/dcn20/dcn20_dwb_scl.c | 877 ++
.../gpu/drm/amd/display/dc/inc/core_types.h | 52 ++
drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 187
.../gpu/drm/amd/display/dc/inc/hw/mcif_wb.h | 105 +++
9 files changed, 2427 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/mcif_wb.h
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h
b/drivers/gpu/drm/amd/display/dc/dc_types.h
index 92a670894c05..01793aa3e093 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -421,6 +421,32 @@ enum display_content_type {
DISPLAY_CONTENT_TYPE_GAME = 8
};
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+/* writeback */
+struct dc_dwb_cnv_params {
+ unsigned intsrc_width; /* input active width */
+ unsigned intsrc_height; /* input active height
(half-active height in interlaced mode) */
+ unsigned intcrop_width; /* cropped window width at cnv
output */
+ boolcrop_en;/* window cropping enable in
cnv */
+ unsigned intcrop_height;/* cropped window height at cnv
output */
+ unsigned intcrop_x; /* cropped window start x value
at cnv output */
+ unsigned intcrop_y; /* cropped window start y value
at cnv output */
+ enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth -
8bpc or 10bpc */
+};
+
+struct dc_dwb_params {
+ struct dc_dwb_cnv_paramscnv_params; /* CNV source size and
cropping window parameters */
+ unsigned intdest_width; /* Destination width */
+ unsigned intdest_height;/* Destination height */
+ enum dwb_scaler_modeout_format; /* default = YUV420 -
TODO: limit this to 0 and 1 on dcn3 */
+ enum dwb_output_depth output_depth; /* output pixel depth -
8bpc or 10bpc */
+ enum dwb_capture_rate capture_rate; /* controls the frame
capture rate */
+ struct scaling_taps scaler_taps;/* Scaling taps */
+ enum dwb_subsample_position subsample_position;
+ struct dc_transfer_func *out_transfer_func;
+};
+#endif
+
/* audio*/
union audio_sample_rates {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
new file mode 100644
index ..374cc9acda3b
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright 2012-17 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+
[PATCH 329/459] drm/amd/display: Add DCN2 MMHUBBUB
From: Harry Wentland
Add support to program the DCN2 MMHUBBUB (Multimedia HUB interface)
HW Blocks:
+++--+ +--+
| HUBBUB || HUBP | <-- | MMHUBBUB |
+++--+ +--+
|
v
++
| DPP |
++
|
v
++
| MPC |
++
|
v
+---+
| OPP |
+---+
|
v
++
| OPTC |
++
|
v
++ ++
| DIO | | DCCG |
++ ++
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
.../drm/amd/display/dc/dcn20/dcn20_mmhubbub.c | 323 +++
.../drm/amd/display/dc/dcn20/dcn20_mmhubbub.h | 544 ++
2 files changed, 867 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c
new file mode 100644
index ..694260c10a01
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.c
@@ -0,0 +1,323 @@
+/*
+ * Copyright 2012-15 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+
+#include "reg_helper.h"
+#include "resource.h"
+#include "mcif_wb.h"
+#include "dcn20_mmhubbub.h"
+
+
+#define REG(reg)\
+ mcif_wb20->mcif_wb_regs->reg
+
+#define CTX \
+ mcif_wb20->base.ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+ mcif_wb20->mcif_wb_shift->field_name,
mcif_wb20->mcif_wb_mask->field_name
+
+#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xff) + 0xFE) >> 8
+#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40
+
+/* wbif programming guide:
+ * 1. set up wbif parameter:
+ *unsigned long long luma_address[4]; //4 frame buffer
+ *unsigned long long chroma_address[4];
+ *unsigned intluma_pitch;
+ *unsigned intchroma_pitch;
+ *unsigned int warmup_pitch=0x10; //256B align, the page size
is 4KB when it is 0x10
+ *unsigned intslice_lines; //slice size
+ *unsigned int time_per_pixel;// time per pixel, in ns
+ *unsigned int arbitration_slice; // 0: 512 bytes 1: 1024
bytes 2: 2048 Bytes
+ *unsigned int max_scaled_time; // used for QOS generation
+ *unsigned int swlock=0x0;
+ *unsigned int cli_watermark[4]; //4 group urgent watermark
+ *unsigned int pstate_watermark[4]; //4 group pstate watermark
+ *unsigned int sw_int_en; // Software interrupt
enable, frame end and overflow
+ *unsigned int sw_slice_int_en; // slice end interrupt enable
+ *unsigned int sw_overrun_int_en; // overrun error interrupt
enable
+ *unsigned int vce_int_en;// VCE interrupt enable,
frame end and overflow
+ *unsigned int vce_slice_int_en; // VCE slice end interrupt
enable, frame end and overflow
+ *
+ * 2. configure wbif register
+ *a. call mmhubbub_config_wbif()
+ *
+ * 3. Enable wbif
+ *call set_wbif_bufmgr_enable();
+ *
+ * 4. wbif_dump_status(), option, for debug purpose
+ *the bufmgr status can show the progress of write back, can be used for
debug purpose
+ */
+
+static void mmhubbub2_config_mcif_buf(struct mcif_wb *mcif_wb,
+ struct mcif_buf_params *params,
+ unsigned int dest_height)
+{
+ struct dcn20_mmhubbub *mcif_wb20 = TO_DCN20_MMHUBBUB(mcif_wb);
+
+ /* sw lock buffer0~buffer3, default is 0 */
+ REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK,
params->swlock);
+
+ /* buffer address for packing mode or Luma in planar mode */
[PATCH 328/459] drm/amd/display: Add DCN2 HUBP and HUBBUB
From: Harry Wentland Add support to program the DCN2 HUBP (Display to data fabric interface pipe) and HUBBUB (DCN memory HUB interface) HW Blocks: +++--+ | HUBBUB || HUBP | +++--+ | v ++ | DPP | ++ | v ++ | MPC | ++ | v +---+ | OPP | +---+ | v ++ | OPTC | ++ | v ++ ++ | DIO | | DCCG | ++ ++ Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/dcn10/dcn10_hubbub.c | 45 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c | 27 + .../gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h | 8 + .../drm/amd/display/dc/dcn20/dcn20_hubbub.c | 523 + .../drm/amd/display/dc/dcn20/dcn20_hubbub.h | 108 +++ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c | 699 ++ .../gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h | 244 ++ .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 62 ++ drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 25 + 9 files changed, 1739 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.h diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c index bf978831bb0e..daa229b97fcf 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c @@ -145,6 +145,7 @@ bool hubbub1_verify_allow_pstate_change_high( forced_pstate_allow = false; } +#ifdef CONFIG_DRM_AMD_DC_DCN1_01 /* RV2: * dchubbubdebugind, at: 0xB * description @@ -180,8 +181,46 @@ bool hubbub1_verify_allow_pstate_change_high( * 29:WB1 Allow Pstate Change * 30:Arbiter's allow_pstate_change * 31:SOC pstate change request" -* -* RV1: +*/ +#else +#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + /*DCN2.x: + HUBBUB:DCHUBBUB_TEST_ARB_DEBUG10 DCHUBBUBDEBUGIND:0xB + 0: Pipe0 Plane0 Allow P-state Change + 1: Pipe0 Plane1 Allow P-state Change + 2: Pipe0 Cursor0 Allow P-state Change + 3: Pipe0 Cursor1 Allow P-state Change + 4: Pipe1 Plane0 Allow P-state Change + 5: Pipe1 Plane1 Allow P-state Change + 6: Pipe1 Cursor0 Allow P-state Change + 7: Pipe1 Cursor1 Allow P-state Change + 8: Pipe2 Plane0 Allow P-state Change + 9: Pipe2 Plane1 Allow P-state Change + 10: Pipe2 Cursor0 Allow P-state Change + 11: Pipe2 Cursor1 Allow P-state Change + 12: Pipe3 Plane0 Allow P-state Change + 13: Pipe3 Plane1 Allow P-state Change + 14: Pipe3 Cursor0 Allow P-state Change + 15: Pipe3 Cursor1 Allow P-state Change + 16: Pipe4 Plane0 Allow P-state Change + 17: Pipe4 Plane1 Allow P-state Change + 18: Pipe4 Cursor0 Allow P-state Change + 19: Pipe4 Cursor1 Allow P-state Change + 20: Pipe5 Plane0 Allow P-state Change + 21: Pipe5 Plane1 Allow P-state Change + 22: Pipe5 Cursor0 Allow P-state Change + 23: Pipe5 Cursor1 Allow P-state Change + 24: Pipe6 Plane0 Allow P-state Change + 25: Pipe6 Plane1 Allow P-state Change + 26: Pipe6 Cursor0 Allow P-state Change + 27: Pipe6 Cursor1 Allow P-state Change + 28: WB0 Allow P-state Change + 29: WB1 Allow P-state Change + 30: Arbiter`s Allow P-state Change + 31: SOC P-state Change request + */ +#else + /* RV1: * dchubbubdebugind, at: 0x7 * description "3-0: Pipe0 cursor0 QOS * 7-4: Pipe1 cursor0 QOS @@ -204,6 +243,8 @@ bool hubbub1_verify_allow_pstate_change_high( * 30:Arbiter's allow_pstate_change * 31:SOC pstate change request */ +#endif +#endif REG_WRITE(DCHUBBUB_TEST_DEBUG_INDEX, hubbub1->debug_test_index_pstate); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c index 54b219a710d8..3f9ad09769b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c @@ -306,6 +306,28 @@ void hubp1_program_pixel_format( REG_UPDATE(DCSURF_SURFACE_CONFIG, SURFACE_PIXEL_FORMAT, 12); break; +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case SURFACE_PIXEL_FORMAT_GRPH_RGB10_FIX: + REG_UPDATE(DCSURF_SURFACE_CONFIG, + SURFACE_PIXEL_FORMAT, 112); + break; + case SURFACE_PIXEL_FORMAT_GRPH_BGR10_FIX:
[PATCH 322/459] drm/amd/display: Add DCN2 DIO
From: Harry Wentland
Add support for the DIO (Display IO) block of DCN2, which entails our
stream and link encoders.
HW Blocks:
++
| DIO |
++
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 174 +++
.../display/dc/dcn10/dcn10_stream_encoder.h | 40 ++
.../amd/display/dc/dcn20/dcn20_link_encoder.c | 438 +
.../amd/display/dc/dcn20/dcn20_link_encoder.h | 165 +++
.../display/dc/dcn20/dcn20_stream_encoder.c | 440 ++
.../display/dc/dcn20/dcn20_stream_encoder.h | 97
.../drm/amd/display/dc/inc/hw/link_encoder.h | 14 +
.../amd/display/dc/inc/hw/stream_encoder.h| 24 +
.../dc/virtual/virtual_stream_encoder.c | 5 +
9 files changed, 1397 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.h
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index b74b80a247ec..33b2af1a181c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -72,6 +72,9 @@
struct dcn10_link_enc_aux_registers {
uint32_t AUX_CONTROL;
uint32_t AUX_DPHY_RX_CONTROL0;
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ uint32_t AUX_DPHY_TX_CONTROL;
+#endif
};
struct dcn10_link_enc_hpd_registers {
@@ -103,6 +106,23 @@ struct dcn10_link_enc_registers {
uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
uint32_t DP_SEC_CNTL1;
uint32_t TMDS_CTL_BITS;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ /* DCCG */
+ uint32_t CLOCK_ENABLE;
+ /* DIG */
+ uint32_t DIG_LANE_ENABLE;
+ /* UNIPHY */
+ uint32_t CHANNEL_XBAR_CNTL;
+ /* indirect registers */
+ uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
+ uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
+ uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2;
+ uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3;
+ uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2;
+ uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;
+ uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;
+ uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;
+#endif
};
#define LE_SF(reg_name, field_name, post_fix)\
@@ -208,12 +228,166 @@ struct dcn10_link_enc_registers {
type AUX_LS_READ_EN;\
type AUX_RX_RECEIVE_WINDOW
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+
+#define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \
+ type RDPCS_PHY_DP_TX0_DATA_EN;\
+ type RDPCS_PHY_DP_TX1_DATA_EN;\
+ type RDPCS_PHY_DP_TX2_DATA_EN;\
+ type RDPCS_PHY_DP_TX3_DATA_EN;\
+ type RDPCS_PHY_DP_TX0_PSTATE;\
+ type RDPCS_PHY_DP_TX1_PSTATE;\
+ type RDPCS_PHY_DP_TX2_PSTATE;\
+ type RDPCS_PHY_DP_TX3_PSTATE;\
+ type RDPCS_PHY_DP_TX0_MPLL_EN;\
+ type RDPCS_PHY_DP_TX1_MPLL_EN;\
+ type RDPCS_PHY_DP_TX2_MPLL_EN;\
+ type RDPCS_PHY_DP_TX3_MPLL_EN;\
+ type RDPCS_TX_FIFO_LANE0_EN;\
+ type RDPCS_TX_FIFO_LANE1_EN;\
+ type RDPCS_TX_FIFO_LANE2_EN;\
+ type RDPCS_TX_FIFO_LANE3_EN;\
+ type RDPCS_EXT_REFCLK_EN;\
+ type RDPCS_TX_FIFO_EN;\
+ type UNIPHY_LINK_ENABLE;\
+ type UNIPHY_CHANNEL0_INVERT;\
+ type UNIPHY_CHANNEL1_INVERT;\
+ type UNIPHY_CHANNEL2_INVERT;\
+ type UNIPHY_CHANNEL3_INVERT;\
+ type UNIPHY_LINK_ENABLE_HPD_MASK;\
+ type UNIPHY_LANE_STAGGER_DELAY;\
+ type RDPCS_SRAMCLK_BYPASS;\
+ type RDPCS_SRAMCLK_EN;\
+ type RDPCS_SRAMCLK_CLOCK_ON;\
+ type DPCS_TX_FIFO_EN;\
+ type RDPCS_PHY_DP_TX0_DISABLE;\
+ type RDPCS_PHY_DP_TX1_DISABLE;\
+ type RDPCS_PHY_DP_TX2_DISABLE;\
+ type RDPCS_PHY_DP_TX3_DISABLE;\
+ type RDPCS_PHY_DP_TX0_CLK_RDY;\
+ type RDPCS_PHY_DP_TX1_CLK_RDY;\
+ type RDPCS_PHY_DP_TX2_CLK_RDY;\
+ type RDPCS_PHY_DP_TX3_CLK_RDY;\
+ type RDPCS_PHY_DP_TX0_REQ;\
+ type RDPCS_PHY_DP_TX1_REQ;\
+ type RDPCS_PHY_DP_TX2_REQ;\
+ type RDPCS_PHY_DP_TX3_REQ;\
+ type RDPCS_PHY_DP_TX0_ACK;\
+ type RDPCS_PHY_DP_TX1_ACK;\
+ type RDPCS_PHY_DP_TX2_ACK;\
+ type RDPCS_PHY_DP_TX3_ACK;\
+ type RDPCS_PHY_DP_TX0_RESET;\
+ type RDPCS_PHY_DP_TX1_RESET;\
+ type RDPCS_PHY_DP_TX2_RESET;\
+
[PATCH 312/459] drm/amd/powerplay: notify smu with active display count
From: hersen wu when dc update clocks via smu, smu needs to know how many displays active. this interface is for dc notify number of active displays to smu. Signed-off-by: hersen wu Reviewed-by: Huang Rui Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index 7366ef36ac55..caf6c9847c0f 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -773,6 +773,7 @@ static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count) if (!smu->pm_enabled) return ret; + ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count); return ret; } -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 327/459] drm/amd/display: Add DCN2 DPP
From: Harry Wentland
Add support to program the DCN2 DPP (Multiple pipe and plane combine)
HW Blocks:
++
| DPP |
++
|
v
++
| MPC |
++
|
v
+---+
| OPP |
+---+
|
v
++
| OPTC |
++
|
v
++ ++
| DIO | | DCCG |
++ ++
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 10 +
.../gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h | 5 +
.../drm/amd/display/dc/dcn10/dcn10_dpp_cm.c | 4 +
.../drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c | 8 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 493 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h | 698
.../drm/amd/display/dc/dcn20/dcn20_dpp_cm.c | 990 ++
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 53 +
8 files changed, 2261 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp_cm.c
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
index 6f4b24756323..b95ec73fcae3 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c
@@ -290,7 +290,12 @@ void dpp1_cnv_setup (
enum surface_pixel_format format,
enum expansion_mode mode,
struct dc_csc_transform input_csc_color_matrix,
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ enum dc_color_space input_color_space,
+ struct cnv_alpha_2bit_lut *alpha_2bit_lut)
+#else
enum dc_color_space input_color_space)
+#endif
{
uint32_t pixel_format;
uint32_t alpha_en;
@@ -523,6 +528,11 @@ static const struct dpp_funcs dcn10_dpp_funcs = {
.set_optional_cursor_attributes =
dpp1_cnv_set_optional_cursor_attributes,
.dpp_dppclk_control = dpp1_dppclk_control,
.dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier,
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ .dpp_program_blnd_lut = NULL,
+ .dpp_program_shaper_lut = NULL,
+ .dpp_program_3dlut = NULL
+#endif
};
static struct dpp_caps dcn10_dpp_cap = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
index 282e22f9b175..8a5517eebb7c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h
@@ -1486,7 +1486,12 @@ void dpp1_cnv_setup (
enum surface_pixel_format format,
enum expansion_mode mode,
struct dc_csc_transform input_csc_color_matrix,
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ enum dc_color_space input_color_space,
+ struct cnv_alpha_2bit_lut *alpha_2bit_lut);
+#else
enum dc_color_space input_color_space);
+#endif
void dpp1_full_bypass(struct dpp *dpp_base);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
index 882bcc5a40f6..aa0c7a7d13a0 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c
@@ -731,6 +731,10 @@ void dpp1_full_bypass(struct dpp *dpp_base)
/* COLOR_KEYER_CONTROL.COLOR_KEYER_EN = 0 this should be default */
if (dpp->tf_mask->CM_BYPASS_EN)
REG_SET(CM_CONTROL, 0, CM_BYPASS_EN, 1);
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ else
+ REG_SET(CM_CONTROL, 0, CM_BYPASS, 1);
+#endif
/* Setting degamma bypass for now */
REG_SET(CM_DGAM_CONTROL, 0, CM_DGAM_LUT_MODE, 0);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
index ce21a290bf3e..d67e0abeee93 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c
@@ -218,6 +218,14 @@ static void dpp1_dscl_set_lb(
INTERLEAVE_EN, lb_params->interleave_en, /* Interleave
source enable */
LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /*
Alpha enable */
}
+#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
+ else {
+ /* DSCL caps: pixel data processed in float format */
+ REG_SET_2(LB_DATA_FORMAT, 0,
+ INTERLEAVE_EN, lb_params->interleave_en, /* Interleave
source enable */
+ LB_DATA_FORMAT__ALPHA_EN, lb_params->alpha_en); /*
Alpha enable */
+ }
+#endif
REG_SET_2(LB_MEMORY_CTRL, 0,
MEMORY_CONFIG, mem_size_config,
diff --git
[PATCH 313/459] drm/amd/display: Read soc_bounding_box from gpu_info (v2)
From: Harry Wentland
[WHY]
We don't want to expose sensitive ASIC information before ASIC release.
[HOW]
Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it
at driver load.
v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex)
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 10 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 63 +++
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7 +++
drivers/gpu/drm/amd/display/dc/dc.h | 9 +++
5 files changed, 91 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index cd29c5476b1c..6970d3f56c51 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1431,7 +1431,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct
amdgpu_device *adev)
adev->gfx.cu_info.max_scratch_slots_per_cu =
le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
adev->gfx.cu_info.lds_size =
le32_to_cpu(gpu_info_fw->gc_lds_size);
- if (hdr->version_minor == 1) {
+ if (hdr->version_minor >= 1) {
const struct gpu_info_firmware_v1_1 *gpu_info_fw =
(const struct gpu_info_firmware_v1_1
*)(adev->firmware.gpu_info_fw->data +
le32_to_cpu(hdr->header.ucode_array_offset_bytes));
@@ -1440,6 +1440,14 @@ static int amdgpu_device_parse_gpu_info_fw(struct
amdgpu_device *adev)
adev->gfx.config.num_packer_per_sc =
le32_to_cpu(gpu_info_fw->num_packer_per_sc);
}
+#ifdef CONFIG_DRM_AMD_DC_DCN2_0
+ if (hdr->version_minor == 2) {
+ const struct gpu_info_firmware_v1_2 *gpu_info_fw =
+ (const struct gpu_info_firmware_v1_2
*)(adev->firmware.gpu_info_fw->data +
+
le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+ adev->dm.soc_bounding_box =
_info_fw->soc_bounding_box;
+ }
+#endif
break;
}
default:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 07f035937650..52b024917075 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -210,6 +210,69 @@ struct gpu_info_firmware_v1_1 {
uint32_t num_packer_per_sc;
};
+struct gpu_info_voltage_scaling_v1_0 {
+ int state;
+ uint32_t dscclk_mhz;
+ uint32_t dcfclk_mhz;
+ uint32_t socclk_mhz;
+ uint32_t dram_speed_mts;
+ uint32_t fabricclk_mhz;
+ uint32_t dispclk_mhz;
+ uint32_t phyclk_mhz;
+ uint32_t dppclk_mhz;
+};
+
+struct gpu_info_soc_bounding_box_v1_0 {
+ uint32_t sr_exit_time_us;
+ uint32_t sr_enter_plus_exit_time_us;
+ uint32_t urgent_latency_us;
+ uint32_t urgent_latency_pixel_data_only_us;
+ uint32_t urgent_latency_pixel_mixed_with_vm_data_us;
+ uint32_t urgent_latency_vm_data_only_us;
+ uint32_t writeback_latency_us;
+ uint32_t ideal_dram_bw_after_urgent_percent;
+ uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_only; //
PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
+ uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
+ uint32_t pct_ideal_dram_sdp_bw_after_urgent_vm_only;
+ uint32_t max_avg_sdp_bw_use_normal_percent;
+ uint32_t max_avg_dram_bw_use_normal_percent;
+ unsigned int max_request_size_bytes;
+ uint32_t downspread_percent;
+ uint32_t dram_page_open_time_ns;
+ uint32_t dram_rw_turnaround_time_ns;
+ uint32_t dram_return_buffer_per_channel_bytes;
+ uint32_t dram_channel_width_bytes;
+ uint32_t fabric_datapath_to_dcn_data_return_bytes;
+ uint32_t dcn_downspread_percent;
+ uint32_t dispclk_dppclk_vco_speed_mhz;
+ uint32_t dfs_vco_period_ps;
+ unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
+ unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
+ unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
+ unsigned int round_trip_ping_latency_dcfclk_cycles;
+ unsigned int urgent_out_of_order_return_per_channel_bytes;
+ unsigned int channel_interleave_bytes;
+ unsigned int num_banks;
+ unsigned int num_chans;
+ unsigned int vmm_page_size_bytes;
+ uint32_t dram_clock_change_latency_us;
+ uint32_t writeback_dram_clock_change_latency_us;
+ unsigned int return_bus_width_bytes;
+ unsigned int voltage_override;
+
[PATCH 307/459] drm/amd/powerplay: enable BACO feature as WAR
From: Jack Xiao It would hit SMU fw bug without BACO enablement when audio driver put audio device to D3 state. Before the bug in SMU fw get fixed, enable BACO feature as WAR. Signed-off-by: Jack Xiao Acked-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index c4bd14ab2add..f781c7f4ba46 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -331,6 +331,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT) | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) + | FEATURE_MASK(FEATURE_BACO_BIT) | FEATURE_MASK(FEATURE_ACDC_BIT); if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 311/459] drm/amd/powerplay: allow dc request uclk change
From: hersen wu
when dc set mode or color format in frame buffer
change, it may request clock changes, like dispclk,
dcfclk, uclk. after smu get clock requests, smu
will make decision.
Signed-off-by: hersen wu
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 93714ee9f32e..7366ef36ac55 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1277,8 +1277,9 @@ smu_v11_0_display_clock_voltage_request(struct
smu_context *smu,
if (!smu->pm_enabled)
return -EINVAL;
+
if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
- smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
+ smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
switch (clk_type) {
case amd_pp_dcef_clock:
clk_select = SMU_DCEFCLK;
--
2.20.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 332/459] drm/amd/display: Add DCN2 VMID
From: Harry Wentland
Add support to program DCN2 VMID (Virtual Memory Support)
Signed-off-by: Harry Wentland
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c | 62 +
.../gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h | 91 +++
2 files changed, 153 insertions(+)
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c
create mode 100644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c
new file mode 100644
index ..50953c0bd4e3
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dcn20_vmid.h"
+#include "reg_helper.h"
+
+#define REG(reg)\
+ vmid->regs->reg
+
+#define CTX \
+ vmid->ctx
+
+#undef FN
+#define FN(reg_name, field_name) \
+ vmid->shifts->field_name, vmid->masks->field_name
+
+void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct
dcn_vmid_page_table_config *config)
+{
+ REG_SET(PAGE_TABLE_START_ADDR_HI32, 0,
+ VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4,
(config->page_table_start_addr >> 32) & 0xF);
+ REG_SET(PAGE_TABLE_START_ADDR_LO32, 0,
+ VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32,
config->page_table_start_addr & 0x);
+
+ REG_SET(PAGE_TABLE_END_ADDR_HI32, 0,
+ VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4,
(config->page_table_end_addr >> 32) & 0xF);
+ REG_SET(PAGE_TABLE_END_ADDR_LO32, 0,
+ VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32,
config->page_table_end_addr & 0x);
+
+ REG_SET_2(CNTL, 0,
+ VM_CONTEXT0_PAGE_TABLE_DEPTH, config->depth,
+ VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, config->block_size);
+}
+
+void dcn20_vmid_set_ptb(struct dcn20_vmid *vmid, uint64_t base)
+{
+ REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0,
+ VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, (base >> 32) &
0x);
+ REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0,
+ VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, base &
0x);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h
new file mode 100644
index ..9c2f7016af2a
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#ifndef DAL_DC_DCN20_DCN20_VMID_H_
+#define DAL_DC_DCN20_DCN20_VMID_H_
+
+#include "vmid.h"
+
+#define BASE_INNER(seg) \
+ DCE_BASE__INST0_SEG ## seg
+
[PATCH 314/459] drm/amdgpu: Split gpu_info_soc_bounding_box out from amdgpu_ucode.h
From: Leo Li
DC needs to include the soc bounding box when initializing HW resources.
Including amdgpu_ucode.h directly will cause warnings, since amdgpu.h is
required to define amdgpu_device. The solution here is to split the
bounding box structs into a different header, then include it in both
amdgpu_ucode.h, and relevant DC HW resource files.
Signed-off-by: Leo Li
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h | 82 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 58 +---
2 files changed, 84 insertions(+), 56 deletions(-)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h
new file mode 100644
index ..3282dfa50433
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_socbb.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __AMDGPU_SOCBB_H__
+#define __AMDGPU_SOCBB_H__
+
+struct gpu_info_voltage_scaling_v1_0 {
+ int state;
+ uint32_t dscclk_mhz;
+ uint32_t dcfclk_mhz;
+ uint32_t socclk_mhz;
+ uint32_t dram_speed_mts;
+ uint32_t fabricclk_mhz;
+ uint32_t dispclk_mhz;
+ uint32_t phyclk_mhz;
+ uint32_t dppclk_mhz;
+};
+
+struct gpu_info_soc_bounding_box_v1_0 {
+ uint32_t sr_exit_time_us;
+ uint32_t sr_enter_plus_exit_time_us;
+ uint32_t urgent_latency_us;
+ uint32_t urgent_latency_pixel_data_only_us;
+ uint32_t urgent_latency_pixel_mixed_with_vm_data_us;
+ uint32_t urgent_latency_vm_data_only_us;
+ uint32_t writeback_latency_us;
+ uint32_t ideal_dram_bw_after_urgent_percent;
+ uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_only; //
PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly
+ uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;
+ uint32_t pct_ideal_dram_sdp_bw_after_urgent_vm_only;
+ uint32_t max_avg_sdp_bw_use_normal_percent;
+ uint32_t max_avg_dram_bw_use_normal_percent;
+ unsigned int max_request_size_bytes;
+ uint32_t downspread_percent;
+ uint32_t dram_page_open_time_ns;
+ uint32_t dram_rw_turnaround_time_ns;
+ uint32_t dram_return_buffer_per_channel_bytes;
+ uint32_t dram_channel_width_bytes;
+ uint32_t fabric_datapath_to_dcn_data_return_bytes;
+ uint32_t dcn_downspread_percent;
+ uint32_t dispclk_dppclk_vco_speed_mhz;
+ uint32_t dfs_vco_period_ps;
+ unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
+ unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
+ unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
+ unsigned int round_trip_ping_latency_dcfclk_cycles;
+ unsigned int urgent_out_of_order_return_per_channel_bytes;
+ unsigned int channel_interleave_bytes;
+ unsigned int num_banks;
+ unsigned int num_chans;
+ unsigned int vmm_page_size_bytes;
+ uint32_t dram_clock_change_latency_us;
+ uint32_t writeback_dram_clock_change_latency_us;
+ unsigned int return_bus_width_bytes;
+ unsigned int voltage_override;
+ uint32_t xfc_bus_transport_time_us;
+ uint32_t xfc_xbuf_latency_tolerance_us;
+ int use_urgent_burst_bw;
+ unsigned int num_states;
+ struct gpu_info_voltage_scaling_v1_0 clock_limits[8];
+};
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 52b024917075..f46944453c6e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -23,6 +23,8 @@
#ifndef __AMDGPU_UCODE_H__
#define __AMDGPU_UCODE_H__
+#include "amdgpu_socbb.h"
+
struct common_firmware_header {
uint32_t size_bytes; /* size of
[PATCH 309/459] drm/amdgpu: fix PA_SC_FIFO_SIZE for Navi10
From: Marek Olšák Signed-off-by: Marek Olšák Reviewed-by: Xiaojie Yuan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 779597a6f33a..0090cba2d24d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -1017,7 +1017,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev) adev->gfx.config.max_hw_contexts = 8; adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; adev->gfx.config.sc_prim_fifo_size_backend = 0x100; - adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; + adev->gfx.config.sc_hiz_tile_fifo_size = 0; adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG); break; @@ -1553,15 +1553,16 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) */ gfx_v10_0_select_se_sh(adev, 0x, 0x, 0x); - WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE, - (adev->gfx.config.sc_prim_fifo_size_frontend << - PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) | - (adev->gfx.config.sc_prim_fifo_size_backend << - PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) | - (adev->gfx.config.sc_hiz_tile_fifo_size << - PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) | - (adev->gfx.config.sc_earlyz_tile_fifo_size << - PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)); + tmp = REG_SET_FIELD(0, PA_SC_FIFO_SIZE, SC_FRONTEND_PRIM_FIFO_SIZE, + adev->gfx.config.sc_prim_fifo_size_frontend); + tmp = REG_SET_FIELD(tmp, PA_SC_FIFO_SIZE, SC_BACKEND_PRIM_FIFO_SIZE, + adev->gfx.config.sc_prim_fifo_size_backend); + tmp = REG_SET_FIELD(tmp, PA_SC_FIFO_SIZE, SC_HIZ_TILE_FIFO_SIZE, + adev->gfx.config.sc_hiz_tile_fifo_size); + tmp = REG_SET_FIELD(tmp, PA_SC_FIFO_SIZE, SC_EARLYZ_TILE_FIFO_SIZE, + adev->gfx.config.sc_earlyz_tile_fifo_size); + WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE, tmp); + mutex_unlock(>grbm_idx_mutex); } -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 305/459] drm/amdgpu: add new navi10 DIDs
From: tiancyin
Reviewed-by: Jack Xiao
Signed-off-by: tiancyin
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d0168e03d85e..7cf6ab07b113 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -989,7 +989,9 @@ static const struct pci_device_id pciidlist[] = {
{0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
{0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
{0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
+ {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
{0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
+ {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
{0, 0, 0}
--
2.20.1
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[PATCH 310/459] drm/amdgpu: initialize THM & CLK IP registers base address
From: Hawking Zhang Signed-off-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c b/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c index 8cd4568c07ee..55014ce8670a 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_reg_init.c @@ -58,6 +58,8 @@ int navi10_reg_base_init(struct amdgpu_device *adev) adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i])); adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i])); + adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i])); + adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i])); } return 0; -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 308/459] drm/amd/powerplay: remove unsupport function set_thermal_fan_table for navi10
From: Kevin Wang
the PPSMC_MSG_SetFanTemperatureTarget is not support on navi10
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index f781c7f4ba46..e29d2da21fbc 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -885,18 +885,6 @@ static bool navi10_is_dpm_running(struct smu_context *smu)
return !!(feature_enabled & SMC_DPM_FEATURE);
}
-static int navi10_set_thermal_fan_table(struct smu_context *smu)
-{
- int ret;
- struct smu_table_context *table_context = >smu_table;
- PPTable_t *pptable = table_context->driver_pptable;
-
- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_SetFanTemperatureTarget,
- (uint32_t)pptable->FanTargetTemperature);
-
- return ret;
-}
-
static int navi10_get_fan_speed_percent(struct smu_context *smu,
uint32_t *speed)
{
@@ -1309,7 +1297,6 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.force_dpm_limit_value = navi10_force_dpm_limit_value,
.unforce_dpm_levels = navi10_unforce_dpm_levels,
.is_dpm_running = navi10_is_dpm_running,
- .set_thermal_fan_table = navi10_set_thermal_fan_table,
.get_fan_speed_percent = navi10_get_fan_speed_percent,
.get_power_profile_mode = navi10_get_power_profile_mode,
.set_power_profile_mode = navi10_set_power_profile_mode,
--
2.20.1
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[PATCH 302/459] drm/amdgpu/powerplay/vega20: use correct table index
Use the SMU_* variant so we look up the correct index.
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 514e40979f19..adf51f9e1e73 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1802,7 +1802,7 @@ static int vega20_get_power_profile_mode(struct
smu_context *smu, char *buf)
/* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
workload_type = smu_workload_get_type(smu, i);
result = smu_update_table(smu,
- TABLE_ACTIVITY_MONITOR_COEFF |
workload_type << 16,
+ SMU_TABLE_ACTIVITY_MONITOR_COEFF |
workload_type << 16,
(void *)(_monitor), false);
if (result) {
pr_err("[%s] Failed to get activity monitor!",
__func__);
@@ -1888,7 +1888,7 @@ static int vega20_set_power_profile_mode(struct
smu_context *smu, long *input, u
if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
ret = smu_update_table(smu,
- TABLE_ACTIVITY_MONITOR_COEFF |
WORKLOAD_PPLIB_CUSTOM_BIT << 16,
+ SMU_TABLE_ACTIVITY_MONITOR_COEFF |
WORKLOAD_PPLIB_CUSTOM_BIT << 16,
(void *)(_monitor), false);
if (ret) {
pr_err("[%s] Failed to get activity monitor!",
__func__);
@@ -1943,7 +1943,7 @@ static int vega20_set_power_profile_mode(struct
smu_context *smu, long *input, u
}
ret = smu_update_table(smu,
- TABLE_ACTIVITY_MONITOR_COEFF |
WORKLOAD_PPLIB_CUSTOM_BIT << 16,
+ SMU_TABLE_ACTIVITY_MONITOR_COEFF |
WORKLOAD_PPLIB_CUSTOM_BIT << 16,
(void *)(_monitor), true);
if (ret) {
pr_err("[%s] Failed to set activity monitor!",
__func__);
@@ -2767,7 +2767,7 @@ static int vega20_odn_edit_dpm_table(struct smu_context
*smu,
break;
case PP_OD_RESTORE_DEFAULT_TABLE:
- ret = smu_update_table(smu, TABLE_OVERDRIVE,
table_context->overdrive_table, false);
+ ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
table_context->overdrive_table, false);
if (ret) {
pr_err("Failed to export over drive table!\n");
return ret;
@@ -2776,7 +2776,7 @@ static int vega20_odn_edit_dpm_table(struct smu_context
*smu,
break;
case PP_OD_COMMIT_DPM_TABLE:
- ret = smu_update_table(smu, TABLE_OVERDRIVE,
table_context->overdrive_table, true);
+ ret = smu_update_table(smu, SMU_TABLE_OVERDRIVE,
table_context->overdrive_table, true);
if (ret) {
pr_err("Failed to import over drive table!\n");
return ret;
--
2.20.1
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[PATCH 304/459] drm/amd/powerplay: add ppt interface version log
From: tiancyin
Signed-off-by: tiancyin
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 3f1176420b0e..93714ee9f32e 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -257,8 +257,10 @@ static int smu_v11_0_check_fw_version(struct smu_context
*smu)
smu_minor = (smu_version >> 8) & 0xff;
smu_debug = (smu_version >> 0) & 0xff;
- pr_info("SMU Driver IF Version = 0x%08x, SMU FW Version = 0x%08x
(%d.%d.%d)\n",
- if_version, smu_version, smu_major, smu_minor, smu_debug);
+ pr_info("SMU Driver IF Version = 0x%08x, SMU FW IF Version = 0x%08x,"
+ " SMU FW Version = 0x%08x (%d.%d.%d)\n",
+ if_version, smu->smc_if_version,
+ smu_version, smu_major, smu_minor, smu_debug);
if (if_version != smu->smc_if_version) {
pr_err("SMU driver if version not matched\n");
--
2.20.1
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[PATCH 300/459] drm/amdgpu/VCN: implement indirect DPG SRAM mode
From: Leo Liu
SRAM will be programmed by PSP
Signed-off-by: Leo Liu
Reviewed-by: James Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 3 ++
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 69 ++---
2 files changed, 53 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 762cffeaf301..99f14fcc1460 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -111,6 +111,9 @@
(0x1 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT |
\
mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT |
\
offset <<
UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
+ } else {
\
+ *adev->vcn.dpg_sram_curr_addr++ = offset;
\
+ *adev->vcn.dpg_sram_curr_addr++ = value;
\
}
\
} while (0)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index bef20704e2b9..77f4c631afa0 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -28,6 +28,7 @@
#include "soc15.h"
#include "soc15d.h"
#include "amdgpu_pm.h"
+#include "amdgpu_psp.h"
#include "vcn/vcn_2_0_0_offset.h"
#include "vcn/vcn_2_0_0_sh_mask.h"
@@ -407,14 +408,23 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct
amdgpu_device *adev, bool indirec
/* cache window 0: fw */
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
- WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
-
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
- WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
-
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
- WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
+ if (!indirect) {
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0,
indirect);
+ } else {
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0,
0, indirect);
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
0, 0, indirect);
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0,
indirect);
+ }
offset = 0;
} else {
WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
@@ -429,18 +439,31 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct
amdgpu_device *adev, bool indirec
AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
}
- WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
+ if (!indirect)
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
+ else
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
/* cache window 1: stack */
- WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
- lower_32_bits(adev->vcn.gpu_addr + offset), 0, indirect);
- WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
- upper_32_bits(adev->vcn.gpu_addr + offset), 0, indirect);
-
[PATCH 296/459] drm/amdgpu/psp: add new psp interface for vcn updating sram
From: Jack Xiao
PSP leverages the existing fw loading function for vcn updating sram.
Signed-off-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 3 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index e9794e3c3936..3c08e5c483f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1214,6 +1214,19 @@ int psp_rlc_autoload_start(struct psp_context *psp)
return ret;
}
+int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
+ uint64_t cmd_gpu_addr, int cmd_size)
+{
+ struct amdgpu_firmware_info ucode = {0};
+
+ ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
+ AMDGPU_UCODE_ID_VCN0_RAM;
+ ucode.mc_addr = cmd_gpu_addr;
+ ucode.ucode_size = cmd_size;
+
+ return psp_execute_np_fw_load(>psp, );
+}
+
static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
enum AMDGPU_UCODE_ID ucode_type)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index aa5668df03b6..6039acc84346 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -260,6 +260,9 @@ extern int psp_wait_for(struct psp_context *psp, uint32_t
reg_index,
extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
int psp_gpu_reset(struct amdgpu_device *adev);
+int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
+ uint64_t cmd_gpu_addr, int cmd_size);
+
int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
--
2.20.1
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[PATCH 297/459] drm/amd/powerplay: update smu11_driver_if_navi10.h
From: Jack Xiao
update the smu11_driver_if_navi10.h since navi10 smu fw
update to 42.23
Signed-off-by: Jack Xiao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
.../powerplay/inc/smu11_driver_if_navi10.h| 24 +++
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
index b3993d382ad5..a8b31bc50054 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_navi10.h
@@ -26,7 +26,7 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x2F
+#define SMU11_DRIVER_IF_VERSION 0x32
#define PPTABLE_NV10_SMU_VERSION 8
@@ -114,7 +114,7 @@
#define FEATURE_MMHUB_PG_BIT40
#define FEATURE_ATHUB_PG_BIT41
-#define FEATURE_SPARE_42_BIT42
+#define FEATURE_APCC_DFLL_BIT 42
#define FEATURE_SPARE_43_BIT43
#define FEATURE_SPARE_44_BIT44
#define FEATURE_SPARE_45_BIT45
@@ -490,23 +490,26 @@ typedef struct {
uint16_t FanTargetTemperature;
uint16_t MemoryTemperatureLimit;
- uint16_t Reserved2;
+ uint16_t MemoryTemperatureLimit1;
uint16_t TGP;
- uint16_t Reserved3;
+ uint16_t CardPower;
uint32_t DieTemperatureRegisterOffset;
- uint32_t Reserved4;
+ uint32_t Reserved2;
- uint32_t Reserved5;
+ uint32_t Reserved3;
uint32_t Status;
uint16_t DieTemperature;
uint16_t MemoryTemperature;
- uint32_t MmHubPadding[8]; // SMU internal use
+ uint16_t SelectedCardPower;
+ uint16_t Reserved4;
+
+ uint32_t BoardLevelEnergyAccumulator;
} OutOfBandMonitor_t;
typedef struct {
@@ -794,8 +797,8 @@ typedef struct {
uint16_t BoardPadding;
// Mvdd Svi2 Div Ratio Setting
- uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16
fractional bits (Q16.16)
-
+ uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16
fractional bits (Q16.16)
+
uint32_t BoardReserved[9];
// Padding for MMHUB - do not modify this
@@ -865,7 +868,8 @@ typedef struct {
uint32_t ThrottlerStatus ;
uint8_t LinkDpmLevel;
- uint8_t Padding[3];
+ uint8_t Padding8_2;
+ uint16_t CurrFanSpeed;
// Padding - ignore
uint32_t MmHubPadding[8]; // SMU internal use
--
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[PATCH 298/459] drm/amd/powerplay: disable fw dstate when gfxoff is enabled
From: Jack Xiao
SMU FW has bug that it would cause hung when both fw dstate and
gfxoff are enabled at the same time.
Signed-off-by: Jack Xiao
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 4db5ecd385a4..af0abed6169e 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -336,9 +336,12 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
| FEATURE_MASK(FEATURE_ACDC_BIT);
- if (adev->pm.pp_feature & PP_GFXOFF_MASK)
+ if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
| FEATURE_MASK(FEATURE_GFXOFF_BIT);
+ /* TODO: remove it once fw fix the bug */
+ *(uint64_t *)feature_mask &=
~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
+ }
if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
--
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[PATCH 299/459] drm/amdgpu/VCN: add buffer for indirect SRAM usage
From: Leo Liu
This will be used later for indirect SRAM mode
Signed-off-by: Leo Liu
Reviewed-by: James Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 16
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 6 ++
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index d0b95e58959a..7621077378dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -137,6 +137,16 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
return r;
}
+ if (adev->vcn.indirect_sram) {
+ r = amdgpu_bo_create_kernel(adev, 64 * 2 * 4, PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM, >vcn.dpg_sram_bo,
+ >vcn.dpg_sram_gpu_addr,
>vcn.dpg_sram_cpu_addr);
+ if (r) {
+ dev_err(adev->dev, "(%d) failed to allocate DPG bo\n",
r);
+ return r;
+ }
+ }
+
return 0;
}
@@ -146,6 +156,12 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
kvfree(adev->vcn.saved_bo);
+ if (adev->vcn.indirect_sram) {
+ amdgpu_bo_free_kernel(>vcn.dpg_sram_bo,
+ >vcn.dpg_sram_gpu_addr,
+ (void **)>vcn.dpg_sram_cpu_addr);
+ }
+
amdgpu_bo_free_kernel(>vcn.vcpu_bo,
>vcn.gpu_addr,
(void **)>vcn.cpu_addr);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 5b38798f8bc3..762cffeaf301 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -164,6 +164,12 @@ struct amdgpu_vcn {
struct amdgpu_vcn_reg internal, external;
int (*pause_dpg_mode)(struct amdgpu_device *adev,
struct dpg_pause_state *new_state);
+
+ boolindirect_sram;
+ struct amdgpu_bo*dpg_sram_bo;
+ void*dpg_sram_cpu_addr;
+ uint64_tdpg_sram_gpu_addr;
+ uint32_t*dpg_sram_curr_addr;
};
int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
--
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Re: [PATCH 000/459] amdgpu support for Navi10
Looks like my mail relay has blocked the rest of this series for sending too many emails. Please see the git link. Alex On Mon, Jun 17, 2019 at 3:26 PM Alex Deucher wrote: > > Hi, > > This patch set adds support for Navi10 asics to amdgpu. This includes > support for: > - Core driver support > - Displays (DCN2) > - GFX and compute (GFX10) > - System DMA (SDMA 5) > - Multimedia decode and encode (VCN2) > - Power management > > The new register headers are huge, so I have not sent them out. You can find > the full patch series here: > https://cgit.freedesktop.org/~agd5f/linux/log/?h=amd-staging-drm-next-navi10 > > LLVM changes are already working their way upstream and mesa changes (OpenGL > and > Multmedia) will be available shortly. > > > Aidan Wood (2): > drm/amd/display: Properly set DCF clock > drm/amd/display: Properly set u clock > > Alex Deucher (15): > drm/amdkfd: Introduce DIQ type mqd manager for gfx10 > drm/amdkfd: Add mqd size in mqd manager struct for gfx10 > drm/amdkfd: Allocate hiq and sdma mqd from mqd trunk for gfx10 > drm/amdkfd: Introduce XGMI SDMA queue type for gfx10 > drm/amdkfd: Delete alloc_format field from map_queue struct for gfx10 > drm/amdkfd: update gfx10 support for latest kfd changes > drm/amdkfd: add more navi10 pci ids > drm/amdgpu: add Navi10 pci ids > drm/amd/powerplay/smu11: remove smu_update_table_with_arg > drm/amdgpu/powerplay: add license to smu11 header > drm/amdgpu/powerplay/vega20: use correct table index > drm/amdgpu/gfx10: update to latest golden setting > drm/amd/display: add fast_validate parameter to > dcn20_validate_bandwidth > drm/amd/display: updates for dcn20_update_bandwidth > drm/amd/display: update dcn2 dc_plane_cap > > Anthony Koo (1): > drm/amd/display: do not power on eDP power rail early > > Aric Cyr (1): > drm/amd/display: Intermittent DCN2 pipe hang on mode change > > Bob Yang (1): > drm/amd/display: fixed DCC corruption > > Charlene Liu (13): > drm/amd/display: dcn2 dmcu wait_for_loop update with dispclk. > drm/amd/display: fix can not turn on two displays due to DSC_RESOURCE > failed. > drm/amd/display: Add hubp_init entry to hubp vtable > drm/amd/display: add SW_USE_I2C_REG request. > drm/amd/display: Create DWB resource for DCN2 > drm/amd/display: [backport] dwb dm + efc support > drm/amd/display: used optimum VSTARTUP instead of MaxVStartup > drm/amd/display: Return UPDATE_TYPE_FULL on writeback update > drm/amd/display: add some parameters to validate bandwidth functions > drm/amd/display: add dwb stere caps and version > drm/amd/display: add p010 and ayuv plane caps > drm/amd/display: dcn2 use fixed clocks. > drm/amd/display: expose dentist_get_did_from_divider > > Chris Park (1): > drm/amd/display: Move link functions from dc to dc_link > > Christian König (1): > drm/amdgpu: disable concurrent flushes for Navi10 v2 > > Dmytro Laktyushkin (9): > drm/amd/display: clean up validation failure log spam > drm/amd/display: fix dsc validation > drm/amd/display: fix fpga fclk programming > drm/amd/display: fix dcn2 mpc split decision > drm/amd/display: fix odm mpo disable > drm/amd/display: fix macro_tile_size for tiling > drm/amd/display: add null checks and set update flags for DCN2 > drm/amd/display: move vmid determination logic to a module > drm/amd/display: add missing mod_vmid destructor > > Eric Bernstein (3): > drm/amd/display: Refactor DIO stream encoder > drm/amd/display: Alpha plane type > drm/amd/display: expose enable dp output functions > > Eric Yang (1): > drm/amd/display: Refactor clk_mgr functions > > Eryk Brol (2): > drm/amd/display: Ensure DRR triggers in BP > drm/amd/display: Change DCN2 vupdate start programming > > Harry Wentland (23): > drm/amd/display: Read soc_bounding_box from gpu_info (v2) > drm/amd/display: Add DCN2 and NV ASIC ID > drm/amd/display: add AUX and I2C for DCN2 > drm/amd/display: Add GPIO support for DCN2 > drm/amd/display: Add DCN2 BIOS parsing > drm/amd/display: Add DCN2 IRQ handling > drm/amd/display: Add DCN2 changes to DML > drm/amd/display: Add DCN2 DIO > drm/amd/display: Add DCN2 clk mgr > drm/amd/display: Add DCN2 OPTC > drm/amd/display: Add DCN2 OPP > drm/amd/display: Add DCN2 MPC > drm/amd/display: Add DCN2 DPP > drm/amd/display: Add DCN2 HUBP and HUBBUB > drm/amd/display: Add DCN2 MMHUBBUB > drm/amd/display: Add DCN2 DWB > drm/amd/display: Add DCN2 IPP > drm/amd/display: Add DCN2 VMID > drm/amd/display: Add DCN2 HW Sequencer and Resource > drm/amd/display: Add DC core changes for DCN2 > drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2) > drm/amdgpu: Enable DC support for Navi10 > drm/amd/display: Add DSC support for Navi (v2) > > Hawking Zhang (82): > drm/amdgpu: add ATHUB 2.0 register headers > drm/amdgpu: add CLK 11.0 register headers > drm/amdgpu: add DCN 2.0 register headers > drm/amdgpu: add HDP 5.0
[PATCH 296/459] drm/amdgpu/psp: add new psp interface for vcn updating sram
From: Jack Xiao
PSP leverages the existing fw loading function for vcn updating sram.
Signed-off-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 13 +
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 3 +++
2 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index e9794e3c3936..3c08e5c483f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1214,6 +1214,19 @@ int psp_rlc_autoload_start(struct psp_context *psp)
return ret;
}
+int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
+ uint64_t cmd_gpu_addr, int cmd_size)
+{
+ struct amdgpu_firmware_info ucode = {0};
+
+ ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
+ AMDGPU_UCODE_ID_VCN0_RAM;
+ ucode.mc_addr = cmd_gpu_addr;
+ ucode.ucode_size = cmd_size;
+
+ return psp_execute_np_fw_load(>psp, );
+}
+
static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
enum AMDGPU_UCODE_ID ucode_type)
{
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index aa5668df03b6..6039acc84346 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -260,6 +260,9 @@ extern int psp_wait_for(struct psp_context *psp, uint32_t
reg_index,
extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
int psp_gpu_reset(struct amdgpu_device *adev);
+int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
+ uint64_t cmd_gpu_addr, int cmd_size);
+
int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id);
--
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[PATCH 293/459] drm/amdgpu/psp: add new VCN RAM ucode id to psp
From: Jack Xiao
PSP supports to program vcn sram by ucode loading interface.
Signed-off-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
index 9486bb36ebf9..5080a73a95a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
@@ -233,6 +233,8 @@ enum psp_gfx_fw_type {
GFX_FW_TYPE_RLCP_CAM= 46, /* RLCP CAM
NV */
GFX_FW_TYPE_RLC_SPP_CAM_EXT = 47, /* RLC SPP CAM EXT
NV */
GFX_FW_TYPE_RLX6_DRAM_BOOT = 48, /* RLX6 DRAM BOOT
NV */
+ GFX_FW_TYPE_VCN0_RAM= 49, /* VCN_RAM NV */
+ GFX_FW_TYPE_VCN1_RAM= 50, /* VCN_RAM NV */
GFX_FW_TYPE_MAX
};
--
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[PATCH 295/459] drm/amdgpu/psp: convert ucode id to psp ucode id
From: Jack Xiao Convert ucode id to the corresponding psp ucode id. Signed-off-by: Jack Xiao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index bbc3b0488982..e9794e3c3936 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -891,6 +891,12 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, case AMDGPU_UCODE_ID_DMCU_INTV: *type = GFX_FW_TYPE_DMCU_ISR; break; + case AMDGPU_UCODE_ID_VCN0_RAM: + *type = GFX_FW_TYPE_VCN0_RAM; + break; + case AMDGPU_UCODE_ID_VCN1_RAM: + *type = GFX_FW_TYPE_VCN1_RAM; + break; case AMDGPU_UCODE_ID_MAXIMUM: default: return -EINVAL; -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 294/459] drm/amdgpu: add corresponding vcn ram ucode id
From: Jack Xiao
Add VCN RAM ucode id in corresponding to psp ucode id.
Signed-off-by: Jack Xiao
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
index 37810e07304e..07f035937650 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
@@ -271,6 +271,8 @@ enum AMDGPU_UCODE_ID {
AMDGPU_UCODE_ID_VCN,
AMDGPU_UCODE_ID_DMCU_ERAM,
AMDGPU_UCODE_ID_DMCU_INTV,
+ AMDGPU_UCODE_ID_VCN0_RAM,
+ AMDGPU_UCODE_ID_VCN1_RAM,
AMDGPU_UCODE_ID_MAXIMUM,
};
--
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[PATCH 270/459] drm/amd/powerplay: move function thermal_get_temperature to veag20_ppt
From: Kevin Wang
the fcuntion thermal_get_temperature will be access SmuMetrics_t data,
the data structure is asic related, so move vega20_ppt to implement.
Signed-off-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 7
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 48 ++
2 files changed, 48 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 538f52ab4b72..175463d9aa2d 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -1265,7 +1265,6 @@ static int smu_v11_0_thermal_get_temperature(struct
smu_context *smu,
return 0;
}
-
static uint16_t convert_to_vddc(uint8_t vid)
{
return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
@@ -1304,12 +1303,6 @@ static int smu_v11_0_read_sensor(struct smu_context *smu,
ret = smu_get_current_clk_freq(smu, SMU_GFXCLK, (uint32_t
*)data);
*size = 4;
break;
- case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
- case AMDGPU_PP_SENSOR_EDGE_TEMP:
- case AMDGPU_PP_SENSOR_MEM_TEMP:
- ret = smu_v11_0_thermal_get_temperature(smu, sensor, (uint32_t
*)data);
- *size = 4;
- break;
case AMDGPU_PP_SENSOR_VDDGFX:
ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
*size = 4;
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index dd354a993bf1..625718cc8b63 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -3000,6 +3000,48 @@ static int vega20_get_current_activity_percent(struct
smu_context *smu,
return 0;
}
+static int vega20_thermal_get_temperature(struct smu_context *smu,
+enum amd_pp_sensors sensor,
+uint32_t *value)
+{
+ struct amdgpu_device *adev = smu->adev;
+ SmuMetrics_t metrics;
+ uint32_t temp = 0;
+ int ret = 0;
+
+ if (!value)
+ return -EINVAL;
+
+ ret = vega20_get_metrics_table(smu, );
+ if (ret)
+ return ret;
+
+ switch (sensor) {
+ case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
+ temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
+ temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
+ CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
+
+ temp = temp & 0x1ff;
+ temp *= SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES;
+
+ *value = temp;
+ break;
+ case AMDGPU_PP_SENSOR_EDGE_TEMP:
+ *value = metrics.TemperatureEdge *
+ PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ break;
+ case AMDGPU_PP_SENSOR_MEM_TEMP:
+ *value = metrics.TemperatureHBM *
+ PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ break;
+ default:
+ pr_err("Invalid sensor for retrieving temp\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
static int vega20_read_sensor(struct smu_context *smu,
enum amd_pp_sensors sensor,
void *data, uint32_t *size)
@@ -3024,6 +3066,12 @@ static int vega20_read_sensor(struct smu_context *smu,
ret = vega20_get_gpu_power(smu, (uint32_t *)data);
*size = 4;
break;
+ case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
+ case AMDGPU_PP_SENSOR_EDGE_TEMP:
+ case AMDGPU_PP_SENSOR_MEM_TEMP:
+ ret = vega20_thermal_get_temperature(smu, sensor, (uint32_t
*)data);
+ *size = 4;
+ break;
default:
return -EINVAL;
}
--
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[PATCH 259/459] drm/amd/powerplay/smu11: enable ds socclk by default
From: Tao Zhou Signed-off-by: Tao Zhou Acked-by: Alex Deucher Reviewed-by: Kevin Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index 5f697ed3796b..f1f920234dbd 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -299,6 +299,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, | FEATURE_MASK(FEATURE_DPM_LINK_BIT) | FEATURE_MASK(FEATURE_GFX_ULV_BIT) | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT) + | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT) | FEATURE_MASK(FEATURE_PPT_BIT) | FEATURE_MASK(FEATURE_TDC_BIT) | FEATURE_MASK(FEATURE_GFX_EDC_BIT) -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 254/459] amd/powerplay: update the vcn pg
From: Kenneth Feng
update the vcn pg function in navi10.
Signed-off-by: Kenneth Feng
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 6 ++
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 14 ++
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index b62d272380d5..a4812c05c09c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -439,9 +439,15 @@ struct smu_dpm_context {
struct mclock_latency_table *mclk_latency_table;
};
+struct smu_power_gate {
+ bool uvd_gated;
+ bool vce_gated;
+};
+
struct smu_power_context {
void *power_context;
uint32_t power_context_size;
+ struct smu_power_gate power_gate;
};
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 186c5726580a..cea5704e3f4f 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -521,15 +521,21 @@ static int navi10_set_default_dpm_table(struct
smu_context *smu)
static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
{
int ret = 0;
+ struct smu_power_context *smu_power = >smu_power;
+ struct smu_power_gate *power_gate = _power->power_gate;
- if (enable) {
+ if (enable && power_gate->uvd_gated) {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
if (ret)
return ret;
+ power_gate->uvd_gated = false;
} else {
- ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
- if (ret)
- return ret;
+ if (!enable && !power_gate->uvd_gated) {
+ ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
+ if (ret)
+ return ret;
+ power_gate->uvd_gated = true;
+ }
}
return 0;
--
2.20.1
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[PATCH 287/459] drm/amd/powerplay: simplified od_settings for each asic
From: Kevin Wang
the od_settings is asic related data, so move it to asic file.
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 12 --
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 7 +-
drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 139 +-
drivers/gpu/drm/amd/powerplay/vega20_ppt.h| 6 +
4 files changed, 77 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index a01ace1bda34..edd1da68c47d 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1058,21 +1058,9 @@ static int smu_hw_fini(void *handle)
kfree(table_context->max_sustainable_clocks);
table_context->max_sustainable_clocks = NULL;
- kfree(table_context->od_feature_capabilities);
- table_context->od_feature_capabilities = NULL;
-
- kfree(table_context->od_settings_max);
- table_context->od_settings_max = NULL;
-
- kfree(table_context->od_settings_min);
- table_context->od_settings_min = NULL;
-
kfree(table_context->overdrive_table);
table_context->overdrive_table = NULL;
- kfree(table_context->od8_settings);
- table_context->od8_settings = NULL;
-
kfree(smu->irq_source);
smu->irq_source = NULL;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 82c2c02347ac..a8e5f4d69861 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -431,13 +431,7 @@ struct smu_table_context
uint8_t thermal_controller_type;
uint16_tTDPODLimit;
- uint8_t *od_feature_capabilities;
- uint32_t*od_settings_max;
- uint32_t*od_settings_min;
void*overdrive_table;
- void*od8_settings;
- boolod_gfxclk_update;
- boolod_memclk_update;
};
struct smu_dpm_context {
@@ -510,6 +504,7 @@ struct smu_context
struct smu_power_contextsmu_power;
struct smu_feature smu_feature;
struct amd_pp_display_configuration *display_config;
+ void *od_settings;
uint32_t pstate_sclk;
uint32_t pstate_mclk;
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 43f9e2acb8e6..514e40979f19 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -365,6 +365,7 @@ static int vega20_setup_od8_information(struct smu_context
*smu)
{
ATOM_Vega20_POWERPLAYTABLE *powerplay_table = NULL;
struct smu_table_context *table_context = >smu_table;
+ struct vega20_od8_settings *od8_settings = (struct vega20_od8_settings
*)smu->od_settings;
uint32_t od_feature_count, od_feature_array_size,
od_setting_count, od_setting_array_size;
@@ -385,13 +386,13 @@ static int vega20_setup_od8_information(struct
smu_context *smu)
od_feature_array_size = sizeof(uint8_t) * od_feature_count;
- if (table_context->od_feature_capabilities)
+ if (od8_settings->od_feature_capabilities)
return -EINVAL;
- table_context->od_feature_capabilities =
kmemdup(_table->OverDrive8Table.ODFeatureCapabilities,
+ od8_settings->od_feature_capabilities =
kmemdup(_table->OverDrive8Table.ODFeatureCapabilities,
od_feature_array_size,
GFP_KERNEL);
- if (!table_context->od_feature_capabilities)
+ if (!od8_settings->od_feature_capabilities)
return -ENOMEM;
/* Setup correct ODSettingCount, and store ODSettingArray from
@@ -404,31 +405,31 @@ static int vega20_setup_od8_information(struct
smu_context *smu)
od_setting_array_size = sizeof(uint32_t) * od_setting_count;
- if (table_context->od_settings_max)
+ if (od8_settings->od_settings_max)
return -EINVAL;
- table_context->od_settings_max =
kmemdup(_table->OverDrive8Table.ODSettingsMax,
+ od8_settings->od_settings_max =
kmemdup(_table->OverDrive8Table.ODSettingsMax,
od_setting_array_size,
GFP_KERNEL);
- if (!table_context->od_settings_max) {
-
[PATCH 241/459] drm/amd/powerplay: add function get_current_activity_percent for navi10
From: Kevin Wang
add callback function get_current_activity_percent for navi10 asic
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index e21a1eaee8b9..711da04c30a8 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -767,6 +767,25 @@ static int navi10_get_gpu_power(struct smu_context *smu,
uint32_t *value)
return 0;
}
+static int navi10_get_current_activity_percent(struct smu_context *smu,
+ uint32_t *value)
+{
+ int ret = 0;
+ SmuMetrics_t metrics;
+
+ if (!value)
+ return -EINVAL;
+
+ ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
+ (void *), false);
+ if (ret)
+ return ret;
+
+ *value = metrics.AverageGfxActivity;
+
+ return 0;
+}
+
static const struct pptable_funcs navi10_ppt_funcs = {
.tables_init = navi10_tables_init,
.alloc_dpm_context = navi10_allocate_dpm_context,
@@ -791,6 +810,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.force_dpm_limit_value = navi10_force_dpm_limit_value,
.unforce_dpm_levels = navi10_unforce_dpm_levels,
.get_gpu_power = navi10_get_gpu_power,
+ .get_current_activity_percent = navi10_get_current_activity_percent,
};
void navi10_set_ppt_funcs(struct smu_context *smu)
--
2.20.1
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[PATCH 279/459] drm/amd/powerplay: add interface to get uclk dpm table
From: hersen wu
dc needs get uclk dpm table for bandwidth calculation
Signed-off-by: hersen wu
Acked-by: Alex Deucher
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 3 ++
drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 30 +++
2 files changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 8acc17973577..ccb41fc4f74f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -611,6 +611,7 @@ struct pptable_funcs {
enum smu_clk_type clk_type,
uint32_t *value);
int (*get_thermal_temperature_range)(struct smu_context *smu, struct
smu_temperature_range *range);
+ int (*get_uclk_dpm_states)(struct smu_context *smu, uint32_t
*clocks_in_khz, uint32_t *num_states);
};
struct smu_funcs
@@ -897,6 +898,8 @@ struct smu_funcs
((smu)->funcs->register_irq_handler ?
(smu)->funcs->register_irq_handler(smu) : 0)
#define smu_set_azalia_d3_pme(smu) \
((smu)->funcs->set_azalia_d3_pme ?
(smu)->funcs->set_azalia_d3_pme((smu)) : 0)
+#define smu_get_uclk_dpm_states(smu, clocks_in_khz, num_states) \
+ ((smu)->ppt_funcs->get_uclk_dpm_states ?
(smu)->ppt_funcs->get_uclk_dpm_states((smu), (clocks_in_khz), (num_states)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 15413f646e5a..4db5ecd385a4 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1248,6 +1248,35 @@ static int navi10_read_sensor(struct smu_context *smu,
return ret;
}
+static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t
*clocks_in_khz, uint32_t *num_states)
+{
+ uint32_t num_discrete_levels = 0;
+ uint16_t *dpm_levels = NULL;
+ uint16_t i = 0;
+ struct smu_table_context *table_context = >smu_table;
+ PPTable_t *driver_ppt = NULL;
+
+ if (!clocks_in_khz || ! num_states || !table_context->driver_pptable)
+ return -EINVAL;
+
+ driver_ppt = table_context->driver_pptable;
+ num_discrete_levels =
driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
+ dpm_levels = driver_ppt->FreqTableUclk;
+
+ if (num_discrete_levels == 0 || dpm_levels == NULL)
+ return -EINVAL;
+
+ *num_states = num_discrete_levels;
+ for (i = 0; i < num_discrete_levels; i++) {
+ /* convert to khz */
+ *clocks_in_khz = (*dpm_levels) * 1000;
+ clocks_in_khz++;
+ dpm_levels++;
+ }
+
+ return 0;
+}
+
static const struct pptable_funcs navi10_ppt_funcs = {
.tables_init = navi10_tables_init,
.alloc_dpm_context = navi10_allocate_dpm_context,
@@ -1281,6 +1310,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.get_profiling_clk_mask = navi10_get_profiling_clk_mask,
.set_watermarks_table = navi10_set_watermarks_table,
.read_sensor = navi10_read_sensor,
+ .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
};
void navi10_set_ppt_funcs(struct smu_context *smu)
--
2.20.1
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[PATCH 277/459] drm/amd/powerplay: notify smu with active display count
From: hersen wu
when dc update clocks via smu, smu needs to know how many
displays active. this interface is for dc notify number
of active displays to smu.
Signed-off-by: hersen wu
Reviewed-by: Huang Rui
Acked-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 13 -
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 8 +---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 +++---
3 files changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 35578be95da6..9384c1a5c594 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -802,7 +802,7 @@ static int smu_smc_table_hw_init(struct smu_context *smu,
return 0;
}
- ret = smu_init_display(smu);
+ ret = smu_init_display_count(smu, 0);
if (ret)
return ret;
@@ -1470,6 +1470,17 @@ int smu_force_performance_level(struct smu_context *smu,
enum amd_dpm_forced_lev
return ret;
}
+int smu_set_display_count(struct smu_context *smu, uint32_t count)
+{
+ int ret = 0;
+
+ mutex_lock(>mutex);
+ ret = smu_init_display_count(smu, count);
+ mutex_unlock(>mutex);
+
+ return ret;
+}
+
const struct amd_ip_funcs smu_ip_funcs = {
.name = "smu",
.early_init = smu_early_init,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 58861c0340b9..267c4f6eb317 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -638,7 +638,7 @@ struct smu_funcs
int (*send_smc_msg)(struct smu_context *smu, uint16_t msg);
int (*send_smc_msg_with_param)(struct smu_context *smu, uint16_t msg,
uint32_t param);
int (*read_smc_arg)(struct smu_context *smu, uint32_t *arg);
- int (*init_display)(struct smu_context *smu);
+ int (*init_display_count)(struct smu_context *smu, uint32_t count);
int (*set_allowed_mask)(struct smu_context *smu);
int (*get_enabled_mask)(struct smu_context *smu, uint32_t
*feature_mask, uint32_t num);
int (*update_feature_enable_state)(struct smu_context *smu, uint32_t
feature_id, bool enabled);
@@ -752,8 +752,8 @@ struct smu_funcs
((smu)->funcs->read_smc_arg? (smu)->funcs->read_smc_arg((smu), (arg)) :
0)
#define smu_alloc_dpm_context(smu) \
((smu)->ppt_funcs->alloc_dpm_context ?
(smu)->ppt_funcs->alloc_dpm_context((smu)) : 0)
-#define smu_init_display(smu) \
- ((smu)->funcs->init_display ? (smu)->funcs->init_display((smu)) : 0)
+#define smu_init_display_count(smu, count) \
+ ((smu)->funcs->init_display_count ?
(smu)->funcs->init_display_count((smu), (count)) : 0)
#define smu_feature_set_allowed_mask(smu) \
((smu)->funcs->set_allowed_mask? (smu)->funcs->set_allowed_mask((smu))
: 0)
#define smu_feature_get_enabled_mask(smu, mask, num) \
@@ -947,4 +947,6 @@ int smu_set_hard_freq_range(struct smu_context *smu, enum
smu_clk_type clk_type,
uint32_t min, uint32_t max);
enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu);
int smu_force_performance_level(struct smu_context *smu, enum
amd_dpm_forced_level level);
+int smu_set_display_count(struct smu_context *smu, uint32_t count);
+
#endif
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 1b5d4084eedc..39b4c160afc4 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -765,13 +765,13 @@ static int smu_v11_0_set_tool_table_location(struct
smu_context *smu)
return ret;
}
-static int smu_v11_0_init_display(struct smu_context *smu)
+static int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t
count)
{
int ret = 0;
if (!smu->pm_enabled)
return ret;
- ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0);
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, count);
return ret;
}
@@ -1685,7 +1685,7 @@ static const struct smu_funcs smu_v11_0_funcs = {
.write_watermarks_table = smu_v11_0_write_watermarks_table,
.set_min_dcef_deep_sleep = smu_v11_0_set_min_dcef_deep_sleep,
.set_tool_table_location = smu_v11_0_set_tool_table_location,
- .init_display = smu_v11_0_init_display,
+ .init_display_count = smu_v11_0_init_display_count,
.set_allowed_mask = smu_v11_0_set_allowed_mask,
.get_enabled_mask = smu_v11_0_get_enabled_mask,
.system_features_control = smu_v11_0_system_features_control,
--
2.20.1
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[PATCH 275/459] drm/amd/powerplay: remove smu callback funciton get_mclk(get_sclk)
From: Kevin Wang
remove smu callback: get_mclk, get_sclk.
because the function smu_get_dpm_freq_range has the same function.
Signed-off-by: Kevin Wang
Reviewed-by: Evan Quan
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 32 +--
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 34 ++--
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 6 --
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 85 ---
4 files changed, 54 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
index b5397135c417..f54a1ef53276 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c
@@ -907,18 +907,38 @@ amdgpu_get_vce_clock_state(void *handle, u32 idx)
int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low)
{
- if (is_support_sw_smu(adev))
- return smu_get_sclk(>smu, low);
- else
+ uint32_t clk_freq;
+ int ret = 0;
+ if (is_support_sw_smu(adev)) {
+ ret = smu_get_dpm_freq_range(>smu, SMU_GFXCLK,
+low ? _freq : NULL,
+!low ? _freq : NULL);
+ if (ret)
+ return 0;
+ return clk_freq * 100;
+
+ }
+ else {
return
(adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (low));
+ }
}
int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low)
{
- if (is_support_sw_smu(adev))
- return smu_get_mclk(>smu, low);
- else
+ uint32_t clk_freq;
+ int ret = 0;
+ if (is_support_sw_smu(adev)) {
+ ret = smu_get_dpm_freq_range(>smu, SMU_UCLK,
+low ? _freq : NULL,
+!low ? _freq : NULL);
+ if (ret)
+ return 0;
+ return clk_freq * 100;
+
+ }
+ else {
return
(adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (low));
+ }
}
int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t
block_type, bool gate)
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index ad8f6dd7713d..35578be95da6 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -135,30 +135,52 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum
smu_clk_type clk_type,
if (!min && !max)
return -EINVAL;
+ switch (clk_type) {
+ case SMU_UCLK:
+ if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
+ pr_warn("uclk dpm is not enabled\n");
+ return 0;
+ }
+ break;
+ case SMU_GFXCLK:
+ if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
+ pr_warn("gfxclk dpm is not enabled\n");
+ return 0;
+ }
+ break;
+ default:
+ break;
+ }
+
+ mutex_lock(>mutex);
clk_id = smu_clk_get_index(smu, clk_type);
- if (clk_id < 0)
- return clk_id;
+ if (clk_id < 0) {
+ ret = -EINVAL;
+ goto failed;
+ }
param = (clk_id & 0x) << 16;
if (max) {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
param);
if (ret)
- return ret;
+ goto failed;
ret = smu_read_smc_arg(smu, max);
if (ret)
- return ret;
+ goto failed;
}
if (min) {
ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq,
param);
if (ret)
- return ret;
+ goto failed;
ret = smu_read_smc_arg(smu, min);
if (ret)
- return ret;
+ goto failed;
}
+failed:
+ mutex_unlock(>mutex);
return ret;
}
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 5e49b38ddd0d..58861c0340b9 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -679,8 +679,6 @@ struct smu_funcs
int (*update_od8_settings)(struct smu_context *smu,
uint32_t index,
uint32_t value);
- uint32_t (*get_sclk)(struct smu_context *smu, bool low);
- uint32_t (*get_mclk)(struct smu_context *smu, bool low);
int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed);
uint32_t
[PATCH 246/459] drm/amd/powerplay: remove upload_dpm_level function for vega20
From: Kevin Wang
the function upload_dpm_level is an internal function,
so remove public interface.
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 5 ++---
2 files changed, 2 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index e05f4dd96f4b..0275c4b96c9a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -576,8 +576,6 @@ struct pptable_funcs {
int (*notify_smc_dispaly_config)(struct smu_context *smu);
int (*force_dpm_limit_value)(struct smu_context *smu, bool highest);
int (*unforce_dpm_levels)(struct smu_context *smu);
- int (*upload_dpm_level)(struct smu_context *smu, bool max,
- uint32_t feature_mask);
int (*get_profiling_clk_mask)(struct smu_context *smu,
enum amd_dpm_forced_level level,
uint32_t *sclk_mask,
@@ -814,8 +812,6 @@ struct smu_funcs
((smu)->ppt_funcs->force_dpm_limit_value ?
(smu)->ppt_funcs->force_dpm_limit_value((smu), (highest)) : 0)
#define smu_unforce_dpm_levels(smu) \
((smu)->ppt_funcs->unforce_dpm_levels ?
(smu)->ppt_funcs->unforce_dpm_levels((smu)) : 0)
-#define smu_upload_dpm_level(smu, max, feature_mask) \
- ((smu)->ppt_funcs->upload_dpm_level ?
(smu)->ppt_funcs->upload_dpm_level((smu), (max), (feature_mask)) : 0)
#define smu_get_profiling_clk_mask(smu, level, sclk_mask, mclk_mask, soc_mask)
\
((smu)->ppt_funcs->get_profiling_clk_mask ?
(smu)->ppt_funcs->get_profiling_clk_mask((smu), (level), (sclk_mask),
(mclk_mask), (soc_mask)) : 0)
#define smu_set_cpu_power_state(smu) \
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 94374827a83b..2f33fec4da98 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -2329,13 +2329,13 @@ static int vega20_unforce_dpm_levels(struct smu_context
*smu)
dpm_table->soc_table.dpm_state.soft_max_level =
dpm_table->soc_table.dpm_levels[soft_max_level].value;
- ret = smu_upload_dpm_level(smu, false, 0x);
+ ret = vega20_upload_dpm_level(smu, false, 0x);
if (ret) {
pr_err("Failed to upload DPM Bootup Levels!");
return ret;
}
- ret = smu_upload_dpm_level(smu, true, 0x);
+ ret = vega20_upload_dpm_level(smu, true, 0x);
if (ret) {
pr_err("Failed to upload DPM Max Levels!");
return ret;
@@ -3142,7 +3142,6 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.notify_smc_dispaly_config = vega20_notify_smc_dispaly_config,
.force_dpm_limit_value = vega20_force_dpm_limit_value,
.unforce_dpm_levels = vega20_unforce_dpm_levels,
- .upload_dpm_level = vega20_upload_dpm_level,
.get_profiling_clk_mask = vega20_get_profiling_clk_mask,
.set_ppfeature_status = vega20_set_ppfeature_status,
.get_ppfeature_status = vega20_get_ppfeature_status,
--
2.20.1
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[PATCH 265/459] drm/amd/powerplay: enable ac/dc feature on navi10
From: Kenneth Feng enable ac/dc feature on navi10. currently we don't have the case to verify it. Signed-off-by: Kenneth Feng Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index c312eadcf3e0..2a85ef476a1d 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -329,7 +329,8 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT) | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) - | FEATURE_MASK(FEATURE_FW_DSTATE_BIT); + | FEATURE_MASK(FEATURE_FW_DSTATE_BIT) + | FEATURE_MASK(FEATURE_ACDC_BIT); if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 250/459] drm/amd/powerplay: add function get_profiling_clk_mask for navi10
From: Kevin Wang
add callback function get_profiling_clk_mask for navi10 asic
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 42 ++
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 55d67cd922f3..1d42d6866fc9 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1030,6 +1030,47 @@ static int navi10_set_power_profile_mode(struct
smu_context *smu, long *input, u
return ret;
}
+static int navi10_get_profiling_clk_mask(struct smu_context *smu,
+enum amd_dpm_forced_level level,
+uint32_t *sclk_mask,
+uint32_t *mclk_mask,
+uint32_t *soc_mask)
+{
+ int ret = 0;
+ uint32_t level_count = 0;
+
+ if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
+ if (sclk_mask)
+ *sclk_mask = 0;
+ } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
+ if (mclk_mask)
+ *mclk_mask = 0;
+ } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
+ if(sclk_mask) {
+ ret = smu_get_dpm_level_count(smu, SMU_SCLK,
_count);
+ if (ret)
+ return ret;
+ *sclk_mask = level_count - 1;
+ }
+
+ if(mclk_mask) {
+ ret = smu_get_dpm_level_count(smu, SMU_MCLK,
_count);
+ if (ret)
+ return ret;
+ *sclk_mask = level_count - 1;
+ }
+
+ if(soc_mask) {
+ ret = smu_get_dpm_level_count(smu, SMU_SOCCLK,
_count);
+ if (ret)
+ return ret;
+ *sclk_mask = level_count - 1;
+ }
+ }
+
+ return ret;
+}
+
static const struct pptable_funcs navi10_ppt_funcs = {
.tables_init = navi10_tables_init,
.alloc_dpm_context = navi10_allocate_dpm_context,
@@ -1061,6 +1102,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.get_fan_speed_percent = navi10_get_fan_speed_percent,
.get_power_profile_mode = navi10_get_power_profile_mode,
.set_power_profile_mode = navi10_set_power_profile_mode,
+ .get_profiling_clk_mask = navi10_get_profiling_clk_mask,
};
void navi10_set_ppt_funcs(struct smu_context *smu)
--
2.20.1
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[PATCH 288/459] drm/amdgpu/VCN2.0 remove unused Macro and declaration
From: Leo Liu Just for cleanup Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Reviewed-by: James Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index dcb148994ed7..5782f79dbe04 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -45,7 +45,6 @@ #define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET0x5a6 #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2 -#define mmUVD_GPCOM_SYS_CMD_INTERNAL_OFFSET0x1bF #define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET0x1bfff #define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET 0x4029 @@ -67,7 +66,6 @@ #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000 -static int vcn_v2_0_stop(struct amdgpu_device *adev); static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev); static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev); -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 268/459] drm/amdgpu/gfx10: remove static GDS, GWS and OA allcoation
From: Hawking Zhang
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 57 +-
1 file changed, 11 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index f6ea69a42306..9595065e2d3e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1232,25 +1232,6 @@ static int gfx_v10_0_sw_init(void *handle)
if (r)
return r;
- /* reserve GDS, GWS and OA resource for gfx */
- r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
- PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
- >gds.gds_gfx_bo, NULL, NULL);
- if (r)
- return r;
-
- r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
- PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
- >gds.gws_gfx_bo, NULL, NULL);
- if (r)
- return r;
-
- r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
- PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
- >gds.oa_gfx_bo, NULL, NULL);
- if (r)
- return r;
-
/* allocate visible FB for rlc auto-loading fw */
if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
@@ -1291,10 +1272,6 @@ static int gfx_v10_0_sw_fini(void *handle)
int i;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
- amdgpu_bo_free_kernel(>gds.oa_gfx_bo, NULL, NULL);
- amdgpu_bo_free_kernel(>gds.gws_gfx_bo, NULL, NULL);
- amdgpu_bo_free_kernel(>gds.gds_gfx_bo, NULL, NULL);
-
for (i = 0; i < adev->gfx.num_gfx_rings; i++)
amdgpu_ring_fini(>gfx.gfx_ring[i]);
for (i = 0; i < adev->gfx.num_compute_rings; i++)
@@ -4526,7 +4503,7 @@ static void gfx_v10_0_ring_emit_de_meta(struct
amdgpu_ring *ring, bool resume)
int cnt;
csa_addr = amdgpu_csa_vaddr(ring->adev);
- gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.mem.total_size,
+ gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
PAGE_SIZE);
de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
@@ -5119,29 +5096,17 @@ static void gfx_v10_0_set_rlc_funcs(struct
amdgpu_device *adev)
static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
{
/* init asic gds info */
- adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
- adev->gds.gws.total_size = 64;
- adev->gds.oa.total_size = 16;
-
- if (adev->gds.mem.total_size == 64 * 1024) {
- adev->gds.mem.gfx_partition_size = 4096;
- adev->gds.mem.cs_partition_size = 4096;
-
- adev->gds.gws.gfx_partition_size = 4;
- adev->gds.gws.cs_partition_size = 4;
-
- adev->gds.oa.gfx_partition_size = 4;
- adev->gds.oa.cs_partition_size = 1;
- } else {
- adev->gds.mem.gfx_partition_size = 1024;
- adev->gds.mem.cs_partition_size = 1024;
-
- adev->gds.gws.gfx_partition_size = 16;
- adev->gds.gws.cs_partition_size = 16;
-
- adev->gds.oa.gfx_partition_size = 4;
- adev->gds.oa.cs_partition_size = 4;
+ switch (adev->asic_type) {
+ case CHIP_NAVI10:
+ adev->gds.gds_size = 0x1;
+ break;
+ default:
+ adev->gds.gds_size = 0x1;
+ break;
}
+
+ adev->gds.gws_size = 64;
+ adev->gds.oa_size = 16;
}
static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device
*adev,
--
2.20.1
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[PATCH 271/459] drm/amd/powerplay: move get_thermal_temperature_range to ppt funcs
From: Hawking Zhang
The thermal policy could be ASIC specific ones and depends on structures
in pptable. As a result, get_thermal_temperature_range should be implemented
as ppt funcs instead of smu funcs
Signed-off-by: Hawking Zhang
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 14 +++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 90 +++
drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 47 +-
3 files changed, 70 insertions(+), 81 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 0fd3d89386be..f89971992e6f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -26,6 +26,10 @@
#include "kgd_pp_interface.h"
#include "dm_pp_interface.h"
+#define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
+#define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
+#define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
+
struct smu_hw_power_state {
unsigned int magic;
};
@@ -106,6 +110,13 @@ struct smu_state_software_algorithm_block {
struct smu_temperature_range {
int min;
int max;
+ int edge_emergency_max;
+ int hotspot_min;
+ int hotspot_crit_max;
+ int hotspot_emergency_max;
+ int mem_min;
+ int mem_crit_max;
+ int mem_emergency_max;
};
struct smu_state_validation_block {
@@ -597,6 +608,7 @@ struct pptable_funcs {
int (*get_current_clk_freq_by_table)(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *value);
+ int (*get_thermal_temperature_range)(struct smu_context *smu, struct
smu_temperature_range *range);
};
struct smu_funcs
@@ -881,6 +893,8 @@ struct smu_funcs
((smu)->ppt_funcs->set_watermarks_table ?
(smu)->ppt_funcs->set_watermarks_table((smu), (tab), (clock_ranges)) : 0)
#define smu_get_current_clk_freq_by_table(smu, clk_type, value) \
((smu)->ppt_funcs->get_current_clk_freq_by_table ?
(smu)->ppt_funcs->get_current_clk_freq_by_table((smu), (clk_type), (value)) : 0)
+#define smu_get_thermal_temperature_range(smu, range) \
+ ((smu)->ppt_funcs->get_thermal_temperature_range?
(smu)->ppt_funcs->get_thermal_temperature_range((smu), (range)) : 0)
extern int smu_get_atom_data_table(struct smu_context *smu, uint32_t table,
uint16_t *size, uint8_t *frev, uint8_t *crev,
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 175463d9aa2d..c6dc2a6d8093 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -31,7 +31,6 @@
#include "atom.h"
#include "vega20_ppt.h"
#include "navi10_ppt.h"
-#include "pp_thermal.h"
#include "asic_reg/thm/thm_11_0_2_offset.h"
#include "asic_reg/thm/thm_11_0_2_sh_mask.h"
@@ -44,10 +43,6 @@
MODULE_FIRMWARE("amdgpu/vega20_smc.bin");
MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
-#define SMU11_THERMAL_MINIMUM_ALERT_TEMP 0
-#define SMU11_THERMAL_MAXIMUM_ALERT_TEMP 255
-
-#define SMU11_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
#define SMU11_VOLTAGE_SCALE 4
static int smu_v11_0_send_msg_without_waiting(struct smu_context *smu,
@@ -1112,38 +1107,19 @@ static int smu_v11_0_get_current_clk_freq(struct
smu_context *smu,
return ret;
}
-static int smu_v11_0_get_thermal_range(struct smu_context *smu,
- struct PP_TemperatureRange *range)
-{
- PPTable_t *pptable = smu->smu_table.driver_pptable;
- memcpy(range, [0], sizeof(struct
PP_TemperatureRange));
-
- range->max = pptable->TedgeLimit *
- PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
- range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
- PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
- range->hotspot_crit_max = pptable->ThotspotLimit *
- PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
- range->hotspot_emergency_max = (pptable->ThotspotLimit +
CTF_OFFSET_HOTSPOT) *
- PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
- range->mem_crit_max = pptable->ThbmLimit *
- PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
- range->mem_emergency_max = (pptable->ThbmLimit + CTF_OFFSET_HBM)*
- PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-
- return 0;
-}
-
static int smu_v11_0_set_thermal_range(struct smu_context *smu,
- struct PP_TemperatureRange *range)
+ struct smu_temperature_range *range)
{
struct amdgpu_device *adev = smu->adev;
- int low = SMU11_THERMAL_MINIMUM_ALERT_TEMP *
- PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
- int high = SMU11_THERMAL_MAXIMUM_ALERT_TEMP *
- PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ int low = SMU_THERMAL_MINIMUM_ALERT_TEMP *
+
[PATCH 266/459] drm/amd/powerplay: enable uclk dpm default on navi10
From: Kevin Wang
enable uclk (mclk) dpm by default on navi10
Signed-off-by: Kevin Wang
Reviewed-by: Kenneth Feng
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 2a85ef476a1d..d20d498af675 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -314,6 +314,9 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)
| FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
| FEATURE_MASK(FEATURE_DPM_LINK_BIT)
+ | FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
+ | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
+ | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT)
| FEATURE_MASK(FEATURE_GFX_ULV_BIT)
| FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
| FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
@@ -332,11 +335,6 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
| FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
| FEATURE_MASK(FEATURE_ACDC_BIT);
- if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
- *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
- | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
- | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
-
if (adev->pm.pp_feature & PP_GFXOFF_MASK)
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_SS_BIT)
| FEATURE_MASK(FEATURE_GFXOFF_BIT);
@@ -350,7 +348,9 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
if ((adev->asic_type == CHIP_NAVI10) &&
(adev->rev_id == 0)) {
*(uint64_t *)feature_mask &=
- ~FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
+ ~(FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
+ |
FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
+ |
FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT));
*(uint64_t *)feature_mask &=
~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
}
--
2.20.1
___
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[PATCH 290/459] drm/amdgpu/VCN2.0: add DPG mode start and stop (v2)
From: Leo Liu
This is for using SRAM directly
v2: rebase (Alex)
Signed-off-by: Leo Liu
Reviewed-by: Alex Deucher
Reviewed-by: James Zhu
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 299 +-
1 file changed, 296 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 5782f79dbe04..3068b0870c8f 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -66,6 +66,11 @@
#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000
+#define mmUVD_RBC_XX_IB_REG_CHECK 0x026b
+#define mmUVD_RBC_XX_IB_REG_CHECK_BASE_IDX 1
+#define mmUVD_REG_XX_MASK 0x026c
+#define mmUVD_REG_XX_MASK_BASE_IDX 1
+
static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device *adev);
@@ -257,7 +262,8 @@ static int vcn_v2_0_hw_init(void *handle)
done:
if (!r)
- DRM_INFO("VCN decode and encode initialized successfully.\n");
+ DRM_INFO("VCN decode and encode initialized successfully(under
%s).\n",
+ (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG
Mode":"SPG Mode");
return r;
}
@@ -275,8 +281,9 @@ static int vcn_v2_0_hw_fini(void *handle)
struct amdgpu_ring *ring = >vcn.ring_dec;
int i;
- if (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
- RREG32_SOC15(VCN, 0, mmUVD_STATUS))
+ if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
+ (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
+ RREG32_SOC15(VCN, 0, mmUVD_STATUS)))
vcn_v2_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
ring->sched.ready = false;
@@ -389,6 +396,77 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev)
WREG32_SOC15(UVD, 0, mmJPEG_DEC_GFX10_ADDR_CONFIG,
adev->gfx.config.gb_addr_config);
}
+static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool
indirect)
+{
+ uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
+ uint32_t offset;
+
+ /* cache window 0: fw */
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
+ offset = 0;
+ } else {
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+ lower_32_bits(adev->vcn.gpu_addr), 0, indirect);
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+ upper_32_bits(adev->vcn.gpu_addr), 0, indirect);
+ offset = size;
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
+ AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
+ }
+
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
+
+ /* cache window 1: stack */
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+ lower_32_bits(adev->vcn.gpu_addr + offset), 0, indirect);
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
+ upper_32_bits(adev->vcn.gpu_addr + offset), 0, indirect);
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0,
indirect);
+
+ /* cache window 2: context */
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+ lower_32_bits(adev->vcn.gpu_addr + offset +
AMDGPU_VCN_STACK_SIZE), 0, indirect);
+ WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0(
+ UVD, 0,
[PATCH 292/459] drm/amdgpu: enable VCN2.0 DPG mode
From: Leo Liu It will be the default for VCN2.x family Signed-off-by: Leo Liu Reviewed-by: Alex Deucher Reviewed-by: James Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 70d844d06e20..3cfc15be6ff8 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -505,7 +505,8 @@ static int nv_common_early_init(void *handle) AMD_CG_SUPPORT_VCN_MGCG | AMD_CG_SUPPORT_BIF_MGCG | AMD_CG_SUPPORT_BIF_LS; - adev->pg_flags = AMD_PG_SUPPORT_VCN; + adev->pg_flags = AMD_PG_SUPPORT_VCN | + AMD_PG_SUPPORT_VCN_DPG; adev->external_rev_id = adev->rev_id + 0x1; break; default: -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH] drm/amd/amdgpu: cast mem->num_pages to 64-bits when shifting
On 2019-06-17 3:28 p.m., Christian König wrote:
> Am 17.06.19 um 21:15 schrieb Kuehling, Felix:
>> Looks good to me. One cosmetic comment inline. With that fixed this
>> patch is Reviewed-by: Felix Kuehling
>>
>> On 2019-06-14 12:51 p.m., StDenis, Tom wrote:
>>> On 32-bit hosts mem->num_pages is 32-bits and can overflow
>>> when shifted. Add a cast to avoid this.
>>>
>>> Signed-off-by: Tom St Denis
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 8 +---
>>> 1 file changed, 5 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
>>> index c963ad86072e..31895d3c33de 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
>>> @@ -279,14 +279,16 @@ static int amdgpu_vram_mgr_new(struct
>>> ttm_mem_type_manager *man,
>>> uint64_t vis_usage = 0;
>>> unsigned i;
>>> int r;
>>> + uint64_t mem_bytes;
>> Christian likes the "upside-down christmas tree" to help readability of
>> local variable declarations.
>
> Ah, yeah. Thanks for the note.
>
> I actually don't care about that much, but I always get rejects from
> upstream subsystem maintainers if I don't do this.
>
> It's most likely not even documented somewhere,
Right. The fact that I even noticed it probably means that I have a mild
case of OCD myself. If it was a strict requirement, it should be caught
by checkpatch.pl.
Cheers,
Felix
> Christian.
>
>>
>>
>>> lpfn = place->lpfn;
>>> if (!lpfn)
>>> lpfn = man->size;
>>> /* bail out quickly if there's likely not enough VRAM for
>>> this BO */
>>> - if (atomic64_add_return(mem->num_pages << PAGE_SHIFT,
>>> >usage) > adev->gmc.mc_vram_size) {
>>> - atomic64_sub(mem->num_pages << PAGE_SHIFT, >usage);
>>> + mem_bytes = (u64)mem->num_pages << PAGE_SHIFT;
>>> + if (atomic64_add_return(mem_bytes, >usage) >
>>> adev->gmc.mc_vram_size) {
>>> + atomic64_sub(mem_bytes, >usage);
>>> mem->mm_node = NULL;
>>> return 0;
>>> }
>>> @@ -308,7 +310,7 @@ static int amdgpu_vram_mgr_new(struct
>>> ttm_mem_type_manager *man,
>>> nodes = kvmalloc_array((uint32_t)num_nodes, sizeof(*nodes),
>>> GFP_KERNEL | __GFP_ZERO);
>>> if (!nodes) {
>>> - atomic64_sub(mem->num_pages << PAGE_SHIFT, >usage);
>>> + atomic64_sub(mem_bytes, >usage);
>>> return -ENOMEM;
>>> }
>> ___
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
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[PATCH 269/459] drm/amd/powerplay: move function get_metrics_table to vega20_ppt
From: Kevin Wang
the SmuMetrics_t table is asic related data structure.
so move vega20_ppt file to implement.
Signed-off-by: Kevin Wang
Signed-off-by: Alex Deucher
---
.../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 6 +--
drivers/gpu/drm/amd/powerplay/navi10_ppt.c| 2 +-
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 36 +++---
drivers/gpu/drm/amd/powerplay/vega20_ppt.c| 37 ---
4 files changed, 42 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index 4706eaf39cf7..0fd3d89386be 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -406,6 +406,8 @@ struct smu_table_context
void*power_play_table;
uint32_tpower_play_table_size;
void*hardcode_pptable;
+ unsigned long metrics_time;
+ void*metrics_table;
void*max_sustainable_clocks;
struct smu_bios_boot_up_values boot_values;
@@ -524,8 +526,6 @@ struct smu_context
uint32_t smc_if_version;
- unsigned long metrics_time;
- void *metrics_table;
};
struct pptable_funcs {
@@ -589,7 +589,7 @@ struct pptable_funcs {
int (*set_ppfeature_status)(struct smu_context *smu, uint64_t
ppfeatures);
int (*get_ppfeature_status)(struct smu_context *smu, char *buf);
bool (*is_dpm_running)(struct smu_context *smu);
- void (*tables_init)(struct smu_context *smu, struct smu_table *tables);
+ int (*tables_init)(struct smu_context *smu, struct smu_table *tables);
int (*set_thermal_fan_table)(struct smu_context *smu);
int (*get_fan_speed_percent)(struct smu_context *smu, uint32_t *speed);
int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index d20d498af675..130719663566 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -479,7 +479,7 @@ static int navi10_store_powerplay_table(struct smu_context
*smu)
return 0;
}
-static void navi10_tables_init(struct smu_context *smu, struct smu_table
*tables)
+static int navi10_tables_init(struct smu_context *smu, struct smu_table
*tables)
{
SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 1896ce1ece6b..538f52ab4b72 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -407,7 +407,9 @@ static int smu_v11_0_init_smc_tables(struct smu_context
*smu)
smu_table->tables = tables;
- smu_tables_init(smu, tables);
+ ret = smu_tables_init(smu, tables);
+ if (ret)
+ return ret;
ret = smu_v11_0_init_dpm_context(smu);
if (ret)
@@ -425,8 +427,11 @@ static int smu_v11_0_fini_smc_tables(struct smu_context
*smu)
return -EINVAL;
kfree(smu_table->tables);
+ kfree(smu_table->metrics_table);
smu_table->tables = NULL;
smu_table->table_count = 0;
+ smu_table->metrics_table = NULL;
+ smu_table->metrics_time = 0;
ret = smu_v11_0_fini_dpm_context(smu);
if (ret)
@@ -449,13 +454,6 @@ static int smu_v11_0_init_power(struct smu_context *smu)
return -ENOMEM;
smu_power->power_context_size = sizeof(struct smu_11_0_dpm_context);
- smu->metrics_time = 0;
- smu->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
- if (!smu->metrics_table) {
- kfree(smu_power->power_context);
- return -ENOMEM;
- }
-
return 0;
}
@@ -468,9 +466,7 @@ static int smu_v11_0_fini_power(struct smu_context *smu)
if (!smu_power->power_context || smu_power->power_context_size == 0)
return -EINVAL;
- kfree(smu->metrics_table);
kfree(smu_power->power_context);
- smu->metrics_table = NULL;
smu_power->power_context = NULL;
smu_power->power_context_size = 0;
@@ -1227,26 +1223,6 @@ static int smu_v11_0_start_thermal_control(struct
smu_context *smu)
return ret;
}
-static int smu_v11_0_get_metrics_table(struct smu_context *smu,
- SmuMetrics_t *metrics_table)
-{
- int ret = 0;
-
- if (!smu->metrics_time || time_after(jiffies, smu->metrics_time + HZ /
1000)) {
- ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS,
- (void *)metrics_table, false);
- if (ret) {
- pr_info("Failed to export SMU metrics
[PATCH 264/459] drm/amd/powerplay: enable gfxclk ds, dcefclk ds and fw dstate on navi10
From: Kenneth Feng on navi10, by default the below four features are enabled. gfxclk deep sleep: enabled and verified fw dstate: enabled and then soc ulv is verified dcefclk deep sleep: enabled and verified. notice that on different boards, due to the minimum dcefclk deep sleep setting in VBIOS, we may not see dcefclk deep sleep kicking in. Signed-off-by: Kenneth Feng Reviewed-by: Huang Rui Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c index dece57fc751e..c312eadcf3e0 100644 --- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c @@ -326,7 +326,10 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT) | FEATURE_MASK(FEATURE_MMHUB_PG_BIT) | FEATURE_MASK(FEATURE_ATHUB_PG_BIT) - | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); + | FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT) + | FEATURE_MASK(FEATURE_DS_GFXCLK_BIT) + | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT) + | FEATURE_MASK(FEATURE_FW_DSTATE_BIT); if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 274/459] drm/amd/powerplay: remove smu mutex lock in smu_hw_init
From: Kevin Wang the smu mutex lock is unnecessary in smu hw init. Signed-off-by: Kevin Wang Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index 421e1df79ae5..ad8f6dd7713d 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -981,8 +981,6 @@ static int smu_hw_init(void *handle) } } - mutex_lock(>mutex); - ret = smu_feature_init_dpm(smu); if (ret) goto failed; @@ -1011,8 +1009,6 @@ static int smu_hw_init(void *handle) if (ret) goto failed; - mutex_unlock(>mutex); - if (!smu->pm_enabled) adev->pm.dpm_enabled = false; else -- 2.20.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH 237/459] drm/amd/powerplay: add function display_configuration_changed for navi10
From: Kevin Wang
1.add callback function to support navi10 asic.
2.Remove unnecessary logical code.
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 25 ++
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 --
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 10 +
3 files changed, 40 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 569f788ce2f6..7e7e0a604aef 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -671,6 +671,30 @@ static int navi10_pre_display_config_changed(struct
smu_context *smu)
return ret;
}
+static int navi10_display_config_changed(struct smu_context *smu)
+{
+ int ret = 0;
+
+ if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+ !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+ ret = smu_write_watermarks_table(smu);
+ if (ret)
+ return ret;
+
+ smu->watermarks_bitmap |= WATERMARKS_LOADED;
+ }
+
+ if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+ smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
+ smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+ ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
+
smu->display_config->num_display);
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
static const struct pptable_funcs navi10_ppt_funcs = {
.tables_init = navi10_tables_init,
.alloc_dpm_context = navi10_allocate_dpm_context,
@@ -691,6 +715,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.populate_umd_state_clk = navi10_populate_umd_state_clk,
.get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
.pre_display_config_changed = navi10_pre_display_config_changed,
+ .display_config_changed = navi10_display_config_changed,
};
void navi10_set_ppt_funcs(struct smu_context *smu)
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index fc5df68df694..957fb63b8d5e 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -714,9 +714,21 @@ static int smu_v11_0_write_pptable(struct smu_context *smu)
static int smu_v11_0_write_watermarks_table(struct smu_context *smu)
{
- return smu_update_table(smu, SMU_TABLE_WATERMARKS,
-
smu->smu_table.tables[SMU_TABLE_WATERMARKS].cpu_addr,
+ int ret = 0;
+ struct smu_table_context *smu_table = >smu_table;
+ struct smu_table *table = NULL;
+
+ table = _table->tables[SMU_TABLE_WATERMARKS];
+ if (!table)
+ return -EINVAL;
+
+ if (!table->cpu_addr)
+ return -EINVAL;
+
+ ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, table->cpu_addr,
true);
+
+ return ret;
}
static int smu_v11_0_set_deep_sleep_dcefclk(struct smu_context *smu, uint32_t
clk)
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 1f0f4d85fe23..55d1649d6111 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1992,17 +1992,9 @@ static int vega20_display_config_changed(struct
smu_context *smu)
{
int ret = 0;
- if (!smu->funcs)
- return -EINVAL;
-
- if (!smu->smu_dpm.dpm_context ||
- !smu->smu_table.tables ||
- !smu->smu_table.tables[TABLE_WATERMARKS].cpu_addr)
- return -EINVAL;
-
if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
!(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
- ret = smu->funcs->write_watermarks_table(smu);
+ ret = smu_write_watermarks_table(smu);
if (ret) {
pr_err("Failed to update WMTABLE!");
return ret;
--
2.20.1
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[PATCH 291/459] drm/amdgpu/VCN2.0: add DPG pause mode
From: Leo Liu
Pause the DPG when not doing decode
Signed-off-by: Leo Liu
Reviewed-by: Alex Deucher
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 70 +++
1 file changed, 70 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index 3068b0870c8f..bef20704e2b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -77,6 +77,8 @@ static void vcn_v2_0_set_jpeg_ring_funcs(struct amdgpu_device
*adev);
static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
static int vcn_v2_0_set_powergating_state(void *handle,
enum amd_powergating_state state);
+static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
+ struct dpg_pause_state *new_state);
/**
* vcn_v2_0_early_init - set function pointers
@@ -192,6 +194,8 @@ static int vcn_v2_0_sw_init(void *handle)
if (r)
return r;
+ adev->vcn.pause_dpg_mode = vcn_v2_0_pause_dpg_mode;
+
adev->vcn.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
adev->vcn.external.jpeg_pitch = SOC15_REG_OFFSET(UVD, 0,
mmUVD_JPEG_PITCH);
@@ -1289,6 +1293,68 @@ static int vcn_v2_0_stop(struct amdgpu_device *adev)
return 0;
}
+static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
+ struct dpg_pause_state *new_state)
+{
+ struct amdgpu_ring *ring;
+ uint32_t reg_data = 0;
+ int ret_code;
+
+ /* pause/unpause if state is changed */
+ if (adev->vcn.pause_state.fw_based != new_state->fw_based) {
+ DRM_DEBUG("dpg pause state changed %d -> %d",
+ adev->vcn.pause_state.fw_based, new_state->fw_based);
+ reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
+ (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
+
+ if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
+ ret_code = 0;
+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 0x1,
+ UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,
ret_code);
+
+ if (!ret_code) {
+ /* pause DPG */
+ reg_data |=
UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
+ WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
+
+ /* wait for ACK */
+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
+ UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
+
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, ret_code);
+
+ /* Restore */
+ ring = >vcn.ring_enc[0];
+ WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO,
ring->gpu_addr);
+ WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI,
upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE,
ring->ring_size / 4);
+ WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR,
lower_32_bits(ring->wptr));
+ WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
lower_32_bits(ring->wptr));
+
+ ring = >vcn.ring_enc[1];
+ WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2,
ring->gpu_addr);
+ WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2,
upper_32_bits(ring->gpu_addr));
+ WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2,
ring->ring_size / 4);
+ WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2,
lower_32_bits(ring->wptr));
+ WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
lower_32_bits(ring->wptr));
+
+ WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
+ RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2)
& 0x7FFF);
+
+ SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
+ UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
+
UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code);
+ }
+ } else {
+ /* unpause dpg, no need to wait */
+ reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
+ WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
+ }
+ adev->vcn.pause_state.fw_based = new_state->fw_based;
+ }
+
+ return 0;
+}
+
static bool vcn_v2_0_is_idle(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1367,6 +1433,10 @@ static void vcn_v2_0_dec_ring_set_wptr(struct
amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
+ if
[PATCH 240/459] drm/amd/powerplay: add function get_gpu_power for navi10
From: Kevin Wang
add callback function get_gpu_power for navi10 asic
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 22b6ae93137c..e21a1eaee8b9 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -749,6 +749,24 @@ static int navi10_unforce_dpm_levels(struct smu_context
*smu) {
return ret;
}
+static int navi10_get_gpu_power(struct smu_context *smu, uint32_t *value)
+{
+ int ret = 0;
+ SmuMetrics_t metrics;
+
+ if (!value)
+ return -EINVAL;
+
+ ret = smu_update_table(smu, SMU_TABLE_SMU_METRICS, (void *),
+ false);
+ if (ret)
+ return ret;
+
+ *value = metrics.CurrSocketPower << 8;
+
+ return 0;
+}
+
static const struct pptable_funcs navi10_ppt_funcs = {
.tables_init = navi10_tables_init,
.alloc_dpm_context = navi10_allocate_dpm_context,
@@ -772,6 +790,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.display_config_changed = navi10_display_config_changed,
.force_dpm_limit_value = navi10_force_dpm_limit_value,
.unforce_dpm_levels = navi10_unforce_dpm_levels,
+ .get_gpu_power = navi10_get_gpu_power,
};
void navi10_set_ppt_funcs(struct smu_context *smu)
--
2.20.1
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[PATCH 284/459] drm/amd/powerplay: fix clk type name error OD_SCLK OD_MCLK
From: Kevin Wang
use sw-smu clk type name to replace legacy clk type name
Signed-off-by: Kevin Wang
Reviewed-by: Huang Rui
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 4 ++--
drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 16
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ccb41fc4f74f..3936e81582de 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -564,9 +564,9 @@ struct pptable_funcs {
int (*update_specified_od8_value)(struct smu_context *smu,
uint32_t index,
uint32_t value);
- int (*get_od_percentage)(struct smu_context *smu, enum pp_clock_type
type);
+ int (*get_od_percentage)(struct smu_context *smu, enum smu_clk_type
clk_type);
int (*set_od_percentage)(struct smu_context *smu,
-enum pp_clock_type type,
+enum smu_clk_type clk_type,
uint32_t value);
int (*od_edit_dpm_table)(struct smu_context *smu,
enum PP_OD_DPM_TABLE_COMMAND type,
diff --git a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
index 1d91739d18e0..e6925e09ba19 100644
--- a/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/vega20_ppt.c
@@ -1690,7 +1690,7 @@ static int vega20_get_metrics_table(struct smu_context
*smu,
return ret;
}
static int vega20_get_od_percentage(struct smu_context *smu,
- enum pp_clock_type type)
+ enum smu_clk_type clk_type)
{
struct smu_dpm_context *smu_dpm = >smu_dpm;
struct vega20_dpm_table *dpm_table = NULL;
@@ -1702,12 +1702,12 @@ static int vega20_get_od_percentage(struct smu_context
*smu,
dpm_table = smu_dpm->dpm_context;
golden_table = smu_dpm->golden_dpm_context;
- switch (type) {
- case OD_SCLK:
+ switch (clk_type) {
+ case SMU_OD_SCLK:
single_dpm_table = &(dpm_table->gfx_table);
golden_dpm_table = &(golden_table->gfx_table);
break;
- case OD_MCLK:
+ case SMU_OD_MCLK:
single_dpm_table = &(dpm_table->mem_table);
golden_dpm_table = &(golden_table->mem_table);
break;
@@ -2447,7 +2447,7 @@ static int vega20_update_specified_od8_value(struct
smu_context *smu,
}
static int vega20_set_od_percentage(struct smu_context *smu,
- enum pp_clock_type type,
+ enum smu_clk_type clk_type,
uint32_t value)
{
struct smu_dpm_context *smu_dpm = >smu_dpm;
@@ -2465,15 +2465,15 @@ static int vega20_set_od_percentage(struct smu_context
*smu,
dpm_table = smu_dpm->dpm_context;
golden_table = smu_dpm->golden_dpm_context;
- switch (type) {
- case OD_SCLK:
+ switch (clk_type) {
+ case SMU_OD_SCLK:
single_dpm_table = &(dpm_table->gfx_table);
golden_dpm_table = &(golden_table->gfx_table);
feature_enabled = smu_feature_is_enabled(smu,
SMU_FEATURE_DPM_GFXCLK_BIT);
clk_id = PPCLK_GFXCLK;
index = OD8_SETTING_GFXCLK_FMAX;
break;
- case OD_MCLK:
+ case SMU_OD_MCLK:
single_dpm_table = &(dpm_table->mem_table);
golden_dpm_table = &(golden_table->mem_table);
feature_enabled = smu_feature_is_enabled(smu,
SMU_FEATURE_DPM_UCLK_BIT);
--
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[PATCH 283/459] drm/amd/powerplay: fix deadlock issue for smu_force_performance_level
From: Kevin Wang
the smu->mutex is internal lock resource in sw-smu, some functions will use
it at the same time, so it maybe will cause deadlock issue.
this patch fix this issue in smu_force_performance_level function.
Signed-off-by: Kevin Wang
Signed-off-by: Alex Deucher
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 9 -
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 5 -
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 6b97f3098118..c37db5166343 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -370,18 +370,9 @@ static ssize_t
amdgpu_set_dpm_forced_performance_level(struct device *dev,
}
if (is_support_sw_smu(adev)) {
- mutex_lock(>pm.mutex);
- if (adev->pm.dpm.thermal_active) {
- count = -EINVAL;
- mutex_unlock(>pm.mutex);
- goto fail;
- }
ret = smu_force_performance_level(>smu, level);
if (ret)
count = -EINVAL;
- else
- adev->pm.dpm.forced_level = level;
- mutex_unlock(>pm.mutex);
} else if (adev->powerplay.pp_funcs->force_performance_level) {
mutex_lock(>pm.mutex);
if (adev->pm.dpm.thermal_active) {
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 9384c1a5c594..ca16ead46379 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1459,12 +1459,15 @@ int smu_force_performance_level(struct smu_context
*smu, enum amd_dpm_forced_lev
break;
}
- mutex_lock(>mutex);
smu->adev->ip_blocks[i].version->funcs->enable_umd_pstate(smu, );
ret = smu_handle_task(smu, level,
AMD_PP_TASK_READJUST_POWER_STATE);
+ if (ret)
+ return ret;
+ mutex_lock(>mutex);
+ smu_dpm_ctx->dpm_level = level;
mutex_unlock(>mutex);
return ret;
--
2.20.1
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