RE: [PATCH] SWDEV-206718 drm/amdgpu: Fix tdr3 could hang with slow compute issue

[Deng, Emily]

Ping

Best wishes
Emily Deng



>-Original Message-
>From: Emily Deng 
>Sent: Wednesday, October 9, 2019 6:52 PM
>To: amd-gfx@lists.freedesktop.org
>Cc: Deng, Emily 
>Subject: [PATCH] SWDEV-206718 drm/amdgpu: Fix tdr3 could hang with slow
>compute issue
>
>When index is 1, need to set compute ring timeout for sriov and passthrough.
>
>Signed-off-by: Emily Deng 
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 -
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 6 --
> 2 files changed, 8 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>index 53ce227..2f5a015 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>@@ -2664,8 +2664,11 @@ static int
>amdgpu_device_get_job_timeout_settings(struct amdgpu_device *adev)
>* There is only one value specified and
>* it should apply to all non-compute jobs.
>*/
>-  if (index == 1)
>+  if (index == 1) {
>   adev->sdma_timeout = adev->video_timeout = adev-
>>gfx_timeout;
>+  if (amdgpu_sriov_vf(adev) ||
>amdgpu_passthrough(adev))
>+  adev->compute_timeout = adev->gfx_timeout;
>+  }
>   }
>
>   return ret;
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>index a88ea74..311abc8 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
>@@ -250,9 +250,11 @@ module_param_named(msi, amdgpu_msi, int, 0444);
>  * By default(with no lockup_timeout settings), the timeout for all non-
>compute(GFX, SDMA and Video)
>  * jobs is 1. And there is no timeout enforced on compute jobs.
>  */
>-MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default:
>1 for non-compute jobs and infinity timeout for compute jobs."
>+MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default:
>for bare metal 1 for non-compute jobs and infinity timeout for compute
>jobs; "
>+  "for passthrough or sriov, 1 for all jobs."
>   " 0: keep default value. negative: infinity timeout), "
>-  "format is [Non-Compute] or [GFX,Compute,SDMA,Video]");
>+  "format: for bare metal [Non-Compute] or
>[GFX,Compute,SDMA,Video]; "
>+  "for passthrough or sriov [all jobs] or
>[GFX,Compute,SDMA,Video].");
> module_param_string(lockup_timeout, amdgpu_lockup_timeout,
>sizeof(amdgpu_lockup_timeout), 0444);
>
> /**
>--
>2.7.4

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[PATCH] drm/amd/powerplay: enable Arcturus runtime VCN dpm on/off

[Quan, Evan]

Enable runtime VCN DPM on/off on Arcturus.

Change-Id: Ie7d94d67cb4c622c96acced1b5ef0f4e63db5aad
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c|  7 +
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 30 
 2 files changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c 
b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 2608c932a775..d270df892223 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -25,6 +25,7 @@
 #include 
 #include "amdgpu.h"
 #include "amdgpu_vcn.h"
+#include "amdgpu_pm.h"
 #include "soc15.h"
 #include "soc15d.h"
 #include "vcn_v2_0.h"
@@ -709,6 +710,9 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
uint32_t rb_bufsz, tmp;
int i, j, k, r;
 
+   if (adev->pm.dpm_enabled)
+   amdgpu_dpm_enable_uvd(adev, true);
+
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
continue;
@@ -939,6 +943,9 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
}
 
+   if (adev->pm.dpm_enabled)
+   amdgpu_dpm_enable_uvd(adev, false);
+
return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index a00b60968909..6731fed5458e 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -1907,6 +1907,35 @@ static bool arcturus_is_dpm_running(struct smu_context 
*smu)
return !!(feature_enabled & SMC_DPM_FEATURE);
 }
 
+static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
+{
+   struct smu_power_context *smu_power = >smu_power;
+   struct smu_power_gate *power_gate = _power->power_gate;
+   int ret = 0;
+
+   if (enable) {
+   if (!smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
+   ret = smu_feature_set_enabled(smu, 
SMU_FEATURE_VCN_PG_BIT, 1);
+   if (ret) {
+   pr_err("[EnableVCNDPM] failed!\n");
+   return ret;
+   }
+   }
+   power_gate->vcn_gated = false;
+   } else {
+   if (smu_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
+   ret = smu_feature_set_enabled(smu, 
SMU_FEATURE_VCN_PG_BIT, 0);
+   if (ret) {
+   pr_err("[DisableVCNDPM] failed!\n");
+   return ret;
+   }
+   }
+   power_gate->vcn_gated = true;
+   }
+
+   return ret;
+}
+
 static const struct pptable_funcs arcturus_ppt_funcs = {
/* translate smu index into arcturus specific index */
.get_smu_msg_index = arcturus_get_smu_msg_index,
@@ -1945,6 +1974,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.dump_pptable = arcturus_dump_pptable,
.get_power_limit = arcturus_get_power_limit,
.is_dpm_running = arcturus_is_dpm_running,
+   .dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
 };
 
 void arcturus_set_ppt_funcs(struct smu_context *smu)
-- 
2.23.0

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[PATCH] drm/amd/powerplay: print where the pptable comes from

[Yuan, Xiaojie]

this helps to know whether the pptable is from firmware or vbios

Signed-off-by: Xiaojie Yuan 
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 9883f0a4471a..809883c21241 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -369,6 +369,9 @@ static int smu_v11_0_setup_pptable(struct smu_context *smu)
version_major = le16_to_cpu(hdr->header.header_version_major);
version_minor = le16_to_cpu(hdr->header.header_version_minor);
if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
+   pr_info("using soft pptable #%d\n",
+   smu->smu_table.boot_values.pp_table_id);
+
switch (version_minor) {
case 0:
ret = smu_v11_0_set_pptable_v2_0(smu, , );
@@ -385,6 +388,8 @@ static int smu_v11_0_setup_pptable(struct smu_context *smu)
return ret;
 
} else {
+   pr_info("using pptable from vbios\n");
+
index = 
get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
powerplayinfo);
 
-- 
2.20.1

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Re: [PATCH 7/8] drm/amdgpu: reserve vram for memory training

[Alex Deucher]

On Fri, Oct 11, 2019 at 7:23 PM Tuikov, Luben  wrote:
>
> On 2019-10-10 11:50 p.m., Tianci Yin wrote:
> > From: "Tianci.Yin" 
> >
> > memory training using specific fixed vram segment, reserve these
> > segments before anyone may allocate it.
> >
> > Change-Id: I1436755813a565608a2857a683f535377620a637
> > Reviewed-by: Alex Deucher 
> > Signed-off-by: Tianci.Yin 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 96 +
> >  1 file changed, 96 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > index 9da6350a4ba2..42d0fcb98382 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> > @@ -1667,6 +1667,93 @@ static int amdgpu_ttm_fw_reserve_vram_init(struct 
> > amdgpu_device *adev)
> > >fw_vram_usage.va);
> >  }
> >
> > +/*
> > + * Memoy training reservation functions
> > + */
> > +
> > +/**
> > + * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved 
> > vram
> > + *
> > + * @adev: amdgpu_device pointer
> > + *
> > + * free memory training reserved vram if it has been reserved.
> > + */
> > +static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device 
> > *adev)
> > +{
> > + struct psp_memory_training_context *ctx = >psp.mem_train_ctx;
> > +
> > + ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
> > + if (ctx->c2p_bo) {
> > + amdgpu_bo_free_kernel(>c2p_bo, NULL, NULL);
> > + ctx->c2p_bo = NULL;
> > + }
>
> Generally it is a good idea to paragraph your code.
> So an empty line between if-statements is a good idea.
> However, there is no need in:
>
> ret = f(x);
> if (ret) {
> 
> }
>
> if (blah) {
> 
> }
>
> The above are two (2) well-formed paragraphs.
>
> > + if (ctx->p2c_bo) {
> > + amdgpu_bo_free_kernel(>p2c_bo, NULL, NULL);
> > + ctx->p2c_bo = NULL;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from 
> > memory training
> > + *
> > + * @adev: amdgpu_device pointer
> > + *
> > + * create bo vram reservation from memory training.
> > + */
> > +static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device 
> > *adev)
> > +{
> > + int ret;
> > + struct psp_memory_training_context *ctx = >psp.mem_train_ctx;
> > +
> > + memset(ctx, 0, sizeof(*ctx));
> > + if (!adev->fw_vram_usage.mem_train_support) {
> > + DRM_DEBUG("memory training does not support!\n");
> > + return 0;
> > + }
> > +
> > + ctx->c2p_train_data_offset = adev->fw_vram_usage.mem_train_fb_loc;
> > + ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - 
> > GDDR6_MEM_TRAINING_OFFSET);
> > + ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
> > +
> > + 
> > DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
> > +   ctx->train_data_size,
> > +   ctx->p2c_train_data_offset,
> > +   ctx->c2p_train_data_offset);
> > +
> > + ret = amdgpu_bo_create_kernel_at(adev,
> > +  ctx->p2c_train_data_offset,
> > +  ctx->train_data_size,
> > +  AMDGPU_GEM_DOMAIN_VRAM,
> > +  >p2c_bo,
> > +  NULL);
> > + if (ret) {
> > + DRM_ERROR("alloc p2c_bo failed(%d)!\n", ret);
> > + ret = -ENOMEM;
> > + goto err_out;
> > + }
>
> NAK!
> Why are you re-writing the error code from "amdgpu_bo_create_kenrel_at()"?
> Pass the error as is.
>
> > +
> > + ret = amdgpu_bo_create_kernel_at(adev,
> > +  ctx->c2p_train_data_offset,
> > +  ctx->train_data_size,
> > +  AMDGPU_GEM_DOMAIN_VRAM,
> > +  >c2p_bo,
> > +  NULL);
> > + if (ret) {
> > + DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
> > + ret = -ENOMEM;
> > + goto err_out;
> > + }
>
> NAK!
> Why are you re-writing the error code from "amdgpu_bo_create_kenrel_at()"?
> Pass the error as is.
>
> > +
> > + ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
> > + return 0;
> > +
> > +err_out:
>
> Yes... well "err_out" could be any identifier, including
> a variable, as our variables follow snake-notation, all lowercase.
>
> Back at the turn of this century, Linux followed capitalized
> goto labels to distinguish them from anything else around
> in the kernel code:
>
> goto Bad_err;
> ...
>
> return 0;
> Bad_err:
> return bad_gift;
> }
>
> To distinguish that a capitalized identifier is a goto label,
> "Bad_err" and all 

Re: [PATCH 4/8] drm/amdgpu: update atomfirmware header with memory training related members

[Alex Deucher]

On Fri, Oct 11, 2019 at 6:53 PM Tuikov, Luben  wrote:
>
> On 2019-10-10 11:50 p.m., Tianci Yin wrote:
> > From: "Tianci.Yin" 
> >
> > add new vram_reserve_block structure and atomfirmware_internal_constants 
> > enumeration
> >
> > Change-Id: I6ba642ecd7ad94250162ae5c322ed8d85de9c35a
> > Reviewed-by: Alex Deucher 
> > Signed-off-by: Tianci.Yin 
> > ---
> >  drivers/gpu/drm/amd/include/atomfirmware.h | 28 +-
> >  1 file changed, 22 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h 
> > b/drivers/gpu/drm/amd/include/atomfirmware.h
> > index e88541d67aa0..463c18e99d78 100644
> > --- a/drivers/gpu/drm/amd/include/atomfirmware.h
> > +++ b/drivers/gpu/drm/amd/include/atomfirmware.h
> > @@ -492,12 +492,13 @@ struct atom_firmware_info_v3_1
> >  /* Total 32bit cap indication */
> >  enum atombios_firmware_capability
> >  {
> > -  ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x0001,
> > -  ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION  = 0x0002,
> > -  ATOM_FIRMWARE_CAP_WMI_SUPPORT  = 0x0040,
> > -  ATOM_FIRMWARE_CAP_HWEMU_ENABLE  = 0x0080,
> > -  ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x0100,
> > -  ATOM_FIRMWARE_CAP_SRAM_ECC  = 0x0200,
> > + ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x0001,
> > + ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION  = 0x0002,
> > + ATOM_FIRMWARE_CAP_WMI_SUPPORT  = 0x0040,
> > + ATOM_FIRMWARE_CAP_HWEMU_ENABLE  = 0x0080,
> > + ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x0100,
> > + ATOM_FIRMWARE_CAP_SRAM_ECC  = 0x0200,
> > + ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING  = 0x0400,
> >  };
> >
> >  enum atom_cooling_solution_id{
> > @@ -671,6 +672,21 @@ struct vram_usagebyfirmware_v2_1
> >uint16_t  used_by_driver_in_kb;
> >  };
> >
> > +/* This is part of vram_usagebyfirmware_v2_1 */
> > +struct vram_reserve_block
> > +{
> > + uint32_t start_address_in_kb;
> > + uint16_t used_by_firmware_in_kb;
> > + uint16_t used_by_driver_in_kb;
> > +};
> > +
> > +/* Definitions for constance */
> > +enum atomfirmware_internal_constants
> > +{
> > + ONE_K   = 0x400,
> > + ONE_MEG = 0x10,
> > + ONE_G   = 0x4000,
>
> So... this is pronounced in English as "One Gee", and even though
> I like it much much better due to what is actually says (no, it is not
> "one gigabyte"), I'd rather you called this "ONE_GiB".
>
> You do not have "One G" anywhere in this code. :-)
>
> To fit international standardization and the move Linux constants
> have been going to, name them this:
>
> ONE_KiB
> ONE_MiB
> ONE_GiB
>
> This means what it says and also that they are power of 2.
>
> ONE_GB (10^9) is less than ONE_GiB (2^30).
>

This file isn't owned by us.  We are just syncing with their latest
updates.  We try and stick to what they have pretty closely to avoid
conflicts in future updates.

Alex

> Regards,
> Luben
>
> > +};
> >
> >  /*
> >
> > ***
> >
>
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Re: [PATCH v2] drm/amd/powerplay: bug fix for pcie parameters override

[Alex Deucher]

On Fri, Oct 11, 2019 at 6:34 AM Kenneth Feng  wrote:
>
> Bug fix for pcie paramerers override on swsmu.
> Below is a scenario to have this problem.
> pptable definition on pcie dpm:
> 0 -> pcie gen speed:1, pcie lanes: *16
> 1 -> pcie gen speed:4, pcie lanes: *16
> Then if we have a system only have the capbility:
> pcie gen speed: 3, pcie lanes: *8,
> we will override dpm 1 to pcie gen speed 3, pcie lanes *8.
> But the code skips the dpm 0 configuration.
> So the real pcie dpm parameters are:
> 0 -> pcie gen speed:1, pcie lanes: *16
> 1 -> pcie gen speed:3, pcie lanes: *8
> Then the wrong pcie lanes will be toggled.
>
> Signed-off-by: Kenneth Feng 

Reviewed-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 44 
> --
>  drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  8 +
>  drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 23 ++
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 44 
> ++
>  drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 25 ++-
>  5 files changed, 99 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index c9266ea..de54da2 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -945,50 +945,6 @@ static int smu_fini_fb_allocations(struct smu_context 
> *smu)
> return 0;
>  }
>
> -static int smu_override_pcie_parameters(struct smu_context *smu)
> -{
> -   struct amdgpu_device *adev = smu->adev;
> -   uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
> -   int ret;
> -
> -   if (adev->flags & AMD_IS_APU)
> -   return 0;
> -
> -   if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
> -   pcie_gen = 3;
> -   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
> -   pcie_gen = 2;
> -   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
> -   pcie_gen = 1;
> -   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
> -   pcie_gen = 0;
> -
> -   /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
> -* Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
> -* Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
> -*/
> -   if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
> -   pcie_width = 6;
> -   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
> -   pcie_width = 5;
> -   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
> -   pcie_width = 4;
> -   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
> -   pcie_width = 3;
> -   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
> -   pcie_width = 2;
> -   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
> -   pcie_width = 1;
> -
> -   smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
> -   ret = smu_send_smc_msg_with_param(smu,
> - SMU_MSG_OverridePcieParameters,
> - smu_pcie_arg);
> -   if (ret)
> -   pr_err("[%s] Attempt to override pcie params failed!\n", 
> __func__);
> -   return ret;
> -}
> -
>  static int smu_smc_table_hw_init(struct smu_context *smu,
>  bool initialize)
>  {
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index ccf711c..809de0d 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -468,6 +468,7 @@ struct pptable_funcs {
> int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool 
> asic_default);
> int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type 
> clk_type,
>uint32_t dpm_level, uint32_t *freq);
> +   int (*update_pcie_parameters)(struct smu_context *smu, uint32_t 
> pcie_gen_cap, uint32_t pcie_width_cap);
>  };
>
>  struct smu_funcs
> @@ -550,6 +551,7 @@ struct smu_funcs
> int (*mode2_reset)(struct smu_context *smu);
> int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum 
> smu_clk_type clk_type, uint32_t *min, uint32_t *max);
> int (*set_soft_freq_limited_range)(struct smu_context *smu, enum 
> smu_clk_type clk_type, uint32_t min, uint32_t max);
> +   int (*override_pcie_parameters)(struct smu_context *smu);
>  };
>
>  #define smu_init_microcode(smu) \
> @@ -782,6 +784,12 @@ struct smu_funcs
>  #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
> ((smu)->funcs->set_soft_freq_limited_range ? 
> (smu)->funcs->set_soft_freq_limited_range((smu), 

Re: [PATCH 2/5] drm/amdgpu: move gpu reset out of amdgpu_device_suspend

[Alex Deucher]

Thanks.  I'll make note of this in the commit message.

On Fri, Oct 11, 2019 at 9:42 PM Quan, Evan  wrote:
>
> Thanks for the clarification. That will be fine then.
> Reviewed-by: Evan Quan 
>
> -Original Message-
> From: Alex Deucher 
> Sent: Friday, October 11, 2019 9:25 PM
> To: Quan, Evan 
> Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
> 
> Subject: Re: [PATCH 2/5] drm/amdgpu: move gpu reset out of 
> amdgpu_device_suspend
>
> On Fri, Oct 11, 2019 at 12:07 AM Quan, Evan  wrote:
> >
> > It seems amdgpu_pmops_runtime_suspend() needs to be updated accordingly 
> > also.
>
> I purposely left that out.  I think that is a bug.  We don't need to reset 
> the GPU for runtime suspend.  We only need it for hibernation because of the 
> whole freeze/thaw dance.
>
> Alex
>
> >
> > -Original Message-
> > From: amd-gfx  On Behalf Of
> > Alex Deucher
> > Sent: Thursday, October 10, 2019 11:26 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander 
> > Subject: [PATCH 2/5] drm/amdgpu: move gpu reset out of
> > amdgpu_device_suspend
> >
> > Move it into the caller.  There are cases were we don't want it.  We
> > need it for hibernation, but we don't need it for runtime pm.
> >
> > Signed-off-by: Alex Deucher 
> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 7 ++-
> >  2 files changed, 6 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index 9b9b15360194..91bdb246e405 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -3173,10 +3173,6 @@ int amdgpu_device_suspend(struct drm_device *dev, 
> > bool suspend, bool fbcon)
> > /* Shut down the device */
> > pci_disable_device(dev->pdev);
> > pci_set_power_state(dev->pdev, PCI_D3hot);
> > -   } else {
> > -   r = amdgpu_asic_reset(adev);
> > -   if (r)
> > -   DRM_ERROR("amdgpu asic reset failed\n");
> > }
> >
> > return 0;
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > index d43c46de7807..64141386e603 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> > @@ -1118,8 +1118,13 @@ static int amdgpu_pmops_resume(struct device
> > *dev)  static int amdgpu_pmops_freeze(struct device *dev)  {
> > struct drm_device *drm_dev = dev_get_drvdata(dev);
> > +   struct amdgpu_device *adev = drm_dev->dev_private;
> > +   int r;
> >
> > -   return amdgpu_device_suspend(drm_dev, false, true);
> > +   r = amdgpu_device_suspend(drm_dev, false, true);
> > +   if (r)
> > +   return r;
> > +   return amdgpu_asic_reset(adev);
> >  }
> >
> >  static int amdgpu_pmops_thaw(struct device *dev)
> > --
> > 2.20.1
> >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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RE: [PATCH 2/5] drm/amdgpu: move gpu reset out of amdgpu_device_suspend

[Quan, Evan]

Thanks for the clarification. That will be fine then.
Reviewed-by: Evan Quan 

-Original Message-
From: Alex Deucher  
Sent: Friday, October 11, 2019 9:25 PM
To: Quan, Evan 
Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander 

Subject: Re: [PATCH 2/5] drm/amdgpu: move gpu reset out of amdgpu_device_suspend

On Fri, Oct 11, 2019 at 12:07 AM Quan, Evan  wrote:
>
> It seems amdgpu_pmops_runtime_suspend() needs to be updated accordingly also.

I purposely left that out.  I think that is a bug.  We don't need to reset the 
GPU for runtime suspend.  We only need it for hibernation because of the whole 
freeze/thaw dance.

Alex

>
> -Original Message-
> From: amd-gfx  On Behalf Of 
> Alex Deucher
> Sent: Thursday, October 10, 2019 11:26 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: [PATCH 2/5] drm/amdgpu: move gpu reset out of 
> amdgpu_device_suspend
>
> Move it into the caller.  There are cases were we don't want it.  We 
> need it for hibernation, but we don't need it for runtime pm.
>
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 7 ++-
>  2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 9b9b15360194..91bdb246e405 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3173,10 +3173,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
> suspend, bool fbcon)
> /* Shut down the device */
> pci_disable_device(dev->pdev);
> pci_set_power_state(dev->pdev, PCI_D3hot);
> -   } else {
> -   r = amdgpu_asic_reset(adev);
> -   if (r)
> -   DRM_ERROR("amdgpu asic reset failed\n");
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index d43c46de7807..64141386e603 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1118,8 +1118,13 @@ static int amdgpu_pmops_resume(struct device 
> *dev)  static int amdgpu_pmops_freeze(struct device *dev)  {
> struct drm_device *drm_dev = dev_get_drvdata(dev);
> +   struct amdgpu_device *adev = drm_dev->dev_private;
> +   int r;
>
> -   return amdgpu_device_suspend(drm_dev, false, true);
> +   r = amdgpu_device_suspend(drm_dev, false, true);
> +   if (r)
> +   return r;
> +   return amdgpu_asic_reset(adev);
>  }
>
>  static int amdgpu_pmops_thaw(struct device *dev)
> --
> 2.20.1
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
___
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Re: [PATCH 8/8] drm/amdgpu/psp: add psp memory training implementation

[Tuikov, Luben]

On 2019-10-10 11:50 p.m., Tianci Yin wrote:
> From: "Tianci.Yin" 
> 
> add memory training implementation code to save resume time.
> 
> Change-Id: I625794a780b11d824ab57ef39cc33b872c6dc6c9
> Reviewed-by: Alex Deucher 
> Signed-off-by: Tianci.Yin 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h |   1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c |   9 ++
>  drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 171 
>  3 files changed, 181 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index e3d715c31ac9..03c5c18bb51e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -151,6 +151,7 @@ extern uint amdgpu_sdma_phase_quantum;
>  extern char *amdgpu_disable_cu;
>  extern char *amdgpu_virtual_display;
>  extern uint amdgpu_pp_feature_mask;
> +extern uint amdgpu_force_long_training;
>  extern int amdgpu_job_hang_limit;
>  extern int amdgpu_lbpw;
>  extern int amdgpu_compute_multipipe;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 5985bd79216d..f03dcc5d185d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -127,6 +127,7 @@ char *amdgpu_disable_cu = NULL;
>  char *amdgpu_virtual_display = NULL;
>  /* OverDrive(bit 14) disabled by default*/
>  uint amdgpu_pp_feature_mask = 0xbfff;
> +uint amdgpu_force_long_training = 0;
>  int amdgpu_job_hang_limit = 0;
>  int amdgpu_lbpw = -1;
>  int amdgpu_compute_multipipe = -1;
> @@ -390,6 +391,14 @@ module_param_named(sched_hw_submission, 
> amdgpu_sched_hw_submission, int, 0444);
>  MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
>  module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444);
>  
> +/**
> + * DOC: forcelongtraining (uint)
> + * Force long memory training in resume.
> + * The default is zero, indicates short training in resume.
> + */
> +MODULE_PARM_DESC(forcelongtraining, "force memory long training");
> +module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 
> 0444);
> +
>  /**
>   * DOC: pcie_gen_cap (uint)
>   * Override PCIE gen speed capabilities. See the CAIL flags in 
> drivers/gpu/drm/amd/include/amd_pcie.h.
> diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c 
> b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> index 2ba0f68ced10..074f23c846cb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
> @@ -902,6 +902,174 @@ static int psp_v11_0_rlc_autoload_start(struct 
> psp_context *psp)
>   return psp_rlc_autoload_start(psp);
>  }
>  
> +static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int 
> msg)
> +{
> + int ret = 0;
> + int i = 0;
> + uint32_t data_32 = 0;
> + struct amdgpu_device *adev = psp->adev;

NAK! to preinitializing variables.

> +
> + data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
> + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
> + WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
> +
> + /*max 5s*/
> + while (i < 50) {
> + ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, 
> mmMP0_SMN_C2PMSG_35),
> +0x8000, 0x8000, false);

Hmm, none of the loop body depends on "i"?
So, conceivably one could do this one time instead of 50?
Interesting... So perhaps the "50" couuld be a macro explaining
what kind of constant it is...

> + if (ret == 0)
> + break;
> + i++;
> + }

NAK to broken up loop definition. Use a for-loop:

for (i = 0; i < 50; i++) {
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
   0x8000, 0x8000, false);
if (ret)
break;
}

This makes the code more secure as well as the loop-body relocatable
into a function, etc. As well as obvious that the body
of the loop does NOT depend on "i" and therefore "50" is completely
arbitratry.

> + DRM_DEBUG("%s training %s, cost %d * %dms.\n",
> +   (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
> +   (ret == 0) ? "succeed" : "failed",
> +   i, adev->usec_timeout/1000);
> + return ret;
> +}
> +
> +static int psp_v11_0_memory_training_fini(struct psp_context *psp)
> +{
> + int ret = 0;

NAK!

> + struct psp_memory_training_context *ctx = >mem_train_ctx;
> +
> + ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
> + if(ctx->sys_cache) {

Space after keyword: "if (...".

> + kfree(ctx->sys_cache);
> + ctx->sys_cache = NULL;
> + }
> +
> + return ret;

NAK!
This function should be "void"! Like all "free" functions.

> +}
> +
> +static int psp_v11_0_memory_training_init(struct psp_context *psp)
> +{
> + int ret = 0;

NAK due to pre-initializing "ret".

> + struct psp_memory_training_context *ctx = >mem_train_ctx;

Re: [PATCH 7/8] drm/amdgpu: reserve vram for memory training

[Tuikov, Luben]

On 2019-10-10 11:50 p.m., Tianci Yin wrote:
> From: "Tianci.Yin" 
> 
> memory training using specific fixed vram segment, reserve these
> segments before anyone may allocate it.
> 
> Change-Id: I1436755813a565608a2857a683f535377620a637
> Reviewed-by: Alex Deucher 
> Signed-off-by: Tianci.Yin 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 96 +
>  1 file changed, 96 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 9da6350a4ba2..42d0fcb98382 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1667,6 +1667,93 @@ static int amdgpu_ttm_fw_reserve_vram_init(struct 
> amdgpu_device *adev)
> >fw_vram_usage.va);
>  }
>  
> +/*
> + * Memoy training reservation functions
> + */
> +
> +/**
> + * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
> + *
> + * @adev: amdgpu_device pointer
> + *
> + * free memory training reserved vram if it has been reserved.
> + */
> +static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
> +{
> + struct psp_memory_training_context *ctx = >psp.mem_train_ctx;
> +
> + ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
> + if (ctx->c2p_bo) {
> + amdgpu_bo_free_kernel(>c2p_bo, NULL, NULL);
> + ctx->c2p_bo = NULL;
> + }

Generally it is a good idea to paragraph your code.
So an empty line between if-statements is a good idea.
However, there is no need in:

ret = f(x);
if (ret) {

}

if (blah) {

}

The above are two (2) well-formed paragraphs.

> + if (ctx->p2c_bo) {
> + amdgpu_bo_free_kernel(>p2c_bo, NULL, NULL);
> + ctx->p2c_bo = NULL;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * amdgpu_ttm_training_reserve_vram_init - create bo vram reservation from 
> memory training
> + *
> + * @adev: amdgpu_device pointer
> + *
> + * create bo vram reservation from memory training.
> + */
> +static int amdgpu_ttm_training_reserve_vram_init(struct amdgpu_device *adev)
> +{
> + int ret;
> + struct psp_memory_training_context *ctx = >psp.mem_train_ctx;
> +
> + memset(ctx, 0, sizeof(*ctx));
> + if (!adev->fw_vram_usage.mem_train_support) {
> + DRM_DEBUG("memory training does not support!\n");
> + return 0;
> + }
> +
> + ctx->c2p_train_data_offset = adev->fw_vram_usage.mem_train_fb_loc;
> + ctx->p2c_train_data_offset = (adev->gmc.mc_vram_size - 
> GDDR6_MEM_TRAINING_OFFSET);
> + ctx->train_data_size = GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
> +
> + 
> DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
> +   ctx->train_data_size,
> +   ctx->p2c_train_data_offset,
> +   ctx->c2p_train_data_offset);
> +
> + ret = amdgpu_bo_create_kernel_at(adev,
> +  ctx->p2c_train_data_offset,
> +  ctx->train_data_size,
> +  AMDGPU_GEM_DOMAIN_VRAM,
> +  >p2c_bo,
> +  NULL);
> + if (ret) {
> + DRM_ERROR("alloc p2c_bo failed(%d)!\n", ret);
> + ret = -ENOMEM;
> + goto err_out;
> + }

NAK!
Why are you re-writing the error code from "amdgpu_bo_create_kenrel_at()"?
Pass the error as is.

> +
> + ret = amdgpu_bo_create_kernel_at(adev,
> +  ctx->c2p_train_data_offset,
> +  ctx->train_data_size,
> +  AMDGPU_GEM_DOMAIN_VRAM,
> +  >c2p_bo,
> +  NULL);
> + if (ret) {
> + DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
> + ret = -ENOMEM;
> + goto err_out;
> + }

NAK!
Why are you re-writing the error code from "amdgpu_bo_create_kenrel_at()"?
Pass the error as is.

> +
> + ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
> + return 0;
> +
> +err_out:

Yes... well "err_out" could be any identifier, including
a variable, as our variables follow snake-notation, all lowercase.

Back at the turn of this century, Linux followed capitalized
goto labels to distinguish them from anything else around
in the kernel code:

goto Bad_err;
...

return 0;
Bad_err:
return bad_gift;
}

To distinguish that a capitalized identifier is a goto label,
"Bad_err" and all lower-case label is just another variable
or function identifier, "bad_gift".

Regards,
Luben

> + amdgpu_ttm_training_reserve_vram_fini(adev);
> + return ret;
> +}
> +
>  /**
>   * amdgpu_ttm_init - Init the memory management (ttm) as well as various
>   * gtt/vram related fields.
> @@ -1740,6 +1827,14 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
>   

Re: [PATCH 5/8] drm/amdgpu/atomfirmware: add memory training related helper functions

[Tuikov, Luben]

On 2019-10-10 11:50 p.m., Tianci Yin wrote:
> From: "Tianci.Yin" 
> 
> parse firmware to get memory training capability and fb location.
> 
> Change-Id: I147c1d48e255e0191be4beb1ad6b637da607bf75
> Reviewed-by: Alex Deucher 
> Signed-off-by: Tianci.Yin 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |   7 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c  |   5 +
>  .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c  | 133 ++
>  .../gpu/drm/amd/amdgpu/amdgpu_atomfirmware.h  |   1 +
>  4 files changed, 146 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 1102e6bae5d5..e3d715c31ac9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -291,6 +291,9 @@ struct amdgpu_ip_block_version {
>   const struct amd_ip_funcs *funcs;
>  };
>  
> +#define hw_revision(major, minor, revision) \
> + uint32_t) major) << 16) | ((uint32_t) minor << 8) | ((uint32_t) 
> revision))
> +

Last century, compilers and preprocessors weren't that smart and
should a variable exist of the same name as the replacement token in
a substituion macro, and the macro was used in that function, then
they got confused.

And also, you should surround the substition tokens in parenthesis
in the RHS of the macro expression!

For this reason we used tokens which one would never find in normal
C code:

#define HW_REV(_Major, _Minor, _Rev) \
uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | 
((uint32_t) (_Rev)))

It became a habit and as it happens to all habits... a style.

>  struct amdgpu_ip_block {
>   struct amdgpu_ip_block_status status;
>   const struct amdgpu_ip_block_version *version;
> @@ -633,6 +636,10 @@ struct amdgpu_fw_vram_usage {
>   u64 size;
>   struct amdgpu_bo *reserved_bo;
>   void *va;
> +
> + /*offset on the top of vram, used as c2p write buffer*/
> + u64 mem_train_fb_loc;
> + bool mem_train_support;
>  };

We try to make comments pleasantly readable:

/* Offset on the top of VRAM, used as c2p write buffer.
 */
u64  mem_train_fb_loc;
bool mem_train_support;
}

Regards,
Luben

>  
>  /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> index 1c9d40f97a9b..72232fccf61a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
> @@ -2038,6 +2038,11 @@ int amdgpu_atombios_init(struct amdgpu_device *adev)
>   if (adev->is_atom_fw) {
>   amdgpu_atomfirmware_scratch_regs_init(adev);
>   amdgpu_atomfirmware_allocate_fb_scratch(adev);
> + ret = amdgpu_atomfirmware_get_mem_train_fb_loc(adev);
> + if (ret) {
> + DRM_ERROR("Failed to get mem train fb location.\n");
> + return ret;
> + }
>   } else {
>   amdgpu_atombios_scratch_regs_init(adev);
>   amdgpu_atombios_allocate_fb_scratch(adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> index 39fd8ae5a822..1ebf5e9a9b7b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
> @@ -27,6 +27,7 @@
>  #include "amdgpu_atomfirmware.h"
>  #include "atom.h"
>  #include "atombios.h"
> +#include "soc15_hw_ip.h"
>  
>  bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device 
> *adev)
>  {
> @@ -462,3 +463,135 @@ int amdgpu_atomfirmware_get_gfx_info(struct 
> amdgpu_device *adev)
>   }
>   return -EINVAL;
>  }
> +
> +/*
> + * Check if VBIOS supports GDDR6 training data save/restore
> + */
> +static bool gddr6_mem_train_vbios_support(struct amdgpu_device *adev)
> +{
> + uint16_t data_offset;
> + int index;
> +
> + index = 
> get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
> + firmwareinfo);
> + if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, 
> NULL,
> +   NULL, NULL, _offset)) {
> + struct atom_firmware_info_v3_1 *firmware_info =
> + (struct atom_firmware_info_v3_1 
> *)(adev->mode_info.atom_context->bios +
> +data_offset);
> +
> + DRM_DEBUG("atom firmware capability:0x%08x.\n",
> +   le32_to_cpu(firmware_info->firmware_capability));
> +
> + if (le32_to_cpu(firmware_info->firmware_capability) &
> + ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING)
> + return true;
> + }
> +
> + return false;
> +}
> +
> +static int gddr6_mem_train_support(struct amdgpu_device *adev)
> +{
> + int ret;
> + bool vbios_support;
> + uint32_t major, minor, revision, hw_v;
> +
> + if 

Re: [PATCH 4/8] drm/amdgpu: update atomfirmware header with memory training related members

[Tuikov, Luben]

On 2019-10-10 11:50 p.m., Tianci Yin wrote:
> From: "Tianci.Yin" 
> 
> add new vram_reserve_block structure and atomfirmware_internal_constants 
> enumeration
> 
> Change-Id: I6ba642ecd7ad94250162ae5c322ed8d85de9c35a
> Reviewed-by: Alex Deucher 
> Signed-off-by: Tianci.Yin 
> ---
>  drivers/gpu/drm/amd/include/atomfirmware.h | 28 +-
>  1 file changed, 22 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h 
> b/drivers/gpu/drm/amd/include/atomfirmware.h
> index e88541d67aa0..463c18e99d78 100644
> --- a/drivers/gpu/drm/amd/include/atomfirmware.h
> +++ b/drivers/gpu/drm/amd/include/atomfirmware.h
> @@ -492,12 +492,13 @@ struct atom_firmware_info_v3_1
>  /* Total 32bit cap indication */
>  enum atombios_firmware_capability
>  {
> -  ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x0001,
> -  ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION  = 0x0002,
> -  ATOM_FIRMWARE_CAP_WMI_SUPPORT  = 0x0040,
> -  ATOM_FIRMWARE_CAP_HWEMU_ENABLE  = 0x0080,
> -  ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x0100,
> -  ATOM_FIRMWARE_CAP_SRAM_ECC  = 0x0200,
> + ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x0001,
> + ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION  = 0x0002,
> + ATOM_FIRMWARE_CAP_WMI_SUPPORT  = 0x0040,
> + ATOM_FIRMWARE_CAP_HWEMU_ENABLE  = 0x0080,
> + ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x0100,
> + ATOM_FIRMWARE_CAP_SRAM_ECC  = 0x0200,
> + ATOM_FIRMWARE_CAP_ENABLE_2STAGE_BIST_TRAINING  = 0x0400,
>  };
>  
>  enum atom_cooling_solution_id{
> @@ -671,6 +672,21 @@ struct vram_usagebyfirmware_v2_1
>uint16_t  used_by_driver_in_kb; 
>  };
>  
> +/* This is part of vram_usagebyfirmware_v2_1 */
> +struct vram_reserve_block
> +{
> + uint32_t start_address_in_kb;
> + uint16_t used_by_firmware_in_kb;
> + uint16_t used_by_driver_in_kb;
> +};
> +
> +/* Definitions for constance */
> +enum atomfirmware_internal_constants
> +{
> + ONE_K   = 0x400,
> + ONE_MEG = 0x10,
> + ONE_G   = 0x4000,

So... this is pronounced in English as "One Gee", and even though
I like it much much better due to what is actually says (no, it is not
"one gigabyte"), I'd rather you called this "ONE_GiB".

You do not have "One G" anywhere in this code. :-)

To fit international standardization and the move Linux constants
have been going to, name them this:

ONE_KiB
ONE_MiB
ONE_GiB

This means what it says and also that they are power of 2.

ONE_GB (10^9) is less than ONE_GiB (2^30).

Regards,
Luben

> +};
>  
>  /* 
>***
> 

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Re: [PATCH 2/8] drm/amdgpu: add a generic fb accessing helper function

[Tuikov, Luben]

On 2019-10-10 11:50 p.m., Tianci Yin wrote:
> From: "Tianci.Yin" 
> 
> add a generic helper function for accessing framebuffer via MMIO
> 
> Change-Id: I4baa0aa53c93a94c2eff98c6211a61f369239982
> Reviewed-by: Alex Deucher 
> Signed-off-by: Tianci.Yin 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  2 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 34 +++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 13 +--
>  3 files changed, 37 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 51ccf175cda0..1102e6bae5d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -991,6 +991,8 @@ int amdgpu_device_init(struct amdgpu_device *adev,
>  void amdgpu_device_fini(struct amdgpu_device *adev);
>  int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
>  
> +int amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
> +   uint32_t *buf, size_t size, bool write);
>  uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
>   uint32_t acc_flags);
>  void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 598158e95ec1..fb21ec1f8a61 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -154,6 +154,40 @@ bool amdgpu_device_is_px(struct drm_device *dev)
>   return false;
>  }
>  
> +/**
> + * VRAM access helper functions.
> + *
> + * amdgpu_device_vram_access - read/write a buffer in vram
> + *
> + * @adev: amdgpu_device pointer
> + * @pos: offset of the buffer in vram
> + * @buf: virtual address of the buffer in system memory
> + * @size: read/write size, sizeof(@buf) must > @size
> + * @write: true - write to vram, otherwise - read from vram
> + *
> + * Returns 0 on success or an -error on failure.

Really? Where?
This function seems to return 0.
Traditionally read/write functions
return the number of bytes read/written or error.
You do neither. Just define it void.

> + */
> +int amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos,
> +   uint32_t *buf, size_t size, bool write)
> +{
> + uint64_t end = pos + size;

NAK! to preinitializing automatic variables.

> + unsigned long flags;
> +
> + while (pos < end) {
> + spin_lock_irqsave(>mmio_idx_lock, flags);
> + WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x8000);
> + WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
> + if (write)
> + WREG32_NO_KIQ(mmMM_DATA, *buf++);
> + else
> + *buf++ = RREG32_NO_KIQ(mmMM_DATA);
> + spin_unlock_irqrestore(>mmio_idx_lock, flags);
> + pos += 4;
> + }

NAK! to this this:

while (pos < end) { <---+
  |--> Part of the loop definition
pos += 4;   <---+
}

Instead of breaking up the loop definition like this,
use a for-loop, and DO NOT preinitialize the "end" variable,
and also protect from overflow, all like this:

last = size - 1;
for (last += pos; pos <= last; pos += 4) {

}

I mentioned the why of this in my previous review of the same
topic patchset over the same while loop fiasco.

Regards,
Luben

> +
> + return 0;
> +}
> +
>  /*
>   * MMIO register access helper functions.
>   */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index db2dab3a6dff..324c2d605f54 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -134,21 +134,10 @@ static int hw_id_map[MAX_HWIP] = {
>  
>  static int amdgpu_discovery_read_binary(struct amdgpu_device *adev, uint8_t 
> *binary)
>  {
> - uint32_t *p = (uint32_t *)binary;
>   uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
>   uint64_t pos = vram_size - BINARY_MAX_SIZE;
> - unsigned long flags;
> -
> - while (pos < vram_size) {
> - spin_lock_irqsave(>mmio_idx_lock, flags);
> - WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)pos) | 0x8000);
> - WREG32_NO_KIQ(mmMM_INDEX_HI, pos >> 31);
> - *p++ = RREG32_NO_KIQ(mmMM_DATA);
> - spin_unlock_irqrestore(>mmio_idx_lock, flags);
> - pos += 4;
> - }
>  
> - return 0;
> + return amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, 
> BINARY_MAX_SIZE, false);
>  }
>  
>  static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t 
> size)
> 

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Re: [PATCH] drm/amd/display: Free gamma after calculating legacy transfer function

[Li, Sun peng (Leo)]

On 2019-10-11 12:26 p.m., Nicholas Kazlauskas wrote:
> [Why]
> We're leaking memory by not freeing the gamma used to calculate the
> transfer function for legacy gamma.
> 
> [How]
> Release the gamma after we're done with it.
> 
> Cc: Philip Yang 
> Cc: Harry Wentland 
> Cc: Bhawanpreet Lakha 
> Cc: Leo Li 
> Signed-off-by: Nicholas Kazlauskas 
Thanks!

> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> index b43bb7f90e4e..2233d293a707 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
> @@ -210,6 +210,8 @@ static int __set_legacy_tf(struct dc_transfer_func *func,
>   res = mod_color_calculate_regamma_params(func, gamma, true, has_rom,
>NULL);
>  
> + dc_gamma_release();
> +
>   return res ? 0 : -ENOMEM;
>  }
>  
> 
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[PATCH] drm/amd/display: add NULL checks for clock manager pointer

[Alex Deucher]

From: Ahzo 

This fixes kernel NULL pointer dereferences on shutdown:
RIP: 0010:build_audio_output.isra.0+0x97/0x110 [amdgpu]
RIP: 0010:enable_link_dp+0x186/0x300 [amdgpu]

Signed-off-by: Ahzo 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c   | 2 +-
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 5 +++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 152c564a8344..8b58cfa3e98e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1510,7 +1510,7 @@ static enum dc_status enable_link_dp(
 
pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
-   if (!apply_seamless_boot_optimization)
+   if (state->clk_mgr && !apply_seamless_boot_optimization)
state->clk_mgr->funcs->update_clocks(state->clk_mgr, state, 
false);
 
dp_enable_link_phy(
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index f8c1b4f1b987..8d8fa10b5d86 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1161,8 +1161,9 @@ static void build_audio_output(
}
}
 
-   if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
-   pipe_ctx->stream->signal == 
SIGNAL_TYPE_DISPLAY_PORT_MST) {
+   if (state->clk_mgr &&
+   (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
+   pipe_ctx->stream->signal == 
SIGNAL_TYPE_DISPLAY_PORT_MST)) {
audio_output->pll_info.dp_dto_source_clock_in_khz =
state->clk_mgr->funcs->get_dp_ref_clk_frequency(
state->clk_mgr);
-- 
2.20.1

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[PATCH 1/2] drm/amdgpu/uvd6: fix allocation size in enc ring test

[Alex Deucher]

We need to allocate a large enough buffer for the
session info, otherwise the IB test can overwrite
other memory.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 670784a78512..909bc2ce791f 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -215,12 +215,12 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring 
*ring, uint32_t handle
uint64_t dummy;
int i, r;
 
-   r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, );
+   r = amdgpu_job_alloc_with_ib(ring->adev, (ib_size_dw * 4) + 1024, );
if (r)
return r;
 
ib = >ibs[0];
-   dummy = ib->gpu_addr + 1024;
+   dummy = ib->gpu_addr + (ib_size_dw * 4);
 
ib->length_dw = 0;
ib->ptr[ib->length_dw++] = 0x0018;
@@ -277,12 +277,12 @@ static int uvd_v6_0_enc_get_destroy_msg(struct 
amdgpu_ring *ring,
uint64_t dummy;
int i, r;
 
-   r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, );
+   r = amdgpu_job_alloc_with_ib(ring->adev, (ib_size_dw * 4) + 1024, );
if (r)
return r;
 
ib = >ibs[0];
-   dummy = ib->gpu_addr + 1024;
+   dummy = ib->gpu_addr + (ib_size_dw * 4);
 
ib->length_dw = 0;
ib->ptr[ib->length_dw++] = 0x0018;
-- 
2.20.1

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[PATCH 2/2] drm/amdgpu/uvd7: fix allocation size in enc ring test

[Alex Deucher]

We need to allocate a large enough buffer for the
session info, otherwise the IB test can overwrite
other memory.

Bug: https://bugzilla.kernel.org/show_bug.cgi?id=204241
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c 
b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 01f658fa72c6..0ce6a1e7ff79 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -223,12 +223,12 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring 
*ring, uint32_t handle
uint64_t dummy;
int i, r;
 
-   r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, );
+   r = amdgpu_job_alloc_with_ib(ring->adev, (ib_size_dw * 4) + 1024, );
if (r)
return r;
 
ib = >ibs[0];
-   dummy = ib->gpu_addr + 1024;
+   dummy = ib->gpu_addr + (ib_size_dw * 4);
 
ib->length_dw = 0;
ib->ptr[ib->length_dw++] = 0x0018;
@@ -284,12 +284,12 @@ static int uvd_v7_0_enc_get_destroy_msg(struct 
amdgpu_ring *ring, uint32_t handl
uint64_t dummy;
int i, r;
 
-   r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, );
+   r = amdgpu_job_alloc_with_ib(ring->adev, (ib_size_dw * 4) + 1024, );
if (r)
return r;
 
ib = >ibs[0];
-   dummy = ib->gpu_addr + 1024;
+   dummy = ib->gpu_addr + (ib_size_dw * 4);
 
ib->length_dw = 0;
ib->ptr[ib->length_dw++] = 0x0018;
-- 
2.20.1

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Re: [PATCH 5/6] drm/amdgpu/dm/mst: Report possible_crtcs incorrectly, for now

[Lyude Paul]

a little late but: i915 does have this hack (or rather-possible_crtcs with MST
in i915 has been broken for a while and got fixed, but had to get reverted
because of this issue), it's where this originally came from.

On Wed, 2019-10-09 at 17:01 +0200, Daniel Vetter wrote:
> On Fri, Sep 27, 2019 at 11:27:41AM -0400, Sean Paul wrote:
> > On Thu, Sep 26, 2019 at 06:51:07PM -0400, Lyude Paul wrote:
> > > This commit is seperate from the previous one to make it easier to
> > > revert in the future. Basically, there's multiple userspace applications
> > > that interpret possible_crtcs very wrong:
> > > 
> > > https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
> > > https://gitlab.gnome.org/GNOME/mutter/issues/759
> > > 
> > > While work is ongoing to fix these issues in userspace, we need to
> > > report ->possible_crtcs incorrectly for now in order to avoid
> > > introducing a regression in in userspace. Once these issues get fixed,
> > > this commit should be reverted.
> > > 
> > > Signed-off-by: Lyude Paul 
> > > Cc: Ville Syrjälä 
> > > ---
> > >  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++
> > >  1 file changed, 11 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > index b404f1ae6df7..fe8ac801d7a5 100644
> > > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> > > @@ -4807,6 +4807,17 @@ static int amdgpu_dm_crtc_init(struct
> > > amdgpu_display_manager *dm,
> > >   if (!acrtc->mst_encoder)
> > >   goto fail;
> > >  
> > > + /*
> > > +  * FIXME: This is a hack to workaround the following issues:
> > > +  *
> > > +  * https://gitlab.gnome.org/GNOME/mutter/issues/759
> > > +  * https://gitlab.freedesktop.org/xorg/xserver/merge_requests/277
> > > +  *
> > > +  * One these issues are closed, this should be removed
> > 
> > Even when these issues are closed, we'll still be introducing a regression
> > if we
> > revert this change. Time for actually_possible_crtcs? :)
> > 
> > You also might want to briefly explain the u/s bug in case the links go
> > sour.
> > 
> > > +  */
> > > + acrtc->mst_encoder->base.possible_crtcs =
> > > + amdgpu_dm_get_encoder_crtc_mask(dm->adev);
> > 
> > Why don't we put this hack in amdgpu_dm_dp_create_fake_mst_encoder()?
> 
> If we don't have the same hack for i915 mst I think we shouldn't merge
> this ... broken userspace is broken.
> -Daniel
-- 
Cheers,
Lyude Paul

RE: [PATCH 01/29] drm/amd/display: update register field access mechanism

[Li, Roman]

Series is
Reviewed-by: Roman Li 

-Original Message-
From: amd-gfx  On Behalf Of Bhawanpreet 
Lakha
Sent: Friday, October 11, 2019 3:53 PM
To: amd-gfx@lists.freedesktop.org
Cc: Berthe, Abdoulaye 
Subject: [PATCH 01/29] drm/amd/display: update register field access mechanism

From: abdoulaye berthe 

1-add timeout length and multiplier fields to aux_control1 register 2-update 
access mechanism from macro constructed name to uint32_t defined addresses.
3-define registers and field per asic family

Signed-off-by: abdoulaye berthe 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c  |  11 +-  
drivers/gpu/drm/amd/display/dc/dce/dce_aux.h  | 175 +-
 .../amd/display/dc/dce100/dce100_resource.c   |  12 +-
 .../amd/display/dc/dce110/dce110_resource.c   |  12 +-
 .../amd/display/dc/dce112/dce112_resource.c   |  12 +-
 .../amd/display/dc/dce120/dce120_resource.c   |  12 +-
 .../drm/amd/display/dc/dce80/dce80_resource.c |  12 +-  
.../drm/amd/display/dc/dcn10/dcn10_resource.c |  12 +-  
.../drm/amd/display/dc/dcn20/dcn20_resource.c |  13 +-  
.../drm/amd/display/dc/dcn21/dcn21_resource.c |  12 +-
 10 files changed, 271 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 48a0e4ae80c2..de233270e3d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -42,6 +42,10 @@
 
 #include "reg_helper.h"
 
+#undef FN
+#define FN(reg_name, field_name) \
+   aux110->shift->field_name, aux110->mask->field_name
+
 #define FROM_AUX_ENGINE(ptr) \
container_of((ptr), struct aux_engine_dce110, base)
 
@@ -414,11 +418,14 @@ void dce110_engine_destroy(struct dce_aux **engine)
*engine = NULL;
 
 }
+
 struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 
*aux_engine110,
struct dc_context *ctx,
uint32_t inst,
uint32_t timeout_period,
-   const struct dce110_aux_registers *regs)
+   const struct dce110_aux_registers *regs,
+   const struct dce110_aux_registers_mask *mask,
+   const struct dce110_aux_registers_shift *shift)
 {
aux_engine110->base.ddc = NULL;
aux_engine110->base.ctx = ctx;
@@ -428,6 +435,8 @@ struct dce_aux *dce110_aux_engine_construct(struct 
aux_engine_dce110 *aux_engine
aux_engine110->timeout_period = timeout_period;
aux_engine110->regs = regs;
 
+   aux_engine110->mask = mask;
+   aux_engine110->shift = shift;
return _engine110->base;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
index ed7fec8fe253..717378502e9d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
@@ -29,6 +29,7 @@
 #include "i2caux_interface.h"
 #include "inc/hw/aux_engine.h"
 
+
 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 #define AUX_COMMON_REG_LIST0(id)\
SRI(AUX_CONTROL, DP_AUX, id), \
@@ -36,6 +37,7 @@
SRI(AUX_SW_DATA, DP_AUX, id), \
SRI(AUX_SW_CONTROL, DP_AUX, id), \
SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
+   SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \
SRI(AUX_SW_STATUS, DP_AUX, id)
 #endif
 
@@ -55,6 +57,7 @@ struct dce110_aux_registers {
uint32_t AUX_SW_DATA;
uint32_t AUX_SW_CONTROL;
uint32_t AUX_INTERRUPT_CONTROL;
+   uint32_t AUX_DPHY_RX_CONTROL1;
uint32_t AUX_SW_STATUS;
uint32_t AUXN_IMPCAL;
uint32_t AUXP_IMPCAL;
@@ -62,6 +65,156 @@ struct dce110_aux_registers {
uint32_t AUX_RESET_MASK;
 };
 
+#define DCE_AUX_REG_FIELD_LIST(type)\
+   type AUX_EN;\
+   type AUX_RESET;\
+   type AUX_RESET_DONE;\
+   type AUX_REG_RW_CNTL_STATUS;\
+   type AUX_SW_USE_AUX_REG_REQ;\
+   type AUX_SW_DONE_USING_AUX_REG;\
+   type AUX_SW_AUTOINCREMENT_DISABLE;\
+   type AUX_SW_DATA_RW;\
+   type AUX_SW_INDEX;\
+   type AUX_SW_GO;\
+   type AUX_SW_DATA;\
+   type AUX_SW_REPLY_BYTE_COUNT;\
+   type AUX_SW_DONE;\
+   type AUX_SW_DONE_ACK;\
+   type AUXN_IMPCAL_ENABLE;\
+   type AUXP_IMPCAL_ENABLE;\
+   type AUXN_IMPCAL_OVERRIDE_ENABLE;\
+   type AUXP_IMPCAL_OVERRIDE_ENABLE;\
+   type AUX_RX_TIMEOUT_LEN;\
+   type AUX_RX_TIMEOUT_LEN_MUL;\
+   type AUXN_CALOUT_ERROR_AK;\
+   type AUXP_CALOUT_ERROR_AK;\
+   type AUX_SW_START_DELAY;\
+   type AUX_SW_WR_BYTES
+
+#define DCE10_AUX_MASK_SH_LIST(mask_sh)\
+   AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
+   AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
+   AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
+   AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
+   AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
+   AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
+   AUX_SF(AUX_SW_CONTROL, 

[PATCH 18/29] drm/amd/display: update renoir bounding box and res_caps

[Bhawanpreet Lakha]

The values for bounding box and res_caps were incorrect. So
Fix them

Signed-off-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/dc/dcn21/dcn21_resource.c | 24 ++-
 1 file changed, 13 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 5e15f800a9f1..002e7fb67068 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -82,6 +82,7 @@
 
 
 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
+   .odm_capable = 1,
.gpuvm_enable = 0,
.hostvm_enable = 0,
.gpuvm_max_page_table_levels = 1,
@@ -203,11 +204,11 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
.state = 4,
.dcfclk_mhz = 810.0,
.fabricclk_mhz = 1600.0,
-   .dispclk_mhz = 1015.0,
-   .dppclk_mhz = 1015.0,
-   .phyclk_mhz = 810.0,
+   .dispclk_mhz = 1395.0,
+   .dppclk_mhz = 1285.0,
+   .phyclk_mhz = 1325.0,
.socclk_mhz = 953.0,
-   .dscclk_mhz = 318.334,
+   .dscclk_mhz = 489.0,
.dram_speed_mts = 4266.0,
},
/*Extra state, no dispclk ramping*/
@@ -215,18 +216,18 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
.state = 5,
.dcfclk_mhz = 810.0,
.fabricclk_mhz = 1600.0,
-   .dispclk_mhz = 1015.0,
-   .dppclk_mhz = 1015.0,
-   .phyclk_mhz = 810.0,
+   .dispclk_mhz = 1395.0,
+   .dppclk_mhz = 1285.0,
+   .phyclk_mhz = 1325.0,
.socclk_mhz = 953.0,
-   .dscclk_mhz = 318.334,
+   .dscclk_mhz = 489.0,
.dram_speed_mts = 4266.0,
},
 
},
 
-   .sr_exit_time_us = 9.0,
-   .sr_enter_plus_exit_time_us = 11.0,
+   .sr_exit_time_us = 12.5,
+   .sr_enter_plus_exit_time_us = 17.0,
.urgent_latency_us = 4.0,
.urgent_latency_pixel_data_only_us = 4.0,
.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
@@ -764,6 +765,7 @@ static const struct resource_caps res_cap_rn = {
.num_pll = 5,  // maybe 3 because the last two used for USB-c
.num_dwb = 1,
.num_ddc = 5,
+   .num_vmid = 1,
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
.num_dsc = 3,
 #endif
@@ -833,7 +835,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_dcc = DCC_ENABLE,
.vsr_support = true,
.performance_trace = false,
-   .max_downscale_src_width = 5120,/*upto 5K*/
+   .max_downscale_src_width = 3840,
.disable_pplib_wm_range = false,
.scl_reset_length10 = true,
.sanity_checks = true,
-- 
2.17.1

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[PATCH 14/29] drm/amd/display: use dcn10 version of program tiling on Renoir

[Bhawanpreet Lakha]

From: Eric Yang 

[Why]
Renoir is gfx9, same as dcn10, not dcn20.

Signed-off-by: Eric Yang 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
index a00af513aa2b..2f5a5867e674 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c
@@ -22,6 +22,8 @@
  * Authors: AMD
  *
  */
+
+#include "dcn10/dcn10_hubp.h"
 #include "dcn21_hubp.h"
 
 #include "dm_services.h"
@@ -202,7 +204,7 @@ static struct hubp_funcs dcn21_hubp_funcs = {
.hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
.hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
.hubp_program_surface_flip_and_addr = 
hubp2_program_surface_flip_and_addr,
-   .hubp_program_surface_config = hubp2_program_surface_config,
+   .hubp_program_surface_config = hubp1_program_surface_config,
.hubp_is_flip_pending = hubp1_is_flip_pending,
.hubp_setup = hubp21_setup,
.hubp_setup_interdependent = hubp2_setup_interdependent,
-- 
2.17.1

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[PATCH 25/29] drm/amd/display: fix header for RN clk mgr

[Bhawanpreet Lakha]

From: joseph gravenor 

[why]
Should always MP0_BASE for any register definition from MP per-IP header files.
I belive the reason the linux version of MP1_BASE works is The 0th element of 
the 0th table
of that is identical to the corrisponding value of MP0_BASE in the renoir 
offset header file.
The reason we should only use MP0_BASE is There is only one set of per-IP 
headers MP
that includes all register definitions related to SMU IP block. This IP 
includes MP0, MP1, MP2
and  an ecryption engine that can be used only by MP0. As a result all register 
definitions from
MP file should be based only on MP0_BASE data.

[How]
Change MP1_BASE to MP0_BASE

Signed-off-by: joseph gravenor 
Acked-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git 
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index 8e860f567d5c..db28e91adb3d 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -33,7 +33,7 @@
 #include "mp/mp_12_0_0_sh_mask.h"
 
 #define REG(reg_name) \
-   (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## 
reg_name)
+   (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## 
reg_name)
 
 #define FN(reg_name, field) \
FD(reg_name##__##field)
-- 
2.17.1

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[PATCH 04/29] drm/amd/display: Add DP_DPHY_INTERNAL_CTR regs

[Bhawanpreet Lakha]

Signed-off-by: Bhawanpreet Lakha 
---
 .../drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h| 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h 
b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
index be4249adb356..eddf83ec1c39 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h
@@ -9859,6 +9859,8 @@
 #define mmDP0_DP_STEER_FIFO_BASE_IDX   
2
 #define mmDP0_DP_MSA_MISC  
0x210e
 #define mmDP0_DP_MSA_MISC_BASE_IDX 
2
+#define mmDP0_DP_DPHY_INTERNAL_CTRL
0x210f
+#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX   
2
 #define mmDP0_DP_VID_TIMING
0x2110
 #define mmDP0_DP_VID_TIMING_BASE_IDX   
2
 #define mmDP0_DP_VID_N 
0x2111
@@ -10187,6 +10189,8 @@
 #define mmDP1_DP_STEER_FIFO_BASE_IDX   
2
 #define mmDP1_DP_MSA_MISC  
0x220e
 #define mmDP1_DP_MSA_MISC_BASE_IDX 
2
+#define mmDP1_DP_DPHY_INTERNAL_CTRL
0x220f
+#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX   
2
 #define mmDP1_DP_VID_TIMING
0x2210
 #define mmDP1_DP_VID_TIMING_BASE_IDX   
2
 #define mmDP1_DP_VID_N 
0x2211
@@ -10515,6 +10519,8 @@
 #define mmDP2_DP_STEER_FIFO_BASE_IDX   
2
 #define mmDP2_DP_MSA_MISC  
0x230e
 #define mmDP2_DP_MSA_MISC_BASE_IDX 
2
+#define mmDP2_DP_DPHY_INTERNAL_CTRL
0x230f
+#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX   
2
 #define mmDP2_DP_VID_TIMING
0x2310
 #define mmDP2_DP_VID_TIMING_BASE_IDX   
2
 #define mmDP2_DP_VID_N 
0x2311
@@ -10843,6 +10849,8 @@
 #define mmDP3_DP_STEER_FIFO_BASE_IDX   
2
 #define mmDP3_DP_MSA_MISC  
0x240e
 #define mmDP3_DP_MSA_MISC_BASE_IDX 
2
+#define mmDP3_DP_DPHY_INTERNAL_CTRL
0x240f
+#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX   
2
 #define mmDP3_DP_VID_TIMING
0x2410
 #define mmDP3_DP_VID_TIMING_BASE_IDX   
2
 #define mmDP3_DP_VID_N 
0x2411
@@ -11171,6 +11179,8 @@
 #define mmDP4_DP_STEER_FIFO_BASE_IDX   
2
 #define mmDP4_DP_MSA_MISC  
0x250e
 #define mmDP4_DP_MSA_MISC_BASE_IDX 
2
+#define mmDP4_DP_DPHY_INTERNAL_CTRL
0x250f
+#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX   
2
 #define mmDP4_DP_VID_TIMING
0x2510
 #define mmDP4_DP_VID_TIMING_BASE_IDX   
2
 #define mmDP4_DP_VID_N 
0x2511
-- 
2.17.1

[PATCH 27/29] drm/amd/display: use requested_dispclk_khz instead of clk

[Bhawanpreet Lakha]

Use requested_dispclk_khz / 1000 directly

Signed-off-by: Bhawanpreet Lakha 
---
 .../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c | 13 ++---
 1 file changed, 2 insertions(+), 11 deletions(-)

diff --git 
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index 2650776acbc3..5647fcf10717 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -84,16 +84,12 @@ int rn_vbios_smu_set_dispclk(struct clk_mgr_internal 
*clk_mgr, int requested_dis
int actual_dispclk_set_mhz = -1;
struct dc *core_dc = clk_mgr->base.ctx->dc;
struct dmcu *dmcu = core_dc->res_pool->dmcu;
-   uint32_t clk = requested_dispclk_khz / 1000;
-
-   if (clk <= 100)
-   clk = 101;
 
/*  Unit of SMU msg parameter is Mhz */
actual_dispclk_set_mhz = rn_vbios_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDispclkFreq,
-   clk);
+   requested_dispclk_khz / 1000);
 
if (!IS_FPGA_MAXIMUS_DC(core_dc->ctx->dce_environment)) {
if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
@@ -162,15 +158,10 @@ int rn_vbios_smu_set_dppclk(struct clk_mgr_internal 
*clk_mgr, int requested_dpp_
 {
int actual_dppclk_set_mhz = -1;
 
-   uint32_t clk = requested_dpp_khz / 1000;
-
-   if (clk <= 100)
-   clk = 101;
-
actual_dppclk_set_mhz = rn_vbios_smu_send_msg_with_param(
clk_mgr,
VBIOSSMC_MSG_SetDppclkFreq,
-   clk);
+   requested_dpp_khz / 1000);
 
return actual_dppclk_set_mhz * 1000;
 }
-- 
2.17.1

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[PATCH 21/29] drm/amd/display: update odm mode validation to be in line with policy

[Bhawanpreet Lakha]

From: Dmytro Laktyushkin 

Previously 8k30 worked with dsc and odm combine due to a workaround that ran
the formula a second time with dsc support enable should dsc validation fail.
This worked when clocks were low enough for formula to enable odm to lower
voltage, however now broke due to increased clocks.

This change updates the ODM combine policy within the formula to properly
reflect our current policy within DC, only enabling ODM when we have to, as
well as adding a check for viewport width when dsc is enabled.

As a side effect the redundant call to dml when odm is required is now
unnecessary.

Signed-off-by: Dmytro Laktyushkin 
Acked-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c   | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index 3b6ed60dcd35..fd707e7459b5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -65,6 +65,7 @@ typedef struct {
 
 #define BPP_INVALID 0
 #define BPP_BLENDED_PIPE 0x
+#define DCN21_MAX_DSC_IMAGE_WIDTH 5184
 
 static void DisplayPipeConfiguration(struct display_mode_lib *mode_lib);
 static void 
DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation(
@@ -3936,6 +3937,10 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
mode_lib->vba.MaximumSwathWidthInLineBuffer);
}
for (i = 0; i <= mode_lib->vba.soc.num_states; i++) {
+   double MaxMaxDispclkRoundedDown = RoundToDFSGranularityDown(
+   mode_lib->vba.MaxDispclk[mode_lib->vba.soc.num_states],
+   mode_lib->vba.DISPCLKDPPCLKVCOSpeed);
+
for (j = 0; j < 2; j++) {
mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity = 
RoundToDFSGranularityDown(
mode_lib->vba.MaxDispclk[i],
@@ -3965,7 +3970,9 @@ void dml21_ModeSupportAndSystemConfigurationFull(struct 
display_mode_lib *mode_l
&& i == 
mode_lib->vba.soc.num_states)

mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine = mode_lib->vba.PixelClock[k] 
/ 2
* (1 + 
mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
-   if (mode_lib->vba.ODMCapability == false || 
mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine <= 
mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
+   if (mode_lib->vba.ODMCapability == false ||
+   
(locals->PlaneRequiredDISPCLKWithoutODMCombine <= MaxMaxDispclkRoundedDown
+   && 
(!locals->DSCEnabled[k] || locals->HActive[k] <= DCN21_MAX_DSC_IMAGE_WIDTH))) {
locals->ODMCombineEnablePerState[i][k] 
= false;
mode_lib->vba.PlaneRequiredDISPCLK = 
mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
} else {
-- 
2.17.1

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[PATCH 22/29] drm/amd/display: handle "18" case in TruncToValidBPP

[Bhawanpreet Lakha]

Handle 18 DecimalBPP like other cases

Signed-off-by: Bhawanpreet Lakha 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index fd707e7459b5..ba77957aefe3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -3380,6 +3380,8 @@ static unsigned int TruncToValidBPP(
return 30;
else if (DecimalBPP >= 24 && (DesiredBPP == 0 || 
DesiredBPP == 24))
return 24;
+   else if (DecimalBPP >= 18 && (DesiredBPP == 0 || 
DesiredBPP == 18))
+   return 18;
else
return BPP_INVALID;
}
-- 
2.17.1

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[PATCH 08/29] drm/amd/display: add REFCYC_PER_TRIP_TO_MEMORY programming

[Bhawanpreet Lakha]

it allows us to do urgent latency programming

Signed-off-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/dc/dcn20/dcn20_resource.c | 16 
 .../drm/amd/display/dc/dcn21/dcn21_hubbub.c   | 39 +--
 .../drm/amd/display/dc/dcn21/dcn21_hubbub.h   | 17 
 .../gpu/drm/amd/display/dc/inc/hw/mem_input.h |  1 +
 4 files changed, 69 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 9cc6797e3860..086d1bc0d0a5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2573,6 +2573,10 @@ void dcn20_calculate_wm(
context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = 
get_wm_stutter_exit(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = 
get_wm_dram_clock_change(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = 
get_wm_memory_trip(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+   context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = 
get_fraction_of_urgent_bandwidth(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
+   context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = 
get_fraction_of_urgent_bandwidth_imm_flip(>bw_ctx.dml, pipes, 
pipe_cnt) * 1000;
+#endif
 
if (vlevel < 2) {
pipes[0].clks_cfg.voltage = 2;
@@ -2584,6 +2588,10 @@ void dcn20_calculate_wm(
context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = 
get_wm_stutter_exit(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = 
get_wm_dram_clock_change(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = 
get_wm_memory_trip(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+   context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = 
get_fraction_of_urgent_bandwidth(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
+   context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = 
get_fraction_of_urgent_bandwidth_imm_flip(>bw_ctx.dml, pipes, 
pipe_cnt) * 1000;
+#endif
 
if (vlevel < 3) {
pipes[0].clks_cfg.voltage = 3;
@@ -2595,6 +2603,10 @@ void dcn20_calculate_wm(
context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = 
get_wm_stutter_exit(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = 
get_wm_dram_clock_change(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = 
get_wm_memory_trip(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+   context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = 
get_fraction_of_urgent_bandwidth(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
+   context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = 
get_fraction_of_urgent_bandwidth_imm_flip(>bw_ctx.dml, pipes, 
pipe_cnt) * 1000;
+#endif
 
pipes[0].clks_cfg.voltage = vlevel;
pipes[0].clks_cfg.dcfclk_mhz = 
context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
@@ -2604,6 +2616,10 @@ void dcn20_calculate_wm(
context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = 
get_wm_stutter_exit(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 
get_wm_dram_clock_change(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = 
get_wm_memory_trip(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+   context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = 
get_fraction_of_urgent_bandwidth(>bw_ctx.dml, pipes, pipe_cnt) * 1000;
+   context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = 
get_fraction_of_urgent_bandwidth_imm_flip(>bw_ctx.dml, pipes, 
pipe_cnt) * 1000;
+#endif
 }
 
 void dcn20_calculate_dlg_params(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
index d1266741763b..8e7e79f44272 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
@@ -97,7 +97,7 @@ void dcn21_dchvm_init(struct hubbub *hubbub)
REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
 }
 
-static int hubbub21_init_dchub(struct hubbub *hubbub,
+int hubbub21_init_dchub(struct hubbub *hubbub,
struct dcn_hubbub_phys_addr_config *pa_config)
 {
struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
@@ -120,7 +120,7 @@ static int hubbub21_init_dchub(struct hubbub *hubbub,
return NUM_VMID;
 }
 
-static void hubbub21_program_urgent_watermarks(
+void hubbub21_program_urgent_watermarks(
struct hubbub *hubbub,
struct 

[PATCH 13/29] drm/amd/display: initialize RN gpuvm context programming function

[Bhawanpreet Lakha]

From: Dmytro Laktyushkin 

Renoir can use vm contexes as long as HOSTVM is off so
this should be initialized.

Signed-off-by: Dmytro Laktyushkin 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
index 2232ccf14bdd..44f64a8e33f1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
@@ -628,7 +628,7 @@ void hubbub21_apply_DEDCN21_147_wa(struct hubbub *hubbub)
 static const struct hubbub_funcs hubbub21_funcs = {
.update_dchub = hubbub2_update_dchub,
.init_dchub_sys_ctx = hubbub21_init_dchub,
-   .init_vm_ctx = NULL,
+   .init_vm_ctx = hubbub2_init_vm_ctx,
.dcc_support_swizzle = hubbub2_dcc_support_swizzle,
.dcc_support_pixel_format = hubbub2_dcc_support_pixel_format,
.get_dcc_compression_cap = hubbub2_get_dcc_compression_cap,
-- 
2.17.1

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[PATCH 00/29] Renoir DC Patches v2

[Bhawanpreet Lakha]

Hi all,

There was a delta betwwen internal dcn21 code and upstream dcn21 code.
These changes bring them inline.


Summary of Changes
*Add RN registors
*Add dcn12 hwseq and link_encoder
*RN specific fixes
*aux timeout support
*bounding box changes

v2:
*add usb-c functions
*compile fix and check lightup on renoir
*fix aux timeout regression

new patches
  drm/amd/display: handle dp is usb-c
  drm/amd/display: null check pp_smu clock table before using it
  drm/amd/display: disable ext aux support for vega



Bhawanpreet Lakha (14):
  drm/amd/display: Add DP_DPHY_INTERNAL_CTR regs
  drm/amd/display: Add DCN_BASE regs
  drm/amd/display: Add renoir hw_seq
  drm/amd/display: create dcn21_link_encoder files
  drm/amd/display: add REFCYC_PER_TRIP_TO_MEMORY programming
  drm/amd/display: fix incorrect page table address for renoir
  drm/amd/display: add detile buffer size for renoir
  drm/amd/display: update dcn21 hubbub registers
  drm/amd/display: update renoir bounding box and res_caps
  drm/amd/display: change PP_SM defs to 8
  drm/amd/display: handle "18" case in TruncToValidBPP
  drm/amd/display: use requested_dispclk_khz instead of clk
  drm/amd/display: handle dp is usb-c
  drm/amd/display: null check pp_smu clock table before using it

Dmytro Laktyushkin (4):
  drm/amd/display: enable hostvm based on roimmu active for dcn2.1
  drm/amd/display: initialize RN gpuvm context programming function
  drm/amd/display: correct dcn21 NUM_VMID to 16
  drm/amd/display: update odm mode validation to be in line with policy

Eric Yang (2):
  drm/amd/display: use dcn10 version of program tiling on Renoir
  drm/amd/display: add sanity check for clk table from smu

Lewis Huang (3):
  drm/amd/display: move the bounding box patch before calculate wm
  drm/amd/display: Temporary workaround to toggle watermark setting
  drm/amd/display: enable smu set dcfclk

Michael Strauss (1):
  drm/amd/display: Fix rn audio playback and video playback speed

Roman Li (1):
  drm/amd/display: disable ext aux support for vega

Sung Lee (1):
  drm/amd/display: add dummy functions to smu for Renoir Silicon Diags

abdoulaye berthe (2):
  drm/amd/display: update register field access mechanism
  drm/amd/display: configurable aux timeout support

joseph gravenor (1):
  drm/amd/display: fix header for RN clk mgr

 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |  25 +-
 .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c   |  19 +-
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |  14 +
 drivers/gpu/drm/amd/display/dc/dc.h   |   2 +
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c  |  82 ++-
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h  | 187 ++-
 .../gpu/drm/amd/display/dc/dce/dce_hwseq.h|   1 +
 .../amd/display/dc/dce100/dce100_resource.c   |  15 +-
 .../amd/display/dc/dce110/dce110_resource.c   |  14 +-
 .../amd/display/dc/dce112/dce112_resource.c   |  15 +-
 .../amd/display/dc/dce120/dce120_resource.c   |  15 +-
 .../drm/amd/display/dc/dce80/dce80_resource.c |  14 +-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   4 +
 .../amd/display/dc/dcn10/dcn10_link_encoder.h |  49 +-
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |  15 +-
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|   4 +
 .../amd/display/dc/dcn20/dcn20_link_encoder.h |   7 +
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  31 +-
 drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   2 +-
 .../drm/amd/display/dc/dcn21/dcn21_hubbub.c   | 116 -
 .../drm/amd/display/dc/dcn21/dcn21_hubbub.h   |  34 +-
 .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c |   4 +-
 .../drm/amd/display/dc/dcn21/dcn21_hwseq.c| 122 +
 .../drm/amd/display/dc/dcn21/dcn21_hwseq.h|  33 ++
 .../amd/display/dc/dcn21/dcn21_link_encoder.c | 470 ++
 .../amd/display/dc/dcn21/dcn21_link_encoder.h |  61 +++
 .../drm/amd/display/dc/dcn21/dcn21_resource.c | 269 --
 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h|   6 +-
 .../dc/dml/dcn21/display_mode_vba_21.c|  11 +-
 .../gpu/drm/amd/display/dc/inc/dc_link_ddc.h  |   3 +
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |   2 +
 .../drm/amd/display/dc/inc/hw/aux_engine.h|   3 +
 .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h  |   1 +
 .../gpu/drm/amd/display/dc/inc/hw/mem_input.h |   1 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   3 +
 .../include/asic_reg/dcn/dcn_2_1_0_offset.h   |  10 +
 .../gpu/drm/amd/include/renoir_ip_offset.h|  34 ++
 37 files changed, 1572 insertions(+), 126 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h

-- 
2.17.1

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[PATCH 09/29] drm/amd/display: move the bounding box patch before calculate wm

[Bhawanpreet Lakha]

From: Lewis Huang 

[why]
driver updateis the dcn2_1_soc into dml before call update_bw_bounding_box

[How]
Move the patch function before calculate wm.

Signed-off-by: Lewis Huang 
Signed-off-by: joseph graveno 
Acked-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/dc/dcn21/dcn21_resource.c | 25 +++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index ddf52e260ed6..e39961d0f24e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1007,6 +1007,29 @@ static void calculate_wm_set_for_vlevel(
 
 }
 
+static void patch_bounding_box(struct dc *dc, struct 
_vcs_dpi_soc_bounding_box_st *bb)
+{
+   kernel_fpu_begin();
+   if (dc->bb_overrides.sr_exit_time_ns) {
+   bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
+   }
+
+   if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
+   bb->sr_enter_plus_exit_time_us =
+   dc->bb_overrides.sr_enter_plus_exit_time_ns / 
1000.0;
+   }
+
+   if (dc->bb_overrides.urgent_latency_ns) {
+   bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 
1000.0;
+   }
+
+   if (dc->bb_overrides.dram_clock_change_latency_ns) {
+   bb->dram_clock_change_latency_us =
+   dc->bb_overrides.dram_clock_change_latency_ns / 
1000.0;
+   }
+   kernel_fpu_end();
+}
+
 void dcn21_calculate_wm(
struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes,
@@ -1021,6 +1044,8 @@ void dcn21_calculate_wm(
 
ASSERT(bw_params);
 
+   patch_bounding_box(dc, >bw_ctx.dml.soc);
+
for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; 
i++) {
if (!context->res_ctx.pipe_ctx[i].stream)
continue;
-- 
2.17.1

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[PATCH 15/29] drm/amd/display: correct dcn21 NUM_VMID to 16

[Bhawanpreet Lakha]

From: Dmytro Laktyushkin 

1 vmid limitation only exists for HOSTVM which is a custom
use case anyway.

Signed-off-by: Dmytro Laktyushkin 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
index 44f64a8e33f1..aeb5de6f4530 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
@@ -52,7 +52,7 @@
 #ifdef NUM_VMID
 #undef NUM_VMID
 #endif
-#define NUM_VMID 1
+#define NUM_VMID 16
 
 static uint32_t convert_and_clamp(
uint32_t wm_ns,
-- 
2.17.1

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[PATCH 02/29] drm/amd/display: configurable aux timeout support

[Bhawanpreet Lakha]

From: abdoulaye berthe 

[Description]
1-add configurable timeout support to aux engine.
2-add timeout support field to dc_caps
3-add reg_key to override extended timeout support

Signed-off-by: abdoulaye berthe 
Acked-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 14 
 drivers/gpu/drm/amd/display/dc/dc.h   |  2 +
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c  | 73 ++-
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h  | 16 +++-
 .../amd/display/dc/dce100/dce100_resource.c   |  5 +-
 .../amd/display/dc/dce110/dce110_resource.c   |  4 +-
 .../amd/display/dc/dce112/dce112_resource.c   |  5 +-
 .../amd/display/dc/dce120/dce120_resource.c   |  5 +-
 .../drm/amd/display/dc/dce80/dce80_resource.c |  4 +-
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |  5 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  4 +-
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  4 +-
 .../gpu/drm/amd/display/dc/inc/dc_link_ddc.h  |  3 +
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  2 +
 .../drm/amd/display/dc/inc/hw/aux_engine.h|  3 +
 15 files changed, 132 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 57fb0574f198..9a56f110bbd1 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -634,6 +634,20 @@ bool dc_link_aux_transfer_with_retries(struct ddc_service 
*ddc,
return dce_aux_transfer_with_retries(ddc, payload);
 }
 
+
+enum dc_status dc_link_aux_configure_timeout(struct ddc_service *ddc,
+   uint32_t timeout)
+{
+   enum dc_status status = DC_OK;
+   struct ddc *ddc_pin = ddc->ddc_pin;
+
+   if 
(ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout
 == NULL)
+   return DC_ERROR_UNEXPECTED;
+   if 
(!ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc,
 timeout))
+   status = DC_ERROR_UNEXPECTED;
+   return status;
+}
+
 /*test only function*/
 void dal_ddc_service_set_ddc_pin(
struct ddc_service *ddc_service,
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 41e366f59f10..5967106826ca 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -111,6 +111,7 @@ struct dc_caps {
bool force_dp_tps4_for_cp2520;
bool disable_dp_clk_share;
bool psp_setup_panel_mode;
+   bool extended_aux_timeout_support;
 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
bool hw_3d_lut;
 #endif
@@ -220,6 +221,7 @@ struct dc_config {
bool power_down_display_on_boot;
bool edp_not_connected;
bool forced_clocks;
+   bool disable_extended_timeout_support; // Used to disable extended 
timeout and lttpr feature as well
bool multi_mon_pp_mclk_switch;
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index de233270e3d5..976bd4987a28 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -59,6 +59,14 @@ enum {
AUX_TIMED_OUT_RETRY_COUNTER = 2,
AUX_DEFER_RETRY_COUNTER = 6
 };
+
+#define TIME_OUT_INCREMENT  1016
+#define TIME_OUT_MULTIPLIER_8  8
+#define TIME_OUT_MULTIPLIER_16  16
+#define TIME_OUT_MULTIPLIER_32  32
+#define TIME_OUT_MULTIPLIER_64  64
+#define MAX_TIMEOUT_LENGTH  127
+
 static void release_engine(
struct dce_aux *engine)
 {
@@ -202,7 +210,7 @@ static void submit_channel_request(
REG_UPDATE(AUX_INTERRUPT_CONTROL, AUX_SW_DONE_ACK, 1);
 
REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 0,
-   10, aux110->timeout_period/10);
+   10, aux110->polling_timeout_period/10);
 
/* set the delay and the number of bytes to write */
 
@@ -331,7 +339,7 @@ static enum aux_channel_operation_result get_channel_status(
 
/* poll to make sure that SW_DONE is asserted */
REG_WAIT(AUX_SW_STATUS, AUX_SW_DONE, 1,
-   10, aux110->timeout_period/10);
+   10, aux110->polling_timeout_period/10);
 
value = REG_READ(AUX_SW_STATUS);
/* in case HPD is LOW, exit AUX transaction */
@@ -419,24 +427,81 @@ void dce110_engine_destroy(struct dce_aux **engine)
 
 }
 
+static bool dce_aux_configure_timeout(struct ddc_service *ddc,
+   uint32_t timeout_in_us)
+{
+   uint32_t multiplier = 0;
+   uint32_t length = 0;
+   uint32_t timeout = 0;
+   struct ddc *ddc_pin = ddc->ddc_pin;
+   struct dce_aux *aux_engine = 
ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en];
+   struct aux_engine_dce110 *aux110 = FROM_AUX_ENGINE(aux_engine);
+
+   /* 1-Update polling timeout period */
+   aux110->polling_timeout_period = timeout_in_us * 

[PATCH 12/29] drm/amd/display: Temporary workaround to toggle watermark setting

[Bhawanpreet Lakha]

From: Lewis Huang 

[Why]
Watermarks not propagated to DCHUBP after it is powered on

[How]
Add temoprary function apply_DEDCN21_147_wa to apply wm settings for Renoir

Signed-off-by: Lewis Huang 
Reviewed-by: Tony Cheng 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c| 4 
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c   | 9 +
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h  | 1 +
 4 files changed, 15 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index ce2530509e12..6229a8ca0013 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1533,6 +1533,10 @@ static void dcn20_program_front_end_for_ctx(
msleep(1);
}
}
+
+   /* WA to apply WM setting*/
+   if (dc->hwseq->wa.DEGVIDCN21)
+   
dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
 }
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
index fdfbdeb32459..2232ccf14bdd 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
@@ -616,6 +616,14 @@ void hubbub21_wm_read_state(struct hubbub *hubbub,
DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, 
>dram_clk_chanage);
 }
 
+void hubbub21_apply_DEDCN21_147_wa(struct hubbub *hubbub)
+{
+   struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
+   uint32_t prog_wm_value;
+
+   prog_wm_value = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
+   REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, prog_wm_value);
+}
 
 static const struct hubbub_funcs hubbub21_funcs = {
.update_dchub = hubbub2_update_dchub,
@@ -627,6 +635,7 @@ static const struct hubbub_funcs hubbub21_funcs = {
.wm_read_state = hubbub21_wm_read_state,
.get_dchub_ref_freq = hubbub2_get_dchub_ref_freq,
.program_watermarks = hubbub21_program_watermarks,
+   .apply_DEDCN21_147_wa = hubbub21_apply_DEDCN21_147_wa,
 };
 
 void hubbub21_construct(struct dcn20_hubbub *hubbub,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index e39961d0f24e..5e15f800a9f1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1468,6 +1468,7 @@ static struct dce_hwseq *dcn21_hwseq_create(
hws->regs = _reg;
hws->shifts = _shift;
hws->masks = _mask;
+   hws->wa.DEGVIDCN21 = true;
}
return hws;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
index a6297219d7fc..c81a17aeaa25 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
@@ -147,6 +147,7 @@ struct hubbub_funcs {
bool (*is_allow_self_refresh_enabled)(struct hubbub *hubbub);
void (*allow_self_refresh_control)(struct hubbub *hubbub, bool allow);
 
+   void (*apply_DEDCN21_147_wa)(struct hubbub *hubbub);
 };
 
 struct hubbub {
-- 
2.17.1

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[PATCH 07/29] drm/amd/display: create dcn21_link_encoder files

[Bhawanpreet Lakha]

[Why]
DCN20 and DCN21 have different phy programming sequences.

[How]
Create a separate dcn21_link_encoder for Renoir

Signed-off-by: Bhawanpreet Lakha 
---
 .../amd/display/dc/dcn10/dcn10_link_encoder.h |  35 +-
 .../amd/display/dc/dcn20/dcn20_link_encoder.h |   7 +
 drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   2 +-
 .../amd/display/dc/dcn21/dcn21_link_encoder.c | 379 ++
 .../amd/display/dc/dcn21/dcn21_link_encoder.h |  51 +++
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  85 +++-
 6 files changed, 555 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index 0c12395cfa36..239a6c90ffb9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -250,6 +250,10 @@ struct dcn10_link_enc_registers {
type RDPCS_EXT_REFCLK_EN;\
type RDPCS_TX_FIFO_EN;\
type UNIPHY_LINK_ENABLE;\
+   type UNIPHY_CHANNEL0_XBAR_SOURCE;\
+   type UNIPHY_CHANNEL1_XBAR_SOURCE;\
+   type UNIPHY_CHANNEL2_XBAR_SOURCE;\
+   type UNIPHY_CHANNEL3_XBAR_SOURCE;\
type UNIPHY_CHANNEL0_INVERT;\
type UNIPHY_CHANNEL1_INVERT;\
type UNIPHY_CHANNEL2_INVERT;\
@@ -342,12 +346,41 @@ struct dcn10_link_enc_registers {
type RDPCS_PHY_DPALT_DISABLE_ACK;\
type RDPCS_PHY_DP_MPLLB_V2I;\
type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
+   type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\
+   type RDPCS_PHY_RX_VREF_CTRL;\
type RDPCS_PHY_DP_MPLLB_CP_INT;\
type RDPCS_PHY_DP_MPLLB_CP_PROP;\
type RDPCS_PHY_RX_REF_LD_VAL;\
type RDPCS_PHY_RX_VCO_LD_VAL;\
type DPCSTX_DEBUG_CONFIG; \
-   type RDPCSTX_DEBUG_CONFIG
+   type RDPCSTX_DEBUG_CONFIG; \
+   type RDPCS_PHY_DP_TX0_EQ_MAIN;\
+   type RDPCS_PHY_DP_TX0_EQ_PRE;\
+   type RDPCS_PHY_DP_TX0_EQ_POST;\
+   type RDPCS_PHY_DP_TX1_EQ_MAIN;\
+   type RDPCS_PHY_DP_TX1_EQ_PRE;\
+   type RDPCS_PHY_DP_TX1_EQ_POST;\
+   type RDPCS_PHY_DP_TX2_EQ_MAIN;\
+   type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\
+   type RDPCS_PHY_DP_TX2_EQ_PRE;\
+   type RDPCS_PHY_DP_TX2_EQ_POST;\
+   type RDPCS_PHY_DP_TX3_EQ_MAIN;\
+   type RDPCS_PHY_DCO_RANGE;\
+   type RDPCS_PHY_DCO_FINETUNE;\
+   type RDPCS_PHY_DP_TX3_EQ_PRE;\
+   type RDPCS_PHY_DP_TX3_EQ_POST;\
+   type RDPCS_PHY_SUP_PRE_HP;\
+   type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\
+   type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\
+   type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\
+   type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\
+   type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\
+   type UNIPHYA_SOFT_RESET;\
+   type UNIPHYB_SOFT_RESET;\
+   type UNIPHYC_SOFT_RESET;\
+   type UNIPHYD_SOFT_RESET;\
+   type UNIPHYE_SOFT_RESET;\
+   type UNIPHYF_SOFT_RESET
 
 #define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \
type DIG_LANE0EN;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
index 3736b5548a25..0c98a0bbbd14 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_link_encoder.h
@@ -91,6 +91,13 @@ struct mpll_cfg {
uint32_t ref_range;
uint32_t ref_clk;
bool hdmimode_enable;
+   bool sup_pre_hp;
+   bool dp_tx0_vergdrv_byp;
+   bool dp_tx1_vergdrv_byp;
+   bool dp_tx2_vergdrv_byp;
+   bool dp_tx3_vergdrv_byp;
+
+
 };
 
 struct dpcssys_phy_seq_cfg {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile 
b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
index 5b8f42ae2334..b7a9285348fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
@@ -1,7 +1,7 @@
 #
 # Makefile for DCN21.
 
-DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o
+DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o 
dcn21_link_encoder.o
 
 CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
new file mode 100644
index ..526865c43b48
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
@@ -0,0 +1,379 @@
+/*
+ * Copyright 2012-15 Advanced Micro 

[PATCH 16/29] drm/amd/display: add detile buffer size for renoir

[Bhawanpreet Lakha]

Detile buffer size affects dcc caps, it was already added for
dcn2. Now add it for dcn21

Signed-off-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
index aeb5de6f4530..f546260c15b7 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
@@ -653,4 +653,5 @@ void hubbub21_construct(struct dcn20_hubbub *hubbub,
hubbub->masks = hubbub_mask;
 
hubbub->debug_test_index_pstate = 0xB;
+   hubbub->detile_buf_size = 164 * 1024; /* 164KB for DCN2.0 */
 }
-- 
2.17.1

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[PATCH 19/29] drm/amd/display: change PP_SM defs to 8

[Bhawanpreet Lakha]

DPM level is 8 these were incorrect before. Fix them

Signed-off-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 
b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
index c03a441ee638..de3c83c8f6c3 100644
--- a/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_pp_smu.h
@@ -252,9 +252,9 @@ struct pp_smu_funcs_nv {
 #if defined(CONFIG_DRM_AMD_DC_DCN2_1)
 
 #define PP_SMU_NUM_SOCCLK_DPM_LEVELS  8
-#define PP_SMU_NUM_DCFCLK_DPM_LEVELS  4
-#define PP_SMU_NUM_FCLK_DPM_LEVELS4
-#define PP_SMU_NUM_MEMCLK_DPM_LEVELS  4
+#define PP_SMU_NUM_DCFCLK_DPM_LEVELS  8
+#define PP_SMU_NUM_FCLK_DPM_LEVELS8
+#define PP_SMU_NUM_MEMCLK_DPM_LEVELS  8
 
 struct dpm_clock {
   uint32_t  Freq;// In MHz
-- 
2.17.1

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[PATCH 28/29] drm/amd/display: handle dp is usb-c

[Bhawanpreet Lakha]

This patch adds handling of dp is usb-c, it is not tested but is
needed to support dp over usb-c

Signed-off-by: Bhawanpreet Lakha 
---
 .../amd/display/dc/dcn10/dcn10_link_encoder.h | 14 +++
 .../amd/display/dc/dcn21/dcn21_link_encoder.c | 93 ++-
 .../amd/display/dc/dcn21/dcn21_link_encoder.h | 10 ++
 3 files changed, 116 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index 239a6c90ffb9..88fcc395adf5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -113,6 +113,20 @@ struct dcn10_link_enc_registers {
uint32_t DIG_LANE_ENABLE;
/* UNIPHY */
uint32_t CHANNEL_XBAR_CNTL;
+   /* DPCS */
+   uint32_t RDPCSTX_PHY_CNTL3;
+   uint32_t RDPCSTX_PHY_CNTL4;
+   uint32_t RDPCSTX_PHY_CNTL5;
+   uint32_t RDPCSTX_PHY_CNTL6;
+   uint32_t RDPCSTX_PHY_CNTL7;
+   uint32_t RDPCSTX_PHY_CNTL8;
+   uint32_t RDPCSTX_PHY_CNTL9;
+   uint32_t RDPCSTX_PHY_CNTL10;
+   uint32_t RDPCSTX_PHY_CNTL11;
+   uint32_t RDPCSTX_PHY_CNTL12;
+   uint32_t RDPCSTX_PHY_CNTL13;
+   uint32_t RDPCSTX_PHY_CNTL14;
+   uint32_t RDPCSTX_PHY_CNTL15;
/* indirect registers */
uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
index 526865c43b48..e8a504ca5890 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
@@ -203,6 +203,77 @@ static bool update_cfg_data(
return true;
 }
 
+void dcn21_link_encoder_get_max_link_cap(struct link_encoder *enc,
+   struct dc_link_settings *link_settings)
+{
+   struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+   uint32_t value;
+
+   REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, );
+
+   if (!value && link_settings->lane_count > LANE_COUNT_TWO)
+   link_settings->lane_count = LANE_COUNT_TWO;
+}
+
+bool dcn21_link_encoder_is_in_alt_mode(struct link_encoder *enc)
+{
+   struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+   uint32_t value;
+
+   REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, );
+
+   // if value == 1 alt mode is disabled, otherwise it is enabled
+   return !value;
+}
+
+bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc)
+{
+   struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+   int value;
+
+   if (enc->features.flags.bits.DP_IS_USB_C) {
+   REG_GET(RDPCSTX_PHY_CNTL6,
+   RDPCS_PHY_DPALT_DISABLE, );
+
+   if (value == 1) {
+   ASSERT(0);
+   return false;
+   }
+   REG_UPDATE(RDPCSTX_PHY_CNTL6,
+   RDPCS_PHY_DPALT_DISABLE_ACK, 0);
+
+   udelay(40);
+
+   REG_GET(RDPCSTX_PHY_CNTL6,
+   RDPCS_PHY_DPALT_DISABLE, 
);
+   if (value == 1) {
+   ASSERT(0);
+   REG_UPDATE(RDPCSTX_PHY_CNTL6,
+   RDPCS_PHY_DPALT_DISABLE_ACK, 1);
+   return false;
+   }
+   }
+
+   REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 1);
+
+   return true;
+}
+
+
+
+static void dcn21_link_encoder_release_phy(struct link_encoder *enc)
+{
+   struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
+
+   if (enc->features.flags.bits.DP_IS_USB_C) {
+   REG_UPDATE(RDPCSTX_PHY_CNTL6,
+   RDPCS_PHY_DPALT_DISABLE_ACK, 1);
+   }
+
+   REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 0);
+
+}
+
 void dcn21_link_encoder_enable_dp_output(
struct link_encoder *enc,
const struct dc_link_settings *link_settings,
@@ -212,6 +283,9 @@ void dcn21_link_encoder_enable_dp_output(
struct dcn21_link_encoder *enc21 = (struct dcn21_link_encoder *) enc10;
struct dpcssys_phy_seq_cfg *cfg = >phy_seq_cfg;
 
+   if (!dcn21_link_encoder_acquire_phy(enc))
+   return;
+
if (!enc->ctx->dc->debug.avoid_vbios_exec_table) {
dcn10_link_encoder_enable_dp_output(enc, link_settings, 
clock_source);
return;
@@ -226,13 +300,28 @@ void dcn21_link_encoder_enable_dp_output(
 
 }
 
+void dcn21_link_encoder_enable_dp_mst_output(
+   struct link_encoder *enc,
+   const struct dc_link_settings *link_settings,
+   enum clock_source_id clock_source)
+{
+   if (!dcn21_link_encoder_acquire_phy(enc))
+   return;
+
+   dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, 
clock_source);
+}
+

[PATCH 24/29] drm/amd/display: add sanity check for clk table from smu

[Bhawanpreet Lakha]

From: Eric Yang 

[Why]
Handle the case where we don't get a valid table. Also fixes compiler
warning for variable potentially used before assignment.

[How]
If the entire table has no valid fclk, reject the table and use our own
hard code.

Signed-off-by: Eric Yang 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index fb8aa9436bf0..0e712df87109 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -546,6 +546,8 @@ void rn_clk_mgr_helper_populate_bw_params(struct 
clk_bw_params *bw_params, struc
 {
int i, j = 0;
 
+   j = -1;
+
ASSERT(PP_SMU_NUM_FCLK_DPM_LEVELS <= MAX_NUM_DPM_LVL);
 
/* Find lowest DPM, FCLK is filled in reverse order*/
@@ -557,6 +559,12 @@ void rn_clk_mgr_helper_populate_bw_params(struct 
clk_bw_params *bw_params, struc
}
}
 
+   if (j == -1) {
+   /* clock table is all 0s, just use our own hardcode */
+   ASSERT(0);
+   return;
+   }
+
bw_params->clk_table.num_entries = j + 1;
 
for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
-- 
2.17.1

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[PATCH 05/29] drm/amd/display: Add DCN_BASE regs

[Bhawanpreet Lakha]

Signed-off-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/include/renoir_ip_offset.h| 34 +++
 1 file changed, 34 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/renoir_ip_offset.h 
b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
index 094648cac392..07633e22e99a 100644
--- a/drivers/gpu/drm/amd/include/renoir_ip_offset.h
+++ b/drivers/gpu/drm/amd/include/renoir_ip_offset.h
@@ -169,6 +169,11 @@ static const struct IP_BASE NBIF0_BASE ={ { { { 
0x, 0x0014, 0x0D
 { { 0, 0, 0, 0, 0 } },
 { { 0, 0, 0, 0, 0 } },
 { { 0, 0, 0, 0, 0 } } } };
+static const struct IP_BASE DCN_BASE   ={ { { { 0x0012, 0x00C0, 
0x34C0, 0, 0 } },
+{ { 0, 0, 0, 0, 0 } },
+{ { 0, 0, 0, 0, 0 } },
+{ { 0, 0, 0, 0, 0 } },
+{ { 0, 0, 0, 0, 0 } } } };
 static const struct IP_BASE OSSSYS_BASE ={ { { { 0x10A0, 0x0240A000, 0, 0, 
0 } },
 { { 0, 0, 0, 0, 0 } },
 { { 0, 0, 0, 0, 0 } },
@@ -1361,4 +1366,33 @@ static const struct IP_BASE UVD0_BASE ={ { { { 
0x7800, 0x7E00, 0x0240300
 #define UVD0_BASE__INST6_SEG3  0
 #define UVD0_BASE__INST6_SEG4  0
 
+#define DCN_BASE__INST0_SEG0  0x0012
+#define DCN_BASE__INST0_SEG1  0x00C0
+#define DCN_BASE__INST0_SEG2  0x34C0
+#define DCN_BASE__INST0_SEG3  0
+#define DCN_BASE__INST0_SEG4  0
+
+#define DCN_BASE__INST1_SEG0  0
+#define DCN_BASE__INST1_SEG1  0
+#define DCN_BASE__INST1_SEG2  0
+#define DCN_BASE__INST1_SEG3  0
+#define DCN_BASE__INST1_SEG4  0
+
+#define DCN_BASE__INST2_SEG0  0
+#define DCN_BASE__INST2_SEG1  0
+#define DCN_BASE__INST2_SEG2  0
+#define DCN_BASE__INST2_SEG3  0
+#define DCN_BASE__INST2_SEG4  0
+
+#define DCN_BASE__INST3_SEG0  0
+#define DCN_BASE__INST3_SEG1  0
+#define DCN_BASE__INST3_SEG2  0
+#define DCN_BASE__INST3_SEG3  0
+#define DCN_BASE__INST3_SEG4  0
+
+#define DCN_BASE__INST4_SEG0  0
+#define DCN_BASE__INST4_SEG1  0
+#define DCN_BASE__INST4_SEG2  0
+#define DCN_BASE__INST4_SEG3  0
+#define DCN_BASE__INST4_SEG4  0
 #endif
-- 
2.17.1

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[PATCH 23/29] drm/amd/display: Fix rn audio playback and video playback speed

[Bhawanpreet Lakha]

From: Michael Strauss 

[WHY]
dprefclk is improperly read due to incorrect units used.
Causes an audio clock to be improperly set, making audio
non-functional and videos play back too fast

[HOW]
Scale dprefclk value from MHz to KHz (multiply by 1000)
to ensure that dprefclk_khz is in correct units

Signed-off-by: Michael Strauss 
Acked-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 93e46e376bb1..fb8aa9436bf0 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -377,7 +377,7 @@ void rn_get_clk_states(struct clk_mgr *clk_mgr_base, struct 
clk_states *s)
 
rn_dump_clk_registers(, clk_mgr_base, _info);
 
-   s->dprefclk_khz = sb.dprefclk;
+   s->dprefclk_khz = sb.dprefclk * 1000;
 }
 
 void rn_enable_pme_wa(struct clk_mgr *clk_mgr_base)
@@ -633,16 +633,15 @@ void rn_clk_mgr_construct(
clk_mgr->dentist_vco_freq_khz = 360;
 
rn_dump_clk_registers(, _mgr->base, _info);
-   clk_mgr->base.dprefclk_khz = s.dprefclk;
-
-   if (clk_mgr->base.dprefclk_khz != 60) {
-   clk_mgr->base.dprefclk_khz = 60;
-   ASSERT(1); //TODO: Renoir follow up.
-   }
+   /* Convert dprefclk units from MHz to KHz */
+   /* Value already divided by 10, some resolution lost */
+   clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;
 
/* in case we don't get a value from the register, use default 
*/
-   if (clk_mgr->base.dprefclk_khz == 0)
+   if (clk_mgr->base.dprefclk_khz == 0) {
+   ASSERT(clk_mgr->base.dprefclk_khz == 60);
clk_mgr->base.dprefclk_khz = 60;
+   }
}
 
dce_clock_read_ss_info(clk_mgr);
-- 
2.17.1

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[PATCH 17/29] drm/amd/display: update dcn21 hubbub registers

[Bhawanpreet Lakha]

use dcn20 common regs define to share some regs with dcn20

Signed-off-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h | 17 +++--
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
index 698c470cc0f6..c4840dfb1fa5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h
@@ -36,6 +36,10 @@
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B),\
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C),\
SR(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D),\
+   SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A),\
+   SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B),\
+   SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C),\
+   SR(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D),\
SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
SR(DCHVM_CTRL0), \
SR(DCHVM_MEM_CTRL), \
@@ -44,16 +48,9 @@
SR(DCHVM_RIOMMU_STAT0)
 
 #define HUBBUB_REG_LIST_DCN21()\
-   HUBBUB_REG_LIST_DCN_COMMON(), \
+   HUBBUB_REG_LIST_DCN20_COMMON(), \
HUBBUB_SR_WATERMARK_REG_LIST(), \
-   HUBBUB_HVM_REG_LIST(), \
-   SR(DCHUBBUB_CRC_CTRL), \
-   SR(DCN_VM_FB_LOCATION_BASE),\
-   SR(DCN_VM_FB_LOCATION_TOP),\
-   SR(DCN_VM_FB_OFFSET),\
-   SR(DCN_VM_AGP_BOT),\
-   SR(DCN_VM_AGP_TOP),\
-   SR(DCN_VM_AGP_BASE)
+   HUBBUB_HVM_REG_LIST()
 
 #define HUBBUB_MASK_SH_LIST_HVM(mask_sh) \
HUBBUB_SF(DCHUBBUB_ARB_DF_REQ_OUTSTAND, 
DCHUBBUB_ARB_MIN_REQ_OUTSTAND_COMMIT_THRESHOLD, mask_sh), \
@@ -102,7 +99,7 @@
HUBBUB_SF(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, 
DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, mask_sh)
 
 #define HUBBUB_MASK_SH_LIST_DCN21(mask_sh)\
-   HUBBUB_MASK_SH_LIST_HVM(mask_sh),\
+   HUBBUB_MASK_SH_LIST_HVM(mask_sh), \
HUBBUB_MASK_SH_LIST_DCN_COMMON(mask_sh), \
HUBBUB_MASK_SH_LIST_STUTTER(mask_sh), \
HUBBUB_SF(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 
mask_sh), \
-- 
2.17.1

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[PATCH 11/29] drm/amd/display: fix incorrect page table address for renoir

[Bhawanpreet Lakha]

Incorrect page table address and programming sys aperture for
stutter gather, so fix it.

Signed-off-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/dc/dcn21/dcn21_hubbub.c   | 23 ++-
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
index bd247e5e753e..fdfbdeb32459 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
@@ -111,19 +111,30 @@ int hubbub21_init_dchub(struct hubbub *hubbub,
struct dcn_hubbub_phys_addr_config *pa_config)
 {
struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
+   struct dcn_vmid_page_table_config phys_config;
 
REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
-   FB_BASE, pa_config->system_aperture.fb_base);
+   FB_BASE, pa_config->system_aperture.fb_base >> 24);
REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
-   FB_TOP, pa_config->system_aperture.fb_top);
+   FB_TOP, pa_config->system_aperture.fb_top >> 24);
REG_SET(DCN_VM_FB_OFFSET, 0,
-   FB_OFFSET, pa_config->system_aperture.fb_offset);
+   FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
REG_SET(DCN_VM_AGP_BOT, 0,
-   AGP_BOT, pa_config->system_aperture.agp_bot);
+   AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
REG_SET(DCN_VM_AGP_TOP, 0,
-   AGP_TOP, pa_config->system_aperture.agp_top);
+   AGP_TOP, pa_config->system_aperture.agp_top >> 24);
REG_SET(DCN_VM_AGP_BASE, 0,
-   AGP_BASE, pa_config->system_aperture.agp_base);
+   AGP_BASE, pa_config->system_aperture.agp_base >> 24);
+
+   if (pa_config->gart_config.page_table_start_addr != 
pa_config->gart_config.page_table_end_addr) {
+   phys_config.page_table_start_addr = 
pa_config->gart_config.page_table_start_addr >> 12;
+   phys_config.page_table_end_addr = 
pa_config->gart_config.page_table_end_addr >> 12;
+   phys_config.page_table_base_addr = 
pa_config->gart_config.page_table_base_addr | 1; //Note: hack
+   phys_config.depth = 0;
+   phys_config.block_size = 0;
+   // Init VMID 0 based on PA config
+   dcn20_vmid_setup(>vmid[0], _config);
+   }
 
dcn21_dchvm_init(hubbub);
 
-- 
2.17.1

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[PATCH 20/29] drm/amd/display: add dummy functions to smu for Renoir Silicon Diags

[Bhawanpreet Lakha]

From: Sung Lee 

[Why]
Previously only dummy functions were added in Diags for FPGA.
On silicon, this would lead to a segmentation fault on silicon diags.

[How]
Check if diags silicon and if so, add dummy functions.

Signed-off-by: Sung Lee 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 002e7fb67068..25f62a3f2ffc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1397,7 +1397,7 @@ static struct pp_smu_funcs *dcn21_pp_smu_create(struct 
dc_context *ctx)
if (!pp_smu)
return pp_smu;
 
-   if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
+   if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || 
IS_DIAG_DC(ctx->dce_environment)) {
pp_smu->ctx.ver = PP_SMU_VER_RN;
pp_smu->rn_funcs.get_dpm_clock_table = 
dummy_get_dpm_clock_table;
pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
-- 
2.17.1

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[PATCH 03/29] drm/amd/display: disable ext aux support for vega

[Bhawanpreet Lakha]

From: Roman Li 

[Why]
Earlier changes to support configurable aux timeout
caused dc init failure on vega due to missing reg defs.
Needs to be disabled until implemented for vega.

[How]
Set extended aux timeout cap for vega to false.

fixes: drm/amd/display: configurable aux timeout support

Signed-off-by: Roman Li 
Reviewed-By: abdoulaye berthe 
---
 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c 
b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
index 75dd9457cc2d..c30faa05fd27 100644
--- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c
@@ -1017,7 +1017,7 @@ static bool construct(
dc->caps.max_cursor_size = 128;
dc->caps.dual_link_dvi = true;
dc->caps.psp_setup_panel_mode = true;
-   dc->caps.extended_aux_timeout_support = true;
+   dc->caps.extended_aux_timeout_support = false;
dc->debug = debug_defaults;
 
/*
-- 
2.17.1

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[PATCH 10/29] drm/amd/display: enable hostvm based on roimmu active for dcn2.1

[Bhawanpreet Lakha]

From: Dmytro Laktyushkin 

Enabling hostvm when ROIMMU is not active seems to break GPUVM.
This fixes the issue by not enabling hostvm if ROIMMU is not
activated.

Signed-off-by: Dmytro Laktyushkin 
Acked-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/dc/dcn21/dcn21_hubbub.c   | 40 ---
 1 file changed, 25 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
index 8e7e79f44272..bd247e5e753e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c
@@ -22,6 +22,7 @@
  * Authors: AMD
  *
  */
+#include 
 #include "dm_services.h"
 #include "dcn20/dcn20_hubbub.h"
 #include "dcn21_hubbub.h"
@@ -71,30 +72,39 @@ static uint32_t convert_and_clamp(
 void dcn21_dchvm_init(struct hubbub *hubbub)
 {
struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
+   uint32_t riommu_active;
+   int i;
 
//Init DCHVM block
REG_UPDATE(DCHVM_CTRL0, HOSTVM_INIT_REQ, 1);
 
//Poll until RIOMMU_ACTIVE = 1
-   //TODO: Figure out interval us and retry count
-   REG_WAIT(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, 1, 5, 100);
+   for (i = 0; i < 100; i++) {
+   REG_GET(DCHVM_RIOMMU_STAT0, RIOMMU_ACTIVE, _active);
 
-   //Reflect the power status of DCHUBBUB
-   REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);
+   if (riommu_active)
+   break;
+   else
+   udelay(5);
+   }
+
+   if (riommu_active) {
+   //Reflect the power status of DCHUBBUB
+   REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_POWERSTATUS, 1);
 
-   //Start rIOMMU prefetching
-   REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);
+   //Start rIOMMU prefetching
+   REG_UPDATE(DCHVM_RIOMMU_CTRL0, HOSTVM_PREFETCH_REQ, 1);
 
-   // Enable dynamic clock gating
-   REG_UPDATE_4(DCHVM_CLK_CTRL,
-   HVM_DISPCLK_R_GATE_DIS, 0,
-   HVM_DISPCLK_G_GATE_DIS, 0,
-   HVM_DCFCLK_R_GATE_DIS, 0,
-   HVM_DCFCLK_G_GATE_DIS, 0);
+   // Enable dynamic clock gating
+   REG_UPDATE_4(DCHVM_CLK_CTRL,
+   HVM_DISPCLK_R_GATE_DIS, 0,
+   HVM_DISPCLK_G_GATE_DIS, 0,
+   HVM_DCFCLK_R_GATE_DIS, 0,
+   HVM_DCFCLK_G_GATE_DIS, 0);
 
-   //Poll until HOSTVM_PREFETCH_DONE = 1
-   //TODO: Figure out interval us and retry count
-   REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
+   //Poll until HOSTVM_PREFETCH_DONE = 1
+   REG_WAIT(DCHVM_RIOMMU_STAT0, HOSTVM_PREFETCH_DONE, 1, 5, 100);
+   }
 }
 
 int hubbub21_init_dchub(struct hubbub *hubbub,
-- 
2.17.1

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[PATCH 01/29] drm/amd/display: update register field access mechanism

[Bhawanpreet Lakha]

From: abdoulaye berthe 

1-add timeout length and multiplier fields to aux_control1 register
2-update access mechanism from macro constructed name to uint32_t
defined addresses.
3-define registers and field per asic family

Signed-off-by: abdoulaye berthe 
Acked-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.c  |  11 +-
 drivers/gpu/drm/amd/display/dc/dce/dce_aux.h  | 175 +-
 .../amd/display/dc/dce100/dce100_resource.c   |  12 +-
 .../amd/display/dc/dce110/dce110_resource.c   |  12 +-
 .../amd/display/dc/dce112/dce112_resource.c   |  12 +-
 .../amd/display/dc/dce120/dce120_resource.c   |  12 +-
 .../drm/amd/display/dc/dce80/dce80_resource.c |  12 +-
 .../drm/amd/display/dc/dcn10/dcn10_resource.c |  12 +-
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  13 +-
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  12 +-
 10 files changed, 271 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 48a0e4ae80c2..de233270e3d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -42,6 +42,10 @@
 
 #include "reg_helper.h"
 
+#undef FN
+#define FN(reg_name, field_name) \
+   aux110->shift->field_name, aux110->mask->field_name
+
 #define FROM_AUX_ENGINE(ptr) \
container_of((ptr), struct aux_engine_dce110, base)
 
@@ -414,11 +418,14 @@ void dce110_engine_destroy(struct dce_aux **engine)
*engine = NULL;
 
 }
+
 struct dce_aux *dce110_aux_engine_construct(struct aux_engine_dce110 
*aux_engine110,
struct dc_context *ctx,
uint32_t inst,
uint32_t timeout_period,
-   const struct dce110_aux_registers *regs)
+   const struct dce110_aux_registers *regs,
+   const struct dce110_aux_registers_mask *mask,
+   const struct dce110_aux_registers_shift *shift)
 {
aux_engine110->base.ddc = NULL;
aux_engine110->base.ctx = ctx;
@@ -428,6 +435,8 @@ struct dce_aux *dce110_aux_engine_construct(struct 
aux_engine_dce110 *aux_engine
aux_engine110->timeout_period = timeout_period;
aux_engine110->regs = regs;
 
+   aux_engine110->mask = mask;
+   aux_engine110->shift = shift;
return _engine110->base;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
index ed7fec8fe253..717378502e9d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.h
@@ -29,6 +29,7 @@
 #include "i2caux_interface.h"
 #include "inc/hw/aux_engine.h"
 
+
 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
 #define AUX_COMMON_REG_LIST0(id)\
SRI(AUX_CONTROL, DP_AUX, id), \
@@ -36,6 +37,7 @@
SRI(AUX_SW_DATA, DP_AUX, id), \
SRI(AUX_SW_CONTROL, DP_AUX, id), \
SRI(AUX_INTERRUPT_CONTROL, DP_AUX, id), \
+   SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id), \
SRI(AUX_SW_STATUS, DP_AUX, id)
 #endif
 
@@ -55,6 +57,7 @@ struct dce110_aux_registers {
uint32_t AUX_SW_DATA;
uint32_t AUX_SW_CONTROL;
uint32_t AUX_INTERRUPT_CONTROL;
+   uint32_t AUX_DPHY_RX_CONTROL1;
uint32_t AUX_SW_STATUS;
uint32_t AUXN_IMPCAL;
uint32_t AUXP_IMPCAL;
@@ -62,6 +65,156 @@ struct dce110_aux_registers {
uint32_t AUX_RESET_MASK;
 };
 
+#define DCE_AUX_REG_FIELD_LIST(type)\
+   type AUX_EN;\
+   type AUX_RESET;\
+   type AUX_RESET_DONE;\
+   type AUX_REG_RW_CNTL_STATUS;\
+   type AUX_SW_USE_AUX_REG_REQ;\
+   type AUX_SW_DONE_USING_AUX_REG;\
+   type AUX_SW_AUTOINCREMENT_DISABLE;\
+   type AUX_SW_DATA_RW;\
+   type AUX_SW_INDEX;\
+   type AUX_SW_GO;\
+   type AUX_SW_DATA;\
+   type AUX_SW_REPLY_BYTE_COUNT;\
+   type AUX_SW_DONE;\
+   type AUX_SW_DONE_ACK;\
+   type AUXN_IMPCAL_ENABLE;\
+   type AUXP_IMPCAL_ENABLE;\
+   type AUXN_IMPCAL_OVERRIDE_ENABLE;\
+   type AUXP_IMPCAL_OVERRIDE_ENABLE;\
+   type AUX_RX_TIMEOUT_LEN;\
+   type AUX_RX_TIMEOUT_LEN_MUL;\
+   type AUXN_CALOUT_ERROR_AK;\
+   type AUXP_CALOUT_ERROR_AK;\
+   type AUX_SW_START_DELAY;\
+   type AUX_SW_WR_BYTES
+
+#define DCE10_AUX_MASK_SH_LIST(mask_sh)\
+   AUX_SF(AUX_CONTROL, AUX_EN, mask_sh),\
+   AUX_SF(AUX_ARB_CONTROL, AUX_REG_RW_CNTL_STATUS, mask_sh),\
+   AUX_SF(AUX_ARB_CONTROL, AUX_SW_USE_AUX_REG_REQ, mask_sh),\
+   AUX_SF(AUX_ARB_CONTROL, AUX_SW_DONE_USING_AUX_REG, mask_sh),\
+   AUX_SF(AUX_SW_CONTROL, AUX_SW_START_DELAY, mask_sh),\
+   AUX_SF(AUX_SW_CONTROL, AUX_SW_WR_BYTES, mask_sh),\
+   AUX_SF(AUX_SW_CONTROL, AUX_SW_GO, mask_sh),\
+   AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
+   AUX_SF(AUX_SW_DATA, AUX_SW_DATA_RW, mask_sh),\
+   AUX_SF(AUX_SW_DATA, AUX_SW_AUTOINCREMENT_DISABLE, mask_sh),\
+   AUX_SF(AUX_SW_DATA, AUX_SW_INDEX, mask_sh),\
+   

[PATCH 29/29] drm/amd/display: null check pp_smu clock table before using it

[Bhawanpreet Lakha]

Signed-off-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 0e712df87109..b647e0320e4b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -656,7 +656,7 @@ void rn_clk_mgr_construct(
 
clk_mgr->base.bw_params = _bw_params;
 
-   if (pp_smu) {
+   if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) {
pp_smu->rn_funcs.get_dpm_clock_table(_smu->rn_funcs.pp_smu, 
_table);
rn_clk_mgr_helper_populate_bw_params(clk_mgr->base.bw_params, 
_table, >asic_id);
}
-- 
2.17.1

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[PATCH 06/29] drm/amd/display: Add renoir hw_seq

[Bhawanpreet Lakha]

This change adds renoir hw_seq, needed to do renoir
specific hw programing

Signed-off-by: Bhawanpreet Lakha 
---
 .../gpu/drm/amd/display/dc/dce/dce_hwseq.h|   1 +
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   4 +
 drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   2 +-
 .../drm/amd/display/dc/dcn21/dcn21_hwseq.c| 122 ++
 .../drm/amd/display/dc/dcn21/dcn21_hwseq.h|  33 +
 .../drm/amd/display/dc/dcn21/dcn21_resource.c | 118 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   3 +
 7 files changed, 255 insertions(+), 28 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h 
b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index ac04d77058f0..32d145a0d6fc 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -679,6 +679,7 @@ struct dce_hwseq_registers {
HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN17_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN18_PGFSM_PWR_STATUS, mask_sh), \
HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
+   HWSEQ_LVTMA_MASK_SH_LIST(mask_sh), \
HWS_SF(, LVTMA_PWRSEQ_CNTL, LVTMA_BLON, mask_sh), \
HWS_SF(, LVTMA_PWRSEQ_STATE, LVTMA_PWRSEQ_TARGET_STATE_R, mask_sh)
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 32bf6cf09677..df1be8ada66d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -670,6 +670,10 @@ static void dcn10_bios_golden_init(struct dc *dc)
int i;
bool allow_self_fresh_force_enable = true;
 
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+   if (dc->hwss.s0i3_golden_init_wa && dc->hwss.s0i3_golden_init_wa(dc))
+   return;
+#endif
if (dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled)
allow_self_fresh_force_enable =

dc->res_pool->hubbub->funcs->is_allow_self_refresh_enabled(dc->res_pool->hubbub);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile 
b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
index b2b39090fb57..5b8f42ae2334 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/Makefile
@@ -1,7 +1,7 @@
 #
 # Makefile for DCN21.
 
-DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o
+DCN21 = dcn21_hubp.o dcn21_hubbub.o dcn21_resource.o dcn21_hwseq.o
 
 CFLAGS_dcn21_resource.o := -mhard-float -msse -mpreferred-stack-boundary=4
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
new file mode 100644
index ..b25215cadf85
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dm_helpers.h"
+#include "core_types.h"
+#include "resource.h"
+#include "dce/dce_hwseq.h"
+#include "dcn20/dcn20_hwseq.h"
+#include "vmid.h"
+#include "reg_helper.h"
+#include "hw/clk_mgr.h"
+
+
+#define DC_LOGGER_INIT(logger)
+
+#define CTX \
+   hws->ctx
+#define REG(reg)\
+   hws->regs->reg
+
+#undef FN
+#define FN(reg_name, field_name) \
+   hws->shifts->field_name, hws->masks->field_name
+
+/* Temporary read settings, future will get values from kmd directly */
+static void mmhub_update_page_table_config(struct dcn_hubbub_phys_addr_config 
*config,
+   struct dce_hwseq *hws)
+{
+   uint32_t page_table_base_hi;
+   uint32_t page_table_base_lo;
+
+   REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+  

[PATCH 26/29] drm/amd/display: enable smu set dcfclk

[Bhawanpreet Lakha]

From: Lewis Huang 

[Why]
SMU fixed this issue after version 0x370c00

[How]
enable smu send message to set dcfclk after smu version 0x370c00

Signed-off-by: Lewis Huang 
Acked-by: Bhawanpreet Lakha 
---
 .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c   | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git 
a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
index db28e91adb3d..2650776acbc3 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c
@@ -124,7 +124,7 @@ int rn_vbios_smu_set_hard_min_dcfclk(struct 
clk_mgr_internal *clk_mgr, int reque
 {
int actual_dcfclk_set_mhz = -1;
 
-   if (clk_mgr->smu_ver < 0x)
+   if (clk_mgr->smu_ver < 0x370c00)
return actual_dcfclk_set_mhz;
 
actual_dcfclk_set_mhz = rn_vbios_smu_send_msg_with_param(
@@ -139,7 +139,7 @@ int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct 
clk_mgr_internal *clk_mgr, int
 {
int actual_min_ds_dcfclk_mhz = -1;
 
-   if (clk_mgr->smu_ver < 0x)
+   if (clk_mgr->smu_ver < 0x370c00)
return actual_min_ds_dcfclk_mhz;
 
actual_min_ds_dcfclk_mhz = rn_vbios_smu_send_msg_with_param(
-- 
2.17.1

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Re: [PATCH] drm/amd/display: Use pixel encoding 444 for dongle usb-c to hdmi

[Julien Isorce]

Hi Harry,

Do you need more information ?

Thx
Julien

On Tue, Oct 8, 2019 at 11:15 AM Julien Isorce 
wrote:

> Hi Harry,
>
> I can reproduce on LG, Samsung and NEC monitors.
>
> "Have you checked whether the driver picks RGB or YCBCR420 without your
> patch?" -> it was selecting RGB .
>
> For example on https://commons.wikimedia.org/wiki/File:Gray_scale.jpg ,
> the second band from the left, will be entirely pinkish.
> Since the issue also happens without dongle, so with a direct cable from
> the miniDP from the graphic card to DisplayPort on the screen I think there
> is more serious issue with RGB output in amdgpu. But it is not easy to
> reproduce, you should try on above image.
>
> In any case, the goal with the patch is just to get the same output when
> using 2 screens at the same time, one connected to hdmi output of the
> graphic card and one connected  to usb-c to graphic card (hdmi cable with
> dongle). So prior this patch, the first one would use YCbCr 444 and the
> second would use RGB.
> After this patch, both will use YCbCr 444 (both are hdmi).
> The patch does not change the case for miniDP to DisplayPort, the driver
> will still use RGB. Because maybe the RGB issue is also specific to that
> graphic card which
> is VEGA"M". So that is why the patch only tries to match hdmi cases
> together, whether it is direct connection or through usb-c.
>
> -
> Julien
>
>
>
> On Tue, Oct 8, 2019 at 10:44 AM Harry Wentland  wrote:
>
>> Hi Julien,
>>
>> curious which monitor you're using.
>>
>> Have you checked whether the driver picks RGB or YCBCR420 without your
>> patch?
>>
>> I'm not sure I understand how the pinkish color issue looks. Do you see
>> a pinkish color at the transition from grey to another color? Or is the
>> entire grey area pinkish?
>>
>> Thanks,
>> Harry
>>
>> On 2019-10-08 12:06 p.m., Julien Isorce wrote:
>> > Hi,
>> >
>> > Gentle ping ?
>> >
>> > Thx
>> > Julien
>> >
>> > On Tue, Oct 1, 2019 at 3:21 PM Julien Isorce > > > wrote:
>> >
>> > Fix pinkish color issue around grey areas. This also happens
>> > when not using any dongle so directly with a usb-c to Display
>> > Port cable. Meaning there is something wrong when using pixel
>> > encoding RGB with amd driver in the general case. In the meantime
>> > just use the same pixel encoding as when using HDMI without dongle.
>> > This way users will see the same thing on 2 identical screens when
>> > one is connected with hdmi-to-hdmi and the other is connected with
>> > usb-c-to-hdmi.
>> >
>> > Signed-off-by: Julien Isorce > > >
>> > ---
>> >  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +
>> >  1 file changed, 5 insertions(+)
>> >
>> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> > index d3f404f097eb..8139dcc0bfba 100644
>> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
>> > @@ -3313,6 +3313,7 @@ static void
>> > fill_stream_properties_from_drm_display_mode(
>> >  {
>> > struct dc_crtc_timing *timing_out = >timing;
>> > const struct drm_display_info *info =
>> >display_info;
>> > +   const struct dc_link *link = stream->sink->link;
>> >
>> > memset(timing_out, 0, sizeof(struct dc_crtc_timing));
>> >
>> > @@ -3327,6 +3328,10 @@ static void
>> > fill_stream_properties_from_drm_display_mode(
>> > else if ((connector->display_info.color_formats &
>> > DRM_COLOR_FORMAT_YCRCB444)
>> > && stream->signal ==
>> SIGNAL_TYPE_HDMI_TYPE_A)
>> > timing_out->pixel_encoding =
>> PIXEL_ENCODING_YCBCR444;
>> > +   else if ((connector->display_info.color_formats &
>> > DRM_COLOR_FORMAT_YCRCB444)
>> > +   && stream->sink->sink_signal ==
>> > SIGNAL_TYPE_DISPLAY_PORT
>> > +   && link->dpcd_caps.dongle_type ==
>> > DISPLAY_DONGLE_DP_HDMI_CONVERTER)
>> > +   timing_out->pixel_encoding =
>> PIXEL_ENCODING_YCBCR444;
>> > else
>> > timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
>> >
>> > --
>> > 2.17.1
>> >
>> >
>> > ___
>> > amd-gfx mailing list
>> > amd-gfx@lists.freedesktop.org
>> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>> >
>>
>
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Re: [PATCH v3] drm/amdgpu: user pages array memory leak fix

[Yang, Philip]

On 2019-10-11 1:33 p.m., Kuehling, Felix wrote:
> On 2019-10-11 10:36 a.m., Yang, Philip wrote:
>> user_pages array should always be freed after validation regardless if
>> user pages are changed after bo is created because with HMM change parse
>> bo always allocate user pages array to get user pages for userptr bo.
>>
>> v2: remove unused local variable and amend commit
>>
>> v3: add back get user pages in gem_userptr_ioctl, to detect application
>> bug where an userptr VMA is not ananymous memory and reject it.
>>
>> Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962
>>
>> Signed-off-by: Philip Yang 
>> Tested-by: Joe Barnett 
>> Reviewed-by: Christian König 
>> ---
>>drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 +---
>>1 file changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> index c18a153b3d2a..e7b39daa22f6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> @@ -476,7 +476,6 @@ static int amdgpu_cs_list_validate(struct 
>> amdgpu_cs_parser *p,
>>
>>  list_for_each_entry(lobj, validated, tv.head) {
>>  struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
>> -bool binding_userptr = false;
>>  struct mm_struct *usermm;
>>
>>  usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
>> @@ -493,14 +492,13 @@ static int amdgpu_cs_list_validate(struct 
>> amdgpu_cs_parser *p,
>>
>>  amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
>>   lobj->user_pages);
>> -binding_userptr = true;
>>  }
>>
>>  r = amdgpu_cs_validate(p, bo);
>>  if (r)
>>  return r;
>>
>> -if (binding_userptr) {
>> +if (lobj->user_pages) {
> 
> This if is not needed. kvfree should be able to handle NULL pointers,
> and unconditionally setting the pointer to NULL afterwards is not a
> problem either. With that fixed, this commit is
> 
> Reviewed-by: Felix Kuehling 
> 
> However, I don't think this should be the final solution. My concern
> with this solution is, that you end up freeing and regenerating the
> user_pages arrays more frequently than necessary: On every command
> submission, even if there was no MMU notifier since the last command
> submission. I was hoping we could get back to a solution where we can
> maintain the same user_pages array across command submissions, since MMU
> notifiers are rare. That should reduce overhead from doing all thos page
> table walks in HMM on every command submissions when using userptrs.
> 
Yes, I will have another patch to address this using hmm_range_valid, 
the idea is to allow hmm range tracking cross gem_userptr_ioctl and 
cs_ioctl.

Thanks,
Philip

> Regards,
>     Felix
> 
> 
>>  kvfree(lobj->user_pages);
>>  lobj->user_pages = NULL;
>>  }
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Re: [PATCH v3] drm/amdgpu: user pages array memory leak fix

[Kuehling, Felix]

On 2019-10-11 10:36 a.m., Yang, Philip wrote:
> user_pages array should always be freed after validation regardless if
> user pages are changed after bo is created because with HMM change parse
> bo always allocate user pages array to get user pages for userptr bo.
>
> v2: remove unused local variable and amend commit
>
> v3: add back get user pages in gem_userptr_ioctl, to detect application
> bug where an userptr VMA is not ananymous memory and reject it.
>
> Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962
>
> Signed-off-by: Philip Yang 
> Tested-by: Joe Barnett 
> Reviewed-by: Christian König 
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 +---
>   1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index c18a153b3d2a..e7b39daa22f6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -476,7 +476,6 @@ static int amdgpu_cs_list_validate(struct 
> amdgpu_cs_parser *p,
>   
>   list_for_each_entry(lobj, validated, tv.head) {
>   struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
> - bool binding_userptr = false;
>   struct mm_struct *usermm;
>   
>   usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
> @@ -493,14 +492,13 @@ static int amdgpu_cs_list_validate(struct 
> amdgpu_cs_parser *p,
>   
>   amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
>lobj->user_pages);
> - binding_userptr = true;
>   }
>   
>   r = amdgpu_cs_validate(p, bo);
>   if (r)
>   return r;
>   
> - if (binding_userptr) {
> + if (lobj->user_pages) {

This if is not needed. kvfree should be able to handle NULL pointers, 
and unconditionally setting the pointer to NULL afterwards is not a 
problem either. With that fixed, this commit is

Reviewed-by: Felix Kuehling 

However, I don't think this should be the final solution. My concern 
with this solution is, that you end up freeing and regenerating the 
user_pages arrays more frequently than necessary: On every command 
submission, even if there was no MMU notifier since the last command 
submission. I was hoping we could get back to a solution where we can 
maintain the same user_pages array across command submissions, since MMU 
notifiers are rare. That should reduce overhead from doing all thos page 
table walks in HMM on every command submissions when using userptrs.

Regards,
   Felix


>   kvfree(lobj->user_pages);
>   lobj->user_pages = NULL;
>   }
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Re: [PATCH RFC v4 14/16] drm, cgroup: Introduce lgpu as DRM cgroup resource

[t...@kernel.org]

Hello, Daniel.

On Wed, Oct 09, 2019 at 06:06:52PM +0200, Daniel Vetter wrote:
> That's not the point I was making. For cpu cgroups there's a very well
> defined connection between the cpu bitmasks/numbers in cgroups and the cpu
> bitmasks you use in various system calls (they match). And that stuff
> works across vendors.

Please note that there are a lot of limitations even to cpuset.
Affinity is easy to implement and seems attractive in terms of
absolute isolation but it's inherently cumbersome and limited in
granularity and can lead to surprising failure modes where contention
on one cpu can't be resolved by the load balancer and leads to system
wide slowdowns / stalls caused by the dependency chain anchored at the
affinity limited tasks.

Maybe this is a less of a problem for gpu workloads but in general the
more constraints are put on scheduling, the more likely is the system
to develop twisted dependency chains while other parts of the system
are sitting idle.

How does scheduling currently work when there are competing gpu
workloads?  There gotta be some fairness provision whether that's unit
allocation based or time slicing, right?  If that's the case, it might
be best to implement proportional control on top of that.
Work-conserving mechanisms are the most versatile, easiest to use and
least likely to cause regressions.

Thanks.

-- 
tejun
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[ANNOUNCE] xf86-video-amdgpu 19.1.0

[Michel Dänzer]

I'm pleased to announce the 19.1.0 release of xf86-video-amdgpu, the
Xorg driver for AMD Radeon GPUs supported by the amdgpu kernel driver.
This release supports xserver versions 1.13-1.20.

There are no big changes in this release, just fixes and other minor
improvements.

Thanks to everybody who contributed to this release in any way!


NOTE:

As of September, I'm no longer working for AMD but for Red Hat's
graphics infrastructure team. I'm hoping that someone from my former
team at AMD will step up to maintain this driver.


Flora Cui (1):
  dri2: reply to client for WaitMSC request in any case

Michel Dänzer (13):
  Retry get_fb_ptr in get_fb
  dri3: Always flush glamor before sharing pixmap storage with clients
  dri2: Re-use previous CRTC when possible if pick_best_crtc returns NULL
  Remove dri2_drawable_crtc parameter consider_disabled
  present: Check that we can get a KMS FB for flipping
  Don't disable page flipping completely with SW cursor
  gitlab-ci: Use templates from wayland/ci-templates
  present: Also check pixmap pitch in check_flip with current xserver
  present: Don't check pixmap pitch in check_flip with current DC
  present: Don't check pixmap pitch in check_flip with non-DC >= 3.34
  Don't set up black scanout buffer if LeaveVT is called from CloseScreen
  Don't unreference FBs of pixmaps from different screens in LeaveVT
  Bump version for the 19.1.0 release

git tag: xf86-video-amdgpu-19.1.0

https://xorg.freedesktop.org/archive/individual/driver/xf86-video-amdgpu-19.1.0.tar.bz2
MD5:  55ad19b858e186a2cf4e91ed832c05e7  xf86-video-amdgpu-19.1.0.tar.bz2
SHA1: 044a97ea2f36dd3d2d4844bb503dd4e2b2854d56  xf86-video-amdgpu-19.1.0.tar.bz2
SHA256: 4f0ea4e0ae61995ac2b7c72433d31deab63b60c78763020aaa1b28696124fe5d  
xf86-video-amdgpu-19.1.0.tar.bz2
SHA512: 
ccdaa2378492da1a2f3d18fedacd1318c4708da534a8a959276a82730d5420619d83ad1ec8d7835c55655fe56123cd9bffb44e6223c5a97033c01f598af4a173
  xf86-video-amdgpu-19.1.0.tar.bz2
PGP:  
https://xorg.freedesktop.org/archive/individual/driver/xf86-video-amdgpu-19.1.0.tar.bz2.sig

https://xorg.freedesktop.org/archive/individual/driver/xf86-video-amdgpu-19.1.0.tar.gz
MD5:  5aec06fed52d09838d0511c59dd2d861  xf86-video-amdgpu-19.1.0.tar.gz
SHA1: 453ef4c403c1966bb0555057248629a1514ab18e  xf86-video-amdgpu-19.1.0.tar.gz
SHA256: 9967435ca5686395375adea503ee774ddb95181505247d164ee3a1a2995a081f  
xf86-video-amdgpu-19.1.0.tar.gz
SHA512: 
660bea3ff6c8123ebc7df82b8e90308759c1575a3b28fddc95f0e46b575250991eda36f0e85d9db9777d712c247dadc8ce1f45541146ac513ec8874b774a440d
  xf86-video-amdgpu-19.1.0.tar.gz
PGP:  
https://xorg.freedesktop.org/archive/individual/driver/xf86-video-amdgpu-19.1.0.tar.gz.sig

-- 
Earthling Michel Dänzer   |   https://redhat.com
Libre software enthusiast | Mesa and X developer


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Re: [PATCH 0/3] drm/amd/display/dc/dce: remove some not used variables

[Harry Wentland]

Thanks for the patches.

I think for all of them we should just drop the REG_READ calls
completely. They look like leftovers from when we had a different
register update scheme that would read the register, then update or get
the field value. Now we just use the REG_ macros that will combine the
read with the GET or UPDATE operations.

Harry

On 2019-10-09 2:25 a.m., zhengbin wrote:
> zhengbin (3):
>   drm/amd/display: Remove set but not used variables
> 'bl_pwm_cntl','pwm_period_cntl'
>   drm/amd/display: Remove set but not used variable 'value0'
>   drm/amd/display: Remove set but not used variables 'regval','speakers'
> 
>  drivers/gpu/drm/amd/display/dc/dce/dce_abm.c| 8 
>  drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c   | 3 +--
>  drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c | 5 +
>  3 files changed, 6 insertions(+), 10 deletions(-)
> 
> --
> 2.7.4
> 
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[PATCH] drm/amd/display: Free gamma after calculating legacy transfer function

[Nicholas Kazlauskas]

[Why]
We're leaking memory by not freeing the gamma used to calculate the
transfer function for legacy gamma.

[How]
Release the gamma after we're done with it.

Cc: Philip Yang 
Cc: Harry Wentland 
Cc: Bhawanpreet Lakha 
Cc: Leo Li 
Signed-off-by: Nicholas Kazlauskas 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index b43bb7f90e4e..2233d293a707 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -210,6 +210,8 @@ static int __set_legacy_tf(struct dc_transfer_func *func,
res = mod_color_calculate_regamma_params(func, gamma, true, has_rom,
 NULL);
 
+   dc_gamma_release();
+
return res ? 0 : -ENOMEM;
 }
 
-- 
2.20.1

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Re: [PATCH 00/26] Renoir DC Patches

[Harry Wentland]

Series is
Acked-by: Harry Wentland 

Harry

On 2019-10-09 5:05 p.m., Bhawanpreet Lakha wrote:
> Hi all,
> 
> There was a delta betwwen internal dcn21 code and upstream dcn21 code.
> These changes bring them inline.
> 
> 
> Summary of Changes
> *Add RN registors
> *Add dcn12 hwseq and link_encoder
> *RN specific fixes
> *aux timeout support
> *bounding box changes
> 
> Bhawanpreet Lakha (12):
>   drm/amd/display: Add DP_DPHY_INTERNAL_CTR regs
>   drm/amd/display: Add DCN_BASE regs
>   drm/amd/display: Add renoir hw_seq
>   drm/amd/display: create dcn21_link_encoder files
>   drm/amd/display: add REFCYC_PER_TRIP_TO_MEMORY programming
>   drm/amd/display: fix incorrect page table address for renoir
>   drm/amd/display: add detile buffer size for renoir
>   drm/amd/display: update dcn21 hubbub registers
>   drm/amd/display: update renoir bounding box and res_caps
>   drm/amd/display: change PP_SM defs to 8
>   drm/amd/display: handle "18" case in TruncToValidBPP
>   drm/amd/display: use requested_dispclk_khz instead of clk
> 
> Dmytro Laktyushkin (4):
>   drm/amd/display: enable hostvm based on roimmu active for dcn2.1
>   drm/amd/display: initialize RN gpuvm context programming function
>   drm/amd/display: correct dcn21 NUM_VMID to 16
>   drm/amd/display: update odm mode validation to be in line with policy
> 
> Eric Yang (2):
>   drm/amd/display: use dcn10 version of program tiling on Renoir
>   drm/amd/display: add sanity check for clk table from smu
> 
> Lewis Huang (3):
>   drm/amd/display: move the bounding box patch before calculate wm
>   drm/amd/display: Temporary workaround to toggle watermark setting
>   drm/amd/display: enable smu set dcfclk
> 
> Michael Strauss (1):
>   drm/amd/display: Fix rn audio playback and video playback speed
> 
> Sung Lee (1):
>   drm/amd/display: add dummy functions to smu for Renoir Silicon Diags
> 
> abdoulaye berthe (2):
>   drm/amd/display: update register field access mechanism
>   drm/amd/display: configurable aux timeout support
> 
> joseph gravenor (1):
>   drm/amd/display: fix header for RN clk mgr
> 
>  .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |  23 +-
>  .../dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c   |  19 +-
>  .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |  14 +
>  drivers/gpu/drm/amd/display/dc/dc.h   |   2 +
>  drivers/gpu/drm/amd/display/dc/dce/dce_aux.c  |  82 +++-
>  drivers/gpu/drm/amd/display/dc/dce/dce_aux.h  | 187 -
>  .../gpu/drm/amd/display/dc/dce/dce_hwseq.h|   1 +
>  .../amd/display/dc/dce100/dce100_resource.c   |  15 +-
>  .../amd/display/dc/dce110/dce110_resource.c   |  14 +-
>  .../amd/display/dc/dce112/dce112_resource.c   |  15 +-
>  .../amd/display/dc/dce120/dce120_resource.c   |  15 +-
>  .../drm/amd/display/dc/dce80/dce80_resource.c |  14 +-
>  .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |   4 +
>  .../amd/display/dc/dcn10/dcn10_link_encoder.h |  35 +-
>  .../drm/amd/display/dc/dcn10/dcn10_resource.c |  15 +-
>  .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|   4 +
>  .../amd/display/dc/dcn20/dcn20_link_encoder.h |   7 +
>  .../drm/amd/display/dc/dcn20/dcn20_resource.c |  31 +-
>  drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   2 +-
>  .../drm/amd/display/dc/dcn21/dcn21_hubbub.c   | 116 --
>  .../drm/amd/display/dc/dcn21/dcn21_hubbub.h   |  34 +-
>  .../gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c |   4 +-
>  .../drm/amd/display/dc/dcn21/dcn21_hwseq.c| 122 ++
>  .../drm/amd/display/dc/dcn21/dcn21_hwseq.h|  33 ++
>  .../amd/display/dc/dcn21/dcn21_link_encoder.c | 384 ++
>  .../amd/display/dc/dcn21/dcn21_link_encoder.h |  51 +++
>  .../drm/amd/display/dc/dcn21/dcn21_resource.c | 269 ++--
>  drivers/gpu/drm/amd/display/dc/dm_pp_smu.h|   6 +-
>  .../dc/dml/dcn21/display_mode_vba_21.c|  11 +-
>  .../gpu/drm/amd/display/dc/inc/dc_link_ddc.h  |   3 +
>  .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |   2 +
>  .../drm/amd/display/dc/inc/hw/aux_engine.h|   3 +
>  .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h  |   1 +
>  .../gpu/drm/amd/display/dc/inc/hw/mem_input.h |   1 +
>  .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   3 +
>  .../include/asic_reg/dcn/dcn_2_1_0_offset.h   |  10 +
>  .../gpu/drm/amd/include/renoir_ip_offset.h|  34 ++
>  37 files changed, 1461 insertions(+), 125 deletions(-)
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c
>  create mode 100644 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.h
> 
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[PATCH v3] drm/amdgpu: user pages array memory leak fix

[Yang, Philip]

user_pages array should always be freed after validation regardless if
user pages are changed after bo is created because with HMM change parse
bo always allocate user pages array to get user pages for userptr bo.

v2: remove unused local variable and amend commit

v3: add back get user pages in gem_userptr_ioctl, to detect application
bug where an userptr VMA is not ananymous memory and reject it.

Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962

Signed-off-by: Philip Yang 
Tested-by: Joe Barnett 
Reviewed-by: Christian König 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index c18a153b3d2a..e7b39daa22f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -476,7 +476,6 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser 
*p,
 
list_for_each_entry(lobj, validated, tv.head) {
struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
-   bool binding_userptr = false;
struct mm_struct *usermm;
 
usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
@@ -493,14 +492,13 @@ static int amdgpu_cs_list_validate(struct 
amdgpu_cs_parser *p,
 
amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
 lobj->user_pages);
-   binding_userptr = true;
}
 
r = amdgpu_cs_validate(p, bo);
if (r)
return r;
 
-   if (binding_userptr) {
+   if (lobj->user_pages) {
kvfree(lobj->user_pages);
lobj->user_pages = NULL;
}
-- 
2.17.1

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RE: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support dc

[Liang, Prike]

> -Original Message-
> From: amd-gfx  On Behalf Of
> Hersen Wu
> Sent: Thursday, October 10, 2019 10:58 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Wu, Hersen ; Wang, Kevin(Yang)
> ; Wentland, Harry 
> Subject: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support dc
> 
> there are two paths for renoir dc access smu.
> one dc access smu directly using bios smc
> interface: set disply, dprefclk, etc.
> another goes through pplib for get dpm clock table and set watermmark.
> 
> Signed-off-by: Hersen Wu 
> ---
>  .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  | 16 +---
>  drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 35 +++
>  .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 16 ++--
>  drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 96
> +++
>  drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 39 
>  5 files changed, 141 insertions(+), 61 deletions(-)
> 
> diff --git
> a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> index f4cfa0caeba8..95564b8de3ce 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
> @@ -589,10 +589,9 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
>   if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
>   pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,
> 
> _with_clock_ranges);
> - else if (adev->smu.funcs &&
> -  adev->smu.funcs->set_watermarks_for_clock_ranges)
> + else
>   smu_set_watermarks_for_clock_ranges(>smu,
> - _with_clock_ranges);
> + _with_clock_ranges);
>  }
> 
>  void pp_rv_set_pme_wa_enable(struct pp_smu *pp) @@ -665,7 +664,6
> @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,  {
>   const struct dc_context *ctx = pp->dm;
>   struct amdgpu_device *adev = ctx->driver_context;
> - struct smu_context *smu = >smu;
>   struct dm_pp_wm_sets_with_clock_ranges_soc15
> wm_with_clock_ranges;
>   struct dm_pp_clock_range_for_dmif_wm_set_soc15
> *wm_dce_clocks =
>   wm_with_clock_ranges.wm_dmif_clocks_ranges;
> @@ -708,15 +706,7 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct
> pp_smu *pp,
>   ranges->writer_wm_sets[i].min_drain_clk_mhz *
> 1000;
>   }
> 
> - if (!smu->funcs)
> - return PP_SMU_RESULT_UNSUPPORTED;
> -
> - /* 0: successful or smu.funcs->set_watermarks_for_clock_ranges =
> NULL;
> -  * 1: fail
> -  */
> - if (smu_set_watermarks_for_clock_ranges(>smu,
> - _with_clock_ranges))
> - return PP_SMU_RESULT_UNSUPPORTED;
> + smu_set_watermarks_for_clock_ranges(>smu,
>   _with_clock_ranges);
> 
>   return PP_SMU_RESULT_OK;
>  }
> diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> index c9266ea70331..1b71c38cdf96 100644
> --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
> @@ -1834,6 +1834,41 @@ int smu_set_mp1_state(struct smu_context *smu,
>   return ret;
>  }
> 
> +int smu_write_watermarks_table(struct smu_context *smu) {
> + int ret = 0;
> + struct smu_table_context *smu_table = >smu_table;
> + struct smu_table *table = NULL;
> +
> + table = _table->tables[SMU_TABLE_WATERMARKS];
> +
> + if (!table->cpu_addr)
> + return -EINVAL;
> +
> + ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table-
> >cpu_addr,
> + true);
> +
> + return ret;
> +}
> +
> +int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
> + struct dm_pp_wm_sets_with_clock_ranges_soc15
> *clock_ranges) {
> + int ret = 0;
> + struct smu_table *watermarks = 
> >smu_table.tables[SMU_TABLE_WATERMARKS];
> + void *table = watermarks->cpu_addr;
> +
> + if (!smu->disable_watermark &&
> + smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_DCEFCLK_BIT) &&
> + smu_feature_is_enabled(smu,
> SMU_FEATURE_DPM_SOCCLK_BIT)) {
> + smu_set_watermarks_table(smu, table, clock_ranges);
> + smu->watermarks_bitmap |= WATERMARKS_EXIST;
> + smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
> + }
> +
> + return ret;
> +}
> +
>  const struct amd_ip_funcs smu_ip_funcs = {
>   .name = "smu",
>   .early_init = smu_early_init,
> diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> index ccf711c327c8..1469146da1aa 100644
> --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
> @@ -468,6 +468,7 @@ struct pptable_funcs {
>   int (*get_power_limit)(struct smu_context *smu, uint32_t *limit,
> bool asic_default);
>   int (*get_dpm_clk_limited)(struct 

Re: [PATCH] drm/amdgpu/display: clean up dcn2*_pp_smu functions

[Harry Wentland]

On 2019-10-10 11:10 a.m., Alex Deucher wrote:
> Use the dcn21 functions in dcn21_resource.c and make the
> dcn20 functions static since they are only used in
> dcn20_resource now.
> 
> Cc: bhawanpreet.la...@amd.com
> Signed-off-by: Alex Deucher 

Reviewed-by: Harry Wentland 

Harry

> ---
>  drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 6 --
>  drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h | 3 ---
>  drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 4 +++-
>  3 files changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> index 7ace3b261d87..914e378bcda4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> @@ -1156,6 +1156,8 @@ static const struct resource_create_funcs 
> res_create_maximus_funcs = {
>   .create_hwseq = dcn20_hwseq_create,
>  };
>  
> +static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
> +
>  void dcn20_clock_source_destroy(struct clock_source **clk_src)
>  {
>   kfree(TO_DCE110_CLK_SRC(*clk_src));
> @@ -2928,7 +2930,7 @@ bool dcn20_mmhubbub_create(struct dc_context *ctx, 
> struct resource_pool *pool)
>   return true;
>  }
>  
> -struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
> +static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
>  {
>   struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
>  
> @@ -2943,7 +2945,7 @@ struct pp_smu_funcs *dcn20_pp_smu_create(struct 
> dc_context *ctx)
>   return pp_smu;
>  }
>  
> -void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
> +static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
>  {
>   if (pp_smu && *pp_smu) {
>   kfree(*pp_smu);
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h 
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
> index 44f95aa0d61e..55006462f481 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
> @@ -95,9 +95,6 @@ struct display_stream_compressor *dcn20_dsc_create(
>   struct dc_context *ctx, uint32_t inst);
>  void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
>  
> -struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx);
> -void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
> -
>  struct hubp *dcn20_hubp_create(
>   struct dc_context *ctx,
>   uint32_t inst);
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
> b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> index d2fc61490052..f0c95d82feb2 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
> @@ -636,6 +636,8 @@ static const struct dcn10_stream_encoder_mask se_mask = {
>   SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
>  };
>  
> +static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
> +
>  static struct input_pixel_processor *dcn21_ipp_create(
>   struct dc_context *ctx, uint32_t inst)
>  {
> @@ -939,7 +941,7 @@ static void destruct(struct dcn21_resource_pool *pool)
>   dcn_dccg_destroy(>base.dccg);
>  
>   if (pool->base.pp_smu != NULL)
> - dcn20_pp_smu_destroy(>base.pp_smu);
> + dcn21_pp_smu_destroy(>base.pp_smu);
>  }
>  
>  
> 
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Re: [PATCH] drm/amdgpu: user pages array memory leak fix

[Yang, Philip]

On 2019-10-11 4:40 a.m., Christian König wrote:
> Am 03.10.19 um 21:44 schrieb Yang, Philip:
>> user_pages array should always be freed after validation regardless if
>> user pages are changed after bo is created because with HMM change parse
>> bo always allocate user pages array to get user pages for userptr bo.
>>
>> Don't need to get user pages while creating uerptr bo because user pages
>> will only be used while validating after parsing userptr bo.
>>
>> Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962
>>
>> v2: remove unused local variable and amend commit
>>
>> Signed-off-by: Philip Yang 
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  4 +---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 23 +--
>>   2 files changed, 2 insertions(+), 25 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> index 49b767b7238f..961186e7113e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> @@ -474,7 +474,6 @@ static int amdgpu_cs_list_validate(struct 
>> amdgpu_cs_parser *p,
>>   list_for_each_entry(lobj, validated, tv.head) {
>>   struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
>> -    bool binding_userptr = false;
>>   struct mm_struct *usermm;
>>   usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
>> @@ -491,14 +490,13 @@ static int amdgpu_cs_list_validate(struct 
>> amdgpu_cs_parser *p,
>>   amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
>>    lobj->user_pages);
>> -    binding_userptr = true;
>>   }
>>   r = amdgpu_cs_validate(p, bo);
>>   if (r)
>>   return r;
>> -    if (binding_userptr) {
>> +    if (lobj->user_pages) {
>>   kvfree(lobj->user_pages);
>>   lobj->user_pages = NULL;
>>   }
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> index a828e3d0bfbd..3ccd61d69964 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
>> @@ -283,7 +283,6 @@ int amdgpu_gem_create_ioctl(struct drm_device 
>> *dev, void *data,
>>   int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
>>    struct drm_file *filp)
>>   {
>> -    struct ttm_operation_ctx ctx = { true, false };
>>   struct amdgpu_device *adev = dev->dev_private;
>>   struct drm_amdgpu_gem_userptr *args = data;
>>   struct drm_gem_object *gobj;
>> @@ -326,32 +325,12 @@ int amdgpu_gem_userptr_ioctl(struct drm_device 
>> *dev, void *data,
>>   goto release_object;
>>   }
>> -    if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
> 
> We can't drop that handling here, it is mandatory to detect an 
> application bug where an application tries to user an userptr with a VMA 
> which is not anonymous memory.
> 
> This must be detected and rejected as invalid here.
> 
> I suggest that we allocate a local pages array similar to how we do it 
> during CS and release that after the function is done.
> 
Thanks for this, we can use bo->tbo.ttm->pages array here to avoid extra 
alloc/free of pages array because CS uses local pages array and update 
to bo->tbo.ttm->pages if user pages are moved. I will submit patch v3 
for review.

> Regards,
> Christian.
> 
>> -    r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
>> -    if (r)
>> -    goto release_object;
>> -
>> -    r = amdgpu_bo_reserve(bo, true);
>> -    if (r)
>> -    goto user_pages_done;
>> -
>> -    amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
>> -    r = ttm_bo_validate(>tbo, >placement, );
>> -    amdgpu_bo_unreserve(bo);
>> -    if (r)
>> -    goto user_pages_done;
>> -    }
>> -
>>   r = drm_gem_handle_create(filp, gobj, );
>>   if (r)
>> -    goto user_pages_done;
>> +    goto release_object;
>>   args->handle = handle;
>> -user_pages_done:
>> -    if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
>> -    amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
>> -
>>   release_object:
>>   drm_gem_object_put_unlocked(gobj);
> 
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RE: [PATCH 1/4] drm/amdgpu/soc15: disable doorbell interrupt as part of BACO entry sequence

[Zhang, Hawking]

Series is
Reviewed-by: Hawking Zhang 

Regards,
Hawking
-Original Message-
From: amd-gfx  On Behalf Of Le Ma
Sent: 2019年10月11日 19:10
To: amd-gfx@lists.freedesktop.org
Cc: Ma, Le 
Subject: [PATCH 1/4] drm/amdgpu/soc15: disable doorbell interrupt as part of 
BACO entry sequence

Workaround to make RAS recovery work in BACO reset.

Change-Id: I4e4a81f719dcc88dfd49f583c4be3a373b5eab2c
Signed-off-by: Le Ma 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c   | 8 
 drivers/gpu/drm/amd/amdgpu/soc15.c   | 9 +
 3 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
index 1f26a17..919bd56 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
@@ -67,6 +67,8 @@ struct amdgpu_nbio_funcs {
  bool enable);
void (*ih_doorbell_range)(struct amdgpu_device *adev,
  bool use_doorbell, int doorbell_index);
+   void (*enable_doorbell_interrupt)(struct amdgpu_device *adev,
+ bool enable);
void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
 bool enable);
void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev, 
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 238c248..0db458f 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -502,6 +502,13 @@ static void nbio_v7_4_query_ras_error_count(struct 
amdgpu_device *adev,
}
 }
 
+static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev,
+   bool enable)
+{
+   WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL,
+  DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1); }
+
 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
@@ -516,6 +523,7 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
.enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
.enable_doorbell_selfring_aperture = 
nbio_v7_4_enable_doorbell_selfring_aperture,
.ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
+   .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt,
.update_medium_grain_clock_gating = 
nbio_v7_4_update_medium_grain_clock_gating,
.update_medium_grain_light_sleep = 
nbio_v7_4_update_medium_grain_light_sleep,
.get_clockgating_state = nbio_v7_4_get_clockgating_state, diff --git 
a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index fc6cfbc..5cf5f11 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -493,10 +493,15 @@ static int soc15_asic_baco_reset(struct amdgpu_device 
*adev)  {
void *pp_handle = adev->powerplay.pp_handle;
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+   struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 
if (!pp_funcs ||!pp_funcs->get_asic_baco_state 
||!pp_funcs->set_asic_baco_state)
return -ENOENT;
 
+   /* avoid NBIF got stuck when do RAS recovery in BACO reset */
+   if (ras && ras->supported)
+   adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
+
/* enter BACO state */
if (pp_funcs->set_asic_baco_state(pp_handle, 1))
return -EIO;
@@ -505,6 +510,10 @@ static int soc15_asic_baco_reset(struct amdgpu_device 
*adev)
if (pp_funcs->set_asic_baco_state(pp_handle, 0))
return -EIO;
 
+   /* re-enable doorbell interrupt after BACO exit */
+   if (ras && ras->supported)
+   adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
+
dev_info(adev->dev, "GPU BACO reset\n");
 
adev->in_baco_reset = 1;
--
2.7.4

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Re: [PATCH 4/4] drm/amd/powerplay: add BACO platformCaps for VEGA20

[Alex Deucher]

Series is:
Reviewed-by: Alex Deucher 

On Fri, Oct 11, 2019 at 7:10 AM Le Ma  wrote:
>
> BACO reset is needed for RAS recovery.
>
> Change-Id: I8207fc314744468c89ba4a030cb2bb15b082aac7
> Signed-off-by: Le Ma 
> ---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> index 6629c475..3d3c647 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> @@ -183,6 +183,9 @@ static int vega20_set_features_platform_caps(struct 
> pp_hwmgr *hwmgr)
> PHM_PlatformCaps_TablelessHardwareInterface);
>
> phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> +   PHM_PlatformCaps_BACO);
> +
> +   phm_cap_set(hwmgr->platform_descriptor.platformCaps,
> PHM_PlatformCaps_EnableSMU7ThermalManagement);
>
> if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
> --
> 2.7.4
>
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Re: [PATCH 3/3] drm/amdgpu: add RAS support for VML2 and ATCL2

[Alex Deucher]

On Thu, Oct 10, 2019 at 10:50 PM Dennis Li  wrote:
>
> Add codes to query the EDC count of VML2 & ATCL2
>
> Change-Id: If2c251481ba0a1a34ce3405a85f86d65eecee461
> Signed-off-by: Dennis Li 

Series is:
Acked-by: Alex Deucher 

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 167 ++
>  1 file changed, 167 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 2a95093b85a5..22be6177938e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -6152,6 +6152,171 @@ static int gfx_v9_0_ras_error_inject(struct 
> amdgpu_device *adev,
> return ret;
>  }
>
> +static const char *vml2_mems[] = {
> +   "UTC_VML2_BANK_CACHE_0_BIGK_MEM0",
> +   "UTC_VML2_BANK_CACHE_0_BIGK_MEM1",
> +   "UTC_VML2_BANK_CACHE_0_4K_MEM0",
> +   "UTC_VML2_BANK_CACHE_0_4K_MEM1",
> +   "UTC_VML2_BANK_CACHE_1_BIGK_MEM0",
> +   "UTC_VML2_BANK_CACHE_1_BIGK_MEM1",
> +   "UTC_VML2_BANK_CACHE_1_4K_MEM0",
> +   "UTC_VML2_BANK_CACHE_1_4K_MEM1",
> +   "UTC_VML2_BANK_CACHE_2_BIGK_MEM0",
> +   "UTC_VML2_BANK_CACHE_2_BIGK_MEM1",
> +   "UTC_VML2_BANK_CACHE_2_4K_MEM0",
> +   "UTC_VML2_BANK_CACHE_2_4K_MEM1",
> +   "UTC_VML2_BANK_CACHE_3_BIGK_MEM0",
> +   "UTC_VML2_BANK_CACHE_3_BIGK_MEM1",
> +   "UTC_VML2_BANK_CACHE_3_4K_MEM0",
> +   "UTC_VML2_BANK_CACHE_3_4K_MEM1",
> +};
> +
> +static const char *vml2_walker_mems[] = {
> +   "UTC_VML2_CACHE_PDE0_MEM0",
> +   "UTC_VML2_CACHE_PDE0_MEM1",
> +   "UTC_VML2_CACHE_PDE1_MEM0",
> +   "UTC_VML2_CACHE_PDE1_MEM1",
> +   "UTC_VML2_CACHE_PDE2_MEM0",
> +   "UTC_VML2_CACHE_PDE2_MEM1",
> +   "UTC_VML2_RDIF_LOG_FIFO",
> +};
> +
> +static const char *atc_l2_cache_2m_mems[] = {
> +   "UTC_ATCL2_CACHE_2M_BANK0_WAY0_MEM",
> +   "UTC_ATCL2_CACHE_2M_BANK0_WAY1_MEM",
> +   "UTC_ATCL2_CACHE_2M_BANK1_WAY0_MEM",
> +   "UTC_ATCL2_CACHE_2M_BANK1_WAY1_MEM",
> +};
> +
> +static const char *atc_l2_cache_4k_mems[] = {
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0",
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1",
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2",
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3",
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4",
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5",
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6",
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7",
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0",
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1",
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2",
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3",
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4",
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5",
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6",
> +   "UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6",
> +   "UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7",
> +};
> +
> +static int gfx_v9_0_query_utc_edc_status(struct amdgpu_device *adev,
> +struct ras_err_data *err_data)
> +{
> +   uint32_t i, data;
> +   uint32_t sec_count, ded_count;
> +
> +   WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, 255);
> +   WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT, 0);
> +   WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_INDEX, 255);
> +   WREG32_SOC15(GC, 0, mmVM_L2_WALKER_MEM_ECC_CNT, 0);
> +   WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_INDEX, 255);
> +   WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_EDC_CNT, 0);
> +   WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_INDEX, 255);
> +   WREG32_SOC15(GC, 0, mmATC_L2_CACHE_4K_EDC_CNT, 0);
> +
> +   for (i = 0; i < 16; i++) {
> +   WREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_INDEX, i);
> +   data = RREG32_SOC15(GC, 0, mmVM_L2_MEM_ECC_CNT);
> +
> +   sec_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, SEC_COUNT);
> +   if (sec_count) {
> +   DRM_INFO("Instance[%d]: SubBlock %s, SEC %d\n", i,
> +vml2_mems[i], sec_count);
> +   err_data->ce_count += sec_count;
> +   }
> +
> +   ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT);
> +   if (ded_count) {
> +   

Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit

[Wang, Kevin(Yang)]

Reviewed-by: Kevin Wang 


From: Feng, Kenneth 
Sent: Thursday, October 10, 2019 3:00 PM
To: Yuan, Xiaojie ; Deucher, Alexander 
; amd-gfx@lists.freedesktop.org 

Cc: Xiao, Jack ; Wang, Kevin(Yang) ; 
Zhang, Hawking ; Quan, Evan 
Subject: RE: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit


Hi Alex,

This issue was navi10 specific and was found in May, 2019.

It was early after the asic back, then since gfxoff was removed from navi10, we 
didn’t really verify which firmware version started to have a fix.

For navi14/navi12, there’s no such issue at all.

Sorry for losing the track of it.





From: Yuan, Xiaojie
Sent: Thursday, October 10, 2019 1:17 AM
To: Deucher, Alexander ; 
amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Wang, Kevin(Yang) ; 
Zhang, Hawking ; Quan, Evan ; Feng, 
Kenneth 
Subject: Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit



Hi Alex,



For now, gfxoff for navi10 is disabled by default, and I also verified on 
navi14 with both GFXOFF and FW_DSTATE feature bits toggled on.



Hi Kenneth / Jack,



Could you help to confirm the firmware version?



BR,

Xiaojie



From: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Sent: Wednesday, October 9, 2019 9:35 PM
To: Yuan, Xiaojie mailto:xiaojie.y...@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Xiao, Jack mailto:jack.x...@amd.com>>; Wang, Kevin(Yang) 
mailto:kevin1.w...@amd.com>>; Zhang, Hawking 
mailto:hawking.zh...@amd.com>>; Quan, Evan 
mailto:evan.q...@amd.com>>; Feng, Kenneth 
mailto:kenneth.f...@amd.com>>
Subject: Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit



What version of firmware has the fix?  Was it recently fixed?  We should check 
the version if the old one may be out in the wild.



Alex



From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Yuan, Xiaojie mailto:xiaojie.y...@amd.com>>
Sent: Wednesday, October 9, 2019 7:08 AM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Xiao, Jack mailto:jack.x...@amd.com>>; Wang, Kevin(Yang) 
mailto:kevin1.w...@amd.com>>; Zhang, Hawking 
mailto:hawking.zh...@amd.com>>; Quan, Evan 
mailto:evan.q...@amd.com>>; Feng, Kenneth 
mailto:kenneth.f...@amd.com>>; Yuan, Xiaojie 
mailto:xiaojie.y...@amd.com>>
Subject: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit



SMU firmware has fix the bug, so remove this workaround.

Signed-off-by: Xiaojie Yuan mailto:xiaojie.y...@amd.com>>
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 44152c1f01c7..3628295469c4 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -359,11 +359,8 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);

-   if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
+   if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
-   /* TODO: remove it once fw fix the bug */
-   *(uint64_t *)feature_mask &= 
~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
-   }

 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 *(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
--
2.20.1

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Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit

[Deucher, Alexander]

Acked-by: Alex Deucher 

From: Yuan, Xiaojie 
Sent: Friday, October 11, 2019 4:20 AM
To: Deucher, Alexander ; Feng, Kenneth 
; amd-gfx@lists.freedesktop.org 

Cc: Xiao, Jack ; Wang, Kevin(Yang) ; 
Zhang, Hawking ; Quan, Evan 
Subject: Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit

Hi there,

Could someone give an RB or ACK? This patch has been verified on both navi12 
and navi14.
Thanks.

BR,
Xiaojie

From: Deucher, Alexander 
Sent: Thursday, October 10, 2019 8:20 PM
To: Feng, Kenneth ; Yuan, Xiaojie ; 
amd-gfx@lists.freedesktop.org 
Cc: Xiao, Jack ; Wang, Kevin(Yang) ; 
Zhang, Hawking ; Quan, Evan 
Subject: Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit

Great.  thanks!

Alex

From: Feng, Kenneth 
Sent: Thursday, October 10, 2019 3:00 AM
To: Yuan, Xiaojie ; Deucher, Alexander 
; amd-gfx@lists.freedesktop.org 

Cc: Xiao, Jack ; Wang, Kevin(Yang) ; 
Zhang, Hawking ; Quan, Evan 
Subject: RE: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit


Hi Alex,

This issue was navi10 specific and was found in May, 2019.

It was early after the asic back, then since gfxoff was removed from navi10, we 
didn’t really verify which firmware version started to have a fix.

For navi14/navi12, there’s no such issue at all.

Sorry for losing the track of it.





From: Yuan, Xiaojie
Sent: Thursday, October 10, 2019 1:17 AM
To: Deucher, Alexander ; 
amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Wang, Kevin(Yang) ; 
Zhang, Hawking ; Quan, Evan ; Feng, 
Kenneth 
Subject: Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit



Hi Alex,



For now, gfxoff for navi10 is disabled by default, and I also verified on 
navi14 with both GFXOFF and FW_DSTATE feature bits toggled on.



Hi Kenneth / Jack,



Could you help to confirm the firmware version?



BR,

Xiaojie



From: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Sent: Wednesday, October 9, 2019 9:35 PM
To: Yuan, Xiaojie mailto:xiaojie.y...@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Xiao, Jack mailto:jack.x...@amd.com>>; Wang, Kevin(Yang) 
mailto:kevin1.w...@amd.com>>; Zhang, Hawking 
mailto:hawking.zh...@amd.com>>; Quan, Evan 
mailto:evan.q...@amd.com>>; Feng, Kenneth 
mailto:kenneth.f...@amd.com>>
Subject: Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit



What version of firmware has the fix?  Was it recently fixed?  We should check 
the version if the old one may be out in the wild.



Alex



From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Yuan, Xiaojie mailto:xiaojie.y...@amd.com>>
Sent: Wednesday, October 9, 2019 7:08 AM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Xiao, Jack mailto:jack.x...@amd.com>>; Wang, Kevin(Yang) 
mailto:kevin1.w...@amd.com>>; Zhang, Hawking 
mailto:hawking.zh...@amd.com>>; Quan, Evan 
mailto:evan.q...@amd.com>>; Feng, Kenneth 
mailto:kenneth.f...@amd.com>>; Yuan, Xiaojie 
mailto:xiaojie.y...@amd.com>>
Subject: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit



SMU firmware has fix the bug, so remove this workaround.

Signed-off-by: Xiaojie Yuan mailto:xiaojie.y...@amd.com>>
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 44152c1f01c7..3628295469c4 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -359,11 +359,8 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);

-   if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
+   if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
-   /* TODO: remove it once fw fix the bug */
-   *(uint64_t *)feature_mask &= 
~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
-   }

 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 *(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
--
2.20.1

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Re: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support dc

[Wang, Kevin(Yang)]

it looks fine for me.

Reviewed-by: Kevin Wang 

Best Regards,
Kevin


From: Hersen Wu 
Sent: Thursday, October 10, 2019 10:58 PM
To: amd-gfx@lists.freedesktop.org 
Cc: Wentland, Harry ; Wang, Kevin(Yang) 
; Wu, Hersen 
Subject: [PATCH] drm/amdgpu/powerplay: add renoir funcs to support dc

there are two paths for renoir dc access smu.
one dc access smu directly using bios smc
interface: set disply, dprefclk, etc.
another goes through pplib for get dpm clock
table and set watermmark.

Signed-off-by: Hersen Wu 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c  | 16 +---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 35 +++
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h| 16 ++--
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c| 96 +++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 39 
 5 files changed, 141 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index f4cfa0caeba8..95564b8de3ce 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -589,10 +589,9 @@ void pp_rv_set_wm_ranges(struct pp_smu *pp,
 if (pp_funcs && pp_funcs->set_watermarks_for_clocks_ranges)
 pp_funcs->set_watermarks_for_clocks_ranges(pp_handle,

_with_clock_ranges);
-   else if (adev->smu.funcs &&
-adev->smu.funcs->set_watermarks_for_clock_ranges)
+   else
 smu_set_watermarks_for_clock_ranges(>smu,
-   _with_clock_ranges);
+   _with_clock_ranges);
 }

 void pp_rv_set_pme_wa_enable(struct pp_smu *pp)
@@ -665,7 +664,6 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
 {
 const struct dc_context *ctx = pp->dm;
 struct amdgpu_device *adev = ctx->driver_context;
-   struct smu_context *smu = >smu;
 struct dm_pp_wm_sets_with_clock_ranges_soc15 wm_with_clock_ranges;
 struct dm_pp_clock_range_for_dmif_wm_set_soc15 *wm_dce_clocks =
 wm_with_clock_ranges.wm_dmif_clocks_ranges;
@@ -708,15 +706,7 @@ enum pp_smu_status pp_nv_set_wm_ranges(struct pp_smu *pp,
 ranges->writer_wm_sets[i].min_drain_clk_mhz * 1000;
 }

-   if (!smu->funcs)
-   return PP_SMU_RESULT_UNSUPPORTED;
-
-   /* 0: successful or smu.funcs->set_watermarks_for_clock_ranges = NULL;
-* 1: fail
-*/
-   if (smu_set_watermarks_for_clock_ranges(>smu,
-   _with_clock_ranges))
-   return PP_SMU_RESULT_UNSUPPORTED;
+   smu_set_watermarks_for_clock_ranges(>smu, _with_clock_ranges);

 return PP_SMU_RESULT_OK;
 }
diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c9266ea70331..1b71c38cdf96 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1834,6 +1834,41 @@ int smu_set_mp1_state(struct smu_context *smu,
 return ret;
 }

+int smu_write_watermarks_table(struct smu_context *smu)
+{
+   int ret = 0;
+   struct smu_table_context *smu_table = >smu_table;
+   struct smu_table *table = NULL;
+
+   table = _table->tables[SMU_TABLE_WATERMARKS];
+
+   if (!table->cpu_addr)
+   return -EINVAL;
+
+   ret = smu_update_table(smu, SMU_TABLE_WATERMARKS, 0, table->cpu_addr,
+   true);
+
+   return ret;
+}
+
+int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
+   struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
+{
+   int ret = 0;
+   struct smu_table *watermarks = 
>smu_table.tables[SMU_TABLE_WATERMARKS];
+   void *table = watermarks->cpu_addr;
+
+   if (!smu->disable_watermark &&
+   smu_feature_is_enabled(smu, 
SMU_FEATURE_DPM_DCEFCLK_BIT) &&
+   smu_feature_is_enabled(smu, 
SMU_FEATURE_DPM_SOCCLK_BIT)) {
+   smu_set_watermarks_table(smu, table, clock_ranges);
+   smu->watermarks_bitmap |= WATERMARKS_EXIST;
+   smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
+   }
+
+   return ret;
+}
+
 const struct amd_ip_funcs smu_ip_funcs = {
 .name = "smu",
 .early_init = smu_early_init,
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ccf711c327c8..1469146da1aa 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -468,6 +468,7 @@ struct pptable_funcs {
 int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool 
asic_default);
 int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type 

Re: [PATCH v2] drm/amdgpu/discovery: reserve discovery data at the top of VRAM

[Deucher, Alexander]

Reviewed-by: Alex Deucher 

From: amd-gfx  on behalf of Yuan, 
Xiaojie 
Sent: Friday, October 11, 2019 12:09 AM
To: amd-gfx@lists.freedesktop.org 
Cc: alexdeuc...@gmail.com ; Xiao, Jack 
; Yuan, Xiaojie ; Zhang, Hawking 

Subject: [PATCH v2] drm/amdgpu/discovery: reserve discovery data at the top of 
VRAM

IP Discovery data is TMR fenced by the latest PSP BL,
so we need to reserve this region.

Tested on navi10/12/14 with VBIOS integrated with latest PSP BL.

v2: use DISCOVERY_TMR_SIZE macro as bo size
use amdgpu_bo_create_kernel_at() to allocate bo

Signed-off-by: Xiaojie Yuan 
Reviewed-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c |  4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c   | 17 +
 drivers/gpu/drm/amd/include/discovery.h   |  1 -
 5 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index be0b2c69c223..6775647f0ba5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -812,6 +812,7 @@ struct amdgpu_device {
 uint8_t *bios;
 uint32_tbios_size;
 struct amdgpu_bo*stolen_vga_memory;
+   struct amdgpu_bo*discovery_memory;
 uint32_tbios_scratch_reg_offset;
 uint32_tbios_scratch[AMDGPU_BIOS_NUM_SCRATCH];

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 1481899f86c1..71198c5318e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -136,7 +136,7 @@ static int amdgpu_discovery_read_binary(struct 
amdgpu_device *adev, uint8_t *bin
 {
 uint32_t *p = (uint32_t *)binary;
 uint64_t vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20;
-   uint64_t pos = vram_size - BINARY_MAX_SIZE;
+   uint64_t pos = vram_size - DISCOVERY_TMR_SIZE;
 unsigned long flags;

 while (pos < vram_size) {
@@ -179,7 +179,7 @@ int amdgpu_discovery_init(struct amdgpu_device *adev)
 uint16_t checksum;
 int r;

-   adev->discovery = kzalloc(BINARY_MAX_SIZE, GFP_KERNEL);
+   adev->discovery = kzalloc(DISCOVERY_TMR_SIZE, GFP_KERNEL);
 if (!adev->discovery)
 return -ENOMEM;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
index 85b8c4d4d576..5a6693d7d269 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
@@ -24,6 +24,8 @@
 #ifndef __AMDGPU_DISCOVERY__
 #define __AMDGPU_DISCOVERY__

+#define DISCOVERY_TMR_SIZE  (64 << 10)
+
 int amdgpu_discovery_init(struct amdgpu_device *adev);
 void amdgpu_discovery_fini(struct amdgpu_device *adev);
 int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index edffc883549a..ed7b10e0848d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1955,6 +1955,20 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 NULL, _vga_buf);
 if (r)
 return r;
+
+   /*
+* reserve one TMR (64K) memory at the top of VRAM which holds
+* IP Discovery data and is protected by PSP.
+*/
+   r = amdgpu_bo_create_kernel_at(adev,
+  adev->gmc.real_vram_size - 
DISCOVERY_TMR_SIZE,
+  DISCOVERY_TMR_SIZE,
+  AMDGPU_GEM_DOMAIN_VRAM,
+  >discovery_memory,
+  NULL);
+   if (r)
+   return r;
+
 DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));

@@ -2024,6 +2038,9 @@ void amdgpu_ttm_late_init(struct amdgpu_device *adev)
 void *stolen_vga_buf;
 /* return the VGA stolen memory (if any) back to VRAM */
 amdgpu_bo_free_kernel(>stolen_vga_memory, NULL, _vga_buf);
+
+   /* return the IP Discovery TMR memory back to VRAM */
+   amdgpu_bo_free_kernel(>discovery_memory, NULL, NULL);
 }

 /**
diff --git a/drivers/gpu/drm/amd/include/discovery.h 
b/drivers/gpu/drm/amd/include/discovery.h
index 5dcb776548d8..7ec4331e67f2 100644
--- a/drivers/gpu/drm/amd/include/discovery.h
+++ b/drivers/gpu/drm/amd/include/discovery.h
@@ -25,7 +25,6 @@
 #define _DISCOVERY_H_

 #define PSP_HEADER_SIZE 256
-#define BINARY_MAX_SIZE (64 << 10)
 #define BINARY_SIGNATURE

Re: [PATCH] drm/amdgpu: Bail earlier when amdgpu.cik_/si_support is not set to 1

[Alex Deucher]

On Fri, Oct 11, 2019 at 5:27 AM Hans de Goede  wrote:
>
> Hi,
>
> On 10-10-2019 18:59, Daniel Vetter wrote:
> > On Thu, Oct 10, 2019 at 6:28 PM Hans de Goede  wrote:
> >>
> >> Bail from the pci_driver probe function instead of from the drm_driver
> >> load function.
> >>
> >> This avoid /dev/dri/card0 temporarily getting registered and then
> >> unregistered again, sending unwanted add / remove udev events to
> >> userspace.
> >>
> >> Specifically this avoids triggering the (userspace) bug fixed by this
> >> plymouth merge-request:
> >> https://gitlab.freedesktop.org/plymouth/plymouth/merge_requests/59
> >>
> >> Note that despite that being a userspace bug, not sending unnecessary
> >> udev events is a good idea in general.
> >
> > I think even better would be getting rid of the load/unload callbacks,
> > this issue here isn't the only problem with them.
> >
> > Reviewed-by: Daniel Vetter 
>
> Thanks,
>
> > I guess also cc: stable material?
>
> Yes.
>
> amdgpu maintainers, can you please add a Cc: stable while merging?
> Let me know if you want a new version with this added.

I'll take care of it when I merge this.  Thanks!

Alex

>
> Regards,
>
> Hans
>
>
>
> >> BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1490490
> >> Signed-off-by: Hans de Goede 
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 35 +
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 35 -
> >>   2 files changed, 35 insertions(+), 35 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> index 6f8aaf655a9f..2a00a36106b2 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> >> @@ -1048,6 +1048,41 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
> >>  return -ENODEV;
> >>  }
> >>
> >> +#ifdef CONFIG_DRM_AMDGPU_SI
> >> +   if (!amdgpu_si_support) {
> >> +   switch (flags & AMD_ASIC_MASK) {
> >> +   case CHIP_TAHITI:
> >> +   case CHIP_PITCAIRN:
> >> +   case CHIP_VERDE:
> >> +   case CHIP_OLAND:
> >> +   case CHIP_HAINAN:
> >> +   dev_info(>dev,
> >> +"SI support provided by radeon.\n");
> >> +   dev_info(>dev,
> >> +"Use radeon.si_support=0 
> >> amdgpu.si_support=1 to override.\n"
> >> +   );
> >> +   return -ENODEV;
> >> +   }
> >> +   }
> >> +#endif
> >> +#ifdef CONFIG_DRM_AMDGPU_CIK
> >> +   if (!amdgpu_cik_support) {
> >> +   switch (flags & AMD_ASIC_MASK) {
> >> +   case CHIP_KAVERI:
> >> +   case CHIP_BONAIRE:
> >> +   case CHIP_HAWAII:
> >> +   case CHIP_KABINI:
> >> +   case CHIP_MULLINS:
> >> +   dev_info(>dev,
> >> +"CIK support provided by radeon.\n");
> >> +   dev_info(>dev,
> >> +"Use radeon.cik_support=0 
> >> amdgpu.cik_support=1 to override.\n"
> >> +   );
> >> +   return -ENODEV;
> >> +   }
> >> +   }
> >> +#endif
> >> +
> >>  /* Get rid of things like offb */
> >>  ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, 
> >> "amdgpudrmfb");
> >>  if (ret)
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
> >> b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> >> index f2c097983f48..d55f5baa83d3 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
> >> @@ -144,41 +144,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, 
> >> unsigned long flags)
> >>  struct amdgpu_device *adev;
> >>  int r, acpi_status;
> >>
> >> -#ifdef CONFIG_DRM_AMDGPU_SI
> >> -   if (!amdgpu_si_support) {
> >> -   switch (flags & AMD_ASIC_MASK) {
> >> -   case CHIP_TAHITI:
> >> -   case CHIP_PITCAIRN:
> >> -   case CHIP_VERDE:
> >> -   case CHIP_OLAND:
> >> -   case CHIP_HAINAN:
> >> -   dev_info(dev->dev,
> >> -"SI support provided by radeon.\n");
> >> -   dev_info(dev->dev,
> >> -"Use radeon.si_support=0 
> >> amdgpu.si_support=1 to override.\n"
> >> -   );
> >> -   return -ENODEV;
> >> -   }
> >> -   }
> >> -#endif
> >> -#ifdef CONFIG_DRM_AMDGPU_CIK
> >> -   if (!amdgpu_cik_support) {
> >> -   switch (flags & AMD_ASIC_MASK) {
> >> -   case CHIP_KAVERI:
> >> -   case CHIP_BONAIRE:
> >> -   case CHIP_HAWAII:
> >> -   case CHIP_KABINI:
> >> - 

Re: [PATCH 2/5] drm/amdgpu: move gpu reset out of amdgpu_device_suspend

[Alex Deucher]

On Fri, Oct 11, 2019 at 12:07 AM Quan, Evan  wrote:
>
> It seems amdgpu_pmops_runtime_suspend() needs to be updated accordingly also.

I purposely left that out.  I think that is a bug.  We don't need to
reset the GPU for runtime suspend.  We only need it for hibernation
because of the whole freeze/thaw dance.

Alex

>
> -Original Message-
> From: amd-gfx  On Behalf Of Alex 
> Deucher
> Sent: Thursday, October 10, 2019 11:26 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: [PATCH 2/5] drm/amdgpu: move gpu reset out of amdgpu_device_suspend
>
> Move it into the caller.  There are cases were we don't
> want it.  We need it for hibernation, but we don't need
> it for runtime pm.
>
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 7 ++-
>  2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 9b9b15360194..91bdb246e405 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3173,10 +3173,6 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
> suspend, bool fbcon)
> /* Shut down the device */
> pci_disable_device(dev->pdev);
> pci_set_power_state(dev->pdev, PCI_D3hot);
> -   } else {
> -   r = amdgpu_asic_reset(adev);
> -   if (r)
> -   DRM_ERROR("amdgpu asic reset failed\n");
> }
>
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index d43c46de7807..64141386e603 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1118,8 +1118,13 @@ static int amdgpu_pmops_resume(struct device *dev)
>  static int amdgpu_pmops_freeze(struct device *dev)
>  {
> struct drm_device *drm_dev = dev_get_drvdata(dev);
> +   struct amdgpu_device *adev = drm_dev->dev_private;
> +   int r;
>
> -   return amdgpu_device_suspend(drm_dev, false, true);
> +   r = amdgpu_device_suspend(drm_dev, false, true);
> +   if (r)
> +   return r;
> +   return amdgpu_asic_reset(adev);
>  }
>
>  static int amdgpu_pmops_thaw(struct device *dev)
> --
> 2.20.1
>
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Re: [PATCH] drm/amdgpu: Bail earlier when amdgpu.cik_/si_support is not set to 1

[Hans de Goede]

Hi,

On 10-10-2019 18:59, Daniel Vetter wrote:

On Thu, Oct 10, 2019 at 6:28 PM Hans de Goede  wrote:


Bail from the pci_driver probe function instead of from the drm_driver
load function.

This avoid /dev/dri/card0 temporarily getting registered and then
unregistered again, sending unwanted add / remove udev events to
userspace.

Specifically this avoids triggering the (userspace) bug fixed by this
plymouth merge-request:
https://gitlab.freedesktop.org/plymouth/plymouth/merge_requests/59

Note that despite that being a userspace bug, not sending unnecessary
udev events is a good idea in general.


I think even better would be getting rid of the load/unload callbacks,
this issue here isn't the only problem with them.

Reviewed-by: Daniel Vetter 


Thanks,


I guess also cc: stable material?


Yes.

amdgpu maintainers, can you please add a Cc: stable while merging?
Let me know if you want a new version with this added.

Regards,

Hans




BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1490490
Signed-off-by: Hans de Goede 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 35 +
  drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 35 -
  2 files changed, 35 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 6f8aaf655a9f..2a00a36106b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1048,6 +1048,41 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
 return -ENODEV;
 }

+#ifdef CONFIG_DRM_AMDGPU_SI
+   if (!amdgpu_si_support) {
+   switch (flags & AMD_ASIC_MASK) {
+   case CHIP_TAHITI:
+   case CHIP_PITCAIRN:
+   case CHIP_VERDE:
+   case CHIP_OLAND:
+   case CHIP_HAINAN:
+   dev_info(>dev,
+"SI support provided by radeon.\n");
+   dev_info(>dev,
+"Use radeon.si_support=0 amdgpu.si_support=1 to 
override.\n"
+   );
+   return -ENODEV;
+   }
+   }
+#endif
+#ifdef CONFIG_DRM_AMDGPU_CIK
+   if (!amdgpu_cik_support) {
+   switch (flags & AMD_ASIC_MASK) {
+   case CHIP_KAVERI:
+   case CHIP_BONAIRE:
+   case CHIP_HAWAII:
+   case CHIP_KABINI:
+   case CHIP_MULLINS:
+   dev_info(>dev,
+"CIK support provided by radeon.\n");
+   dev_info(>dev,
+"Use radeon.cik_support=0 amdgpu.cik_support=1 to 
override.\n"
+   );
+   return -ENODEV;
+   }
+   }
+#endif
+
 /* Get rid of things like offb */
 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, 
"amdgpudrmfb");
 if (ret)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index f2c097983f48..d55f5baa83d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -144,41 +144,6 @@ int amdgpu_driver_load_kms(struct drm_device *dev, 
unsigned long flags)
 struct amdgpu_device *adev;
 int r, acpi_status;

-#ifdef CONFIG_DRM_AMDGPU_SI
-   if (!amdgpu_si_support) {
-   switch (flags & AMD_ASIC_MASK) {
-   case CHIP_TAHITI:
-   case CHIP_PITCAIRN:
-   case CHIP_VERDE:
-   case CHIP_OLAND:
-   case CHIP_HAINAN:
-   dev_info(dev->dev,
-"SI support provided by radeon.\n");
-   dev_info(dev->dev,
-"Use radeon.si_support=0 amdgpu.si_support=1 to 
override.\n"
-   );
-   return -ENODEV;
-   }
-   }
-#endif
-#ifdef CONFIG_DRM_AMDGPU_CIK
-   if (!amdgpu_cik_support) {
-   switch (flags & AMD_ASIC_MASK) {
-   case CHIP_KAVERI:
-   case CHIP_BONAIRE:
-   case CHIP_HAWAII:
-   case CHIP_KABINI:
-   case CHIP_MULLINS:
-   dev_info(dev->dev,
-"CIK support provided by radeon.\n");
-   dev_info(dev->dev,
-"Use radeon.cik_support=0 amdgpu.cik_support=1 to 
override.\n"
-   );
-   return -ENODEV;
-   }
-   }
-#endif
-
 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
 if (adev == NULL) {
 return -ENOMEM;
--
2.23.0






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[PATCH 1/4] drm/amdgpu/soc15: disable doorbell interrupt as part of BACO entry sequence

[Le Ma]

Workaround to make RAS recovery work in BACO reset.

Change-Id: I4e4a81f719dcc88dfd49f583c4be3a373b5eab2c
Signed-off-by: Le Ma 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 2 ++
 drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c   | 8 
 drivers/gpu/drm/amd/amdgpu/soc15.c   | 9 +
 3 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
index 1f26a17..919bd56 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
@@ -67,6 +67,8 @@ struct amdgpu_nbio_funcs {
  bool enable);
void (*ih_doorbell_range)(struct amdgpu_device *adev,
  bool use_doorbell, int doorbell_index);
+   void (*enable_doorbell_interrupt)(struct amdgpu_device *adev,
+ bool enable);
void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
 bool enable);
void (*update_medium_grain_light_sleep)(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
index 238c248..0db458f 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
@@ -502,6 +502,13 @@ static void nbio_v7_4_query_ras_error_count(struct 
amdgpu_device *adev,
}
 }
 
+static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev,
+   bool enable)
+{
+   WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL,
+  DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
+}
+
 const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
.get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
.get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
@@ -516,6 +523,7 @@ const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
.enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
.enable_doorbell_selfring_aperture = 
nbio_v7_4_enable_doorbell_selfring_aperture,
.ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
+   .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt,
.update_medium_grain_clock_gating = 
nbio_v7_4_update_medium_grain_clock_gating,
.update_medium_grain_light_sleep = 
nbio_v7_4_update_medium_grain_light_sleep,
.get_clockgating_state = nbio_v7_4_get_clockgating_state,
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index fc6cfbc..5cf5f11 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -493,10 +493,15 @@ static int soc15_asic_baco_reset(struct amdgpu_device 
*adev)
 {
void *pp_handle = adev->powerplay.pp_handle;
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+   struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
 
if (!pp_funcs ||!pp_funcs->get_asic_baco_state 
||!pp_funcs->set_asic_baco_state)
return -ENOENT;
 
+   /* avoid NBIF got stuck when do RAS recovery in BACO reset */
+   if (ras && ras->supported)
+   adev->nbio.funcs->enable_doorbell_interrupt(adev, false);
+
/* enter BACO state */
if (pp_funcs->set_asic_baco_state(pp_handle, 1))
return -EIO;
@@ -505,6 +510,10 @@ static int soc15_asic_baco_reset(struct amdgpu_device 
*adev)
if (pp_funcs->set_asic_baco_state(pp_handle, 0))
return -EIO;
 
+   /* re-enable doorbell interrupt after BACO exit */
+   if (ras && ras->supported)
+   adev->nbio.funcs->enable_doorbell_interrupt(adev, true);
+
dev_info(adev->dev, "GPU BACO reset\n");
 
adev->in_baco_reset = 1;
-- 
2.7.4

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[PATCH 3/4] drm/amd/powerplay: send EnterBaco msg with argument as RAS recovery flag

[Le Ma]

1 indicates RAS recovery flag in SMU FW.

Change-Id: Icb8c14586fca1b8ae443bbde764570a9e41850fa
Signed-off-by: Le Ma 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
index b068d1c..9b5e72b 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
@@ -89,10 +89,15 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum 
BACO_STATE state)
data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
data |= 0x8000;
WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
-   }
 
-   if(smum_send_msg_to_smc_with_parameter(hwmgr, 
PPSMC_MSG_EnterBaco, 0))
-   return -EINVAL;
+   if(smum_send_msg_to_smc_with_parameter(hwmgr,
+   PPSMC_MSG_EnterBaco, 0))
+   return -EINVAL;
+   } else {
+   if(smum_send_msg_to_smc_with_parameter(hwmgr,
+   PPSMC_MSG_EnterBaco, 1))
+   return -EINVAL;
+   }
 
} else if (state == BACO_STATE_OUT) {
if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco))
-- 
2.7.4

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[PATCH 2/4] drm/amd/powerplay: avoid disabling ECC if RAS is enabled for VEGA20

[Le Ma]

Program THM_BACO_CNTL.SOC_DOMAIN_IDLE=1 will tell VBIOS to disable ECC when
BACO exit. This can save BACO exit time by PSP on none-ECC SKU. Drop the setting
for ECC supported SKU.

Change-Id: I2a82c128fa5e9731b886dd61f1273dc48ea1923c
Signed-off-by: Le Ma 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
index df6ff92..b068d1c 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
@@ -29,7 +29,7 @@
 #include "vega20_baco.h"
 #include "vega20_smumgr.h"
 
-
+#include "amdgpu_ras.h"
 
 static const struct soc15_baco_cmd_entry clean_baco_tbl[] =
 {
@@ -74,6 +74,7 @@ int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum 
BACO_STATE *state)
 int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
+   struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
enum BACO_STATE cur_state;
uint32_t data;
 
@@ -84,10 +85,11 @@ int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum 
BACO_STATE state)
return 0;
 
if (state == BACO_STATE_IN) {
-   data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
-   data |= 0x8000;
-   WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
-
+   if (!ras || !ras->supported) {
+   data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
+   data |= 0x8000;
+   WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
+   }
 
if(smum_send_msg_to_smc_with_parameter(hwmgr, 
PPSMC_MSG_EnterBaco, 0))
return -EINVAL;
-- 
2.7.4

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[PATCH 4/4] drm/amd/powerplay: add BACO platformCaps for VEGA20

[Le Ma]

BACO reset is needed for RAS recovery.

Change-Id: I8207fc314744468c89ba4a030cb2bb15b082aac7
Signed-off-by: Le Ma 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index 6629c475..3d3c647 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -183,6 +183,9 @@ static int vega20_set_features_platform_caps(struct 
pp_hwmgr *hwmgr)
PHM_PlatformCaps_TablelessHardwareInterface);
 
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
+   PHM_PlatformCaps_BACO);
+
+   phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EnableSMU7ThermalManagement);
 
if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
-- 
2.7.4

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[PATCH v2] drm/amd/powerplay: bug fix for pcie parameters override

[Kenneth Feng]

Bug fix for pcie paramerers override on swsmu.
Below is a scenario to have this problem.
pptable definition on pcie dpm:
0 -> pcie gen speed:1, pcie lanes: *16
1 -> pcie gen speed:4, pcie lanes: *16
Then if we have a system only have the capbility:
pcie gen speed: 3, pcie lanes: *8,
we will override dpm 1 to pcie gen speed 3, pcie lanes *8.
But the code skips the dpm 0 configuration.
So the real pcie dpm parameters are:
0 -> pcie gen speed:1, pcie lanes: *16
1 -> pcie gen speed:3, pcie lanes: *8
Then the wrong pcie lanes will be toggled.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 44 --
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h |  8 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 23 ++
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c  | 44 ++
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c | 25 ++-
 5 files changed, 99 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c9266ea..de54da2 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -945,50 +945,6 @@ static int smu_fini_fb_allocations(struct smu_context *smu)
return 0;
 }
 
-static int smu_override_pcie_parameters(struct smu_context *smu)
-{
-   struct amdgpu_device *adev = smu->adev;
-   uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
-   int ret;
-
-   if (adev->flags & AMD_IS_APU)
-   return 0;
-
-   if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
-   pcie_gen = 3;
-   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-   pcie_gen = 2;
-   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
-   pcie_gen = 1;
-   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
-   pcie_gen = 0;
-
-   /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
-* Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
-* Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
-*/
-   if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
-   pcie_width = 6;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
-   pcie_width = 5;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
-   pcie_width = 4;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
-   pcie_width = 3;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
-   pcie_width = 2;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
-   pcie_width = 1;
-
-   smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
-   ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_OverridePcieParameters,
- smu_pcie_arg);
-   if (ret)
-   pr_err("[%s] Attempt to override pcie params failed!\n", 
__func__);
-   return ret;
-}
-
 static int smu_smc_table_hw_init(struct smu_context *smu,
 bool initialize)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ccf711c..809de0d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -468,6 +468,7 @@ struct pptable_funcs {
int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool 
asic_default);
int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type 
clk_type,
   uint32_t dpm_level, uint32_t *freq);
+   int (*update_pcie_parameters)(struct smu_context *smu, uint32_t 
pcie_gen_cap, uint32_t pcie_width_cap);
 };
 
 struct smu_funcs
@@ -550,6 +551,7 @@ struct smu_funcs
int (*mode2_reset)(struct smu_context *smu);
int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type 
clk_type, uint32_t *min, uint32_t *max);
int (*set_soft_freq_limited_range)(struct smu_context *smu, enum 
smu_clk_type clk_type, uint32_t min, uint32_t max);
+   int (*override_pcie_parameters)(struct smu_context *smu);
 };
 
 #define smu_init_microcode(smu) \
@@ -782,6 +784,12 @@ struct smu_funcs
 #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
((smu)->funcs->set_soft_freq_limited_range ? 
(smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : 
-EINVAL)
 
+#define smu_override_pcie_parameters(smu) \
+   ((smu)->funcs->override_pcie_parameters ? 
(smu)->funcs->override_pcie_parameters((smu)) : 0)
+
+#define smu_update_pcie_parameters(smu, pcie_gen_cap, pcie_width_cap) \
+   

[PATCH] drm/amd/powerplay: bug fix for pcie parameters override

[Kenneth Feng]

Bug fix for pcie paramerers override on swsmu.
Below is a scenario to have this problem.
pptable definition on pcie dpm:
0 -> pcie gen speed:1, pcie lanes: *16
1 -> pcie gen speed:4, pcie lanes: *16
Then if we have a system only have the capbility:
pcie gen speed: 3, pcie lanes: *8,
we will override dpm 1 to pcie gen speed 3, pcie lanes *8.
But the code skips the dpm 0 configuration.
So the real pcie dpm parameters are:
0 -> pcie gen speed:1, pcie lanes: *16
1 -> pcie gen speed:3, pcie lanes: *8
Then the wrong pcie lanes will be toggled.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c  |   44 -
 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h  |8 +
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c  |   23 +
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c   |   44 +
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c_mi100 | 1404 +++
 drivers/gpu/drm/amd/powerplay/vega20_ppt.c  |   25 +-
 6 files changed, 1503 insertions(+), 45 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/powerplay/smu_v11_0.c_mi100

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c9266ea..de54da2 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -945,50 +945,6 @@ static int smu_fini_fb_allocations(struct smu_context *smu)
return 0;
 }
 
-static int smu_override_pcie_parameters(struct smu_context *smu)
-{
-   struct amdgpu_device *adev = smu->adev;
-   uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg;
-   int ret;
-
-   if (adev->flags & AMD_IS_APU)
-   return 0;
-
-   if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
-   pcie_gen = 3;
-   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-   pcie_gen = 2;
-   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
-   pcie_gen = 1;
-   else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
-   pcie_gen = 0;
-
-   /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
-* Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
-* Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
-*/
-   if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
-   pcie_width = 6;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
-   pcie_width = 5;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
-   pcie_width = 4;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
-   pcie_width = 3;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
-   pcie_width = 2;
-   else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
-   pcie_width = 1;
-
-   smu_pcie_arg = (1 << 16) | (pcie_gen << 8) | pcie_width;
-   ret = smu_send_smc_msg_with_param(smu,
- SMU_MSG_OverridePcieParameters,
- smu_pcie_arg);
-   if (ret)
-   pr_err("[%s] Attempt to override pcie params failed!\n", 
__func__);
-   return ret;
-}
-
 static int smu_smc_table_hw_init(struct smu_context *smu,
 bool initialize)
 {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ccf711c..809de0d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -468,6 +468,7 @@ struct pptable_funcs {
int (*get_power_limit)(struct smu_context *smu, uint32_t *limit, bool 
asic_default);
int (*get_dpm_clk_limited)(struct smu_context *smu, enum smu_clk_type 
clk_type,
   uint32_t dpm_level, uint32_t *freq);
+   int (*update_pcie_parameters)(struct smu_context *smu, uint32_t 
pcie_gen_cap, uint32_t pcie_width_cap);
 };
 
 struct smu_funcs
@@ -550,6 +551,7 @@ struct smu_funcs
int (*mode2_reset)(struct smu_context *smu);
int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type 
clk_type, uint32_t *min, uint32_t *max);
int (*set_soft_freq_limited_range)(struct smu_context *smu, enum 
smu_clk_type clk_type, uint32_t min, uint32_t max);
+   int (*override_pcie_parameters)(struct smu_context *smu);
 };
 
 #define smu_init_microcode(smu) \
@@ -782,6 +784,12 @@ struct smu_funcs
 #define smu_set_soft_freq_limited_range(smu, clk_type, min, max) \
((smu)->funcs->set_soft_freq_limited_range ? 
(smu)->funcs->set_soft_freq_limited_range((smu), (clk_type), (min), (max)) : 
-EINVAL)
 
+#define smu_override_pcie_parameters(smu) \
+   ((smu)->funcs->override_pcie_parameters ? 
(smu)->funcs->override_pcie_parameters((smu)) : 0)
+
+#define 

Re: [PATCH 00/15] Add BACO support for CI/VI asics

[Christian König]

Am 11.10.19 um 03:21 schrieb Alex Deucher:

This patch set enables BACO CI and VI asics.  BACO is
Bus Active Chip Off.  It allows us to turn off the GPU
while still keeping the bus interface up, so the device
does not disappear from the system.  PowerXpress and
Hybrid Graphics laptops support BOCO (Bus Off Chip Off)
which is controlled by ACPI.  BACO was conceived as
a power saving feature, but we also use it for reset
since the chip gets powered down.  These patches are
a pre-requisite for using BACO as a power saving
feature which will follow in another patch set.

BACO is working well on VI parts.  I haven't gotten
it working yet on CI parts, but I'm including the
code for reference if anyone wants to play with it.


Acked-by: Christian König  for the series.

Regards,
Christian.



Alex Deucher (15):
   drm/amdgpu: add new BIF 4.1 register for BACO
   drm/amdgpu: add new BIF 5.0 register for BACO
   drm/amdgpu: add new SMU 7.0.1 registers for BACO
   drm/amdgpu: add new SMU 7.1.2 registers for BACO
   drm/amdgpu: add new SMU 7.1.3 registers for BACO
   drm/amdgpu/powerplay: add core support for pre-SOC15 baco
   drm/amdgpu/powerplay: add support for BACO on tonga
   drm/amdgpu/powerplay: add support for BACO on Iceland
   drm/amdgpu/powerplay: add support for BACO on polaris
   drm/amdgpu/powerplay: add support for BACO on VegaM
   drm/amdgpu/powerplay: add support for BACO on Fiji
   drm/amdgpu/powerplay: add support for BACO on CI
   drm/amdgpu/powerplay: split out common smu7 BACO code
   drm/amdgpu/powerplay: wire up BACO to powerplay API for smu7
   drm/amdgpu: enable BACO reset for SMU7 based dGPUs (v2)

  drivers/gpu/drm/amd/amdgpu/cik.c  |  48 +++-
  drivers/gpu/drm/amd/amdgpu/cik.h  |   3 +
  drivers/gpu/drm/amd/amdgpu/vi.c   |  84 ++-
  drivers/gpu/drm/amd/amdgpu/vi.h   |   3 +
  .../drm/amd/include/asic_reg/bif/bif_4_1_d.h  |   1 +
  .../include/asic_reg/bif/bif_4_1_sh_mask.h|   2 +
  .../drm/amd/include/asic_reg/bif/bif_5_0_d.h  |   1 +
  .../include/asic_reg/bif/bif_5_0_sh_mask.h|   2 +
  .../amd/include/asic_reg/smu/smu_7_0_1_d.h|   1 +
  .../include/asic_reg/smu/smu_7_0_1_sh_mask.h  |   2 +
  .../amd/include/asic_reg/smu/smu_7_1_2_d.h|   1 +
  .../include/asic_reg/smu/smu_7_1_2_sh_mask.h  |   2 +
  .../amd/include/asic_reg/smu/smu_7_1_3_d.h|   1 +
  .../include/asic_reg/smu/smu_7_1_3_sh_mask.h  |   2 +
  drivers/gpu/drm/amd/powerplay/hwmgr/Makefile  |   3 +-
  drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c | 195 +++
  drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h |  29 +++
  .../gpu/drm/amd/powerplay/hwmgr/common_baco.c |  19 ++
  .../gpu/drm/amd/powerplay/hwmgr/common_baco.h |  13 +
  .../gpu/drm/amd/powerplay/hwmgr/fiji_baco.c   | 196 +++
  .../gpu/drm/amd/powerplay/hwmgr/fiji_baco.h   |  29 +++
  .../drm/amd/powerplay/hwmgr/polaris_baco.c| 222 +
  .../drm/amd/powerplay/hwmgr/polaris_baco.h|  29 +++
  .../gpu/drm/amd/powerplay/hwmgr/smu7_baco.c   |  91 +++
  .../gpu/drm/amd/powerplay/hwmgr/smu7_baco.h   |  32 +++
  .../gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c  |   4 +
  .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.c  | 231 ++
  .../gpu/drm/amd/powerplay/hwmgr/tonga_baco.h  |  29 +++
  28 files changed, 1264 insertions(+), 11 deletions(-)
  create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.c
  create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/ci_baco.h
  create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.c
  create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/fiji_baco.h
  create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.c
  create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/polaris_baco.h
  create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.c
  create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/smu7_baco.h
  create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.c
  create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/tonga_baco.h



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Re: [PATCH] drm/amdgpu/sdma5: fix mask value of POLL_REGMEM packet for pipe sync

[Christian König]

Good catch! Reviewed-by: Christian König 

Am 09.10.19 um 19:11 schrieb Deucher, Alexander:

Reviewed-by: Alex Deucher 

*From:* amd-gfx  on behalf of 
Yuan, Xiaojie 

*Sent:* Wednesday, October 9, 2019 1:09 PM
*To:* amd-gfx@lists.freedesktop.org 
*Cc:* Xiao, Jack ; Yuan, Xiaojie 
; Zhang, Hawking 
*Subject:* [PATCH] drm/amdgpu/sdma5: fix mask value of POLL_REGMEM 
packet for pipe sync

sdma will hang once sequence number to be polled reaches 0x1000_

Signed-off-by: Xiaojie Yuan 
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c

index ad5c3566337c..3460c00f3eaa 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1126,7 +1126,7 @@ static void 
sdma_v5_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)

 amdgpu_ring_write(ring, addr & 0xfffc);
 amdgpu_ring_write(ring, upper_32_bits(addr) & 0x);
 amdgpu_ring_write(ring, seq); /* reference */
-   amdgpu_ring_write(ring, 0xfff); /* mask */
+   amdgpu_ring_write(ring, 0x); /* mask */
 amdgpu_ring_write(ring, 
SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |

SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
 }
--
2.20.1

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RE: [PATCH 15/15] drm/amdgpu: enable BACO reset for SMU7 based dGPUs (v2)

[Quan, Evan]

Series is reviewed-by: Evan Quan 

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Friday, October 11, 2019 9:22 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander 
Subject: [PATCH 15/15] drm/amdgpu: enable BACO reset for SMU7 based dGPUs (v2)

Use BACO to reset the GPU if supported on SMU7 based
dGPUs.

v2: don't use baco on CI parts

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/cik.c | 48 --
 drivers/gpu/drm/amd/amdgpu/cik.h |  3 ++
 drivers/gpu/drm/amd/amdgpu/vi.c  | 84 ++--
 drivers/gpu/drm/amd/amdgpu/vi.h  |  3 ++
 4 files changed, 128 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index b81bb414fcb3..fc8b34480f66 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1270,15 +1270,15 @@ static int cik_gpu_pci_config_reset(struct 
amdgpu_device *adev)
 }
 
 /**
- * cik_asic_reset - soft reset GPU
+ * cik_asic_pci_config_reset - soft reset GPU
  *
  * @adev: amdgpu_device pointer
  *
- * Look up which blocks are hung and attempt
- * to reset them.
+ * Use PCI Config method to reset the GPU.
+ *
  * Returns 0 for success.
  */
-static int cik_asic_reset(struct amdgpu_device *adev)
+static int cik_asic_pci_config_reset(struct amdgpu_device *adev)
 {
int r;
 
@@ -1294,7 +1294,45 @@ static int cik_asic_reset(struct amdgpu_device *adev)
 static enum amd_reset_method
 cik_asic_reset_method(struct amdgpu_device *adev)
 {
-   return AMD_RESET_METHOD_LEGACY;
+   bool baco_reset;
+
+   switch (adev->asic_type) {
+   case CHIP_BONAIRE:
+   case CHIP_HAWAII:
+   /* disable baco reset until it works */
+   /* smu7_asic_get_baco_capability(adev, _reset); */
+   baco_reset = false;
+   break;
+   default:
+   baco_reset = false;
+   break;
+   }
+
+   if (baco_reset)
+   return AMD_RESET_METHOD_BACO;
+   else
+   return AMD_RESET_METHOD_LEGACY;
+}
+
+/**
+ * cik_asic_reset - soft reset GPU
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Look up which blocks are hung and attempt
+ * to reset them.
+ * Returns 0 for success.
+ */
+static int cik_asic_reset(struct amdgpu_device *adev)
+{
+   int r;
+
+   if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
+   r = smu7_asic_baco_reset(adev);
+   else
+   r = cik_asic_pci_config_reset(adev);
+
+   return r;
 }
 
 static u32 cik_get_config_memsize(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.h b/drivers/gpu/drm/amd/amdgpu/cik.h
index 54c625a2e570..9870bf27870e 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.h
+++ b/drivers/gpu/drm/amd/amdgpu/cik.h
@@ -31,4 +31,7 @@ void cik_srbm_select(struct amdgpu_device *adev,
 int cik_set_ip_blocks(struct amdgpu_device *adev);
 
 void legacy_doorbell_index_init(struct amdgpu_device *adev);
+int smu7_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap);
+int smu7_asic_baco_reset(struct amdgpu_device *adev);
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 5f8c8786cac5..78e5cdc0c058 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -689,16 +689,50 @@ static int vi_gpu_pci_config_reset(struct amdgpu_device 
*adev)
return -EINVAL;
 }
 
+int smu7_asic_get_baco_capability(struct amdgpu_device *adev, bool *cap)
+{
+   void *pp_handle = adev->powerplay.pp_handle;
+   const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+
+   if (!pp_funcs || !pp_funcs->get_asic_baco_capability) {
+   *cap = false;
+   return -ENOENT;
+   }
+
+   return pp_funcs->get_asic_baco_capability(pp_handle, cap);
+}
+
+int smu7_asic_baco_reset(struct amdgpu_device *adev)
+{
+   void *pp_handle = adev->powerplay.pp_handle;
+   const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
+
+   if (!pp_funcs ||!pp_funcs->get_asic_baco_state 
||!pp_funcs->set_asic_baco_state)
+   return -ENOENT;
+
+   /* enter BACO state */
+   if (pp_funcs->set_asic_baco_state(pp_handle, 1))
+   return -EIO;
+
+   /* exit BACO state */
+   if (pp_funcs->set_asic_baco_state(pp_handle, 0))
+   return -EIO;
+
+   dev_info(adev->dev, "GPU BACO reset\n");
+
+   return 0;
+}
+
 /**
- * vi_asic_reset - soft reset GPU
+ * vi_asic_pci_config_reset - soft reset GPU
  *
  * @adev: amdgpu_device pointer
  *
- * Look up which blocks are hung and attempt
- * to reset them.
+ * Use PCI Config method to reset the GPU.
+ *
  * Returns 0 for success.
  */
-static int vi_asic_reset(struct amdgpu_device *adev)
+static int vi_asic_pci_config_reset(struct amdgpu_device *adev)
 {
int r;
 
@@ -714,7 +748,47 @@ static int vi_asic_reset(struct amdgpu_device *adev)
 static enum 

Re: [PATCH] drm/amdgpu: user pages array memory leak fix

[Christian König]

Am 03.10.19 um 21:44 schrieb Yang, Philip:

user_pages array should always be freed after validation regardless if
user pages are changed after bo is created because with HMM change parse
bo always allocate user pages array to get user pages for userptr bo.

Don't need to get user pages while creating uerptr bo because user pages
will only be used while validating after parsing userptr bo.

Bugzilla: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1844962

v2: remove unused local variable and amend commit

Signed-off-by: Philip Yang 
---
  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c  |  4 +---
  drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 23 +--
  2 files changed, 2 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 49b767b7238f..961186e7113e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -474,7 +474,6 @@ static int amdgpu_cs_list_validate(struct amdgpu_cs_parser 
*p,
  
  	list_for_each_entry(lobj, validated, tv.head) {

struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
-   bool binding_userptr = false;
struct mm_struct *usermm;
  
  		usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);

@@ -491,14 +490,13 @@ static int amdgpu_cs_list_validate(struct 
amdgpu_cs_parser *p,
  
  			amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,

 lobj->user_pages);
-   binding_userptr = true;
}
  
  		r = amdgpu_cs_validate(p, bo);

if (r)
return r;
  
-		if (binding_userptr) {

+   if (lobj->user_pages) {
kvfree(lobj->user_pages);
lobj->user_pages = NULL;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index a828e3d0bfbd..3ccd61d69964 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -283,7 +283,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void 
*data,
  int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
 struct drm_file *filp)
  {
-   struct ttm_operation_ctx ctx = { true, false };
struct amdgpu_device *adev = dev->dev_private;
struct drm_amdgpu_gem_userptr *args = data;
struct drm_gem_object *gobj;
@@ -326,32 +325,12 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void 
*data,
goto release_object;
}
  
-	if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {


We can't drop that handling here, it is mandatory to detect an 
application bug where an application tries to user an userptr with a VMA 
which is not anonymous memory.


This must be detected and rejected as invalid here.

I suggest that we allocate a local pages array similar to how we do it 
during CS and release that after the function is done.


Regards,
Christian.


-   r = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages);
-   if (r)
-   goto release_object;
-
-   r = amdgpu_bo_reserve(bo, true);
-   if (r)
-   goto user_pages_done;
-
-   amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
-   r = ttm_bo_validate(>tbo, >placement, );
-   amdgpu_bo_unreserve(bo);
-   if (r)
-   goto user_pages_done;
-   }
-
r = drm_gem_handle_create(filp, gobj, );
if (r)
-   goto user_pages_done;
+   goto release_object;
  
  	args->handle = handle;
  
-user_pages_done:

-   if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE)
-   amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm);
-
  release_object:
drm_gem_object_put_unlocked(gobj);
  


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Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit

[Yuan, Xiaojie]

Hi there,

Could someone give an RB or ACK? This patch has been verified on both navi12 
and navi14.
Thanks.

BR,
Xiaojie

From: Deucher, Alexander 
Sent: Thursday, October 10, 2019 8:20 PM
To: Feng, Kenneth ; Yuan, Xiaojie ; 
amd-gfx@lists.freedesktop.org 
Cc: Xiao, Jack ; Wang, Kevin(Yang) ; 
Zhang, Hawking ; Quan, Evan 
Subject: Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit

Great.  thanks!

Alex

From: Feng, Kenneth 
Sent: Thursday, October 10, 2019 3:00 AM
To: Yuan, Xiaojie ; Deucher, Alexander 
; amd-gfx@lists.freedesktop.org 

Cc: Xiao, Jack ; Wang, Kevin(Yang) ; 
Zhang, Hawking ; Quan, Evan 
Subject: RE: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit


Hi Alex,

This issue was navi10 specific and was found in May, 2019.

It was early after the asic back, then since gfxoff was removed from navi10, we 
didn’t really verify which firmware version started to have a fix.

For navi14/navi12, there’s no such issue at all.

Sorry for losing the track of it.





From: Yuan, Xiaojie
Sent: Thursday, October 10, 2019 1:17 AM
To: Deucher, Alexander ; 
amd-gfx@lists.freedesktop.org
Cc: Xiao, Jack ; Wang, Kevin(Yang) ; 
Zhang, Hawking ; Quan, Evan ; Feng, 
Kenneth 
Subject: Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit



Hi Alex,



For now, gfxoff for navi10 is disabled by default, and I also verified on 
navi14 with both GFXOFF and FW_DSTATE feature bits toggled on.



Hi Kenneth / Jack,



Could you help to confirm the firmware version?



BR,

Xiaojie



From: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Sent: Wednesday, October 9, 2019 9:35 PM
To: Yuan, Xiaojie mailto:xiaojie.y...@amd.com>>; 
amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Xiao, Jack mailto:jack.x...@amd.com>>; Wang, Kevin(Yang) 
mailto:kevin1.w...@amd.com>>; Zhang, Hawking 
mailto:hawking.zh...@amd.com>>; Quan, Evan 
mailto:evan.q...@amd.com>>; Feng, Kenneth 
mailto:kenneth.f...@amd.com>>
Subject: Re: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit



What version of firmware has the fix?  Was it recently fixed?  We should check 
the version if the old one may be out in the wild.



Alex



From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Yuan, Xiaojie mailto:xiaojie.y...@amd.com>>
Sent: Wednesday, October 9, 2019 7:08 AM
To: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Cc: Xiao, Jack mailto:jack.x...@amd.com>>; Wang, Kevin(Yang) 
mailto:kevin1.w...@amd.com>>; Zhang, Hawking 
mailto:hawking.zh...@amd.com>>; Quan, Evan 
mailto:evan.q...@amd.com>>; Feng, Kenneth 
mailto:kenneth.f...@amd.com>>; Yuan, Xiaojie 
mailto:xiaojie.y...@amd.com>>
Subject: [PATCH 2/2] drm/amd/powerplay: re-enable FW_DSTATE feature bit



SMU firmware has fix the bug, so remove this workaround.

Signed-off-by: Xiaojie Yuan mailto:xiaojie.y...@amd.com>>
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c 
b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index 44152c1f01c7..3628295469c4 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -359,11 +359,8 @@ navi10_get_allowed_feature_mask(struct smu_context *smu,
 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);

-   if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
+   if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
-   /* TODO: remove it once fw fix the bug */
-   *(uint64_t *)feature_mask &= 
~FEATURE_MASK(FEATURE_FW_DSTATE_BIT);
-   }

 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 *(uint64_t *)feature_mask |= 
FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
--
2.20.1

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Re: [amdgpu] ASSERT()'s in write_i2c*retimer_setting() functions

[Koenig, Christian]

Forwarding to the appropriate display folks.

Can you guys take a look?

Christian.

Am 11.10.19 um 01:34 schrieb Gabriel C:
> Hello,
>
> I've built recently a new box with a Ryzen3 2200G APU.
>
> Each time I plug in an HDMI cable ( to a TV or Monitor ),
> or boot with HDMI connected a lot ASSERT()'s from
> write_i2c*retimer_setting() functions are triggered.
>
> I see the same on a Laptop with a Ryzen7 3750H with
> hybrid GPU configuration.
>
> Besides the noise in dmesg and the delay on boot,
> everything is working fine. I cannot find anything wrong
> or broken.
>
> Since the write errors seem to not be fatal, I think a friendly message
> would help more instead of flooding the dmesg with dumps while
> everything is working properly.
>
> Why is ASSERT() used there?
>
> I have a dmesg from the Ryzen3 box with drm.debug and a snipped
> from the Laptop ( not near me right now ) uploaded there:
>
> https://crazy.dev.frugalware.org/amdgpu/
>
> Please let me know if you need more information,
> If needed I can upload a dmesg from the Laptop with drm.debug too.
>
>
> Best Regards,
>
> Gabriel C

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Re: [PATCH v3] drm/radeon: Fix EEH during kexec

[Greg KH]

On Thu, Oct 10, 2019 at 02:44:29PM -0500, KyleMahlkuch wrote:
> During kexec some adapters hit an EEH since they are not properly
> shut down in the radeon_pci_shutdown() function. Adding
> radeon_suspend_kms() fixes this issue.
> Enabled only on PPC because this patch causes issues on some other
> boards.
> 
> Signed-off-by: Kyle Mahlkuch 

Real email address please, with a '@' sign.

And your "From:" line did not match up with this :(

> ---
>  drivers/gpu/drm/radeon/radeon_drv.c | 14 ++
>  1 file changed, 14 insertions(+)



This is not the correct way to submit patches for inclusion in the
stable kernel tree.  Please read:
https://www.kernel.org/doc/html/latest/process/stable-kernel-rules.html
for how to do this properly.


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