[PATCH 18/28] drm/amd/display: add support for per-state dummy-pstate latency

2020-06-07 Thread Qingqing Zhuo 
From: Jun Lei 

[why]
Dummy pstate latency actually varies between different
UCLK frequencies, when calculating watermark C, if DAL
always assumes worst case, then it can lead to dummy
pstate not supported scenarios.

[how]
Rather than statically calculating dummy pstate using
worst case, we store the entire table of UCLK to dummy
pstate relationships.  On a per mode basis, we calculate
the actual UCLK lower limit, and use the dynamic worst
case dummy pstate latency.  This prevents the situation
where we don't support full p-state (which will force
high DPM), but still use low DPM dummy pstate latency.

Signed-off-by: Jun Lei 
Reviewed-by: Joshua Aberback 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h 
b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
index 49c50af9cd9e..505357597603 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h
@@ -198,11 +198,17 @@ struct wm_table {
 #endif
 };
 
+struct dummy_pstate_entry {
+   unsigned int dram_speed_mts;
+   unsigned int dummy_pstate_latency_us;
+};
+
 struct clk_bw_params {
unsigned int vram_type;
unsigned int num_channels;
struct clk_limit_table clk_table;
struct wm_table wm_table;
+   struct dummy_pstate_entry dummy_pstate_table[4];
 };
 /* Public interfaces */
 
-- 
2.17.1

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[PATCH 20/28] drm/amd/display: make calculate watermarks a function pointer

2020-06-07 Thread Qingqing Zhuo 
From: Dmytro Laktyushkin 

To allow code reuse with minimal duplication watermark
calculation needs to be function pointer.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Bernstein 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/inc/core_types.h | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h 
b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 4fbed8dd0c59..5f985fcbedf1 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -101,7 +101,11 @@ struct resource_funcs {
struct dc *dc,
struct dc_state *context,
bool fast_validate);
-
+   void (*calculate_wm)(
+   struct dc *dc, struct dc_state *context,
+   display_e2e_pipe_params_st *pipes,
+   int pipe_cnt,
+   int vlevel);
int (*populate_dml_pipes)(
struct dc *dc,
struct dc_state *context,
-- 
2.17.1

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[PATCH 17/28] drm/amd/display: Revert "DP link layer test 4.2.1.1 fix due to specs update"

2020-06-07 Thread Qingqing Zhuo 
From: Wenjing Liu 

[why]
The change causes some regression in a common use case.
Will need more investigation before fixing the original issue.

[how]
This reverts commit ad418864c63a1718f9e283207b3fac96fbc148c2.

Signed-off-by: Wenjing Liu 
Reviewed-by: Jun Lei 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  4 +-
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c | 13 ++--
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 59 ++-
 .../drm/amd/display/dc/core/dc_link_hwss.c|  2 +-
 drivers/gpu/drm/amd/display/dc/dc.h   |  2 +-
 drivers/gpu/drm/amd/display/dc/dc_link.h  |  1 -
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  2 +-
 .../gpu/drm/amd/display/dc/inc/dc_link_ddc.h  |  2 +-
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |  2 +-
 9 files changed, 42 insertions(+), 45 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index cb5491fb326c..cbb4c24d748d 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -690,11 +690,9 @@ static bool detect_dp(struct dc_link *link,
 
if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
-
+   dpcd_set_source_specific_data(link);
if (!detect_dp_sink_caps(link))
return false;
-   dpcd_set_source_specific_data(link);
-
if (is_mst_supported(link)) {
sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
link->type = dc_connection_mst_branch;
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
index 242ed5976cdb..aefd29a440b5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c
@@ -648,17 +648,16 @@ bool dc_link_aux_transfer_with_retries(struct ddc_service 
*ddc,
 }
 
 
-bool dc_link_aux_try_to_configure_timeout(struct ddc_service *ddc,
+uint32_t dc_link_aux_configure_timeout(struct ddc_service *ddc,
uint32_t timeout)
 {
-   bool result = false;
+   uint32_t prev_timeout = 0;
struct ddc *ddc_pin = ddc->ddc_pin;
 
-   if 
(ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout)
 {
-   
ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc,
 timeout);
-   result = true;
-   }
-   return result;
+   if 
(ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout)
+   prev_timeout =
+   
ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc,
 timeout);
+   return prev_timeout;
 }
 
 /*test only function*/
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 674f53aaf2b4..6c03dcd6acb5 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -245,7 +245,7 @@ static uint8_t dc_dp_initialize_scrambling_data_symbols(
 
 static inline bool is_repeater(struct dc_link *link, uint32_t offset)
 {
-   return (link->lttpr_non_transparent_mode && offset != 0);
+   return (!link->is_lttpr_mode_transparent && offset != 0);
 }
 
 static void dpcd_set_lt_pattern_and_lane_settings(
@@ -1038,7 +1038,7 @@ static enum link_training_result 
perform_clock_recovery_sequence(
/* 3. wait receiver to lock-on*/
wait_time_microsec = lt_settings->cr_pattern_time;
 
-   if (link->lttpr_non_transparent_mode)
+   if (!link->is_lttpr_mode_transparent)
wait_time_microsec = TRAINING_AUX_RD_INTERVAL;
 
wait_for_training_aux_rd_interval(
@@ -1268,7 +1268,7 @@ static void configure_lttpr_mode(struct dc_link *link)
link->dpcd_caps.lttpr_caps.mode = repeater_mode;
}
 
-   if (link->lttpr_non_transparent_mode) {
+   if (!link->is_lttpr_mode_transparent) {
 
DC_LOG_HW_LINK_TRAINING("%s\n Set LTTPR to Non Transparent 
Mode\n", __func__);
 
@@ -1473,7 +1473,7 @@ enum link_training_result 
dc_link_dp_perform_link_training(
_settings);
 
/* Configure lttpr mode */
-   if (link->lttpr_non_transparent_mode)
+   if (!link->is_lttpr_mode_transparent)
configure_lttpr_mode(link);
 
if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
@@ -1489,7 +1489,7 @@ enum link_training_result 
dc_link_dp_perform_link_training(
 
dp_set_fec_ready(link, fec_enable);
 
-   if (link->lttpr_non_transparent_mode) {
+   if (!link->is_lttpr_mode_transparent) {
 
/* 2. perform link training (set link training done
 *

[PATCH 27/28] drm/amd/display: [FW Promotion] Release 1.0.15

2020-06-07 Thread Qingqing Zhuo 
From: Anthony Koo 

[Header Changes]
- Add new initialization bits for driver to check
  firmware status
- Add command for HW locking via DMUB

Signed-off-by: Anthony Koo 
Reviewed-by: Anthony Koo 
Acked-by: Qingqing Zhuo 
---
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 68 ++-
 1 file changed, 65 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 5066c639670e..7c03c4798348 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x5470fd231
+#define DMUB_FW_VERSION_GIT_HASH 0xee850bb2f
 #define DMUB_FW_VERSION_MAJOR 1
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 14
+#define DMUB_FW_VERSION_REVISION 15
 #define DMUB_FW_VERSION_UCODE ((DMUB_FW_VERSION_MAJOR << 24) | 
(DMUB_FW_VERSION_MINOR << 16) | DMUB_FW_VERSION_REVISION)
 #endif
 
@@ -137,8 +137,31 @@ union dmub_fw_meta {
 };
 
 #pragma pack(pop)
+
+//==
+//< 
DMUB_STATUS>
+//==
+
+/**
+ * DMCUB scratch registers can be used to determine firmware status.
+ * Current scratch register usage is as follows:
+ *
+ * SCRATCH0: Legacy status register
+ * SCRATCH1: Firmware version
+ * SCRATCH2: Firmware status bits defined by dmub_fw_status_bit
+ * SCRATCH3: Reserved firmware status bits
+ */
+
+/**
+ * DMCUB firmware status bits for SCRATCH2.
+ */
+enum dmub_fw_status_bit {
+   DMUB_FW_STATUS_BIT_DAL_FIRMWARE = (1 << 0),
+   DMUB_FW_STATUS_BIT_COMMAND_TABLE_READY = (1 << 1),
+};
+
 
//==
-//==
+//
 
//==
 //< 
DMUB_VBIOS>=
 
//==
@@ -230,6 +253,7 @@ enum dmub_cmd_type {
DMUB_CMD__PLAT_54186_WA = 5,
DMUB_CMD__PSR = 64,
DMUB_CMD__ABM = 66,
+   DMUB_CMD__HW_LOCK = 69,
DMUB_CMD__VBIOS = 128,
 };
 
@@ -453,6 +477,44 @@ struct dmub_rb_cmd_psr_set_version {
struct dmub_cmd_psr_set_version_data psr_set_version_data;
 };
 
+union dmub_hw_lock_flags {
+   struct {
+   uint8_t lock_pipe   : 1;
+   uint8_t lock_cursor : 1;
+   uint8_t lock_dig: 1;
+   uint8_t triple_buffer_lock : 1;
+   } bits;
+
+   uint8_t u8All;
+};
+
+struct dmub_hw_lock_inst_flags {
+   uint8_t otg_inst;
+   uint8_t opp_inst;
+   uint8_t dig_inst;
+   uint8_t pad;
+};
+
+enum hw_lock_client {
+   HW_LOCK_CLIENT_DRIVER = 0,
+   HW_LOCK_CLIENT_FW,
+   HW_LOCK_CLIENT_INVALID = 0x,
+};
+
+struct dmub_cmd_lock_hw_data {
+   enum hw_lock_client client;
+   struct dmub_hw_lock_inst_flags inst_flags;
+   union dmub_hw_lock_flags hw_locks;
+   uint8_t lock;
+   uint8_t should_release;
+   uint8_t pad;
+};
+
+struct dmub_rb_cmd_lock_hw {
+   struct dmub_cmd_header header;
+   struct dmub_cmd_lock_hw_data lock_hw_data;
+};
+
 enum dmub_cmd_abm_type {
DMUB_CMD__ABM_INIT_CONFIG   = 0,
DMUB_CMD__ABM_SET_PIPE  = 1,
-- 
2.17.1

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[PATCH 06/28] drm/amd/display: Use u16 for drm_bpp in DSC calculations

2020-06-07 Thread Qingqing Zhuo 
From: Nicholas Kazlauskas 

[Why]
DSC calculations fail because the u16 bits_per_pixel from
the DRM struct is being casted to the u8 drm_bpp parameters
and locals. Integer wraparound is happening because this
value is greater than 255.

[How]
Use u16 to match what's in the structure instead of u8.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Rodrigo Siqueira 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c 
b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
index 667afbc260f9..4da21966ddce 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
@@ -175,7 +175,7 @@ static int median3(int a, int b, int c)
 }
 
 static void _do_calc_rc_params(struct rc_params *rc, enum colour_mode cm,
-  enum bits_per_comp bpc, u8 drm_bpp,
+  enum bits_per_comp bpc, u16 drm_bpp,
   bool is_navite_422_or_420,
   int slice_width, int slice_height,
   int minor_version)
@@ -265,7 +265,7 @@ static void _do_calc_rc_params(struct rc_params *rc, enum 
colour_mode cm,
rc->rc_buf_thresh[13] = 8064;
 }
 
-static u32 _do_bytes_per_pixel_calc(int slice_width, u8 drm_bpp,
+static u32 _do_bytes_per_pixel_calc(int slice_width, u16 drm_bpp,
bool is_navite_422_or_420)
 {
float bpp;
@@ -321,7 +321,7 @@ void calc_rc_params(struct rc_params *rc, const struct 
drm_dsc_config *pps)
enum colour_mode mode;
enum bits_per_comp bpc;
bool is_navite_422_or_420;
-   u8 drm_bpp = pps->bits_per_pixel;
+   u16 drm_bpp = pps->bits_per_pixel;
int slice_width  = pps->slice_width;
int slice_height = pps->slice_height;
 
@@ -357,7 +357,7 @@ u32 calc_dsc_bytes_per_pixel(const struct drm_dsc_config 
*pps)
 
 {
u32 ret;
-   u8 drm_bpp = pps->bits_per_pixel;
+   u16 drm_bpp = pps->bits_per_pixel;
int slice_width  = pps->slice_width;
bool is_navite_422_or_420 = pps->native_422 || pps->native_420;
 
-- 
2.17.1

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[PATCH 22/28] drm/amd/display: Improve DisplayPort monitor interop

2020-06-07 Thread Qingqing Zhuo 
From: Aric Cyr 

[Why]
DC is very fast at link training and stream enablement
which causes issues such as blackscreens for non-compliant
monitors.

[How]
After debugging with scaler vendors we implement the
minimum delays at the necessary locations to ensure
the monitor does not hang.  Delays are generic due to
lack of IEEE OUI information on the failing displays.

Also reverts commit b9976bd920a19d509de09b6dc727fcaae60fbb32.

Signed-off-by: Aric Cyr 
Reviewed-by: Wenjing Liu 
Acked-by: Qingqing Zhuo 
Acked-by: Tony Cheng 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |  4 +++-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  | 23 +++
 drivers/gpu/drm/amd/display/dc/dc.h   |  1 -
 .../display/dc/dce110/dce110_hw_sequencer.c   | 11 -
 4 files changed, 26 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index cbb4c24d748d..114ee29132fa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3309,9 +3309,11 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
write_i2c_redriver_setting(pipe_ctx, false);
}
}
-   dc->hwss.disable_stream(pipe_ctx);
 
disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
+
+   dc->hwss.disable_stream(pipe_ctx);
+
if (pipe_ctx->stream->timing.flags.DSC) {
if (dc_is_dp_signal(pipe_ctx->stream->signal))
dp_set_dsc_enable(pipe_ctx, false);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 6c03dcd6acb5..484a6849f3de 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1102,6 +1102,10 @@ static inline enum link_training_result 
perform_link_training_int(
dpcd_pattern.v1_4.TRAINING_PATTERN_SET = 
DPCD_TRAINING_PATTERN_VIDEOIDLE;
dpcd_set_training_pattern(link, dpcd_pattern);
 
+   /* delay 5ms after notifying sink of idle pattern before switching 
output */
+   if (link->connector_signal != SIGNAL_TYPE_EDP)
+   msleep(5);
+
/* 4. mainlink output idle pattern*/
dp_set_hw_test_pattern(link, DP_TEST_PATTERN_VIDEO_MODE, NULL, 0);
 
@@ -1551,6 +1555,12 @@ bool perform_link_training_with_retries(
struct dc_link *link = stream->link;
enum dp_panel_mode panel_mode = dp_get_panel_mode(link);
 
+   /* We need to do this before the link training to ensure the idle 
pattern in SST
+* mode will be sent right after the link training
+*/
+   link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
+   
pipe_ctx->stream_res.stream_enc->id, true);
+
for (j = 0; j < attempts; ++j) {
 
dp_enable_link_phy(
@@ -1559,21 +1569,14 @@ bool perform_link_training_with_retries(
pipe_ctx->clock_source->id,
link_setting);
 
-   if ((link && link->dc->debug.dppowerup_delay > 0) || 
stream->sink_patches.dppowerup_delay > 0) {
-   int delay_dp_power_up_in_ms =
-   (link->dc->debug.dppowerup_delay >= 
stream->sink_patches.dppowerup_delay) ?
-   link->dc->debug.dppowerup_delay : 
stream->sink_patches.dppowerup_delay;
+   if (stream->sink_patches.dppowerup_delay > 0) {
+   int delay_dp_power_up_in_ms = 
stream->sink_patches.dppowerup_delay;
+
msleep(delay_dp_power_up_in_ms);
}
 
dp_set_panel_mode(link, panel_mode);
 
-   /* We need to do this before the link training to ensure the 
idle pattern in SST
-* mode will be sent right after the link training
-*/
-   link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
-   
pipe_ctx->stream_res.stream_enc->id, true);
-
if (link->aux_access_disabled) {
dc_link_dp_perform_link_training_skip_aux(link, 
link_setting);
return true;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index f9bdd9115edc..7da41d465a34 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -498,7 +498,6 @@ struct dc_debug_options {
bool usbc_combo_phy_reset_wa;
bool disable_dsc;
bool enable_dram_clock_change_one_display_vactive;
-   unsigned int dppowerup_delay;
 };
 
 struct dc_debug_data {
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 0ce430cf4dd0..49380ed3aeae 100644
---

[PATCH 09/28] drm/amd/display: Fix VBA chroma calculation for pipe splitting

2020-06-07 Thread Qingqing Zhuo 
From: Nicholas Kazlauskas 

[Why]
DML failures occur for 420 modes with dynamic pipe
splitting enabled because the ChromaViewport exceeds
the ChromaSurfaceWidth.

This is caused by adding the viewport_width instead
of the viewport_width_c.

This similarly occurs for rotated modes due to the
use of viewport_height instead of viewport_height_c.

[How]
Correct the calculations.

Signed-off-by: Nicholas Kazlauskas 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c 
b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 5a1ca8a5954c..7916a7ea9336 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -623,14 +623,14 @@ static void fetch_pipe_params(struct display_mode_lib 
*mode_lib)

mode_lib->vba.ViewportWidth[mode_lib->vba.NumberOfActivePlanes] +=

src_k->viewport_width;

mode_lib->vba.ViewportWidthChroma[mode_lib->vba.NumberOfActivePlanes] +=
-   
src_k->viewport_width;
+   
src_k->viewport_width_c;

mode_lib->vba.ScalerRecoutWidth[mode_lib->vba.NumberOfActivePlanes] +=

dst_k->recout_width;
} else {

mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] +=

src_k->viewport_height;

mode_lib->vba.ViewportHeightChroma[mode_lib->vba.NumberOfActivePlanes] +=
-   
src_k->viewport_height;
+   
src_k->viewport_height_c;
}

mode_lib->vba.NumberOfDSCSlices[mode_lib->vba.NumberOfActivePlanes] +=
dout_k->dsc_slices;
-- 
2.17.1

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[PATCH 14/28] drm/amd/display: Passing initial SDP deadline to dmub

2020-06-07 Thread Qingqing Zhuo 
From: po-tchen 

[Why]
The SDP deadline indicate the vertical time to send CRC
infopacket in PSR.

Signed-off-by: po-tchen 
Reviewed-by: Anthony Koo 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c 
b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index fd4e1021903a..916d305d3022 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -233,6 +233,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
copy_settings_data->frame_cap_ind   = 
psr_context->psrFrameCaptureIndicationReq;
copy_settings_data->debug.bitfields.visual_confirm  = 
dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR ?
true : 
false;
+   copy_settings_data->init_sdp_deadline   = 
psr_context->sdpTransmitLineNumDeadline;
 
dc_dmub_srv_cmd_queue(dc->dmub_srv, );
dc_dmub_srv_cmd_execute(dc->dmub_srv);
-- 
2.17.1

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[PATCH 13/28] drm/amd/display: Force delay after DP receive power up

2020-06-07 Thread Qingqing Zhuo 
From: Martin Tsai 

[Why]
Some sprcified monitor scalar cannot recognize timing
change on demand. Once the link phy disable and enable
during a short period then the Sink protection mechanism
could keep the screen in blank and cannot be recoverred.

[How]
To add 100ms delay between enable link phy and link training.

Signed-off-by: Martin Tsai 
Reviewed-by: Aric Cyr 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 ---
 drivers/gpu/drm/amd/display/dc/dc.h  | 1 +
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 08c3b32e188c..674f53aaf2b4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1559,9 +1559,10 @@ bool perform_link_training_with_retries(
pipe_ctx->clock_source->id,
link_setting);
 
-   if (stream->sink_patches.dppowerup_delay > 0) {
-   int delay_dp_power_up_in_ms = 
stream->sink_patches.dppowerup_delay;
-
+   if ((link && link->dc->debug.dppowerup_delay > 0) || 
stream->sink_patches.dppowerup_delay > 0) {
+   int delay_dp_power_up_in_ms =
+   (link->dc->debug.dppowerup_delay >= 
stream->sink_patches.dppowerup_delay) ?
+   link->dc->debug.dppowerup_delay : 
stream->sink_patches.dppowerup_delay;
msleep(delay_dp_power_up_in_ms);
}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 8cdbfa15874b..9138adf63f9f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -498,6 +498,7 @@ struct dc_debug_options {
bool usbc_combo_phy_reset_wa;
bool disable_dsc;
bool enable_dram_clock_change_one_display_vactive;
+   unsigned int dppowerup_delay;
 };
 
 struct dc_debug_data {
-- 
2.17.1

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[PATCH 05/28] drm/amd/display: Move call to disable DPG

2020-06-07 Thread Qingqing Zhuo 
From: Wesley Chalmers 

[WHY]
Disabling DPG should happen after setting watermarks and clocks

Signed-off-by: Wesley Chalmers 
Reviewed-by: Tony Cheng 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 5b7466a243b2..49dd310ed588 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1248,7 +1248,6 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
int i, k, l;
struct dc_stream_state *dc_streams[MAX_STREAMS] = {0};
 
-   disable_dangling_plane(dc, context);
 
for (i = 0; i < context->stream_count; i++)
dc_streams[i] =  context->streams[i];
@@ -1264,6 +1263,7 @@ static enum dc_status dc_commit_state_no_check(struct dc 
*dc, struct dc_state *c
if (dc->optimize_seamless_boot_streams == 0)
dc->hwss.prepare_bandwidth(dc, context);
 
+   disable_dangling_plane(dc, context);
/* re-program planes for existing stream, in case we need to
 * free up plane resource for later use
 */
-- 
2.17.1

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[PATCH 02/28] drm/amd/display: Rework dsc to isolate FPU operations

2020-06-07 Thread Qingqing Zhuo 
From: Rodrigo Siqueira 

When we want to use float point operation on Linux
we need to use within special kernel protection
(`kernel_fpu_{begin,end}()`.), otherwise the kernel
can clobber userspace FPU register state. For detecting
these issues we use a tool named objtool (with -Ffa
flags) to highlight the FPU problems, all warnings can
be summed up as follows:

./tools/objtool/objtool check -Ffa
drivers/gpu/drm/amd/display/dc/dml/dml_common_defs.o

[..] dc/dsc/rc_calc.o: warning: objtool: get_qp_set()+0x2f8:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc.o: warning: objtool: dsc_roundf()+0x5:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc.o: warning: objtool: dsc_ceil()+0x5:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc.o: warning: objtool: get_ofs_set()+0x3eb:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc.o: warning: objtool: calc_rc_params()+0x3c:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/dc_dsc.o: warning: objtool:
get_dsc_bandwidth_range.isra.0()+0x8d:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/dc_dsc.o: warning: objtool: setup_dsc_config()+0x2ef:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc_dpi.o: warning: objtool:copy_pps_fields()+0xbb:
FPU instruction outside of kernel_fpu_{begin,end}()
[..] dc/dsc/rc_calc_dpi.o: warning: objtool:
dscc_compute_dsc_parameters()+0x7b:
FPU instruction outside of kernel_fpu_{begin,end}()

This commit fixes the above issues by rework DSC as described:

1. Isolate all FPU operations in a single file;
2. Use FPU flags only in the file that handles FPU operations;
3. Isolate all functions that require float point operation in static
   functions;
4. Add a mid-layer function that does not use any float point operation,
   and that could be safely invoked in other parts of the code.
5. Keep float point operation under DC_FP_{START/END} macro.

CC: Christian König 
CC: Alexander Deucher 
CC: Peter Zijlstra 
CC: Tony Cheng 
CC: Harry Wentland 
Signed-off-by: Rodrigo Siqueira 
Reviewed-by: Mikita Lipski 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dsc/Makefile   |   2 -
 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c   |  18 +--
 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c  | 151 +-
 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h  |   5 +-
 .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c  |  27 +---
 5 files changed, 153 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/Makefile 
b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
index 3f66868df171..ea29cf95d470 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/Makefile
+++ b/drivers/gpu/drm/amd/display/dc/dsc/Makefile
@@ -28,8 +28,6 @@ endif
 endif
 
 CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc.o := $(dsc_ccflags)
-CFLAGS_$(AMDDALPATH)/dc/dsc/rc_calc_dpi.o := $(dsc_ccflags)
-CFLAGS_$(AMDDALPATH)/dc/dsc/dc_dsc.o := $(dsc_ccflags)
 
 DSC = dc_dsc.o rc_calc.o rc_calc_dpi.o
 
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c 
b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 0ea6662a1563..0c7f247bb7de 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -22,10 +22,12 @@
  * Author: AMD
  */
 
+#include 
 #include "dc_hw_types.h"
 #include "dsc.h"
 #include 
 #include "dc.h"
+#include "rc_calc.h"
 
 /* This module's internal functions */
 
@@ -304,22 +306,6 @@ static inline uint32_t dsc_div_by_10_round_up(uint32_t 
value)
return (value + 9) / 10;
 }
 
-static inline uint32_t calc_dsc_bpp_x16(uint32_t stream_bandwidth_kbps, 
uint32_t pix_clk_100hz, uint32_t bpp_increment_div)
-{
-   uint32_t dsc_target_bpp_x16;
-   float f_dsc_target_bpp;
-   float f_stream_bandwidth_100bps = stream_bandwidth_kbps * 10.0f;
-   uint32_t precision = bpp_increment_div; // bpp_increment_div is 
actually precision
-
-   f_dsc_target_bpp = f_stream_bandwidth_100bps / pix_clk_100hz;
-
-   // Round down to the nearest precision stop to bring it into DSC spec 
range
-   dsc_target_bpp_x16 = (uint32_t)(f_dsc_target_bpp * precision);
-   dsc_target_bpp_x16 = (dsc_target_bpp_x16 * 16) / precision;
-
-   return dsc_target_bpp_x16;
-}
-
 /* Get DSC bandwidth range based on [min_bpp, max_bpp] target bitrate range, 
and timing's pixel clock
  * and uncompressed bandwidth.
  */
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c 
b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
index 03ae15946c6d..667afbc260f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c
@@ -23,6 +23,7 @@
  * Authors: AMD
  *
  */
+#include 
 
 #include "os_types.h"
 #include "rc_calc.h"
@@ -40,7 +41,8 @@
break
 
 
-void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc, enum 
max_min max_min, float bpp)
+static void get_qp_set(qp_set qps, enum colour_mode cm, enum bits_per_comp bpc,
+

[PATCH 23/28] drm/amd/display: change global buffer to local buffer

2020-06-07 Thread Qingqing Zhuo 
From: Lewis Huang 

[Why]
Multi-adapter calculate regamma table at the same time.
Two thread used the same global variable cause race
condition.

[How]
Change global buffer to local buffer

Signed-off-by: Lewis Huang 
Reviewed-by: Aric Cyr 
Acked-by: Qingqing Zhuo 
---
 .../amd/display/amdgpu_dm/amdgpu_dm_color.c   |  10 +-
 .../drm/amd/display/modules/color/Makefile|   4 +
 .../amd/display/modules/color/color_gamma.c   | 115 ++
 .../amd/display/modules/color/color_gamma.h   |  18 ++-
 .../amd/display/modules/color/color_table.c   |  48 
 .../amd/display/modules/color/color_table.h   |  47 +++
 6 files changed, 183 insertions(+), 59 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/modules/color/color_table.c
 create mode 100644 drivers/gpu/drm/amd/display/modules/color/color_table.h

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
index 4dfb6b55bb2e..b321ff654df4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
@@ -195,10 +195,13 @@ static int __set_legacy_tf(struct dc_transfer_func *func,
   bool has_rom)
 {
struct dc_gamma *gamma = NULL;
+   struct calculate_buffer cal_buffer = {0};
bool res;
 
ASSERT(lut && lut_size == MAX_COLOR_LEGACY_LUT_ENTRIES);
 
+   cal_buffer.buffer_index = -1;
+
gamma = dc_create_gamma();
if (!gamma)
return -ENOMEM;
@@ -208,7 +211,7 @@ static int __set_legacy_tf(struct dc_transfer_func *func,
__drm_lut_to_dc_gamma(lut, gamma, true);
 
res = mod_color_calculate_regamma_params(func, gamma, true, has_rom,
-NULL);
+NULL, _buffer);
 
dc_gamma_release();
 
@@ -221,10 +224,13 @@ static int __set_output_tf(struct dc_transfer_func *func,
   bool has_rom)
 {
struct dc_gamma *gamma = NULL;
+   struct calculate_buffer cal_buffer = {0};
bool res;
 
ASSERT(lut && lut_size == MAX_COLOR_LUT_ENTRIES);
 
+   cal_buffer.buffer_index = -1;
+
gamma = dc_create_gamma();
if (!gamma)
return -ENOMEM;
@@ -248,7 +254,7 @@ static int __set_output_tf(struct dc_transfer_func *func,
 */
gamma->type = GAMMA_CS_TFM_1D;
res = mod_color_calculate_regamma_params(func, gamma, false,
-has_rom, NULL);
+has_rom, NULL, 
_buffer);
}
 
dc_gamma_release();
diff --git a/drivers/gpu/drm/amd/display/modules/color/Makefile 
b/drivers/gpu/drm/amd/display/modules/color/Makefile
index 65c33a76951a..3ee7f27ff93b 100644
--- a/drivers/gpu/drm/amd/display/modules/color/Makefile
+++ b/drivers/gpu/drm/amd/display/modules/color/Makefile
@@ -25,6 +25,10 @@
 
 MOD_COLOR = color_gamma.o
 
+ifdef CONFIG_DRM_AMD_DC_DCN
+MOD_COLOR += color_table.o
+endif
+
 AMD_DAL_MOD_COLOR = $(addprefix $(AMDDALPATH)/modules/color/,$(MOD_COLOR))
 #$(info   DAL COLOR MODULE MAKEFILE )
 
diff --git a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c 
b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
index 9431b48aecb4..05f1651b7171 100644
--- a/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
+++ b/drivers/gpu/drm/amd/display/modules/color/color_gamma.c
@@ -30,20 +30,10 @@
 #include "opp.h"
 #include "color_gamma.h"
 
-#define NUM_PTS_IN_REGION 16
-#define NUM_REGIONS 32
-#define MAX_HW_POINTS (NUM_PTS_IN_REGION*NUM_REGIONS)
-
 static struct hw_x_point coordinates_x[MAX_HW_POINTS + 2];
 
-static struct fixed31_32 pq_table[MAX_HW_POINTS + 2];
-static struct fixed31_32 de_pq_table[MAX_HW_POINTS + 2];
-
 // these are helpers for calculations to reduce stack usage
 // do not depend on these being preserved across calls
-static struct fixed31_32 scratch_1;
-static struct fixed31_32 scratch_2;
-static struct translate_from_linear_space_args scratch_gamma_args;
 
 /* Helper to optimize gamma calculation, only use in translate_from_linear, in
  * particular the dc_fixpt_pow function which is very expensive
@@ -56,9 +46,6 @@ static struct translate_from_linear_space_args 
scratch_gamma_args;
  * just multiply with 2^gamma which can be computed once, and save the result 
so we
  * recursively compute all the values.
  */
-static struct fixed31_32 pow_buffer[NUM_PTS_IN_REGION];
-static struct fixed31_32 gamma_of_2; // 2^gamma
-int pow_buffer_ptr = -1;

/*sRGB   709 2.2 2.4 P3*/
 static const int32_t gamma_numerator01[] = { 31308,18, 0,  0,  
0};
 static const int32_t gamma_numerator02[] = { 12920,4500,   0,  0,  
0};
@@ -66,9 +53,6 @@ static const

[PATCH 01/28] drm/amd/display: correct alpha_en programming for new pixel format

2020-06-07 Thread Qingqing Zhuo 
From: Charlene Liu 

[why]
for following new format, no alpha
   SURFACE_PIXEL_FORMAT_GRPH_RGB10_FLOAT/_FIX:
   SURFACE_PIXEL_FORMAT_GRPH_BGR10_FLOAT/_FIX
   same as case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:

Signed-off-by: Charlene Liu 
Reviewed-by: Chris Park 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
index 42bba7c9548b..4af96cc5d9d6 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c
@@ -181,9 +181,11 @@ static void dpp2_cnv_setup (
break;
case SURFACE_PIXEL_FORMAT_GRPH_RGB10_FIX:
pixel_format = 112;
+   alpha_en = 0;
break;
case SURFACE_PIXEL_FORMAT_GRPH_BGR10_FIX:
pixel_format = 113;
+   alpha_en = 0;
break;
case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
pixel_format = 114;
@@ -199,9 +201,11 @@ static void dpp2_cnv_setup (
break;
case SURFACE_PIXEL_FORMAT_GRPH_RGB10_FLOAT:
pixel_format = 118;
+   alpha_en = 0;
break;
case SURFACE_PIXEL_FORMAT_GRPH_BGR10_FLOAT:
pixel_format = 119;
+   alpha_en = 0;
break;
default:
break;
-- 
2.17.1

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[PATCH 24/28] drm/amd/display: Disable pipe split for modes with borders

2020-06-07 Thread Qingqing Zhuo 
From: Dale Zhao 

[Why]
For some special timing with border, like DMT 640*480 72Hz,
pipe split can't handle well. Thus, it will be black screen
for these special timing.

[How]
Disable pipe split for these timing with borders as W/A.

Signed-off-by: Dale Zhao 
Reviewed-by: Tony Cheng 
Acked-by: Qingqing Zhuo 
---
 .../drm/amd/display/dc/dcn20/dcn20_resource.c   | 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index afa99f967558..fb167393b8fe 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2666,6 +2666,23 @@ int dcn20_validate_apply_pipe_split_flags(
if (plane_count > dc->res_pool->pipe_count / 2)
avoid_split = true;
 
+   /* W/A: Mode timing with borders may not work well with pipe split, 
avoid for this corner case */
+   for (i = 0; i < dc->res_pool->pipe_count; i++) {
+   struct pipe_ctx *pipe = >res_ctx.pipe_ctx[i];
+   struct dc_crtc_timing timing;
+
+   if (!pipe->stream)
+   continue;
+   else {
+   timing = pipe->stream->timing;
+   if (timing.h_border_left + timing.h_border_right
+   + timing.v_border_top + 
timing.v_border_bottom > 0) {
+   avoid_split = true;
+   break;
+   }
+   }
+   }
+
/* Avoid split loop looks for lowest voltage level that allows most 
unsplit pipes possible */
if (avoid_split) {
for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
-- 
2.17.1

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[PATCH 28/28] drm/amd/display: 3.2.89

2020-06-07 Thread Qingqing Zhuo 
From: Aric Cyr 

Signed-off-by: Aric Cyr 
Reviewed-by: Aric Cyr 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index 7da41d465a34..a45b5ea98918 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -42,7 +42,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.88"
+#define DC_VER "3.2.89"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.17.1

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[PATCH 11/28] drm/amd/display: [FW Promotion] Release 1.0.14

2020-06-07 Thread Qingqing Zhuo 
From: Anthony Koo 

[Header Changes]
   - Add SDP transmission deadline for PSR config cmd

Signed-off-by: Anthony Koo 
Reviewed-by: Anthony Koo 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index d04d2fc9ea61..5066c639670e 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x3353119e1
+#define DMUB_FW_VERSION_GIT_HASH 0x5470fd231
 #define DMUB_FW_VERSION_MAJOR 1
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 13
+#define DMUB_FW_VERSION_REVISION 14
 #define DMUB_FW_VERSION_UCODE ((DMUB_FW_VERSION_MAJOR << 24) | 
(DMUB_FW_VERSION_MINOR << 16) | DMUB_FW_VERSION_REVISION)
 #endif
 
@@ -421,6 +421,8 @@ struct dmub_cmd_psr_copy_settings_data {
uint8_t frame_delay;
uint8_t frame_cap_ind;
uint8_t pad[3];
+   uint16_t init_sdp_deadline;
+   uint16_t pad2;
 };
 
 struct dmub_rb_cmd_psr_copy_settings {
-- 
2.17.1

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[PATCH 25/28] drm/amd/display: not reset dmub in driver.

2020-06-07 Thread Qingqing Zhuo 
From: Yongqiang Sun 

[Why]
during S0i3, set power state is toggled a few times,
and dmub uC will restart with current reset/hw_init.

[How]
Remove reset in set power state, and before doing hw_init,
check if dmub is enabled, and doing FW autoload check only
if dmub is already enabled.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index 1e03f6fdabd6..2c4a2fe9311d 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -275,7 +275,11 @@ void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, 
uint32_t wptr_offset)
 
 bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub)
 {
-   return REG_READ(DMCUB_REGION3_CW2_BASE_ADDRESS) != 0;
+   uint32_t is_hw_init;
+
+   REG_GET(DMCUB_CNTL, DMCUB_ENABLE, _hw_init);
+
+   return is_hw_init != 0;
 }
 
 bool dmub_dcn20_is_supported(struct dmub_srv *dmub)
-- 
2.17.1

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[PATCH 21/28] drm/amd/display: Enable use of dmub iff dmcu is disabled

2020-06-07 Thread Qingqing Zhuo 
From: Aurabindo Pillai 

[Why & How]
DMUB command table should be allowed to be used
only if dmcu is explicitly disabled.

Signed-off-by: Aurabindo Pillai 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 7a37065c55d1..7a038eef8902 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1906,6 +1906,8 @@ static bool dcn21_resource_construct(
BREAK_TO_DEBUGGER();
goto create_fail;
}
+
+   dc->debug.dmub_command_table = false;
}
 
if (dc->config.disable_dmcu) {
-- 
2.17.1

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[PATCH 26/28] drm/amd/display: Not doing bios data pack.

2020-06-07 Thread Qingqing Zhuo 
From: Yongqiang Sun 

[Why]
dmub FW running abnormal after resume from S0i3 due
to data aliagnment issue.

[How]
Before having a solution for this issue, temparory
not doing data pack.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Sung Lee 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c 
b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index 150cdbc02d44..9311fec1643c 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -1880,10 +1880,12 @@ static enum bp_result bios_get_board_layout_info(
return BP_RESULT_OK;
 }
 
+
 static uint16_t bios_parser_pack_data_tables(
struct dc_bios *dcb,
void *dst)
 {
+#ifdef PACK_BIOS_DATA
struct bios_parser *bp = BP_FROM_DCB(dcb);
struct atom_rom_header_v2_2 *rom_header = NULL;
struct atom_rom_header_v2_2 *packed_rom_header = NULL;
@@ -1975,6 +1977,9 @@ static uint16_t bios_parser_pack_data_tables(
}
}
return packed_data_tbl_offset;
+#endif
+   // TODO: There is data bytes alignment issue, disable it for now.
+   return 0;
 }
 
 static const struct dc_vbios_funcs vbios_funcs = {
-- 
2.17.1

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[PATCH 16/28] drm/amd/display: remove unnecessary mpcc updates

2020-06-07 Thread Qingqing Zhuo 
From: Dmytro Laktyushkin 

We were updating mpcc if there were tree changes which
is unnecessary since any mpcc being added or removed
will automatically update the tree.

Signed-off-by: Dmytro Laktyushkin 
Reviewed-by: Eric Bernstein 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 13 ++---
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 65e83fdd7b44..db57cb619a0c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1265,14 +1265,13 @@ static void dcn20_detect_pipe_changes(struct pipe_ctx 
*old_pipe, struct pipe_ctx
if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
new_pipe->update_flags.bits.tg_changed = 1;
 
-   /* Detect mpcc blending changes, only dpp inst and bot matter here */
+   /*
+* Detect mpcc blending changes, only dpp inst and opp matter here,
+* mpccs getting removed/inserted update connected ones during their own
+* programming
+*/
if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
-   || old_pipe->stream_res.opp != new_pipe->stream_res.opp
-   || (!old_pipe->bottom_pipe && new_pipe->bottom_pipe)
-   || (old_pipe->bottom_pipe && !new_pipe->bottom_pipe)
-   || (old_pipe->bottom_pipe && new_pipe->bottom_pipe
-   && old_pipe->bottom_pipe->plane_res.mpcc_inst
-   != 
new_pipe->bottom_pipe->plane_res.mpcc_inst))
+   || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
new_pipe->update_flags.bits.mpcc = 1;
 
/* Detect dppclk change */
-- 
2.17.1

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[PATCH 15/28] drm/amd/display: runtime select dmub emulatior.

2020-06-07 Thread Qingqing Zhuo 
From: Yongqiang Sun 

[Why & How]
Add emul specific hw function to dmub, in case of
emulator is created, we can runtime switch between
dmub emulator or dmub uC via is_virtual flag in dmub.

Signed-off-by: Yongqiang Sun 
Reviewed-by: Tony Cheng 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h |  4 
 drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c | 16 
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h 
b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 93d6ff80b248..c6a8d6c54621 100644
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -256,6 +256,10 @@ struct dmub_srv_hw_funcs {
 
void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);
 
+   uint32_t (*emul_get_inbox1_rptr)(struct dmub_srv *dmub);
+
+   void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t 
wptr_offset);
+
bool (*is_supported)(struct dmub_srv *dmub);
 
bool (*is_hw_init)(struct dmub_srv *dmub);
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c 
b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 937f6c3c9911..eb51b7920864 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -199,13 +199,13 @@ enum dmub_status dmub_srv_create(struct dmub_srv *dmub,
 
/* Override (some) hardware funcs based on user params. */
if (params->hw_funcs) {
-   if (params->hw_funcs->get_inbox1_rptr)
-   dmub->hw_funcs.get_inbox1_rptr =
-   params->hw_funcs->get_inbox1_rptr;
+   if (params->hw_funcs->emul_get_inbox1_rptr)
+   dmub->hw_funcs.emul_get_inbox1_rptr =
+   params->hw_funcs->emul_get_inbox1_rptr;
 
-   if (params->hw_funcs->set_inbox1_wptr)
-   dmub->hw_funcs.set_inbox1_wptr =
-   params->hw_funcs->set_inbox1_wptr;
+   if (params->hw_funcs->emul_set_inbox1_wptr)
+   dmub->hw_funcs.emul_set_inbox1_wptr =
+   params->hw_funcs->emul_set_inbox1_wptr;
 
if (params->hw_funcs->is_supported)
dmub->hw_funcs.is_supported =
@@ -502,7 +502,7 @@ enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub)
 */
dmub_rb_flush_pending(>inbox1_rb);
 
-   dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
+   dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt);
return DMUB_STATUS_OK;
 }
 
@@ -557,7 +557,7 @@ enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv 
*dmub,
return DMUB_STATUS_INVALID;
 
for (i = 0; i <= timeout_us; ++i) {
-   dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub);
+   dmub->inbox1_rb.rptr = 
dmub->hw_funcs.get_inbox1_rptr(dmub);
if (dmub_rb_empty(>inbox1_rb))
return DMUB_STATUS_OK;
 
-- 
2.17.1

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[PATCH 19/28] drm/amd/display: Add helper to convert DC status

2020-06-07 Thread Qingqing Zhuo 
From: Rodrigo Siqueira 

During the debugging process related to a hot-plug
problem with 4k display, we realized that we had
some issues related to the global state validation.
This problem was not explicitly highlighted in the
dmesg log, for this reason, this commit adds a function
that converts `enum dc_status` to a human-readable
string and appends the proper warning message in case
of failure.

Signed-off-by: Rodrigo Siqueira 
Reviewed-by: Harry Wentland 
Acked-by: Qingqing Zhuo 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++--
 .../gpu/drm/amd/display/dc/core/dc_debug.c| 59 +++
 .../gpu/drm/amd/display/dc/inc/core_status.h  |  2 +
 3 files changed, 69 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index f348693217d8..9ab0d8521576 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5152,11 +5152,12 @@ create_validate_stream_for_sink(struct 
amdgpu_dm_connector *aconnector,
dc_result = dc_validate_stream(adev->dm.dc, stream);
 
if (dc_result != DC_OK) {
-   DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation 
with error %d\n",
+   DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation 
with error %d (%s)\n",
  drm_mode->hdisplay,
  drm_mode->vdisplay,
  drm_mode->clock,
- dc_result);
+ dc_result,
+ dc_status_to_str(dc_result));
 
dc_stream_release(stream);
stream = NULL;
@@ -8593,7 +8594,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
struct drm_plane_state *old_plane_state, *new_plane_state;
enum surface_update_type update_type = UPDATE_TYPE_FAST;
enum surface_update_type overall_update_type = UPDATE_TYPE_FAST;
-
+   enum dc_status status;
int ret, i;
 
/*
@@ -8805,8 +8806,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
ret = drm_dp_mst_atomic_check(state);
if (ret)
goto fail;
-
-   if (dc_validate_global_state(dc, dm_state->context, false) != 
DC_OK) {
+   status = dc_validate_global_state(dc, dm_state->context, false);
+   if (status != DC_OK) {
+   DC_LOG_WARNING("DC global validation failure: %s (%d)",
+  dc_status_to_str(status), status);
ret = -EINVAL;
goto fail;
}
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
index 502ed3c7959d..87d89449b9af 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c
@@ -365,3 +365,62 @@ void context_clock_trace(
context->bw_ctx.bw.dcn.clk.socclk_khz);
 #endif
 }
+
+/**
+ * dc_status_to_str - convert dc_status to a human readable string
+ * @status: dc_status to be converted
+ *
+ * Return:
+ * A string describing the DC status.
+ */
+char *dc_status_to_str(enum dc_status status)
+{
+   switch (status) {
+   case DC_OK:
+   return "DC OK";
+   case DC_NO_CONTROLLER_RESOURCE:
+   return "No controller resource";
+   case DC_NO_STREAM_ENC_RESOURCE:
+   return "No stream encoder";
+   case DC_NO_CLOCK_SOURCE_RESOURCE:
+   return "No clock source";
+   case DC_FAIL_CONTROLLER_VALIDATE:
+   return "Controller validation failure";
+   case DC_FAIL_ENC_VALIDATE:
+   return "Encoder validation failure";
+   case DC_FAIL_ATTACH_SURFACES:
+   return "Surfaces attachment failure";
+   case DC_FAIL_DETACH_SURFACES:
+   return "Surfaces detachment failure";
+   case DC_FAIL_SURFACE_VALIDATE:
+   return "Surface validation failure";
+   case DC_NO_DP_LINK_BANDWIDTH:
+   return "No DP link bandwidth";
+   case DC_EXCEED_DONGLE_CAP:
+   return "Exceed dongle capability";
+   case DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED:
+   return "Unsupported pixel format";
+   case DC_FAIL_BANDWIDTH_VALIDATE:
+   return "Bandwidth validation failure (BW and Watermark)";
+   case DC_FAIL_SCALING:
+   return "Scaling failure";
+   case DC_FAIL_DP_LINK_TRAINING:
+   return "DP link training failure";
+   case DC_FAIL_DSC_VALIDATE:
+   return "DSC validation failure";
+   case DC_NO_DSC_RESOURCE:
+   return "No DSC resource";
+   case DC_FAIL_UNSUPPORTED_1:
+

[PATCH 08/28] drm/amd/display: Revert "enable plane if plane_status changed"

2020-06-07 Thread Qingqing Zhuo 
From: Hugo Hu 

revert commit 77dcea7a0b133b362b2ebbf494eb13ee3e946836.

Signed-off-by: Hugo Hu 
Reviewed-by: Tony Cheng 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 9 +
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 0b318f799db3..65e83fdd7b44 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1209,20 +1209,13 @@ void dcn20_pipe_control_lock(
 
 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct 
pipe_ctx *new_pipe)
 {
-   bool plane_state_update = false;
new_pipe->update_flags.raw = 0;
 
/* Exit on unchanged, unused pipe */
if (!old_pipe->plane_state && !new_pipe->plane_state)
return;
-
-   /* Detect plane state update */
-   if (old_pipe->plane_state && new_pipe->plane_state
-   && (old_pipe->plane_state != new_pipe->plane_state)) {
-   plane_state_update = true;
-   }
/* Detect pipe enable/disable */
-   if ((!old_pipe->plane_state && new_pipe->plane_state) || 
plane_state_update) {
+   if (!old_pipe->plane_state && new_pipe->plane_state) {
new_pipe->update_flags.bits.enable = 1;
new_pipe->update_flags.bits.mpcc = 1;
new_pipe->update_flags.bits.dppclk = 1;
-- 
2.17.1

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[PATCH 03/28] drm/amd/display: Fix incorrect dcn1 bandwidth calculations

2020-06-07 Thread Qingqing Zhuo 
From: Michael Strauss 

[WHY]
Typos cause bandwidth calculation errors, one
of which can cause infinite loop on dcn1 with eDP

Signed-off-by: Michael Strauss 
Reviewed-by: Dmytro Laktyushkin 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c 
b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
index 1ef0074302c5..41284e263325 100644
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calc_auto.c
@@ -805,7 +805,7 @@ void mode_support_and_system_configuration(struct 
dcn_bw_internal_vars *v)
 
if (v->pte_enable == dcn_bw_yes && 
v->dcc_enable[k] == dcn_bw_yes) {

v->time_for_meta_pte_without_immediate_flip = dcn_bw_max3(
-   
v->meta_pte_bytes_frame[k] / v->prefetch_bandwidth[k],
+   
v->meta_pte_bytes_frame[k] / v->prefetch_bw[k],

v->extra_latency,
v->htotal[k] / 
v->pixel_clock[k] / 4.0);
} else {
@@ -814,7 +814,7 @@ void mode_support_and_system_configuration(struct 
dcn_bw_internal_vars *v)
 
if (v->pte_enable == dcn_bw_yes || 
v->dcc_enable[k] == dcn_bw_yes) {

v->time_for_meta_and_dpte_row_without_immediate_flip = dcn_bw_max3((
-   
v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bandwidth[k],
+   
v->meta_row_bytes[k] + v->dpte_bytes_per_row[k]) / v->prefetch_bw[k],
v->htotal[k] / 
v->pixel_clock[k] - v->time_for_meta_pte_without_immediate_flip,

v->extra_latency);
} else {
@@ -827,7 +827,7 @@ void mode_support_and_system_configuration(struct 
dcn_bw_internal_vars *v)

v->lines_for_meta_and_dpte_row_without_immediate_flip[k] =dcn_bw_floor2(4.0 * 
(v->time_for_meta_and_dpte_row_without_immediate_flip / (v->htotal[k] / 
v->pixel_clock[k]) + 0.125), 1.0) / 4;
v->maximum_vstartup = 
v->maximum_vstartup - 1;
 
-   if 
(v->lines_for_meta_pte_without_immediate_flip[k] < 8.0 && 
v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0)
+   if 
(v->lines_for_meta_pte_without_immediate_flip[k] < 32.0 && 
v->lines_for_meta_and_dpte_row_without_immediate_flip[k] < 16.0)
break;
 
} while(1);
-- 
2.17.1

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[PATCH 07/28] drm/amd/display: Remove unused macro from dcn21

2020-06-07 Thread Qingqing Zhuo 
From: Roman Li 

[Why]
SOC_BOUNDING_BOX_VALID is unused and not required for dcn21.

[How]
Remove it.

Signed-off-by: Roman Li 
Reviewed-by: Bhawanpreet Lakha 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index 00436654c584..24aa3f1db031 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -88,7 +88,6 @@
 #include "dce/dmub_psr.h"
 #include "dce/dmub_abm.h"
 
-#define SOC_BOUNDING_BOX_VALID false
 #define DC_LOGGER_INIT(logger)
 
 
-- 
2.17.1

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[PATCH 10/28] drm/amd/display: update audio wall clock programming

2020-06-07 Thread Qingqing Zhuo 
From: Charlene Liu 

[why]
for audio on real TV issue.

[how]
-add wall clock programming for DPREF based when
Pixel clock is done by DP DTO.

Signed-off-by: Charlene Liu 
Reviewed-by: Chris Park 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dce/dce_audio.c  | 4 +++-
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 4 +---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c 
b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
index 5a35495bc11d..408046579712 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c
@@ -140,6 +140,8 @@ static void check_audio_bandwidth_hdmi(
bool limit_freq_to_88_2_khz = false;
bool limit_freq_to_96_khz = false;
bool limit_freq_to_174_4_khz = false;
+   if (!crtc_info)
+   return;
 
/* For two channels supported return whatever sink support,unmodified*/
if (channel_count > 2) {
@@ -784,7 +786,7 @@ void dce_aud_wall_dto_setup(
 
struct azalia_clock_info clock_info = { 0 };
 
-   if (dc_is_hdmi_signal(signal)) {
+   if (dc_is_hdmi_tmds_signal(signal)) {
uint32_t src_sel;
 
/*DTO0 Programming goal:
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 2ec5e9e1bdc6..0ce430cf4dd0 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1148,7 +1148,7 @@ static void build_audio_output(

pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
 
 /*for HDMI, audio ACR is with deep color ratio factor*/
-   if (dc_is_hdmi_signal(pipe_ctx->stream->signal) &&
+   if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&
audio_output->crtc_info.requested_pixel_clock_100Hz ==
(stream->timing.pix_clk_100hz)) {
if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == 
PIXEL_ENCODING_YCBCR420) {
@@ -1963,10 +1963,8 @@ static void dce110_setup_audio_dto(
 
if (pipe_ctx->top_pipe)
continue;
-
if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
continue;
-
if (pipe_ctx->stream_res.audio != NULL) {
struct audio_output audio_output;
 
-- 
2.17.1

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[PATCH 00/28] DC Patches June 8, 2020

2020-06-07 Thread Qingqing Zhuo 
This DC patchset brings changes in multiple areas. In summary, we highlight:
* Bug fixes in bandwidth calculation, DSC calculation, etc.
* Improvements in DP 
* Code refactoring and cleanup
* FW promotion

Anthony Koo (3):
  drm/amd/display: [FW Promotion] Release 1.0.13
  drm/amd/display: [FW Promotion] Release 1.0.14
  drm/amd/display: [FW Promotion] Release 1.0.15

Aric Cyr (3):
  drm/amd/display: 3.2.88
  drm/amd/display: Improve DisplayPort monitor interop
  drm/amd/display: 3.2.89

Aurabindo Pillai (1):
  drm/amd/display: Enable use of dmub iff dmcu is disabled

Charlene Liu (2):
  drm/amd/display: correct alpha_en programming for new pixel format
  drm/amd/display: update audio wall clock programming

Dale Zhao (1):
  drm/amd/display: Disable pipe split for modes with borders

Dmytro Laktyushkin (2):
  drm/amd/display: remove unnecessary mpcc updates
  drm/amd/display: make calculate watermarks a function pointer

Hugo Hu (1):
  drm/amd/display: Revert "enable plane if plane_status changed"

Jun Lei (1):
  drm/amd/display: add support for per-state dummy-pstate latency

Lewis Huang (1):
  drm/amd/display: change global buffer to local buffer

Martin Tsai (1):
  drm/amd/display: Force delay after DP receive power up

Michael Strauss (1):
  drm/amd/display: Fix incorrect dcn1 bandwidth calculations

Nicholas Kazlauskas (2):
  drm/amd/display: Use u16 for drm_bpp in DSC calculations
  drm/amd/display: Fix VBA chroma calculation for pipe splitting

Rodrigo Siqueira (2):
  drm/amd/display: Rework dsc to isolate FPU operations
  drm/amd/display: Add helper to convert DC status

Roman Li (1):
  drm/amd/display: Remove unused macro from dcn21

Wenjing Liu (1):
  drm/amd/display: Revert "DP link layer test 4.2.1.1 fix due to specs
update"

Wesley Chalmers (1):
  drm/amd/display: Move call to disable DPG

Yongqiang Sun (3):
  drm/amd/display: runtime select dmub emulatior.
  drm/amd/display: not reset dmub in driver.
  drm/amd/display: Not doing bios data pack.

po-tchen (1):
  drm/amd/display: Passing initial SDP deadline to dmub

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  13 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_color.c   |  10 +-
 .../drm/amd/display/dc/bios/bios_parser2.c|   5 +
 .../drm/amd/display/dc/calcs/dcn_calc_auto.c  |   6 +-
 drivers/gpu/drm/amd/display/dc/core/dc.c  |   2 +-
 .../gpu/drm/amd/display/dc/core/dc_debug.c|  59 +++
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |   8 +-
 .../gpu/drm/amd/display/dc/core/dc_link_ddc.c |  13 +-
 .../gpu/drm/amd/display/dc/core/dc_link_dp.c  |  75 +
 .../drm/amd/display/dc/core/dc_link_hwss.c|   2 +-
 drivers/gpu/drm/amd/display/dc/dc.h   |   4 +-
 drivers/gpu/drm/amd/display/dc/dc_link.h  |   1 -
 .../gpu/drm/amd/display/dc/dce/dce_audio.c|   4 +-
 drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c |   1 +
 .../display/dc/dce110/dce110_hw_sequencer.c   |  15 +-
 .../gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c  |   4 +
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c|  22 +--
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  17 ++
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |   5 +-
 .../drm/amd/display/dc/dml/display_mode_vba.c |   4 +-
 drivers/gpu/drm/amd/display/dc/dsc/Makefile   |   2 -
 drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c   |  18 +--
 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c  | 151 +-
 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h  |   5 +-
 .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c  |  27 +---
 .../gpu/drm/amd/display/dc/inc/core_status.h  |   2 +
 .../gpu/drm/amd/display/dc/inc/core_types.h   |   6 +-
 .../gpu/drm/amd/display/dc/inc/dc_link_ddc.h  |   2 +-
 .../gpu/drm/amd/display/dc/inc/dc_link_dp.h   |   2 +-
 .../gpu/drm/amd/display/dc/inc/hw/clk_mgr.h   |   6 +
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h   |   4 +
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  70 +++-
 .../gpu/drm/amd/display/dmub/src/dmub_dcn20.c |   6 +-
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   |  16 +-
 .../drm/amd/display/modules/color/Makefile|   4 +
 .../amd/display/modules/color/color_gamma.c   | 115 ++---
 .../amd/display/modules/color/color_gamma.h   |  18 ++-
 .../amd/display/modules/color/color_table.c   |  48 ++
 .../amd/display/modules/color/color_table.h   |  47 ++
 39 files changed, 612 insertions(+), 207 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/modules/color/color_table.c
 create mode 100644 drivers/gpu/drm/amd/display/modules/color/color_table.h

-- 
2.17.1

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[PATCH 12/28] drm/amd/display: 3.2.88

2020-06-07 Thread Qingqing Zhuo 
From: Aric Cyr 

Signed-off-by: Aric Cyr 
Reviewed-by: Aric Cyr 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index e09eb876a366..8cdbfa15874b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -42,7 +42,7 @@
 #include "inc/hw/dmcu.h"
 #include "dml/display_mode_lib.h"
 
-#define DC_VER "3.2.87"
+#define DC_VER "3.2.88"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.17.1

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[PATCH 04/28] drm/amd/display: [FW Promotion] Release 1.0.13

2020-06-07 Thread Qingqing Zhuo 
From: Anthony Koo 

[Header Changes]
   - Version bump to 1.0.13

Signed-off-by: Anthony Koo 
Reviewed-by: Nicholas Kazlauskas 
Acked-by: Qingqing Zhuo 
---
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h 
b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 15ff4e471c3d..d04d2fc9ea61 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -36,10 +36,10 @@
 
 /* Firmware versioning. */
 #ifdef DMUB_EXPOSE_VERSION
-#define DMUB_FW_VERSION_GIT_HASH 0x718f63a96
+#define DMUB_FW_VERSION_GIT_HASH 0x3353119e1
 #define DMUB_FW_VERSION_MAJOR 1
 #define DMUB_FW_VERSION_MINOR 0
-#define DMUB_FW_VERSION_REVISION 12
+#define DMUB_FW_VERSION_REVISION 13
 #define DMUB_FW_VERSION_UCODE ((DMUB_FW_VERSION_MAJOR << 24) | 
(DMUB_FW_VERSION_MINOR << 16) | DMUB_FW_VERSION_REVISION)
 #endif
 
-- 
2.17.1

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RE: [PATCH] drm/amdgpu/soc15: fix using ip discovery tables on renoir (v2)

2020-06-07 Thread Quan, Evan 
[AMD Official Use Only - Internal Distribution Only]

Acked-by: Evan Quan 

-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Friday, June 5, 2020 11:40 PM
To: amd-gfx@lists.freedesktop.org; Liang, Prike 
Cc: Deucher, Alexander 
Subject: [PATCH] drm/amdgpu/soc15: fix using ip discovery tables on renoir (v2)

The PWR block moved into SMUIO, so the ip discovery table
doesn't have an entry for PWR, but the register has the
same absolute offset, so just patch up the offsets after
updating the offsets from the IP discovery table.

v2: PWR became SMUIO block 1.  fix the mapping.

Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c 
b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 623745b2d8b3..dd17a8422111 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -686,6 +686,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
 DRM_WARN("failed to init reg base from ip discovery table, "
  "fallback to legacy init method\n");
 vega10_reg_base_init(adev);
+} else {
+/* PWR block was merged into SMUIO on renoir and became SMUIO block 1 */
+adev->reg_offset[PWR_HWIP][0] = adev->reg_offset[SMUIO_HWIP][1];
 }
 }
 break;
--
2.25.4

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