[PATCH] drm/amdkfd: Fix the warning of array-index-out-of-bounds

2022-10-07 Thread Ma Jun 
Increasing the simbling array size to fix the warning of
array-index-out-of-bounds. The VCRAT_SIZE_FOR_GPU is also
increased accrordingly.

Signed-off-by: Ma Jun 
---
 drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 +-
 drivers/gpu/drm/amd/amdkfd/kfd_crat.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c 
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
index 477a30981c1b..3ec425c3737d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
@@ -1683,7 +1683,7 @@ int kfd_create_crat_image_acpi(void **crat_image, size_t 
*size)
  * expected to cover all known conditions. But to be safe additional check
  * is put in the code to ensure we don't overwrite.
  */
-#define VCRAT_SIZE_FOR_GPU (4 * PAGE_SIZE)
+#define VCRAT_SIZE_FOR_GPU (6 * PAGE_SIZE)
 
 /* kfd_fill_cu_for_cpu - Fill in Compute info for the given CPU NUMA node
  *
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h 
b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h
index fbb5f6c32ef5..31a4bbc9f9cb 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h
@@ -80,7 +80,7 @@ struct crat_header {
 #define CRAT_SUBTYPE_IOLINK_AFFINITY   5
 #define CRAT_SUBTYPE_MAX   6
 
-#define CRAT_SIBLINGMAP_SIZE   32
+#define CRAT_SIBLINGMAP_SIZE   64
 
 /*
  * ComputeUnit Affinity structure and definitions
-- 
2.25.1

RE: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

2022-10-07 Thread Gao, Likun 
[AMD Official Use Only - General]

Yes, thanks for helping explanation.

Regards,
Likun

-Original Message-
From: Zhu, Jiadong  
Sent: Saturday, October 8, 2022 1:17 PM
To: Zhang, Hawking ; Gao, Likun ; 
amd-gfx@lists.freedesktop.org
Cc: Grodzovsky, Andrey ; Michel Dänzer 
; Tuikov, Luben ; Koenig, Christian 

Subject: RE: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

I think Likun means to stop creating sw ring if there is no gfx ring existed.

Thanks,
Jiadong

-Original Message-
From: Zhang, Hawking 
Sent: Saturday, October 8, 2022 12:37 PM
To: Gao, Likun ; Zhu, Jiadong ; 
amd-gfx@lists.freedesktop.org
Cc: Grodzovsky, Andrey ; Michel Dänzer 
; Tuikov, Luben ; Zhu, Jiadong 
; Koenig, Christian 
Subject: RE: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

[AMD Official Use Only - General]

I don't think so. In such case, current cwsr and user queue mechanism handle 
the pre-emption very well. The command submission actually bypass drm GPU 
scheduler.

Regards,
Hawking

-Original Message-
From: amd-gfx  On Behalf Of Gao, Likun
Sent: Saturday, October 8, 2022 11:52
To: Zhu, Jiadong ; amd-gfx@lists.freedesktop.org
Cc: Grodzovsky, Andrey ; Michel Dänzer 
; Tuikov, Luben ; Zhu, Jiadong 
; Koenig, Christian 
Subject: RE: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

[AMD Official Use Only - General]

Shall we need to deal with the situation that no real gfx ring exist? 
(adev->gfx.num_gfx_rings is 0)

Regards,
Likun

-Original Message-
From: amd-gfx  On Behalf Of 
jiadong@amd.com
Sent: Thursday, September 29, 2022 5:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben ; Michel Dänzer ; 
Zhu, Jiadong ; Koenig, Christian 
; Grodzovsky, Andrey 
Subject: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

From: "Jiadong.Zhu" 

Set ring functions with software ring callbacks on gfx9.

The software ring could be tested by debugfs_test_ib case.

v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for software rings.
v5: Update for code format. Fix conflict.
v6: Remove unnecessary checks and enable software ring on gfx9 by default.
v7: Use static array for software ring names and priorities.

Acked-by: Luben Tuikov 
Cc: Christian Koenig 
Cc: Luben Tuikov 
Cc: Andrey Grodzovsky 
Cc: Michel Dänzer 
Signed-off-by: Jiadong.Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h  |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c |  20 
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h |   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 104 ++-
 5 files changed, 127 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 9996dadb39f7..4fdfc3ec134a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -348,6 +348,7 @@ struct amdgpu_gfx {
 
boolis_poweron;
 
+   struct amdgpu_ring  sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS];
struct amdgpu_ring_mux  muxer;
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 40b1277b4f0c..f08ee1ac281c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -39,6 +39,7 @@ struct amdgpu_vm;
 #define AMDGPU_MAX_RINGS   28
 #define AMDGPU_MAX_HWIP_RINGS  8
 #define AMDGPU_MAX_GFX_RINGS   2
+#define AMDGPU_MAX_SW_GFX_RINGS 2
 #define AMDGPU_MAX_COMPUTE_RINGS   8
 #define AMDGPU_MAX_VCE_RINGS   3
 #define AMDGPU_MAX_UVD_ENC_RINGS   2
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
index 43cab8a37754..2e64ffccc030 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
@@ -29,6 +29,14 @@
 
 #define AMDGPU_MUX_RESUBMIT_JIFFIES_TIMEOUT (HZ / 2)
 
+static const struct ring_info {
+   unsigned int hw_pio;
+   const char *ring_name;
+} sw_ring_info[] = {
+   { AMDGPU_RING_PRIO_DEFAULT, "gfx_low"},
+   { AMDGPU_RING_PRIO_2, "gfx_high"},
+};
+
 int amdgpu_ring_mux_init(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring,
 unsigned int entry_size)
 {
@@ -215,3 +223,15 @@ void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, 
uint32_t count)  {
WARN_ON(!ring->is_sw_ring);
 }
+
+const char *amdgpu_sw_ring_name(int idx) {
+   return idx < ARRAY_SIZE(sw_ring_info) ?
+   sw_ring_info[idx].ring_name : NULL;
+}
+
+unsigned int amdgpu_sw_ring_priority(int idx) {
+   return idx < ARRAY_SIZE(sw_ring_info) ?
+   sw_ring_info[idx].hw_pio : AMDGPU_RING_PRIO_DEFAULT; }
diff --git

RE: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

2022-10-07 Thread Zhu, Jiadong 
I think Likun means to stop creating sw ring if there is no gfx ring existed.

Thanks,
Jiadong

-Original Message-
From: Zhang, Hawking  
Sent: Saturday, October 8, 2022 12:37 PM
To: Gao, Likun ; Zhu, Jiadong ; 
amd-gfx@lists.freedesktop.org
Cc: Grodzovsky, Andrey ; Michel Dänzer 
; Tuikov, Luben ; Zhu, Jiadong 
; Koenig, Christian 
Subject: RE: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

[AMD Official Use Only - General]

I don't think so. In such case, current cwsr and user queue mechanism handle 
the pre-emption very well. The command submission actually bypass drm GPU 
scheduler.

Regards,
Hawking

-Original Message-
From: amd-gfx  On Behalf Of Gao, Likun
Sent: Saturday, October 8, 2022 11:52
To: Zhu, Jiadong ; amd-gfx@lists.freedesktop.org
Cc: Grodzovsky, Andrey ; Michel Dänzer 
; Tuikov, Luben ; Zhu, Jiadong 
; Koenig, Christian 
Subject: RE: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

[AMD Official Use Only - General]

Shall we need to deal with the situation that no real gfx ring exist? 
(adev->gfx.num_gfx_rings is 0)

Regards,
Likun

-Original Message-
From: amd-gfx  On Behalf Of 
jiadong@amd.com
Sent: Thursday, September 29, 2022 5:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben ; Michel Dänzer ; 
Zhu, Jiadong ; Koenig, Christian 
; Grodzovsky, Andrey 
Subject: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

From: "Jiadong.Zhu" 

Set ring functions with software ring callbacks on gfx9.

The software ring could be tested by debugfs_test_ib case.

v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for software rings.
v5: Update for code format. Fix conflict.
v6: Remove unnecessary checks and enable software ring on gfx9 by default.
v7: Use static array for software ring names and priorities.

Acked-by: Luben Tuikov 
Cc: Christian Koenig 
Cc: Luben Tuikov 
Cc: Andrey Grodzovsky 
Cc: Michel Dänzer 
Signed-off-by: Jiadong.Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h  |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c |  20 
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h |   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 104 ++-
 5 files changed, 127 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 9996dadb39f7..4fdfc3ec134a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -348,6 +348,7 @@ struct amdgpu_gfx {
 
boolis_poweron;
 
+   struct amdgpu_ring  sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS];
struct amdgpu_ring_mux  muxer;
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 40b1277b4f0c..f08ee1ac281c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -39,6 +39,7 @@ struct amdgpu_vm;
 #define AMDGPU_MAX_RINGS   28
 #define AMDGPU_MAX_HWIP_RINGS  8
 #define AMDGPU_MAX_GFX_RINGS   2
+#define AMDGPU_MAX_SW_GFX_RINGS 2
 #define AMDGPU_MAX_COMPUTE_RINGS   8
 #define AMDGPU_MAX_VCE_RINGS   3
 #define AMDGPU_MAX_UVD_ENC_RINGS   2
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
index 43cab8a37754..2e64ffccc030 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
@@ -29,6 +29,14 @@
 
 #define AMDGPU_MUX_RESUBMIT_JIFFIES_TIMEOUT (HZ / 2)
 
+static const struct ring_info {
+   unsigned int hw_pio;
+   const char *ring_name;
+} sw_ring_info[] = {
+   { AMDGPU_RING_PRIO_DEFAULT, "gfx_low"},
+   { AMDGPU_RING_PRIO_2, "gfx_high"},
+};
+
 int amdgpu_ring_mux_init(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring,
 unsigned int entry_size)
 {
@@ -215,3 +223,15 @@ void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, 
uint32_t count)  {
WARN_ON(!ring->is_sw_ring);
 }
+
+const char *amdgpu_sw_ring_name(int idx) {
+   return idx < ARRAY_SIZE(sw_ring_info) ?
+   sw_ring_info[idx].ring_name : NULL;
+}
+
+unsigned int amdgpu_sw_ring_priority(int idx) {
+   return idx < ARRAY_SIZE(sw_ring_info) ?
+   sw_ring_info[idx].hw_pio : AMDGPU_RING_PRIO_DEFAULT; }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
index d91629589577..28399f4b0e5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
@@ -73,4 +73,6 @@ void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, 
uint32_t count);  void amdgpu_sw_ring_ib_begin(struct amdgpu_ring *ring);  void 
amdgpu_sw_ring_ib_end(struct amdgpu_ring

RE: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

2022-10-07 Thread Zhu, Jiadong 
I agree, let me update the patch.

Thanks,
Jiadong

-Original Message-
From: Gao, Likun  
Sent: Saturday, October 8, 2022 11:52 AM
To: Zhu, Jiadong ; amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben ; Michel Dänzer ; 
Zhu, Jiadong ; Koenig, Christian 
; Grodzovsky, Andrey 
Subject: RE: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

[AMD Official Use Only - General]

Shall we need to deal with the situation that no real gfx ring exist? 
(adev->gfx.num_gfx_rings is 0)

Regards,
Likun

-Original Message-
From: amd-gfx  On Behalf Of 
jiadong@amd.com
Sent: Thursday, September 29, 2022 5:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben ; Michel Dänzer ; 
Zhu, Jiadong ; Koenig, Christian 
; Grodzovsky, Andrey 
Subject: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

From: "Jiadong.Zhu" 

Set ring functions with software ring callbacks on gfx9.

The software ring could be tested by debugfs_test_ib case.

v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for software rings.
v5: Update for code format. Fix conflict.
v6: Remove unnecessary checks and enable software ring on gfx9 by default.
v7: Use static array for software ring names and priorities.

Acked-by: Luben Tuikov 
Cc: Christian Koenig 
Cc: Luben Tuikov 
Cc: Andrey Grodzovsky 
Cc: Michel Dänzer 
Signed-off-by: Jiadong.Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h  |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c |  20 
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h |   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 104 ++-
 5 files changed, 127 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 9996dadb39f7..4fdfc3ec134a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -348,6 +348,7 @@ struct amdgpu_gfx {
 
boolis_poweron;
 
+   struct amdgpu_ring  sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS];
struct amdgpu_ring_mux  muxer;
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 40b1277b4f0c..f08ee1ac281c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -39,6 +39,7 @@ struct amdgpu_vm;
 #define AMDGPU_MAX_RINGS   28
 #define AMDGPU_MAX_HWIP_RINGS  8
 #define AMDGPU_MAX_GFX_RINGS   2
+#define AMDGPU_MAX_SW_GFX_RINGS 2
 #define AMDGPU_MAX_COMPUTE_RINGS   8
 #define AMDGPU_MAX_VCE_RINGS   3
 #define AMDGPU_MAX_UVD_ENC_RINGS   2
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
index 43cab8a37754..2e64ffccc030 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
@@ -29,6 +29,14 @@
 
 #define AMDGPU_MUX_RESUBMIT_JIFFIES_TIMEOUT (HZ / 2)
 
+static const struct ring_info {
+   unsigned int hw_pio;
+   const char *ring_name;
+} sw_ring_info[] = {
+   { AMDGPU_RING_PRIO_DEFAULT, "gfx_low"},
+   { AMDGPU_RING_PRIO_2, "gfx_high"},
+};
+
 int amdgpu_ring_mux_init(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring,
 unsigned int entry_size)
 {
@@ -215,3 +223,15 @@ void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, 
uint32_t count)  {
WARN_ON(!ring->is_sw_ring);
 }
+
+const char *amdgpu_sw_ring_name(int idx) {
+   return idx < ARRAY_SIZE(sw_ring_info) ?
+   sw_ring_info[idx].ring_name : NULL;
+}
+
+unsigned int amdgpu_sw_ring_priority(int idx) {
+   return idx < ARRAY_SIZE(sw_ring_info) ?
+   sw_ring_info[idx].hw_pio : AMDGPU_RING_PRIO_DEFAULT; }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
index d91629589577..28399f4b0e5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
@@ -73,4 +73,6 @@ void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, 
uint32_t count);  void amdgpu_sw_ring_ib_begin(struct amdgpu_ring *ring);  void 
amdgpu_sw_ring_ib_end(struct amdgpu_ring *ring);
 
+const char *amdgpu_sw_ring_name(int idx); unsigned int 
+amdgpu_sw_ring_priority(int idx);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6b609f33261f..3b607c09d267 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -47,6 +47,7 @@
 
 #include "amdgpu_ras.h"
 
+#include "amdgpu_ring_mux.h"
 #include "gfx_v9_4.h"
 #include "gfx_v9_0.h"
 #include "gfx_v9_4_2.h"
@@ -56,6 +57,7 @@
 #include "asic_reg/gc/gc_9_0_default.h"
 
 #define GFX9_NUM_GFX_RINGS 1
+#define GFX9_NUM_SW_GFX_RINGS  2

RE: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

2022-10-07 Thread Zhang, Hawking 
[AMD Official Use Only - General]

I don't think so. In such case, current cwsr and user queue mechanism handle 
the pre-emption very well. The command submission actually bypass drm GPU 
scheduler.

Regards,
Hawking

-Original Message-
From: amd-gfx  On Behalf Of Gao, Likun
Sent: Saturday, October 8, 2022 11:52
To: Zhu, Jiadong ; amd-gfx@lists.freedesktop.org
Cc: Grodzovsky, Andrey ; Michel Dänzer 
; Tuikov, Luben ; Zhu, Jiadong 
; Koenig, Christian 
Subject: RE: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

[AMD Official Use Only - General]

Shall we need to deal with the situation that no real gfx ring exist? 
(adev->gfx.num_gfx_rings is 0)

Regards,
Likun

-Original Message-
From: amd-gfx  On Behalf Of 
jiadong@amd.com
Sent: Thursday, September 29, 2022 5:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben ; Michel Dänzer ; 
Zhu, Jiadong ; Koenig, Christian 
; Grodzovsky, Andrey 
Subject: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

From: "Jiadong.Zhu" 

Set ring functions with software ring callbacks on gfx9.

The software ring could be tested by debugfs_test_ib case.

v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for software rings.
v5: Update for code format. Fix conflict.
v6: Remove unnecessary checks and enable software ring on gfx9 by default.
v7: Use static array for software ring names and priorities.

Acked-by: Luben Tuikov 
Cc: Christian Koenig 
Cc: Luben Tuikov 
Cc: Andrey Grodzovsky 
Cc: Michel Dänzer 
Signed-off-by: Jiadong.Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h  |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c |  20 
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h |   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 104 ++-
 5 files changed, 127 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 9996dadb39f7..4fdfc3ec134a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -348,6 +348,7 @@ struct amdgpu_gfx {
 
boolis_poweron;
 
+   struct amdgpu_ring  sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS];
struct amdgpu_ring_mux  muxer;
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 40b1277b4f0c..f08ee1ac281c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -39,6 +39,7 @@ struct amdgpu_vm;
 #define AMDGPU_MAX_RINGS   28
 #define AMDGPU_MAX_HWIP_RINGS  8
 #define AMDGPU_MAX_GFX_RINGS   2
+#define AMDGPU_MAX_SW_GFX_RINGS 2
 #define AMDGPU_MAX_COMPUTE_RINGS   8
 #define AMDGPU_MAX_VCE_RINGS   3
 #define AMDGPU_MAX_UVD_ENC_RINGS   2
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
index 43cab8a37754..2e64ffccc030 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
@@ -29,6 +29,14 @@
 
 #define AMDGPU_MUX_RESUBMIT_JIFFIES_TIMEOUT (HZ / 2)
 
+static const struct ring_info {
+   unsigned int hw_pio;
+   const char *ring_name;
+} sw_ring_info[] = {
+   { AMDGPU_RING_PRIO_DEFAULT, "gfx_low"},
+   { AMDGPU_RING_PRIO_2, "gfx_high"},
+};
+
 int amdgpu_ring_mux_init(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring,
 unsigned int entry_size)
 {
@@ -215,3 +223,15 @@ void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, 
uint32_t count)  {
WARN_ON(!ring->is_sw_ring);
 }
+
+const char *amdgpu_sw_ring_name(int idx) {
+   return idx < ARRAY_SIZE(sw_ring_info) ?
+   sw_ring_info[idx].ring_name : NULL;
+}
+
+unsigned int amdgpu_sw_ring_priority(int idx) {
+   return idx < ARRAY_SIZE(sw_ring_info) ?
+   sw_ring_info[idx].hw_pio : AMDGPU_RING_PRIO_DEFAULT; }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
index d91629589577..28399f4b0e5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
@@ -73,4 +73,6 @@ void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, 
uint32_t count);  void amdgpu_sw_ring_ib_begin(struct amdgpu_ring *ring);  void 
amdgpu_sw_ring_ib_end(struct amdgpu_ring *ring);
 
+const char *amdgpu_sw_ring_name(int idx); unsigned int 
+amdgpu_sw_ring_priority(int idx);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6b609f33261f..3b607c09d267 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -47,6 +47,7 @@
 
 #include "amdgpu_ras.h"
 
+#include "amdgpu_ring_mux.h"
 #include

RE: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

2022-10-07 Thread Gao, Likun 
[AMD Official Use Only - General]

Shall we need to deal with the situation that no real gfx ring exist? 
(adev->gfx.num_gfx_rings is 0)

Regards,
Likun

-Original Message-
From: amd-gfx  On Behalf Of 
jiadong@amd.com
Sent: Thursday, September 29, 2022 5:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Tuikov, Luben ; Michel Dänzer ; 
Zhu, Jiadong ; Koenig, Christian 
; Grodzovsky, Andrey 
Subject: [PATCH 2/4] drm/amdgpu: Add software ring callbacks for gfx9 (v7)

From: "Jiadong.Zhu" 

Set ring functions with software ring callbacks on gfx9.

The software ring could be tested by debugfs_test_ib case.

v2: Set sw_ring 2 to enable software ring by default.
v3: Remove the parameter for software ring enablement.
v4: Use amdgpu_ring_init/fini for software rings.
v5: Update for code format. Fix conflict.
v6: Remove unnecessary checks and enable software ring on gfx9 by default.
v7: Use static array for software ring names and priorities.

Acked-by: Luben Tuikov 
Cc: Christian Koenig 
Cc: Luben Tuikov 
Cc: Andrey Grodzovsky 
Cc: Michel Dänzer 
Signed-off-by: Jiadong.Zhu 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h  |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h |   1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c |  20 
 drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h |   2 +
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 104 ++-
 5 files changed, 127 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 9996dadb39f7..4fdfc3ec134a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -348,6 +348,7 @@ struct amdgpu_gfx {
 
boolis_poweron;
 
+   struct amdgpu_ring  sw_gfx_ring[AMDGPU_MAX_SW_GFX_RINGS];
struct amdgpu_ring_mux  muxer;
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 40b1277b4f0c..f08ee1ac281c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -39,6 +39,7 @@ struct amdgpu_vm;
 #define AMDGPU_MAX_RINGS   28
 #define AMDGPU_MAX_HWIP_RINGS  8
 #define AMDGPU_MAX_GFX_RINGS   2
+#define AMDGPU_MAX_SW_GFX_RINGS 2
 #define AMDGPU_MAX_COMPUTE_RINGS   8
 #define AMDGPU_MAX_VCE_RINGS   3
 #define AMDGPU_MAX_UVD_ENC_RINGS   2
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
index 43cab8a37754..2e64ffccc030 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c
@@ -29,6 +29,14 @@
 
 #define AMDGPU_MUX_RESUBMIT_JIFFIES_TIMEOUT (HZ / 2)
 
+static const struct ring_info {
+   unsigned int hw_pio;
+   const char *ring_name;
+} sw_ring_info[] = {
+   { AMDGPU_RING_PRIO_DEFAULT, "gfx_low"},
+   { AMDGPU_RING_PRIO_2, "gfx_high"},
+};
+
 int amdgpu_ring_mux_init(struct amdgpu_ring_mux *mux, struct amdgpu_ring *ring,
 unsigned int entry_size)
 {
@@ -215,3 +223,15 @@ void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, 
uint32_t count)  {
WARN_ON(!ring->is_sw_ring);
 }
+
+const char *amdgpu_sw_ring_name(int idx) {
+   return idx < ARRAY_SIZE(sw_ring_info) ?
+   sw_ring_info[idx].ring_name : NULL;
+}
+
+unsigned int amdgpu_sw_ring_priority(int idx) {
+   return idx < ARRAY_SIZE(sw_ring_info) ?
+   sw_ring_info[idx].hw_pio : AMDGPU_RING_PRIO_DEFAULT; }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
index d91629589577..28399f4b0e5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.h
@@ -73,4 +73,6 @@ void amdgpu_sw_ring_insert_nop(struct amdgpu_ring *ring, 
uint32_t count);  void amdgpu_sw_ring_ib_begin(struct amdgpu_ring *ring);  void 
amdgpu_sw_ring_ib_end(struct amdgpu_ring *ring);
 
+const char *amdgpu_sw_ring_name(int idx); unsigned int 
+amdgpu_sw_ring_priority(int idx);
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 6b609f33261f..3b607c09d267 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -47,6 +47,7 @@
 
 #include "amdgpu_ras.h"
 
+#include "amdgpu_ring_mux.h"
 #include "gfx_v9_4.h"
 #include "gfx_v9_0.h"
 #include "gfx_v9_4_2.h"
@@ -56,6 +57,7 @@
 #include "asic_reg/gc/gc_9_0_default.h"
 
 #define GFX9_NUM_GFX_RINGS 1
+#define GFX9_NUM_SW_GFX_RINGS  2
 #define GFX9_MEC_HPD_SIZE 4096
 #define RLCG_UCODE_LOADING_START_ADDRESS 0x2000L  #define 
RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0xL @@ -2273,6 +2275,7 @@ static 
int gfx_v9_0_sw_init(void *handle)
struct amdgpu_ring *ring;
struct amdgpu_kiq *kiq;
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+   unsigned

RE: [PATCH] drm/amdgpu: Fix SDMA engine resume issue under SRIOV

2022-10-07 Thread Zhang, Bokun 
[AMD Official Use Only - General]

Tested-by: Bokun, Zhang 

This patch is better since it extracted the unset code and only execute it in 
the SRIOV routine.
I have tested it with multi-VF.

Thanks!


-Original Message-
From: Alex Deucher  
Sent: Thursday, October 6, 2022 3:56 PM
To: Zhang, Bokun 
Cc: Liu, Monk ; Deucher, Alexander 
; Deng, Emily ; Koenig, 
Christian ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amdgpu: Fix SDMA engine resume issue under SRIOV

On Thu, Oct 6, 2022 at 2:11 PM Zhang, Bokun  wrote:
>
> [AMD Official Use Only - General]
>
> Hey guys,
> Please help review this patch for the suspend and resume issue.
> I have tested it with multi-VF environment, I think it is ok.

Seems a little hacky, but I think that's the least intrusive for stable.  How 
about the attached patches?

Alex


>
> Thanks!
>
> -Original Message-
> From: Bokun Zhang 
> Sent: Thursday, October 6, 2022 2:09 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhang, Bokun 
> Subject: [PATCH] drm/amdgpu: Fix SDMA engine resume issue under SRIOV
>
> - Under SRIOV, SDMA engine is shared between VFs. Therefore,
>   we will not stop SDMA during hw_fini. This is not an issue
>   with normal dirver loading and unloading.
>
> - However, when we put the SDMA engine to suspend state and resume
>   it, the issue starts to show up. Something could attempt to use
>   that SDMA engine to clear or move memory before the engine is
>   initialized since the DRM entity is still there.
>
> - Therefore, we will call sdma_v5_2_enable(false) during hw_fini,
>   and if we are under SRIOV, we will call sdma_v5_2_enable(true)
>   afterwards to allow other VFs to use SDMA. This way, the DRM
>   entity of SDMA engine is emptied and it will follow the flow
>   of resume code path.
>
> Signed-off-by: Bokun Zhang 
> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 13 ++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c 
> b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index f136fec7b4f4..3eaf1a573e73 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -1357,12 +1357,19 @@ static int sdma_v5_2_hw_fini(void *handle)  {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
>
> -   if (amdgpu_sriov_vf(adev))
> -   return 0;
> -
> +   /*
> +* Under SRIOV, the VF cannot single-mindedly stop SDMA engine
> +* However, we still need to clean up the DRM entity
> +* Therefore, we will re-enable SDMA afterwards.
> +*/
> sdma_v5_2_ctx_switch_enable(adev, false);
> sdma_v5_2_enable(adev, false);
>
> +   if (amdgpu_sriov_vf(adev)) {
> +   sdma_v5_2_enable(adev, true);
> +   sdma_v5_2_ctx_switch_enable(adev, true);
> +   }
> +
> return 0;
>  }
>
> --
> 2.34.1

[linux-next:master] BUILD REGRESSION 082fce125e57cff60687181c97f3a8ee620c38f5

2022-10-07 Thread kernel test robot 
tree/branch: 
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 082fce125e57cff60687181c97f3a8ee620c38f5  Add linux-next specific 
files for 20221007

Error/Warning reports:

https://lore.kernel.org/linux-doc/202209201326.sy9kholm-...@intel.com
https://lore.kernel.org/linux-doc/202209231933.vcyettul-...@intel.com
https://lore.kernel.org/linux-doc/202210070057.npbamyxb-...@intel.com
https://lore.kernel.org/llvm/202209220019.yr2vuxhg-...@intel.com

Error/Warning: (recently discovered and may have been fixed)

ERROR: modpost: "devm_ioremap_resource" [drivers/dma/fsl-edma.ko] undefined!
ERROR: modpost: "devm_ioremap_resource" [drivers/dma/idma64.ko] undefined!
ERROR: modpost: "devm_ioremap_resource" [drivers/dma/qcom/hdma.ko] undefined!
ERROR: modpost: "devm_memremap" [drivers/misc/open-dice.ko] undefined!
ERROR: modpost: "devm_memunmap" [drivers/misc/open-dice.ko] undefined!
ERROR: modpost: "devm_platform_ioremap_resource" 
[drivers/char/xillybus/xillybus_of.ko] undefined!
ERROR: modpost: "ioremap" [drivers/net/ethernet/8390/pcnet_cs.ko] undefined!
ERROR: modpost: "ioremap" [drivers/tty/ipwireless/ipwireless.ko] undefined!
ERROR: modpost: "iounmap" [drivers/net/ethernet/8390/pcnet_cs.ko] undefined!
ERROR: modpost: "iounmap" [drivers/tty/ipwireless/ipwireless.ko] undefined!
Warning: Documentation/translations/zh_CN/devicetree/kernel-api.rst references 
a file that doesn't exist: Documentation/Devicetree/kernel-api.rst
Warning: MAINTAINERS references a file that doesn't exist: 
Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
Warning: MAINTAINERS references a file that doesn't exist: 
Documentation/devicetree/bindings/mtd/amlogic,meson-nand.txt
arch/arm64/kernel/alternative.c:199:6: warning: no previous prototype for 
'apply_alternatives_vdso' [-Wmissing-prototypes]
arch/arm64/kernel/alternative.c:295:14: warning: no previous prototype for 
'alt_cb_patch_nops' [-Wmissing-prototypes]
arch/loongarch/mm/init.c:166:24: warning: variable 'new' set but not used 
[-Wunused-but-set-variable]
drivers/gpu/drm/amd/amdgpu/../display/dc/virtual/virtual_link_hwss.c:40:6: 
warning: no previous prototype for 'virtual_disable_link_output' 
[-Wmissing-prototypes]
drivers/iio/adc/mcp3911.c:252 mcp3911_write_raw() error: buffer overflow 
'mcp3911_osr_table' 8 <= 31
drivers/iio/adc/mcp3911.c:441 mcp3911_probe() warn: passing zero to 'PTR_ERR'
drivers/iio/adc/mcp3911.c:499 mcp3911_probe() warn: passing zero to 'PTR_ERR'
drivers/nvme/target/loop.c:578 nvme_loop_create_ctrl() warn: 'opts->queue_size 
- 1' 4294967295 can't fit into 65535 'ctrl->ctrl.sqsize'
fs/ext4/super.c:1744:19: warning: 'deprecated_msg' defined but not used 
[-Wunused-const-variable=]
pahole: .tmp_vmlinux.btf: No such file or directory

Error/Warning ids grouped by kconfigs:

gcc_recent_errors
|-- alpha-allyesconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-virtual-virtual_link_hwss.c:warning:no-previous-prototype-for-virtual_disable_link_output
|-- alpha-buildonly-randconfig-r003-20221003
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-virtual-virtual_link_hwss.c:warning:no-previous-prototype-for-virtual_disable_link_output
|-- arc-allyesconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-virtual-virtual_link_hwss.c:warning:no-previous-prototype-for-virtual_disable_link_output
|-- arm-allyesconfig
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-virtual-virtual_link_hwss.c:warning:no-previous-prototype-for-virtual_disable_link_output
|-- arm64-allyesconfig
|   |-- 
arch-arm64-kernel-alternative.c:warning:no-previous-prototype-for-alt_cb_patch_nops
|   |-- 
arch-arm64-kernel-alternative.c:warning:no-previous-prototype-for-apply_alternatives_vdso
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-virtual-virtual_link_hwss.c:warning:no-previous-prototype-for-virtual_disable_link_output
|-- arm64-randconfig-r004-20221002
|   |-- 
arch-arm64-kernel-alternative.c:warning:no-previous-prototype-for-alt_cb_patch_nops
|   |-- 
arch-arm64-kernel-alternative.c:warning:no-previous-prototype-for-apply_alternatives_vdso
|   `-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-virtual-virtual_link_hwss.c:warning:no-previous-prototype-for-virtual_disable_link_output
|-- arm64-randconfig-r014-20221003
|   |-- 
arch-arm64-kernel-alternative.c:warning:no-previous-prototype-for-alt_cb_patch_nops
|   `-- 
arch-arm64-kernel-alternative.c:warning:no-previous-prototype-for-apply_alternatives_vdso
|-- csky-randconfig-m041-20221002
|   |-- drivers-iio-adc-mcp3911.c-mcp3911_probe()-warn:passing-zero-to-PTR_ERR
|   |-- 
drivers-iio-adc-mcp3911.c-mcp3911_write_raw()-error:buffer-overflow-mcp3911_osr_table
|   `-- 
drivers-nvme-target-loop.c-nvme_loop_create_ctrl()-warn:opts-queue_size-can-t-fit-into-ctrl-ctrl.sqsize
|-- i386-allyesconfig
|   |-- 
drivers-gpu-drm-amd-amdgpu-..-display-dc-virtual-virtual_link_hwss.c:warning

Re: [20/23] drm/amd/display: Fix watermark calculation

2022-10-07 Thread Limonciello, Mario 

On 10/6/2022 16:26, Qingqing Zhuo wrote:

From: Alvin Lee 

Watermark calculation was incorrect
due to missing brackets.

Reviewed-by: Rodrigo Siqueira 
Acked-by: Qingqing Zhuo 
Signed-off-by: Alvin Lee 


This just landed upstream for 6.0 and is a trivial fix for what the 
intention was, it should go 6.0.y too.


Cc: sta...@vger.kernel.org # 6.0
Fixes: 85f4bc0c333c ("drm/amd/display: Add SubVP required code")


---
  drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c 
b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index bbde635c56fc..0541e87e4f38 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -781,7 +781,7 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc,
// Store the original watermark value for this SubVP config so 
we can lower it when the
// MCLK switch starts
wm_val_refclk = 
context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns *
-   dc->res_pool->ref_clocks.dchub_ref_clock_inKhz 
/ 1000 / 1000;
+   (dc->res_pool->ref_clocks.dchub_ref_clock_inKhz 
/ 1000) / 1000;
  
  		cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0x ? wm_val_refclk : 0x;

}

Re: [01/23] drm/amd/display: Update PMFW z-state interface for DCN314

2022-10-07 Thread Limonciello, Mario 

On 10/6/2022 16:26, Qingqing Zhuo wrote:

From: Nicholas Kazlauskas 

[Why]
Request from PMFW to change the messaging format to specify whether we
support z-state via individual bits.

[How]
Update the args we pass in the support message.

Reviewed-by: Charlene Liu 
Acked-by: Qingqing Zhuo 
Signed-off-by: Nicholas Kazlauskas 


I'm aware this isn't strictly a fix, but as the firmware interface is 
changing I think we also want this to come back to 6.0.y too as products 
with DCN314 will be enabled with 6.0 and we want to make sure the 
messaging to the PMFW is correct as we enable different power management 
scenarios.


Cc: sta...@vger.kernel.org # 6.0
Fixes: d5c6909e7460 ("drm/amd/display: Add DCN314 clock manager")
Reviewed-by: Mario Limonciello 


---
  .../drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c| 11 +++
  .../gpu/drm/amd/display/dc/dcn314/dcn314_resource.c   |  3 ++-
  2 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c 
b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
index 897105d1c111..ef0795b14a1f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_smu.c
@@ -339,29 +339,24 @@ void dcn314_smu_set_zstate_support(struct 
clk_mgr_internal *clk_mgr, enum dcn_zs
if (!clk_mgr->smu_present)
return;
  
-	if (!clk_mgr->base.ctx->dc->debug.enable_z9_disable_interface &&

-   (support == DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY))
-   support = DCN_ZSTATE_SUPPORT_DISALLOW;
-
-
// Arg[15:0] = 8/9/0 for Z8/Z9/disallow -> existing bits
// Arg[16] = Disallow Z9 -> new bit
switch (support) {
  
  	case DCN_ZSTATE_SUPPORT_ALLOW:

msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
-   param = 9;
+   param = (1 << 10) | (1 << 9) | (1 << 8);
break;
  
  	case DCN_ZSTATE_SUPPORT_DISALLOW:

msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
-   param = 8;
+   param = 0;
break;
  
  
  	case DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY:

msg_id = VBIOSSMC_MSG_AllowZstatesEntry;
-   param = 0x00010008;
+   param = (1 << 10);
break;
  
  	default: //DCN_ZSTATE_SUPPORT_UNKNOWN

diff --git a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
index 70b647b9b4d3..d0ad72caead2 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn314/dcn314_resource.c
@@ -881,7 +881,8 @@ static const struct dc_plane_cap plane_cap = {
  };
  
  static const struct dc_debug_options debug_defaults_drv = {

-   .disable_z10 = true, /*hw not support it*/
+   .disable_z10 = false,
+   .enable_z9_disable_interface = true,
.disable_dmcu = true,
.force_abm_enable = false,
.timing_trace = false,

Re: mainline build failure due to 5d8c3e836fc2 ("drm/amd/display: fix array-bounds error in dc_stream_remove_writeback()")

2022-10-07 Thread Linus Torvalds 
On Thu, Oct 6, 2022 at 1:50 PM Sudip Mukherjee
 wrote:
>
> > And it looks like Sudip's proposed fix for this particular code is
> > additionally fixing unsigned vs signed as well. I think -Warray-bounds
> > did its job (though, with quite a confusing index range in the report).
>
> Not my. Linus's. I just tested. :)

I suspect Kees meant Stephen's other patch that Hamza pointed at, and
that is perhaps the cleaner version.

That said, I hate how this forces us to write random code changes just
to make a compiler just randomly _happen_ to not complain about it.

   Linus

Re: drm/amd/display: explicitly disable psr_feature_enable appropriately

2022-10-07 Thread Limonciello, Mario 

On 10/6/2022 23:28, Shirish S wrote:

[Why]
If psr_feature_enable is set to true by default, it continues to be enabled
for non capable links.

[How]
explicitly disable the feature on links that are not capable of the same.

Signed-off-by: Shirish S 
Reviewed-by: Leo Li 


This has been a problem potentially all the way to when PSR was first added.

I think this should probably go back to stable.  The commit that last 
touched it (f4594cd1fa556) was in 5.13, but this could at least be fixed 
in the 5.15 LTS kernel and newer.


Cc: sta...@vger.kernel.org # 5.15+
Fixes: 8c322309e48e9 ("drm/amd/display: Enable PSR")
Reviewed-by: Mario Limonciello 


---
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 8 ++--
  1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index 8ca10ab3dfc1..26291db0a3cf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -60,11 +60,15 @@ static bool link_supports_psrsu(struct dc_link *link)
   */
  void amdgpu_dm_set_psr_caps(struct dc_link *link)
  {
-   if (!(link->connector_signal & SIGNAL_TYPE_EDP))
+   if (!(link->connector_signal & SIGNAL_TYPE_EDP)) {
+   link->psr_settings.psr_feature_enabled = false;
return;
+   }
  
-	if (link->type == dc_connection_none)

+   if (link->type == dc_connection_none) {
+   link->psr_settings.psr_feature_enabled = false;
return;
+   }
  
  	if (link->dpcd_caps.psr_info.psr_version == 0) {

link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;

Re: [PATCH] drm/amd/display: explicitly disable psr_feature_enable appropriately

2022-10-07 Thread Leo Li 




On 2022-10-07 00:28, Shirish S wrote:

[Why]
If psr_feature_enable is set to true by default, it continues to be enabled
for non capable links.

[How]
explicitly disable the feature on links that are not capable of the same.

Signed-off-by: Shirish S 

Reviewed-by: Leo Li 

Thanks!

---
  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c | 8 ++--
  1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index 8ca10ab3dfc1..26291db0a3cf 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -60,11 +60,15 @@ static bool link_supports_psrsu(struct dc_link *link)
   */
  void amdgpu_dm_set_psr_caps(struct dc_link *link)
  {
-   if (!(link->connector_signal & SIGNAL_TYPE_EDP))
+   if (!(link->connector_signal & SIGNAL_TYPE_EDP)) {
+   link->psr_settings.psr_feature_enabled = false;
return;
+   }
  
-	if (link->type == dc_connection_none)

+   if (link->type == dc_connection_none) {
+   link->psr_settings.psr_feature_enabled = false;
return;
+   }
  
  	if (link->dpcd_caps.psr_info.psr_version == 0) {

link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;