RE: [PATCH] drm/amdgpu: program device_cntl2 through pci cfg space

[Feng, Kenneth]

[AMD Official Use Only - AMD Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Min, Frank 
Sent: Tuesday, May 21, 2024 1:24 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Gao, Likun ; 
Feng, Kenneth 
Subject: FW: [PATCH] drm/amdgpu: program device_cntl2 through pci cfg space

[AMD Official Use Only - AMD Internal Distribution Only]

From: Frank Min 

device_cntl2 is accessible from pci config space, so program it through pci cfg 
space instead of mmio.

Signed-off-by: Frank Min 
---
 drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c 
b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
index fe64c04ee20b..5a20bb229788 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c
@@ -315,6 +315,7 @@ static u32 nbif_v6_3_1_get_rom_offset(struct amdgpu_device 
*adev)  static void nbif_v6_3_1_program_ltr(struct amdgpu_device *adev)  {
uint32_t def, data;
+   u16 devctl2;

def = RREG32_SOC15(NBIO, 0, regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
data = 0x35EB;
@@ -328,13 +329,15 @@ static void nbif_v6_3_1_program_ltr(struct amdgpu_device 
*adev)
if (def != data)
WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data);

-   def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
+   pcie_capability_read_word(adev->pdev, PCI_EXP_DEVCTL2,
+ );
+
+   if (adev->pdev->ltr_path == (devctl2 & PCI_EXP_DEVCTL2_LTR_EN))
+   return;
+
if (adev->pdev->ltr_path)
-   data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
+   pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2,
+PCI_EXP_DEVCTL2_LTR_EN);
else
-   data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
-   if (def != data)
-   WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
+   pcie_capability_clear_word(adev->pdev, PCI_EXP_DEVCTL2,
+PCI_EXP_DEVCTL2_LTR_EN);
 }
 #endif

--
2.34.1

RE: [PATCH 2/2] drm/amd/amdgpu: use the default reset for ras recovery

[Feng, Kenneth]

[AMD Official Use Only - General]

+@Zhang, GuoQing (Sam)

-Original Message-
From: Kenneth Feng 
Sent: Monday, April 29, 2024 3:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Owen(SRDC) ; Aldabagh, Maad 
; Ma, Qing (Mark) ; Feng, Kenneth 

Subject: [PATCH 2/2] drm/amd/amdgpu: use the default reset for ras recovery

use the default reset for ras recovery

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index a037e8fba29f..f92b2c4f0d5c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -2437,6 +2437,7 @@ static void amdgpu_ras_do_recovery(struct work_struct 
*work)
struct amdgpu_device *adev = ras->adev;
struct list_head device_list, *device_list_handle =  NULL;
struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev);
+   int save_reset_method = amdgpu_reset_method;

if (hive) {
atomic_set(>ras_recovery, 1);
@@ -2501,7 +2502,13 @@ static void amdgpu_ras_do_recovery(struct work_struct 
*work)
}
}

+   if (amdgpu_gpu_recovery == 2)
+   amdgpu_reset_method = -1;
+
amdgpu_device_gpu_recover(ras->adev, NULL, _context);
+
+   if (amdgpu_gpu_recovery == 2)
+   amdgpu_reset_method = save_reset_method;
}
atomic_set(>in_recovery, 0);
if (hive) {
--
2.34.1

RE: [PATCH 1/2] drm/amd/amdgpu: customized the reset to skip soft recovery

[Feng, Kenneth]

[AMD Official Use Only - General]

+@Zhang, GuoQing (Sam)

-Original Message-
From: Kenneth Feng 
Sent: Monday, April 29, 2024 3:32 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Owen(SRDC) ; Aldabagh, Maad 
; Ma, Qing (Mark) ; Feng, Kenneth 

Subject: [PATCH 1/2] drm/amd/amdgpu: customized the reset to skip soft recovery

customized the reset to skip soft recovery

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-  
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index ea14f1c8f430..65c3a387fec7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -548,7 +548,7 @@ module_param_named(compute_multipipe, 
amdgpu_compute_multipipe, int, 0444);
  * DOC: gpu_recovery (int)
  * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default 
is -1 (auto, disabled except SRIOV).
  */
-MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 
= disable, -1 = auto)");
+MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 =
+enable, 0 = disable, -1 = auto, 2 = customized)");
 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);

 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index e4742b65032d..5c75993698a5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -51,7 +51,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct 
drm_sched_job *s_job)

adev->job_hang = true;

-   if (amdgpu_gpu_recovery &&
+   if (amdgpu_gpu_recovery && amdgpu_gpu_recovery != 2 &&
amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) 
{
DRM_ERROR("ring %s timeout, but soft recovered\n",
  s_job->sched->name);
--
2.34.1

RE: [PATCH] drm/amdgpu: Process bif doorbell event

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Zhang, Hawking 
Sent: Monday, April 1, 2024 7:15 PM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Feng, Kenneth ; Xiao, Jack 

Cc: Zhang, Hawking 
Subject: [PATCH] drm/amdgpu: Process bif doorbell event

When BACO exit is triggered by doorbell transaction, firmware will config bif 
to issue msi interrupt to indicate doorbell transaction. If bif ring is not 
enabled in such case, driver needs to ack the interrupt by clearing the 
interrupt status.

Signed-off-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h |  2 +
 drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c   | 56 
 drivers/gpu/drm/amd/amdgpu/soc21.c   | 14 +-
 3 files changed, 71 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
index 7b8c03be1d9e..db341921cfc1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
@@ -102,6 +102,7 @@ struct amdgpu_nbio_funcs {
u32 (*get_memory_partition_mode)(struct amdgpu_device *adev,
 u32 *supp_modes);
u64 (*get_pcie_replay_count)(struct amdgpu_device *adev);
+   u32 (*init_bif_doorbell_event)(struct amdgpu_device *adev);
 };

 struct amdgpu_nbio {
@@ -111,6 +112,7 @@ struct amdgpu_nbio {
struct ras_common_if *ras_if;
const struct amdgpu_nbio_funcs *funcs;
struct amdgpu_nbio_ras  *ras;
+   struct amdgpu_irq_src bif_doorbell_irq;
 };

 int amdgpu_nbio_ras_sw_init(struct amdgpu_device *adev); diff --git 
a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c 
b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
index 7f88a298ac5f..e5a331b6eee9 100644
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
@@ -477,6 +477,61 @@ static void nbio_v4_3_program_aspm(struct amdgpu_device 
*adev)  #endif  }

+static int nbio_v4_3_set_bif_doorbell_irq_state(struct amdgpu_device *adev,
+   struct amdgpu_irq_src *src,
+   unsigned type,
+   enum amdgpu_interrupt_state 
state) {
+/*let firmware to config bif doorbell irq state */
+return 0;
+}
+
+static int nbio_v4_3_process_bif_doorbell_irq(struct amdgpu_device *adev,
+ struct amdgpu_irq_src *source,
+ struct amdgpu_iv_entry *entry) {
+   /* pmfw will config bif doorbell irq to host if baco exit
+* is triggered by doorbell transaction. In such case, driver
+* needs to clear the interrupt status */
+
+   uint32_t reg_data;
+
+   reg_data = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_RB_CNTL);
+
+   /* if bif ring is enabled, do nothing */
+   if (REG_GET_FIELD(reg_data, BIF_BX0_BIF_RB_CNTL, RB_ENABLE))
+   return 0;
+
+   /* write 1 to clear doorbell interrupt */
+   reg_data = RREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL);
+   if (REG_GET_FIELD(reg_data, BIF_BX0_BIF_DOORBELL_INT_CNTL, 
DOORBELL_INTERRUPT_STATUS)) {
+   reg_data = REG_SET_FIELD(reg_data,
+BIF_BX0_BIF_DOORBELL_INT_CNTL,
+DOORBELL_INTERRUPT_CLEAR, 1);
+   WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_DOORBELL_INT_CNTL, 
reg_data);
+   }
+
+   return 0;
+}
+
+static const struct amdgpu_irq_src_funcs nbio_v4_3_bif_doorbell_irq_funcs = {
+   .set = nbio_v4_3_set_bif_doorbell_irq_state,
+   .process = nbio_v4_3_process_bif_doorbell_irq,
+};
+
+static u32 nbio_v4_3_init_bif_doorbell_event(struct amdgpu_device
+*adev) {
+   u32 r;
+
+   adev->nbio.bif_doorbell_irq.funcs = _v4_3_bif_doorbell_irq_funcs;
+   adev->nbio.bif_doorbell_irq.num_types = 1;
+
+   r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_BIF,
+ NBIF_7_4__SRCID__DOORBELL_INTERRUPT,
+ >nbio.bif_doorbell_irq);
+   return r;
+}
+
 const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {
.get_hdp_flush_req_offset = nbio_v4_3_get_hdp_flush_req_offset,
.get_hdp_flush_done_offset = nbio_v4_3_get_hdp_flush_done_offset,
@@ -499,6 +554,7 @@ const struct amdgpu_nbio_funcs nbio_v4_3_funcs = {
.remap_hdp_registers = nbio_v4_3_remap_hdp_registers,
.get_rom_offset = nbio_v4_3_get_rom_offset,
.program_aspm = nbio_v4_3_program_aspm,
+   .init_bif_doorbell_event = nbio_v4_3_init_bif_doorbell_event,
 };


diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c 
b/drivers/gpu/drm/amd/amdgpu/soc21.c
index abe319b0f063..ee6d810589c0 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -792,6 +792,9 @@ static int soc21_common_late_init(voi

RE: [PATCH] drm/amd/pm: centralize all pp_dpm_xxx attribute nodes update cb

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Wang, Yang(Kevin) 
Sent: Monday, April 1, 2024 8:39 AM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Lazar, Lijo ; 
Wang, Yang(Kevin) 
Subject: [PATCH] drm/amd/pm: centralize all pp_dpm_xxx attribute nodes update cb

centralize all pp_dpm_xxx attr nodes into
pp_dpm_clk_default_attr_update() function.

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 207 -
 1 file changed, 115 insertions(+), 92 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index b410df28ccb2..5bc1cd4993e8 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -38,6 +38,8 @@
 #define MAX_NUM_OF_FEATURES_PER_SUBSET 8
 #define MAX_NUM_OF_SUBSETS 8

+#define DEVICE_ATTR_IS(_name)  (attr_id == device_attr_id__##_name)
+
 struct od_attribute {
struct kobj_attribute   attribute;
struct list_headentry;
@@ -2115,6 +2117,99 @@ static int pp_dpm_dcefclk_attr_update(struct 
amdgpu_device *adev, struct amdgpu_
return 0;
 }

+static int pp_dpm_clk_default_attr_update(struct amdgpu_device *adev, struct 
amdgpu_device_attr *attr,
+ uint32_t mask, enum 
amdgpu_device_attr_states *states) {
+   struct device_attribute *dev_attr = >dev_attr;
+   enum amdgpu_device_attr_id attr_id = attr->attr_id;
+   uint32_t mp1_ver = amdgpu_ip_version(adev, MP1_HWIP, 0);
+   uint32_t gc_ver = amdgpu_ip_version(adev, GC_HWIP, 0);
+
+   *states = ATTR_STATE_SUPPORTED;
+
+   if (!(attr->flags & mask)) {
+   *states = ATTR_STATE_UNSUPPORTED;
+   return 0;
+   }
+
+   if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
+   if (gc_ver < IP_VERSION(9, 0, 0))
+   *states = ATTR_STATE_UNSUPPORTED;
+   } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
+   if (mp1_ver < IP_VERSION(10, 0, 0))
+   *states = ATTR_STATE_UNSUPPORTED;
+   } else if (DEVICE_ATTR_IS(pp_dpm_vclk)) {
+   if (!(gc_ver == IP_VERSION(10, 3, 1) ||
+ gc_ver == IP_VERSION(10, 3, 3) ||
+ gc_ver == IP_VERSION(10, 3, 6) ||
+ gc_ver == IP_VERSION(10, 3, 7) ||
+ gc_ver == IP_VERSION(10, 3, 0) ||
+ gc_ver == IP_VERSION(10, 1, 2) ||
+ gc_ver == IP_VERSION(11, 0, 0) ||
+ gc_ver == IP_VERSION(11, 0, 1) ||
+ gc_ver == IP_VERSION(11, 0, 4) ||
+ gc_ver == IP_VERSION(11, 5, 0) ||
+ gc_ver == IP_VERSION(11, 0, 2) ||
+ gc_ver == IP_VERSION(11, 0, 3) ||
+ gc_ver == IP_VERSION(9, 4, 3)))
+   *states = ATTR_STATE_UNSUPPORTED;
+   } else if (DEVICE_ATTR_IS(pp_dpm_vclk1)) {
+   if (!((gc_ver == IP_VERSION(10, 3, 1) ||
+  gc_ver == IP_VERSION(10, 3, 0) ||
+  gc_ver == IP_VERSION(11, 0, 2) ||
+  gc_ver == IP_VERSION(11, 0, 3)) && 
adev->vcn.num_vcn_inst >= 2))
+   *states = ATTR_STATE_UNSUPPORTED;
+   } else if (DEVICE_ATTR_IS(pp_dpm_dclk)) {
+   if (!(gc_ver == IP_VERSION(10, 3, 1) ||
+ gc_ver == IP_VERSION(10, 3, 3) ||
+ gc_ver == IP_VERSION(10, 3, 6) ||
+ gc_ver == IP_VERSION(10, 3, 7) ||
+ gc_ver == IP_VERSION(10, 3, 0) ||
+ gc_ver == IP_VERSION(10, 1, 2) ||
+ gc_ver == IP_VERSION(11, 0, 0) ||
+ gc_ver == IP_VERSION(11, 0, 1) ||
+ gc_ver == IP_VERSION(11, 0, 4) ||
+ gc_ver == IP_VERSION(11, 5, 0) ||
+ gc_ver == IP_VERSION(11, 0, 2) ||
+ gc_ver == IP_VERSION(11, 0, 3) ||
+ gc_ver == IP_VERSION(9, 4, 3)))
+   *states = ATTR_STATE_UNSUPPORTED;
+   } else if (DEVICE_ATTR_IS(pp_dpm_dclk1)) {
+   if (!((gc_ver == IP_VERSION(10, 3, 1) ||
+  gc_ver == IP_VERSION(10, 3, 0) ||
+  gc_ver == IP_VERSION(11, 0, 2) ||
+  gc_ver == IP_VERSION(11, 0, 3)) && 
adev->vcn.num_vcn_inst >= 2))
+   *states = ATTR_STATE_UNSUPPORTED;
+   } else if (DEVICE_ATTR_IS(pp_dpm_pcie)) {
+   if (gc_ver == IP_VERSION(9, 4, 2) ||
+   gc_ver == IP_VERSION(9, 4, 3))
+   *states = ATTR_STATE_UNSUPPORTED;
+   }
+
+   switch (gc_ver) {
+   case IP_VERSION(9, 4, 1):
+   case IP_VERSION(9, 4, 2):
+   /* the Mi series card does not support standalone 
mclk/socclk/fclk leve

RE: [PATCH] drm/amdgpu: Bypass asd if display hw is not available

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Hawking Zhang 
Sent: Sunday, March 31, 2024 1:02 PM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Feng, Kenneth 
Cc: Zhang, Hawking 
Subject: [PATCH] drm/amdgpu: Bypass asd if display hw is not available

ASD is not needed by headless GPU.

Signed-off-by: Hawking Zhang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 94b310fdb719d..83bf86352267d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1053,6 +1053,11 @@ static int psp_asd_initialize(struct psp_context *psp)
if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
return 0;

+   /* bypass asd if display hardware is not available */
+   if (!amdgpu_device_has_display_hardware(psp->adev) &&
+   amdgpu_ip_version(psp->adev, MP0_HWIP, 0) >= IP_VERSION(13, 0, 10))
+   return 0;
+
psp->asd_context.mem_context.shared_mc_addr  = 0;
psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
psp->asd_context.ta_load_type= GFX_CMD_ID_LOAD_ASD;
--
2.17.1

RE: [PATCH v2] drm/amd/pm: enable amdgpu smu send message log

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Yang Wang
Sent: Thursday, January 18, 2024 1:37 PM
To: amd-gfx@lists.freedesktop.org
Cc: Lazar, Lijo ; Feng, Kenneth ; 
Wang, Yang(Kevin) 
Subject: [PATCH v2] drm/amd/pm: enable amdgpu smu send message log

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


From: Yang Wang 

v1:
enable amdgpu smu driver message log.

v2:
add smu/pmfw response value into debug log.

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 00cd615bbcdc..b8dbd4e25348 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -378,8 +378,15 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context 
*smu,
res = __smu_cmn_reg2errno(smu, reg);
if (res != 0)
__smu_cmn_reg_print_error(smu, reg, index, param, msg);
-   if (read_arg)
+   if (read_arg) {
smu_cmn_read_arg(smu, read_arg);
+   dev_dbg(adev->dev, "smu send message: %s(%d) param: 0x%08x, 
resp: 0x%08x,\
+   readval: 0x%08x\n",
+   smu_get_message_name(smu, msg), index, param, reg, 
*read_arg);
+   } else {
+   dev_dbg(adev->dev, "smu send message: %s(%d) param: 0x%08x, 
resp: 0x%08x\n",
+   smu_get_message_name(smu, msg), index, param, reg);
+   }
 Out:
if (unlikely(adev->pm.smu_debug_mask & SMU_DEBUG_HALT_ON_ERROR) && res) 
{
amdgpu_device_halt(adev);
--
2.34.1

RE: [PATCH v2] drm/amd/swsmu: remove duplicate definition of smu v14_0_0 driver if version

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Ma, Li 
Sent: Friday, December 15, 2023 11:44 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Feng, Kenneth 
; Zhang, Yifan ; Yu, Lang 
; Ma, Li 
Subject: [PATCH v2] drm/amd/swsmu: remove duplicate definition of smu v14_0_0 
driver if version

There is a repeated define of smu v14_0_0 driver if version, so delete one in 
driver if header.

Signed-off-by: Li Ma 
---
 .../drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h   | 5 -
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h | 2 +-
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h
index 8f42771e1f0a..5bb7a63c0602 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0_0.h
@@ -24,11 +24,6 @@
 #ifndef SMU14_DRIVER_IF_V14_0_0_H
 #define SMU14_DRIVER_IF_V14_0_0_H

-// *** IMPORTANT ***
-// SMU TEAM: Always increment the interface version if -// any structure is 
changed in this file -#define PMFW_DRIVER_IF_VERSION 7
-
 typedef struct {
   int32_t value;
   uint32_t numFractionalBits;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
index a5b569976f19..3f7463c1c1a9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h
@@ -26,8 +26,8 @@
 #include "amdgpu_smu.h"

 #define SMU14_DRIVER_IF_VERSION_INV 0x
+#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_0 0x7
 #define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 0x1 -#define 
SMU14_DRIVER_IF_VERSION_SMU_V14_0_0 0x6

 #define FEATURE_MASK(feature) (1ULL << feature)

--
2.25.1

RE: [PATCH] drm/amdgpu: correct the amdgpu runtime dereference usage count

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Liang, Prike
Sent: Friday, November 17, 2023 9:37 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Li, Sun peng (Leo) 
; Wentland, Harry 
Subject: RE: [PATCH] drm/amdgpu: correct the amdgpu runtime dereference usage 
count

[AMD Official Use Only - General]

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


[AMD Official Use Only - General]

Ping for the review.

Regards,
--Prike

> -Original Message-
> From: Liang, Prike 
> Sent: Tuesday, November 14, 2023 10:41 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Liang, Prike
> 
> Subject: [PATCH] drm/amdgpu: correct the amdgpu runtime dereference
> usage count
>
> Fix the amdgpu runpm dereference usage count.
>
> Signed-off-by: Prike Liang 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> index 0cacd0b9f8be..4737ada467cc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> @@ -340,12 +340,12 @@ int amdgpu_display_crtc_set_config(struct
> drm_mode_set *set,
>   adev->have_disp_power_ref = true;
>   return ret;
>   }
> - /* if we have no active crtcs, then drop the power ref
> -  * we got before
> + /* if we have no active crtcs, then go to
> +  * drop the power ref we got before
>*/
>   if (!active && adev->have_disp_power_ref) {
> - pm_runtime_put_autosuspend(dev->dev);
>   adev->have_disp_power_ref = false;
> + goto out;
>   }
>
>  out:
> --
> 2.34.1

RE: [PATCH] drm/amd/pm:Fix return vlaue and drop redundant param

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Ma, Jun 
Sent: Thursday, November 2, 2023 3:59 PM
To: amd-gfx@lists.freedesktop.org; Feng, Kenneth ; 
Deucher, Alexander 
Cc: Ma, Jun 
Subject: [PATCH] drm/amd/pm:Fix return vlaue and drop redundant param

Fix the return value and drop redundant parameter of get_asic_baco_capability 
function to simplify the code

Signed-off-by: Ma Jun 
---
 drivers/gpu/drm/amd/include/kgd_pp_interface.h   |  2 +-
 drivers/gpu/drm/amd/pm/amdgpu_dpm.c  |  8 +++-
 drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 11 ---
 drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c   |  7 +++
 drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.h   |  2 +-
 drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.c   |  9 -
 drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu9_baco.h   |  2 +-
 drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.c |  9 -  
drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_baco.h |  2 +-
 drivers/gpu/drm/amd/pm/powerplay/inc/hwmgr.h |  2 +-
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c| 12 +---
 11 files changed, 28 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h 
b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 3201808c2dd8..60e6b82077e8 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -421,7 +421,7 @@ struct amd_pm_funcs {
int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
-   int (*get_asic_baco_capability)(void *handle, bool *cap);
+   bool (*get_asic_baco_capability)(void *handle);
int (*get_asic_baco_state)(void *handle, int *state);
int (*set_asic_baco_state)(void *handle, int state);
int (*get_ppfeature_status)(void *handle, char *buf); diff --git 
a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
index acf3527fff2d..24fd036a15c0 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c
@@ -185,8 +185,7 @@ bool amdgpu_dpm_is_baco_supported(struct amdgpu_device 
*adev)  {
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
void *pp_handle = adev->powerplay.pp_handle;
-   bool baco_cap;
-   int ret = 0;
+   bool ret;

if (!pp_funcs || !pp_funcs->get_asic_baco_capability)
return false;
@@ -204,12 +203,11 @@ bool amdgpu_dpm_is_baco_supported(struct amdgpu_device 
*adev)

mutex_lock(>pm.mutex);

-   ret = pp_funcs->get_asic_baco_capability(pp_handle,
-_cap);
+   ret = pp_funcs->get_asic_baco_capability(pp_handle);

mutex_unlock(>pm.mutex);

-   return ret ? false : baco_cap;
+   return ret;
 }

 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev) diff --git 
a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index 9e4f8a4104a3..e82c2b2fffb5 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -1368,21 +1368,18 @@ static int pp_set_active_display_count(void *handle, 
uint32_t count)
return phm_set_active_display_count(hwmgr, count);  }

-static int pp_get_asic_baco_capability(void *handle, bool *cap)
+static bool pp_get_asic_baco_capability(void *handle)
 {
struct pp_hwmgr *hwmgr = handle;

-   *cap = false;
if (!hwmgr)
-   return -EINVAL;
+   return false;

if (!(hwmgr->not_vf && amdgpu_dpm) ||
!hwmgr->hwmgr_func->get_asic_baco_capability)
-   return 0;
+   return false;

-   hwmgr->hwmgr_func->get_asic_baco_capability(hwmgr, cap);
-
-   return 0;
+   return hwmgr->hwmgr_func->get_asic_baco_capability(hwmgr);
 }

 static int pp_get_asic_baco_state(void *handle, int *state) diff --git 
a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c
index 044cda005aed..e8a9471c1898 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_baco.c
@@ -33,21 +33,20 @@
 #include "smu/smu_7_1_2_d.h"
 #include "smu/smu_7_1_2_sh_mask.h"

-int smu7_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)
+bool smu7_baco_get_capability(struct pp_hwmgr *hwmgr)
 {
struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
uint32_t reg;

-   *cap = false;
if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, 
PHM_PlatformCaps_BACO))
return 0;

reg = RREG32(mmCC_BIF_BX_FUS

RE: [PATCH v2 1/2] drm/amdgpu: Optimize the asic type fix code

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Ma, Jun 
Sent: Thursday, November 2, 2023 8:58 AM
To: Ma, Jun ; amd-gfx@lists.freedesktop.org; Feng, Kenneth 
; Deucher, Alexander 
Cc: Ma, Jun 
Subject: Re: [PATCH v2 1/2] drm/amdgpu: Optimize the asic type fix code

ping...

Regards,
Ma Jun

On 11/1/2023 11:04 AM, Ma Jun wrote:
> Use a new struct array to define the asic information which asic type
> needs to be fixed.
>
> Signed-off-by: Ma Jun 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 35 ++---
>  include/drm/amd_asic_type.h |  5 
>  2 files changed, 31 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 84703e0a73bd..756cf49557a2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -2067,6 +2067,14 @@ static const struct pci_device_id pciidlist[] =
> {
>
>  MODULE_DEVICE_TABLE(pci, pciidlist);
>
> +static const struct amdgpu_asic_type_quirk asic_type_quirks[] = {
> + /* differentiate between P10 and P11 asics with the same DID */
> + {0x67FF, 0xE3, CHIP_POLARIS10},
> + {0x67FF, 0xE7, CHIP_POLARIS10},
> + {0x67FF, 0xF3, CHIP_POLARIS10},
> + {0x67FF, 0xF7, CHIP_POLARIS10},
> +};
> +
>  static struct drm_driver amdgpu_kms_driver;
>
>  static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) @@
> -2109,6 +2117,22 @@ static void amdgpu_init_debug_options(struct 
> amdgpu_device *adev)
>   }
>  }
>
> +static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev,
> +unsigned long flags) {
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(asic_type_quirks); i++) {
> + if (pdev->device == asic_type_quirks[i].device &&
> + pdev->revision == asic_type_quirks[i].revision) {
> + flags &= ~AMD_ASIC_MASK;
> + flags |= asic_type_quirks[i].type;
> + break;
> + }
> + }
> +
> + return flags;
> +}
> +
>  static int amdgpu_pci_probe(struct pci_dev *pdev,
>   const struct pci_device_id *ent)  { @@ -2138,15 
> +2162,8 @@
> static int amdgpu_pci_probe(struct pci_dev *pdev,
>"See modparam exp_hw_support\n");
>   return -ENODEV;
>   }
> - /* differentiate between P10 and P11 asics with the same DID */
> - if (pdev->device == 0x67FF &&
> - (pdev->revision == 0xE3 ||
> -  pdev->revision == 0xE7 ||
> -  pdev->revision == 0xF3 ||
> -  pdev->revision == 0xF7)) {
> - flags &= ~AMD_ASIC_MASK;
> - flags |= CHIP_POLARIS10;
> - }
> +
> + flags = amdgpu_fix_asic_type(pdev, flags);
>
>   /* Due to hardware bugs, S/G Display on raven requires a 1:1 IOMMU 
> mapping,
>* however, SME requires an indirect IOMMU mapping because the
> encryption diff --git a/include/drm/amd_asic_type.h
> b/include/drm/amd_asic_type.h index 90b69270f2fa..724c45e3e9a7 100644
> --- a/include/drm/amd_asic_type.h
> +++ b/include/drm/amd_asic_type.h
> @@ -68,4 +68,9 @@ enum amd_asic_type {
>
>  extern const char *amdgpu_asic_name[];
>
> +struct amdgpu_asic_type_quirk {
> + unsigned short device;  /* PCI device ID */
> + u8 revision;/* revision ID */
> + unsigned short type;/* real ASIC type */
> +};
>  #endif /*__AMD_ASIC_TYPE_H__ */

RE: [PATCH] drm/amd/pm: Fix error of MACO flag setting code

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Ma, Jun 
Sent: Tuesday, October 31, 2023 1:43 PM
To: amd-gfx@lists.freedesktop.org; Feng, Kenneth ; 
Deucher, Alexander 
Cc: Ma, Jun 
Subject: [PATCH] drm/amd/pm: Fix error of MACO flag setting code

MACO only works if BACO is supported

Signed-off-by: Ma Jun 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 8   
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 9 +
 2 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 2f3ffe9c0cf0..9f038e544270 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -355,12 +355,12 @@ static int smu_v13_0_0_check_powerplay_table(struct 
smu_context *smu)
if (powerplay_table->platform_caps & 
SMU_13_0_0_PP_PLATFORM_CAP_HARDWAREDC)
smu->dc_controlled_by_gpio = true;

-   if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO ||
-   powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
+   if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_BACO)
+{
smu_baco->platform_support = true;

-   if (powerplay_table->platform_caps & SMU_13_0_0_PP_PLATFORM_CAP_MACO)
-   smu_baco->maco_support = true;
+   if (powerplay_table->platform_caps & 
SMU_13_0_0_PP_PLATFORM_CAP_MACO)
+   smu_baco->maco_support = true;
+   }

if (!overdrive_lowerlimits->FeatureCtrlMask ||
!overdrive_upperlimits->FeatureCtrlMask)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index bc48347a4949..dc2316d8914c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -346,12 +346,13 @@ static int smu_v13_0_7_check_powerplay_table(struct 
smu_context *smu)
if (powerplay_table->platform_caps & 
SMU_13_0_7_PP_PLATFORM_CAP_HARDWAREDC)
smu->dc_controlled_by_gpio = true;

-   if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO ||
-   powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_MACO)
+   if (powerplay_table->platform_caps & SMU_13_0_7_PP_PLATFORM_CAP_BACO)
+{
smu_baco->platform_support = true;

-   if (smu_baco->platform_support && (BoardTable->HsrEnabled || 
BoardTable->VddqOffEnabled))
-   smu_baco->maco_support = true;
+   if ((powerplay_table->platform_caps & 
SMU_13_0_7_PP_PLATFORM_CAP_MACO)
+   && (BoardTable->HsrEnabled || 
BoardTable->VddqOffEnabled))
+   smu_baco->maco_support = true;
+   }

if (!overdrive_lowerlimits->FeatureCtrlMask ||
!overdrive_upperlimits->FeatureCtrlMask)
--
2.34.1

RE: [PATCH] drm/amdgpu: correct amdgpu ip block rev info

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Yang Wang
Sent: Tuesday, October 31, 2023 10:50 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Yang(Kevin) 
Subject: [PATCH] drm/amdgpu: correct amdgpu ip block rev info

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


correct following amdgpu ip block version information:
- gfx_v9_4_3
- sdma_v4_4_2

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c  | 2 +-  
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index b3d4458e3889..1c46d205c0ac 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -4295,7 +4295,7 @@ const struct amdgpu_ip_block_version gfx_v9_4_3_ip_block 
= {
.type = AMD_IP_BLOCK_TYPE_GFX,
.major = 9,
.minor = 4,
-   .rev = 0,
+   .rev = 3,
.funcs = _v9_4_3_ip_funcs,
 };

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c 
b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index c46bc6aa4f48..c851413ba6b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -2048,7 +2048,7 @@ const struct amdgpu_ip_block_version sdma_v4_4_2_ip_block 
= {
.type = AMD_IP_BLOCK_TYPE_SDMA,
.major = 4,
.minor = 4,
-   .rev = 0,
+   .rev = 2,
.funcs = _v4_4_2_ip_funcs,
 };

--
2.34.1

RE: [PATCH] drm/amdgpu: remove unused macro HW_REV

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Yang Wang
Sent: Tuesday, October 31, 2023 10:13 AM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Yang(Kevin) 
Subject: [PATCH] drm/amdgpu: remove unused macro HW_REV

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


remove unused macro HW_REV

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a2e8c2b60857..969d8ba8b8dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -365,9 +365,6 @@ struct amdgpu_ip_block_version {
const struct amd_ip_funcs *funcs;  };

-#define HW_REV(_Major, _Minor, _Rev) \
-   uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | 
((uint32_t) (_Rev)))
-
 struct amdgpu_ip_block {
struct amdgpu_ip_block_status status;
const struct amdgpu_ip_block_version *version;
--
2.34.1

RE: [PATCH] drm/amd/pm: Return 0 as default min power limit for legacy asics

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Ma, Jun 
Sent: Friday, October 27, 2023 9:57 AM
To: amd-gfx@lists.freedesktop.org; Feng, Kenneth ; 
Deucher, Alexander 
Cc: Ma, Jun 
Subject: [PATCH] drm/amd/pm: Return 0 as default min power limit for legacy 
asics

Return 0 as the default min power limit for the asics using powerplay.

Signed-off-by: Ma Jun 
---
 drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c 
b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index 9e4f8a4104a3..914c15387157 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -1022,6 +1022,9 @@ static int pp_get_power_limit(void *handle, uint32_t 
*limit,
*limit /= 100;
}
break;
+   case PP_PWR_LIMIT_MIN:
+   *limit = 0;
+   break;
default:
ret = -EOPNOTSUPP;
break;
--
2.34.1

RE: [PATCH v2] drm/amd/pm: fix the high voltage and temperature issue

[Feng, Kenneth]

[AMD Official Use Only - General]

Sorry that I forgot another change in this V2.
Please ignore this one.
Thanks.


-Original Message-
From: Kenneth Feng 
Sent: Wednesday, October 25, 2023 11:51 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Feng, Kenneth 

Subject: [PATCH v2] drm/amd/pm: fix the high voltage and temperature issue

fix the high voltage and temperature issue after the driver is unloaded on smu 
13.0.0, smu 13.0.7 and smu 13.0.10
v2 - fix the code format and make sure it is used on the unload case only.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 36 +++
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 33 +++--
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  1 +  
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h  |  2 ++
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 13 +++
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  |  8 -  
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  |  8 -
 7 files changed, 90 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 31f8c3ead161..c5c892a8b3f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3986,13 +3986,23 @@ int amdgpu_device_init(struct amdgpu_device *adev,
}
}
} else {
-   tmp = amdgpu_reset_method;
-   /* It should do a default reset when loading or 
reloading the driver,
-* regardless of the module parameter reset_method.
-*/
-   amdgpu_reset_method = AMD_RESET_METHOD_NONE;
-   r = amdgpu_asic_reset(adev);
-   amdgpu_reset_method = tmp;
+   switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
+   case IP_VERSION(13, 0, 0):
+   case IP_VERSION(13, 0, 7):
+   case IP_VERSION(13, 0, 10):
+   r = psp_gpu_reset(adev);
+   break;
+   default:
+   tmp = amdgpu_reset_method;
+   /* It should do a default reset when loading or 
reloading the driver,
+* regardless of the module parameter 
reset_method.
+*/
+   amdgpu_reset_method = AMD_RESET_METHOD_NONE;
+   r = amdgpu_asic_reset(adev);
+   amdgpu_reset_method = tmp;
+   break;
+   }
+
if (r) {
dev_err(adev->dev, "asic reset on init 
failed\n");
goto failed;
@@ -5945,6 +5955,18 @@ int amdgpu_device_baco_exit(struct drm_device *dev)
return -ENOTSUPP;

ret = amdgpu_dpm_baco_exit(adev);
+
+   if (!ret)
+   switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
+   case IP_VERSION(13, 0, 0):
+   case IP_VERSION(13, 0, 7):
+   case IP_VERSION(13, 0, 10):
+   adev->gfx.is_poweron = false;
+   break;
+   default:
+   break;
+   }
+
if (ret)
return ret;

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7c3356d6da5e..2e82172ba250 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -733,7 +733,7 @@ static int smu_early_init(void *handle)
smu->adev = adev;
smu->pm_enabled = !!amdgpu_dpm;
smu->is_apu = false;
-   smu->smu_baco.state = SMU_BACO_STATE_EXIT;
+   smu->smu_baco.state = SMU_BACO_STATE_NONE;
smu->smu_baco.platform_support = false;
smu->user_dpm_profile.fan_mode = -1;

@@ -1740,10 +1740,31 @@ static int smu_smc_hw_cleanup(struct smu_context *smu)
return 0;
 }

+static int smu_reset_mp1_state(struct smu_context *smu) {
+   struct amdgpu_device *adev = smu->adev;
+   int ret = 0;
+
+   if ((!adev->in_runpm) && (!adev->in_suspend) &&
+   (!amdgpu_in_reset(adev)))
+   switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
+ case IP_VERSION(13, 0, 0):
+ case IP_VERSION(13, 0, 7):
+ case IP_VERSION(13, 0, 10):
+   ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
+   break;
+ default:
+   break;
+   }
+
+   return ret;
+}
+
 static int smu_hw_fini(void *handle)
 {
struct amdgpu_device *adev = (struct 

RE: [PATCH 1/3] drm/amdgpu: ungate power gating when system suspend

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Yuan, Perry 
Sent: Tuesday, October 24, 2023 10:33 AM
To: Zhang, Yifan ; Feng, Kenneth ; 
Limonciello, Mario 
Cc: Deucher, Alexander ; Wang, Yang(Kevin) 
; amd-gfx@lists.freedesktop.org
Subject: [PATCH 1/3] drm/amdgpu: ungate power gating when system suspend

[Why] During suspend, if GFX DPM is enabled and GFXOFF feature is enabled the 
system may get hung. So, it is suggested to disable GFXOFF feature during 
suspend and enable it after resume.

[How] Update the code to disable GFXOFF feature during suspend and enable it 
after resume.

[  311.396526] amdgpu :03:00.0: amdgpu: SMU: I'm not done with your 
previous command: SMN_C2PMSG_66:0x001E SMN_C2PMSG_82:0x [  
311.396530] amdgpu :03:00.0: amdgpu: Fail to disable dpm features!
[  311.396531] [drm:amdgpu_device_ip_suspend_phase2 [amdgpu]] *ERROR* suspend 
of IP block  failed -62

Signed-off-by: Perry Yuan 
Signed-off-by: Kun Liu 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index d9ccacd06fba..6399bc71c56d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3498,6 +3498,8 @@ static void gfx_v10_0_ring_invalidate_tlbs(struct 
amdgpu_ring *ring,  static void gfx_v10_0_update_spm_vmid_internal(struct 
amdgpu_device *adev,
   unsigned int vmid);

+static int gfx_v10_0_set_powergating_state(void *handle,
+ enum amd_powergating_state state);
 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t 
queue_mask)  {
amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); @@ 
-7172,6 +7174,13 @@ static int gfx_v10_0_hw_fini(void *handle)
amdgpu_irq_put(adev, >gfx.priv_reg_irq, 0);
amdgpu_irq_put(adev, >gfx.priv_inst_irq, 0);

+   /* WA added for Vangogh asic fixing the SMU suspend failure
+* It needs to set power gating again during gfxoff control
+* otherwise the gfxoff disallowing will be failed to set.
+*/
+   if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1))
+   gfx_v10_0_set_powergating_state(handle, AMD_PG_STATE_UNGATE);
+
if (!adev->no_hw_access) {
if (amdgpu_async_gfx_ring) {
if (amdgpu_gfx_disable_kgq(adev, 0))
--
2.34.1

RE: [PATCH] drm/amd/pm: fix the high voltage and temperature issue on smu 13

[Feng, Kenneth]

[AMD Official Use Only - General]

Thanks Alex, I will make another patch.
And please refer to the comments inline below.


-Original Message-
From: Alex Deucher 
Sent: Friday, October 20, 2023 9:58 PM
To: Feng, Kenneth 
Cc: amd-gfx@lists.freedesktop.org; Wang, Yang(Kevin) 
Subject: Re: [PATCH] drm/amd/pm: fix the high voltage and temperature issue on 
smu 13

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


On Fri, Oct 20, 2023 at 4:32 AM Kenneth Feng  wrote:
>
> fix the high voltage and temperature issue after the driver is
> unloaded on smu 13.0.0, smu 13.0.7 and smu 13.0.10
>
> Signed-off-by: Kenneth Feng 
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 36 +++
>  drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c|  4 +--
>  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 27 --
>  drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  1 +
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h  |  2 ++
>  .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 13 +++
>  .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  |  8 -
> .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  |  8 -
>  8 files changed, 86 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 31f8c3ead161..c5c892a8b3f9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3986,13 +3986,23 @@ int amdgpu_device_init(struct amdgpu_device *adev,
> }
> }
> } else {
> -   tmp = amdgpu_reset_method;
> -   /* It should do a default reset when loading or 
> reloading the driver,
> -* regardless of the module parameter reset_method.
> -*/
> -   amdgpu_reset_method = AMD_RESET_METHOD_NONE;
> -   r = amdgpu_asic_reset(adev);
> -   amdgpu_reset_method = tmp;
> +   switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
> +   case IP_VERSION(13, 0, 0):
> +   case IP_VERSION(13, 0, 7):
> +   case IP_VERSION(13, 0, 10):
> +   r = psp_gpu_reset(adev);
> +   break;
> +   default:
> +   tmp = amdgpu_reset_method;
> +   /* It should do a default reset when loading 
> or reloading the driver,
> +* regardless of the module parameter 
> reset_method.
> +*/
> +   amdgpu_reset_method = AMD_RESET_METHOD_NONE;
> +   r = amdgpu_asic_reset(adev);
> +   amdgpu_reset_method = tmp;
> +   break;
> +   }
> +
> if (r) {
> dev_err(adev->dev, "asic reset on init 
> failed\n");
> goto failed; @@ -5945,6 +5955,18 @@
> int amdgpu_device_baco_exit(struct drm_device *dev)
> return -ENOTSUPP;
>
> ret = amdgpu_dpm_baco_exit(adev);
> +
> +   if (!ret)
> +   switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
> +   case IP_VERSION(13, 0, 0):
> +   case IP_VERSION(13, 0, 7):
> +   case IP_VERSION(13, 0, 10):
> +   adev->gfx.is_poweron = false;
> +   break;
> +   default:
> +   break;
> +   }

Maybe better to move this into smu_v13_0_0_baco_exit() so we keep the asic 
specific details out of the common files?

> +
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> index 80ca2c05b0b8..3ad38e42773b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> @@ -73,7 +73,7 @@ gmc_v11_0_vm_fault_interrupt_state(struct amdgpu_device 
> *adev,
>  * fini/suspend, so the overall state doesn't
>  * change over the course of suspend/resume.
>  */
> -   if (!adev->in_s0ix)
> +   if (!adev->in_s0ix && adev->gfx.is_poweron)
> amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB(0), 
> false);
> break;
> case AMDGPU_IRQ_STATE_ENABLE:
>

RE: [PATCH] drm/amd/pm: Fix the return value in default case

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Ma, Jun 
Sent: Thursday, October 19, 2023 10:29 AM
To: amd-gfx@lists.freedesktop.org; Feng, Kenneth ; 
Deucher, Alexander 
Cc: Ma, Jun ; Ma, Jun 
Subject: [PATCH] drm/amd/pm: Fix the return value in default case

Fix the return value in default case and drop redundant 'break'.

Signed-off-by: Ma Jun 
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7087f9840ab7..3b4053e2607b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2434,7 +2434,6 @@ int smu_get_power_limit(void *handle,
break;
default:
return -EOPNOTSUPP;
-   break;
}

switch (pp_limit_level) {
@@ -2452,7 +2451,6 @@ int smu_get_power_limit(void *handle,
break;
default:
return -EOPNOTSUPP;
-   break;
}

if (limit_type != SMU_DEFAULT_PPT_LIMIT) { @@ -2486,7 +2484,7 @@ int 
smu_get_power_limit(void *handle,
*limit = smu->min_power_limit;
break;
default:
-   break;
+   return -EINVAL;
}
}

--
2.34.1

RE: [PATCH] drm/amd/pm: Support for getting power1_cap_min value

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Ma, Jun 
Sent: Tuesday, October 17, 2023 3:22 PM
To: amd-gfx@lists.freedesktop.org; Feng, Kenneth ; 
Deucher, Alexander 
Cc: Ma, Jun ; Ma, Jun 
Subject: [PATCH] drm/amd/pm: Support for getting power1_cap_min value

Support for getting power1_cap_min value on smu13 and smu11.
For other Asics, we still use 0 as the default value.

Signed-off-by: Ma Jun 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c| 14 
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 16 +
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  8 +++--  
.../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 33 +++---
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 33 +++---
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 34 +++
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  |  5 ++-
 .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 13 ---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 34 ---  
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c  |  9 +++--  
.../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 34 ---
 drivers/gpu/drm/amd/pm/swsmu/smu_internal.h   |  2 +-
 12 files changed, 147 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index c7c29aa24c36..d76c3abf406f 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2921,14 +2921,6 @@ static ssize_t amdgpu_hwmon_show_power_input(struct 
device *dev,
return sysfs_emit(buf, "%zd\n", val);
 }

-static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
-struct device_attribute *attr,
-char *buf)
-{
-   return sysfs_emit(buf, "%i\n", 0);
-}
-
-
 static ssize_t amdgpu_hwmon_show_power_cap_generic(struct device *dev,
struct device_attribute *attr,
char *buf,
@@ -2965,6 +2957,12 @@ static ssize_t 
amdgpu_hwmon_show_power_cap_generic(struct device *dev,
return size;
 }

+static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
+struct device_attribute *attr,
+char *buf)
+{
+   return amdgpu_hwmon_show_power_cap_generic(dev, attr, buf,
+PP_PWR_LIMIT_MIN); }

 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
 struct device_attribute *attr,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7c3356d6da5e..f4a68d107184 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -849,7 +849,8 @@ static int smu_late_init(void *handle)
ret = smu_get_asic_power_limits(smu,
>current_power_limit,
>default_power_limit,
-   >max_power_limit);
+   >max_power_limit,
+   >min_power_limit);
if (ret) {
dev_err(adev->dev, "Failed to get asic power limits!\n");
return ret;
@@ -2447,6 +2448,8 @@ int smu_get_power_limit(void *handle,
limit_level = SMU_PPT_LIMIT_MAX;
break;
case PP_PWR_LIMIT_MIN:
+   limit_level = SMU_PPT_LIMIT_MIN;
+   break;
default:
return -EOPNOTSUPP;
break;
@@ -2466,8 +2469,7 @@ int smu_get_power_limit(void *handle,
case IP_VERSION(11, 0, 13):
ret = smu_get_asic_power_limits(smu,

>current_power_limit,
-   NULL,
-   NULL);
+   NULL, NULL, 
NULL);
break;
default:
break;
@@ -2480,6 +2482,8 @@ int smu_get_power_limit(void *handle,
case SMU_PPT_LIMIT_MAX:
*limit = smu->max_power_limit;
break;
+   case SMU_PPT_LIMIT_MIN:
+   *limit = smu->min_power_limit;
default:
break;
}
@@ -2502,10 +2506,10 @@ static int smu_set_power_limit(void *handle, uint32_t 
limit)
if (smu->ppt_funcs->set_power_limit)
return smu->ppt_funcs->set_power_limit(smu, limit_type, 
limit);

-   if (limit > smu->max_power_limit) {

RE: [PATCH] drm/amd/pm: drop most smu_cmn_get_smc_version in smu

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Zhang, Yifan 
Sent: Tuesday, October 10, 2023 10:52 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Koenig, Christian 
; Ma, Li ; Feng, Kenneth 
; Zhang, Yifan 
Subject: [PATCH] drm/amd/pm: drop most smu_cmn_get_smc_version in smu

smu_check_fw_version is called in smu hw init, thus smu if version and version 
are garenteed to be stored in smu context. No need to call 
smu_cmn_get_smc_version again after system boot up.

Signed-off-by: Yifan Zhang 
---
 .../gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c | 66 ---
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 37 +++
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 43 +++-
 .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c  | 45 +++--
 .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 60 +
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c  | 20 ++  
.../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c  | 22 ++-
 7 files changed, 61 insertions(+), 232 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
index 44e4289b95cd..e38620e9436c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
@@ -963,17 +963,10 @@ static int arcturus_force_clk_levels(struct smu_context 
*smu,
struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
struct smu_11_0_dpm_table *single_dpm_table = NULL;
uint32_t soft_min_level, soft_max_level;
-   uint32_t smu_version;
int ret = 0;

-   ret = smu_cmn_get_smc_version(smu, NULL, _version);
-   if (ret) {
-   dev_err(smu->adev->dev, "Failed to get smu version!\n");
-   return ret;
-   }
-
-   if ((smu_version >= 0x361200) &&
-   (smu_version <= 0x361a00)) {
+   if ((smu->smc_fw_version >= 0x361200) &&
+   (smu->smc_fw_version <= 0x361a00)) {
dev_err(smu->adev->dev, "Forcing clock level is not supported 
with "
   "54.18 - 54.26(included) SMU firmwares\n");
return -EOPNOTSUPP;
@@ -1344,16 +1337,11 @@ static int arcturus_get_power_profile_mode(struct 
smu_context *smu,
uint32_t i, size = 0;
int16_t workload_type = 0;
int result = 0;
-   uint32_t smu_version;

if (!buf)
return -EINVAL;

-   result = smu_cmn_get_smc_version(smu, NULL, _version);
-   if (result)
-   return result;
-
-   if (smu_version >= 0x360d00)
+   if (smu->smc_fw_version >= 0x360d00)
size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s 
%s %s\n",
title[0], title[1], title[2], title[3], title[4], 
title[5],
title[6], title[7], title[8], title[9], title[10]); @@ 
-1372,7 +1360,7 @@ static int arcturus_get_power_profile_mode(struct 
smu_context *smu,
if (workload_type < 0)
continue;

-   if (smu_version >= 0x360d00) {
+   if (smu->smc_fw_version >= 0x360d00) {
result = smu_cmn_update_table(smu,
  
SMU_TABLE_ACTIVITY_MONITOR_COEFF,
  workload_type,
@@ -1387,7 +1375,7 @@ static int arcturus_get_power_profile_mode(struct 
smu_context *smu,
size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
i, amdgpu_pp_profile_name[i], (i == 
smu->power_profile_mode) ? "*" : " ");

-   if (smu_version >= 0x360d00) {
+   if (smu->smc_fw_version >= 0x360d00) {
size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d 
%7d %7d %7d %7d %7d %7d %7d\n",
" ",
0,
@@ -1429,19 +1417,15 @@ static int arcturus_set_power_profile_mode(struct 
smu_context *smu,
int workload_type = 0;
uint32_t profile_mode = input[size];
int ret = 0;
-   uint32_t smu_version;

if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
dev_err(smu->adev->dev, "Invalid power profile mode %d\n", 
profile_mode);
return -EINVAL;
}

-   ret = smu_cmn_get_smc_version(smu, NULL, _version);
-   if (ret)
-   return ret;

if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
-(smu_version >= 0x360d00)) {
+(smu->smc_fw_version >= 0x360d00)) {
ret = smu_cmn_update_table(smu,
   SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 

RE: [PATCH] drm/amd/pm: allow the user to force BACO on smu v13.0.0/7

[Feng, Kenneth]

[AMD Official Use Only - General]

Hi Alex,
Right, just BAMACO has its advantage for the fast resume.
Maybe later we can further identify which sku needs to save more power vs 
faster resume time.
For example, mobile device can by default use BACO and desktop/workstation 
device can by default use BAMACO.
Thanks.


-Original Message-
From: Alex Deucher 
Sent: Wednesday, August 16, 2023 12:56 AM
To: Feng, Kenneth 
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/amd/pm: allow the user to force BACO on smu v13.0.0/7

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


On Tue, Aug 15, 2023 at 5:05 AM Kenneth Feng  wrote:
>
> allow the user to force BACO on smu v13.0.0/7
>
> Signed-off-by: Kenneth Feng 

Acked-by: Alex Deucher  Would it be better to 
default to BACO?  It would save more power at the expense of resume latency.

Alex


> ---
>  drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c   | 2 +-
>  drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 3 ++-
> drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 3 ++-
>  3 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> index 895cda8e6934..52e9c7611013 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> @@ -2263,7 +2263,7 @@ int smu_v13_0_baco_set_state(struct smu_context *smu,
> if (state == SMU_BACO_STATE_ENTER) {
> ret = smu_cmn_send_smc_msg_with_param(smu,
>   SMU_MSG_EnterBaco,
> - smu_baco->maco_support ?
> + (smu_baco->maco_support 
> && amdgpu_runtime_pm != 1) ?
>   BACO_SEQ_BAMACO : 
> BACO_SEQ_BACO,
>   NULL);
> } else {
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> index a5857acee641..12ccc12657d7 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
> @@ -2211,7 +2211,8 @@ static int smu_v13_0_0_baco_enter(struct
> smu_context *smu)
>
> if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
> return smu_v13_0_baco_set_armd3_sequence(smu,
> -   smu_baco->maco_support ? BACO_SEQ_BAMACO : 
> BACO_SEQ_BACO);
> +   (smu_baco->maco_support && amdgpu_runtime_pm 
> != 1) ?
> +   BACO_SEQ_BAMACO :
> + BACO_SEQ_BACO);
> else
> return smu_v13_0_baco_enter(smu);  } diff --git
> a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> index 93b3e8fa8238..f0bcc7995983 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> @@ -2139,7 +2139,8 @@ static int smu_v13_0_7_baco_enter(struct
> smu_context *smu)
>
> if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
> return smu_v13_0_baco_set_armd3_sequence(smu,
> -   smu_baco->maco_support ? BACO_SEQ_BAMACO : 
> BACO_SEQ_BACO);
> +   (smu_baco->maco_support && amdgpu_runtime_pm 
> != 1) ?
> +   BACO_SEQ_BAMACO :
> + BACO_SEQ_BACO);
> else
> return smu_v13_0_baco_enter(smu);  }
> --
> 2.34.1
>

RE: [PATCH] drm/amd/pm: disallow the fan setting if there is no fan on smu13

[Feng, Kenneth]

[AMD Official Use Only - General]

Currently no_fan is determined in sw init.
if (!smu->ppt_funcs->get_fan_control_mode)
smu->adev->pm.no_fan = true;

This is the case that some boards have fans and some don't have.
smu->ppt_funcs->get_fan_control_mode still need to be defined.
!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT) is enough to 
get the fan capability.
Not sure if it's better to depend on pm.no_fan.
Thanks.



-Original Message-
From: Lazar, Lijo 
Sent: Tuesday, August 8, 2023 6:12 PM
To: Feng, Kenneth ; amd-gfx@lists.freedesktop.org
Cc: Arif, Maisam 
Subject: Re: [PATCH] drm/amd/pm: disallow the fan setting if there is no fan on 
smu13



On 8/8/2023 1:21 PM, Kenneth Feng wrote:
> disallow the fan setting if there is no fan on smu13
>
> Signed-off-by: Kenneth Feng 
> ---
>   drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 9 ++---
>   1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> index 9b62b45ebb7f..09ef0a7e7679 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
> @@ -1131,7 +1131,9 @@ smu_v13_0_display_clock_voltage_request(struct 
> smu_context *smu,
>
>   uint32_t smu_v13_0_get_fan_control_mode(struct smu_context *smu)
>   {
> - if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
> + if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
> + return AMD_FAN_CTRL_NONE;

If there is no PMFW fan control, isn't it better to set pm.no_fan?

Thanks,
Lijo

> + else if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
>   return AMD_FAN_CTRL_MANUAL;
>   else
>   return AMD_FAN_CTRL_AUTO;
> @@ -1143,7 +1145,7 @@ smu_v13_0_auto_fan_control(struct smu_context *smu, 
> bool auto_fan_control)
>   int ret = 0;
>
>   if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
> - return 0;
> + return -EINVAL;
>
>   ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, 
> auto_fan_control);
>   if (ret)
> @@ -1204,7 +1206,8 @@ smu_v13_0_set_fan_control_mode(struct smu_context *smu,
>
>   switch (mode) {
>   case AMD_FAN_CTRL_NONE:
> - ret = smu_v13_0_set_fan_speed_pwm(smu, 255);
> + if (smu_cmn_feature_is_supported(smu, 
> SMU_FEATURE_FAN_CONTROL_BIT))
> + ret = -EINVAL;
>   break;
>   case AMD_FAN_CTRL_MANUAL:
>   ret = smu_v13_0_auto_fan_control(smu, 0);

RE: [PATCH] drm/amd/pm: fix variable dereferenced issue in amdgpu_device_attr_create()

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Yang Wang
Sent: Tuesday, August 1, 2023 5:16 PM
To: amd-gfx@lists.freedesktop.org
Cc: Dan Carpenter ; Wang, Yang(Kevin) 

Subject: [PATCH] drm/amd/pm: fix variable dereferenced issue in 
amdgpu_device_attr_create()

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


- fix variable ('attr') dereferenced issue.
- using condition check instead of BUG_ON().

Fixes: 4e01847c38f7 ("drm/amdgpu: optimize amdgpu device attribute code")

Cc: Dan Carpenter 
Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 3922dd274f30..383b2b778456 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2171,15 +2171,19 @@ static int amdgpu_device_attr_create(struct 
amdgpu_device *adev,
 uint32_t mask, struct list_head 
*attr_list)  {
int ret = 0;
-   struct device_attribute *dev_attr = >dev_attr;
-   const char *name = dev_attr->attr.name;
enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
struct amdgpu_device_attr_entry *attr_entry;
+   struct device_attribute *dev_attr;
+   const char *name;

int (*attr_update)(struct amdgpu_device *adev, struct 
amdgpu_device_attr *attr,
   uint32_t mask, enum amdgpu_device_attr_states 
*states) = default_attr_update;

-   BUG_ON(!attr);
+   if (!attr)
+   return -EINVAL;
+
+   dev_attr = >dev_attr;
+   name = dev_attr->attr.name;

attr_update = attr->attr_update ? attr->attr_update : 
default_attr_update;

--
2.34.1

RE: [PATCH 2/2] drm/amdgpu/pm: make mclk consistent for smu 13.0.7

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Alex Deucher
Sent: Thursday, July 13, 2023 10:33 PM
To: Deucher, Alexander 
Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amdgpu/pm: make mclk consistent for smu 13.0.7

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


Ping on this series?

Alex

On Tue, Jun 13, 2023 at 12:42 PM Alex Deucher  wrote:
>
> Use current uclk to be consistent with other dGPUs.
>
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> index cda4e818aab7..8eb8c30e6c69 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> @@ -949,7 +949,7 @@ static int smu_v13_0_7_read_sensor(struct smu_context 
> *smu,
> break;
> case AMDGPU_PP_SENSOR_GFX_MCLK:
> ret = smu_v13_0_7_get_smu_metrics_data(smu,
> -  METRICS_AVERAGE_UCLK,
> +  METRICS_CURR_UCLK,
>(uint32_t *)data);
> *(uint32_t *)data *= 100;
> *size = 4;
> --
> 2.40.1
>

RE: [PATCH] drm/amd/pm: disbale dcefclk device sysnode on GFX v9.4.3 chip

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 

-Original Message-
From: amd-gfx  On Behalf Of Wang, 
Yang(Kevin)
Sent: Wednesday, July 5, 2023 10:25 AM
To: amd-gfx@lists.freedesktop.org
Subject: RE: [PATCH] drm/amd/pm: disbale dcefclk device sysnode on GFX v9.4.3 
chip

[AMD Official Use Only - General]

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


[AMD Official Use Only - General]

Ping...

-Original Message-
From: Wang, Yang(Kevin) 
Sent: Friday, June 30, 2023 7:22 PM
To: amd-gfx@lists.freedesktop.org
Cc: Wang, Yang(Kevin) 
Subject: [PATCH] drm/amd/pm: disbale dcefclk device sysnode on GFX v9.4.3 chip

the dceflck sysnode is not aviable on GFX v9.4.3 chip.

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 9ef88a0b1b57..5bf401533103 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2050,7 +2050,8 @@ static int default_attr_update(struct amdgpu_device 
*adev, struct amdgpu_device_
} else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
if (gc_ver < IP_VERSION(9, 0, 0) ||
gc_ver == IP_VERSION(9, 4, 1) ||
-   gc_ver == IP_VERSION(9, 4, 2))
+   gc_ver == IP_VERSION(9, 4, 2) ||
+   gc_ver == IP_VERSION(9, 4, 3))
*states = ATTR_STATE_UNSUPPORTED;
} else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
if (mp1_ver < IP_VERSION(10, 0, 0))
--
2.34.1

RE: [PATCH] drm/amd/pm: add delay to avoid unintened shutdown due to hotspot temperature spark

[Feng, Kenneth]

[AMD Official Use Only - General]

Do we really need this delay on all the ASICs?
Maybe set the default value to 0 is more reasonable?
Thanks.


-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: Tuesday, May 16, 2023 10:51 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan 

Subject: [PATCH] drm/amd/pm: add delay to avoid unintened shutdown due to 
hotspot temperature spark

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


There will be a double check for the hotspot temperature on delay expired. This 
can avoid unintended shutdown due to hotspot temperature spark.

Signed-off-by: Evan Quan 
--
v1->v2:
  - add the proper millidegree Celsius to degree Celsius transform
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   | 14 
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 34 +++
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  2 ++
 .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c|  9 ++---
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c|  9 ++---
 6 files changed, 55 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 39192eba3ff8..4cd873659365 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -243,6 +243,7 @@ extern int amdgpu_num_kcq;  #define AMDGPU_VCNFW_LOG_SIZE 
(32 * 1024)  extern int amdgpu_vcnfw_log;  extern int amdgpu_sg_display;
+extern uint amdgpu_ctf_delay;

 #define AMDGPU_VM_MAX_NUM_CTX  4096
 #define AMDGPU_SG_THRESHOLD(256*1024*1024)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 749eeb9a2976..6c699fefdf92 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -198,6 +198,7 @@ int amdgpu_smartshift_bias;  int amdgpu_use_xgmi_p2p = 1;  
int amdgpu_vcnfw_log;  int amdgpu_sg_display = -1; /* auto */
+uint amdgpu_ctf_delay = 50; /* in ms */

 static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);

@@ -973,6 +974,19 @@ MODULE_PARM_DESC(smu_pptable_id,
"specify pptable id to be used (-1 = auto(default) value, 0 = use 
pptable from vbios, > 0 = soft pptable id)");  
module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);

+/**
+ * DOC: ctf_delay (uint)
+ * On SW CTF triggerred, to protect the chip from over-heated and
+possible damage, we usually
+ * trigger a system shutdown. However, considering there may be a
+hotspot temperature spark
+ * momentarily hitting the SW CTF setting point, a delay is added to avoid 
unintended shutdown.
+ * On the delay expired, the shutdown will be performed if the hotspot
+temp is still
+ * bigger than the SW CTF setting. Otherwise, nothing will be done.
+ * The default setting for the delay is 50ms.
+ */
+MODULE_PARM_DESC(ctf_delay,
+   "the delay(default 50ms) enforced before real action
+taken on ctf triggerred"); module_param_named(ctf_delay,
+amdgpu_ctf_delay, uint, 0444);
+
 /* These devices are not supported by amdgpu.
  * They are supported by the mach64, r128, radeon drivers
  */
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 3c860939031e..71153b335ad9 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -24,6 +24,7 @@

 #include 
 #include 
+#include 

 #include "amdgpu.h"
 #include "amdgpu_smu.h"
@@ -1070,6 +1071,34 @@ static void smu_interrupt_work_fn(struct work_struct 
*work)
smu->ppt_funcs->interrupt_work(smu);
 }

+static void smu_swctf_delayed_work_handler(struct work_struct *work) {
+   struct smu_context *smu =
+   container_of(work, struct smu_context, swctf_delayed_work.work);
+   struct smu_temperature_range *range =
+   >thermal_range;
+   struct amdgpu_device *adev = smu->adev;
+   uint32_t hotspot_tmp, size;
+
+   /*
+* If the hotspot temperature is confirmed as below SW CTF setting point
+* after the delay enforced, nothing will be done.
+* Otherwise, a graceful shutdown will be performed to prevent further 
damage.
+*/
+   if (smu->ppt_funcs->read_sensor &&
+   !smu->ppt_funcs->read_sensor(smu,
+AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
+_tmp,
+) &&
+   range->software_shutdown_temp &&
+   hotspot_tmp / 1000 < range->software_shutdown_temp)
+   return;
+
+   dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) 
detected!\n");
+   dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW 
CTF!\n");
+   orderly_poweroff(true);
+}

RE: [PATCH] drm/amd/pm: fix possible power mode mismatch between driver and PMFW

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Quan, Evan 
Sent: Friday, May 12, 2023 11:18 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Feng, Kenneth 
; Quan, Evan 
Subject: [PATCH] drm/amd/pm: fix possible power mode mismatch between driver 
and PMFW

PMFW may boots the ASIC with a different power mode from the system's real one. 
Notify PMFW explicitly the power mode the system in. This is needed only when 
ACDC switch via gpio is not supported.

Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 18 +
 .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c   | 20 +--
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  |  1 +
 3 files changed, 20 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 5633c5797e85..2ddf5198e5c4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -733,6 +733,24 @@ static int smu_late_init(void *handle)
return ret;
}

+   /*
+* Explicitly notify PMFW the power mode the system in. Since
+* the PMFW may boot the ASIC with a different mode.
+* For those supporting ACDC switch via gpio, PMFW will
+* handle the switch automatically. Driver involvement
+* is unnecessary.
+*/
+   if (!smu->dc_controlled_by_gpio) {
+   ret = smu_set_power_source(smu,
+  adev->pm.ac_power ? 
SMU_POWER_SOURCE_AC :
+  SMU_POWER_SOURCE_DC);
+   if (ret) {
+   dev_err(adev->dev, "Failed to switch to %s mode!\n",
+   adev->pm.ac_power ? "AC" : "DC");
+   return ret;
+   }
+   }
+
if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) ||
(adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3)))
return 0;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index c4000518dc56..275f708db636 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -3413,26 +3413,8 @@ static int navi10_post_smu_init(struct smu_context *smu)
return 0;

ret = navi10_run_umc_cdr_workaround(smu);
-   if (ret) {
+   if (ret)
dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");
-   return ret;
-   }
-
-   if (!smu->dc_controlled_by_gpio) {
-   /*
-* For Navi1X, manually switch it to AC mode as PMFW
-* may boot it with DC mode.
-*/
-   ret = smu_v11_0_set_power_source(smu,
-adev->pm.ac_power ?
-SMU_POWER_SOURCE_AC :
-SMU_POWER_SOURCE_DC);
-   if (ret) {
-   dev_err(adev->dev, "Failed to switch to %s mode!\n",
-   adev->pm.ac_power ? "AC" : "DC");
-   return ret;
-   }
-   }

return ret;
 }
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 3d9ff46706fb..98a33f8ee209 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1770,6 +1770,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = 
{
.enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost,
.get_power_limit = smu_v13_0_7_get_power_limit,
.set_power_limit = smu_v13_0_set_power_limit,
+   .set_power_source = smu_v13_0_set_power_source,
.get_power_profile_mode = smu_v13_0_7_get_power_profile_mode,
.set_power_profile_mode = smu_v13_0_7_set_power_profile_mode,
.set_tool_table_location = smu_v13_0_set_tool_table_location,
--
2.34.1

RE: [PATCH 1/2] drm/amd/pm: correct SMU13.0.7 pstate profiling clock settings

[Feng, Kenneth]

[AMD Official Use Only - General]

Series is Reviewed-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Horatio Zhang
Sent: Monday, April 10, 2023 10:03 AM
To: amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei ; Zhang, Horatio ; 
Quan, Evan 
Subject: [PATCH 1/2] drm/amd/pm: correct SMU13.0.7 pstate profiling clock 
settings

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


Correct the pstate standard/peak profiling mode clock settings for SMU13.0.7.

Signed-off-by: Horatio Zhang 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 22 +--
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index ccdc2ecab1dd..1b1c6c21c002 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1329,9 +1329,17 @@ static int smu_v13_0_7_populate_umd_state_clk(struct 
smu_context *smu)
_context->dpm_tables.fclk_table;
struct smu_umd_pstate_table *pstate_table =
>pstate_table;
+   struct smu_table_context *table_context = >smu_table;
+   PPTable_t *pptable = table_context->driver_pptable;
+   DriverReportedClocks_t driver_clocks =
+   pptable->SkuTable.DriverReportedClocks;

pstate_table->gfxclk_pstate.min = gfx_table->min;
-   pstate_table->gfxclk_pstate.peak = gfx_table->max;
+   if (driver_clocks.GameClockAc &&
+   (driver_clocks.GameClockAc < gfx_table->max))
+   pstate_table->gfxclk_pstate.peak = driver_clocks.GameClockAc;
+   else
+   pstate_table->gfxclk_pstate.peak = gfx_table->max;

pstate_table->uclk_pstate.min = mem_table->min;
pstate_table->uclk_pstate.peak = mem_table->max; @@ -1348,12 +1356,12 
@@ static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
pstate_table->fclk_pstate.min = fclk_table->min;
pstate_table->fclk_pstate.peak = fclk_table->max;

-   /*
-* For now, just use the mininum clock frequency.
-* TODO: update them when the real pstate settings available
-*/
-   pstate_table->gfxclk_pstate.standard = gfx_table->min;
-   pstate_table->uclk_pstate.standard = mem_table->min;
+   if (driver_clocks.BaseClockAc &&
+   driver_clocks.BaseClockAc < gfx_table->max)
+   pstate_table->gfxclk_pstate.standard = 
driver_clocks.BaseClockAc;
+   else
+   pstate_table->gfxclk_pstate.standard = gfx_table->max;
+   pstate_table->uclk_pstate.standard = mem_table->max;
pstate_table->socclk_pstate.standard = soc_table->min;
pstate_table->vclk_pstate.standard = vclk_table->min;
pstate_table->dclk_pstate.standard = dclk_table->min;
--
2.34.1

RE: [PATCH 0/3] enable new capped/uncapped power profiles

[Feng, Kenneth]

[AMD Official Use Only - General]

Acked-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Perry Yuan
Sent: Friday, February 24, 2023 4:33 PM
To: Deucher, Alexander ; Quan, Evan 
; Lazar, Lijo ; Li, Candice 
; amd-gfx@lists.freedesktop.org
Cc: Huang, Shimmer ; Liu, Kun 
Subject: [PATCH 0/3] enable new capped/uncapped power profiles

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


The patchset will enable the capped and uncapped mode

This new capped power mode has limit DRAM Thresholds and conditions in 
DF-PState Algorithm based on the workload type set from driver.
The uncapped mode will reset to normal performance level which has no such 
power limitations.

Perf Centric Workload (Uncapped)0
Power Centric Workload (Capped) 1

Perry Yuan (3):
  drm/amdgpu/pm: add capped/uncapped power profile modes
  drm/amdgpu: map new capped and uncapped mode power profiles for
Vangogh
  drm/amdgpu: skip the invalid workload type

 drivers/gpu/drm/amd/include/kgd_pp_interface.h  | 2 ++
 drivers/gpu/drm/amd/pm/amdgpu_pm.c  | 2 ++
 .../drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_vangogh.h  | 4 +++-
 drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c| 6 --
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c| 4 +++-
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c| 4 +++-
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c  | 4 ++--
 7 files changed, 19 insertions(+), 7 deletions(-)

--
2.34.1

RE: [PATCH] drm/amd/pm/smu13: BACO is supported when it's in BACO state

[Feng, Kenneth]

[AMD Official Use Only - General]

It makes sense.
Reviewed-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Guchun Chen
Sent: Tuesday, January 10, 2023 11:38 AM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Zhang, Hawking ; Lazar, 
Lijo ; Quan, Evan 
Cc: Chen, Guchun 
Subject: [PATCH] drm/amd/pm/smu13: BACO is supported when it's in BACO state

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


This leverages the logc in smu11. No need to talk to SMU to check BACO 
enablement as it's in BACO state already.

Signed-off-by: Guchun Chen 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index ccaedfcf977e..78945e79dbee 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2243,6 +2243,10 @@ bool smu_v13_0_baco_is_support(struct smu_context *smu)
!smu_baco->platform_support)
return false;

+   /* return true if ASIC is in BACO state already */
+   if (smu_v13_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
+   return true;
+
if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
return false;
--
2.25.1

RE: [PATCH 2/2] drm/amdgpu: add the fan abnormal detection feature

[Feng, Kenneth]

[AMD Official Use Only - General]

Series is Reviewed-by: Kenneth Feng 

-Original Message-
From: amd-gfx  On Behalf Of lyndonli
Sent: Monday, November 21, 2022 9:45 AM
To: amd-gfx@lists.freedesktop.org
Cc: Xu, Feifei ; enneth.f...@amd.com; Quan, Evan 
; Li, Lyndon 
Subject: [PATCH 2/2] drm/amdgpu: add the fan abnormal detection feature

Caution: This message originated from an External Source. Use proper caution 
when opening attachments, clicking links, or responding.


Update the SW CTF limit from existing register when there's a fan failure 
detected via SMU interrupt.

Signed-off-by: lyndonli 
---
 drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h |  1 +
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c| 28 +++
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  |  1 +
 3 files changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
index 44bbf17e4bef..3bc4128a22ac 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h
@@ -168,6 +168,7 @@ struct smu_temperature_range {
int mem_crit_max;
int mem_emergency_max;
int software_shutdown_temp;
+   int software_shutdown_temp_offset;
 };

 struct smu_state_validation_block {
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 89f0f6eb19f3..5a905002252d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -1376,6 +1376,7 @@ static int smu_v13_0_irq_process(struct amdgpu_device 
*adev,
 */
uint32_t ctxid = entry->src_data[0];
uint32_t data;
+   uint32_t high;

if (client_id == SOC15_IH_CLIENTID_THM) {
switch (src_id) {
@@ -1432,6 +1433,33 @@ static int smu_v13_0_irq_process(struct amdgpu_device 
*adev,

schedule_work(>throttling_logging_work);

break;
+   case 0x8:
+   high = 
smu->thermal_range.software_shutdown_temp +
+   
smu->thermal_range.software_shutdown_temp_offset;
+   high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP, 
high);
+   dev_emerg(adev->dev, "Reduce soft CTF limit to 
%d (by an offset %d)\n",
+   high,
+
+ smu->thermal_range.software_shutdown_temp_offset);
+
+   data = RREG32_SOC15(THM, 0, 
regTHM_THERMAL_INT_CTRL);
+   data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
+   DIG_THERM_INTH,
+   (high & 0xff));
+   data = data & 
(~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
+   WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, 
data);
+   break;
+   case 0x9:
+   high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
+   
smu->thermal_range.software_shutdown_temp);
+   dev_emerg(adev->dev, "Recover soft CTF
+ limit to %d\n", high);
+
+   data = RREG32_SOC15(THM, 0, 
regTHM_THERMAL_INT_CTRL);
+   data = REG_SET_FIELD(data, THM_THERMAL_INT_CTRL,
+   DIG_THERM_INTH,
+   (high & 0xff));
+   data = data & 
(~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
+   WREG32_SOC15(THM, 0, regTHM_THERMAL_INT_CTRL, 
data);
+   break;
}
}
}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index d74debc584f8..c3c9ef523e59 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1223,6 +1223,7 @@ static int 
smu_v13_0_7_get_thermal_temperature_range(struct smu_context *smu,
range->mem_emergency_max = 
(pptable->SkuTable.TemperatureLimit[TEMP_MEM] + CTF_OFFSET_MEM)*
SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
+   range->software_shutdown_temp_offset =
+ pptable->SkuTable.FanAbnormalTempLimitOffset;

return 0;
 }
--
2.25.1

答复: [PATCH v2 2/2] amdgpu/pm: Fix possible array out-of-bounds if SCLK levels != 2

[Feng, Kenneth]

[AMD Official Use Only - General]


[AMD Official Use Only - General]
Reviewed-by: Kenneth Feng mailto:kenneth.f...@amd.com>>


Best wishes
Kenneth Feng


发件人: Powell, Darren 
日期: 星期四, 2022年6月16日 05:00
收件人: amd-gfx@lists.freedesktop.org 
抄送: Lazar, Lijo , Wang, Yang(Kevin) 
, Feng, Kenneth , Quan, Evan 
, Ma, Le 
主题: Re: [PATCH v2 2/2] amdgpu/pm: Fix possible array out-of-bounds if SCLK 
levels != 2

[AMD Official Use Only - General]

Ping 

From: Powell, Darren 
Sent: Wednesday, May 11, 2022 1:44 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Lazar, Lijo ; Wang, Yang(Kevin) 
; Feng, Kenneth ; Quan, Evan 
; Ma, Le ; Powell, Darren 

Subject: [PATCH v2 2/2] amdgpu/pm: Fix possible array out-of-bounds if SCLK 
levels != 2

[v2]
simplified fix after Lijo's feedback
 removed clocks.num_levels from calculation of loop count
   removed unsafe accesses to shim table freq_values
 retained corner case output only min,now if
   clocks.num_levels == 1 && now > min

 [v1]
added a check to populate and use SCLK shim table freq_values only
   if using dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL or
 AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM
removed clocks.num_levels from calculation of shim table size
removed unsafe accesses to shim table freq_values
   output gfx_table values if using other dpm levels
added check for freq_match when using freq_values for when now == min_clk

== Test ==
LOGFILE=aldebaran-sclk.test.log
AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print 
$9}'`
HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}

lspci -nn | grep "VGA\|Display"  > $LOGFILE
FILES="pp_od_clk_voltage
pp_dpm_sclk"

for f in $FILES
do
  echo === $f === >> $LOGFILE
  cat $HWMON_DIR/device/$f >> $LOGFILE
done
cat $LOGFILE

Signed-off-by: Darren Powell 
---
 .../drm/amd/pm/swsmu/smu13/aldebaran_ppt.c| 34 +++
 1 file changed, 12 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 6a4fca47ae53..3eb82bc88890 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -740,7 +740,7 @@ static int aldebaran_print_clk_levels(struct smu_context 
*smu,
 struct smu_13_0_dpm_table *single_dpm_table;
 struct smu_dpm_context *smu_dpm = >smu_dpm;
 struct smu_13_0_dpm_context *dpm_context = NULL;
-   uint32_t display_levels;
+   int display_levels;
 uint32_t freq_values[3] = {0};
 uint32_t min_clk, max_clk;

@@ -772,7 +772,7 @@ static int aldebaran_print_clk_levels(struct smu_context 
*smu,
 return ret;
 }

-   display_levels = clocks.num_levels;
+   display_levels = (clocks.num_levels == 1) ? 1 : 2;

 min_clk = pstate_table->gfxclk_pstate.curr.min;
 max_clk = pstate_table->gfxclk_pstate.curr.max;
@@ -782,30 +782,20 @@ static int aldebaran_print_clk_levels(struct smu_context 
*smu,

 /* fine-grained dpm has only 2 levels */
 if (now > min_clk && now < max_clk) {
-   display_levels = clocks.num_levels + 1;
+   display_levels++;
 freq_values[2] = max_clk;
 freq_values[1] = now;
 }

-   /*
-* For DPM disabled case, there will be only one clock level.
-* And it's safe to assume that is always the current clock.
-*/
-   if (display_levels == clocks.num_levels) {
-   for (i = 0; i < clocks.num_levels; i++)
-   size += sysfs_emit_at(buf, size, "%d: %uMhz 
%s\n", i,
-   freq_values[i],
-   (clocks.num_levels == 1) ?
-   "*" :
-   (aldebaran_freqs_in_same_level(
-freq_values[i], now) ?
-"*" :
-""));
-   } else {
-   for (i = 0; i < display_levels; i++)
-   size += sysfs_emit_at(buf, size, "%d: %uMhz 
%s\n", i,
-   freq_values[i], i == 1 ? "*" : 
"");
-   }
+   for (i = 0; i < display_levels; i++)
+   size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
+   freq

答复: [PATCH] drm/amd/pm: skip to set mp1 unload state in special case

[Feng, Kenneth]

[AMD Official Use Only - General]


[AMD Official Use Only - General]
Reviewed-by: Kenneth Feng mailto:kenneth.f...@amd.com>>


Best wishes
Kenneth Feng


发件人: amd-gfx  代表 Yang Wang 

日期: 星期五, 2022年6月10日 11:52
收件人: amd-gfx@lists.freedesktop.org 
抄送: Feng, Kenneth , Wang, Yang(Kevin) 

主题: [PATCH] drm/amd/pm: skip to set mp1 unload state in special case
[CAUTION: External Email]

set mp1 unload state will cause the SMC FW can't accept any SMU message,
skip to set mp1 unload state to avoid following case fail:
- runtime pm case.
- gpu reset case.

Fixes: 826126d8f805 ("drm/amd/pm: fix driver reload SMC firmware fail issue for 
smu13")

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 11 ++-
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 3d269d1c2749..fd79b213fab4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1415,12 +1415,13 @@ static int smu_disable_dpms(struct smu_context *smu)
switch (adev->ip_versions[MP1_HWIP][0]) {
case IP_VERSION(13, 0, 0):
case IP_VERSION(13, 0, 7):
-   ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
-   if (ret) {
-   dev_err(adev->dev, "Fail set mp1 state to UNLOAD!\n");
-   return ret;
+   if (!(adev->in_runpm || amdgpu_in_reset(adev))) {
+   ret = smu_set_mp1_state(smu, PP_MP1_STATE_UNLOAD);
+   if (ret) {
+   dev_err(adev->dev, "Fail set mp1 state to 
UNLOAD!\n");
+   return ret;
+   }
}
-
return 0;
default:
break;
--
2.25.1

答复: [PATCH 2/5] drm/amd/pm: enable BACO on smu_v13_0_7

[Feng, Kenneth]

[AMD Official Use Only - General]


[AMD Official Use Only - General]
Yeah, synced to the latest code. Somehow ‘drm/amd/pm: drop redundant 
declarations’was reverted somehow at a point.
Thanks.


Best wishes
Kenneth Feng


发件人: Lazar, Lijo 
日期: 星期三, 2022年6月8日 17:14
收件人: Feng, Kenneth , amd-gfx@lists.freedesktop.org 

主题: Re: [PATCH 2/5] drm/amd/pm: enable BACO on smu_v13_0_7


On 6/8/2022 2:35 PM, Kenneth Feng wrote:
> enable BACO on smu_v13_0_7
>
> Signed-off-by: Kenneth Feng 
> ---
>   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c| 1 +
>   drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 7 +++
>   2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index fb04d82f66e6..f57710790b8c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1456,6 +1456,7 @@ static int smu_disable_dpms(struct smu_context *smu)
>case IP_VERSION(11, 0, 0):
>case IP_VERSION(11, 0, 5):
>case IP_VERSION(11, 0, 9):
> + case IP_VERSION(13, 0, 7):
>return 0;
>default:
>break;
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> index 7da42cae5d6e..dc614befcdf5 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
> @@ -97,6 +97,7 @@ static struct cmn2asic_msg_mapping 
> smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =
>MSG_MAP(UseDefaultPPTable,  PPSMC_MSG_UseDefaultPPTable,   
> 0),
>MSG_MAP(RunDcBtc,   PPSMC_MSG_RunDcBtc,
> 0),
>MSG_MAP(EnterBaco,  PPSMC_MSG_EnterBaco,   
> 0),
> + MSG_MAP(ExitBaco,   PPSMC_MSG_ExitBaco, 
> 0),
>MSG_MAP(SetSoftMinByFreq,   PPSMC_MSG_SetSoftMinByFreq,
> 1),
>MSG_MAP(SetSoftMaxByFreq,   PPSMC_MSG_SetSoftMaxByFreq,
> 1),
>MSG_MAP(SetHardMinByFreq,   PPSMC_MSG_SetHardMinByFreq,
> 1),
> @@ -281,6 +282,7 @@ smu_v13_0_7_get_allowed_feature_mask(struct smu_context 
> *smu,
>*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
>*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_PCC_DFLL_BIT);
>*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_CG_BIT);
> + *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_BIT);
>
>if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
>*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);
> @@ -1584,6 +1586,11 @@ static const struct pptable_funcs 
> smu_v13_0_7_ppt_funcs = {
>.set_tool_table_location = smu_v13_0_set_tool_table_location,
>.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
>.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
> + .baco_is_support = smu_v13_0_baco_is_support,
> + .baco_get_state = smu_v13_0_baco_get_state,
> + .baco_set_state = smu_v13_0_baco_set_state,
> + .baco_enter = smu_v13_0_baco_enter,
> + .baco_exit = smu_v13_0_baco_exit,

I remember seeing this one -  "drm/amd/pm: drop redundant declarations"
which drops smu13 baco common functions. Is this in sync with the latest
source?

Thanks,
Lijo


>   };
>
>   void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
>

答复: [PATCH 1/2] drm/amd/pm: add smu feature map support for smu_v13_0_7

[Feng, Kenneth]

[AMD Official Use Only - General]

Series is Reviewed-by: Kenneth Feng 
mailto:kenneth.f...@amd.com>>


Best wishes
Kenneth Feng


发件人: amd-gfx  代表 Yang Wang 

日期: 星期三, 2022年5月11日 13:09
收件人: amd-gfx@lists.freedesktop.org 
抄送: Wang, Yang(Kevin) 
主题: [PATCH 1/2] drm/amd/pm: add smu feature map support for smu_v13_0_7
[CAUTION: External Email]

the pp_features can't display full feauture information
when these mapping is not exiting.

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h  | 23 
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 58 ---
 2 files changed, 73 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h 
b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
index 3f40cd6e4165..799050ea7515 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h
@@ -368,6 +368,29 @@ enum smu_clk_type {
__SMU_DUMMY_MAP(DATA_CALCULATION),  \
__SMU_DUMMY_MAP(DPM_VCLK),  \
__SMU_DUMMY_MAP(DPM_DCLK),  \
+   __SMU_DUMMY_MAP(FW_DATA_READ),  \
+   __SMU_DUMMY_MAP(DPM_GFX_POWER_OPTIMIZER),   \
+   __SMU_DUMMY_MAP(DPM_DCN),   \
+   __SMU_DUMMY_MAP(VMEMP_SCALING), \
+   __SMU_DUMMY_MAP(VDDIO_MEM_SCALING), \
+   __SMU_DUMMY_MAP(MM_DPM),\
+   __SMU_DUMMY_MAP(SOC_MPCLK_DS),  \
+   __SMU_DUMMY_MAP(BACO_MPCLK_DS), \
+   __SMU_DUMMY_MAP(THROTTLERS),\
+   __SMU_DUMMY_MAP(SMARTSHIFT),\
+   __SMU_DUMMY_MAP(GFX_READ_MARGIN),   \
+   __SMU_DUMMY_MAP(GFX_IMU),   \
+   __SMU_DUMMY_MAP(GFX_PCC_DFLL),  \
+   __SMU_DUMMY_MAP(BOOT_TIME_CAL), \
+   __SMU_DUMMY_MAP(BOOT_POWER_OPT),\
+   __SMU_DUMMY_MAP(GFXCLK_SPREAD_SPECTRUM),\
+   __SMU_DUMMY_MAP(SOC_PCC),   \
+   __SMU_DUMMY_MAP(OPTIMIZED_VMIN),\
+   __SMU_DUMMY_MAP(CLOCK_POWER_DOWN_BYPASS),   \
+   __SMU_DUMMY_MAP(MEM_TEMP_READ), \
+   __SMU_DUMMY_MAP(ATHUB_MMHUB_PG),\
+   __SMU_DUMMY_MAP(BACO_CG),   \
+   __SMU_DUMMY_MAP(SOC_CG),

 #undef __SMU_DUMMY_MAP
 #define __SMU_DUMMY_MAP(feature)   SMU_FEATURE_##feature##_BIT
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 00964b3728fe..7c9e0ba7ab50 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -131,14 +131,56 @@ static struct cmn2asic_mapping 
smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {
 };

 static struct cmn2asic_mapping smu_v13_0_7_feature_mask_map[SMU_FEATURE_COUNT] 
= {
-   [SMU_FEATURE_DPM_GFXCLK_BIT] = {1, FEATURE_DPM_GFXCLK_BIT},
-   [SMU_FEATURE_DPM_UCLK_BIT] = {1, FEATURE_DPM_UCLK_BIT},
-   [SMU_FEATURE_DPM_FCLK_BIT] = {1, FEATURE_DPM_FCLK_BIT},
-   [SMU_FEATURE_DPM_SOCCLK_BIT] = {1, FEATURE_DPM_SOCCLK_BIT},
-   [SMU_FEATURE_DPM_LINK_BIT] = {1, FEATURE_DPM_LINK_BIT},
-   [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
-   [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
-   [SMU_FEATURE_FAN_CONTROL_BIT] = {1, FEATURE_FAN_CONTROL_BIT},
+   FEA_MAP(FW_DATA_READ),
+   FEA_MAP(DPM_GFXCLK),
+   FEA_MAP(DPM_GFX_POWER_OPTIMIZER),
+   FEA_MAP(DPM_UCLK),
+   FEA_MAP(DPM_FCLK),
+   FEA_MAP(DPM_SOCCLK),
+   FEA_MAP(DPM_MP0CLK),
+   FEA_MAP(DPM_LINK),
+   FEA_MAP(DPM_DCN),
+   FEA_MAP(VMEMP_SCALING),
+   FEA_MAP(VDDIO_MEM_SCALING),
+   FEA_MAP(DS_GFXCLK),
+   FEA_MAP(DS_SOCCLK),
+   FEA_MAP(DS_FCLK),
+   FEA_MAP(DS_LCLK),
+   FEA_MAP(DS_DCFCLK),
+   FEA_MAP(DS_UCLK),
+   FEA_MAP(GFX_ULV),
+   FEA_MAP(FW_DSTATE),
+   FEA_MAP(GFXOFF),
+   FEA_MAP(BACO),
+   FEA_MAP(MM_DPM),
+   FEA_MAP(SOC_MPCLK_DS),
+   FEA_MAP(BACO_MPCLK_DS),
+   FEA_MAP(THROTTLERS),
+   FEA_MAP(SMARTSHIFT),
+   FEA_MAP(GTHR),
+   FEA_MAP(ACDC),
+   FEA_MAP(VR0HOT),
+   FEA_MAP(FW_CTF),
+   FEA_MAP(FAN_CONTROL),
+   FEA_MAP(GFX_DCS),
+   FEA_MAP(GFX_READ_MARGIN),
+   FEA_MAP(LED_DISPLAY),
+   FEA_MAP(GFXCLK_SPREAD_SPECTRUM),
+   FEA_MAP(OUT_OF_BAND_MONITOR),
+   FEA_MAP(OPTIMIZED_VMIN),
+   FEA_MAP(GFX_IMU),
+   FEA_MAP(BOOT_TIME_CAL),
+   FEA_MAP(GFX_PCC_DFLL),
+   FEA_MAP(SOC_CG),
+   FEA_MAP(DF_CSTATE),
+   FEA_MAP(GFX_EDC),
+   FEA_MAP(BOOT_POWER_OPT),
+   FEA_MAP(CLOCK_POWER_DOWN_BYPASS),
+   FEA_MAP(DS_VCN),
+   FEA_MAP(BACO_CG),
+   FEA_MAP(MEM_TEMP_READ),
+   FEA_MAP(ATHUB_MMHUB_PG),
+   

答复: [PATCH] drm/amd/pm: add smu power_limit callback for smu_v13_0_7

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng mailto:kenneth.f...@amd.com>>

Best wishes
Kenneth Feng


发件人: amd-gfx  代表 Yang Wang 

日期: 星期三, 2022年5月11日 15:01
收件人: amd-gfx@lists.freedesktop.org 
抄送: Wang, Yang(Kevin) 
主题: [PATCH] drm/amd/pm: add smu power_limit callback for smu_v13_0_7
[CAUTION: External Email]

- get_power_limit
- set_power_limit

add above callback functions to enable power_cap hwmon node.

Signed-off-by: Yang Wang 
---
 .../drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c  | 39 +++
 1 file changed, 39 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 7c9e0ba7ab50..4e1861fb2c6a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1367,6 +1367,43 @@ static int smu_v13_0_7_enable_mgpu_fan_boost(struct 
smu_context *smu)
   NULL);
 }

+static int smu_v13_0_7_get_power_limit(struct smu_context *smu,
+  uint32_t *current_power_limit,
+  uint32_t *default_power_limit,
+  uint32_t *max_power_limit)
+{
+   struct smu_table_context *table_context = >smu_table;
+   struct smu_13_0_7_powerplay_table *powerplay_table =
+   (struct smu_13_0_7_powerplay_table 
*)table_context->power_play_table;
+   PPTable_t *pptable = table_context->driver_pptable;
+   SkuTable_t *skutable = >SkuTable;
+   uint32_t power_limit, od_percent;
+
+   if (smu_v13_0_get_current_power_limit(smu, _limit))
+   power_limit = smu->adev->pm.ac_power ?
+ skutable->SocketPowerLimitAc[PPT_THROTTLER_PPT0] :
+ skutable->SocketPowerLimitDc[PPT_THROTTLER_PPT0];
+
+   if (current_power_limit)
+   *current_power_limit = power_limit;
+   if (default_power_limit)
+   *default_power_limit = power_limit;
+
+   if (max_power_limit) {
+   if (smu->od_enabled) {
+   od_percent = 
le32_to_cpu(powerplay_table->overdrive_table.max[SMU_13_0_7_ODSETTING_POWERPERCENTAGE]);
+
+   dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d 
(default: %d)\n", od_percent, power_limit);
+
+   power_limit *= (100 + od_percent);
+   power_limit /= 100;
+   }
+   *max_power_limit = power_limit;
+   }
+
+   return 0;
+}
+
 static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char 
*buf)
 {
DpmActivityMonitorCoeffIntExternal_t 
activity_monitor_external[PP_SMC_POWER_PROFILE_COUNT];
@@ -1539,6 +1576,8 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = 
{
.get_fan_control_mode = smu_v13_0_get_fan_control_mode,
.set_fan_control_mode = smu_v13_0_set_fan_control_mode,
.enable_mgpu_fan_boost = smu_v13_0_7_enable_mgpu_fan_boost,
+   .get_power_limit = smu_v13_0_7_get_power_limit,
+   .set_power_limit = smu_v13_0_set_power_limit,
.get_power_profile_mode = smu_v13_0_7_get_power_profile_mode,
.set_power_profile_mode = smu_v13_0_7_set_power_profile_mode,
.set_tool_table_location = smu_v13_0_set_tool_table_location,
--
2.25.1

答复: [PATCH] drm/amd/pm: add smu pp_feature_mask callback for smu_v13_0_7

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng mailto:kenneth.f...@amd.com>>

Best wishes
Kenneth Feng


发件人: amd-gfx  代表 Yang Wang 

日期: 星期三, 2022年5月11日 02:01
收件人: amd-gfx@lists.freedesktop.org 
抄送: Wang, Yang(Kevin) 
主题: [PATCH] drm/amd/pm: add smu pp_feature_mask callback for smu_v13_0_7
[CAUTION: External Email]

- set_pp_feature_mask
- get_pp_feature_mask

the pp_feature device node isn't working when
above callback functions aren't provided.

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 583a96784558..00964b3728fe 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1500,6 +1500,8 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = 
{
.get_power_profile_mode = smu_v13_0_7_get_power_profile_mode,
.set_power_profile_mode = smu_v13_0_7_set_power_profile_mode,
.set_tool_table_location = smu_v13_0_set_tool_table_location,
+   .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
+   .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
 };

 void smu_v13_0_7_set_ppt_funcs(struct smu_context *smu)
--
2.25.1

答复: [PATCH] drm/amdgpu: make smu_v13_0_7_check_fw_status() static

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng mailto:kenneth.f...@amd.com>>

Best wishes
Kenneth Feng


发件人: amd-gfx  代表 Alex Deucher 

日期: 星期五, 2022年5月6日 22:33
收件人: amd-gfx@lists.freedesktop.org 
抄送: Deucher, Alexander , kernel test robot 

主题: [PATCH] drm/amdgpu: make smu_v13_0_7_check_fw_status() static
[CAUTION: External Email]

It's not used outside of the this file.

Reported-by: kernel test robot 
Signed-off-by: Alex Deucher 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index cf5800822174..9949ee3ae090 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -291,7 +291,7 @@ static int smu_v13_0_7_store_powerplay_table(struct 
smu_context *smu)
return 0;
 }

-int smu_v13_0_7_check_fw_status(struct smu_context *smu) {
+static int smu_v13_0_7_check_fw_status(struct smu_context *smu) {
struct amdgpu_device *adev = smu->adev;
uint32_t mp1_fw_flags;

--
2.35.1

答复: [PATCH] drm/amdgpu: use proper index in smu_v13_0_7_get_power_profile_mode()

[Feng, Kenneth]

[AMD Official Use Only - General]

Reviewed-by: Kenneth Feng mailto:kenneth.f...@amd.com>>

Best wishes
Kenneth Feng


发件人: Deucher, Alexander 
日期: 星期五, 2022年5月6日 22:07
收件人: amd-gfx@lists.freedesktop.org 
抄送: Deucher, Alexander , Feng, Kenneth 
, Stephen Rothwell 
主题: [PATCH] drm/amdgpu: use proper index in smu_v13_0_7_get_power_profile_mode()
Otherwise we get an out of bounds access.

Fixes: 878205b8c170 ("drm/amd/pm: enable workload type change on smu_v13_0_7")
Signed-off-by: Alex Deucher 
Cc: Kenneth Feng 
Cc: Stephen Rothwell 
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 8e576054bee5..cf5800822174 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1361,7 +1361,7 @@ static int smu_v13_0_7_get_power_profile_mode(struct 
smu_context *smu, char *buf
 do {   
 \
 size += sysfs_emit_at(buf, size, "%-30s", #field); 
 \
 for (j = 0; j <= PP_SMC_POWER_PROFILE_WINDOW3D; j++)   
 \
-   size += sysfs_emit_at(buf, size, "%-16d", 
activity_monitor_external[i].DpmActivityMonitorCoeffInt.field);   \
+   size += sysfs_emit_at(buf, size, "%-16d", 
activity_monitor_external[j].DpmActivityMonitorCoeffInt.field);   \
 size += sysfs_emit_at(buf, size, "\n");
 \
 } while (0)

--
2.35.1

RE: [PATCH] drm/amd/pm: fix hwmon node of power1_label create issue

[Feng, Kenneth]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Wang, Yang(Kevin)  
Sent: Tuesday, February 8, 2022 2:35 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Lazar, Lijo ; 
Hou, Xiaomeng (Matthew) ; Wang, Yang(Kevin) 

Subject: [PATCH] drm/amd/pm: fix hwmon node of power1_label create issue

fix typo issue about "power1_label",
it will cause hwmon node of power1_label is not created.

Fixes: ae07970a06 ("drm/amd/pm: add support for hwmon control of slow and fast 
PPT limit on vangogh")

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index d68e7132da2c..d6c01c59f32e 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -3288,7 +3288,7 @@ static umode_t hwmon_attributes_visible(struct kobject 
*kobj,
 attr == _dev_attr_power2_cap.dev_attr.attr ||
 attr == _dev_attr_power2_cap_default.dev_attr.attr ||
 attr == _dev_attr_power2_label.dev_attr.attr ||
-attr == _dev_attr_power1_label.dev_attr.attr))
+attr == _dev_attr_power2_label.dev_attr.attr))
return 0;
 
return effective_mode;
-- 
2.25.1

RE: [PATCH] drm/amd/pm: disable GetPptLimit message in sriov mode

[Feng, Kenneth]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Wang, Yang(Kevin)  
Sent: Tuesday, February 8, 2022 12:30 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Lazar, Lijo ; 
Nikolic, Marina ; Wang, Yang(Kevin) 

Subject: [PATCH] drm/amd/pm: disable GetPptLimit message in sriov mode

the pmfw is not allowed GetPptLimit message in virtualzation mode.

Fixes: 3e4a01689daa ("drm/amd/pm: Enable sysfs required by rocm-smi toolfor One 
VF mode")

Signed-off-by: Yang Wang 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 804e1c98238d..2a7da2bad96a 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -140,7 +140,7 @@ static struct cmn2asic_msg_mapping 
sienna_cichlid_message_map[SMU_MSG_MAX_COUNT]
MSG_MAP(PrepareMp1ForUnload,PPSMC_MSG_PrepareMp1ForUnload,  
   1),
MSG_MAP(AllowGfxOff,PPSMC_MSG_AllowGfxOff,  
   0),
MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff,   
   0),
-   MSG_MAP(GetPptLimit,PPSMC_MSG_GetPptLimit,  
   1),
+   MSG_MAP(GetPptLimit,PPSMC_MSG_GetPptLimit,  
   0),
MSG_MAP(GetDcModeMaxDpmFreq,PPSMC_MSG_GetDcModeMaxDpmFreq,  
   1),
MSG_MAP(ExitBaco,   PPSMC_MSG_ExitBaco, 
   0),
MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn,   
   0),
-- 
2.25.1

RE: Voltage control on Southern Island GPU using radeon

[Feng, Kenneth]

[AMD Official Use Only]

Hi Evans,
I think you can refer to the code in r600_parse_clk_voltage_dep_table.
And print the value in radeon_table->entries[i].clk(sclk in each level), then 
override it to a lower value.
Thanks.


From: Feng, Kenneth
Sent: Tuesday, August 24, 2021 8:26 AM
To: Evans Jahja ; amd-gfx@lists.freedesktop.org
Subject: RE: Voltage control on Southern Island GPU using radeon


[AMD Official Use Only]

Got it, Evans.
Since HAINAN is very different, need some further confirmation.
Thanks.


From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of Evans Jahja
Sent: Monday, August 23, 2021 6:40 PM
To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
Subject: RE: Voltage control on Southern Island GPU using radeon

[CAUTION: External Email]
Hi Kenneth,

I understand that changing voltage 'standalone' is not a good idea. In that 
case, would it be possible to change the voltage table so that it would give a 
lower clock on certain voltage?

For example, I would like to change

sclk 900, vddc: 1050

to

sclk 800, vddc: 1050

Thanks

On Mon, Aug 23, 2021, 14:59 
mailto:amd-gfx-requ...@lists.freedesktop.org>>
 wrote:
Send amd-gfx mailing list submissions to
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Today's Topics:

   1. RE: Voltage control on Southern Island GPU using radeon
  driver (Feng, Kenneth)
   2. RE: [PATCH] drm/amdgpu: add missing cleanups for Polaris12
  UVD/VCE on suspend (Quan, Evan)


--

Message: 1
Date: Mon, 23 Aug 2021 07:11:10 +
From: "Feng, Kenneth" mailto:kenneth.f...@amd.com>>
To: "Koenig, Christian" 
mailto:christian.koe...@amd.com>>, Evans Jahja
mailto:evansjahj...@gmail.com>>, 
"amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>"
mailto:amd-gfx@lists.freedesktop.org>>
Subject: RE: Voltage control on Southern Island GPU using radeon
driver
Message-ID:

mailto:by5pr12mb55607f9193f1a315210d1b838e...@by5pr12mb5560.namprd12.prod.outlook.com>>

Content-Type: text/plain; charset="utf-8"

[AMD Official Use Only]

Hi Evans
I'm sorry but I don't suggest you manually control the standalone voltage 
because it's predefined with the clock value.
A decrease of voltage could hit the hardware critical path. You may need to 
change the clock and voltage together, we call it dpm level change.
Thanks.


-Original Message-
From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of Christian K?nig
Sent: Monday, August 23, 2021 2:26 PM
To: Evans Jahja mailto:evansjahj...@gmail.com>>; 
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
Subject: Re: Voltage control on Southern Island GPU using radeon driver

[CAUTION: External Email]

Hi Evans,

in general the voltage tables are stored in the atombios and the best advice I 
can give you is to first double check if there isn't an updated BIOS for your 
hardware.

But Alex is the expert on power management, especially for those older hardware 
generations. Maybe he has another idea what to try.

Regards,
Christian.

Am 23.08.21 um 03:56 schrieb Evans Jahja:
> Hi, I have a HAINAN GPU below:
>
> lspci -nn
> 0a:00.0 Display controller [0380]: Advanced Micro Devices, Inc.
> [AMD/ATI] Sun LE [Radeon HD 8550M / R5 M230] [1002:666f]
>
> I run linux 5.13.12 on Arch on a Lenovo B40-70 laptop.
>
> I'm trying to understand more on how voltage control works and how I
> can modify the voltage for doing overvoltage / undervoltage on my GPU.
> The reason is I am observing how running programs under high GPU load
> (glmark2) would lead to crashes when I use dpm=1 in either radeon or
> amdgpu driver, which seems to happen when I am reaching power level 4
> (sclk 900MHz), while a lighter program like glxgears could run and
> 

RE: Voltage control on Southern Island GPU using radeon

[Feng, Kenneth]

[AMD Official Use Only]

Got it, Evans.
Since HAINAN is very different, need some further confirmation.
Thanks.


From: amd-gfx  On Behalf Of Evans Jahja
Sent: Monday, August 23, 2021 6:40 PM
To: amd-gfx@lists.freedesktop.org
Subject: RE: Voltage control on Southern Island GPU using radeon

[CAUTION: External Email]
Hi Kenneth,

I understand that changing voltage 'standalone' is not a good idea. In that 
case, would it be possible to change the voltage table so that it would give a 
lower clock on certain voltage?

For example, I would like to change

sclk 900, vddc: 1050

to

sclk 800, vddc: 1050

Thanks

On Mon, Aug 23, 2021, 14:59 
mailto:amd-gfx-requ...@lists.freedesktop.org>>
 wrote:
Send amd-gfx mailing list submissions to
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>

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or, via email, send a message with subject or body 'help' to

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When replying, please edit your Subject line so it is more specific
than "Re: Contents of amd-gfx digest..."


Today's Topics:

   1. RE: Voltage control on Southern Island GPU using radeon
  driver (Feng, Kenneth)
   2. RE: [PATCH] drm/amdgpu: add missing cleanups for Polaris12
  UVD/VCE on suspend (Quan, Evan)


--

Message: 1
Date: Mon, 23 Aug 2021 07:11:10 +
From: "Feng, Kenneth" mailto:kenneth.f...@amd.com>>
To: "Koenig, Christian" 
mailto:christian.koe...@amd.com>>, Evans Jahja
mailto:evansjahj...@gmail.com>>, 
"amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>"
mailto:amd-gfx@lists.freedesktop.org>>
Subject: RE: Voltage control on Southern Island GPU using radeon
driver
Message-ID:

mailto:by5pr12mb55607f9193f1a315210d1b838e...@by5pr12mb5560.namprd12.prod.outlook.com>>

Content-Type: text/plain; charset="utf-8"

[AMD Official Use Only]

Hi Evans
I'm sorry but I don't suggest you manually control the standalone voltage 
because it's predefined with the clock value.
A decrease of voltage could hit the hardware critical path. You may need to 
change the clock and voltage together, we call it dpm level change.
Thanks.


-Original Message-
From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of Christian K?nig
Sent: Monday, August 23, 2021 2:26 PM
To: Evans Jahja mailto:evansjahj...@gmail.com>>; 
amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
Subject: Re: Voltage control on Southern Island GPU using radeon driver

[CAUTION: External Email]

Hi Evans,

in general the voltage tables are stored in the atombios and the best advice I 
can give you is to first double check if there isn't an updated BIOS for your 
hardware.

But Alex is the expert on power management, especially for those older hardware 
generations. Maybe he has another idea what to try.

Regards,
Christian.

Am 23.08.21 um 03:56 schrieb Evans Jahja:
> Hi, I have a HAINAN GPU below:
>
> lspci -nn
> 0a:00.0 Display controller [0380]: Advanced Micro Devices, Inc.
> [AMD/ATI] Sun LE [Radeon HD 8550M / R5 M230] [1002:666f]
>
> I run linux 5.13.12 on Arch on a Lenovo B40-70 laptop.
>
> I'm trying to understand more on how voltage control works and how I
> can modify the voltage for doing overvoltage / undervoltage on my GPU.
> The reason is I am observing how running programs under high GPU load
> (glmark2) would lead to crashes when I use dpm=1 in either radeon or
> amdgpu driver, which seems to happen when I am reaching power level 4
> (sclk 900MHz), while a lighter program like glxgears could run and
> switch power levels  between 0,1,2 without issue under both drivers. I
> believe my laptop might be faulty, but I would like to take this
> opportunity to try fixing it from the driver's side so that it can run
> anyway, however limited.
>
> Right now, I have managed to increase the performance of my GPU by
> manually overwriting the sclk to 630MHz in all performance_levels in
> radeon_pm.c, which surprises me as overriding the clock was not
> possible for me to do pre

RE: Voltage control on Southern Island GPU using radeon driver

[Feng, Kenneth]

[AMD Official Use Only]

Hi Evans
I'm sorry but I don't suggest you manually control the standalone voltage 
because it's predefined with the clock value.
A decrease of voltage could hit the hardware critical path. You may need to 
change the clock and voltage together, we call it dpm level change.
Thanks.
 

-Original Message-
From: amd-gfx  On Behalf Of Christian 
König
Sent: Monday, August 23, 2021 2:26 PM
To: Evans Jahja ; amd-gfx@lists.freedesktop.org
Subject: Re: Voltage control on Southern Island GPU using radeon driver

[CAUTION: External Email]

Hi Evans,

in general the voltage tables are stored in the atombios and the best advice I 
can give you is to first double check if there isn't an updated BIOS for your 
hardware.

But Alex is the expert on power management, especially for those older hardware 
generations. Maybe he has another idea what to try.

Regards,
Christian.

Am 23.08.21 um 03:56 schrieb Evans Jahja:
> Hi, I have a HAINAN GPU below:
>
> lspci -nn
> 0a:00.0 Display controller [0380]: Advanced Micro Devices, Inc.
> [AMD/ATI] Sun LE [Radeon HD 8550M / R5 M230] [1002:666f]
>
> I run linux 5.13.12 on Arch on a Lenovo B40-70 laptop.
>
> I'm trying to understand more on how voltage control works and how I 
> can modify the voltage for doing overvoltage / undervoltage on my GPU.
> The reason is I am observing how running programs under high GPU load
> (glmark2) would lead to crashes when I use dpm=1 in either radeon or 
> amdgpu driver, which seems to happen when I am reaching power level 4 
> (sclk 900MHz), while a lighter program like glxgears could run and 
> switch power levels  between 0,1,2 without issue under both drivers. I 
> believe my laptop might be faulty, but I would like to take this 
> opportunity to try fixing it from the driver's side so that it can run 
> anyway, however limited.
>
> Right now, I have managed to increase the performance of my GPU by 
> manually overwriting the sclk to 630MHz in all performance_levels in 
> radeon_pm.c, which surprises me as overriding the clock was not 
> possible for me to do previously via sysfs.
>
> I've managed to tweak both sclk and mclk (or so I believe), but I 
> still cannot tweak the voltage (vddc). The reason is, if I increase 
> the sclk to 650MHz, the lockup will happen again. Changing the
> pl->vddc  variable does not seem to do anything. After various tracing
> with printk, I understand that on my system:
>
> pi->voltage_control = radeon_atom_is_voltage_gpio(rdev,
> SET_VOLTAGE_TYPE_ASIC_VDDC,
>VOLTAGE_OBJ_GPIO_LUT)
>
> this returns false, while:
>
> si_pi->voltage_control_svi2 =
> radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC,
>VOLTAGE_OBJ_SVID2);
>
> This returns true, so I believe my system is using SVI2 somehow to set 
> the voltage. Having no experience with SVI2, I read online and found 
> out that SVI2 is a voltage regulator that uses Data / Clock pins to 
> clock-in 8 bits of information and convert it to some voltage value 
> between OFF, 0.5V -> 1.5V, offering fine control based on some look up 
> table.
>
> My questions are as follows:
> Is it possible for me to modify my system so that I can manually 
> adjust the voltage to my GPU?
>
> Thank you very much in advance. This is the first time I deal with 
> kernel drivers, so any guidance on the matter helps a lot.
>
> - Evans
>
>

RE: [PATCH] drm/amd/pm: correct MGpuFanBoost setting

[Feng, Kenneth]

[AMD Official Use Only]

Reviewed-by: Kenneth Feng 

-Original Message-
From: Quan, Evan  
Sent: Tuesday, May 18, 2021 10:05 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Feng, Kenneth 
; Quan, Evan 
Subject: [PATCH] drm/amd/pm: correct MGpuFanBoost setting

No MGpuFanBoost setting for those ASICs which do not support it.
Otherwise, it may breaks their fan control feature.

Change-Id: Ifa9c87ac537a07937a0f0f6a670f21368eb29218
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c|  9 +
 .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c| 10 ++
 2 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index d2063b1e7936..f16c76038f13 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -2936,6 +2936,8 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context 
*smu,
 
 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)  {
+   struct smu_table_context *table_context = >smu_table;
+   PPTable_t *smc_pptable = table_context->driver_pptable;
struct amdgpu_device *adev = smu->adev;
uint32_t param = 0;
 
@@ -2943,6 +2945,13 @@ static int navi10_enable_mgpu_fan_boost(struct 
smu_context *smu)
if (adev->asic_type == CHIP_NAVI12)
return 0;
 
+   /*
+* Skip the MGpuFanBoost setting for those ASICs
+* which do not support it
+*/
+   if (!smc_pptable->MGpuFanBoostLimitRpm)
+   return 0;
+
/* Workaround for WS SKU */
if (adev->pdev->device == 0x7312 &&
adev->pdev->revision == 0)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 3c3a7f9233e0..159cd698323e 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -3201,6 +3201,16 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct 
smu_context *smu,
 
 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)  {
+   struct smu_table_context *table_context = >smu_table;
+   PPTable_t *smc_pptable = table_context->driver_pptable;
+
+   /*
+* Skip the MGpuFanBoost setting for those ASICs
+* which do not support it
+*/
+   if (!smc_pptable->MGpuFanBoostLimitRpm)
+   return 0;
+
return smu_cmn_send_smc_msg_with_param(smu,
   SMU_MSG_SetMGpuFanBoostLimitRpm,
   0,
--
2.29.0
___
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RE: [PATCH 1/2] drm/amdgpu: update gc golden setting for Navi12

[Feng, Kenneth]

[AMD Official Use Only]

Series are Reviewed-by: Kenneth Feng 


-Original Message-
From: Chen, Guchun  
Sent: Tuesday, May 18, 2021 10:01 AM
To: amd-gfx@lists.freedesktop.org; Deucher, Alexander 
; Zhang, Hawking ; Feng, 
Kenneth ; Chen, Jiansong (Simon) ; 
Xiao, Jack ; Quan, Evan 
Cc: Chen, Guchun 
Subject: [PATCH 1/2] drm/amdgpu: update gc golden setting for Navi12

Current golden setting is out of date.

Signed-off-by: Guchun Chen 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 2a3427e5020f..7edd0c0eed8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1399,9 +1399,10 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x, 0x2000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x, 0x0420),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x, 0x0200),
-   SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0480),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x, 0x0490),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x, 
0x003f),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0x, 
0x03860204),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 
+0x0044),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0, 
0x0500),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x7fff, 
0x01fe),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x, 
0xe4e4e4e4), @@ -1419,12 +1420,13 @@ static const struct soc15_reg_golden 
golden_settings_gc_10_1_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x0820, 
0x0820),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0xff0f, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0x, 0x3101),
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f, 
+0x00070104),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0x, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x0133, 0x0130),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0x, 
0x),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7, 0x0103),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
-   SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x, 0x0080)
+   SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x, 0x00c0)
 };
 
 static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset, 
uint32_t *flag, bool write)
--
2.17.1
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RE: [PATCH v2 0/3] Prevent set of DCEFCLK on smu_v11 gpus

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Series are Reviewed-by: Kenneth Feng 


-Original Message-
From: Powell, Darren  
Sent: Friday, April 23, 2021 11:23 AM
To: amd-gfx@lists.freedesktop.org
Cc: Powell, Darren 
Subject: [PATCH v2 0/3] Prevent set of DCEFCLK on smu_v11 gpus

=== Description ===
Set of simple patches to prevent attempts to set dcefclk on NAVI10

=== Test System ===
* DESKTOP(AMD FX-8350 + NAVI10(731F/ca), BIOS: F2)  + ISO(Ubuntu 20.04.1 LTS)  
+ Kernel(5.11.0-custom-amdinternal-dirty)

=== Patch Summary ===
   linux: (g...@gitlab.freedesktop.org:agd5f) origin/amd-staging-drm-next @ 
b54280b32ebb
+ 599f1ebb60cc  amdgpu/pm: add extra info to SMU msg pre-check failed 
message
+ 291dcf836f45  amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and 
SIENNA_CICHLID
+ c8ce10fc1d99  amdgpu/pm: set pp_dpm_dcefclk to readonly on NAVI10 and 
newer gpus

=== Tests ===
General Test Sequence
-
* monitor dmesg output in a shell
  dmesg -w

* launch a root shell
  sudo bash

* set control to manual
  cd /sys/class/drm/card0/device
  echo manual > power_dpm_force_performance_level

* next step is expected to crash the GPU in unpatched and with patch 0001
** system usually continues operation so you can reboot gracefully

* TEST 1: modify pp_dpm_dcefclk to each level (0,1,2) and read setting after 
each write
  echo "1" > pp_dpm_dcefclk ; sleep 2 ; echo " ---set 1---" ; cat  
pp_dpm_dcefclk ;\
  echo "2" > pp_dpm_dcefclk ; sleep 2 ; echo " ---set 2---" ; cat  
pp_dpm_dcefclk ;\
  echo "0" > pp_dpm_dcefclk ; sleep 2 ; echo " ---set 0---" ; cat  
pp_dpm_dcefclk
** example output
  [   74.493190] amdgpu :03:00.0: amdgpu: failed send message: 
SetSoftMaxByFreq (27)  param: 0x000504f2 response 0xff
  [   76.497102] amdgpu :03:00.0: amdgpu: Msg issuing pre-check failed and 
SMU may be not in the right state!
  [   76.497114] amdgpu :03:00.0: amdgpu: Failed to export SMU metrics 
table!
  [   76.497649] amdgpu :03:00.0: amdgpu: Msg issuing pre-check failed and 
SMU may be not in the right state!
  [   78.501229] amdgpu :03:00.0: amdgpu: Msg issuing pre-check failed and 
SMU may be not in the right state!
  [   78.501241] amdgpu :03:00.0: amdgpu: Failed to export SMU metrics 
table!
  [   78.501766] amdgpu :03:00.0: amdgpu: Msg issuing pre-check failed and 
SMU may be not in the right state!
  [   80.505401] amdgpu :03:00.0: amdgpu: Msg issuing pre-check failed and 
SMU may be not in the right state!
  [   80.505414] amdgpu :03:00.0: amdgpu: Failed to export SMU metrics 
table!

* TEST 2:
   ls -la  /sys/class/drm/card0/device/pp_dpm_dcefclk
** example output
  -rw-r--r-- 1 root root 4096 Apr  7 18:33 
/sys/class/drm/card0/device/pp_dpm_dcefclk

* POST TEST
** restore dpm clock to auto
  echo auto > power_dpm_force_performance_level


Test Results

* 0001 amdgpu/pm: add extra info to SMU msg pre-check failed message
** TEST 1 dmesg output
  [  101.414826] amdgpu :03:00.0: amdgpu: failed send message: 
SetSoftMaxByFreq (27)param: 0x000504f2 response 0xff
  [  103.418916] amdgpu :03:00.0: amdgpu: Msg issuing pre-check 
failed(0xff) and SMU may be not in the right state!
  [  103.418930] amdgpu :03:00.0: amdgpu: Failed to export SMU metrics 
table!
  [  103.419474] amdgpu :03:00.0: amdgpu: Msg issuing pre-check 
failed(0xff) and SMU may be not in the right state!
  [  105.423226] amdgpu :03:00.0: amdgpu: Msg issuing pre-check 
failed(0xff) and SMU may be not in the right state!
  [  105.423239] amdgpu :03:00.0: amdgpu: Failed to export SMU metrics 
table!
  [  105.423649] amdgpu :03:00.0: amdgpu: Msg issuing pre-check 
failed(0xff) and SMU may be not in the right state!
  [  107.427502] amdgpu :03:00.0: amdgpu: Msg issuing pre-check 
failed(0xff) and SMU may be not in the right state!
  [  107.427516] amdgpu :03:00.0: amdgpu: Failed to export SMU metrics 
table!

* 0002  amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID
** GPU remains operational after test
** TEST 1 dmesg output
  [  263.087136] amdgpu :03:00.0: amdgpu: Setting DCEFCLK min/max dpm level 
is not supported!
  [  265.092026] amdgpu :03:00.0: amdgpu: Setting DCEFCLK min/max dpm level 
is not supported!
  [  267.096648] amdgpu :03:00.0: amdgpu: Setting DCEFCLK min/max dpm level 
is not supported!

* 0003  amdgpu/pm: set pp_dpm_dcefclk to readonly on smu_v11 gpus
** TEST 2 shell output
  bash: pp_dpm_dcefclk: Permission denied
   ---set 1---
  0: 506Mhz *
  1: 886Mhz 
  2: 1266Mhz 
  bash: pp_dpm_dcefclk: Permission denied
   ---set 2---
  0: 506Mhz *
  1: 886Mhz 
  2: 1266Mhz 
  bash: pp_dpm_dcefclk: Permission denied
   ---set 0---
  0: 506Mhz *
  1: 886Mhz 
  2: 1266Mhz 

Darren Powell (3):
  amdgpu/pm: add extra info to SMU msg pre-check failed message
  amdgpu/pm: Prevent force of DCEFCLK on NAVI10 and SIENNA_CICHLID
  amdgpu/pm: set pp_dpm_dcefclk to readonly on NAVI10 and newer gpus

RE: [PATCH 3/3] amdgpu/pm: set pp_dpm_dcefclk to readonly on smu_v11 gpus

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Hi Darren,
It would be better if the condition is " asic_type >=CHIP_NAVI10".
We assume that from navi10, this restriction is on all.
With this change, the patch is Reviewed-by: Kenneth Feng 
Thanks.


-Original Message-
From: Powell, Darren  
Sent: Saturday, April 17, 2021 6:30 AM
To: amd-gfx@lists.freedesktop.org
Cc: Powell, Darren 
Subject: [PATCH 3/3] amdgpu/pm: set pp_dpm_dcefclk to readonly on smu_v11 gpus

Writing to dcefclk causes the gpu to become unresponsive, and requires a reboot.
Patch prevents user from successfully writing to file pp_dpm_dcefclk on 
smu_vv11 parts and gives better user feedback that this operation is not 
allowed.

Signed-off-by: Darren Powell 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 204e34549013..317e9b47db53 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1891,6 +1891,19 @@ static int default_attr_update(struct amdgpu_device 
*adev, struct amdgpu_device_
}
}
 
+   if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
+   /* SMU MP1 does not support dcefclk level setting */
+   if (asic_type == CHIP_NAVI10  ||
+   asic_type == CHIP_NAVI14  ||
+   asic_type == CHIP_NAVI12  ||
+   asic_type == CHIP_SIENNA_CICHLID  ||
+   asic_type == CHIP_NAVY_FLOUNDER   ||
+   asic_type == CHIP_DIMGREY_CAVEFISH  ) {
+   dev_attr->attr.mode &= ~S_IWUGO;
+   dev_attr->store = NULL;
+   }
+   }
+
 #undef DEVICE_ATTR_IS
 
return 0;
--
2.25.1
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RE: [PATCH] drm/amd/pm: enable ASPM on navi1x

[Feng, Kenneth]

[AMD Public Use]

Thanks. I will remove the comments.


-Original Message-
From: Chen, Guchun  
Sent: Thursday, April 8, 2021 5:55 PM
To: Feng, Kenneth ; amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth 
Subject: RE: [PATCH] drm/amd/pm: enable ASPM on navi1x

[AMD Public Use]

* The ASPM function is not fully enabled and verified on
 * Navi yet. Temporarily skip this until ASPM enabled.
 */

The comments needs to be adjusted as well?

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of Kenneth Feng
Sent: Thursday, April 8, 2021 5:33 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth 
Subject: [PATCH] drm/amd/pm: enable ASPM on navi1x

ASPM can be verified funtionally on navi1x.
And can be enabled for the benefit of the power consumption without the 
performance hurt.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/amdgpu/nv.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c 
index 46d4bbabce75..5edab56c6ab0 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -601,8 +601,7 @@ static void nv_program_aspm(struct amdgpu_device *adev)
if (amdgpu_aspm != 1)
return;
 
-   if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
-   !(adev->flags & AMD_IS_APU) &&
+   if (!(adev->flags & AMD_IS_APU) &&
(adev->nbio.funcs->program_aspm))
adev->nbio.funcs->program_aspm(adev);
 
@@ -938,8 +937,7 @@ static int nv_update_umd_stable_pstate(struct amdgpu_device 
*adev,
 * The ASPM function is not fully enabled and verified on
 * Navi yet. Temporarily skip this until ASPM enabled.
 */
-   if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
-   !(adev->flags & AMD_IS_APU) &&
+   if (!(adev->flags & AMD_IS_APU) &&
(adev->nbio.funcs->enable_aspm))
adev->nbio.funcs->enable_aspm(adev, !enter);
 
--
2.17.1

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RE: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Bindu 
Ramamurthy
Sent: Wednesday, March 17, 2021 7:50 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lakha, Bhawanpreet 
; Zhou1, Tao ; Feng, Kenneth 
; R, Bindu 
Subject: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

[CAUTION: External Email]

[Why]
idle optimization was being disabled after commit.

[How]
check vblank count for display off and enable idle optimization based on this 
count.

Signed-off-by: Bindu Ramamurthy 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 553e39f9538c..56a55143ad2d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -987,7 +987,7 @@ static void event_mall_stutter(struct work_struct *work)

if (vblank_work->enable)
dm->active_vblank_irq_count++;
-   else
+   else if(dm->active_vblank_irq_count)
dm->active_vblank_irq_count--;

dc_allow_idle_optimizations(
@@ -8694,7 +8694,10 @@ static void amdgpu_dm_atomic_commit_tail(struct 
drm_atomic_state *state)
WARN_ON(!dc_commit_state(dm->dc, dc_state));
mutex_unlock(>dc_lock);
}
-
+/* Allow idle optimization when vblank count is 0 for display off */
+if (dm->active_vblank_irq_count == 0)
+   dc_allow_idle_optimizations(dm->dc,true);
+
for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

--
2.25.1

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RE: [PATCH] drm/amdgpu: correct TA RAP firmware information print error

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Kevin Wang
Sent: Monday, March 1, 2021 10:52 AM
To: amd-gfx@lists.freedesktop.org
Cc: Li, Candice ; Wang, Kevin(Yang) 
Subject: [PATCH] drm/amdgpu: correct TA RAP firmware information print error

[CAUTION: External Email]

miss RAP TA in loop ( when i == 4)

Fix:
drm/amdgpu: add RAP TA version print in amdgpu_firmware_info

Signed-off-by: Kevin Wang 
Reported-by: Candice Li 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index a5ed9530f542..6c8ea9d26320 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -1472,7 +1472,7 @@ static int amdgpu_debugfs_firmware_info_show(struct 
seq_file *m, void *unused)
   fw_info.feature, fw_info.ver);

query_fw.fw_type = AMDGPU_INFO_FW_TA;
-   for (i = 0; i < 4; i++) {
+   for (i = 0; i < 5; i++) {
query_fw.index = i;
ret = amdgpu_firmware_info(_info, _fw, adev);
if (ret)
--
2.17.1

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RE: [PATCH] drm/amd/pm: enable LCLK DS

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Yeah, the condition check is better.
Thanks.


-Original Message-
From: Quan, Evan  
Sent: Sunday, February 7, 2021 10:53 AM
To: Feng, Kenneth ; amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth 
Subject: RE: [PATCH] drm/amd/pm: enable LCLK DS

[AMD Official Use Only - Internal Distribution Only]

Do you mean ASPM is the prerequisite for LCLK DS feature?
Then do we need something as below?
If (aspm = 1)
ppfeaturesmask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);

BR
Evan
-Original Message-
From: amd-gfx  On Behalf Of Kenneth Feng
Sent: Sunday, February 7, 2021 9:54 AM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth 
Subject: [PATCH] drm/amd/pm: enable LCLK DS

Enable LCLK deep sleep and it works if we enable ASPM:
modprobe amdgpu aspm=1

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index b9e47f3b0231..d208a434c7cc 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -242,6 +242,7 @@ sienna_cichlid_get_allowed_feature_mask(struct smu_context 
*smu,  | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
+| FEATURE_MASK(FEATURE_DS_LCLK_BIT)
 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
--
2.17.1

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RE: [PATCH] drm/amd/pm: Enable gfx DCS feature

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,
Yes, SMU acts differently with regard to DCS when we set different workloads 
via the workload interface.
The mapping is as below.
Default, power saving, video, custom -> DCS is disabled in SMU firmware 
internally though it's enabled from driver.
3D fullscreen, VR -> FA DCS
Compute -> Async DCS

-Original Message-
From: Alex Deucher  
Sent: Thursday, January 28, 2021 1:49 AM
To: Feng, Kenneth 
Cc: amd-gfx list ; Zhou1, Tao 
Subject: Re: [PATCH] drm/amd/pm: Enable gfx DCS feature

[CAUTION: External Email]

On Wed, Jan 27, 2021 at 12:57 AM Feng, Kenneth  wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Alex,
> Actually the FA DCS is dependent on the workload type.
> FA DCS is applied only when there's 3D fullscreen workload or VR workload.
> So we need to disable it if there's a request from the sysfs/user to set the 
> workload type to 3D fullscreen or VR type because we don't have FA DCS so far.
> By removing this hunk is ok functionally, but the DCS will never kick in 
> though the DCS is enabled. That might be a little bit confusing.
> Thanks.

For clarity, does the SMU act differently with regard to DCS when you set 
different workloads via the workload interface or is this just using the 
assumption that at some point we might dynamically adjust the workload bits 
based on hints from userspace?

Alex


>
>
>
> -Original Message-
> From: Alex Deucher 
> Sent: Wednesday, January 27, 2021 12:55 PM
> To: Feng, Kenneth 
> Cc: amd-gfx list ; Zhou1, Tao 
> 
> Subject: Re: [PATCH] drm/amd/pm: Enable gfx DCS feature
>
> [CAUTION: External Email]
>
> On Tue, Jan 26, 2021 at 8:42 PM Kenneth Feng  wrote:
> >
> > Background:
> > Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
> > When the current/power/temperature exceeds the limit with the heavy 
> > workload, the gfx core can be shut off and powered on back and forth.
> > The ON time and OFF time is determined by the firmware according to 
> > the accumulated power credits.
> > This feature is different from gfxoff.Gfxoff is applied in the idle 
> > case and DCS is applied in the case with heavey workload.There are two 
> > types of DCS:
> > Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D 
> > fullscreen and VR workload.
> > Since we only supports Async DCS now,disalbe DCS when the 3D 
> > fullscreen or the VR workload type is chosen.
> >
> > Verification:
> > The power is lowerer or the perf/watt is increased in the throttling case.
> > To be simplified, the entry/exit counter can be observed from the firmware.
> >
> > Signed-off-by: Kenneth Feng 
> > ---
> >  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12
> > 
> >  1 file changed, 12 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > index 24f3c96a5e5e..436d94cbb166 100644
> > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > @@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct 
> > smu_context *smu,
> > *(uint64_t *)feature_mask |= 
> > FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
> > }
> >
> > +   if (adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type == 
> > CHIP_DIMGREY_CAVEFISH)
> > +   *(uint64_t *)feature_mask |= 
> > + FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> > +
> > if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
> > *(uint64_t *)feature_mask |= 
> > FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> > |
> > FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> > @@ -1437,6 +1440,15 @@ static int 
> > sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
> > smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
> > 1 << workload_type, NULL);
> >
> > +   /* have to disable dcs if it's the 3D fullscreen or VR workload 
> > type */
> > +   if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
> > +   smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
> > +   ret = smu_cmn_feature_set_enabled(smu, 
> > SMU_FEATURE_GFX_DCS_BIT, (workload_type ==
> > +   WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type 
> > == WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
> > +   if (ret)
> > +   

RE: [PATCH] drm/amd/pm: Enable gfx DCS feature

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,
Actually the FA DCS is dependent on the workload type.
FA DCS is applied only when there's 3D fullscreen workload or VR workload.
So we need to disable it if there's a request from the sysfs/user to set the 
workload type to 3D fullscreen or VR type because we don't have FA DCS so far.
By removing this hunk is ok functionally, but the DCS will never kick in though 
the DCS is enabled. That might be a little bit confusing.
Thanks.
 


-Original Message-
From: Alex Deucher  
Sent: Wednesday, January 27, 2021 12:55 PM
To: Feng, Kenneth 
Cc: amd-gfx list ; Zhou1, Tao 
Subject: Re: [PATCH] drm/amd/pm: Enable gfx DCS feature

[CAUTION: External Email]

On Tue, Jan 26, 2021 at 8:42 PM Kenneth Feng  wrote:
>
> Background:
> Gfx Duty Cycle Scaling(DCS) is applied on the small power limit skus.
> When the current/power/temperature exceeds the limit with the heavy 
> workload, the gfx core can be shut off and powered on back and forth.
> The ON time and OFF time is determined by the firmware according to 
> the accumulated power credits.
> This feature is different from gfxoff.Gfxoff is applied in the idle 
> case and DCS is applied in the case with heavey workload.There are two types 
> of DCS:
> Async DCS and Frame-aligned DCS.Frame-aligned DCS is applied on 3D 
> fullscreen and VR workload.
> Since we only supports Async DCS now,disalbe DCS when the 3D 
> fullscreen or the VR workload type is chosen.
>
> Verification:
> The power is lowerer or the perf/watt is increased in the throttling case.
> To be simplified, the entry/exit counter can be observed from the firmware.
>
> Signed-off-by: Kenneth Feng 
> ---
>  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c  | 12 
> 
>  1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 24f3c96a5e5e..436d94cbb166 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -261,6 +261,9 @@ sienna_cichlid_get_allowed_feature_mask(struct 
> smu_context *smu,
> *(uint64_t *)feature_mask |= 
> FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
> }
>
> +   if (adev->asic_type == CHIP_NAVY_FLOUNDER || adev->asic_type == 
> CHIP_DIMGREY_CAVEFISH)
> +   *(uint64_t *)feature_mask |= 
> + FEATURE_MASK(FEATURE_GFX_DCS_BIT);
> +
> if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
> *(uint64_t *)feature_mask |= 
> FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
> | 
> FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
> @@ -1437,6 +1440,15 @@ static int 
> sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *
> smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
> 1 << workload_type, NULL);
>
> +   /* have to disable dcs if it's the 3D fullscreen or VR workload type 
> */
> +   if (smu->adev->asic_type == CHIP_NAVY_FLOUNDER ||
> +   smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) {
> +   ret = smu_cmn_feature_set_enabled(smu, 
> SMU_FEATURE_GFX_DCS_BIT, (workload_type ==
> +   WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT || workload_type == 
> WORKLOAD_PPLIB_VR_BIT) ? 0 : 1);
> +   if (ret)
> +   return ret;
> +   }
> +

Since we don't support FA DCS yet, should we just drop this hunk for now?  I 
think the workload profile stuff should be independent of FA DCS.  Also so we 
want to add a ppfeaturemask flag to easily allow us to disable this at driver 
load time?

Alex


> return ret;
>  }
>
> --
> 2.17.1
>
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RE: [PATCH] drm/amd/pm: fix the return value of pm message

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

This can fix the problem of the below commit.
But I'm not sure what is the real purpose of the below commit. Or can we revert 
it?
Thanks.
commit 72a33b4b7433780df5334f9cfb23ff51669431a0
Author: Huang Rui 
Date:   Fri Jan 8 16:27:15 2021 +0800

drm/amd/pm: enhance the real response for smu message (v2)

The user prefers to know the real response value from C2PMSG 90 register
which is written by firmware not -EIO.

v2: return C2PMSG 90 value

Signed-off-by: Huang Rui 
Reviewed-by: Evan Quan 

Best Regards
Kenneth

-Original Message-
From: amd-gfx  On Behalf Of Huang Rui
Sent: Tuesday, January 12, 2021 6:25 PM
To: amd-gfx@lists.freedesktop.org
Cc: Du, Xiaojian ; Huang, Ray ; Liu, 
Aaron ; Hou, Xiaomeng (Matthew) ; 
Deucher, Alexander ; Quan, Evan 
Subject: [PATCH] drm/amd/pm: fix the return value of pm message

[CAUTION: External Email]

0 should be right driver return value, 0x1 is the right firmware return value. 
So switch to 0 at last.

Signed-off-by: Huang Rui 
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index d7d86fd79e1f..41d5c65a2f21 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -149,6 +149,7 @@ int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
if (read_arg)
smu_cmn_read_arg(smu, read_arg);

+   ret = 0; /* 0 as driver return value */
 out:
mutex_unlock(>message_lock);
return ret;
--
2.25.1

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RE: [PATCH 2/3] drm/amdgpu: Correct the read sclk for navi10

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Hello Emily,
The average clock value is a little different from the 'current clock' value.
May I know what's the purpose of this patch to display the average clock? Any 
issue or any customer requirement?
Thanks.


Best Regards
Kenneth

-Original Message-
From: amd-gfx  On Behalf Of Emily.Deng
Sent: Wednesday, January 6, 2021 9:05 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily 
Subject: [PATCH 2/3] drm/amdgpu: Correct the read sclk for navi10

[CAUTION: External Email]

According to hw, after navi10,it runs in dfll mode, and should read sclk from 
AverageGfxclkFrequency.

Signed-off-by: Emily.Deng 
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
index 51e83123f72a..7ebf9588983f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
@@ -1673,7 +1673,7 @@ static int navi10_read_sensor(struct smu_context *smu,
*size = 4;
break;
case AMDGPU_PP_SENSOR_GFX_SCLK:
-   ret = navi10_get_current_clk_freq_by_table(smu, SMU_GFXCLK, 
(uint32_t *)data);
+   ret = navi10_get_smu_metrics_data(smu, 
+ METRICS_AVERAGE_GFXCLK, (uint32_t *)data);
*(uint32_t *)data *= 100;
*size = 4;
break;
--
2.25.1

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RE: [PATCH 2/2] drm/amd/display: enable idle optimizations for linux (MALL stutter)

[Feng, Kenneth]

[AMD Public Use]


[AMD Public Use]

Hi Bhawanpreet,
With the two patches, I still can't see that dc_allow_idle_optimizations(struct 
dc *dc, bool allow) is called with allow = true after modprobe and startx.
Is there anything else missing?

Best Regards
Kenneth

From: amd-gfx  On Behalf Of Lakha, 
Bhawanpreet
Sent: Friday, December 18, 2020 1:42 AM
To: Deucher, Alexander ; Kazlauskas, Nicholas 

Cc: amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH 2/2] drm/amd/display: enable idle optimizations for linux 
(MALL stutter)


[AMD Public Use]

[CAUTION: External Email]

[AMD Public Use]

Actually, I will drop the guards and if we see issues related to this, we can 
block it.

Bhawan

From: Lakha, Bhawanpreet 
mailto:bhawanpreet.la...@amd.com>>
Sent: December 17, 2020 12:32 PM
To: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>; Kazlauskas, 
Nicholas mailto:nicholas.kazlaus...@amd.com>>
Cc: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Subject: Re: [PATCH 2/2] drm/amd/display: enable idle optimizations for linux 
(MALL stutter)

I would but MALL is not fully validated so it might cause underflow issues if 
we keep it enabled by default. I can create a feature flag mask if that helps?

Bhawan

From: Deucher, Alexander 
mailto:alexander.deuc...@amd.com>>
Sent: December 17, 2020 12:04 PM
To: Lakha, Bhawanpreet 
mailto:bhawanpreet.la...@amd.com>>; Kazlauskas, 
Nicholas mailto:nicholas.kazlaus...@amd.com>>
Cc: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>
Subject: Re: [PATCH 2/2] drm/amd/display: enable idle optimizations for linux 
(MALL stutter)


[AMD Public Use]

Can we drop the Kconfig?  With that, the series is:
Acked-by: Alex Deucher 
mailto:alexander.deuc...@amd.com>>

From: Bhawanpreet Lakha 
mailto:bhawanpreet.la...@amd.com>>
Sent: Thursday, December 17, 2020 11:54 AM
To: Kazlauskas, Nicholas 
mailto:nicholas.kazlaus...@amd.com>>; Deucher, 
Alexander mailto:alexander.deuc...@amd.com>>
Cc: amd-gfx@lists.freedesktop.org 
mailto:amd-gfx@lists.freedesktop.org>>; Lakha, 
Bhawanpreet mailto:bhawanpreet.la...@amd.com>>; 
Kazlauskas, Nicholas 
mailto:nicholas.kazlaus...@amd.com>>
Subject: [PATCH 2/2] drm/amd/display: enable idle optimizations for linux (MALL 
stutter)

[Why]
We can only use this feature when the display is idle. When active vblank
irq count is 0 we know all the displays are idle.

[How]
-Add a active vblank irq counter
-Update the counter when we enable/disable vblank irq
-if vblank irq count is 0 we can consider mall stutter

Change-Id: Ib1e14a84ee2e8c6e057072128693449665012584
Signed-off-by: Bhawanpreet Lakha 
mailto:bhawanpreet.la...@amd.com>>
Acked-by: Alex Deucher 
mailto:alexander.deuc...@amd.com>>
Reviewed-by: Nick Kazlauskas 
mailto:nicholas.kazlaus...@amd.com>>
---
 drivers/gpu/drm/amd/display/Kconfig   |  6 +
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 22 +++
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |  9 
 drivers/gpu/drm/amd/display/dc/dc.h   |  3 +++
 4 files changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/Kconfig 
b/drivers/gpu/drm/amd/display/Kconfig
index 797b5d4b43e5..2444e664c7ee 100644
--- a/drivers/gpu/drm/amd/display/Kconfig
+++ b/drivers/gpu/drm/amd/display/Kconfig
@@ -23,6 +23,12 @@ config DRM_AMD_DC_HDCP
 help
   Choose this option if you want to support HDCP authentication.

+config DRM_AMD_DC_MALL
+   bool "Enable MALL support"
+   depends on DRM_AMD_DC
+   help
+ Choose this option if you want to support MALL
+
 config DRM_AMD_DC_SI
 bool "AMD DC support for Southern Islands ASICs"
 default n
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index a78ec16418b3..080f2a52cfed 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -5479,6 +5479,7 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, 
bool enable)
 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
+   struct amdgpu_display_manager *dm = >dm;
 int rc = 0;

 if (enable) {
@@ -5494,7 +5495,28 @@ static inline int dm_set_vblank(struct drm_crtc *crtc, 
bool enable)
 return rc;

 irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
+#if defined(CONFIG_DRM_AMD_DC_MALL)
+
+   if (!dc_interrupt_set(adev->dm.dc, irq_source, enable))
+   return -EBUSY;
+
+   mutex_lock(>dc_lock);
+
+   if (enable)
+   dm->active_vblank_irq_count++;
+   else
+   

RE: [v2] drm/amdgpu: skip vram operation for BAMACO runtime

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


Best Regards
Kenneth

-Original Message-
From: Gao, Likun  
Sent: Monday, December 14, 2020 3:38 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Deucher, Alexander 
; Feng, Kenneth ; Gao, Likun 

Subject: [v2] drm/amdgpu: skip vram operation for BAMACO runtime

From: Likun Gao 

Skip vram related operation for bamaco rumtime suspend and resume as vram is 
alive when BAMACO.
It can save about 32ms when suspend and about 15ms when resume.

v2: add local adev variable for maco enablement which checked by device MACO 
support cap and runtime method parameter to have a mix of devices that support 
different runtime pm modes.

Signed-off-by: Likun Gao 
Change-Id: I99cbaf720bfeecdc6682057b238d29c4e41cf155
---
 drivers/gpu/drm/amd/amdgpu/amdgpu.h   |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  9 ++-
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c   | 72 +++
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   |  7 +-
 4 files changed, 56 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index eed5410947e9..288c41e0b61f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1027,6 +1027,7 @@ struct amdgpu_device {
/* enable runtime pm on the device */
boolrunpm;
boolin_runpm;
+   boolrunpm_maco_en;
 
boolpm_sysfs_en;
boolucode_sysfs_en;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 0ec7c28c4d5a..0c608b903ec3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2464,7 +2464,8 @@ static int amdgpu_device_ip_late_init(struct 
amdgpu_device *adev)
amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
 
-   amdgpu_device_fill_reset_magic(adev);
+   if (!adev->runpm_maco_en || !adev->in_runpm)
+   amdgpu_device_fill_reset_magic(adev);
 
r = amdgpu_device_enable_mgpu_fan_boost();
if (r)
@@ -3706,7 +3707,8 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
fbcon)
amdgpu_amdkfd_suspend(adev, !fbcon);
 
/* evict vram memory */
-   amdgpu_bo_evict_vram(adev);
+   if (!adev->runpm_maco_en || !adev->in_runpm)
+   amdgpu_bo_evict_vram(adev);
 
amdgpu_fence_driver_suspend(adev);
 
@@ -3718,7 +3720,8 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
fbcon)
 * This second call to evict vram is to evict the gart page table
 * using the CPU.
 */
-   amdgpu_bo_evict_vram(adev);
+   if (!adev->runpm_maco_en || !adev->in_runpm)
+   amdgpu_bo_evict_vram(adev);
 
return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 523d22db094b..a198bc5d6a68 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -397,10 +397,12 @@ static int psp_tmr_init(struct psp_context *psp)
}
}
 
-   pptr = amdgpu_sriov_vf(psp->adev) ? _buf : NULL;
-   ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
+   if (!psp->adev->runpm_maco_en || !psp->adev->in_runpm) {
+   pptr = amdgpu_sriov_vf(psp->adev) ? _buf : NULL;
+   ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE,
  AMDGPU_GEM_DOMAIN_VRAM,
  >tmr_bo, >tmr_mc_addr, pptr);
+   }
 
return ret;
 }
@@ -504,8 +506,10 @@ static int psp_tmr_terminate(struct psp_context *psp)
return ret;
 
/* free TMR memory buffer */
-   pptr = amdgpu_sriov_vf(psp->adev) ? _buf : NULL;
-   amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, pptr);
+   if (!psp->adev->runpm_maco_en || !psp->adev->in_runpm) {
+   pptr = amdgpu_sriov_vf(psp->adev) ? _buf : NULL;
+   amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, pptr);
+   }
 
return 0;
 }
@@ -795,9 +799,10 @@ int psp_xgmi_terminate(struct psp_context *psp)
psp->xgmi_context.initialized = 0;
 
/* free xgmi shared memory */
-   amdgpu_bo_free_kernel(>xgmi_context.xgmi_shared_bo,
-   >xgmi_context.xgmi_shared_mc_addr,
-   >xgmi_context.xgmi_shared_buf);
+   if (!psp->adev->runpm_maco_en || !psp->adev->in_runpm)
+   amdgpu_bo_free_kernel(>xgmi_context.xgmi_shared_bo,
+   >xgmi_context.xgmi_shared_mc_a

RE: [PATCH] drm/amdgpu: add judgement for suspend/resume sequence

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


Best Regards
Kenneth

-Original Message-
From: Gao, Likun  
Sent: Monday, December 7, 2020 11:45 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth 
; Gao, Likun 
Subject: [PATCH] drm/amdgpu: add judgement for suspend/resume sequence

From: Likun Gao 

Only APU should deal with the situation that amdgpu suspend/resume with
s0i3 support to skip RLC/CP/GFX disable during suspend.

Signed-off-by: Likun Gao 
Change-Id: Icca91b3497f12a6d78f005ee63461cf0e8f24958
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 79dd85f71fab..75f40a8c59f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2650,7 +2650,8 @@ static int amdgpu_device_ip_suspend_phase1(struct 
amdgpu_device *adev)  {
int i, r;
 
-   if (!amdgpu_acpi_is_s0ix_supported() || amdgpu_in_reset(adev)) {
+   if (!amdgpu_acpi_is_s0ix_supported() || amdgpu_in_reset(adev) ||
+   !(adev->flags & AMD_IS_APU)) {
amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
}
@@ -3710,7 +3711,8 @@ int amdgpu_device_suspend(struct drm_device *dev, bool 
fbcon)
 
amdgpu_fence_driver_suspend(adev);
 
-   if (!amdgpu_acpi_is_s0ix_supported() || amdgpu_in_reset(adev))
+   if (!amdgpu_acpi_is_s0ix_supported() || amdgpu_in_reset(adev) ||
+   !(adev->flags & AMD_IS_APU))
r = amdgpu_device_ip_suspend_phase2(adev);
else
amdgpu_gfx_state_change_set(adev, sGpuChangeState_D3Entry); @@ 
-3744,7 +3746,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon)
if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
return 0;
 
-   if (amdgpu_acpi_is_s0ix_supported())
+   if (amdgpu_acpi_is_s0ix_supported() && (adev->flags & AMD_IS_APU))
amdgpu_gfx_state_change_set(adev, sGpuChangeState_D0Entry);
 
/* post card */
--
2.25.1
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RE: [PATCH 2/2] drm/amdgpu: add module parameter choose runtime method

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Series is Reviewed-by: Kenneth Feng 


Best Regards
Kenneth

-Original Message-
From: Gao, Likun  
Sent: Friday, November 20, 2020 3:59 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth 
; Gao, Likun 
Subject: [PATCH 2/2] drm/amdgpu: add module parameter choose runtime method

From: Likun Gao 

Default runtime logic not changed.
Provide an alternative runtime method. (set 1 to use BACO; 2 to use BAMACO) 
When set reset_method to 4, it will use BACO or BAMACO for gpu reset, according 
to runtime value.

Signed-off-by: Likun Gao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  4 +-
 .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c| 38 +++
 2 files changed, 32 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 7f98cf1bef07..b2a1dd7581bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -304,7 +304,7 @@ module_param_named(aspm, amdgpu_aspm, int, 0444);
  * Override for runtime power management control for dGPUs in PX/HG laptops. 
The amdgpu driver can dynamically power down
  * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). 
Setting the value to 0 disables this functionality.
  */
-MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX 
only default)");
+MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 
+= force enable with BACO, 0 = disable, -1 = PX only default)");
 module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
 
 /**
@@ -790,7 +790,7 @@ module_param_named(tmz, amdgpu_tmz, int, 0444);
  * DOC: reset_method (int)
  * GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 
= mode2, 4 = baco)
  */
-MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = 
legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco)");
+MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 
+0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco)");
 module_param_named(reset_method, amdgpu_reset_method, int, 0444);
 
 /**
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 7144ea4c0b78..62c34a01a3e1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1485,6 +1485,9 @@ enum smu_baco_state smu_v11_0_baco_get_state(struct 
smu_context *smu)
return baco_state;
 }
 
+#define D3HOT_BACO_SEQUENCE 0
+#define D3HOT_BAMACO_SEQUENCE 2
+
 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state 
state)  {
struct smu_baco_context *smu_baco = >smu_baco; @@ -1499,15 
+1502,34 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum 
smu_baco_state state)
mutex_lock(_baco->mutex);
 
if (state == SMU_BACO_STATE_ENTER) {
-   if (!ras || !ras->supported) {
-   data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
-   data |= 0x8000;
-   WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
-
-   ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_EnterBaco, 0, NULL);
-   } else {
-   ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_EnterBaco, 1, NULL);
+   switch (adev->asic_type) {
+   case CHIP_SIENNA_CICHLID:
+   case CHIP_NAVY_FLOUNDER:
+   case CHIP_DIMGREY_CAVEFISH:
+   if (amdgpu_runtime_pm == 2)
+   ret = smu_cmn_send_smc_msg_with_param(smu,
+ 
SMU_MSG_EnterBaco,
+ 
D3HOT_BAMACO_SEQUENCE,
+ NULL);
+   else
+   ret = smu_cmn_send_smc_msg_with_param(smu,
+ 
SMU_MSG_EnterBaco,
+ 
D3HOT_BACO_SEQUENCE,
+ NULL);
+   break;
+   default:
+   if (!ras || !ras->supported) {
+   data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
+   data |= 0x8000;
+   WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
+
+   ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_EnterBaco, 0, NULL);
+   } else {
+   ret = smu_cmn_send_smc_msg_with_param(smu, 
SMU_MSG_EnterBaco, 1, NULL);

RE: [PATCH 2/2] drm/amd/pm: fix the crash after runtime pm resume

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

[AMD Official Use Only - Internal Distribution Only]

Hi Evan/Alex,
In the process of baco enter/exit, smu disables all features, so 
smu_disable_dpms is not needed.
And the sequential steps in smu_smc_hw_setup after function smu_is_dpm_running 
are not needed since baco doesn't clean up the smu status.
This fix is specific to SIENNA_CICHLID. For the other ASICS, need to confirm 
since the firmware might be different.
Thanks.


Best Regards
Kenneth

-Original Message-
From: Quan, Evan 
Sent: Wednesday, November 18, 2020 8:46 AM
To: Feng, Kenneth ; amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth 
Subject: RE: [PATCH 2/2] drm/amd/pm: fix the crash after runtime pm resume

[AMD Official Use Only - Internal Distribution Only]

I suspect "smu_is_dpm_running" reports a wrong result due to 
"smu_system_features_control(smu, false)" was skipped for SIENNA_CICHLID in 
smu_disable_dpms().
That is outdated cached values were used for "smu_is_dpm_running".
If that's true, a fix in smu_disable_dpms() may be more proper.

Evan
-Original Message-
From: amd-gfx  On Behalf Of Kenneth Feng
Sent: Tuesday, November 17, 2020 9:31 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth 
Subject: [PATCH 2/2] drm/amd/pm: fix the crash after runtime pm resume

Some features are still disabled after runtime pm resume. This can take the 
hardware back.
Unlike other projects, this doesn't need pptable retransfer.

Signed-off-by: Kenneth Feng 
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 39990790ed67..ebd50f144c5d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -914,11 +914,14 @@ static int smu_smc_hw_setup(struct smu_context *smu)  {  
struct amdgpu_device *adev = smu->adev;  uint32_t pcie_gen = 0, pcie_width = 0; 
-int ret;
+int ret = 0;

 if (adev->in_suspend && smu_is_dpm_running(smu)) {  dev_info(adev->dev, "dpm 
has been enabled\n"); -return 0;
+/* this is needed specifically */
+if (adev->asic_type == CHIP_SIENNA_CICHLID) ret =
+smu_system_features_control(smu, true); return ret;
 }

 ret = smu_init_display_count(smu, 0);
--
2.17.1

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RE: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


Best Regards
Kenneth

-Original Message-
From: Gao, Likun  
Sent: Monday, November 16, 2020 3:35 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth 
; Gao, Likun 
Subject: [PATCH] drm/amd/pm: update driver if file for sienna cichlid

From: Likun Gao 

Update driver if file for sienna cichlid.

Signed-off-by: Likun Gao 
Change-Id: Ibcffb2a668202f941b1e8e7a22924976c910cf35
---
 .../pm/inc/smu11_driver_if_sienna_cichlid.h   | 16 +-
 drivers/gpu/drm/amd/pm/inc/smu_v11_0.h|  2 +-
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 22 ---
 3 files changed, 12 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h 
b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
index e418a46603c8..fa95147b5a63 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,9 +27,9 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if  // any structure is 
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x3A
+#define SMU11_DRIVER_IF_VERSION 0x3B
 
-#define PPTABLE_Sienna_Cichlid_SMU_VERSION 6
+#define PPTABLE_Sienna_Cichlid_SMU_VERSION 7
 
 #define NUM_GFXCLK_DPM_LEVELS  16
 #define NUM_SMNCLK_DPM_LEVELS  2
@@ -437,6 +437,7 @@ typedef enum {
   PIECEWISE_LINEAR_FUSED_MODEL = 0,
   PIECEWISE_LINEAR_PP_MODEL,
   QUADRATIC_PP_MODEL,
+  PERPART_PIECEWISE_LINEAR_PP_MODEL,
 } DfllDroopModelSelect_e;
 
 typedef struct {
@@ -612,7 +613,9 @@ typedef struct {
   uint16_t   SmnclkDpmFreq[NUM_SMNCLK_DPM_LEVELS];   // in MHz
   uint16_t   SmnclkDpmVoltage [NUM_SMNCLK_DPM_LEVELS];   // mV(Q2)
 
-  uint32_t PaddingAPCC[4];
+  uint32_t   PaddingAPCC;
+  uint16_t   
PerPartDroopVsetGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS];  //In 
mV(Q2)
+  uint16_t   PaddingPerPartDroop;
 
   // SECTION: Throttler settings
   uint32_t ThrottlerControlMask;   // See Throtter masks defines
@@ -667,7 +670,9 @@ typedef struct {
   uint16_t   FreqTablePhyclk   [NUM_PHYCLK_DPM_LEVELS  ]; // In MHz
   uint16_t   FreqTableDtbclk   [NUM_DTBCLK_DPM_LEVELS  ]; // In MHz
   uint16_t   FreqTableFclk [NUM_FCLK_DPM_LEVELS]; // In MHz
-  uint32_t   Paddingclks[16];
+  uint32_t   Paddingclks;
+
+  DroopInt_t 
PerPartDroopModelGfxDfll[NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS]; //GHz 
->Vstore in IEEE float format
 
   uint32_t   DcModeMaxFreq [PPCLK_COUNT]; // In MHz
   
@@ -1221,7 +1226,8 @@ typedef struct {
 #define WORKLOAD_PPLIB_VR_BIT 4 
 #define WORKLOAD_PPLIB_COMPUTE_BIT5 
 #define WORKLOAD_PPLIB_CUSTOM_BIT 6 
-#define WORKLOAD_PPLIB_COUNT  7 
+#define WORKLOAD_PPLIB_W3D_BIT7 
+#define WORKLOAD_PPLIB_COUNT  8 
 
 
 // These defines are used with the following messages:
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index 41bc919dc9f4..eff396c7a281 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV10 0x36
 #define SMU11_DRIVER_IF_VERSION_NV12 0x36
 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3A
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3B
 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5
 #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x02
 #define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xD
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 0600befc6e4c..21c5ea3a4a63 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -1805,11 +1805,6 @@ static void sienna_cichlid_dump_pptable(struct 
smu_context *smu)
dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, 
pptable->SmnclkDpmFreq[i]);
dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, 
pptable->SmnclkDpmVoltage[i]);
}
-   dev_info(smu->adev->dev, "PaddingAPCC[0] = 0x%x\n", 
pptable->PaddingAPCC[0]);
-   dev_info(smu->adev->dev, "PaddingAPCC[1] = 0x%x\n", 
pptable->PaddingAPCC[1]);
-   dev_info(smu->adev->dev, "PaddingAPCC[2] = 0x%x\n", 
pptable->PaddingAPCC[2]);
-   dev_info(smu->adev->dev, "PaddingAPCC[3] = 0x%x\n", 
pptable->PaddingAPCC[3]);
-
dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", 
pptable->ThrottlerControlMask);
 
dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", 
pptable->FwDStateMask);
@@ -2036,23 

RE: [PATCH] drm/amdgpu: add missing clock gating info in amdgpu_pm_info

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


Best Regards
Kenneth

-Original Message-
From: amd-gfx  On Behalf Of Kevin Wang
Sent: Wednesday, November 4, 2020 3:36 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Wang, Kevin(Yang) 
; Zhang, Hawking 
Subject: [PATCH] drm/amdgpu: add missing clock gating info in amdgpu_pm_info

[CAUTION: External Email]

add missing clock gating informations in amdgpu_pm_info 1. 
AMD_CG_SUPPORT_VCN_MGCG 2. AMD_CG_SUPPORT_HDP_DS 3. AMD_CG_SUPPORT_HDP_SD 4. 
AMD_CG_SUPPORT_IH_CG 5. AMD_CG_SUPPORT_JPEG_MGCG

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index a33b1cc50008..7b6ef05a1d35 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -64,6 +64,11 @@ static const struct cg_flag_name clocks[] = {
{AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
{AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
{AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
+   {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
+   {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
+   {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
+   {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
+   {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},

{AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock 
Gating"},
{AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
--
2.17.1

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RE: [PATCH] drm/amdgpu: cleanup debug information in amdgpu_set_pp_features()

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


Best Regards
Kenneth

-Original Message-
From: amd-gfx  On Behalf Of Kevin Wang
Sent: Wednesday, November 4, 2020 1:06 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan 
; Wang, Kevin(Yang) 
Subject: [PATCH] drm/amdgpu: cleanup debug information in 
amdgpu_set_pp_features()

[CAUTION: External Email]

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index e57153d1fa24..a33b1cc50008 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -941,8 +941,6 @@ static ssize_t amdgpu_set_pp_features(struct device *dev,
if (ret)
return -EINVAL;

-   pr_debug("featuremask = 0x%llx\n", featuremask);
-
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0) {
pm_runtime_put_autosuspend(ddev->dev);
--
2.17.1

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RE: [PATCH] drm/amdgpu: cleanup debug log in amdgpu_set_pp_features()

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


Best Regards
Kenneth

-Original Message-
From: amd-gfx  On Behalf Of Kevin Wang
Sent: Wednesday, November 4, 2020 1:06 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Quan, Evan 
; Wang, Kevin(Yang) 
Subject: [PATCH] drm/amdgpu: cleanup debug log in amdgpu_set_pp_features()

[CAUTION: External Email]

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c 
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index e57153d1fa24..a33b1cc50008 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -941,8 +941,6 @@ static ssize_t amdgpu_set_pp_features(struct device *dev,
if (ret)
return -EINVAL;

-   pr_debug("featuremask = 0x%llx\n", featuremask);
-
ret = pm_runtime_get_sync(ddev->dev);
if (ret < 0) {
pm_runtime_put_autosuspend(ddev->dev);
--
2.17.1

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RE: [PATCH] drm/amd/pm: fix the wrong fan speed in fan1_input

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,
As I confirmed, this is Arcturus specific.
On Arcturus we don't have fan control feature and the fan speed is always 0 
from the metrics table.
For navi series, I'm sure we don't need it. Looks like we can't just revert it.
Thanks.



-Original Message-
From: Alex Deucher  
Sent: Thursday, October 22, 2020 1:19 PM
To: Feng, Kenneth 
Cc: amd-gfx list ; Gao, Likun 
Subject: Re: [PATCH] drm/amd/pm: fix the wrong fan speed in fan1_input

[CAUTION: External Email]

On Thu, Oct 22, 2020 at 1:06 AM Alex Deucher  wrote:
>
> On Thu, Oct 22, 2020 at 1:05 AM Alex Deucher  wrote:
> >
> > On Thu, Oct 22, 2020 at 1:01 AM Feng, Kenneth  wrote:
> > >
> > > [AMD Official Use Only - Internal Distribution Only]
> > >
> > > Hi Alex,
> > > The speed is not 0 in the below scenario if the rpm is got from the 
> > > metrics table on navi10.
> > > The possibility is that you were using an old firmware. The 
> > > firmware on my system is 0x002a3e00 Can you remember the version when you 
> > > saw the problem?
> >
> > SMC feature version: 0, firmware version: 0x002a3600
>
> Actually, I'm not sure.  It might have been updated since the last 
> time I tested this.

If you can confirm it's working on all the asics with the latest firmware, 
maybe it makes more sense to just revert this commit:

commit 3033e9f1c2de0eca89e9a98c7e307820f3fc953e
Author: Alex Deucher 
Date:   Thu Aug 27 00:12:38 2020 -0400

drm/amdgpu/swsmu: handle manual fan readback on SMU11

Need to read back from registers for manual mode rather than
using the metrics table.

Bug: 
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1164data=04%7C01%7CKenneth.Feng%40amd.com%7C7b20871a843e41a5038408d8764a0d51%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637389407704795887%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=2jEFoU62zbGIwEACv3C6xAmyNgIQ4q1kbBfNQ3Ztm7E%3Dreserved=0
Reviewed-by: Evan Quan 
Signed-off-by: Alex Deucher 

Alex

>
> Alex
>
>
> >
> > Alex
> >
> > > Thanks.
> > > # echo 1 > 
> > > devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:
> > > 00.0/hwmon/hwmon3/pwm1_enable # echo 125 > 
> > > devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:
> > > 00.0/hwmon/hwmon3/pwm1 # cat 
> > > devices/pci:00/:00:01.1/:02:00.0/0000:03:00.0/:04:
> > > 00.0/hwmon/hwmon3/pwm1
> > > 109
> > >
> > >
> > >
> > >
> > >
> > >
> > > -Original Message-
> > > From: Alex Deucher 
> > > Sent: Thursday, October 22, 2020 11:28 AM
> > > To: Feng, Kenneth 
> > > Cc: amd-gfx list ; Gao, Likun 
> > > 
> > > Subject: Re: [PATCH] drm/amd/pm: fix the wrong fan speed in 
> > > fan1_input
> > >
> > > [CAUTION: External Email]
> > >
> > > On Wed, Oct 21, 2020 at 11:16 PM Feng, Kenneth  
> > > wrote:
> > > >
> > > > [AMD Official Use Only - Internal Distribution Only]
> > > >
> > > > Hi Alex,
> > > > After reboot, It is also not read back correctly as below.
> > > > # echo 1 >
> > > > devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:0
> > > > 4:00.0 /hwmon/hwmon3/fan1_enable s# cat
> > > > devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:0
> > > > 4:00.0
> > > > /hwmon/hwmon3/fan1_input
> > > > 183105
> > > > # cat
> > > > devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:0
> > > > 4:00.0
> > > > /hwmon/hwmon3/fan1_enable
> > > > 1
> > > >
> > >
> > > What about if you manually set the speed.  E.g., # echo 1 > 
> > > devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:
> > > 00.0/hwmon/hwmon3/fan1_enable # echo 800 > 
> > > devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:
> > > 00.0/hwmon/hwmon3/fan1_target # cat 
> > > devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:
> > > 00.0/hwmon/hwmon3/fan1_input
> > >
> > > The problem I ran into on navi1x was setting the fan speed 
> > > manually resulted in 0 for the fan speed in the metrics table.  
> > > E.g.,
> > >
> > > # echo 1 > 
> > > devices/pci:00/:00:01.1/:02:00.0/:03:0

RE: [PATCH] drm/amd/pm: fix the wrong fan speed in fan1_input

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,
The speed is not 0 in the below scenario if the rpm is got from the metrics 
table on navi10.
The possibility is that you were using an old firmware. The firmware on my 
system is 0x002a3e00
Can you remember the version when you saw the problem?
Thanks.
# echo 1 > 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/pwm1_enable
# echo 125 > 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/pwm1
# cat 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/pwm1
109






-Original Message-
From: Alex Deucher  
Sent: Thursday, October 22, 2020 11:28 AM
To: Feng, Kenneth 
Cc: amd-gfx list ; Gao, Likun 
Subject: Re: [PATCH] drm/amd/pm: fix the wrong fan speed in fan1_input

[CAUTION: External Email]

On Wed, Oct 21, 2020 at 11:16 PM Feng, Kenneth  wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Alex,
> After reboot, It is also not read back correctly as below.
> # echo 1 > 
> devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0
> /hwmon/hwmon3/fan1_enable s# cat 
> devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0
> /hwmon/hwmon3/fan1_input
> 183105
> # cat 
> devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0
> /hwmon/hwmon3/fan1_enable
> 1
>

What about if you manually set the speed.  E.g., # echo 1 > 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/fan1_enable
# echo 800 > 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/fan1_target
# cat 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/fan1_input

The problem I ran into on navi1x was setting the fan speed manually resulted in 
0 for the fan speed in the metrics table.  E.g.,

# echo 1 > 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/pwm1_enable
# echo 125 > 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/pwm1
# cat 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/pwm

See:
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitlab.freedesktop.org%2Fdrm%2Famd%2F-%2Fissues%2F1164data=04%7C01%7CKenneth.Feng%40amd.com%7Cfdef2561887a41322e2a08d8763a897b%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637389341097409110%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=M6EIZVH9vxUJw0d5eh%2B6VzYKQ0LEOwMRdAaEYzrU1d8%3Dreserved=0

Alex


>
>
> -Original Message-
> From: Alex Deucher 
> Sent: Thursday, October 22, 2020 10:18 AM
> To: Feng, Kenneth 
> Cc: amd-gfx list ; Gao, Likun 
> 
> Subject: Re: [PATCH] drm/amd/pm: fix the wrong fan speed in fan1_input
>
> [CAUTION: External Email]
>
> On Wed, Oct 21, 2020 at 9:30 PM Feng, Kenneth  wrote:
> >
> > [AMD Official Use Only - Internal Distribution Only]
> >
> > Hi Alex,
> > Navi10 also has this problem as below.
> > # cat
> > devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00
> > .0
> > /hwmon/hwmon3/fan1_input
> > 1217
> > # cat
> > devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00
> > .0
> > /hwmon/hwmon3/fan1_enable
> > 0
> > # echo 1 >
> > devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00
> > .0
> > /hwmon/hwmon3/fan1_enable # cat
> > devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00
> > .0
> > /hwmon/hwmon3/fan1_enable
> > 1
> > s# cat
> > devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00
> > .0
> > /hwmon/hwmon3/fan1_input
> > 183105
> >
> > In AGM, the rpm is 1800.
>
> Does it read back correctly if you manually set the fan rpm first before 
> reading it back?
>
> Alex
>
>
> >
> >
> >
> > -Original Message-
> > From: Feng, Kenneth
> > Sent: Thursday, October 22, 2020 9:11 AM
> > To: Alex Deucher 
> > Cc: amd-gfx list ; Gao, Likun 
> > 
> > Subject: RE: [PATCH] drm/amd/pm: fix the wrong fan speed in 
> > fan1_input
> >
> > [AMD Official Use Only - Internal Distribution Only]
> >
> > Hi Alex,
> > Right, smu_v11_0_get_fan_speed_rpm() is not correct for sienna cichlid when 
> > it's in manual mode.
> > An example is that in my system, the rpm is about 1800 in manual mode, 
> > confirmed with AGM and the internal smu fw scoreboard.
> > But the fan1_input shows about 18, which is way more than the real 
> > value.
> > If you see the value from 

RE: [PATCH] drm/amd/pm: fix the wrong fan speed in fan1_input

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,
After reboot, It is also not read back correctly as below.
# echo 1 > 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/fan1_enable
s# cat 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/fan1_input
183105
# cat 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/fan1_enable
1



-Original Message-
From: Alex Deucher  
Sent: Thursday, October 22, 2020 10:18 AM
To: Feng, Kenneth 
Cc: amd-gfx list ; Gao, Likun 
Subject: Re: [PATCH] drm/amd/pm: fix the wrong fan speed in fan1_input

[CAUTION: External Email]

On Wed, Oct 21, 2020 at 9:30 PM Feng, Kenneth  wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Alex,
> Navi10 also has this problem as below.
> # cat 
> devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0
> /hwmon/hwmon3/fan1_input
> 1217
> # cat 
> devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0
> /hwmon/hwmon3/fan1_enable
> 0
> # echo 1 > 
> devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0
> /hwmon/hwmon3/fan1_enable # cat 
> devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0
> /hwmon/hwmon3/fan1_enable
> 1
> s# cat 
> devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0
> /hwmon/hwmon3/fan1_input
> 183105
>
> In AGM, the rpm is 1800.

Does it read back correctly if you manually set the fan rpm first before 
reading it back?

Alex


>
>
>
> -Original Message-
> From: Feng, Kenneth
> Sent: Thursday, October 22, 2020 9:11 AM
> To: Alex Deucher 
> Cc: amd-gfx list ; Gao, Likun 
> 
> Subject: RE: [PATCH] drm/amd/pm: fix the wrong fan speed in fan1_input
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Alex,
> Right, smu_v11_0_get_fan_speed_rpm() is not correct for sienna cichlid when 
> it's in manual mode.
> An example is that in my system, the rpm is about 1800 in manual mode, 
> confirmed with AGM and the internal smu fw scoreboard.
> But the fan1_input shows about 18, which is way more than the real value.
> If you see the value from the metrics table is 0 on navi10, maybe it's the 
> real rpm since we still have 0 rpm feature.
> I can double check the navi10.
> Thanks.
>
>
> -Original Message-
> From: Alex Deucher 
> Sent: Thursday, October 22, 2020 2:47 AM
> To: Feng, Kenneth 
> Cc: amd-gfx list ; Gao, Likun 
> 
> Subject: Re: [PATCH] drm/amd/pm: fix the wrong fan speed in fan1_input
>
> [CAUTION: External Email]
>
> On Wed, Oct 21, 2020 at 9:40 AM Alex Deucher  wrote:
> >
> > On Wed, Oct 21, 2020 at 9:01 AM Alex Deucher  wrote:
> > >
> > > On Wed, Oct 21, 2020 at 2:45 AM Kenneth Feng  wrote:
> > > >
> > > > fix the wrong fan speed in fan1_input when the fan control mode is 
> > > > manual.
> > > > the fan speed value is not correct when we set manual mode to 
> > > > fan1_enalbe - 1.
> > > > since the fan speed in the metrics table always reflects the 
> > > > real fan speed,we can fetch the fan speed for both auto and manual mode.
> > > >
> > > > Signed-off-by: Kenneth Feng 
> > >
> > > NACK.  At least on the navi boards I have, the metrics table fan 
> > > speed reads back 0 when the fan is in manual mode.  That's why I 
> > > changed this in the first place.
> >
> > Nevermind, I was thinking about navi1x.  If this is working 
> > correctly on sienna cichlid, please ignore me.
>
> That said, I don't see why the current code should not work.  Maybe a bug 
> elsewhere?  Is smu_v11_0_get_fan_speed_rpm() incorrect for sienna cichlid?
>
> Alex
>
> >
> > Alex
> >
> >
> > >
> > > Alex
> > >
> > >
> > > > ---
> > > >  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 11 +++
> > > >  1 file changed, 3 insertions(+), 8 deletions(-)
> > > >
> > > > diff --git
> > > > a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > > index 496abc31b07e..27b6cade9ade 100644
> > > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > > @@ -1171,14 +1171,9 @@ static int 
> > > > sienna_cichlid_get_fan_speed_rpm(struct smu_context *smu,
> > > > if (!speed)
> > > > re

RE: [PATCH] drm/amd/pm: fix the wrong fan speed in fan1_input

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,
Navi10 also has this problem as below.
# cat 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/fan1_input
1217
# cat 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/fan1_enable
0
# echo 1 > 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/fan1_enable
# cat 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/fan1_enable
1
s# cat 
devices/pci:00/:00:01.1/:02:00.0/:03:00.0/:04:00.0/hwmon/hwmon3/fan1_input
183105

In AGM, the rpm is 1800.



-Original Message-
From: Feng, Kenneth 
Sent: Thursday, October 22, 2020 9:11 AM
To: Alex Deucher 
Cc: amd-gfx list ; Gao, Likun 
Subject: RE: [PATCH] drm/amd/pm: fix the wrong fan speed in fan1_input

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,
Right, smu_v11_0_get_fan_speed_rpm() is not correct for sienna cichlid when 
it's in manual mode.
An example is that in my system, the rpm is about 1800 in manual mode, 
confirmed with AGM and the internal smu fw scoreboard.
But the fan1_input shows about 18, which is way more than the real value.
If you see the value from the metrics table is 0 on navi10, maybe it's the real 
rpm since we still have 0 rpm feature.
I can double check the navi10.
Thanks.


-Original Message-
From: Alex Deucher 
Sent: Thursday, October 22, 2020 2:47 AM
To: Feng, Kenneth 
Cc: amd-gfx list ; Gao, Likun 
Subject: Re: [PATCH] drm/amd/pm: fix the wrong fan speed in fan1_input

[CAUTION: External Email]

On Wed, Oct 21, 2020 at 9:40 AM Alex Deucher  wrote:
>
> On Wed, Oct 21, 2020 at 9:01 AM Alex Deucher  wrote:
> >
> > On Wed, Oct 21, 2020 at 2:45 AM Kenneth Feng  wrote:
> > >
> > > fix the wrong fan speed in fan1_input when the fan control mode is manual.
> > > the fan speed value is not correct when we set manual mode to fan1_enalbe 
> > > - 1.
> > > since the fan speed in the metrics table always reflects the real 
> > > fan speed,we can fetch the fan speed for both auto and manual mode.
> > >
> > > Signed-off-by: Kenneth Feng 
> >
> > NACK.  At least on the navi boards I have, the metrics table fan 
> > speed reads back 0 when the fan is in manual mode.  That's why I 
> > changed this in the first place.
>
> Nevermind, I was thinking about navi1x.  If this is working correctly 
> on sienna cichlid, please ignore me.

That said, I don't see why the current code should not work.  Maybe a bug 
elsewhere?  Is smu_v11_0_get_fan_speed_rpm() incorrect for sienna cichlid?

Alex

>
> Alex
>
>
> >
> > Alex
> >
> >
> > > ---
> > >  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 11 +++
> > >  1 file changed, 3 insertions(+), 8 deletions(-)
> > >
> > > diff --git
> > > a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > index 496abc31b07e..27b6cade9ade 100644
> > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > @@ -1171,14 +1171,9 @@ static int sienna_cichlid_get_fan_speed_rpm(struct 
> > > smu_context *smu,
> > > if (!speed)
> > > return -EINVAL;
> > >
> > > -   switch (smu_v11_0_get_fan_control_mode(smu)) {
> > > -   case AMD_FAN_CTRL_AUTO:
> > > -   return sienna_cichlid_get_smu_metrics_data(smu,
> > > -  
> > > METRICS_CURR_FANSPEED,
> > > -  speed);
> > > -   default:
> > > -   return smu_v11_0_get_fan_speed_rpm(smu, speed);
> > > -   }
> > > +   return sienna_cichlid_get_smu_metrics_data(smu,
> > > +   METRICS_CURR_FANSPEED,
> > > +   speed);
> > >  }
> > >
> > >  static int sienna_cichlid_get_fan_parameters(struct smu_context
> > > *smu)
> > > --
> > > 2.17.1
> > >
> > > ___
> > > amd-gfx mailing list
> > > amd-gfx@lists.freedesktop.org
> > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> > > lists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7
> > > C01%7Ckenneth.feng%40amd.com%7Cd8e969f4b63e4897a3df08d875f1b050%7C
> > > 3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637389028190609906%7CUn
> > > known%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> > > 1haWwiLCJXVCI6Mn0%3D%7C1000sdata=KomP2H%2FadKJChDbNvNPQlTotmE
> > > WrhutsQCHfiRIjNUY%3Dreserved=0
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

RE: [PATCH] drm/amd/pm: fix the wrong fan speed in fan1_input

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Hi Alex,
Right, smu_v11_0_get_fan_speed_rpm() is not correct for sienna cichlid when 
it's in manual mode.
An example is that in my system, the rpm is about 1800 in manual mode, 
confirmed with AGM and the internal smu fw scoreboard.
But the fan1_input shows about 18, which is way more than the real value.
If you see the value from the metrics table is 0 on navi10, maybe it's the real 
rpm since we still have 0 rpm feature.
I can double check the navi10.
Thanks.


-Original Message-
From: Alex Deucher  
Sent: Thursday, October 22, 2020 2:47 AM
To: Feng, Kenneth 
Cc: amd-gfx list ; Gao, Likun 
Subject: Re: [PATCH] drm/amd/pm: fix the wrong fan speed in fan1_input

[CAUTION: External Email]

On Wed, Oct 21, 2020 at 9:40 AM Alex Deucher  wrote:
>
> On Wed, Oct 21, 2020 at 9:01 AM Alex Deucher  wrote:
> >
> > On Wed, Oct 21, 2020 at 2:45 AM Kenneth Feng  wrote:
> > >
> > > fix the wrong fan speed in fan1_input when the fan control mode is manual.
> > > the fan speed value is not correct when we set manual mode to fan1_enalbe 
> > > - 1.
> > > since the fan speed in the metrics table always reflects the real 
> > > fan speed,we can fetch the fan speed for both auto and manual mode.
> > >
> > > Signed-off-by: Kenneth Feng 
> >
> > NACK.  At least on the navi boards I have, the metrics table fan 
> > speed reads back 0 when the fan is in manual mode.  That's why I 
> > changed this in the first place.
>
> Nevermind, I was thinking about navi1x.  If this is working correctly 
> on sienna cichlid, please ignore me.

That said, I don't see why the current code should not work.  Maybe a bug 
elsewhere?  Is smu_v11_0_get_fan_speed_rpm() incorrect for sienna cichlid?

Alex

>
> Alex
>
>
> >
> > Alex
> >
> >
> > > ---
> > >  .../gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 11 +++
> > >  1 file changed, 3 insertions(+), 8 deletions(-)
> > >
> > > diff --git 
> > > a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
> > > b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > index 496abc31b07e..27b6cade9ade 100644
> > > --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> > > @@ -1171,14 +1171,9 @@ static int sienna_cichlid_get_fan_speed_rpm(struct 
> > > smu_context *smu,
> > > if (!speed)
> > > return -EINVAL;
> > >
> > > -   switch (smu_v11_0_get_fan_control_mode(smu)) {
> > > -   case AMD_FAN_CTRL_AUTO:
> > > -   return sienna_cichlid_get_smu_metrics_data(smu,
> > > -  
> > > METRICS_CURR_FANSPEED,
> > > -  speed);
> > > -   default:
> > > -   return smu_v11_0_get_fan_speed_rpm(smu, speed);
> > > -   }
> > > +   return sienna_cichlid_get_smu_metrics_data(smu,
> > > +   METRICS_CURR_FANSPEED,
> > > +   speed);
> > >  }
> > >
> > >  static int sienna_cichlid_get_fan_parameters(struct smu_context 
> > > *smu)
> > > --
> > > 2.17.1
> > >
> > > ___
> > > amd-gfx mailing list
> > > amd-gfx@lists.freedesktop.org
> > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> > > lists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfxdata=04%7
> > > C01%7Ckenneth.feng%40amd.com%7Cd8e969f4b63e4897a3df08d875f1b050%7C
> > > 3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637389028190609906%7CUn
> > > known%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> > > 1haWwiLCJXVCI6Mn0%3D%7C1000sdata=KomP2H%2FadKJChDbNvNPQlTotmE
> > > WrhutsQCHfiRIjNUY%3Dreserved=0
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Re: [PATCH] drm/amd/pm: fix pcie information for sienna cichlid

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


在 2020/10/20 下午4:57，“Gao, Likun” 写入:

From: Likun Gao 

Fix the function used for sienna cichlid to get correct PCIE information
by pp_dpm_pcie.

Signed-off-by: Likun Gao 
Change-Id: I81e529be6e96f083eb7aa244c16700422bde5fec
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index c8e8790e0871..e00c38b1bd41 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -964,8 +964,8 @@ static int sienna_cichlid_print_clk_levels(struct 
smu_context *smu,
 }
 break;
 case SMU_PCIE:
-gen_speed = smu_v11_0_get_current_pcie_link_speed(smu);
-lane_width = smu_v11_0_get_current_pcie_link_width(smu);
+gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
+lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
 for (i = 0; i < NUM_LINK_LEVELS; i++)
 size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
--
2.25.1


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RE: [PATCH] drm/amd/swsmu: correct wrong feature bit mapping

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Wang, Kevin(Yang)  
Sent: Friday, October 16, 2020 5:07 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth 
; Lazar, Lijo ; Wang, Kevin(Yang) 

Subject: [PATCH] drm/amd/swsmu: correct wrong feature bit mapping

1.
when smc feature bit isn't mapped,
the feature state isn't showed on sysfs node of pp_features.
2.
add pp_features table title

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 27 --
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index c30d3338825f..92b2ea4c197b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -431,10 +431,9 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
   char *buf)
 {
uint32_t feature_mask[2] = { 0 };
-   int32_t feature_index = 0;
+   int feature_index = 0;
uint32_t count = 0;
-   uint32_t sort_feature[SMU_FEATURE_COUNT];
-   uint64_t hw_feature_count = 0;
+   int8_t sort_feature[SMU_FEATURE_COUNT];
size_t size = 0;
int ret = 0, i;
 
@@ -447,23 +446,31 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context 
*smu,
size =  sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
feature_mask[1], feature_mask[0]);
 
+   memset(sort_feature, -1, sizeof(sort_feature));
+
for (i = 0; i < SMU_FEATURE_COUNT; i++) {
feature_index = smu_cmn_to_asic_specific_index(smu,
   
CMN2ASIC_MAPPING_FEATURE,
   i);
if (feature_index < 0)
continue;
+
sort_feature[feature_index] = i;
-   hw_feature_count++;
}
 
-   for (i = 0; i < hw_feature_count; i++) {
+   size += sprintf(buf + size, "%-2s. %-20s  %-3s : %-s\n",
+   "No", "Feature", "Bit", "State");
+
+   for (i = 0; i < SMU_FEATURE_COUNT; i++) {
+   if (sort_feature[i] < 0)
+   continue;
+
size += sprintf(buf + size, "%02d. %-20s (%2d) : %s\n",
-  count++,
-  smu_get_feature_name(smu, sort_feature[i]),
-  i,
-  !!smu_cmn_feature_is_enabled(smu, 
sort_feature[i]) ?
-  "enabled" : "disabled");
+   count++,
+   smu_get_feature_name(smu, sort_feature[i]),
+   i,
+   !!smu_cmn_feature_is_enabled(smu, 
sort_feature[i]) ?
+   "enabled" : "disabled");
}
 
return size;
-- 
2.17.1
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RE: [PATCH] drm/amd/pm: support runtime pptable update for sienna_cichlid etc.

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Jiansong Chen  
Sent: Monday, September 14, 2020 4:10 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Feng, Kenneth ; Quan, 
Evan ; Chen, Jiansong (Simon) 
Subject: [PATCH] drm/amd/pm: support runtime pptable update for sienna_cichlid 
etc.

This avoids smu issue when enabling runtime pptable update for sienna_cichlid 
and so on. Runtime pptable udpate is needed for test and debug purpose.

Signed-off-by: Jiansong Chen 
Change-Id: I70b704ab4d6efd169f579c392e5dbc2737dc1fb2
---
 drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c 
b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 7a55ece1f124..7618f9972b8c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1129,7 +1129,7 @@ static int smu_disable_dpms(struct smu_context *smu)
 */
if (smu->uploading_custom_pp_table &&
(adev->asic_type >= CHIP_NAVI10) &&
-   (adev->asic_type <= CHIP_NAVI12))
+   (adev->asic_type <= CHIP_NAVY_FLOUNDER))
return 0;
 
/*
@@ -1214,7 +1214,9 @@ static int smu_hw_fini(void *handle)  int 
smu_reset(struct smu_context *smu)  {
struct amdgpu_device *adev = smu->adev;
-   int ret = 0;
+   int ret;
+
+   amdgpu_gfx_off_ctrl(smu->adev, false);
 
ret = smu_hw_fini(adev);
if (ret)
@@ -1225,8 +1227,12 @@ int smu_reset(struct smu_context *smu)
return ret;
 
ret = smu_late_init(adev);
+   if (ret)
+   return ret;
 
-   return ret;
+   amdgpu_gfx_off_ctrl(smu->adev, true);
+
+   return 0;
 }
 
 static int smu_suspend(void *handle)
--
2.25.1
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RE: [PATCH] drm/amd/pm: correct the thermal alert temperature limit settings

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 



-Original Message-
From: Quan, Evan  
Sent: Tuesday, August 25, 2020 10:55 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Feng, Kenneth 
; Quan, Evan 
Subject: [PATCH] drm/amd/pm: correct the thermal alert temperature limit 
settings

Do the maths in celsius degree. This can fix the issues caused by the changes 
below:

drm/amd/pm: correct Vega20 swctf limit setting
drm/amd/pm: correct Vega12 swctf limit setting
drm/amd/pm: correct Vega10 swctf limit setting

Change-Id: Ia49936240106a3172d10ffc44e51d3c9ba00763d
Signed-off-by: Evan Quan 
---
 .../drm/amd/pm/powerplay/hwmgr/vega10_thermal.c   | 15 +++
 .../drm/amd/pm/powerplay/hwmgr/vega12_thermal.c   | 15 +++
 .../drm/amd/pm/powerplay/hwmgr/vega20_thermal.c   | 15 +++
 3 files changed, 21 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
index ce9514c881ec..d572ba4ec9b1 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_thermal.c
@@ -367,14 +367,13 @@ static int vega10_thermal_set_temperature_range(struct 
pp_hwmgr *hwmgr,
(struct phm_ppt_v2_information *)(hwmgr->pptable);
struct phm_tdp_table *tdp_table = pp_table_info->tdp_table;
struct amdgpu_device *adev = hwmgr->adev;
-   int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP *
-   PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-   int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP *
-   PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP;
+   int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP;
uint32_t val;
 
-   if (low < range->min)
-   low = range->min;
+   /* compare them in unit celsius degree */
+   if (low < range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
+   low = range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
if (high > tdp_table->usSoftwareShutdownTemp)
high = tdp_table->usSoftwareShutdownTemp;
 
@@ -385,8 +384,8 @@ static int vega10_thermal_set_temperature_range(struct 
pp_hwmgr *hwmgr,
 
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
-   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / 
PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / 
PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
+   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
+   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &
(~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &
(~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c 
b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
index e755fc0c9886..7ace439dcde7 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_thermal.c
@@ -173,14 +173,13 @@ static int vega12_thermal_set_temperature_range(struct 
pp_hwmgr *hwmgr,
struct phm_ppt_v3_information *pptable_information =
(struct phm_ppt_v3_information *)hwmgr->pptable;
struct amdgpu_device *adev = hwmgr->adev;
-   int low = VEGA12_THERMAL_MINIMUM_ALERT_TEMP *
-   PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
-   int high = VEGA12_THERMAL_MAXIMUM_ALERT_TEMP *
-   PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
+   int low = VEGA12_THERMAL_MINIMUM_ALERT_TEMP;
+   int high = VEGA12_THERMAL_MAXIMUM_ALERT_TEMP;
uint32_t val;
 
-   if (low < range->min)
-   low = range->min;
+   /* compare them in unit celsius degree */
+   if (low < range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
+   low = range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
if (high > pptable_information->us_software_shutdown_temp)
high = pptable_information->us_software_shutdown_temp;
 
@@ -191,8 +190,8 @@ static int vega12_thermal_set_temperature_range(struct 
pp_hwmgr *hwmgr,
 
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
-   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high / 
PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
-   val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low / 
PP_TEMPERATURE_UNITS_PER_CENTIGRADES));
+   val = REG_SET_FIELD(

RE: [PATCH] drm/amd/pm: enable run_btc callback for sienna_cichlid

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Jiansong Chen  
Sent: Friday, August 21, 2020 11:51 AM
To: amd-gfx@lists.freedesktop.org
Cc: Gao, Likun ; Zhou1, Tao ; Feng, 
Kenneth ; Chen, Jiansong (Simon) 
Subject: [PATCH] drm/amd/pm: enable run_btc callback for sienna_cichlid

DC BTC support for sienna_cichlid is added, it provides the DC tolerance and 
aging measurements.

Signed-off-by: Jiansong Chen 
Change-Id: I93b439b99c1bf365194d61385eb0fe0251f27041
---
 drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
index 8ffa8b71b75f..d2320ce7ef0d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
@@ -95,6 +95,7 @@ static struct cmn2asic_msg_mapping 
sienna_cichlid_message_map[SMU_MSG_MAX_COUNT]
MSG_MAP(TransferTableSmu2Dram,  
PPSMC_MSG_TransferTableSmu2Dram,   0),
MSG_MAP(TransferTableDram2Smu,  
PPSMC_MSG_TransferTableDram2Smu,   0),
MSG_MAP(UseDefaultPPTable,  PPSMC_MSG_UseDefaultPPTable,
   0),
+   MSG_MAP(RunDcBtc,   PPSMC_MSG_RunDcBtc, 
   0),
MSG_MAP(EnterBaco,  PPSMC_MSG_EnterBaco,
   0),
MSG_MAP(SetSoftMinByFreq,   PPSMC_MSG_SetSoftMinByFreq, 
   0),
MSG_MAP(SetSoftMaxByFreq,   PPSMC_MSG_SetSoftMaxByFreq, 
   0),
@@ -1735,6 +1736,11 @@ static int sienna_cichlid_get_dpm_ultimate_freq(struct 
smu_context *smu,
return ret;
 }
 
+static int sienna_cichlid_run_btc(struct smu_context *smu) {
+   return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL); }
+
 static bool sienna_cichlid_is_baco_supported(struct smu_context *smu)  {
struct amdgpu_device *adev = smu->adev; @@ -2792,6 +2798,7 @@ static 
const struct pptable_funcs sienna_cichlid_ppt_funcs = {
.mode1_reset = smu_v11_0_mode1_reset,
.get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
+   .run_btc = sienna_cichlid_run_btc,
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
--
2.25.1
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RE: [PATCH] Revert "drm/amdgpu: disable gfxoff for navy_flounder"

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Jiansong Chen  
Sent: Monday, August 17, 2020 10:46 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhou1, Tao ; Feng, Kenneth ; Chen, 
Jiansong (Simon) 
Subject: [PATCH] Revert "drm/amdgpu: disable gfxoff for navy_flounder"

This reverts commit 6a72ad7e387c6fec821c230fda3460f79fc0f877.
Newly released sdma fw (51.52) provides a fix for the issue.
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index e87d43537013..e527be22a3d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3610,9 +3610,6 @@ static void gfx_v10_0_check_gfxoff_flag(struct 
amdgpu_device *adev)
if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
break;
-   case CHIP_NAVY_FLOUNDER:
-   adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
-   break;
default:
break;
}
-- 
2.25.1
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Re: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


在 2020/8/6 下午5:42，“Gao, Likun” 写入:

From: Likun Gao 

Update drive if file for sienna_cichlid.

Signed-off-by: Likun Gao 
Change-Id: If405461cfbe0133ceb61fa123272b2e53db99755
---
 .../drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h  | 6 +++---
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h   | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git 
a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index aa2708fccb6d..5ef9c92f57c4 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if
 // any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x34
+#define SMU11_DRIVER_IF_VERSION 0x35

 #define PPTABLE_Sienna_Cichlid_SMU_VERSION 5

@@ -127,7 +127,7 @@
 #define FEATURE_DF_CSTATE_BIT   45
 #define FEATURE_2_STEP_PSTATE_BIT   46
 #define FEATURE_SMNCLK_DPM_BIT  47
-#define FEATURE_SPARE_48_BIT48
+#define FEATURE_PERLINK_GMIDOWN_BIT 48
 #define FEATURE_GFX_EDC_BIT 49
 #define FEATURE_SPARE_50_BIT50
 #define FEATURE_SPARE_51_BIT51
@@ -169,7 +169,7 @@ typedef enum {
 #define DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN   0x0200
 #define DPM_OVERRIDE_DISABLE_MEMORY_TEMPERATURE_READ 0x0400
 #define DPM_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCEFCLK   0x0800
-#define DPM_OVERRIDE_DISABLE_FAST_FCLK_TIMER 0x1000
+#define DPM_OVERRIDE_ENABLE_FAST_FCLK_TIMER  0x1000
 #define DPM_OVERRIDE_DISABLE_VCN_PG  0x2000
 #define DPM_OVERRIDE_DISABLE_FMAX_VMAX   0x4000

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 6a42331aba8a..737b6d14372c 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV10 0x36
 #define SMU11_DRIVER_IF_VERSION_NV12 0x33
 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x34
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x35
 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x3

 /* MP Apertures */
--
2.25.1


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RE: [PATCH] drm/amd/powerplay: grant Arcturus softmin/max setting on latest PM firmware

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Quan, Evan  
Sent: Wednesday, August 5, 2020 11:24 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Feng, Kenneth 
; Quan, Evan 
Subject: [PATCH] drm/amd/powerplay: grant Arcturus softmin/max setting on 
latest PM firmware

For Arcturus, the softmin/max settings from driver are permitted on the
latest(54.26 later) SMU firmware. Thus enabling them in driver.

Change-Id: Iff9ac326610075aa7f61cb89c64d2c4128678755
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/arcturus_ppt.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c 
b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index a2ba6633fc21..73de3c013834 100644
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -942,9 +942,10 @@ static int arcturus_force_clk_levels(struct smu_context 
*smu,
return ret;
}
 
-   if (smu_version >= 0x361200) {
+   if ((smu_version >= 0x361200) &&
+   (smu_version <= 0x361a00)) {
dev_err(smu->adev->dev, "Forcing clock level is not supported 
with "
-  "54.18 and onwards SMU firmwares\n");
+  "54.18 - 54.26(included) SMU firmwares\n");
return -EOPNOTSUPP;
}
 
@@ -1437,9 +1438,10 @@ static int arcturus_set_performance_level(struct 
smu_context *smu,
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
-   if (smu_version >= 0x361200) {
+   if ((smu_version >= 0x361200) &&
+   (smu_version <= 0x361a00)) {
dev_err(smu->adev->dev, "Forcing clock level is not 
supported with "
-  "54.18 and onwards SMU firmwares\n");
+  "54.18 - 54.26(included) SMU firmwares\n");
return -EOPNOTSUPP;
}
break;
-- 
2.28.0
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Re: [PATCH] drm/amd/powerplay: update driver if version for navy_flounder

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


在 2020/7/28 下午7:21，“Jiansong Chen” 写入:

It's in accordance with pmfw 65.5.0 for navy_flounder.

Signed-off-by: Jiansong Chen 
Change-Id: I984a1147030264adbc02230e2e1dd416d4ad63b0
---
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 9504f9954fd3..6a42331aba8a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -31,7 +31,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV12 0x33
 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x34
-#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x2
+#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x3

 /* MP Apertures */
 #define MP0_Public0x0380
--
2.17.1


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RE: [PATCH 1/2] drm/amd/swsmu: allow asic to handle sensor type by itself

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 



-Original Message-
From: Wang, Kevin(Yang)  
Sent: Monday, July 27, 2020 11:05 AM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Wang, Kevin(Yang) 

Subject: [PATCH 1/2] drm/amd/swsmu: allow asic to handle sensor type by itself

1. allow asic to handle sensor type by itself.
2. if not, use smu common sensor to handle it.

Signed-off-by: Kevin Wang 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 3b427fa099fe..55463e7a11e2 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1948,6 +1948,10 @@ int smu_read_sensor(struct smu_context *smu,
 
mutex_lock(>mutex);
 
+   if (smu->ppt_funcs->read_sensor)
+   if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
+   goto unlock;
+
switch (sensor) {
case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
*((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 
100; @@ -1978,11 +1982,12 @@ int smu_read_sensor(struct smu_context *smu,
*size = 4;
break;
default:
-   if (smu->ppt_funcs->read_sensor)
-   ret = smu->ppt_funcs->read_sensor(smu, sensor, data, 
size);
+   *size = 0;
+   ret = -EOPNOTSUPP;
break;
}
 
+unlock:
mutex_unlock(>mutex);
 
return ret;
--
2.27.0
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Re: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


在 2020/7/24 下午5:39，“Gao, Likun” 写入:

From: Likun Gao 

Update sienna_cichlid driver if header and related files.
Support new smu metrics for pre & postDS frequency.

Signed-off-by: Likun Gao 
Change-Id: I5446256fd7082a1d51df4ade3828bf5fa1ea3e7f
---
 .../inc/smu11_driver_if_sienna_cichlid.h  | 21 +--
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  2 +-
 .../drm/amd/powerplay/sienna_cichlid_ppt.c| 11 +++---
 3 files changed, 24 insertions(+), 10 deletions(-)

diff --git 
a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index b2232e24d82f..aa2708fccb6d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if
 // any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x33
+#define SMU11_DRIVER_IF_VERSION 0x34

 #define PPTABLE_Sienna_Cichlid_SMU_VERSION 5

@@ -968,9 +968,15 @@ typedef struct {

 typedef struct {
   uint32_t CurrClock[PPCLK_COUNT];
-  uint16_t AverageGfxclkFrequency;
-  uint16_t AverageFclkFrequency;
-  uint16_t AverageUclkFrequency  ;
+
+  uint16_t AverageGfxclkFrequencyPreDs;
+  uint16_t AverageGfxclkFrequencyPostDs;
+  uint16_t AverageFclkFrequencyPreDs;
+  uint16_t AverageFclkFrequencyPostDs;
+  uint16_t AverageUclkFrequencyPreDs  ;
+  uint16_t AverageUclkFrequencyPostDs  ;
+
+
   uint16_t AverageGfxActivity;
   uint16_t AverageUclkActivity   ;
   uint8_t  CurrSocVoltageOffset  ;
@@ -988,6 +994,7 @@ typedef struct {
   uint16_t TemperatureLiquid0;
   uint16_t TemperatureLiquid1;
   uint16_t TemperaturePlx;
+  uint16_t Padding16 ;
   uint32_t ThrottlerStatus   ;

   uint8_t  LinkDpmLevel;
@@ -1006,8 +1013,10 @@ typedef struct {
   uint16_t AverageDclk0Frequency  ;
   uint16_t AverageVclk1Frequency  ;
   uint16_t AverageDclk1Frequency  ;
-  uint16_t VcnActivityPercentage ; //place holder, David N. to provide 
full sequence
-  uint16_t padding16_2;
+  uint16_t VcnActivityPercentage  ; //place holder, David N. to provide 
full sequence
+  uint8_t  PcieRate   ;
+  uint8_t  PcieWidth  ;
+
 } SmuMetrics_t;

 typedef struct {
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 429f5aa8924a..9504f9954fd3 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV10 0x36
 #define SMU11_DRIVER_IF_VERSION_NV12 0x33
 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x34
 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x2

 /* MP Apertures */
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index dcc5d25a7894..f64a1be94cb8 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -70,6 +70,8 @@
 FEATURE_MASK(FEATURE_DPM_FCLK_BIT) | \
 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))

+#define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
+
 static struct cmn2asic_msg_mapping 
sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
 MSG_MAP(TestMessage,PPSMC_MSG_TestMessage, 1),
 MSG_MAP(GetSmuVersion,PPSMC_MSG_GetSmuVersion,   1),
@@ -443,13 +445,16 @@ static int sienna_cichlid_get_smu_metrics_data(struct 
smu_context *smu,
 *value = metrics->CurrClock[PPCLK_DCEFCLK];
 break;
 case METRICS_AVERAGE_GFXCLK:
-*value = metrics->AverageGfxclkFrequency;
+if (metrics->AverageGfxActivity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
+*value = metrics->AverageGfxclkFrequencyPostDs;
+else
+*value = metrics->AverageGfxclkFrequencyPreDs;
 break;
 case METRICS_AVERAGE_FCLK:
-*value = metrics->AverageFclkFrequency;
+*value = metrics->AverageFclkFrequencyPostDs;
 break;
 case METRICS_AVERAGE_UCLK:
-*value = metrics->AverageUclkFrequency;
+*value = metrics->AverageUclkFrequencyPostDs;
 break;
 case METRICS_AVERAGE_GFXACTIVITY:
 *value = metrics->AverageGfxActivity;
--
2.25.1


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RE: [PATCH] Revert "drm/amd/powerplay: drop unnecessary message support check"

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Zhu, Changfeng  
Sent: Wednesday, July 22, 2020 4:01 PM
To: amd-gfx@lists.freedesktop.org; Feng, Kenneth ; Huang, 
Ray 
Cc: Zhu, Changfeng 
Subject: [PATCH] Revert "drm/amd/powerplay: drop unnecessary message support 
check"

From: changzhu 

From: Changfeng 

The below 3 messages are not supported on Renoir SMU_MSG_PrepareMp1ForShutdown 
SMU_MSG_PrepareMp1ForUnload SMU_MSG_PrepareMp1ForReset

It needs to revert patch:
drm/amd/powerplay: drop unnecessary message support check to avoid set mp1 
state fail during gpu reset on renoir.

Change-Id: Ib34d17ab88e1c88173827cca962d8154ad883ab7
Signed-off-by: changfeng 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 9 +
 drivers/gpu/drm/amd/powerplay/smu_cmn.h| 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 838a369c9ec3..f778b00e49eb 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -34,6 +34,7 @@
 #include "sienna_cichlid_ppt.h"
 #include "renoir_ppt.h"
 #include "amd_pcie.h"
+#include "smu_cmn.h"
 
 /*
  * DO NOT use these for err/warn/info/debug messages.
@@ -1589,6 +1590,14 @@ int smu_set_mp1_state(struct smu_context *smu,
return 0;
}
 
+   /* some asics may not support those messages */
+   if (smu_cmn_to_asic_specific_index(smu,
+  CMN2ASIC_MAPPING_MSG,
+  msg) < 0) {
+   mutex_unlock(>mutex);
+   return 0;
+   }
+
ret = smu_send_smc_msg(smu, msg, NULL);
if (ret)
dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n"); diff --git 
a/drivers/gpu/drm/amd/powerplay/smu_cmn.h 
b/drivers/gpu/drm/amd/powerplay/smu_cmn.h
index 98face8c5fd6..f9e63f18b157 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_cmn.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_cmn.h
@@ -25,7 +25,7 @@
 
 #include "amdgpu_smu.h"
 
-#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3) || 
defined(SWSMU_CODE_LAYER_L4)
+#if defined(SWSMU_CODE_LAYER_L1) || defined(SWSMU_CODE_LAYER_L2) || 
+defined(SWSMU_CODE_LAYER_L3) || defined(SWSMU_CODE_LAYER_L4)
 int smu_cmn_send_smc_msg_with_param(struct smu_context *smu,
enum smu_message_type msg,
uint32_t param,
--
2.17.1
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RE: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


Best Regards
Kenneth

-Original Message-
From: Gao, Likun  
Sent: Friday, July 10, 2020 11:10 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking ; Feng, Kenneth 
; Gao, Likun 
Subject: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid

From: Likun Gao 

Update sienna_cichlid driver if header and related files.

Signed-off-by: Likun Gao 
Change-Id: If303e7fca32ebf922ee5d918855bbaca8dc61d38
---
 .../inc/smu11_driver_if_sienna_cichlid.h| 17 +
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h   |  2 +-
 .../gpu/drm/amd/powerplay/sienna_cichlid_ppt.c  |  1 -
 3 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index 302c2bcf9404..b2232e24d82f 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,9 +27,9 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if  // any structure is 
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x32
+#define SMU11_DRIVER_IF_VERSION 0x33
 
-#define PPTABLE_Sienna_Cichlid_SMU_VERSION 4
+#define PPTABLE_Sienna_Cichlid_SMU_VERSION 5
 
 #define NUM_GFXCLK_DPM_LEVELS  16
 #define NUM_SMNCLK_DPM_LEVELS  2
@@ -128,7 +128,7 @@
 #define FEATURE_2_STEP_PSTATE_BIT   46
 #define FEATURE_SMNCLK_DPM_BIT  47
 #define FEATURE_SPARE_48_BIT48
-#define FEATURE_SPARE_49_BIT49
+#define FEATURE_GFX_EDC_BIT 49
 #define FEATURE_SPARE_50_BIT50
 #define FEATURE_SPARE_51_BIT51
 #define FEATURE_SPARE_52_BIT52
@@ -564,6 +564,12 @@ typedef enum {
   TDC_THROTTLER_COUNT
 } TDC_THROTTLER_e;
 
+typedef enum {
+  CUSTOMER_VARIANT_ROW,
+  CUSTOMER_VARIANT_FALCON,
+  CUSTOMER_VARIANT_COUNT,
+} CUSTOMER_VARIANT_e;
+
 // Used for 2-step UCLK DPM change workaround  typedef struct {
   uint16_t Fmin;
@@ -786,7 +792,10 @@ typedef struct {
   QuadraticInt_tReservedEquation3; 
 
   // SECTION: Sku Reserved
-  uint32_t SkuReserved[15];
+  uint8_t  CustomerVariant;
+  uint8_t  Spare[3];
+  uint32_t SkuReserved[14];
+
 
   // MAJOR SECTION: BOARD PARAMETERS
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index d07bf4fe6e4a..b2f65438ad8d 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV10 0x36  #define 
SMU11_DRIVER_IF_VERSION_NV12 0x33  #define SMU11_DRIVER_IF_VERSION_NV14 0x36 
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x32
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33
 
 /* MP Apertures */
 #define MP0_Public 0x0380
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c 
b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index dc5ca9121db5..3efa41444ddf 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -2317,7 +2317,6 @@ static void sienna_cichlid_dump_pptable(struct 
smu_context *smu)
dev_info(smu->adev->dev, "SkuReserved[11] = 0x%x\n", 
pptable->SkuReserved[11]);
dev_info(smu->adev->dev, "SkuReserved[12] = 0x%x\n", 
pptable->SkuReserved[12]);
dev_info(smu->adev->dev, "SkuReserved[13] = 0x%x\n", 
pptable->SkuReserved[13]);
-   dev_info(smu->adev->dev, "SkuReserved[14] = 0x%x\n", 
pptable->SkuReserved[14]);
 
dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", 
pptable->GamingClk[0]);
dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", 
pptable->GamingClk[1]);
--
2.25.1
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RE: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


Best Regards
Kenneth

-Original Message-
From: Gao, Likun  
Sent: Wednesday, June 3, 2020 12:36 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Quan, Evan ; Gao, 
Likun 
Subject: [PATCH] drm/amd/powerplay: update driver if file for sienna_cichlid

From: Likun Gao 

Update sienna_cichlid driver if header file to match pptable changes.

Signed-off-by: Likun Gao 
Change-Id: Ie0652935d512124c03f16ae75c44e134567ef5da
---
 .../inc/smu11_driver_if_sienna_cichlid.h| 17 ++---
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h   |  2 +-
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index bdffba1f0086..5322f6da3071 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
 // *** IMPORTANT ***
 // SMU TEAM: Always increment the interface version if  // any structure is 
changed in this file -#define SMU11_DRIVER_IF_VERSION 0x30
+#define SMU11_DRIVER_IF_VERSION 0x31
 
 #define PPTABLE_Sienna_Cichlid_SMU_VERSION 4
 
@@ -914,12 +914,14 @@ typedef struct {
   uint16_t GfxActivityLpfTau;
   uint16_t UclkActivityLpfTau;
   uint16_t SocketPowerLpfTau;  
+  uint16_t VcnClkAverageLpfTau;
+  uint16_t padding16; 
 } DriverSmuConfig_t;
 
 typedef struct {
   DriverSmuConfig_t DriverSmuConfig;
 
-  uint32_t Spare[8];  
+  uint32_t Spare[7];  
   // Padding - ignore
   uint32_t MmHubPadding[8]; // SMU internal use
 } DriverSmuConfigExternal_t;
@@ -984,11 +986,20 @@ typedef struct {
   uint8_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT];
   uint8_t D3HotExitCountPerMode[D3HOT_SEQUENCE_COUNT];
   uint8_t ArmMsgReceivedCountPerMode[D3HOT_SEQUENCE_COUNT];
+
+  //PMFW-4362
+  uint32_t EnergyAccumulator;
+  uint16_t AverageVclk0Frequency  ;
+  uint16_t AverageDclk0Frequency  ;
+  uint16_t AverageVclk1Frequency  ;
+  uint16_t AverageDclk1Frequency  ;
+  uint16_t VcnActivityPercentage ; //place holder, David N. to provide 
+ full sequence  uint16_t padding16_2;
 } SmuMetrics_t;
 
 typedef struct {
   SmuMetrics_t SmuMetrics;
-  uint32_t Spare[5];
+  uint32_t Spare[1];
 
   // Padding - ignore
   uint32_t MmHubPadding[8]; // SMU internal use  
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 4ad3f07891fe..282eb45e7b86 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -31,7 +31,7 @@
 #define SMU11_DRIVER_IF_VERSION_NV10 0x36  #define 
SMU11_DRIVER_IF_VERSION_NV12 0x33  #define SMU11_DRIVER_IF_VERSION_NV14 0x36 
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x30
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x31
 
 /* MP Apertures */
 #define MP0_Public 0x0380
--
2.25.1
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RE: [PATCH 2/2] drm/amd/powerplay: bump the NAVI10 smu-driver if version

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Quan, Evan  
Sent: Monday, April 13, 2020 4:54 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Feng, Kenneth 
; Quan, Evan 
Subject: [PATCH 2/2] drm/amd/powerplay: bump the NAVI10 smu-driver if version

To fit the latest SMC firmware 42.53 and eliminate the warning on driver 
loading.

Change-Id: I3f524d03e53ec6778b7118ef72652a538eec4ace
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 674e426ed59b..e786d63b1e79 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -28,7 +28,7 @@
 #define SMU11_DRIVER_IF_VERSION_INV 0x  #define 
SMU11_DRIVER_IF_VERSION_VG20 0x13  #define SMU11_DRIVER_IF_VERSION_ARCT 0x12 
-#define SMU11_DRIVER_IF_VERSION_NV10 0x35
+#define SMU11_DRIVER_IF_VERSION_NV10 0x36
 #define SMU11_DRIVER_IF_VERSION_NV12 0x33  #define 
SMU11_DRIVER_IF_VERSION_NV14 0x36
 
--
2.26.0
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RE: [PATCH 1/2] drm/amd/powerplay: revise the way to retrieve the board parameters

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Quan, Evan  
Sent: Monday, April 13, 2020 4:54 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Feng, Kenneth 
; Quan, Evan 
Subject: [PATCH 1/2] drm/amd/powerplay: revise the way to retrieve the board 
parameters

It can support different NV1x ASIC better. And this can guard no member got 
missing.

Change-Id: Id5e6608f6be1b31ef1c0a5c1d399da295524ff43
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/include/atomfirmware.h | 102 +  
drivers/gpu/drm/amd/powerplay/navi10_ppt.c |  99 ++--
 2 files changed, 130 insertions(+), 71 deletions(-)

diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h 
b/drivers/gpu/drm/amd/include/atomfirmware.h
index 70146518174c..a6f6e6bf5992 100644
--- a/drivers/gpu/drm/amd/include/atomfirmware.h
+++ b/drivers/gpu/drm/amd/include/atomfirmware.h
@@ -1876,6 +1876,108 @@ struct atom_smc_dpm_info_v4_6
   uint32_t   boardreserved[10];
 };
 
+struct atom_smc_dpm_info_v4_7
+{
+  struct   atom_common_table_header  table_header;
+// SECTION: BOARD PARAMETERS
+// I2C Control
+  struct smudpm_i2c_controller_config_v2  I2cControllers[8];
+
+  // SVI2 Board Parameters
+  uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will 
request. Multiple steps are taken if voltage change exceeds this value.
+  uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will 
request. Multiple steps are taken if voltage change exceeds this value.
+
+  uint8_t  VddGfxVrMapping;   // Use VR_MAPPING* bitfields
+  uint8_t  VddSocVrMapping;   // Use VR_MAPPING* bitfields
+  uint8_t  VddMem0VrMapping;  // Use VR_MAPPING* bitfields
+  uint8_t  VddMem1VrMapping;  // Use VR_MAPPING* bitfields
+
+  uint8_t  GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in 
ULV mode
+  uint8_t  SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in 
ULV mode
+  uint8_t  ExternalSensorPresent; // External RDI connected to TMON (aka 
TEMP IN)
+  uint8_t  Padding8_V;
+
+  // Telemetry Settings
+  uint16_t GfxMaxCurrent;   // in Amps
+  uint8_t  GfxOffset;   // in Amps
+  uint8_t  Padding_TelemetryGfx;
+  uint16_t SocMaxCurrent;   // in Amps
+  uint8_t  SocOffset;   // in Amps
+  uint8_t  Padding_TelemetrySoc;
+
+  uint16_t Mem0MaxCurrent;   // in Amps
+  uint8_t  Mem0Offset;   // in Amps
+  uint8_t  Padding_TelemetryMem0;
+
+  uint16_t Mem1MaxCurrent;   // in Amps
+  uint8_t  Mem1Offset;   // in Amps
+  uint8_t  Padding_TelemetryMem1;
+
+  // GPIO Settings
+  uint8_t  AcDcGpio;// GPIO pin configured for AC/DC switching
+  uint8_t  AcDcPolarity;// GPIO polarity for AC/DC switching
+  uint8_t  VR0HotGpio;  // GPIO pin configured for VR0 HOT event
+  uint8_t  VR0HotPolarity;  // GPIO polarity for VR0 HOT event
+
+  uint8_t  VR1HotGpio;  // GPIO pin configured for VR1 HOT event
+  uint8_t  VR1HotPolarity;  // GPIO polarity for VR1 HOT event
+  uint8_t  GthrGpio;// GPIO pin configured for GTHR Event
+  uint8_t  GthrPolarity;// replace GPIO polarity for GTHR
+
+  // LED Display Settings
+  uint8_t  LedPin0; // GPIO number for LedPin[0]
+  uint8_t  LedPin1; // GPIO number for LedPin[1]
+  uint8_t  LedPin2; // GPIO number for LedPin[2]
+  uint8_t  padding8_4;
+
+  // GFXCLK PLL Spread Spectrum
+  uint8_t  PllGfxclkSpreadEnabled;   // on or off
+  uint8_t  PllGfxclkSpreadPercent;   // Q4.4
+  uint16_t PllGfxclkSpreadFreq;  // kHz
+
+  // GFXCLK DFLL Spread Spectrum
+  uint8_t  DfllGfxclkSpreadEnabled;   // on or off
+  uint8_t  DfllGfxclkSpreadPercent;   // Q4.4
+  uint16_t DfllGfxclkSpreadFreq;  // kHz
+
+  // UCLK Spread Spectrum
+  uint8_t  UclkSpreadEnabled;   // on or off
+  uint8_t  UclkSpreadPercent;   // Q4.4
+  uint16_t UclkSpreadFreq;  // kHz
+
+  // SOCCLK Spread Spectrum
+  uint8_t  SoclkSpreadEnabled;   // on or off
+  uint8_t  SocclkSpreadPercent;   // Q4.4
+  uint16_t SocclkSpreadFreq;  // kHz
+
+  // Total board power
+  uint16_t TotalBoardPower; //Only needed for TCP Estimated case, 
where TCP = TGP+Total Board Power
+  uint16_t BoardPadding;
+
+  // Mvdd Svi2 Div Ratio Setting
+  uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 
fractional bits (Q16.16)
+
+  // GPIO pins for I2C communications with 2nd controller for Input Telemetry 
Sequence
+  uint8_t  GpioI2cScl;  // Serial Clock
+  uint8_t  GpioI2cSda;  // Serial Data
+  uint16_t GpioPadding;
+
+  // Additional LED Display Settings
+  uint8_t  LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed
+  uint8_t  LedPin4; // GPIO number for LedPin[4] - PMFW Error 
Status
+  uint16_t

RE: [PATCH] drm/amd/powerplay: update Arcturus smu-driver if header

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Quan, Evan  
Sent: Monday, April 13, 2020 6:57 PM
To: amd-gfx@lists.freedesktop.org
Cc: Feng, Kenneth ; Quan, Evan 
Subject: [PATCH] drm/amd/powerplay: update Arcturus smu-driver if header

To fit the latest PMFW.

Change-Id: I1ebc5a4c3386e07a9fed73e4bec2c5d1ab8d4b23
Signed-off-by: Evan Quan 
---
 .../amd/powerplay/inc/smu11_driver_if_arcturus.h  | 15 +--
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h |  2 +-
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
index ce5b5011c122..8b82059d97e7 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
@@ -82,8 +82,8 @@
 // Other
 #define FEATURE_OUT_OF_BAND_MONITOR_BIT 24  #define 
FEATURE_TEMP_DEPENDENT_VMIN_BIT 25
+#define FEATURE_PER_PART_VMIN_BIT   26
 
-#define FEATURE_SPARE_26_BIT26
 #define FEATURE_SPARE_27_BIT27
 #define FEATURE_SPARE_28_BIT28
 #define FEATURE_SPARE_29_BIT29
@@ -154,6 +154,7 @@
 
 #define FEATURE_OUT_OF_BAND_MONITOR_MASK  (1 << 
FEATURE_OUT_OF_BAND_MONITOR_BIT   )
 #define FEATURE_TEMP_DEPENDENT_VMIN_MASK  (1 << 
FEATURE_TEMP_DEPENDENT_VMIN_BIT )
+#define FEATURE_PER_PART_VMIN_MASK(1 << FEATURE_PER_PART_VMIN_BIT  
  )
 
 
 //FIXME need updating
@@ -628,8 +629,14 @@ typedef struct {
   uint16_t BasePerformanceFrequencyCap;   //In Mhz
   uint16_t MaxPerformanceFrequencyCap;//In Mhz
 
+  // Per-Part Vmin
+  uint16_t VDDGFX_VminLow;// mv Q2
+  uint16_t VDDGFX_TVminLow;   //Celcius
+  uint16_t VDDGFX_VminLow_HiTemp; // mv Q2  uint16_t 
+ VDDGFX_VminLow_LoTemp; // mv Q2
+
   // SECTION: Reserved
-  uint32_t Reserved[9];
+  uint32_t Reserved[7];
 
   // SECTION: BOARD PARAMETERS
 
@@ -869,6 +876,10 @@ typedef struct {
   uint8_t   Mem_DownHystLimit;
   uint16_t  Mem_Fps;
 
+  uint32_t  BusyThreshold;  // Q16
+  uint32_t  BusyHyst;
+  uint32_t  IdleHyst;
+
   uint32_t  MmHubPadding[8]; // SMU internal use  } 
DpmActivityMonitorCoeffInt_t;
 
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index e786d63b1e79..464d40983de9 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -27,7 +27,7 @@
 
 #define SMU11_DRIVER_IF_VERSION_INV 0x  #define 
SMU11_DRIVER_IF_VERSION_VG20 0x13 -#define SMU11_DRIVER_IF_VERSION_ARCT 0x12
+#define SMU11_DRIVER_IF_VERSION_ARCT 0x14
 #define SMU11_DRIVER_IF_VERSION_NV10 0x36  #define 
SMU11_DRIVER_IF_VERSION_NV12 0x33  #define SMU11_DRIVER_IF_VERSION_NV14 0x36
--
2.26.0
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RE: [PATCH 1/2] drm/amd/powerplay: correct i2c eeprom init/fini sequence

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: Monday, April 13, 2020 4:24 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan 
Subject: [PATCH 1/2] drm/amd/powerplay: correct i2c eeprom init/fini sequence

[CAUTION: External Email]

As data transfer may starts immediately after i2c eeprom init completed. Thus 
i2c eeprom should be initialized after SMU ready. And i2c data transfer should 
be prohibited when SMU down. That is the i2c eeprom fini sequence needs to be 
updated also.

Change-Id: I8444c05b51e67347841641fe5768d3126d089792
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 22 ++-
 .../gpu/drm/amd/powerplay/inc/amdgpu_smu.h|  5 -
 drivers/gpu/drm/amd/powerplay/smu_internal.h  |  5 +
 3 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index e8b27fab6aa1..b69e8d6c0a96 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -932,13 +932,6 @@ static int smu_sw_init(void *handle)
return ret;
}

-   if (adev->smu.ppt_funcs->i2c_eeprom_init) {
-   ret = smu_i2c_eeprom_init(smu, >pm.smu_i2c);
-
-   if (ret)
-   return ret;
-   }
-
return 0;
 }

@@ -948,9 +941,6 @@ static int smu_sw_fini(void *handle)
struct smu_context *smu = >smu;
int ret;

-   if (adev->smu.ppt_funcs->i2c_eeprom_fini)
-   smu_i2c_eeprom_fini(smu, >pm.smu_i2c);
-
kfree(smu->irq_source);
smu->irq_source = NULL;

@@ -1366,6 +1356,10 @@ static int smu_hw_init(void *handle)
if (ret)
goto failed;

+   ret = smu_i2c_eeprom_init(smu, >pm.smu_i2c);
+   if (ret)
+   goto failed;
+
if (!smu->pm_enabled)
adev->pm.dpm_enabled = false;
else
@@ -1403,6 +1397,8 @@ static int smu_hw_fini(void *handle)
if (!smu->pm_enabled)
return 0;

+   smu_i2c_eeprom_fini(smu, >pm.smu_i2c);
+
if (!amdgpu_sriov_vf(adev)){
ret = smu_stop_thermal_control(smu);
if (ret) {
@@ -1542,6 +1538,8 @@ static int smu_suspend(void *handle)
if (!smu->pm_enabled)
return 0;

+   smu_i2c_eeprom_fini(smu, >pm.smu_i2c);
+
if(!amdgpu_sriov_vf(adev)) {
ret = smu_disable_dpm(smu);
if (ret)
@@ -1587,6 +1585,10 @@ static int smu_resume(void *handle)
if (ret)
goto failed;

+   ret = smu_i2c_eeprom_init(smu, >pm.smu_i2c);
+   if (ret)
+   goto failed;
+
if (smu->is_apu)
smu_set_gfx_cgpg(>smu, true);

diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 
b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
index ae2c318dd6fa..30643b9b5b3b 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
@@ -580,11 +580,6 @@ int smu_check_fw_status(struct smu_context *smu);

 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);

-#define smu_i2c_eeprom_init(smu, control) \
-   ((smu)->ppt_funcs->i2c_eeprom_init ? 
(smu)->ppt_funcs->i2c_eeprom_init((control)) : -EINVAL)
-#define smu_i2c_eeprom_fini(smu, control) \
-   ((smu)->ppt_funcs->i2c_eeprom_fini ? 
(smu)->ppt_funcs->i2c_eeprom_fini((control)) : -EINVAL)
-
 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed);

 int smu_get_power_limit(struct smu_context *smu, diff --git 
a/drivers/gpu/drm/amd/powerplay/smu_internal.h 
b/drivers/gpu/drm/amd/powerplay/smu_internal.h
index 40c35bcc5a0a..c97444841abc 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_internal.h
+++ b/drivers/gpu/drm/amd/powerplay/smu_internal.h
@@ -214,4 +214,9 @@ static inline int smu_send_smc_msg(struct smu_context *smu, 
enum smu_message_typ  #define smu_set_power_source(smu, power_src) \
((smu)->ppt_funcs->set_power_source ? 
(smu)->ppt_funcs->set_power_source((smu), (power_src)) : 0)

+#define smu_i2c_eeprom_init(smu, control) \
+   ((smu)->ppt_funcs->i2c_eeprom_init ? 
+(smu)->ppt_funcs->i2c_eeprom_init((control)) : 0) #define 
smu_i2c_eeprom_fini(smu, control) \
+   ((smu)->ppt_funcs->i2c_eeprom_fini ? 
+(smu)->ppt_funcs->i2c_eeprom_fini((control)) : 0)
+
 #endif
--
2.26.0

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RE: [PATCH] drm/amd/amdgpu: Correct gfx10's CG sequence

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

This sequence is confirmed in the design document.
Reviewed-by: Kenneth Feng 


-Original Message-
From: Chengming Gui  
Sent: Friday, April 3, 2020 3:14 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan ; Feng, Kenneth ; Yin, 
Tianci (Rico) ; Xu, Feifei ; Zhang, 
Hawking ; Gui, Jack 
Subject: [PATCH] drm/amd/amdgpu: Correct gfx10's CG sequence

Incorrect CG sequence will cause gfx timedout, if we keep switching power 
profile mode (enter profile mod such as PEAK will disable CG, exit profile mode 
EXIT will enable CG) when run Vulkan test case(case used for test: vkexample).

Signed-off-by: Chengming Gui 
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 23 +++
 1 file changed, 15 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 51be7aa..1439dd9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4097,6 +4097,12 @@ static void 
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
 
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
+   /* 0 - Disable some blocks' MGCG */
+   WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe000);
+   WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff00);
+   WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff00);
+   WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff00);
+
/* 1 - RLC_CGTT_MGCG_OVERRIDE */
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK 
| @@ -4136,19 +4142,20 @@ static void 
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
if (def != data)
WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
 
-   /* 2 - disable MGLS in RLC */
+   /* 2 - disable MGLS in CP */
+   data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
+   if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
+   data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
+   WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
+   }
+
+   /* 3 - disable MGLS in RLC */
data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
}
 
-   /* 3 - disable MGLS in CP */
-   data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
-   if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
-   data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
-   WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
-   }
}
 }
 
@@ -4259,7 +4266,7 @@ static int gfx_v10_0_update_gfx_clock_gating(struct 
amdgpu_device *adev,
/* ===  CGCG /CGLS for GFX 3D Only === */
gfx_v10_0_update_3d_clock_gating(adev, enable);
/* ===  MGCG + MGLS === */
-   gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
+   /* gfx_v10_0_update_medium_grain_clock_gating(adev, enable); */
}
 
if (adev->cg_flags &
--
2.7.4
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RE: [PATCH 1/9] drm/amd/powerplay: avoid calling CI specific SMU message implemention

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Series is Reviewed-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: Friday, March 27, 2020 11:42 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan 
Subject: [PATCH 1/9] drm/amd/powerplay: avoid calling CI specific SMU message 
implemention

[CAUTION: External Email]

Prepare for coming lock protection for SMU message issuing.

Change-Id: If5f7615483d9967f9512fba49cc8454a1300ba6c
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 
b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
index 868e2d5f6e62..66289884c8df 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
@@ -2881,7 +2881,7 @@ static int ci_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
if (hwmgr->dpm_level & profile_mode_mask || 
!PP_CAP(PHM_PlatformCaps_UVDDPM))
break;
}
-   ci_send_msg_to_smc_with_parameter(hwmgr, 
PPSMC_MSG_UVDDPM_SetEnabledMask,
+   smum_send_msg_to_smc_with_parameter(hwmgr, 
PPSMC_MSG_UVDDPM_SetEnabledMask,

data->dpm_level_enable_mask.uvd_dpm_enable_mask);

return 0;
@@ -2912,7 +2912,7 @@ static int ci_update_vce_smc_table(struct pp_hwmgr *hwmgr)
if (hwmgr->dpm_level & profile_mode_mask || 
!PP_CAP(PHM_PlatformCaps_VCEDPM))
break;
}
-   ci_send_msg_to_smc_with_parameter(hwmgr, 
PPSMC_MSG_VCEDPM_SetEnabledMask,
+   smum_send_msg_to_smc_with_parameter(hwmgr, 
PPSMC_MSG_VCEDPM_SetEnabledMask,

data->dpm_level_enable_mask.vce_dpm_enable_mask);

return 0;
--
2.26.0

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RE: [PATCH] drm/amd/powerplay: correct the way for checking SMU_FEATURE_BACO_BIT support

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 



-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: Wednesday, February 12, 2020 3:25 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan 
Subject: [PATCH] drm/amd/powerplay: correct the way for checking 
SMU_FEATURE_BACO_BIT support

[CAUTION: External Email]

Since 'smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)' will always return 
false considering the 'smu_system_features_control(smu, false)' disabled all 
SMU features.

Change-Id: I73956ffa51d6da8375c7c377895a221e13d31594
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 13 -
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c 
b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 7c84d48c19e6..6d4c99b016f9 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -1489,7 +1489,18 @@ static int smu_disable_dpm(struct smu_context *smu)

/* For baco, need to leave BACO feature enabled */
if (use_baco) {
-   if (smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
+   /*
+* Correct the way for checking whether SMU_FEATURE_BACO_BIT
+* is supported.
+*
+* Since 'smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)' 
will
+* always return false as the 'smu_system_features_control(smu, 
false)'
+* was just issued above which disabled all SMU features.
+*
+* Thus 'smu_feature_get_index(smu, SMU_FEATURE_BACO_BIT)' is 
used
+* now for the checking.
+*/
+   if (smu_feature_get_index(smu, SMU_FEATURE_BACO_BIT) >= 
+ 0) {
ret = smu_feature_set_enabled(smu, 
SMU_FEATURE_BACO_BIT, true);
if (ret) {
pr_warn("set BACO feature enabled failed, 
return %d\n", ret);
--
2.25.0

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RE: [PATCH] drm/amd/powerplay: always refetch the enabled features status on dpm enablement

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: Tuesday, February 11, 2020 1:41 PM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan 
Subject: [PATCH] drm/amd/powerplay: always refetch the enabled features status 
on dpm enablement

[CAUTION: External Email]

Otherwise, the cached dpm features status may be inconsistent under some 
case(e.g. baco reset of Navi asic).

Change-Id: Ia7d7089e82cbe4ccaa9fadce1f2f0043c42c73df
Signed-off-by: Evan Quan 
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c 
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 0dc49479a7eb..b06c057a9002 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -898,6 +898,9 @@ int smu_v11_0_system_features_control(struct smu_context 
*smu,
if (ret)
return ret;

+   bitmap_zero(feature->enabled, feature->feature_num);
+   bitmap_zero(feature->supported, feature->feature_num);
+
if (en) {
ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
if (ret)
@@ -907,9 +910,6 @@ int smu_v11_0_system_features_control(struct smu_context 
*smu,
feature->feature_num);
bitmap_copy(feature->supported, (unsigned long *)_mask,
feature->feature_num);
-   } else {
-   bitmap_zero(feature->enabled, feature->feature_num);
-   bitmap_zero(feature->supported, feature->feature_num);
}

return ret;
--
2.25.0

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RE: [Error] amdgpu powerplay ip block error with -22.

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

First you could check if the binary 'polaris12_smc.bin' is in your system: 
/lib/firmware/../amdgpu/
If it's there, then does this happen after a warm reset?
Thanks.


From: amd-gfx  On Behalf Of Yusuf 
Altiparmak
Sent: Thursday, January 2, 2020 4:22 PM
To: amd-gfx@lists.freedesktop.org
Subject: [Error] amdgpu powerplay ip block error with -22.

[CAUTION: External Email]
I am having this error with kernel version 4.19 amdgpu driver for a polaris12 
based GPU. What could be the problem? Any suggestions? Thanks.

Full dmesg:
[5.426009] [drm] amdgpu kernel modesetting enabled.
[5.430109] [drm] initializing kernel modesetting (POLARIS12 0x1002:0x6987 
0x1787:0x2389 0x80).
[5.437591] [drm] register mmio base: 0x2020
[5.440899] [drm] register mmio size: 262144
[5.443888] [drm] add ip block number 0 
[5.447465] [drm] add ip block number 1 
[5.450953] [drm] add ip block number 2 
[5.454442] [drm] add ip block number 3 
[5.458018] [drm] add ip block number 4 
[5.460979] [drm] add ip block number 5 
[5.464466] [drm] add ip block number 6 
[5.468042] [drm] add ip block number 7 
[5.471531] [drm] add ip block number 8 
[5.475047] [drm] UVD is enabled in VM mode
[5.477928] [drm] UVD ENC is enabled in VM mode
[5.481154] [drm] VCE enabled in VM mode
[5.712355] ATOM BIOS: 113-ER16BFC-001
[5.714830] [drm] GPU posting now...
[5.833704] [drm] vm size is 64 GB, 2 levels, block size is 10-bit, fragment 
size is 9-bit
[5.840950] amdgpu 0001:01:00.0: BAR 2: releasing [mem 
0x22000-0x2201f 64bit pref]
[5.847930] amdgpu 0001:01:00.0: BAR 0: releasing [mem 
0x21000-0x21fff 64bit pref]
[5.855688] [drm:.amdgpu_device_resize_fb_bar [amdgpu]] *ERROR* Problem 
resizing BAR0 (-2).
[5.855706] amdgpu 0001:01:00.0: BAR 0: assigned [mem 
0x23000-0x23fff 64bit pref]
[5.869663] amdgpu 0001:01:00.0: BAR 2: assigned [mem 
0x24000-0x2401f 64bit pref]
[5.876582] amdgpu 0001:01:00.0: VRAM: 4096M 0x00F4 - 
0x00F4 (4096M used)
[5.884160] amdgpu 0001:01:00.0: GART: 256M 0x - 
0x0FFF
[5.890519] [drm] Detected VRAM RAM=4096M, BAR=256M
[5.894093] [drm] RAM width 128bits GDDR5
[5.896941] [TTM] Zone  kernel: Available graphics memory: 4062380 kiB
[5.902177] [TTM] Zone   dma32: Available graphics memory: 2097152 kiB
[5.907402] [TTM] Initializing pool allocator
[5.910464] [TTM] Initializing DMA pool allocator
[5.919973] [drm] amdgpu: 4096M of VRAM memory ready
[5.923659] [drm] amdgpu: 4096M of GTT memory ready.
[5.927358] [drm] GART: num cpu pages 65536, num gpu pages 65536
[5.932957] [drm] PCIE GART of 256M enabled (table at 0x00F4).
[5.939122] [drm] Chained IB support enabled!
[5.948873] [drm] Found UVD firmware Version: 1.79 Family ID: 16
[5.953647] [drm] UVD ENC is disabled
[5.975818] [drm] Found VCE firmware Version: 52.4 Binary ID: 3
[6.404774] amdgpu: [powerplay] Failed to send Message.
[6.835902] amdgpu: [powerplay] SMU Firmware start failed!
[6.840086] amdgpu: [powerplay] Failed to load SMU ucode.
[6.844184] amdgpu: [powerplay] smc start failed
[6.847498] amdgpu: [powerplay] powerplay hw init failed
[6.852281] [drm:.amdgpu_device_init [amdgpu]] *ERROR* hw_init of IP block 
 failed -22
[6.859883] amdgpu 0001:01:00.0: amdgpu_device_ip_init failed
[6.864330] amdgpu 0001:01:00.0: Fatal error during GPU init
[6.868689] [drm] amdgpu: finishing device.
[7.339427] pcieport 0001:00:00.0: AER: Corrected error received: 
0001:00:00.0
[7.345374] pcieport 0001:00:00.0: PCIe Bus Error: severity=Corrected, 
type=Data Link Layer, (Transmitter ID)
[7.353993] pcieport 0001:00:00.0:   device [1957:0824] error 
status/mask=1000/2000
[7.361047] pcieport 0001:00:00.0:[12] Timeout
[7.706137] amdgpu: [powerplay]
last message was failed ret is 0
[8.127667] amdgpu: [powerplay]
failed to send message 261 ret is 0
[8.966331] amdgpu: [powerplay]
last message was failed ret is 0
[9.320290] pcieport 0001:00:00.0: AER: Corrected error received: 
0001:00:00.0
[9.326226] pcieport 0001:00:00.0: PCIe Bus Error: severity=Corrected, 
type=Data Link Layer, (Transmitter ID)
[9.334845] pcieport 0001:00:00.0:   device [1957:0824] error 
status/mask=1000/2000
[9.341899] pcieport 0001:00:00.0:[12] Timeout
[9.387975] amdgpu: [powerplay]
failed to send message 261 ret is 0
[   10.226636] amdgpu: [powerplay]
last message was failed ret is 0
[   10.648275] amdgpu: [powerplay]
failed to send message 261 ret is 0
[   11.486932] amdgpu: [powerplay]
last message was failed ret is 0
[   11.908570] amdgpu: [powerplay]
failed to send message 261 ret is 0
[   

RE: [PATCH] drm/amd/powerplay: add smu11_driver_if_arcturus.h new OOB members

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Evan Quan
Sent: Thursday, January 2, 2020 9:54 AM
To: amd-gfx@lists.freedesktop.org
Cc: Quan, Evan 
Subject: [PATCH] drm/amd/powerplay: add smu11_driver_if_arcturus.h new OOB 
members

[CAUTION: External Email]

This is to fit the latest SMC firmware and it's backward compatible.

Change-Id: Ic561f83fa5d9d15a226b9f134da7e7ae90d9c6f9
Signed-off-by: Evan Quan 
---
 .../gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h  | 8 +++-
 drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
index 910226ec512e..ce5b5011c122 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_arcturus.h
@@ -622,8 +622,14 @@ typedef struct {
   uint16_t PccThresholdHigh;
   uint32_t PaddingAPCC[6];  //FIXME pending SPEC

+  // OOB Settings
+  uint16_t BasePerformanceCardPower;
+  uint16_t MaxPerformanceCardPower;
+  uint16_t BasePerformanceFrequencyCap;   //In Mhz
+  uint16_t MaxPerformanceFrequencyCap;//In Mhz
+
   // SECTION: Reserved
-  uint32_t Reserved[11];
+  uint32_t Reserved[9];

   // SECTION: BOARD PARAMETERS

diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h 
b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 662989296174..d5314d12628a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -27,7 +27,7 @@

 #define SMU11_DRIVER_IF_VERSION_INV 0x  #define 
SMU11_DRIVER_IF_VERSION_VG20 0x13 -#define SMU11_DRIVER_IF_VERSION_ARCT 0x10
+#define SMU11_DRIVER_IF_VERSION_ARCT 0x12
 #define SMU11_DRIVER_IF_VERSION_NV10 0x33  #define 
SMU11_DRIVER_IF_VERSION_NV14 0x34

--
2.24.1

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RE: [PATCH] drm/amd/powerplay: skip disable dynamic state management

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: Yintian Tao  
Sent: Wednesday, December 18, 2019 6:15 PM
To: Feng, Kenneth 
Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian 
Subject: [PATCH] drm/amd/powerplay: skip disable dynamic state management

Under sriov, the disable operation is no allowed.

Signed-off-by: Yintian Tao 
---
 drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 253860d30b20..9454ab50f9a1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -99,6 +99,9 @@ int phm_disable_dynamic_state_management(struct pp_hwmgr 
*hwmgr)
 
PHM_FUNC_CHECK(hwmgr);
 
+   if (!hwmgr->not_vf)
+   return 0;
+
if (!smum_is_dpm_running(hwmgr)) {
pr_info("dpm has been disabled\n");
return 0;
-- 
2.17.1
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RE: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]

I assume the smu firmware has been changed accordingly.
Reviewed-by: Kenneth Feng 


-Original Message-
From: Yintian Tao  
Sent: Wednesday, December 11, 2019 10:51 AM
To: Deucher, Alexander ; Feng, Kenneth 

Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian 
Subject: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

Originally, due to the restriction from PSP and SMU, VF has to send message to 
hypervisor driver to handle powerplay change which is complicated and 
redundant. Currently, SMU and PSP can support VF to directly handle powerplay 
change by itself. Therefore, the old code about the handshake between VF and PF 
to handle powerplay will be removed and VF will use new the registers below to 
handshake with SMU.
mmMP1_SMN_C2PMSG_101: register to handle SMU message
mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
mmMP1_SMN_C2PMSG_103: register to handle SMU response

v2: remove module parameter pp_one_vf
v3: fix the parens
v4: forbid vf to change smu feature
v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute
v6: change skip condition at vega10_copy_table_to_smc

Signed-off-by: Yintian Tao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  16 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   4 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 182 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |  51 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |  14 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  78 
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h |   4 -
 drivers/gpu/drm/amd/amdgpu/soc15.c|   8 +-
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c |   4 +-
 .../drm/amd/powerplay/hwmgr/hardwaremanager.c |  15 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   |  16 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c  |  30 +--
 .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 156 ++-
 .../amd/powerplay/hwmgr/vega10_powertune.c|   3 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |   1 +
 .../drm/amd/powerplay/smumgr/smu9_smumgr.c|  56 --
 .../drm/amd/powerplay/smumgr/vega10_smumgr.c  |  14 ++
 17 files changed, 352 insertions(+), 300 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7324a5fc5ccb..47b4f359f07c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
}
}
 
+   if (amdgpu_sriov_vf(adev))
+   amdgpu_virt_init_data_exchange(adev);
+
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r); @@ 
-1921,11 +1924,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
amdgpu_amdkfd_device_init(adev);
 
 init_failed:
-   if (amdgpu_sriov_vf(adev)) {
-   if (!r)
-   amdgpu_virt_init_data_exchange(adev);
+   if (amdgpu_sriov_vf(adev))
amdgpu_virt_release_full_gpu(adev, true);
-   }
 
return r;
 }
@@ -2825,7 +2825,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
-   mutex_init(>virt.dpm_mutex);
mutex_init(>psp.mutex);
 
r = amdgpu_device_check_arguments(adev);
@@ -3044,9 +3043,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 
amdgpu_fbdev_init(adev);
 
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_init(adev);
-
r = amdgpu_pm_sysfs_init(adev);
if (r) {
adev->pm_sysfs_en = false;
@@ -3191,8 +3187,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_fini(adev);
 
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count); @@ -3673,6 
+3667,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
if (r)
goto error;
 
+   amdgpu_virt_init_data_exchange(adev);
/* we need recover gart prior to run SMC/CP/SDMA resume */
amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
 
@@ -3690,7 +3685,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device 
*adev,
amdgpu_amdkfd_post_reset(adev);
 
 error:
-   amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
amdgpu_inc_vram_lost(adev);
diff --g

Recall: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

[Feng, Kenneth]

Feng, Kenneth would like to recall the message, "[PATCH] drm/amd/powerplay: 
enable pp one vf mode for vega10".
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RE: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

[Feng, Kenneth]

[AMD Official Use Only - Internal Distribution Only]



-Original Message-
From: Yintian Tao  
Sent: Wednesday, December 11, 2019 10:51 AM
To: Deucher, Alexander ; Feng, Kenneth 

Cc: amd-gfx@lists.freedesktop.org; Tao, Yintian 
Subject: [PATCH] drm/amd/powerplay: enable pp one vf mode for vega10

Originally, due to the restriction from PSP and SMU, VF has to send message to 
hypervisor driver to handle powerplay change which is complicated and 
redundant. Currently, SMU and PSP can support VF to directly handle powerplay 
change by itself. Therefore, the old code about the handshake between VF and PF 
to handle powerplay will be removed and VF will use new the registers below to 
handshake with SMU.
mmMP1_SMN_C2PMSG_101: register to handle SMU message
mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
mmMP1_SMN_C2PMSG_103: register to handle SMU response

v2: remove module parameter pp_one_vf
v3: fix the parens
v4: forbid vf to change smu feature
v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute
v6: change skip condition at vega10_copy_table_to_smc

Signed-off-by: Yintian Tao 
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c|  16 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c   |   4 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 182 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c  |  51 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h  |  14 +-
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c |  78 
 drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h |   4 -
 drivers/gpu/drm/amd/amdgpu/soc15.c|   8 +-
 drivers/gpu/drm/amd/powerplay/amd_powerplay.c |   4 +-
 .../drm/amd/powerplay/hwmgr/hardwaremanager.c |  15 +-
 drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c   |  16 ++
 drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c  |  30 +--
 .../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 156 ++-
 .../amd/powerplay/hwmgr/vega10_powertune.c|   3 +
 drivers/gpu/drm/amd/powerplay/inc/hwmgr.h |   1 +
 .../drm/amd/powerplay/smumgr/smu9_smumgr.c|  56 --
 .../drm/amd/powerplay/smumgr/vega10_smumgr.c  |  14 ++
 17 files changed, 352 insertions(+), 300 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7324a5fc5ccb..47b4f359f07c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device 
*adev)
}
}
 
+   if (amdgpu_sriov_vf(adev))
+   amdgpu_virt_init_data_exchange(adev);
+
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r); @@ 
-1921,11 +1924,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
amdgpu_amdkfd_device_init(adev);
 
 init_failed:
-   if (amdgpu_sriov_vf(adev)) {
-   if (!r)
-   amdgpu_virt_init_data_exchange(adev);
+   if (amdgpu_sriov_vf(adev))
amdgpu_virt_release_full_gpu(adev, true);
-   }
 
return r;
 }
@@ -2825,7 +2825,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
-   mutex_init(>virt.dpm_mutex);
mutex_init(>psp.mutex);
 
r = amdgpu_device_check_arguments(adev);
@@ -3044,9 +3043,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 
amdgpu_fbdev_init(adev);
 
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_init(adev);
-
r = amdgpu_pm_sysfs_init(adev);
if (r) {
adev->pm_sysfs_en = false;
@@ -3191,8 +3187,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
-   if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
-   amdgpu_pm_virt_sysfs_fini(adev);
 
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count); @@ -3673,6 
+3667,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev,
if (r)
goto error;
 
+   amdgpu_virt_init_data_exchange(adev);
/* we need recover gart prior to run SMC/CP/SDMA resume */
amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
 
@@ -3690,7 +3685,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device 
*adev,
amdgpu_amdkfd_post_reset(adev);
 
 error:
-   amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
amdgpu_inc_vram_lost(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.

Re: [PATCH 2/2] drm/amd/powerplay: pre-check the SMU state before issuing message

[Feng, Kenneth]

Got it. Thanks.
Reviewed-by: Kenneth Feng mailto:kenneth.f...@amd.com>

在 2019年12月4日，下午6:23，Quan, Evan mailto:evan.q...@amd.com>> 写道：

The abort operation is added in smu_v11_0_send_msg_with_param.
And for smu_v11_0_wait_for_response, yes, it's only code factoring.

-Original Message-----
From: Feng, Kenneth mailto:kenneth.f...@amd.com>>
Sent: Wednesday, December 4, 2019 6:14 PM
To: Quan, Evan mailto:evan.q...@amd.com>>
Cc: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 2/2] drm/amd/powerplay: pre-check the SMU state before
issuing message

Hi Evan,
The original design is also aborting sending the message because of a ‘break’
there.
Your patch is for code factoring?
Thanks.

在 2019年12月4日，下午5:53，Evan Quan mailto:evan.q...@amd.com>> 写
道：

[CAUTION: External Email]

Abort the message issuing if the SMU was not in the right state.

Change-Id: Ida9f911e051f6e78de4f475956c78637e56e6ea3
Signed-off-by: Evan Quan mailto:evan.q...@amd.com>>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 16 
2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 325ec4864f90..d84c7f5fb01a 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -68,15 +68,13 @@ static int smu_v11_0_wait_for_response(struct
smu_context *smu)
  for (i = 0; i < timeout; i++) {
  cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
-   break;
+   return cur_value == 0x1 ? 0 : -EIO;
+
  udelay(1);
  }

  /* timeout means wrong logic */
-   if (i == timeout)
-   return -ETIME;
-
-   return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 :
-EIO;
+   return -ETIME;
}

int
@@ -92,9 +90,11 @@ smu_v11_0_send_msg_with_param(struct
smu_context *smu,
  return index;

  ret = smu_v11_0_wait_for_response(smu);
-   if (ret)
-   pr_err("failed send message: %10s (%d) \tparam: 0x%08x
response %#x\n",
-  smu_get_message_name(smu, msg), index, param, ret);
+   if (ret) {
+   pr_err("Msg issuing pre-check failed and "
+  "SMU may be not in the right state!\n");
+   return ret;
+   }

  WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 7f5f7e12a41e..a638326ba1b7 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -56,15 +56,13 @@ int smu_v12_0_wait_for_response(struct
smu_context *smu)
  for (i = 0; i < adev->usec_timeout; i++) {
  cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
  if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
-   break;
+   return cur_value == 0x1 ? 0 : -EIO;
+
  udelay(1);
  }

  /* timeout means wrong logic */
-   if (i == adev->usec_timeout)
-   return -ETIME;
-
-   return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 :
-EIO;
+   return -ETIME;
}

int
@@ -80,9 +78,11 @@ smu_v12_0_send_msg_with_param(struct
smu_context *smu,
  return index;

  ret = smu_v12_0_wait_for_response(smu);
-   if (ret)
-   pr_err("Failed to send message 0x%x, response 0x%x, param
0x%x\n",
-  index, ret, param);
+   if (ret) {
+   pr_err("Msg issuing pre-check failed and "
+  "SMU may be not in the right state!\n");
+   return ret;
+   }

  WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);

--
2.24.0

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