from:"Liu, Zhan"

RE: [PATCH] drm/amd/display: fix if == else warning

2022-04-24 Thread Liu, Zhan

[AMD Official Use Only - General]

> -Original Message-
> From: Guo Zhengkui 
> Sent: 2022/April/24, Sunday 5:06 AM
> To: Wentland, Harry ; Li, Sun peng (Leo)
> ; Siqueira, Rodrigo ;
> Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui ; David Airlie
> ; Daniel Vetter ; Liu, Charlene
> ; Lei, Jun ; Guo Zhengkui
> ; Liu, Zhan ; José Expósito
> ; open list:AMD DISPLAY CORE  g...@lists.freedesktop.org>; open list:DRM DRIVERS  de...@lists.freedesktop.org>; open list 
> Cc: zhengkui_...@outlook.com
> Subject: [PATCH] drm/amd/display: fix if == else warning
>
> Fix the following coccicheck warning:
>
> drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c:98:8-10:
> WARNING: possible condition with no effect (if == else)
>
> Signed-off-by: Guo Zhengkui 

Thanks a lot for fixing this warning.

Reviewed-by: Zhan Liu 

> ---
>  drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c | 2 --
>  1 file changed, 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
> b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
> index fe22530242d2..05b3fba9ccce 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c
> @@ -95,8 +95,6 @@ static void gpu_addr_to_uma(struct dce_hwseq *hwseq,
>   } else if (hwseq->fb_offset.quad_part <= addr->quad_part &&
>   addr->quad_part <= hwseq->uma_top.quad_part) {
>   is_in_uma = true;
> - } else if (addr->quad_part == 0) {
> - is_in_uma = false;
>   } else {
>   is_in_uma = false;
>   }
> --
> 2.20.1

RE: [PATCH] drm/amd/display: Update watermark values for DCN301

2022-01-28 Thread Liu, Zhan

[Public]

> -Original Message-
> From: amd-gfx  On Behalf Of Agustin
> Gutierrez
> Sent: 2022/January/28, Friday 6:07 PM
> To: amd-gfx@lists.freedesktop.org; Gutierrez, Agustin
> 
> Cc: Gutierrez, Agustin 
> Subject: [PATCH] drm/amd/display: Update watermark values for DCN301
>
> [Why]
> There is underflow / visual corruption DCN301, for high
> bandwidth MST DSC configurations such as 2x1440p144 or 2x4k60.
>
> [How]
> Use up-to-date watermark values for DCN301.
>
> Signed-off-by: Agustin Gutierrez 

Looks good to me.

Reviewed-by: Zhan Liu 

> ---
>  .../amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c   | 16 
>  1 file changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
> b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
> index 48005def1164..bc4ddc36fe58 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
> @@ -570,32 +570,32 @@ static struct wm_table lpddr5_wm_table = {
>   .wm_inst = WM_A,
>   .wm_type = WM_TYPE_PSTATE_CHG,
>   .pstate_latency_us = 11.65333,
> - .sr_exit_time_us = 7.95,
> - .sr_enter_plus_exit_time_us = 9,
> + .sr_exit_time_us = 13.5,
> + .sr_enter_plus_exit_time_us = 16.5,
>   .valid = true,
>   },
>   {
>   .wm_inst = WM_B,
>   .wm_type = WM_TYPE_PSTATE_CHG,
>   .pstate_latency_us = 11.65333,
> - .sr_exit_time_us = 9.82,
> - .sr_enter_plus_exit_time_us = 11.196,
> + .sr_exit_time_us = 13.5,
> + .sr_enter_plus_exit_time_us = 16.5,
>   .valid = true,
>   },
>   {
>   .wm_inst = WM_C,
>   .wm_type = WM_TYPE_PSTATE_CHG,
>   .pstate_latency_us = 11.65333,
> - .sr_exit_time_us = 9.89,
> - .sr_enter_plus_exit_time_us = 11.24,
> + .sr_exit_time_us = 13.5,
> + .sr_enter_plus_exit_time_us = 16.5,
>   .valid = true,
>   },
>   {
>   .wm_inst = WM_D,
>   .wm_type = WM_TYPE_PSTATE_CHG,
>   .pstate_latency_us = 11.65333,
> - .sr_exit_time_us = 9.748,
> - .sr_enter_plus_exit_time_us = 11.102,
> + .sr_exit_time_us = 13.5,
> + .sr_enter_plus_exit_time_us = 16.5,
>   .valid = true,
>   },
>   }
> --
> 2.25.1

RE: [PATCH] drm/amd/display: Keep eDP Vdd on when eDP stream is already

2022-01-27 Thread Liu, Zhan

[Public]

After giving it a second thought, I will apply a similar patch on internal 
branch first, then get it promoted to external branch. This patch is abandoned.

Thanks,
Zhan

> -Original Message-
> From: Liu, Zhan
> Sent: 2022/January/27, Thursday 9:51 PM
> To: amd-gfx@lists.freedesktop.org; Liu, Charlene 
> Cc: Pierre-Loup Griffais ; Cornij, Nikola
> ; Kotarac, Pavle ; Gutierrez,
> Agustin 
> Subject: [PATCH] drm/amd/display: Keep eDP Vdd on when eDP stream is already
>
> [Why]
> Even if can_apply_edp_fast_boot is set to 1 at boot, this flag will be 
> cleared to 0
> at S3 resume. However, we still need to keep Vdd on at S3 resume. Turning eDP
> Vdd off at resume will result in black screen at S3 resume.
>
> [How]
> Don't turn eDP Vdd off when there is an existing eDP stream. This can assure 
> eDP
> display come back after S3.
>
> Signed-off-by: Zhan Liu 
> ---
>  .../display/dc/dce110/dce110_hw_sequencer.c   | 23 +--
>  1 file changed, 21 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> index 72dd41e7a7d6..1aa6f2737534 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
> @@ -1796,9 +1796,28 @@ void dce110_enable_accelerated_mode(struct dc *dc,
> struct dc_state *context)
>   break;
>   }
>   }
> - // We are trying to enable eDP, don't power down VDD
> - if (can_apply_edp_fast_boot)
> +
> + /*
> +  * TO-DO: So far the code logic below only addresses single eDP
> case.
> +  * For dual eDP case, there are a few things that need to be
> +  * implemented first:
> +  *
> +  * 1. Change the fastboot logic above, so eDP link[0 or 1]'s
> +  * stream[0 or 1] will all be checked.
> +  *
> +  * 2. Change keep_edp_vdd_on to an array, and maintain
> keep_edp_vdd_on
> +  * for each eDP.
> +  *
> +  * Once above 2 things are completed, we can then change the
> logic below
> +  * correspondingly, so dual eDP case will be fully covered.
> +  */
> +
> + // We are trying to enable eDP, don't power down VDD if there is
> an existing eDP stream
> + if ((edp_stream_num = 1 && edp_streams[0]) ||
> +can_apply_edp_fast_boot) {
>   keep_edp_vdd_on = true;
> + DC_LOG_EVENT_LINK_TRAINING("At least 1 eDP stream is
> already enabled, will keep eDP Vdd on\n");
> + } else
> + DC_LOG_EVENT_LINK_TRAINING("No eDP stream enabled,
> will turn eDP Vdd
> +off\n");
>   }
>
>   // Check seamless boot support
> --
> 2.25.1

[PATCH] drm/amd/display: Keep eDP Vdd on when eDP stream is already

2022-01-27 Thread Liu, Zhan

[Public]

[Why]
Even if can_apply_edp_fast_boot is set to 1 at boot, this flag will
be cleared to 0 at S3 resume. However, we still need to keep Vdd on
at S3 resume. Turning eDP Vdd off at resume will result in black
screen at S3 resume.

[How]
Don't turn eDP Vdd off when there is an existing eDP stream. This can
assure eDP display come back after S3.

Signed-off-by: Zhan Liu 
---
 .../display/dc/dce110/dce110_hw_sequencer.c   | 23 +--
 1 file changed, 21 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 72dd41e7a7d6..1aa6f2737534 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1796,9 +1796,28 @@ void dce110_enable_accelerated_mode(struct dc *dc, 
struct dc_state *context)
break;
}
}
-   // We are trying to enable eDP, don't power down VDD
-   if (can_apply_edp_fast_boot)
+
+   /*
+* TO-DO: So far the code logic below only addresses single eDP 
case.
+* For dual eDP case, there are a few things that need to be
+* implemented first:
+*
+* 1. Change the fastboot logic above, so eDP link[0 or 1]'s
+* stream[0 or 1] will all be checked.
+*
+* 2. Change keep_edp_vdd_on to an array, and maintain 
keep_edp_vdd_on
+* for each eDP.
+*
+* Once above 2 things are completed, we can then change the 
logic below
+* correspondingly, so dual eDP case will be fully covered.
+*/
+
+   // We are trying to enable eDP, don't power down VDD if there 
is an existing eDP stream
+   if ((edp_stream_num = 1 && edp_streams[0]) || 
can_apply_edp_fast_boot) {
keep_edp_vdd_on = true;
+   DC_LOG_EVENT_LINK_TRAINING("At least 1 eDP stream is 
already enabled, will keep eDP Vdd on\n");
+   } else
+   DC_LOG_EVENT_LINK_TRAINING("No eDP stream enabled, will 
turn eDP Vdd off\n");
}

// Check seamless boot support
--
2.25.1

RE: [PATCH] drm/amd/display: Shorten delay time to 1us while resetting FIFO

2022-01-19 Thread Liu, Zhan

[Public]

Thank you all for the review. I've found a better solution here, so I will 
retire this patch, and re-submit a different one.

Thanks,
Zhan

> -Original Message-
> From: Liu, Zhan 
> Sent: 2022/January/19, Wednesday 5:24 PM
> To: Liu, Zhan ; amd-gfx@lists.freedesktop.org
> Cc: Liu, Charlene ; Kotarac, Pavle
> ; Pierre-Loup Griffais ;
> Gutierrez, Agustin ; Cornij, Nikola
> 
> Subject: RE: [PATCH] drm/amd/display: Shorten delay time to 1us while 
> resetting
> FIFO
>
> [Public]
>
> Apologize for sending out the patch with the wrong sensitivity a few seconds 
> ago.
> I've updated sensitivity policy to "Public" here.
>
> Thanks,
> Zhan
>
> > -Original Message-
> > From: amd-gfx  On Behalf Of
> > Liu, Zhan
> > Sent: 2022/January/19, Wednesday 5:19 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Liu, Charlene ; Kotarac, Pavle
> > ; Pierre-Loup Griffais
> > ; Gutierrez, Agustin
> > ; Cornij, Nikola 
> > Subject: [PATCH] drm/amd/display: Shorten delay time to 1us while
> > resetting FIFO
> >
> > [Why]
> > Current FIFO reset delay for dcn10 is 100us, which is too long and
> > will fail atomic flip. As a result, there will be no display on boot.
> >
> > [How]
> > Shorten delay time to 1us. This also aligns with FIFO reset delay on other 
> > ASICs.
> >
> > Signed-off-by: Zhan Liu 
> > ---
> >  drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git
> > a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
> > b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
> > index bf4436d7aaab..2077c22befa5 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
> > @@ -909,7 +909,7 @@ void enc1_stream_encoder_reset_fifo(
> >
> > /* set DIG_START to 0x1 to reset FIFO */
> > REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
> > -   udelay(100);
> > +   udelay(1);
> >
> > /* write 0 to take the FIFO out of reset */
> > REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
> > --
> > 2.25.1

RE: [PATCH] drm/amd/display: Shorten delay time to 1us while resetting FIFO

2022-01-19 Thread Liu, Zhan

[Public]

Apologize for sending out the patch with the wrong sensitivity a few seconds 
ago. I've updated sensitivity policy to "Public" here.

Thanks,
Zhan

> -Original Message-
> From: amd-gfx  On Behalf Of Liu, Zhan
> Sent: 2022/January/19, Wednesday 5:19 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Charlene ; Kotarac, Pavle
> ; Pierre-Loup Griffais ;
> Gutierrez, Agustin ; Cornij, Nikola
> 
> Subject: [PATCH] drm/amd/display: Shorten delay time to 1us while resetting 
> FIFO
>
> [Why]
> Current FIFO reset delay for dcn10 is 100us, which is too long and will fail 
> atomic
> flip. As a result, there will be no display on boot.
>
> [How]
> Shorten delay time to 1us. This also aligns with FIFO reset delay on other 
> ASICs.
>
> Signed-off-by: Zhan Liu 
> ---
>  drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
> b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
> index bf4436d7aaab..2077c22befa5 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
> @@ -909,7 +909,7 @@ void enc1_stream_encoder_reset_fifo(
>
> /* set DIG_START to 0x1 to reset FIFO */
> REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
> -   udelay(100);
> +   udelay(1);
>
> /* write 0 to take the FIFO out of reset */
> REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
> --
> 2.25.1

RE: [PATCH] drm/amd/display: Correct MPC split policy for DCN301

2022-01-19 Thread Liu, Zhan

[Public]

Apologize for sending out the patch with the wrong email sensitivity policy a 
few seconds ago. I've updated sensitivity policy to "Public".

Thanks,
Zhan

> -Original Message-
> From: amd-gfx  On Behalf Of Liu, Zhan
> Sent: 2022/January/19, Wednesday 5:17 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Charlene ; Kotarac, Pavle
> ; Pierre-Loup Griffais ;
> Gutierrez, Agustin ; Cornij, Nikola
> 
> Subject: [PATCH] drm/amd/display: Correct MPC split policy for DCN301
>
> [Why]
> DCN301 has seamless boot enabled. With MPC split enabled at the same time,
> system will hang.
>
> [How]
> Revert MPC split policy back to "MPC_SPLIT_AVOID". Since we have ODM combine
> enabled on DCN301, pipe split is not necessary here.
>
> Signed-off-by: Zhan Liu 
> ---
>  drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> index c1c6e602b06c..b4001233867c 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> @@ -686,7 +686,7 @@ static const struct dc_debug_options debug_defaults_drv
> = {
> .disable_clock_gate = true,
> .disable_pplib_clock_request = true,
> .disable_pplib_wm_range = true,
> -   .pipe_split_policy = MPC_SPLIT_DYNAMIC,
> +   .pipe_split_policy = MPC_SPLIT_AVOID,
> .force_single_disp_pipe_split = false,
> .disable_dcc = DCC_ENABLE,
> .vsr_support = true,
> --
> 2.25.1

[PATCH] drm/amd/display: change FIFO reset condition to embedded display only

2022-01-19 Thread Liu, Zhan

[Public]

[Why]
FIFO reset is only necessary for fast boot sequence, where otg is disabled
and dig fe is enabled when changing dispclk. Fast boot is only enabled
on embedded displays.

[How]
Change FIFO reset condition to "embedded display only".

Signed-off-by: Zhan Liu 
---
 drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index f1593186e964..f3ff141b706a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1608,7 +1608,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
pipe_ctx->stream_res.stream_enc,
pipe_ctx->stream_res.tg->inst);

-   if (dc_is_dp_signal(pipe_ctx->stream->signal) &&
+   if (dc_is_embedded_signal(pipe_ctx->stream->signal) &&
pipe_ctx->stream_res.stream_enc->funcs->reset_fifo)
pipe_ctx->stream_res.stream_enc->funcs->reset_fifo(
pipe_ctx->stream_res.stream_enc);
--
2.25.1

[PATCH] drm/amd/display: Shorten delay time to 1us while resetting FIFO

2022-01-19 Thread Liu, Zhan

[AMD Official Use Only]

[Why]
Current FIFO reset delay for dcn10 is 100us, which is too long
and will fail atomic flip. As a result, there will be no display
on boot.

[How]
Shorten delay time to 1us. This also aligns with FIFO reset delay
on other ASICs.

Signed-off-by: Zhan Liu 
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
index bf4436d7aaab..2077c22befa5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
@@ -909,7 +909,7 @@ void enc1_stream_encoder_reset_fifo(

/* set DIG_START to 0x1 to reset FIFO */
REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
-   udelay(100);
+   udelay(1);

/* write 0 to take the FIFO out of reset */
REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
--
2.25.1

[PATCH] drm/amd/display: Correct MPC split policy for DCN301

2022-01-19 Thread Liu, Zhan

[AMD Official Use Only]

[Why]
DCN301 has seamless boot enabled. With MPC split enabled
at the same time, system will hang.

[How]
Revert MPC split policy back to "MPC_SPLIT_AVOID". Since we have
ODM combine enabled on DCN301, pipe split is not necessary here.

Signed-off-by: Zhan Liu 
---
 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index c1c6e602b06c..b4001233867c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -686,7 +686,7 @@ static const struct dc_debug_options debug_defaults_drv = {
.disable_clock_gate = true,
.disable_pplib_clock_request = true,
.disable_pplib_wm_range = true,
-   .pipe_split_policy = MPC_SPLIT_DYNAMIC,
+   .pipe_split_policy = MPC_SPLIT_AVOID,
.force_single_disp_pipe_split = false,
.disable_dcc = DCC_ENABLE,
.vsr_support = true,
--
2.25.1

RE: [PATCH] drm/amdgpu/display: fold DRM_AMD_DC_DCN201 into DRM_AMD_DC_DCN

2021-10-01 Thread Liu, Zhan

[Public]

> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: 2021/October/01, Friday 10:31 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: [PATCH] drm/amdgpu/display: fold DRM_AMD_DC_DCN201 into
> DRM_AMD_DC_DCN
>
> No need for a separate kconfig option at this point.
>
> Signed-off-by: Alex Deucher 

Reviewed-by: Zhan Liu 

> ---
>  drivers/gpu/drm/amd/display/Kconfig   | 9 -
>  drivers/gpu/drm/amd/display/dc/Makefile   | 2 --
>  drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile   | 2 --
>  drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  | 2 --
> drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 --
>  drivers/gpu/drm/amd/display/dc/irq/Makefile   | 2 --
>  6 files changed, 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/Kconfig
> b/drivers/gpu/drm/amd/display/Kconfig
> index fb074a6067b2..7dffc04a557e 100644
> --- a/drivers/gpu/drm/amd/display/Kconfig
> +++ b/drivers/gpu/drm/amd/display/Kconfig
> @@ -17,15 +17,6 @@ config DRM_AMD_DC_DCN
>   help
> Raven, Navi, and newer family support for display engine
>
> -config DRM_AMD_DC_DCN201
> - bool "Enable DCN201 support in DC"
> - default y
> - depends on DRM_AMD_DC && X86
> - depends on DRM_AMD_DC_DCN
> - help
> -   Choose this option if you want to have
> -   201 support for display engine
> -
>  config DRM_AMD_DC_HDCP
>   bool "Enable HDCP support in DC"
>   depends on DRM_AMD_DC
> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
> b/drivers/gpu/drm/amd/display/dc/Makefile
> index 520f58538364..b5482980e995 100644
> --- a/drivers/gpu/drm/amd/display/dc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> @@ -30,9 +30,7 @@ DC_LIBS += dcn20
>  DC_LIBS += dsc
>  DC_LIBS += dcn10 dml
>  DC_LIBS += dcn21
> -ifdef CONFIG_DRM_AMD_DC_DCN201
>  DC_LIBS += dcn201
> -endif
>  DC_LIBS += dcn30
>  DC_LIBS += dcn301
>  DC_LIBS += dcn302
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
> b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
> index 7f70985b7a1b..6bd73e49a6d2 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile
> @@ -93,7 +93,6 @@ AMD_DAL_CLK_MGR_DCN20 = $(addprefix
> $(AMDDALPATH)/dc/clk_mgr/dcn20/,$(CLK_MGR_DC
>
>  AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN20)
>
> -ifdef CONFIG_DRM_AMD_DC_DCN201
>
> #
> ##
>  # DCN201
>
> #
> ##
> @@ -102,7 +101,6 @@ CLK_MGR_DCN201 = dcn201_clk_mgr.o
>  AMD_DAL_CLK_MGR_DCN201 = $(addprefix
> $(AMDDALPATH)/dc/clk_mgr/dcn201/,$(CLK_MGR_DCN201))
>
>  AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN201) -endif
>
>
> #
> ##
>  # DCN21
> diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> index 421f5135b701..1548b2a3fe03 100644
> --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c
> @@ -257,12 +257,10 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context
> *ctx, struct pp_smu_funcs *p
>   dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
>   return _mgr->base;
>   }
> -#if defined(CONFIG_DRM_AMD_DC_DCN201)
>   if (asic_id.chip_id == DEVICE_ID_NV_13FE) {
>   dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
>   return _mgr->base;
>   }
> -#endif
>   dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
>   return _mgr->base;
>   }
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> index fc490b77f47d..561c10a92bb5 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> @@ -224,11 +224,9 @@ struct resource_pool
> *dc_create_resource_pool(struct dc  *dc,
>   case DCN_VERSION_2_1:
>   res_pool = dcn21_create_resource_pool(init_data, dc);
>   break;
> -#if defined(CONFIG_DRM_AMD_DC_DCN201)
>   case DCN_VERSION_2_01:
>   res_pool = dcn201_create_resource_pool(init_data, dc);
>   break;
> -#endif
>   case DCN_VERSION_3_0:
>   res_pool = dcn30_create_resource_pool(init_data, dc);
>   break;
> diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile
> b/drivers/gpu/drm/amd/display/dc/irq/Makefile
> index 8a182772eed2..fd739aecf104 100644
> --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile
> @@ -94,7 +94,6 @@ AMD_DAL_IRQ_DCN21= $(addprefix
> $(AMDDALPATH)/dc/irq/dcn21/,$(IRQ_DCN21))
>
>  AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN21)
>
> -ifdef

RE: [PATCH 02/02] drm/amd/display: add cyan_skillfish display support

2021-09-27 Thread Liu, Zhan

[Public]

> -Original Message-
> From: Alex Deucher 
> Sent: 2021/September/27, Monday 4:50 PM
> To: Liu, Zhan 
> Cc: amd-gfx@lists.freedesktop.org; Liu, Charlene ;
> Wentland, Harry ; Deucher, Alexander
> ; Lei, Jun ; Pillai,
> Aurabindo 
> Subject: Re: [PATCH 02/02] drm/amd/display: add cyan_skillfish display
> support
>
> On Mon, Sep 27, 2021 at 4:43 PM Liu, Zhan  wrote:
> >
> > [Public]
> >
> > [Why]
> > add display related cyan_skillfish files in.
> >
> > makefile controlled by CONFIG_DRM_AMD_DC_DCN201 flag.
> >
> > Signed-off-by: Charlene Liu 
> > Signed-off-by: Zhan Liu 
> > Reviewed-by: Charlene Liu 
> > Acked-by: Jun Lei 
> > ---
> 
>
> > @@ -1457,34 +1460,33 @@
> >  #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
> > adev->dm.crc_rd_wrk =
> amdgpu_dm_crtc_secure_display_create_work();
> >  #endif
> > -   if (dc_enable_dmub_notifications(adev->dm.dc)) {
> > -   init_completion(>dm.dmub_aux_transfer_done);
> > -   adev->dm.dmub_notify = kzalloc(sizeof(struct 
> > dmub_notification),
> GFP_KERNEL);
> > -   if (!adev->dm.dmub_notify) {
> > -   DRM_INFO("amdgpu: fail to allocate 
> > adev->dm.dmub_notify");
> > -   goto error;
> > -   }
> >
> > -   adev->dm.delayed_hpd_wq =
> create_singlethread_workqueue("amdgpu_dm_hpd_wq");
> > -   if (!adev->dm.delayed_hpd_wq) {
> > -   DRM_ERROR("amdgpu: failed to create hpd offload
> workqueue.\n");
> > -   goto error;
> > -   }
> > -
> > -   amdgpu_dm_outbox_init(adev);
> > -#if defined(CONFIG_DRM_AMD_DC_DCN)
> > -   if (!register_dmub_notify_callback(adev,
> DMUB_NOTIFICATION_AUX_REPLY,
> > -   dmub_aux_setconfig_callback, false)) {
> > -   DRM_ERROR("amdgpu: fail to register dmub aux 
> > callback");
> > -   goto error;
> > -   }
> > -   if (!register_dmub_notify_callback(adev,
> DMUB_NOTIFICATION_HPD, dmub_hpd_callback, true)) {
> > -   DRM_ERROR("amdgpu: fail to register dmub hpd 
> > callback");
> > -   goto error;
> > -   }
> > -#endif
> > +   init_completion(>dm.dmub_aux_transfer_done);
> > +   adev->dm.dmub_notify = kzalloc(sizeof(struct dmub_notification),
> GFP_KERNEL);
> > +   if (!adev->dm.dmub_notify) {
> > +   DRM_INFO("amdgpu: fail to allocate adev->dm.dmub_notify");
> > +   goto error;
> > }
> >
> > +   adev->dm.delayed_hpd_wq =
> create_singlethread_workqueue("amdgpu_dm_hpd_wq");
> > +   if (!adev->dm.delayed_hpd_wq) {
> > +   DRM_ERROR("amdgpu: failed to create hpd offload
> workqueue.\n");
> > +   goto error;
> > +   }
> > +
> > +   amdgpu_dm_outbox_init(adev);
> > +#if defined(CONFIG_DRM_AMD_DC_DCN)
> > +   if (!register_dmub_notify_callback(adev,
> DMUB_NOTIFICATION_AUX_REPLY,
> > +   dmub_aux_setconfig_callback, false)) {
> > +   DRM_ERROR("amdgpu: fail to register dmub aux callback");
> > +   goto error;
> > +   }
> > +   if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD,
> dmub_hpd_callback, true)) {
> > +   DRM_ERROR("amdgpu: fail to register dmub hpd callback");
> > +   goto error;
> > +   }
> > +#endif
> > +
>
> This change above looks unrelated.  Please double check this is correct.

Hi Alex, sorry it was my bad. Yes, you are totally correct, thanks a lot for 
catching that. Let me send out my patch v2 soon.

Thanks,
Zhan

>
> Alex

[PATCH 00/02] cyan skillfish display support

2021-09-27 Thread Liu, Zhan

[Public]

This patch set brings cyan skillfish display support

Charlene Liu / Zhan Liu (2):
drm/amdgpu: add cyan_skillfish asic header files
drm/amd/display: add cyan_skillfish display support

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +
 drivers/gpu/drm/amd/amdgpu/nv.c| 2 +
 drivers/gpu/drm/amd/display/Kconfig| 9 +
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |55 +-
 drivers/gpu/drm/amd/display/dc/Makefile| 3 +
 drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c| 1 +
 drivers/gpu/drm/amd/display/dc/clk_mgr/Makefile|11 +
 drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c   | 7 +
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c |   260 +++
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/dcn201_clk_mgr.h |34 +
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |10 +
 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h  | 9 +
 drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h |39 +
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h   |27 +
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c  | 3 +
 drivers/gpu/drm/amd/display/dc/dcn201/Makefile |33 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dccg.c|84 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dccg.h|37 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.c |   316 +++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_dpp.h |83 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.c  |   107 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubbub.h  |45 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.c|   150 ++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hubp.h|   132 ++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.c   |   630 ++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_hwseq.h   |46 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.c|   131 ++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_init.h|33 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c|   209 ++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.h|59 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.c |   125 ++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_mpc.h |86 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.c |72 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_opp.h |74 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.c|   203 ++
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_optc.h|74 +
 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.c|  1307 

 drivers/gpu/drm/amd/display/dc/dcn201/dcn201_resource.h|50 +
 drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.c  | 1 +
 drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.h  | 1 +
 drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c   | 1 +
 drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 1 +
 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h   |13 +
 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h| 4 +-
 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h| 1 +
 drivers/gpu/drm/amd/display/dc/inc/hw_sequencer_private.h  | 4 +
 drivers/gpu/drm/amd/display/dc/irq/Makefile|12 +
 drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.c |   374 
 drivers/gpu/drm/amd/display/dc/irq/dcn201/irq_service_dcn201.h |34 +
 drivers/gpu/drm/amd/display/include/dal_asic_id.h  | 1 +
 drivers/gpu/drm/amd/display/include/dal_types.h| 1 +
 drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_1_offset.h   |32 +
 drivers/gpu/drm/amd/include/asic_reg/clk/clk_11_0_1_sh_mask.h  |37 +
 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_3_offset.h|  6193 
+
 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_0_3_sh_mask.h   | 22091 
+
 drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_2_0_3_offset.h  |   151 ++
 drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_2_0_3_sh_mask.h |   952 
+
 57 files changed, 34439 insertions(+), 25 deletions(-)

--
2.25.1

RE: [PATCH] drm/amd/display: Use DCN30 watermark calc for DCN301

2021-08-13 Thread Liu, Zhan

[Public]

> -Original Message-
> From: Liu, Zhan 
> Sent: 2021/August/13, Friday 3:21 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Cornij, Nikola ; Liu, Zhan
> ; Logush, Oliver 
> Subject: [PATCH] drm/amd/display: Use DCN30 watermark calc for DCN301
>
>
> [why]
> dcn301_calculate_wm_and_dl() causes flickering when external monitor is
> connected.
>
> This issue has been fixed before by commit 0e4c0ae59d7e
> ("drm/amdgpu/display: drop dcn301_calculate_wm_and_dl for now"),
> however part of the fix was gone after commit 2cbcb78c9ee5 ("Merge tag
> 'amd-drm-next-5.13-2021-03-23' of
> https://gitlab.freedesktop.org/agd5f/linux into drm-next").
>
> [how]
> Use dcn30_calculate_wm_and_dlg() instead as in the original fix.
>
> Fixes: 2cbcb78c9ee5 ("Merge tag 'amd-drm-next-5.13-2021-03-23' of
> https://gitlab.freedesktop.org/agd5f/linux into drm-next")
> Signed-off-by: Nikola Cornij 

Reviewed-by: Zhan Liu 
Tested-by: Zhan Liu 
Tested-by: Oliver Logush 

> ---
>  .../amd/display/dc/dcn301/dcn301_resource.c   | 96 +--
>  1 file changed, 1 insertion(+), 95 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> index 9776d1737818..912285fdce18 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> @@ -1622,106 +1622,12 @@ static void
> dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
> dml_init_instance(>dml, _01_soc, _01_ip,
> DML_PROJECT_DCN30);  }
>
> -static void calculate_wm_set_for_vlevel(
> -   int vlevel,
> -   struct wm_range_table_entry *table_entry,
> -   struct dcn_watermarks *wm_set,
> -   struct display_mode_lib *dml,
> -   display_e2e_pipe_params_st *pipes,
> -   int pipe_cnt)
> -{
> -   double dram_clock_change_latency_cached = dml-
> >soc.dram_clock_change_latency_us;
> -
> -   ASSERT(vlevel < dml->soc.num_states);
> -   /* only pipe 0 is read for voltage and dcf/soc clocks */
> -   pipes[0].clks_cfg.voltage = vlevel;
> -   pipes[0].clks_cfg.dcfclk_mhz = 
> dml->soc.clock_limits[vlevel].dcfclk_mhz;
> -   pipes[0].clks_cfg.socclk_mhz = 
> dml->soc.clock_limits[vlevel].socclk_mhz;
> -
> -   dml->soc.dram_clock_change_latency_us = table_entry-
> >pstate_latency_us;
> -   dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
> -   dml->soc.sr_enter_plus_exit_time_us = table_entry-
> >sr_enter_plus_exit_time_us;
> -
> -   wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
> -   wm_set->cstate_pstate.cstate_enter_plus_exit_ns =
> get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
> -   wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes,
> pipe_cnt) * 1000;
> -   wm_set->cstate_pstate.pstate_change_ns =
> get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
> -   wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes,
> pipe_cnt) * 1000;
> -   wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml,
> pipes, pipe_cnt) * 1000;
> -   wm_set->frac_urg_bw_flip =
> get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
> -   wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt)
> * 1000;
> -   dml->soc.dram_clock_change_latency_us =
> dram_clock_change_latency_cached;
> -
> -}
> -
> -static void dcn301_calculate_wm_and_dlg(
> -   struct dc *dc, struct dc_state *context,
> -   display_e2e_pipe_params_st *pipes,
> -   int pipe_cnt,
> -   int vlevel_req)
> -{
> -   int i, pipe_idx;
> -   int vlevel, vlevel_max;
> -   struct wm_range_table_entry *table_entry;
> -   struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
> -
> -   ASSERT(bw_params);
> -
> -   vlevel_max = bw_params->clk_table.num_entries - 1;
> -
> -   /* WM Set D */
> -   table_entry = _params->wm_table.entries[WM_D];
> -   if (table_entry->wm_type == WM_TYPE_RETRAINING)
> -   vlevel = 0;
> -   else
> -   vlevel = vlevel_max;
> -   calculate_wm_set_for_vlevel(vlevel, table_entry, 
> >bw_ctx.bw.dcn.watermarks.d,
> -   >bw_ctx.dml, pipes, 
> pipe_cnt);
> -   /* WM Set C */
> -   table_entry = _params->wm_table.entries[WM_C];
> -   vlevel = min(max(vlevel_req, 2), vlevel_max);
> -

[PATCH] drm/amd/display: Use DCN30 watermark calc for DCN301

2021-08-13 Thread Liu, Zhan

[AMD Official Use Only]

[why]
dcn301_calculate_wm_and_dl() causes flickering when external monitor is
connected.

This issue has been fixed before by commit 0e4c0ae59d7e
("drm/amdgpu/display: drop dcn301_calculate_wm_and_dl for now"), however
part of the fix was gone after commit 2cbcb78c9ee5 ("Merge tag
'amd-drm-next-5.13-2021-03-23' of
https://gitlab.freedesktop.org/agd5f/linux into drm-next").

[how]
Use dcn30_calculate_wm_and_dlg() instead as in the original fix.

Fixes: 2cbcb78c9ee5 ("Merge tag 'amd-drm-next-5.13-2021-03-23' of 
https://gitlab.freedesktop.org/agd5f/linux into drm-next")
Signed-off-by: Nikola Cornij mailto:nikola.cor...@amd.com
---
 .../amd/display/dc/dcn301/dcn301_resource.c   | 96 +--
 1 file changed, 1 insertion(+), 95 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index 9776d1737818..912285fdce18 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -1622,106 +1622,12 @@ static void dcn301_update_bw_bounding_box(struct dc 
*dc, struct clk_bw_params *b
dml_init_instance(>dml, _01_soc, _01_ip, 
DML_PROJECT_DCN30);
 }

-static void calculate_wm_set_for_vlevel(
-   int vlevel,
-   struct wm_range_table_entry *table_entry,
-   struct dcn_watermarks *wm_set,
-   struct display_mode_lib *dml,
-   display_e2e_pipe_params_st *pipes,
-   int pipe_cnt)
-{
-   double dram_clock_change_latency_cached = 
dml->soc.dram_clock_change_latency_us;
-
-   ASSERT(vlevel < dml->soc.num_states);
-   /* only pipe 0 is read for voltage and dcf/soc clocks */
-   pipes[0].clks_cfg.voltage = vlevel;
-   pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
-   pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
-
-   dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
-   dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
-   dml->soc.sr_enter_plus_exit_time_us = 
table_entry->sr_enter_plus_exit_time_us;
-
-   wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
-   wm_set->cstate_pstate.cstate_enter_plus_exit_ns = 
get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
-   wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, 
pipe_cnt) * 1000;
-   wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, 
pipes, pipe_cnt) * 1000;
-   wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 
1000;
-   wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, 
pipe_cnt) * 1000;
-   wm_set->frac_urg_bw_flip = 
get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
-   wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 
1000;
-   dml->soc.dram_clock_change_latency_us = 
dram_clock_change_latency_cached;
-
-}
-
-static void dcn301_calculate_wm_and_dlg(
-   struct dc *dc, struct dc_state *context,
-   display_e2e_pipe_params_st *pipes,
-   int pipe_cnt,
-   int vlevel_req)
-{
-   int i, pipe_idx;
-   int vlevel, vlevel_max;
-   struct wm_range_table_entry *table_entry;
-   struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
-
-   ASSERT(bw_params);
-
-   vlevel_max = bw_params->clk_table.num_entries - 1;
-
-   /* WM Set D */
-   table_entry = _params->wm_table.entries[WM_D];
-   if (table_entry->wm_type == WM_TYPE_RETRAINING)
-   vlevel = 0;
-   else
-   vlevel = vlevel_max;
-   calculate_wm_set_for_vlevel(vlevel, table_entry, 
>bw_ctx.bw.dcn.watermarks.d,
-   >bw_ctx.dml, pipes, 
pipe_cnt);
-   /* WM Set C */
-   table_entry = _params->wm_table.entries[WM_C];
-   vlevel = min(max(vlevel_req, 2), vlevel_max);
-   calculate_wm_set_for_vlevel(vlevel, table_entry, 
>bw_ctx.bw.dcn.watermarks.c,
-   >bw_ctx.dml, pipes, 
pipe_cnt);
-   /* WM Set B */
-   table_entry = _params->wm_table.entries[WM_B];
-   vlevel = min(max(vlevel_req, 1), vlevel_max);
-   calculate_wm_set_for_vlevel(vlevel, table_entry, 
>bw_ctx.bw.dcn.watermarks.b,
-   >bw_ctx.dml, pipes, 
pipe_cnt);
-
-   /* WM Set A */
-   table_entry = _params->wm_table.entries[WM_A];
-   vlevel = min(vlevel_req, vlevel_max);
-   calculate_wm_set_for_vlevel(vlevel, table_entry, 
>bw_ctx.bw.dcn.watermarks.a,
-   >bw_ctx.dml, pipes, 
pipe_cnt);
-
-   for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
-   if (!context->res_ctx.pipe_ctx[i].stream)
-   continue;
-
-

[PATCH] drm/amd/display: Enabling eDP no power sequencing with DAL feature mask

2021-06-21 Thread Liu, Zhan

[Public]

[Why]
Sometimes, DP receiver chip power-controlled externally by an
Embedded Controller could be treated and used as eDP,
if it drives mobile display. In this case,
we shouldn't be doing power-sequencing, hence we can skip
waiting for T7-ready and T9-ready."

[How]
Added a feature mask to enable eDP no power sequencing feature.

To enable this, set 0x10 flag in amdgpu.dcfeaturemask on
Linux command line.

Signed-off-by: Zhan Liu 
Change-Id: I15e8fb2979fe3ff5491ccf1ee384693d4dce787c
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c   |  1 +
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  3 ++
 drivers/gpu/drm/amd/display/dc/dc.h   |  1 +
 .../display/dc/dce110/dce110_hw_sequencer.c   | 31 ---
 drivers/gpu/drm/amd/include/amd_shared.h  | 10 +++---
 5 files changed, 38 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 3de1accb060e..b588cf4398db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -159,6 +159,7 @@ int amdgpu_smu_pptable_id = -1;
  * highest. That helps saving some idle power.
  * DISABLE_FRACTIONAL_PWM (bit 2) disabled by default
  * PSR (bit 3) disabled by default
+ * EDP NO POWER SEQUENCING (bit 4) disabled by default
  */
 uint amdgpu_dc_feature_mask = 2;
 uint amdgpu_dc_debug_mask;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index c0a3119982b0..abba26c8f20a 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1174,6 +1174,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
if (amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK)
init_data.flags.disable_fractional_pwm = true;

+   if (amdgpu_dc_feature_mask & DC_EDP_NO_POWER_SEQUENCING)
+   init_data.flags.edp_no_power_sequencing = true;
+
init_data.flags.power_down_display_on_boot = true;

INIT_LIST_HEAD(>dm.da_list);
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h 
b/drivers/gpu/drm/amd/display/dc/dc.h
index a70697898025..7f1d2d6f9de8 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -297,6 +297,7 @@ struct dc_config {
bool allow_seamless_boot_optimization;
bool power_down_display_on_boot;
bool edp_not_connected;
+   bool edp_no_power_sequencing;
bool force_enum_edp;
bool forced_clocks;
bool allow_lttpr_non_transparent_mode;
diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index 53dd305fa6b0..013d94c9506a 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1023,8 +1023,20 @@ void dce110_edp_backlight_control(
/* dc_service_sleep_in_milliseconds(50); */
/*edp 1.2*/
panel_instance = link->panel_cntl->inst;
-   if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
-   edp_receiver_ready_T7(link);
+
+   if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {
+   if (!link->dc->config.edp_no_power_sequencing)
+   /*
+* Sometimes, DP receiver chip power-controlled externally by an
+* Embedded Controller could be treated and used as eDP,
+* if it drives mobile display. In this case,
+* we shouldn't be doing power-sequencing, hence we can skip
+* waiting for T7-ready.
+*/
+   edp_receiver_ready_T7(link);
+   else
+   DC_LOG_DC("edp_receiver_ready_T7 skipped\n");
+   }

if (ctx->dc->ctx->dmub_srv &&
ctx->dc->debug.dmub_command_table) {
@@ -1049,8 +1061,19 @@ void dce110_edp_backlight_control(
dc_link_backlight_enable_aux(link, enable);

/*edp 1.2*/
-   if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
-   edp_add_delay_for_T9(link);
+   if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) {
+   if (!link->dc->config.edp_no_power_sequencing)
+   /*
+* Sometimes, DP receiver chip power-controlled externally by an
+* Embedded Controller could be treated and used as eDP,
+* if it drives mobile display. In this case,
+* we shouldn't be doing power-sequencing, hence we can skip
+* waiting for T9-ready.
+*/
+   edp_add_delay_for_T9(link);
+   else
+   DC_LOG_DC("edp_receiver_ready_T9 skipped\n");
+   }

if (!enable && link->dpcd_sink_ext_caps.bits.oled)
msleep(OLED_PRE_T11_DELAY);
diff --git

RE: [PATCH] drm/amdgpu/vangogh: don't check for dpm in is_dpm_running when in suspend

2021-03-26 Thread Liu, Zhan

[AMD Public Use]

> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: 2021/March/26, Friday 4:58 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: [PATCH] drm/amdgpu/vangogh: don't check for dpm in
> is_dpm_running when in suspend
>
> Do the same thing we do for Renoir.  We can check, but since the sbios has
> started DPM, it will always return true which causes the driver to skip some
> of the SMU init when it shouldn't.
>
> Signed-off-by: Alex Deucher 

Reviewed-by: Zhan Liu 

> ---
>  drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 5 +
>  1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> index 2f502fec67d5..ed11e0ab8299 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
> @@ -384,10 +384,15 @@ static int vangogh_dpm_set_jpeg_enable(struct
> smu_context *smu, bool enable)
>
>  static bool vangogh_is_dpm_running(struct smu_context *smu)  {
> +struct amdgpu_device *adev = smu->adev;
>  int ret = 0;
>  uint32_t feature_mask[2];
>  uint64_t feature_enabled;
>
> +/* we need to re-init after suspend so return false */
> +if (adev->in_suspend)
> +return false;
> +
>  ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
>
>  if (ret)
> --
> 2.30.2
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org

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RE: [PATCH] drm/amdgpu/swsmu: don't bail early on hw_setup on resume

2021-03-26 Thread Liu, Zhan

[AMD Public Use]

> -Original Message-
> From: Alex Deucher 
> Sent: 2021/March/26, Friday 5:01 PM
> To: Deucher, Alexander 
> Cc: Liu, Zhan ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amdgpu/swsmu: don't bail early on hw_setup on
> resume
>
> Looks like RN is immune due to the way it's is_dpm_running function is
> implemented.  Maybe something like this is a better solution:
> https://patchwork.freedesktop.org/patch/426293/
>
> Alex

Thanks Alex! Yes, I agree, this solution looks better to me. Since we've 
already done the same thing
for RN, it totally makes sense for us to make VG immune as well. And we can 
limit the influence
to VG only in this case.

Its self-explanatory that this change can get the issue fixed, but I still gave 
it a run on VG
and confirmed the issue is indeed get fixed here.

I will add my "Reviewed-by" under your new patch.

>
> On Fri, Mar 26, 2021 at 10:12 AM Deucher, Alexander
>  wrote:
> >
> > [AMD Official Use Only - Internal Distribution Only]
> >
> >
> > Can someone double check this on RN/CZN with S3 and S0ix?
> >
> > Alex
> >
> > 
> > From: Liu, Zhan 
> > Sent: Friday, March 26, 2021 1:46 AM
> > To: Deucher, Alexander ;
> > amd-gfx@lists.freedesktop.org 
> > Cc: Deucher, Alexander 
> > Subject: RE: [PATCH] drm/amdgpu/swsmu: don't bail early on hw_setup on
> > resume
> >
> > [AMD Official Use Only - Internal Distribution Only]
> >
> > > -Original Message-
> > > From: amd-gfx  On Behalf Of
> > > Alex Deucher
> > > Sent: 2021/March/26, Friday 12:38 AM
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Deucher, Alexander 
> > > Subject: [PATCH] drm/amdgpu/swsmu: don't bail early on hw_setup on
> > > resume
> > >
> > > The SMU comes back up with DPM enabled by the sbios, but the driver
> > > still has to set up the SMU/driver mailbox, etc.
> > >
> > > Signed-off-by: Alex Deucher 
> >
> > Reviewed-by: Zhan Liu 
> >
> > > ---
> > >  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > > b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > > index d4b804c7b986..462917d4d5e2 100644
> > > --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > > +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> > > @@ -1102,7 +1102,7 @@ static int smu_smc_hw_setup(struct
> smu_context
> > > *smu)
> > >  uint32_t pcie_gen = 0, pcie_width = 0;  int ret = 0;
> > >
> > > -if (adev->in_suspend && smu_is_dpm_running(smu)) {
> > > +if (!smu->is_apu && adev->in_suspend &&
> > > smu_is_dpm_running(smu)) {
> > >  dev_info(adev->dev, "dpm has been enabled\n");
> > >  /* this is needed specifically */
> > >  if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
> > > --
> > > 2.30.2
> > >
> > > ___
> > > amd-gfx mailing list
> > > amd-gfx@lists.freedesktop.org
> > >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org

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RE: [PATCH] drm/amdgpu/swsmu: don't bail early on hw_setup on resume

2021-03-25 Thread Liu, Zhan

[AMD Official Use Only - Internal Distribution Only]

> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: 2021/March/26, Friday 12:38 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: [PATCH] drm/amdgpu/swsmu: don't bail early on hw_setup on
> resume
>
> The SMU comes back up with DPM enabled by the sbios, but the driver still
> has to set up the SMU/driver mailbox, etc.
>
> Signed-off-by: Alex Deucher 

Reviewed-by: Zhan Liu 

> ---
>  drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index d4b804c7b986..462917d4d5e2 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -1102,7 +1102,7 @@ static int smu_smc_hw_setup(struct smu_context
> *smu)
>  uint32_t pcie_gen = 0, pcie_width = 0;
>  int ret = 0;
>
> -if (adev->in_suspend && smu_is_dpm_running(smu)) {
> +if (!smu->is_apu && adev->in_suspend &&
> smu_is_dpm_running(smu)) {
>  dev_info(adev->dev, "dpm has been enabled\n");
>  /* this is needed specifically */
>  if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
> --
> 2.30.2
>
> ___
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
> freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfxdata=04%7C01%7Czhan.liu%40amd.com%7C500744d08f7946b2c5d
> e08d8f010ec49%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C6375
> 23302768646367%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiL
> CJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000sdata=vN
> JawxwfojJrxNOG5L8Y2BAWpGRRN6valpk6y00XIQw%3Dreserved=0
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RE: [PATCH v2] drm/amdgpu: Do not change amdgpu framebuffer format during page flip

2021-01-07 Thread Liu, Zhan




> -Original Message-
> From: Daniel Vetter 
> Sent: 2021/January/07, Thursday 12:33 PM
> To: Koenig, Christian 
> Cc: Liu, Zhan ; amd-gfx@lists.freedesktop.org; Cornij,
> Nikola ; Wang, Chao-kai (Stylon)
> ; Wang, Chao-kai (Stylon)
> ; dri-de...@lists.freedesktop.org; Kazlauskas,
> Nicholas ; b...@basnieuwenhuizen.nl
> Subject: Re: [PATCH v2] drm/amdgpu: Do not change amdgpu framebuffer
> format during page flip
> 
> On Sun, Jan 03, 2021 at 04:43:37PM +0100, Christian König wrote:
> > Am 29.12.20 um 22:10 schrieb Zhan Liu:
> > > [Why]
> > > Driver cannot change amdgpu framebuffer (afb) format while doing
> > > page flip. Force system doing so will cause ioctl error, and result
> > > in breaking several functionalities including FreeSync.
> > >
> > > If afb format is forced to change during page flip, following
> > > message will appear in dmesg.log:
> > >
> > > "[drm:drm_mode_page_flip_ioctl [drm]] Page flip is not allowed to
> > > change frame buffer format."
> > >
> > > [How]
> > > Do not change afb format while doing page flip. It is okay to check
> > > whether afb format is valid here, however, forcing afb format change
> > > shouldn't happen here.
> >
> > I don't think this we can do this.
> >
> > It is perfectly valid for a page flip to switch between linear and
> > tiled formats on an I+A or A+A laptop.
> 
> It is, but that's not the bug here. struct drm_framebuffer.format is supposed
> to be invariant over the lifetime of a drm_fb object, you need to set it when
> the fb is created and never change it afterwards. So the patch here isn't yet
> the real deal.
> 
> Also this means the implicit tiling information cannot be changed after a fb 
> is
> created for a given bo, but we've discussed this at length and that limitation
> should be all ok.
> -Daniel

Thank you Christian and Daniel for the input!

Bas recently submitted an alternative patch ([PATCH] drm: Check actual format 
for legacy pageflip.) 
which addresses the same issue, and his patch makes more sense to me, so I will 
abandon my patch in this case.

Thanks,
Zhan


> 
> >
> > Christian.
> >
> > >
> > > Signed-off-by: Zhan Liu 
> > > ---
> > >   drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 3 ++-
> > >   1 file changed, 2 insertions(+), 1 deletion(-)
> > >
> > > Thanks Nick and Bas. Here is my second patch for review.
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > > index a638709e9c92..8a12e27ff4ec 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
> > > @@ -832,7 +832,8 @@ static int convert_tiling_flags_to_modifier(struct
> amdgpu_framebuffer *afb)
> > >   if (!format_info)
> > >   return -EINVAL;
> > > - afb->base.format = format_info;
> > > + if (!afb->base.format)
> > > + afb->base.format = format_info;
> > >   }
> > >   }
> >
> > ___
> > dri-devel mailing list
> > dri-de...@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Fdri-
> develdata=04%7C01%7C
> >
> zhan.liu%40amd.com%7Cda23e6e33a7e46dfc4e308d8b33242c8%7C3dd896
> 1fe4884e
> >
> 608e11a82d994e183d%7C0%7C0%7C637456375746425509%7CUnknown%
> 7CTWFpbGZsb3
> >
> d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0
> %3D%7
> >
> C1000sdata=5lCm4d6FHihfFHUf5mVym0O6lKmZHgR89%2F2Eqj2ojhg
> %3Dr
> > eserved=0
> 
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fblog.ff
> wll.ch%2Fdata=04%7C01%7Czhan.liu%40amd.com%7Cda23e6e33a7e
> 46dfc4e308d8b33242c8%7C3dd8961fe4884e608e11a82d994e183d%7C0%7
> C0%7C637456375746425509%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4
> wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000
> mp;sdata=44x858klbIcVeRtP%2BuJST2K3xuCLisjbfhV9rEQrzpA%3Drese
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RE: [PATCH] drm: Check actual format for legacy pageflip.

2021-01-07 Thread Liu, Zhan

[AMD Official Use Only - Internal Distribution Only]

> -Original Message-
> From: Liu, Zhan
> Sent: 2021/January/06, Wednesday 10:04 AM
> To: Bas Nieuwenhuizen ; Mario Kleiner
> 
> Cc: dri-devel ; amd-gfx list  g...@lists.freedesktop.org>; Deucher, Alexander
> ; Daniel Vetter ;
> Kazlauskas, Nicholas ; Ville Syrjälä
> 
> Subject: RE: [PATCH] drm: Check actual format for legacy pageflip.
>
>
> > -Original Message-
> > From: Liu, Zhan 
> > Sent: 2021/January/04, Monday 3:46 PM
> > To: Bas Nieuwenhuizen ; Mario Kleiner
> > 
> > Cc: dri-devel ; amd-gfx list  > g...@lists.freedesktop.org>; Deucher, Alexander
> > ; Daniel Vetter ;
> > Kazlauskas, Nicholas ; Ville Syrjälä
> > 
> > Subject: Re: [PATCH] drm: Check actual format for legacy pageflip.
> >
> >
> >
> > + Ville
> >
> > On Sat, Jan 2, 2021 at 4:31 PM Mario Kleiner
> > 
> > wrote:
> > >
> > > On Sat, Jan 2, 2021 at 3:02 PM Bas Nieuwenhuizen
> > >  wrote:
> > > >
> > > > With modifiers one can actually have different format_info structs
> > > > for the same format, which now matters for AMDGPU since we convert
> > > > implicit modifiers to explicit modifiers with multiple planes.
> > > >
> > > > I checked other drivers and it doesn't look like they end up
> > > > triggering this case so I think this is safe to relax.
> > > >
> > > > Signed-off-by: Bas Nieuwenhuizen 
> > > > Fixes: 816853f9dc40 ("drm/amd/display: Set new format info for
> > > >converted metadata.")
> > > > ---
> > > >  drivers/gpu/drm/drm_plane.c | 2 +-
> > > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/drm_plane.c
> > > > b/drivers/gpu/drm/drm_plane.c index e6231947f987..f5085990cfac
> > > > 100644
> > > > --- a/drivers/gpu/drm/drm_plane.c
> > > > +++ b/drivers/gpu/drm/drm_plane.c
> > > > @@ -1163,7 +1163,7 @@ int drm_mode_page_flip_ioctl(struct
> > drm_device
> > > >*dev,
> > > > if (ret)
> > > > goto out;
> > > >
> > > > -   if (old_fb->format != fb->format) {
> > > > +   if (old_fb->format->format != fb->format->format) {
> > >
> >
> > I agree with this patch, though considering the original way was made
> > by Ville, I will wait for Ville's input first. Adding my "Acked-by" here.
> >
> > This patch is:
> > Acked-by: Zhan Liu 

Since there is no objection from the community on this patch over the past few 
days, and this patch totally makes sense to me, this patch is:

Reviewed-by: Zhan Liu 

>
> Ping...
>
> >
> > > This was btw. the original way before Ville made it more strict
> > > about
> > > 4 years ago, to catch issues related to tiling, and more complex
> > > layouts, like the dcc tiling/retiling introduced by your modifier
> > > patches. That's why I hope my alternative patch is a good solution
> > > for atomic drivers while keeping the strictness for potential legacy
> > > drivers.
> > >
> > > -mario
> > >
> > > > DRM_DEBUG_KMS("Page flip is not allowed to change
> > > >frame buffer format.\n");
> > > > ret = -EINVAL;
> > > > goto out;
> > > > --
> > > > 2.29.2
> > > >
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RE: [PATCH] drm: Check actual format for legacy pageflip.

2021-01-06 Thread Liu, Zhan

[AMD Official Use Only - Internal Distribution Only]

> -Original Message-
> From: Liu, Zhan 
> Sent: 2021/January/04, Monday 3:46 PM
> To: Bas Nieuwenhuizen ; Mario Kleiner
> 
> Cc: dri-devel ; amd-gfx list  g...@lists.freedesktop.org>; Deucher, Alexander
> ; Daniel Vetter ;
> Kazlauskas, Nicholas ; Ville Syrjälä
> 
> Subject: Re: [PATCH] drm: Check actual format for legacy pageflip.
>
>
>
> + Ville
>
> On Sat, Jan 2, 2021 at 4:31 PM Mario Kleiner 
> wrote:
> >
> > On Sat, Jan 2, 2021 at 3:02 PM Bas Nieuwenhuizen
> >  wrote:
> > >
> > > With modifiers one can actually have different format_info structs
> > > for the same format, which now matters for AMDGPU since we convert
> > > implicit modifiers to explicit modifiers with multiple planes.
> > >
> > > I checked other drivers and it doesn't look like they end up
> > > triggering this case so I think this is safe to relax.
> > >
> > > Signed-off-by: Bas Nieuwenhuizen 
> > > Fixes: 816853f9dc40 ("drm/amd/display: Set new format info for
> > >converted metadata.")
> > > ---
> > >  drivers/gpu/drm/drm_plane.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/drm_plane.c
> > > b/drivers/gpu/drm/drm_plane.c index e6231947f987..f5085990cfac
> > > 100644
> > > --- a/drivers/gpu/drm/drm_plane.c
> > > +++ b/drivers/gpu/drm/drm_plane.c
> > > @@ -1163,7 +1163,7 @@ int drm_mode_page_flip_ioctl(struct
> drm_device
> > >*dev,
> > > if (ret)
> > > goto out;
> > >
> > > -   if (old_fb->format != fb->format) {
> > > +   if (old_fb->format->format != fb->format->format) {
> >
>
> I agree with this patch, though considering the original way was made by
> Ville, I will wait for Ville's input first. Adding my "Acked-by" here.
>
> This patch is:
> Acked-by: Zhan Liu 

Ping...

>
> > This was btw. the original way before Ville made it more strict about
> > 4 years ago, to catch issues related to tiling, and more complex
> > layouts, like the dcc tiling/retiling introduced by your modifier
> > patches. That's why I hope my alternative patch is a good solution for
> > atomic drivers while keeping the strictness for potential legacy
> > drivers.
> >
> > -mario
> >
> > > DRM_DEBUG_KMS("Page flip is not allowed to change
> > >frame buffer format.\n");
> > > ret = -EINVAL;
> > > goto out;
> > > --
> > > 2.29.2
> > >
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Re: [PATCH] drm: Check actual format for legacy pageflip.

2021-01-04 Thread Liu, Zhan

[AMD Official Use Only - Internal Distribution Only]

+ Ville

On Sat, Jan 2, 2021 at 4:31 PM Mario Kleiner  wrote:
>
> On Sat, Jan 2, 2021 at 3:02 PM Bas Nieuwenhuizen
>  wrote:
> >
> > With modifiers one can actually have different format_info structs
> > for the same format, which now matters for AMDGPU since we convert
> > implicit modifiers to explicit modifiers with multiple planes.
> >
> > I checked other drivers and it doesn't look like they end up triggering
> > this case so I think this is safe to relax.
> >
> > Signed-off-by: Bas Nieuwenhuizen 
> > Fixes: 816853f9dc40 ("drm/amd/display: Set new format info for converted 
> > metadata.")
> > ---
> >  drivers/gpu/drm/drm_plane.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
> > index e6231947f987..f5085990cfac 100644
> > --- a/drivers/gpu/drm/drm_plane.c
> > +++ b/drivers/gpu/drm/drm_plane.c
> > @@ -1163,7 +1163,7 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev,
> > if (ret)
> > goto out;
> >
> > -   if (old_fb->format != fb->format) {
> > +   if (old_fb->format->format != fb->format->format) {
>

I agree with this patch, though considering the original way was made by Ville, 
I will wait for Ville's input first. Adding my "Acked-by" here.

This patch is:
Acked-by: Zhan Liu 

> This was btw. the original way before Ville made it more strict about
> 4 years ago, to catch issues related to tiling, and more complex
> layouts, like the dcc tiling/retiling introduced by your modifier
> patches. That's why I hope my alternative patch is a good solution for
> atomic drivers while keeping the strictness for potential legacy
> drivers.
>
> -mario
>
> > DRM_DEBUG_KMS("Page flip is not allowed to change frame 
> > buffer format.\n");
> > ret = -EINVAL;
> > goto out;
> > --
> > 2.29.2
> >
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RE: [PATCH] drm/amd/display: Remove aconnector condition check for dpcd read

2020-04-17 Thread Liu, Zhan

+ Joseph



Hi Joseph,

Would you like to help me review this change? This was a follow-up on the 
discussion we had earlier this year.

Thanks,
Zhan


> -Original Message-
> From: Liu, Zhan 
> Sent: 2020/April/16, Thursday 3:24 PM
> To: amd-gfx@lists.freedesktop.org; Liu, Zhan 
> Subject: [PATCH] drm/amd/display: Remove aconnector condition check for
> dpcd read
> 
> [Why]
> Aconnector is not necessary to be NULL in order to read dpcd successfully.
> 
> Actually if we rely on checking aconnector here, we won't be able to turn off
> all displays before doing display detection. That will cause some MST hubs
> not able to light up.
> 
> [How]
> Remove aconnector check when turning off all displays at hardware
> initialization stage.
> 
> Signed-off-by: Zhan Liu 
> ---
>  .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 36 ---
>  1 file changed, 14 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> index 9f41efddc9bc..6f33f3f0d023 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
> @@ -1332,31 +1332,23 @@ void dcn10_init_hw(struct dc *dc)
>   if (dc->links[i]->connector_signal !=
> SIGNAL_TYPE_DISPLAY_PORT)
>   continue;
> 
> - /*
> -  * core_link_read_dpcd() will invoke
> dm_helpers_dp_read_dpcd(),
> -  * which needs to read dpcd info with the help of
> aconnector.
> -  * If aconnector (dc->links[i]->prev) is NULL, then
> dpcd status
> -  * cannot be read.
> -  */
> - if (dc->links[i]->priv) {
> - /* if any of the displays are lit up turn them
> off */
> - status = core_link_read_dpcd(dc->links[i],
> DP_SET_POWER,
> -
>   _power_state, sizeof(dpcd_power_state));
> - if (status == DC_OK && dpcd_power_state ==
> DP_POWER_STATE_D0) {
> - /* blank dp stream before power off
> receiver*/
> - if (dc->links[i]->link_enc->funcs-
> >get_dig_frontend) {
> - unsigned int fe = dc->links[i]-
> >link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc);
> -
> - for (j = 0; j < dc->res_pool-
> >stream_enc_count; j++) {
> - if (fe == dc-
> >res_pool->stream_enc[j]->id) {
> - dc-
> >res_pool->stream_enc[j]->funcs->dp_blank(
> -
>   dc->res_pool->stream_enc[j]);
> - break;
> - }
> + /* if any of the displays are lit up turn them off */
> + status = core_link_read_dpcd(dc->links[i],
> DP_SET_POWER,
> + _power_state,
> sizeof(dpcd_power_state));
> + if (status == DC_OK && dpcd_power_state ==
> DP_POWER_STATE_D0) {
> + /* blank dp stream before power off
> receiver*/
> + if (dc->links[i]->link_enc->funcs-
> >get_dig_frontend) {
> + unsigned int fe =
> +dc->links[i]->link_enc->funcs->get_dig_frontend(dc->links[i]->link_enc)
> +;
> +
> + for (j = 0; j < dc->res_pool-
> >stream_enc_count; j++) {
> + if (fe == dc->res_pool-
> >stream_enc[j]->id) {
> + dc->res_pool-
> >stream_enc[j]->funcs->dp_blank(
> +
>   dc->res_pool->stream_enc[j]);
> + break;
>   }
>   }
> - dp_receiver_power_ctrl(dc->links[i],
> false);
>   }
> + dp_receiver_power_ctrl(dc->links[i], false);
>   }
>   }
>   }
> --
> 2.17.1

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Re: [PATCH] drm/amd/display: re-order asic declarations

2020-04-02 Thread Liu, Zhan

[AMD Official Use Only - Internal Distribution Only]

From: amd-gfx  on behalf of Shirish S 


Sent: Thursday, April 2, 2020 5:15 AM

To: Deucher, Alexander ; Wentland, Harry 
; Li, Sun peng (Leo) 

Cc: amd-gfx@lists.freedesktop.org ; S, Shirish 


Subject: [PATCH] drm/amd/display: re-order asic declarations




"1382d6409891 drm/amd/display: Fix RV2 Variant Detection"

introduces build error of:

"use of undeclared identifier 'RENOIR_A0'"



To fix the same, this patch re-orders the

ASIC declarations accordingly.



Signed-off-by: Shirish S 


Reviewed-by: Zhan Liu 




---

 drivers/gpu/drm/amd/display/include/dal_asic_id.h | 6 --

 1 file changed, 4 insertions(+), 2 deletions(-)



diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h 
b/drivers/gpu/drm/amd/display/include/dal_asic_id.h

index 8a87d0ed90ae..2359e88d6029 100644

--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h

+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h

@@ -136,6 +136,7 @@

 #define RAVEN2_A0 0x81

 #define RAVEN1_F0 0xF0

 #define RAVEN_UNKNOWN 0xFF

+#define RENOIR_A0 0x91

 #ifndef ASICREV_IS_RAVEN

 #define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < 
RAVEN_UNKNOWN)

 #endif

@@ -171,8 +172,6 @@ enum {

 #define ASICREV_IS_NAVI10_P(eChipRev)(eChipRev < NV_NAVI12_P_A0)

 #define ASICREV_IS_NAVI12_P(eChipRev)((eChipRev >= NV_NAVI12_P_A0) && 
(eChipRev < NV_NAVI14_M_A0))

 #define ASICREV_IS_NAVI14_M(eChipRev)((eChipRev >= NV_NAVI14_M_A0) && 
(eChipRev < NV_UNKNOWN))

-#define RENOIR_A0 0x91

-#define DEVICE_ID_RENOIR_1636 0x1636   // Renoir

 #define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < 
RAVEN1_F0))



 /*

@@ -183,6 +182,9 @@ enum {

 #define DEVICE_ID_TEMASH_9839 0x9839

 #define DEVICE_ID_TEMASH_983D 0x983D



+/* RENOIR */

+#define DEVICE_ID_RENOIR_1636 0x1636

+

 /* Asic Family IDs for different asic family. */

 #define FAMILY_CI 120 /* Sea Islands: Hawaii (P), Bonaire (M) */

 #define FAMILY_KV 125 /* Fusion => Kaveri: Spectre, Spooky; Kabini: Kalindi */

--

2.17.1



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RE: [PATCH 2/2] drm/amd/display: dc_link: code clean up on detect_dp function

2020-02-27 Thread Liu, Zhan



> -Original Message-
> From: amd-gfx  On Behalf Of Liu,
> Zhan
> Sent: 2020/February/27, Thursday 1:40 PM
> To: Melissa Wen ; Wentland, Harry
> ; Li, Sun peng (Leo) ;
> Deucher, Alexander ; Koenig, Christian
> ; Zhou, David(ChunMing)
> ; David Airlie ; Daniel Vetter
> ; Rodrigo Siqueira 
> Cc: amd-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org; linux-
> ker...@vger.kernel.org
> Subject: RE: [PATCH 2/2] drm/amd/display: dc_link: code clean up on
> detect_dp function
> 
> 
> > -Original Message-
> > From: amd-gfx  On Behalf Of
> > Melissa Wen
> > Sent: 2020/February/26, Wednesday 5:08 PM
> > To: Wentland, Harry ; Li, Sun peng (Leo)
> > ; Deucher, Alexander
> ;
> > Koenig, Christian ; Zhou, David(ChunMing)
> > ; David Airlie ; Daniel Vetter
> > ; Rodrigo Siqueira 
> > Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org;
> > linux- ker...@vger.kernel.org
> > Subject: [PATCH 2/2] drm/amd/display: dc_link: code clean up on
> > detect_dp function
> >
> > Removes codestyle issues on detect_dp function as suggested by
> > checkpatch.pl.
> >
> > CHECK: Lines should not end with a '('
> > WARNING: Missing a blank line after declarations
> > WARNING: line over 80 characters
> > CHECK: Alignment should match open parenthesis
> >
> > Signed-off-by: Melissa Wen 
> 
> Thank you Melissa for your contribution! Will apply it.
> 
> This patch is:
> Reviewed-by: Zhan Liu 

Sorry I didn't see Rodrigo already replied your email. Please send us a V2, 
then we will review your V2 patch.

And again, thank you so much for your contribution!

Zhan

> 
> > ---
> >  drivers/gpu/drm/amd/display/dc/core/dc_link.c | 35
> > +--
> >  1 file changed, 16 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> > b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> > index 0f28b5694144..adb717f02c9c 100644
> > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> > @@ -585,14 +585,14 @@ static void
> > read_current_link_settings_on_detect(struct dc_link *link)
> > LINK_SPREAD_05_DOWNSPREAD_30KHZ :
> > LINK_SPREAD_DISABLED;  }
> >
> > -static bool detect_dp(
> > -   struct dc_link *link,
> > -   struct display_sink_capability *sink_caps,
> > -   bool *converter_disable_audio,
> > -   struct audio_support *audio_support,
> > -   enum dc_detect_reason reason)
> > +static bool detect_dp(struct dc_link *link,
> > + struct display_sink_capability *sink_caps,
> > + bool *converter_disable_audio,
> > + struct audio_support *audio_support,
> > + enum dc_detect_reason reason)
> >  {
> > bool boot = false;
> > +
> > sink_caps->signal = link_detect_sink(link, reason);
> > sink_caps->transaction_type =
> > get_ddc_transaction_type(sink_caps->signal);
> > @@ -606,9 +606,8 @@ static bool detect_dp(
> > sink_caps->signal =
> > SIGNAL_TYPE_DISPLAY_PORT_MST;
> > link->type = dc_connection_mst_branch;
> >
> > -   dal_ddc_service_set_transaction_type(
> > -   link->ddc,
> > -   sink_caps-
> > >transaction_type);
> > +   dal_ddc_service_set_transaction_type(link->ddc,
> > +sink_caps-
> > >transaction_type);
> >
> > /*
> >  * This call will initiate MST topology discovery.
> > Which @@ -637,13 +636,10 @@ static bool detect_dp(
> > if (reason == DETECT_REASON_BOOT)
> > boot = true;
> >
> > -   dm_helpers_dp_update_branch_info(
> > -   link->ctx,
> > -   link);
> > +   dm_helpers_dp_update_branch_info(link->ctx, link);
> >
> > -   if (!dm_helpers_dp_mst_start_top_mgr(
> > -   link->ctx,
> > -   link, boot)) {
> > +   if (!dm_helpers_dp_mst_start_top_mgr(link->ctx,
> > +link, boot)) {
> > /* MST not supported */
> > link-

RE: [PATCH 2/2] drm/amd/display: dc_link: code clean up on detect_dp function

2020-02-27 Thread Liu, Zhan



> -Original Message-
> From: amd-gfx  On Behalf Of
> Melissa Wen
> Sent: 2020/February/26, Wednesday 5:08 PM
> To: Wentland, Harry ; Li, Sun peng (Leo)
> ; Deucher, Alexander
> ; Koenig, Christian
> ; Zhou, David(ChunMing)
> ; David Airlie ; Daniel Vetter
> ; Rodrigo Siqueira 
> Cc: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org; linux-
> ker...@vger.kernel.org
> Subject: [PATCH 2/2] drm/amd/display: dc_link: code clean up on detect_dp
> function
> 
> Removes codestyle issues on detect_dp function as suggested by
> checkpatch.pl.
> 
> CHECK: Lines should not end with a '('
> WARNING: Missing a blank line after declarations
> WARNING: line over 80 characters
> CHECK: Alignment should match open parenthesis
> 
> Signed-off-by: Melissa Wen 

Thank you Melissa for your contribution! Will apply it.

This patch is:
Reviewed-by: Zhan Liu 

> ---
>  drivers/gpu/drm/amd/display/dc/core/dc_link.c | 35 +--
>  1 file changed, 16 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index 0f28b5694144..adb717f02c9c 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -585,14 +585,14 @@ static void
> read_current_link_settings_on_detect(struct dc_link *link)
>   LINK_SPREAD_05_DOWNSPREAD_30KHZ :
> LINK_SPREAD_DISABLED;  }
> 
> -static bool detect_dp(
> - struct dc_link *link,
> - struct display_sink_capability *sink_caps,
> - bool *converter_disable_audio,
> - struct audio_support *audio_support,
> - enum dc_detect_reason reason)
> +static bool detect_dp(struct dc_link *link,
> +   struct display_sink_capability *sink_caps,
> +   bool *converter_disable_audio,
> +   struct audio_support *audio_support,
> +   enum dc_detect_reason reason)
>  {
>   bool boot = false;
> +
>   sink_caps->signal = link_detect_sink(link, reason);
>   sink_caps->transaction_type =
>   get_ddc_transaction_type(sink_caps->signal);
> @@ -606,9 +606,8 @@ static bool detect_dp(
>   sink_caps->signal =
> SIGNAL_TYPE_DISPLAY_PORT_MST;
>   link->type = dc_connection_mst_branch;
> 
> - dal_ddc_service_set_transaction_type(
> - link->ddc,
> - sink_caps-
> >transaction_type);
> + dal_ddc_service_set_transaction_type(link->ddc,
> +  sink_caps-
> >transaction_type);
> 
>   /*
>* This call will initiate MST topology discovery.
> Which @@ -637,13 +636,10 @@ static bool detect_dp(
>   if (reason == DETECT_REASON_BOOT)
>   boot = true;
> 
> - dm_helpers_dp_update_branch_info(
> - link->ctx,
> - link);
> + dm_helpers_dp_update_branch_info(link->ctx, link);
> 
> - if (!dm_helpers_dp_mst_start_top_mgr(
> - link->ctx,
> - link, boot)) {
> + if (!dm_helpers_dp_mst_start_top_mgr(link->ctx,
> +  link, boot)) {
>   /* MST not supported */
>   link->type = dc_connection_single;
>   sink_caps->signal =
> SIGNAL_TYPE_DISPLAY_PORT; @@ -651,7 +647,7 @@ static bool detect_dp(
>   }
> 
>   if (link->type != dc_connection_mst_branch &&
> - is_dp_active_dongle(link)) {
> + is_dp_active_dongle(link)) {
>   /* DP active dongles */
>   link->type = dc_connection_active_dongle;
>   if (!link->dpcd_caps.sink_count.bits.SINK_COUNT)
> { @@ -662,14 +658,15 @@ static bool detect_dp(
>   return true;
>   }
> 
> - if (link->dpcd_caps.dongle_type !=
> DISPLAY_DONGLE_DP_HDMI_CONVERTER)
> + if (link->dpcd_caps.dongle_type !=
> + DISPLAY_DONGLE_DP_HDMI_CONVERTER)
>   *converter_disable_audio = true;
>   }
>   } else {
>   /* DP passive dongles */
>   sink_caps->signal = dp_passive_dongle_detection(link->ddc,
> - sink_caps,
> - audio_support);
> + sink_caps,
> +
>   audio_support);
>   }
> 
>   return true;
> --
> 2.25.0
> 
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RE: [PATCH 13/15] drm/amdgpu/display: split dp connector registration (v3)

2020-02-25 Thread Liu, Zhan



> -Original Message-
> From: Liu, Zhan
> Sent: 2020/February/25, Tuesday 10:10 AM
> To: Alex Deucher ; Wentland, Harry
> 
> Cc: amd-gfx list ; Maling list - DRI
> developers ; Deucher, Alexander
> ; Broadworth, Mark
> 
> Subject: RE: [PATCH 13/15] drm/amdgpu/display: split dp connector
> registration (v3)
> 
> 
> > -Original Message-
> > From: Alex Deucher 
> > Sent: 2020/February/25, Tuesday 9:07 AM
> > To: Wentland, Harry 
> > Cc: amd-gfx list ; Maling list - DRI
> > developers ; Deucher, Alexander
> > ; Broadworth, Mark
> > ; Liu, Zhan 
> > Subject: Re: [PATCH 13/15] drm/amdgpu/display: split dp connector
> > registration (v3)
> >
> > On Mon, Feb 24, 2020 at 4:09 PM Harry Wentland 
> > wrote:
> > >
> > > On 2020-02-07 4:17 p.m., Alex Deucher wrote:
> > > > Split into init and register functions to avoid a segfault in some
> > > > configs when the load/unload callbacks are removed.
> > > >
> > >
> > > Looks like MST is completely broken with this change with a NULL
> > > pointer dereference in drm_dp_aux_register.
> > >
> > > > v2:
> > > > - add back accidently dropped has_aux setting
> > > > - set dev in late_register
> > > >
> > > > v3:
> > > > - fix dp cec ordering
> > > >
> > > > Signed-off-by: Alex Deucher 
> > > > ---
> > > >  drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c   | 16
> > 
> > > >  drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 10 ++
> > > >  .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c  |  7 ++-
> > > >  3 files changed, 24 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > > > index ec1501e3a63a..f355d9a752d2 100644
> > > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > > > @@ -1461,6 +1461,20 @@ static enum drm_mode_status
> > amdgpu_connector_dp_mode_valid(struct drm_connector
> > > >   return MODE_OK;
> > > >  }
> > > >
> > > > +static int
> > > > +amdgpu_connector_late_register(struct drm_connector *connector) {
> > > > + struct amdgpu_connector *amdgpu_connector =
> > to_amdgpu_connector(connector);
> > > > + int r = 0;
> > > > +
> > > > + if (amdgpu_connector->ddc_bus->has_aux) {
> > > > + amdgpu_connector->ddc_bus->aux.dev =
> > > > + amdgpu_connector-
> > >base.kdev;
> > > > + r = drm_dp_aux_register(_connector->ddc_bus->aux);
> > > > + }
> > > > +
> > > > + return r;
> > > > +}
> > > > +
> > > >  static const struct drm_connector_helper_funcs
> > amdgpu_connector_dp_helper_funcs = {
> > > >   .get_modes = amdgpu_connector_dp_get_modes,
> > > >   .mode_valid = amdgpu_connector_dp_mode_valid, @@ -1475,6
> > > > +1489,7 @@ static const struct drm_connector_funcs
> > amdgpu_connector_dp_funcs = {
> > > >   .early_unregister = amdgpu_connector_unregister,
> > > >   .destroy = amdgpu_connector_destroy,
> > > >   .force = amdgpu_connector_dvi_force,
> > > > + .late_register = amdgpu_connector_late_register,
> > > >  };
> > > >
> > > >  static const struct drm_connector_funcs
> > > > amdgpu_connector_edp_funcs = { @@ -1485,6 +1500,7 @@ static
> const
> > > > struct drm_connector_funcs
> > amdgpu_connector_edp_funcs = {
> > > >   .early_unregister = amdgpu_connector_unregister,
> > > >   .destroy = amdgpu_connector_destroy,
> > > >   .force = amdgpu_connector_dvi_force,
> > > > + .late_register = amdgpu_connector_late_register,
> > > >  };
> > > >
> > > >  void
> > > > diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> > > > b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> > > > index ea702a64f807..9b74cfdba7b8 100644
> > > > --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> > > > +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> > > > @@ -186,16 +186,10 @@ amdgpu_atombios_dp_aux_transfer(struct
> > > > drm_dp_aux *aux, struct drm_dp_aux_msg

RE: [PATCH 13/15] drm/amdgpu/display: split dp connector registration (v3)

2020-02-25 Thread Liu, Zhan



> -Original Message-
> From: Alex Deucher 
> Sent: 2020/February/25, Tuesday 9:07 AM
> To: Wentland, Harry 
> Cc: amd-gfx list ; Maling list - DRI
> developers ; Deucher, Alexander
> ; Broadworth, Mark
> ; Liu, Zhan 
> Subject: Re: [PATCH 13/15] drm/amdgpu/display: split dp connector
> registration (v3)
> 
> On Mon, Feb 24, 2020 at 4:09 PM Harry Wentland 
> wrote:
> >
> > On 2020-02-07 4:17 p.m., Alex Deucher wrote:
> > > Split into init and register functions to avoid a segfault in some
> > > configs when the load/unload callbacks are removed.
> > >
> >
> > Looks like MST is completely broken with this change with a NULL
> > pointer dereference in drm_dp_aux_register.
> >
> > > v2:
> > > - add back accidently dropped has_aux setting
> > > - set dev in late_register
> > >
> > > v3:
> > > - fix dp cec ordering
> > >
> > > Signed-off-by: Alex Deucher 
> > > ---
> > >  drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c   | 16
> 
> > >  drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 10 ++
> > >  .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c  |  7 ++-
> > >  3 files changed, 24 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > > b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > > index ec1501e3a63a..f355d9a752d2 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c
> > > @@ -1461,6 +1461,20 @@ static enum drm_mode_status
> amdgpu_connector_dp_mode_valid(struct drm_connector
> > >   return MODE_OK;
> > >  }
> > >
> > > +static int
> > > +amdgpu_connector_late_register(struct drm_connector *connector) {
> > > + struct amdgpu_connector *amdgpu_connector =
> to_amdgpu_connector(connector);
> > > + int r = 0;
> > > +
> > > + if (amdgpu_connector->ddc_bus->has_aux) {
> > > + amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector-
> >base.kdev;
> > > + r = drm_dp_aux_register(_connector->ddc_bus->aux);
> > > + }
> > > +
> > > + return r;
> > > +}
> > > +
> > >  static const struct drm_connector_helper_funcs
> amdgpu_connector_dp_helper_funcs = {
> > >   .get_modes = amdgpu_connector_dp_get_modes,
> > >   .mode_valid = amdgpu_connector_dp_mode_valid, @@ -1475,6
> > > +1489,7 @@ static const struct drm_connector_funcs
> amdgpu_connector_dp_funcs = {
> > >   .early_unregister = amdgpu_connector_unregister,
> > >   .destroy = amdgpu_connector_destroy,
> > >   .force = amdgpu_connector_dvi_force,
> > > + .late_register = amdgpu_connector_late_register,
> > >  };
> > >
> > >  static const struct drm_connector_funcs amdgpu_connector_edp_funcs
> > > = { @@ -1485,6 +1500,7 @@ static const struct drm_connector_funcs
> amdgpu_connector_edp_funcs = {
> > >   .early_unregister = amdgpu_connector_unregister,
> > >   .destroy = amdgpu_connector_destroy,
> > >   .force = amdgpu_connector_dvi_force,
> > > + .late_register = amdgpu_connector_late_register,
> > >  };
> > >
> > >  void
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> > > b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> > > index ea702a64f807..9b74cfdba7b8 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
> > > @@ -186,16 +186,10 @@ amdgpu_atombios_dp_aux_transfer(struct
> > > drm_dp_aux *aux, struct drm_dp_aux_msg *m
> > >
> > >  void amdgpu_atombios_dp_aux_init(struct amdgpu_connector
> > > *amdgpu_connector)  {
> > > - int ret;
> > > -
> > >   amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector-
> >hpd.hpd;
> > > - amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector-
> >base.kdev;
> > >   amdgpu_connector->ddc_bus->aux.transfer =
> amdgpu_atombios_dp_aux_transfer;
> > > - ret = drm_dp_aux_register(_connector->ddc_bus->aux);
> > > - if (!ret)
> > > - amdgpu_connector->ddc_bus->has_aux = true;
> > > -
> > > - WARN(ret, "drm_dp_aux_register_i2c_bus() failed with error %d\n",
> ret);
> > > + drm_dp_aux_init(_co

RE: [PATCH] drm/amdgpu: log TA versions on init

2020-02-24 Thread Liu, Zhan



> -Original Message-
> From: amd-gfx  On Behalf Of
> Bhawanpreet Lakha
> Sent: 2020/February/24, Monday 2:45 PM
> To: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> ; Zhang, Hawking
> 
> Cc: Lakha, Bhawanpreet 
> Subject: [PATCH] drm/amdgpu: log TA versions on init
> 
> It is helpful to know what version the TA's are for debugging
> 
> Signed-off-by: Bhawanpreet Lakha 

Reviewed-by: Zhan Liu 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 5 +
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> index a16c8101e250..09d1433677a6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
> @@ -358,6 +358,7 @@ static int psp_asd_load(struct psp_context *psp)
>   if (!ret) {
>   psp->asd_context.asd_initialized = true;
>   psp->asd_context.session_id = cmd->resp.session_id;
> + DRM_INFO("ASD: Initialized (version: 0x%X)", psp-
> >asd_fw_version);
>   }
> 
>   kfree(cmd);
> @@ -518,6 +519,7 @@ static int psp_xgmi_load(struct psp_context *psp)
>   if (!ret) {
>   psp->xgmi_context.initialized = 1;
>   psp->xgmi_context.session_id = cmd->resp.session_id;
> + DRM_INFO("XGMI: Initialized (version: 0x%X)", psp-
> >ta_xgmi_ucode_version);
>   }
> 
>   kfree(cmd);
> @@ -658,6 +660,7 @@ static int psp_ras_load(struct psp_context *psp)
>   if (!ret) {
>   psp->ras.ras_initialized = true;
>   psp->ras.session_id = cmd->resp.session_id;
> + DRM_INFO("RAS: Initialized (version: 0x%X)", psp-
> >ta_ras_ucode_version);
>   }
> 
>   kfree(cmd);
> @@ -832,6 +835,7 @@ static int psp_hdcp_load(struct psp_context *psp)
>   if (!ret) {
>   psp->hdcp_context.hdcp_initialized = true;
>   psp->hdcp_context.session_id = cmd->resp.session_id;
> + DRM_INFO("HDCP: Initialized (version: 0x%X)", psp-
> >ta_hdcp_ucode_version);
>   }
> 
>   kfree(cmd);
> @@ -977,6 +981,7 @@ static int psp_dtm_load(struct psp_context *psp)
>   if (!ret) {
>   psp->dtm_context.dtm_initialized = true;
>   psp->dtm_context.session_id = cmd->resp.session_id;
> + DRM_INFO("DTM: Initialized (version: 0x%X)", psp-
> >ta_dtm_ucode_version);
>   }
> 
>   kfree(cmd);
> --
> 2.17.1
> 
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RE: [PATCH] drm/amd/display: Don't take the address of skip_scdc_overwrite in dc_link_detect_helper

2020-02-14 Thread Liu, Zhan



> -Original Message-
> From: Liu, Zhan
> Sent: 2020/February/14, Friday 11:01 AM
> To: Nathan Chancellor ; Wentland, Harry
> ; Li, Sun peng (Leo) ;
> Deucher, Alexander ; Koenig, Christian
> ; Zhou, David(ChunMing)
> 
> Cc: clang-built-li...@googlegroups.com; dri-de...@lists.freedesktop.org;
> amd-gfx@lists.freedesktop.org; linux-ker...@vger.kernel.org
> Subject: RE: [PATCH] drm/amd/display: Don't take the address of
> skip_scdc_overwrite in dc_link_detect_helper
> 
> 
> 
> > -Original Message-
> > From: dri-devel  On Behalf Of
> > Nathan Chancellor
> > Sent: 2020/February/14, Friday 1:30 AM
> > To: Wentland, Harry ; Li, Sun peng (Leo)
> > ; Deucher, Alexander
> ;
> > Koenig, Christian ; Zhou, David(ChunMing)
> > 
> > Cc: clang-built-li...@googlegroups.com; Nathan Chancellor
> > ; dri-de...@lists.freedesktop.org; amd-
> > g...@lists.freedesktop.org; linux-ker...@vger.kernel.org
> > Subject: [PATCH] drm/amd/display: Don't take the address of
> > skip_scdc_overwrite in dc_link_detect_helper
> >
> > Clang warns:
> >
> > ../drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:980:36:
> > warning: address of 'sink->edid_caps.panel_patch.skip_scdc_overwrite'
> > will always evaluate to 'true' [-Wpointer-bool-conversion]
> > if (>edid_caps.panel_patch.skip_scdc_overwrite)
> > ~~   ^~~
> > 1 warning generated.
> >
> > This is probably not what was intended so remove the address of
> > operator, which matches how skip_scdc_overwrite is handled in the rest of
> the driver.
> >
> > While we're here, drop an extra newline after this if block.
> >
> > Fixes: a760fc1bff03 ("drm/amd/display: add monitor patch to disable
> > SCDC
> > read/write")
> > Link:
> > https://github.com/ClangBuiltLinux/linux/issues/879
> > Signed-off-by: Nathan Chancellor 
> 
> Thank you!
> Reviewed-by: Zhan Liu 

Also applied, thanks!

Zhan

> 
> > ---
> >
> > As an aside, I don't see skip_scdc_overwrite assigned a value
> > anywhere, is this working as intended?
> >
> >  drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +--
> >  1 file changed, 1 insertion(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> > b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> > index 24d99849be5e..a3bfa05c545e 100644
> > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> > @@ -977,10 +977,9 @@ static bool dc_link_detect_helper(struct dc_link
> > *link,
> > if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME)
> > || (edid_status == EDID_OK)))
> > same_edid = is_same_edid(_sink->dc_edid,
> >dc_edid);
> >
> > -   if (>edid_caps.panel_patch.skip_scdc_overwrite)
> > +   if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
> > link->ctx->dc->debug.hdmi20_disable = true;
> >
> > -
> > if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT
> &&
> > sink_caps.transaction_type ==
> > DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
> > /*
> > --
> > 2.25.0
> >
> > ___
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> > dri-de...@lists.freedesktop.org
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RE: [PATCH] drm/amd/display: Don't take the address of skip_scdc_overwrite in dc_link_detect_helper

2020-02-14 Thread Liu, Zhan




> -Original Message-
> From: dri-devel  On Behalf Of
> Nathan Chancellor
> Sent: 2020/February/14, Friday 1:30 AM
> To: Wentland, Harry ; Li, Sun peng (Leo)
> ; Deucher, Alexander
> ; Koenig, Christian
> ; Zhou, David(ChunMing)
> 
> Cc: clang-built-li...@googlegroups.com; Nathan Chancellor
> ; dri-de...@lists.freedesktop.org; amd-
> g...@lists.freedesktop.org; linux-ker...@vger.kernel.org
> Subject: [PATCH] drm/amd/display: Don't take the address of
> skip_scdc_overwrite in dc_link_detect_helper
> 
> Clang warns:
> 
> ../drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:980:36:
> warning: address of 'sink->edid_caps.panel_patch.skip_scdc_overwrite'
> will always evaluate to 'true' [-Wpointer-bool-conversion]
> if (>edid_caps.panel_patch.skip_scdc_overwrite)
> ~~   ^~~
> 1 warning generated.
> 
> This is probably not what was intended so remove the address of operator,
> which matches how skip_scdc_overwrite is handled in the rest of the driver.
> 
> While we're here, drop an extra newline after this if block.
> 
> Fixes: a760fc1bff03 ("drm/amd/display: add monitor patch to disable SCDC
> read/write")
> Link:
> https://github.com/ClangBuiltLinux/linux/issues/879
> Signed-off-by: Nathan Chancellor 

Thank you!
Reviewed-by: Zhan Liu 

> ---
> 
> As an aside, I don't see skip_scdc_overwrite assigned a value anywhere, is
> this working as intended?
> 
>  drivers/gpu/drm/amd/display/dc/core/dc_link.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index 24d99849be5e..a3bfa05c545e 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -977,10 +977,9 @@ static bool dc_link_detect_helper(struct dc_link
> *link,
>   if ((prev_sink != NULL) && ((edid_status == EDID_THE_SAME)
> || (edid_status == EDID_OK)))
>   same_edid = is_same_edid(_sink->dc_edid,
> >dc_edid);
> 
> - if (>edid_caps.panel_patch.skip_scdc_overwrite)
> + if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
>   link->ctx->dc->debug.hdmi20_disable = true;
> 
> -
>   if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT
> &&
>   sink_caps.transaction_type ==
> DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
>   /*
> --
> 2.25.0
> 
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RE: [PATCH 3/3] drm/amdgpu/display move get_num_odm_splits() into dc_resource.c

2020-02-12 Thread Liu, Zhan



> -Original Message-
> From: Alex Deucher 
> Sent: 2020/February/12, Wednesday 11:05 AM
> To: Liu, Zhan 
> Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> 
> Subject: Re: [PATCH 3/3] drm/amdgpu/display move get_num_odm_splits()
> into dc_resource.c
> 
> On Wed, Feb 12, 2020 at 10:58 AM Liu, Zhan  wrote:
> >
> > Please find my reply inline.
> >
> > Thanks,
> > Zhan
> >
> > > -Original Message-
> > > From: amd-gfx  On Behalf Of
> > > Alex Deucher
> > > Sent: 2020/February/11, Tuesday 11:33 PM
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Deucher, Alexander 
> > > Subject: [PATCH 3/3] drm/amdgpu/display move get_num_odm_splits()
> > > into dc_resource.c
> > >
> > > It's used by more than just DCN2.0.  Fixes missing symbol when
> > > amdgpu is built without DCN support.
> > >
> > > Signed-off-by: Alex Deucher 
> > > ---
> > >  .../gpu/drm/amd/display/dc/core/dc_resource.c| 16
> 
> > >  .../drm/amd/display/dc/dcn20/dcn20_resource.c| 16 
> > >  .../drm/amd/display/dc/dcn20/dcn20_resource.h|  1 -
> > >  drivers/gpu/drm/amd/display/dc/inc/resource.h|  3 +++
> > >  4 files changed, 19 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> > > b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> > > index c02e5994d32b..572ce3842535 100644
> > > --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> > > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> > > @@ -532,6 +532,22 @@ static inline void get_vp_scan_direction(
> > >   *flip_horz_scan_dir = !*flip_horz_scan_dir;  }
> > >
> > > +int get_num_odm_splits(struct pipe_ctx *pipe) {
> > > + int odm_split_count = 0;
> > > + struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
> > > + while (next_pipe) {
> > > + odm_split_count++;
> > > + next_pipe = next_pipe->next_odm_pipe;
> > > + }
> > > + pipe = pipe->prev_odm_pipe;
> > > + while (pipe) {
> > > + odm_split_count++;
> > > + pipe = pipe->prev_odm_pipe;
> > > + }
> > > + return odm_split_count;
> > > +}
> > > +
> > >  static void calculate_split_count_and_index(struct pipe_ctx
> > > *pipe_ctx, int *split_count, int *split_idx)  {
> > >   *split_count = get_num_odm_splits(pipe_ctx); diff --git
> > > a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > > b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > > index 39026df56fa6..1061faccec9c 100644
> > > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> > > @@ -1861,22 +1861,6 @@ void
> > > dcn20_populate_dml_writeback_from_context(
> > >
> > >  }
> > >
> > > -int get_num_odm_splits(struct pipe_ctx *pipe) -{
> > > - int odm_split_count = 0;
> > > - struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
> > > - while (next_pipe) {
> > > - odm_split_count++;
> > > - next_pipe = next_pipe->next_odm_pipe;
> > > - }
> > > - pipe = pipe->prev_odm_pipe;
> > > - while (pipe) {
> > > - odm_split_count++;
> > > - pipe = pipe->prev_odm_pipe;
> > > - }
> > > - return odm_split_count;
> > > -}
> > > -
> > >  int dcn20_populate_dml_pipes_from_context(
> > >   struct dc *dc, struct dc_state *context,
> > > display_e2e_pipe_params_st *pipes)  { diff --git
> > > a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
> > > b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
> > > index 5180088ab6bc..f5893840b79b 100644
> > > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
> > > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
> > > @@ -49,7 +49,6 @@ unsigned int dcn20_calc_max_scaled_time(
> > >   unsigned int time_per_pixel,
> > >   enum mmhubbub_wbif_mode mode,
> > >   unsigned int urgent_watermark); -int
> > > get_num_odm_splits(struct pipe_ctx *pipe);  int
> >
> > Seems like the "int" at the end of this line actually belongs to the next 
> >

RE: [PATCH 3/3] drm/amdgpu/display move get_num_odm_splits() into dc_resource.c

2020-02-12 Thread Liu, Zhan

Please find my reply inline.

Thanks,
Zhan

> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: 2020/February/11, Tuesday 11:33 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: [PATCH 3/3] drm/amdgpu/display move get_num_odm_splits() into
> dc_resource.c
> 
> It's used by more than just DCN2.0.  Fixes missing symbol when amdgpu is
> built without DCN support.
> 
> Signed-off-by: Alex Deucher 
> ---
>  .../gpu/drm/amd/display/dc/core/dc_resource.c| 16 
>  .../drm/amd/display/dc/dcn20/dcn20_resource.c| 16 
>  .../drm/amd/display/dc/dcn20/dcn20_resource.h|  1 -
>  drivers/gpu/drm/amd/display/dc/inc/resource.h|  3 +++
>  4 files changed, 19 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> index c02e5994d32b..572ce3842535 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> @@ -532,6 +532,22 @@ static inline void get_vp_scan_direction(
>   *flip_horz_scan_dir = !*flip_horz_scan_dir;  }
> 
> +int get_num_odm_splits(struct pipe_ctx *pipe) {
> + int odm_split_count = 0;
> + struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
> + while (next_pipe) {
> + odm_split_count++;
> + next_pipe = next_pipe->next_odm_pipe;
> + }
> + pipe = pipe->prev_odm_pipe;
> + while (pipe) {
> + odm_split_count++;
> + pipe = pipe->prev_odm_pipe;
> + }
> + return odm_split_count;
> +}
> +
>  static void calculate_split_count_and_index(struct pipe_ctx *pipe_ctx, int
> *split_count, int *split_idx)  {
>   *split_count = get_num_odm_splits(pipe_ctx); diff --git
> a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> index 39026df56fa6..1061faccec9c 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> @@ -1861,22 +1861,6 @@ void
> dcn20_populate_dml_writeback_from_context(
> 
>  }
> 
> -int get_num_odm_splits(struct pipe_ctx *pipe) -{
> - int odm_split_count = 0;
> - struct pipe_ctx *next_pipe = pipe->next_odm_pipe;
> - while (next_pipe) {
> - odm_split_count++;
> - next_pipe = next_pipe->next_odm_pipe;
> - }
> - pipe = pipe->prev_odm_pipe;
> - while (pipe) {
> - odm_split_count++;
> - pipe = pipe->prev_odm_pipe;
> - }
> - return odm_split_count;
> -}
> -
>  int dcn20_populate_dml_pipes_from_context(
>   struct dc *dc, struct dc_state *context,
> display_e2e_pipe_params_st *pipes)  { diff --git
> a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
> index 5180088ab6bc..f5893840b79b 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.h
> @@ -49,7 +49,6 @@ unsigned int dcn20_calc_max_scaled_time(
>   unsigned int time_per_pixel,
>   enum mmhubbub_wbif_mode mode,
>   unsigned int urgent_watermark);
> -int get_num_odm_splits(struct pipe_ctx *pipe);  int

Seems like the "int" at the end of this line actually belongs to the next line.
I am wondering is it a typo or a format-patch glitch?

> dcn20_populate_dml_pipes_from_context(
>   struct dc *dc, struct dc_state *context,
> display_e2e_pipe_params_st *pipes);  struct pipe_ctx
> *dcn20_acquire_idle_pipe_for_layer(
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h
> b/drivers/gpu/drm/amd/display/dc/inc/resource.h
> index 5ae8ada154ef..ca4c36c0c9bc 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h
> @@ -179,4 +179,7 @@ unsigned int resource_pixel_format_to_bpp(enum
> surface_pixel_format format);
> 
>  void get_audio_check(struct audio_info *aud_modes,
>   struct audio_check *aud_chk);
> +
> +int get_num_odm_splits(struct pipe_ctx *pipe);
> +
>  #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */
> --
> 2.24.1
> 
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RE: [PATCH 2/3] drm/amdgpu/display: extend DCN guards

2020-02-12 Thread Liu, Zhan




> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: 2020/February/11, Tuesday 11:33 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: [PATCH 2/3] drm/amdgpu/display: extend DCN guards
> 
> to cover dcn2.x related headers.
> 
> Signed-off-by: Alex Deucher 

This patch is:
Reviewed-by: Zhan Liu 

> ---
>  drivers/gpu/drm/amd/display/dc/core/dc_resource.c  | 4 ++--
>  drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c   | 2 +-
>  drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 2 +-
>  3 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> index a65a1e7820d6..c02e5994d32b 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
> @@ -46,12 +46,12 @@
>  #include "dce100/dce100_resource.h"
>  #include "dce110/dce110_resource.h"
>  #include "dce112/dce112_resource.h"
> +#include "dce120/dce120_resource.h"
>  #if defined(CONFIG_DRM_AMD_DC_DCN)
>  #include "dcn10/dcn10_resource.h"
> -#endif
>  #include "dcn20/dcn20_resource.h"
>  #include "dcn21/dcn21_resource.h"
> -#include "dce120/dce120_resource.h"
> +#endif
> 
>  #define DC_LOGGER_INIT(logger)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
> b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
> index d2d36d48caaa..f252af1947c3 100644
> --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
> +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c
> @@ -47,9 +47,9 @@
>  #include "dce120/hw_factory_dce120.h"
>  #if defined(CONFIG_DRM_AMD_DC_DCN)
>  #include "dcn10/hw_factory_dcn10.h"
> -#endif
>  #include "dcn20/hw_factory_dcn20.h"
>  #include "dcn21/hw_factory_dcn21.h"
> +#endif
> 
>  #include "diagnostics/hw_factory_diag.h"
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
> b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
> index 5d396657a1ee..04e2c0f74cb0 100644
> --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
> +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c
> @@ -45,9 +45,9 @@
>  #include "dce120/hw_translate_dce120.h"
>  #if defined(CONFIG_DRM_AMD_DC_DCN)
>  #include "dcn10/hw_translate_dcn10.h"
> -#endif
>  #include "dcn20/hw_translate_dcn20.h"
>  #include "dcn21/hw_translate_dcn21.h"
> +#endif
> 
>  #include "diagnostics/hw_translate_diag.h"
> 
> --
> 2.24.1
> 
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RE: [PATCH 1/3] drm/amdgpu/display: extend DCN guard in dal_bios_parser_init_cmd_tbl_helper2

2020-02-12 Thread Liu, Zhan



> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: 2020/February/11, Tuesday 11:33 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: [PATCH 1/3] drm/amdgpu/display: extend DCN guard in
> dal_bios_parser_init_cmd_tbl_helper2
> 
> To cover DCN 2.x.
> 
> Signed-off-by: Alex Deucher 

This patch is:
Reviewed-by: Zhan Liu 

> ---
>  .../drm/amd/display/dc/bios/command_table_helper2.c | 13 +++--
>  1 file changed, 3 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> index 7388c987c595..204d7942a6e5 100644
> --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c
> @@ -53,25 +53,18 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
> 
>   case DCE_VERSION_11_2:
>   case DCE_VERSION_11_22:
> + case DCE_VERSION_12_0:
> + case DCE_VERSION_12_1:
>   *h = dal_cmd_tbl_helper_dce112_get_table2();
>   return true;
>  #if defined(CONFIG_DRM_AMD_DC_DCN)
>   case DCN_VERSION_1_0:
>   case DCN_VERSION_1_01:
> - *h = dal_cmd_tbl_helper_dce112_get_table2();
> - return true;
> -#endif
> -
>   case DCN_VERSION_2_0:
> - *h = dal_cmd_tbl_helper_dce112_get_table2();
> - return true;
>   case DCN_VERSION_2_1:
>   *h = dal_cmd_tbl_helper_dce112_get_table2();
>   return true;
> - case DCE_VERSION_12_0:
> - case DCE_VERSION_12_1:
> - *h = dal_cmd_tbl_helper_dce112_get_table2();
> - return true;
> +#endif
> 
>   default:
>   /* Unsupported DCE */
> --
> 2.24.1
> 
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RE: [PATCH] drm/amd/display: Fix a typo when computing dsc configuration

2020-01-31 Thread Liu, Zhan




> -Original Message-
> From: amd-gfx  On Behalf Of
> mikita.lip...@amd.com
> Sent: 2020/January/31, Friday 10:00 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander ; Lipski, Mikita
> ; Wentland, Harry 
> Subject: [PATCH] drm/amd/display: Fix a typo when computing dsc
> configuration
> 
> From: Mikita Lipski 

Reviewed-by: Zhan Liu 

> 
> [why]
> Remove a backslash symbol accidentally left in increase bpp function when
> computing mst dsc configuration.
> 
> Signed-off-by: Mikita Lipski 
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git
> a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> index 96b391e4b3e7..5672f7765919 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
> @@ -632,7 +632,7 @@ static void increase_dsc_bpp(struct
> drm_atomic_state *state,
>   if (drm_dp_atomic_find_vcpi_slots(state,
> 
> params[next_index].port->mgr,
> 
> params[next_index].port,
> -
> vars[next_index].pbn,\
> +
> vars[next_index].pbn,
> 
> dm_mst_get_pbn_divider(dc_link)) < 0)
>   return;
>   if (!drm_dp_mst_atomic_check(state)) {
> --
> 2.17.1
> 
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> amd-gfx@lists.freedesktop.org

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RE: Suspecting corrupted VBIOS after update of AMDGPU on AMD7870

2020-01-30 Thread Liu, Zhan

Okay I see. From your attached dmesg.log, issue comes from here:

[   26.265638] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0 timeout, 
signaled seq=1, emitted seq=2
[   26.265764] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process information: 
process  pid 0 thread  pid 0
[   26.265771] [drm] GPU recovery disabled.

There was a very similar issue that’s recently fixed and merged in 5.5 kernel. 
I’ve noticed that you are using 5.4 kernel, so you can give 5.5 a spin to see 
what happens.

As for these “Green Dots” at BIOS initialization stage, the main amdgpu driver 
was not loaded yet, so it shouldn’t related to amdgpu.

BTW, your new findings 
(https://gist.github.com/Kreyren/3e55e9a754e58956e1690e38b1888de7) gives me 
404. Please fix the link. Good luck!

Warm regards,
Zhan



From: Jacob Hrbek 
Sent: 2020/January/30, Thursday 5:55 PM
To: Liu, Zhan ; amd-gfx@lists.freedesktop.org
Subject: Re: Suspecting corrupted VBIOS after update of AMDGPU on AMD7870

Hello Zhan,
Here is it:
https://gist.githubusercontent.com/Kreyren/e35587d8710e63e511e69d8653fd996b/raw/628df1c76ff99adab1d2161e6a20f631de101d5c/gistfile1.txt<https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgist.githubusercontent.com%2FKreyren%2Fe35587d8710e63e511e69d8653fd996b%2Fraw%2F628df1c76ff99adab1d2161e6a20f631de101d5c%2Fgistfile1.txt=02%7C01%7CZhan.Liu%40amd.com%7C2fe63c116bbd4cacddc008d7a5d79126%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637160218197534666=CGBp3z6G8KJXT9cyfaJxlDlkpaDF36qTsj228KYo1bk%3D=0>

Note that I'm updating previous gists with new findings 
(https://gist.github.com/Kreyren/3e55e9a754e58956e1690e38b1888de7).<https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgist.github.com%2FKreyren%2F3e55e9a754e58956e1690e38b1888de7).=02%7C01%7CZhan.Liu%40amd.com%7C2fe63c116bbd4cacddc008d7a5d79126%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637160218197544657=C8pB8txk8a9du6ulzG%2FA15VBF8vTXfjZ%2BG9vU9%2FFkCw%3D=0>

If relevant i'm also getting these 'Green dots' at the initialization of bios 
(https://linx.li/s/8j3poh2z.png<https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flinx.li%2Fs%2F8j3poh2z.png=02%7C01%7CZhan.Liu%40amd.com%7C2fe63c116bbd4cacddc008d7a5d79126%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637160218197544657=ZuobmBcSLCHK97ta%2FLG5txQCf0vN%2BS47UGRNAlPZu2s%3D=0>).
These dots are not present anywhere else and were not present before said 
update.

Thanks,
- Jacob Hrbek

On Thu, Jan 30, 2020 at 8:10 PM Liu, Zhan 
mailto:zhan@amd.com>> wrote:
Hi Jacob,

Thant you for your bug reporting.

I saw you attached xorg.log, which is great. Could you also grab dmesg.log via 
SSH?

Thanks,
Zhan


From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 On Behalf Of Jacob Hrbek
Sent: 2020/January/30, Thursday 12:18 PM
To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>
Subject: Suspecting corrupted VBIOS after update of AMDGPU on AMD7870

Hello,
I believe that system update that included amdgpu on debian testing (but i am 
on LFS) corrupted my VBIOS on AMD7870 (+- 4 hours after the update the GPU 
using AMDGPU/Radeon drivers resulted in no output).
i'm sending this email to inform about possible bug with my findings on 
https://gist.github.com/Kreyren/3e55e9a754e58956e1690e38b1888de7<https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgist.github.com%2FKreyren%2F3e55e9a754e58956e1690e38b1888de7=02%7C01%7CZhan.Liu%40amd.com%7C2fe63c116bbd4cacddc008d7a5d79126%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637160218197554652=goaR7sDaBxHkmG%2Biln%2FsxEZfSqQ7KTqwbxc9FRxGGMs%3D=0>
 and i would appreciate any help in excluding VBIOS corruption from the 
diagnostics.
Thanks,
- Jacob Hrbek
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RE: Suspecting corrupted VBIOS after update of AMDGPU on AMD7870

2020-01-30 Thread Liu, Zhan

Hi Jacob,

Thant you for your bug reporting.

I saw you attached xorg.log, which is great. Could you also grab dmesg.log via 
SSH?

Thanks,
Zhan


From: amd-gfx  On Behalf Of Jacob Hrbek
Sent: 2020/January/30, Thursday 12:18 PM
To: amd-gfx@lists.freedesktop.org
Subject: Suspecting corrupted VBIOS after update of AMDGPU on AMD7870

Hello,
I believe that system update that included amdgpu on debian testing (but i am 
on LFS) corrupted my VBIOS on AMD7870 (+- 4 hours after the update the GPU 
using AMDGPU/Radeon drivers resulted in no output).
i'm sending this email to inform about possible bug with my findings on 
https://gist.github.com/Kreyren/3e55e9a754e58956e1690e38b1888de7
 and i would appreciate any help in excluding VBIOS corruption from the 
diagnostics.
Thanks,
- Jacob Hrbek
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RE: [PATCH] drm/amdgpu/df3.6: remove unused variable

2020-01-13 Thread Liu, Zhan



> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: 2020/January/13, Monday 1:42 PM
> To: amd-gfx list 
> Cc: Deucher, Alexander 
> Subject: Re: [PATCH] drm/amdgpu/df3.6: remove unused variable
> 
> Ping?
> 
> Alex
> 
> On Fri, Jan 10, 2020 at 7:22 PM Alex Deucher 
> wrote:
> >
> > Unused so drop it.
> >
> > Signed-off-by: Alex Deucher 

Reviewed-by: Zhan Liu  

> > ---
> >  drivers/gpu/drm/amd/amdgpu/df_v3_6.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> > b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> > index 3761c8cc1156..f51326598a8c 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/df_v3_6.c
> > @@ -264,7 +264,7 @@ static DEVICE_ATTR(df_cntr_avail, S_IRUGO,
> > df_v3_6_get_df_cntr_avail, NULL);
> >
> >  static void df_v3_6_query_hashes(struct amdgpu_device *adev)  {
> > -   u32 chan_cfg, tmp;
> > +   u32 tmp;
> >
> > adev->df.hash_status.hash_64k = false;
> > adev->df.hash_status.hash_2m = false;
> > --
> > 2.24.1
> >
> ___
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RE: [PATCH 39/43] drm/amd/display: Use udelay to avoid context switch

2020-01-10 Thread Liu, Zhan




> -Original Message-
> From: amd-gfx  On Behalf Of
> Christian König
> Sent: 2020/January/10, Friday 10:02 AM
> To: Siqueira, Rodrigo ; amd-
> g...@lists.freedesktop.org
> Cc: Li, Sun peng (Leo) ; Cheng, Tony
> ; Tsai, Martin ; Lakha,
> Bhawanpreet ; Wentland, Harry
> 
> Subject: Re: [PATCH 39/43] drm/amd/display: Use udelay to avoid context
> switch
> 
> Am 10.01.20 um 15:46 schrieb Rodrigo Siqueira:
> > From: Martin Tsai 
> >
> > [why]
> > The rapid msleep operation causes the white line garbage when DAL
> > check flip pending status in SetVidPnSourceVisibility.
> > To execute this msleep will induce context switch, and longer delay
> > could cause worse garbage situation.
> >
> > [how]
> > To replace msleep with udelay.
> >
> > Signed-off-by: Martin Tsai 
> > Reviewed-by: Tony Cheng 
> > Acked-by: Harry Wentland 
> > Acked-by: Rodrigo Siqueira 
> > ---
> >   drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > index 89920924a154..0dc652e76848 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
> > @@ -1642,9 +1642,9 @@ void dcn20_program_front_end_for_ctx(
> > struct hubp *hubp = pipe->plane_res.hubp;
> > int j = 0;
> >
> > -   for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS
> > +   for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
> > && hubp->funcs-
> >hubp_is_flip_pending(hubp); j++)
> > -   msleep(1);
> > +   udelay(1);
> 
> Why not using mdelay() here?

As far as I know, mdelay() is only defined on Linux side.

This piece of code is shared by both Linux and Windows, so we have to use a 
function that's available on both platforms.

Zhan

> 
> Christian.
> 
> > }
> > }
> >
> 
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RE: [Bug 206155] New: amdgpu several warnings while booting Fiji GPU, GPU not activated

2020-01-10 Thread Liu, Zhan

+ amd-gfx@lists.freedesktop.org

Hi there,

Thank you for your bug report (though from your email address seems like you 
are a robot :p)

Since it's an amdgpu related bug, please also add amd-gfx@lists.freedesktop.org 
for better visibility.

Thanks,
Zhan

> -Original Message-
> From: dri-devel  On Behalf Of
> bugzilla-dae...@bugzilla.kernel.org
> Sent: 2020/January/10, Friday 9:13 AM
> To: dri-de...@lists.freedesktop.org
> Subject: [Bug 206155] New: amdgpu several warnings while booting Fiji GPU,
> GPU not activated
> 
> https://bugzilla.kernel.org/show_bug.cgi?id=206155
> 
> Bug ID: 206155
>Summary: amdgpu several warnings while booting Fiji GPU, GPU
> not activated
>Product: Drivers
>Version: 2.5
> Kernel Version: 5.4.7
>   Hardware: x86-64
> OS: Linux
>   Tree: Mainline
> Status: NEW
>   Severity: blocking
>   Priority: P1
>  Component: Video(DRI - non Intel)
>   Assignee: drivers_video-...@kernel-bugs.osdl.org
>   Reporter: janpieter.sol...@dommel.be
> Regression: No
> 
> Created attachment 286739
>   --> https://bugzilla.kernel.org/attachment.cgi?id=286739=edit
> 
> powerplay-enabled dmesg
> 
> This dmesg is with powerplay disabled (using ppfeaturemask=0), attached pp-
> enabled dmesg
> 
> [6.728122] amdgpu: [powerplay]
> failed to send message 154 ret is 0
> [6.728130] [drm] UVD initialized successfully.
> [9.324771] amdgpu: [powerplay]
> last message was failed ret is 0
> [   11.818433] amdgpu: [powerplay]
> failed to send message 15a ret is 0
> [   12.122300] amdgpu :0a:00.0: [drm:amdgpu_ring_test_helper
> [amdgpu]]
> *ERROR* ring vce0 test failed (-110)
> [   12.122382] [drm:amdgpu_device_init.cold [amdgpu]] *ERROR* hw_init of
> IP
> block  failed -110
> [   12.122383] amdgpu :0a:00.0: amdgpu_device_ip_init failed
> [   12.122385] amdgpu :0a:00.0: Fatal error during GPU init
> --
> 
> [   14.531652] amdgpu: [powerplay]
> last message was failed ret is 0
> [   14.532747] amdgpu: [powerplay] dpm has been disabled
> [   14.534668] [ cut here ]
> [   14.534753] WARNING: CPU: 1 PID: 942 at
> amdgpu_bo_unpin.cold+0x23/0x42
> [amdgpu]
> [   14.534754] Modules linked in: btrfs xor raid6_pq kvm_amd(-) amdgpu(+)
> wmi_bmof gpu_sched ttm kvm uas irqbypass backlight i2c_piix4 k10temp
> aacraid wmi efivarfs
> [   14.534762] CPU: 1 PID: 942 Comm: systemd-udevd Not tainted 5.4.7 #8
> [   14.534763] Hardware name: Gigabyte Technology Co., Ltd. X570 UD/X570
> UD,
> BIOS F10 11/15/2019
> [   14.534847] RIP: 0010:amdgpu_bo_unpin.cold+0x23/0x42 [amdgpu]
> [   14.534849] Code: 84 00 00 00 00 00 90 48 8b bb f0 b0 ff ff 4c 89 e2 48 c7
> c6 b7 ea 66 c0 89 44 24 04 e8 02 30 21 d5 8b 44 24 04 e9 0f 94 e5 ff <0f> 0b
> 48 8b bb f0 b0 ff ff 4c 89 e2 48 c7 c6 9f ea 66 c0 e8 57 30
> [   14.534850] RSP: 0018:9bba8132f9d0 EFLAGS: 00010246
> [   14.534851] RAX: 88de87d37450 RBX: 88de84984f10 RCX:
> 88de85444f80
> [   14.534852] RDX:  RSI:  RDI:
> 88de87d37400
> [   14.534852] RBP: 88de84987298 R08: 0001 R09:
> 88de95c03500
> [   14.534853] R10: 88de87d37000 R11: 88de87d371c0 R12:
> 88de87d37400
> [   14.534853] R13: 88de84987290 R14: 88de87d37400 R15:
> 
> [   14.534855] FS:  7f3e897bc800() GS:88de96c4()
> knlGS:
> [   14.534856] CS:  0010 DS:  ES:  CR0: 80050033
> [   14.534856] CR2: 7f3e8945a440 CR3: 000207f2c000 CR4:
> 003406e0
> [   14.534857] Call Trace:
> [   14.534929]  amdgpu_bo_free_kernel+0x7d/0x150 [amdgpu]
> [   14.535007]  amdgpu_gfx_rlc_fini+0x42/0x60 [amdgpu]
> [   14.535084]  gfx_v8_0_sw_fini+0x9a/0x190 [amdgpu]
> [   14.535167]  amdgpu_device_fini+0x238/0x42f [amdgpu]
> [   14.535234]  amdgpu_driver_unload_kms+0x50/0xb0 [amdgpu]
> [   14.535317]  amdgpu_driver_load_kms.cold+0x39/0x5b [amdgpu]
> [   14.535320]  drm_dev_register+0x139/0x180
> [   14.535322]  ? do_pci_enable_device+0xad/0xd0
> [   14.535389]  amdgpu_pci_probe+0xb4/0x120 [amdgpu]
> [   14.535392]  ? __pm_runtime_resume+0x54/0x70
> [   14.535394]  local_pci_probe+0x46/0x90
> [   14.535396]  pci_device_probe+0xe9/0x190
> [   14.535399]  really_probe+0xf3/0x2c0
> [   14.535400]  driver_probe_device+0x59/0xd0
> [   14.535402]  device_driver_attach+0x68/0x70
> [   14.535403]  __driver_attach+0x51/0xc0
> [   14.535404]  ? device_driver_attach+0x70/0x70
> [   14.535406]  bus_for_each_dev+0x5e/0x90
> [   14.535408]  bus_add_driver+0x198/0x1e0
> [   14.535409]  driver_register+0x67/0xb0
> [   14.535411]  ? 0xc0755000
> [   14.535412]  do_one_initcall+0x3e/0x1df
> [   14.535415]  ? __vunmap+0x1e3/0x230
> [   14.535417]  ?

RE: Problem whit Radeon rx 590 makes games crash on Linux

2020-01-06 Thread Liu, Zhan

Hi there,

Thank you for raising this question. Here are my two cents that came from my 
own experience:

>From what you mentioned in the community thread, you tried multiple kernel 
>versions on vanilla Manjaro. However, it seems like you didn't upgrade any 
>user-mode driver, and I suspect that's why you encountered so many problems 
>when playing games. If that's the case, you can try install the official AMD 
>RX590 Linux driver: 
>https://www.amd.com/en/support/graphics/radeon-500-series/radeon-rx-500-series/radeon-rx-590.
> I would recommend you use the following installation command: 
>./amdgpu-pro-install

Another possibility is, your graphics card is experiencing heat throttling 
under heavy load, and that's also a common reason why graphics cards are 
struggling a lot on heavy duty games. If that's the case, you can try adding 
more fans to your desktop.

Also, are you using PCI-e x8 on your motherboard? If that's the case, please 
switch to PCI-e x16 to solve the bottleneck.

You could also switch to another Linux distribution (e.g. Ubuntu) and give it a 
try, though I will be a bit surprised if the issue was caused by specific Linux 
distribution.

Hope that helps. Should you have more questions, please feel free to contact us 
on the mailing list.

Thanks,
Zhan

> -Original Message-
> From: amd-gfx  On Behalf Of
> Martin Bångens
> Sent: 2020/January/06, Monday 2:34 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: Problem whit Radeon rx 590 makes games crash on Linux
> 
> Hi AMD graphic driver developer for Linux!
> 
> I have problems with playing games using Linux opensource driver
> 
> I have xfx radeon rx 590 fatboy and tested with proprietary driver games run
> fine but too slow for playing
> 
> here is bit more info about my experience
> 
> ask me anything
> 
> 
> https://community.amd.com/thread/246894 
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> amd-gfx@lists.freedesktop.org

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RE: [PATCH] drm/amd/powerplay: Add SMU WMTABLE Validity Check for Renoir

2019-12-16 Thread Liu, Zhan

Ping...

> -Original Message-
> From: Liu, Zhan 
> Sent: 2019/December/13, Friday 11:50 AM
> To: amd-gfx@lists.freedesktop.org; Wu, Hersen ;
> Deucher, Alexander ; Wang, Kevin(Yang)
> ; Quan, Evan ; Yin, Tianci
> (Rico) 
> Cc: Liu, Zhan 
> Subject: [PATCH] drm/amd/powerplay: Add SMU WMTABLE Validity Check
> for Renoir
> 
> [Why]
> SMU watermark table (WMTABLE) validity check is missing on Renoir. This
> validity check is very useful for checking whether WMTABLE is updated
> successfully.
> 
> [How]
> Add SMU watermark validity check.
> 
> Signed-off-by: Zhan Liu 
> ---
>  drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 12 ++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> index 89a54f8e08d3..81520b0fca68 100644
> --- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> +++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
> @@ -777,9 +777,17 @@ static int renoir_set_watermarks_table(
>   }
> 
>   /* pass data to smu controller */
> - ret = smu_write_watermarks_table(smu);
> + if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
> + !(smu->watermarks_bitmap &
> WATERMARKS_LOADED)) {
> + ret = smu_write_watermarks_table(smu);
> + if (ret) {
> + pr_err("Failed to update WMTABLE!");
> + return ret;
> + }
> + smu->watermarks_bitmap |= WATERMARKS_LOADED;
> + }
> 
> - return ret;
> + return 0;
>  }
> 
>  static int renoir_get_power_profile_mode(struct smu_context *smu,
> --
> 2.17.1

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RE: [PATCH] drm/amd/display: fix undefined struct member reference

2019-12-10 Thread Liu, Zhan



> -Original Message-
> From: Arnd Bergmann 
> Sent: 2019/December/10, Tuesday 3:31 PM
> To: Wentland, Harry ; Li, Sun peng (Leo)
> ; Deucher, Alexander
> ; Koenig, Christian
> ; Zhou, David(ChunMing)
> ; David Airlie ; Daniel Vetter
> ; Liu, Zhan 
> Cc: Arnd Bergmann ; Laktyushkin, Dmytro
> ; Lakha, Bhawanpreet
> ; Lei, Jun ; Liu,
> Charlene ; Yang, Eric ;
> Cornij, Nikola ; amd-gfx@lists.freedesktop.org;
> dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org
> Subject: [PATCH] drm/amd/display: fix undefined struct member reference
> 
> An initialization was added for two optional struct members.  One of these is
> always present in the dcn20_resource file, but the other one depends on
> CONFIG_DRM_AMD_DC_DSC_SUPPORT and causes a build failure if that is
> missing:
> 
> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_resource.c:926:1
> 4: error: excess elements in struct initializer [-Werror]
>.num_dsc = 5,
> 
> Add another #ifdef around the assignment.
> 
> Fixes: c3d03c5a196f ("drm/amd/display: Include num_vmid and num_dsc
> within NV14's resource caps")
> Signed-off-by: Arnd Bergmann 

Thank you for catching that  On my side I kept that flag enabled all the time, 
so I didn't realize there was a warning hidden here. 

Reviewed-by: Zhan Liu 

> ---
>  drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> index faab89d1e694..fdf93e6edf43 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> @@ -923,7 +923,9 @@ static const struct resource_caps res_cap_nv14 = {
>   .num_dwb = 1,
>   .num_ddc = 5,
>   .num_vmid = 16,
> +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
>   .num_dsc = 5,
> +#endif
>  };
> 
>  static const struct dc_debug_options debug_defaults_drv = {
> --
> 2.20.0

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RE: [drm:amdgpu_dm_atomic_commit_tail [amdgpu]] ERROR Waiting for fences timed out or interrupted!

2019-12-05 Thread Liu, Zhan

I've seen a few people reported this issue on Freedesktop/Bugzilla. For example:
https://bugs.freedesktop.org/show_bug.cgi?id=24.

They all experienced this issue while playing games. The higher GPU clock is, 
the more frequent issue can be reproduced.

Also, some Reddit users pointed out all these games are Vulkan based. It could 
be a Vulkan specific issue.

Thanks,
Zhan

> -Original Message-
> From: amd-gfx  On Behalf Of
> Christian Pernegger
> Sent: 2019/December/05, Thursday 6:15 PM
> To: amd-gfx@lists.freedesktop.org
> Subject: [drm:amdgpu_dm_atomic_commit_tail [amdgpu]] *ERROR*
> Waiting for fences timed out or interrupted!
> 
> Hello,
> 
> one of my computers has been crashing while gaming rather a lot lately, with
> kernel messages pointing to amdgpu. First line see subject, rest in the
> attached log.
> SSH still works, attempts to shutdown/reboot don't quite finish.
> 
> Radeon VII in an Asus Pro WS X570-Ace. Ubuntu 18.04.3 HWE, mesa-aco.
> This one was with kernel 5.3.0-24-generic [hwe-edge], mesa
> 19.3.0+aco+git1575452833-3409c06e26d-1bionic1, vesa20_* from linux-
> firmware-20191022, running Ori and the Blind Forest: Definitive Edition via
> Proton/WINED3D11 under Steam Remote Play. I've had similar crashes
> sporadically even with 5.0 [plain hwe] and linux-firmware completely stock,
> and with native games (e.g. Crusader Kings II) running locally.
> It used to be maybe once every other week, though, that was tolerable, now
> Ori usually triggers it in under an hour. Turning off ACO via
> RADV_PERFTEST=llvm makes it worse (not bad enough to make it trigger
> quickly and reliably. though), going back to kernel 5.0 helps (as in an hour 
> or
> two might go by without a crash, but the performance impact is severe).
> 
> All very vague. Which is why this isn't pretending to be a bug report, just a
> "has anyone seen this?" kind of shout-out. If it's worthy of following up, I'd
> be happy to provide further info, just tell me what.
> 
> Cheers,
> C.
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RE: amdgpu: Enable full DCN support on POWER

2019-12-05 Thread Liu, Zhan



> -Original Message-
> From: amd-gfx  On Behalf Of
> Timothy Pearson
> Sent: 2019/December/05, Thursday 4:58 PM
> To: amd-gfx 
> Subject: [PATCH] [RFC v2] amdgpu: Enable full DCN support on POWER
> 
> DCN requires floating point support to operate.  Add the appropriate
> x86/ppc64 guards and FPU / AltiVec / VSX context switches to DCN.
> 
> Signed-off-by: Timothy Pearson 
> ---
>  drivers/gpu/drm/amd/display/Kconfig   |   8 +-
>  drivers/gpu/drm/amd/display/dc/Makefile   |   1 +
>  drivers/gpu/drm/amd/display/dc/calcs/Makefile |   8 +
>  .../gpu/drm/amd/display/dc/calcs/dcn_calcs.c  | 157 ++
>  drivers/gpu/drm/amd/display/dc/dcn20/Makefile |   8 +
>  .../drm/amd/display/dc/dcn20/dcn20_resource.c |  27 +++
>  drivers/gpu/drm/amd/display/dc/dcn21/Makefile |   8 +
>  .../drm/amd/display/dc/dcn21/dcn21_resource.c |  27 +++
>  drivers/gpu/drm/amd/display/dc/dml/Makefile   |   9 +
>  drivers/gpu/drm/amd/display/dc/dsc/Makefile   |   8 +
>  drivers/gpu/drm/amd/display/dc/os_types.h |   6 +
>  11 files changed, 263 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/Kconfig
> b/drivers/gpu/drm/amd/display/Kconfig
> index 313183b80032..c73a63f3e245 100644
> --- a/drivers/gpu/drm/amd/display/Kconfig
> +++ b/drivers/gpu/drm/amd/display/Kconfig
> @@ -6,7 +6,7 @@ config DRM_AMD_DC
>   bool "AMD DC - Enable new display engine"
>   default y
>   select SND_HDA_COMPONENT if SND_HDA_CORE
> - select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL
> && KCOV_ENABLE_COMPARISONS)
> + select DRM_AMD_DC_DCN1_0 if (X86 || PPC64)
> && !(KCOV_INSTRUMENT_ALL &&
> +KCOV_ENABLE_COMPARISONS)
>   help
> Choose this option if you want to use the new display engine
> support for AMDGPU. This adds required support for Vega and @@
> -20,7 +20,7 @@ config DRM_AMD_DC_DCN1_0  config
> DRM_AMD_DC_DCN2_0
>   bool "DCN 2.0 family"
>   default y
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
>   depends on DRM_AMD_DC_DCN1_0
>   help
> Choose this option if you want to have @@ -28,7 +28,7 @@ config
> DRM_AMD_DC_DCN2_0
> 
>  config DRM_AMD_DC_DCN2_1
>   bool "DCN 2.1 family"
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
>   depends on DRM_AMD_DC_DCN2_0
>   help
> Choose this option if you want to have @@ -37,7 +37,7 @@ config
> DRM_AMD_DC_DCN2_1  config DRM_AMD_DC_DSC_SUPPORT
>   bool "DSC support"
>   default y
> - depends on DRM_AMD_DC && X86
> + depends on DRM_AMD_DC && (X86 || PPC64)
>   depends on DRM_AMD_DC_DCN1_0
>   depends on DRM_AMD_DC_DCN2_0
>   help
> diff --git a/drivers/gpu/drm/amd/display/dc/Makefile
> b/drivers/gpu/drm/amd/display/dc/Makefile
> index a160512a2f04..3e026a969386 100644
> --- a/drivers/gpu/drm/amd/display/dc/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/Makefile
> @@ -1,5 +1,6 @@
>  #
>  # Copyright 2017 Advanced Micro Devices, Inc.
> +# Copyright 2019 Raptor Engineering, LLC

NAK.

IANAL, but I don't think you can add your company's name by modifying part of 
the code. The copyright notice shows the authors of the original work.

When modifying the code, you are required to agree with that copyright notice. 
That's the purpose of that copyright notice piece.

>  #
>  # Permission is hereby granted, free of charge, to any person obtaining a  #
> copy of this software and associated documentation files (the "Software"),
> diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> index 26c6d735cdc7..20c88aff930a 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile
> @@ -24,7 +24,13 @@
>  # It calculates Bandwidth and Watermarks values for HW programming  #
> 
> +ifdef CONFIG_X86_64
>  calcs_ccflags := -mhard-float -msse
> +endif
> +
> +ifdef CONFIG_PPC64
> +calcs_ccflags := -mhard-float -maltivec endif
> 
>  ifdef CONFIG_CC_IS_GCC
>  ifeq ($(call cc-ifversion, -lt, 0701, y), y) @@ -32,6 +38,7 @@ IS_OLD_GCC =
> 1  endif  endif
> 
> +ifdef CONFIG_X86_64
>  ifdef IS_OLD_GCC
>  # Stack alignment mismatch, proceed with caution.
>  # GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-
> boundary=3 @@ -40,6 +47,7 @@ calcs_ccflags += -mpreferred-stack-
> boundary=4  else  calcs_ccflags += -msse2  endif
> +endif
> 
>  CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calcs.o := $(calcs_ccflags)
> CFLAGS_$(AMDDALPATH)/dc/calcs/dcn_calc_auto.o := $(calcs_ccflags) diff -
> -git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> index 9b2cb57bf2ba..236e852ea60b 100644
> --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
> @@ -1,5 +1,6 @@
>  /*
>   * Copyright 2017 Advanced Micro Devices, Inc.
> + * Copyright 2019 Raptor Engineering, LLC
>   *
>   *

RE: [PATCH] drm/amdgpu/display: add fallthrough comment

2019-12-05 Thread Liu, Zhan



> -Original Message-
> From: Alex Deucher 
> Sent: 2019/December/05, Thursday 5:13 PM
> To: Liu, Zhan 
> Cc: amd-gfx@lists.freedesktop.org; Deucher, Alexander
> 
> Subject: Re: [PATCH] drm/amdgpu/display: add fallthrough comment
> 
> On Thu, Dec 5, 2019 at 5:10 PM Liu, Zhan  wrote:
> >
> >
> >
> > > -Original Message-
> > > From: amd-gfx  On Behalf Of
> > > Alex Deucher
> > > Sent: 2019/December/05, Thursday 4:39 PM
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Deucher, Alexander 
> > > Subject: [PATCH] drm/amdgpu/display: add fallthrough comment
> > >
> > > To avoid a compiler warning.
> > >
> > > Signed-off-by: Alex Deucher 
> > > ---
> > >  drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 1 +
> > >  1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > > b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > > index 191b68b8163a..f1a5d2c6aa37 100644
> > > --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > > +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> > > @@ -645,6 +645,7 @@ bool dce_aux_transfer_with_retries(struct
> > > ddc_service *ddc,
> > >   case AUX_TRANSACTION_REPLY_AUX_DEFER:
> > >   case
> > > AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
> > >   retry_on_defer = true;
> > > + /* fall through */
> >
> > I am a bit confusing here. Why a comment can avoid a compiler warning?
> 
> The kernel enables fall through warnings, so unless there is a comment
> mentioning that are are expecting to fall through here, we get a warning.
> The idea is to find missing breaks in switch code.
> 
> Alex

Got you. Thank you for your explanation.

Reviewed-by: Zhan Liu 

> 
> >
> > >   case
> > > AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
> > >   if (++aux_defer_retries >=
> > > AUX_MAX_DEFER_RETRIES) {
> > >   goto fail;
> > > --
> > > 2.23.0
> > >
> > > ___
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> > > amd-gfx@lists.freedesktop.org
> > >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.
> > > freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> > >
> gfxdata=02%7C01%7Czhan.liu%40amd.com%7C77d85a0275aa4c0a78
> > >
> 2f08d779cb9716%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C6
> > >
> 37111788208702340sdata=3m%2FuNuNIgq82z%2BAeXJ9y7wn81kV%
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RE: [PATCH] drm/amdgpu/display: add fallthrough comment

2019-12-05 Thread Liu, Zhan



> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: 2019/December/05, Thursday 4:39 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: [PATCH] drm/amdgpu/display: add fallthrough comment
> 
> To avoid a compiler warning.
> 
> Signed-off-by: Alex Deucher 
> ---
>  drivers/gpu/drm/amd/display/dc/dce/dce_aux.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> index 191b68b8163a..f1a5d2c6aa37 100644
> --- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
> @@ -645,6 +645,7 @@ bool dce_aux_transfer_with_retries(struct
> ddc_service *ddc,
>   case AUX_TRANSACTION_REPLY_AUX_DEFER:
>   case
> AUX_TRANSACTION_REPLY_I2C_OVER_AUX_DEFER:
>   retry_on_defer = true;
> + /* fall through */

I am a bit confusing here. Why a comment can avoid a compiler warning?

>   case
> AUX_TRANSACTION_REPLY_I2C_OVER_AUX_NACK:
>   if (++aux_defer_retries >=
> AUX_MAX_DEFER_RETRIES) {
>   goto fail;
> --
> 2.23.0
> 
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RE: [PATCH] drm: Add FEC registers for LT-tunable repeaters

2019-12-05 Thread Liu, Zhan



> -Original Message-
> From: amd-gfx  On Behalf Of
> Rodrigo Siqueira
> Sent: 2019/December/05, Thursday 8:59 AM
> To: =dri-de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; amd-
> g...@lists.freedesktop.org
> Cc: Li, Sun peng (Leo) ; Berthe, Abdoulaye
> ; Jani Nikula ;
> Cornij, Nikola ; Manasi Navare
> ; Wentland, Harry
> ; Ville Syrjälä 
> Subject: [PATCH] drm: Add FEC registers for LT-tunable repeaters
> 
> FEC is supported since DP 1.4, and it was expanded for LT-tunable in DP 1.4a.
> This commit adds the address registers for
> FEC_ERROR_COUNT_PHY_REPEATER1 and
> FEC_CAPABILITY_PHY_REPEATER1.
> 
> Cc: Abdoulaye Berthe 
> Cc: Harry Wentland 
> Cc: Leo Li 
> Cc: Jani Nikula 
> Cc: Manasi Navare 
> Cc: Ville Syrjälä 
> Signed-off-by: Abdoulaye Berthe 
> Signed-off-by: Rodrigo Siqueira 

Looks good to me.
Reviewed-by: Zhan Liu 

> ---
>  include/drm/drm_dp_helper.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 51ecb5112ef8..b2057009aabc 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1042,6 +1042,8 @@
>  #define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1
> 0xf0039 /* 1.3 */
>  #define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1
> 0xf003b /* 1.3 */
>  #define DP_FEC_STATUS_PHY_REPEATER1  0xf0290 /*
> 1.4 */
> +#define DP_FEC_ERROR_COUNT_PHY_REPEATER10xf0291 /*
> 1.4 */
> +#define DP_FEC_CAPABILITY_PHY_REPEATER1 0xf0294 /* 1.4a
> */
> 
>  /* Repeater modes */
>  #define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55/*
> 1.3 */
> --
> 2.24.0
> 
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RE: [PATCH] drm/amdgpu/sriov: No need the event 3 and 4 now

2019-12-02 Thread Liu, Zhan



> -Original Message-
> From: amd-gfx  On Behalf Of
> Emily Deng
> Sent: 2019/November/30, Saturday 5:42 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deng, Emily 
> Subject: [PATCH] drm/amdgpu/sriov: No need the event 3 and 4 now
> 
> As will call unload kms when initialize fail, and the unload kms will send 
> event
> 3 and 4, so don't need event 3 and 4 in device init.
> 
> Signed-off-by: Emily Deng 

Reviewed-by: Zhan Liu 

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index d1d573d..0393e35 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -3036,8 +3036,6 @@ int amdgpu_device_init(struct amdgpu_device
> *adev,
>   }
>   dev_err(adev->dev, "amdgpu_device_ip_init failed\n");
>   amdgpu_vf_error_put(adev,
> AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
> - if (amdgpu_virt_request_full_gpu(adev, false))
> - amdgpu_virt_release_full_gpu(adev, false);
>   goto failed;
>   }
> 
> --
> 2.7.4
> 
> ___
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> 637107505314883521sdata=ymkWbnpIGc%2BM%2Bf1yxtfrlr3Gf4KDQ
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RE: [PATCH] drm/dp_mst: Correct the bug in drm_dp_update_payload_part1()

2019-12-02 Thread Liu, Zhan



> -Original Message-
> From: amd-gfx  On Behalf Of
> Wayne Lin
> Sent: 2019/December/01, Sunday 10:59 PM
> To: dri-de...@lists.freedesktop.org; amd-gfx@lists.freedesktop.org
> Cc: Zuo, Jerry ; Wentland, Harry
> ; Kazlauskas, Nicholas
> ; Lin, Wayne 
> Subject: [PATCH] drm/dp_mst: Correct the bug in
> drm_dp_update_payload_part1()
> 
> [Why]
> If the payload_state is DP_PAYLOAD_DELETE_LOCAL in series, current code
> doesn't delete the payload at current index and just move the index to next
> one after shuffling payloads.
> 
> [How]
> After shuffling payloads, decide whether to move on index or not according
> to payload_state of current payload.
> 
> Signed-off-by: Wayne Lin 


Reviewed-by: Zhan Liu 


> ---
>  drivers/gpu/drm/drm_dp_mst_topology.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c
> b/drivers/gpu/drm/drm_dp_mst_topology.c
> index 81e92b260d7a..8da5d461ea01 100644
> --- a/drivers/gpu/drm/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/drm_dp_mst_topology.c
> @@ -3176,7 +3176,8 @@ int drm_dp_update_payload_part1(struct
> drm_dp_mst_topology_mgr *mgr)
>   drm_dp_mst_topology_put_port(port);
>   }
> 
> - for (i = 0; i < mgr->max_payloads; i++) {
> + for (i = 0; i < mgr->max_payloads;
> + (mgr->payloads[i].payload_state ==
> DP_PAYLOAD_DELETE_LOCAL) ? i :
> +i++) {
>   if (mgr->payloads[i].payload_state !=
> DP_PAYLOAD_DELETE_LOCAL)
>   continue;
> 
> --
> 2.17.1
> 
> ___
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> 37108559483579263sdata=JNUpYWZRxNe%2B0%2FCe04fjWRvWh%2
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RE: [PATCH] drm/amdgpu: move CS secure flag next the structs where it's used

2019-11-27 Thread Liu, Zhan



> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: 2019/November/27, Wednesday 3:57 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander 
> Subject: [PATCH] drm/amdgpu: move CS secure flag next the structs where it's
> used
> 
> So it's not mixed up with the CTX stuff.
> 
> Signed-off-by: Alex Deucher 

Reviewed-by: Zhan Liu 

> ---
>  include/uapi/drm/amdgpu_drm.h | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/include/uapi/drm/amdgpu_drm.h
> b/include/uapi/drm/amdgpu_drm.h index f75c6957064d..918ac3548cd3
> 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -207,9 +207,6 @@ union drm_amdgpu_bo_list {
>  #define AMDGPU_CTX_OP_QUERY_STATE3
>  #define AMDGPU_CTX_OP_QUERY_STATE2   4
> 
> -/* Flag the command submission as secure */
> -#define AMDGPU_CS_FLAGS_SECURE  (1 << 0)
> -
>  /* GPU reset status */
>  #define AMDGPU_CTX_NO_RESET  0
>  /* this the context caused it */
> @@ -559,6 +556,9 @@ struct drm_amdgpu_cs_chunk {
>   __u64   chunk_data;
>  };
> 
> +/* Flag the command submission as secure */
> +#define AMDGPU_CS_FLAGS_SECURE  (1 << 0)
> +
>  struct drm_amdgpu_cs_in {
>   /** Rendering context id */
>   __u32   ctx_id;
> --
> 2.23.0
> 
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RE: [PATCH] drm: radeon: replace 0 with NULL

2019-11-26 Thread Liu, Zhan



> -Original Message-
> From: amd-gfx  On Behalf Of
> Christian König
> Sent: 2019/November/26, Tuesday 5:10 AM
> To: Jules Irenge ; Deucher, Alexander
> 
> Cc: Zhou, David(ChunMing) ; airl...@linux.ie;
> linux-ker...@vger.kernel.org; amd-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org; dan...@ffwll.ch
> Subject: Re: [PATCH] drm: radeon: replace 0 with NULL
> 
> Am 26.11.19 um 01:35 schrieb Jules Irenge:
> > Replace 0 with NULL to fix sparse tool  warning
> >   warning: Using plain integer as NULL pointer
> >
> > Signed-off-by: Jules Irenge 
> 
> Acked-by: Christian König 

Reviewed-by: Zhan Liu 

> 
> > ---
> >   drivers/gpu/drm/radeon/radeon_audio.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/radeon/radeon_audio.c
> b/drivers/gpu/drm/radeon/radeon_audio.c
> > index b9aea5776d3d..2269cfced788 100644
> > --- a/drivers/gpu/drm/radeon/radeon_audio.c
> > +++ b/drivers/gpu/drm/radeon/radeon_audio.c
> > @@ -288,7 +288,7 @@ static void radeon_audio_interface_init(struct
> radeon_device *rdev)
> > } else {
> > rdev->audio.funcs = _funcs;
> > rdev->audio.hdmi_funcs = _hdmi_funcs;
> > -   rdev->audio.dp_funcs = 0;
> > +   rdev->audio.dp_funcs = NULL;
> > }
> >   }
> >
> 
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RE: [PATCH] drm: radeon: replace 0 with NULL

2019-11-26 Thread Liu, Zhan



> -Original Message-
> From: amd-gfx  On Behalf Of
> Christian König
> Sent: 2019/November/26, Tuesday 5:10 AM
> To: Jules Irenge ; Deucher, Alexander
> 
> Cc: Zhou, David(ChunMing) ; airl...@linux.ie;
> linux-ker...@vger.kernel.org; amd-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org; dan...@ffwll.ch
> Subject: Re: [PATCH] drm: radeon: replace 0 with NULL
> 
> Am 26.11.19 um 01:35 schrieb Jules Irenge:
> > Replace 0 with NULL to fix sparse tool  warning
> >   warning: Using plain integer as NULL pointer
> >
> > Signed-off-by: Jules Irenge 
> 
> Acked-by: Christian König 


Reviewed-by: Zhan Liu 


> 
> > ---
> >   drivers/gpu/drm/radeon/radeon_audio.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/radeon/radeon_audio.c
> b/drivers/gpu/drm/radeon/radeon_audio.c
> > index b9aea5776d3d..2269cfced788 100644
> > --- a/drivers/gpu/drm/radeon/radeon_audio.c
> > +++ b/drivers/gpu/drm/radeon/radeon_audio.c
> > @@ -288,7 +288,7 @@ static void radeon_audio_interface_init(struct
> radeon_device *rdev)
> > } else {
> > rdev->audio.funcs = _funcs;
> > rdev->audio.hdmi_funcs = _hdmi_funcs;
> > -   rdev->audio.dp_funcs = 0;
> > +   rdev->audio.dp_funcs = NULL;
> > }
> >   }
> >
> 
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RE: [PATCH] drm/amdgpu: move pci handling out of pm ops

2019-11-26 Thread Liu, Zhan



> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: 2019/November/26, Tuesday 9:51 AM
> To: amd-gfx list 
> Cc: Deucher, Alexander 
> Subject: Re: [PATCH] drm/amdgpu: move pci handling out of pm ops
> 
> Ping?  I've tested this on all the cards I have access to.
> 
> Alex
> 
> On Thu, Nov 21, 2019 at 11:55 AM Alex Deucher 
> wrote:
> >
> > The documentation says the that PCI core handles this for you unless
> > you choose to implement it.  Just rely on the PCI core to handle the
> > pci specific bits.
> >
> > Signed-off-by: Alex Deucher 


Reviewed-by: Zhan Liu 


> > ---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu.h|  4 +--
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 33 +-
> 
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 16 +--
> >  3 files changed, 24 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 97843462c2fb..2e9d0be05f2f 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -1191,8 +1191,8 @@ int amdgpu_driver_open_kms(struct drm_device
> > *dev, struct drm_file *file_priv);  void
> amdgpu_driver_postclose_kms(struct drm_device *dev,
> >  struct drm_file *file_priv);  int
> > amdgpu_device_ip_suspend(struct amdgpu_device *adev); -int
> > amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool
> > fbcon); -int amdgpu_device_resume(struct drm_device *dev, bool resume,
> > bool fbcon);
> > +int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); int
> > +amdgpu_device_resume(struct drm_device *dev, bool fbcon);
> >  u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned
> > int pipe);  int amdgpu_enable_vblank_kms(struct drm_device *dev,
> > unsigned int pipe);  void amdgpu_disable_vblank_kms(struct drm_device
> > *dev, unsigned int pipe); diff --git
> > a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index b1408c5e4640..d832bd22ba9d 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -1090,6 +1090,7 @@ static int
> amdgpu_device_check_arguments(struct
> > amdgpu_device *adev)  static void amdgpu_switcheroo_set_state(struct
> > pci_dev *pdev, enum vga_switcheroo_state state)  {
> > struct drm_device *dev = pci_get_drvdata(pdev);
> > +   int r;
> >
> > if (amdgpu_device_supports_boco(dev) && state ==
> VGA_SWITCHEROO_OFF)
> > return;
> > @@ -1099,7 +1100,12 @@ static void amdgpu_switcheroo_set_state(struct
> pci_dev *pdev, enum vga_switchero
> > /* don't suspend or resume card normally */
> > dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
> >
> > -   amdgpu_device_resume(dev, true, true);
> > +   pci_set_power_state(dev->pdev, PCI_D0);
> > +   pci_restore_state(dev->pdev);
> > +   r = pci_enable_device(dev->pdev);
> > +   if (r)
> > +   DRM_WARN("pci_enable_device failed (%d)\n", r);
> > +   amdgpu_device_resume(dev, true);
> >
> > dev->switch_power_state = DRM_SWITCH_POWER_ON;
> > drm_kms_helper_poll_enable(dev); @@ -1107,7 +1113,11
> > @@ static void amdgpu_switcheroo_set_state(struct pci_dev *pdev,
> enum vga_switchero
> > pr_info("amdgpu: switched off\n");
> > drm_kms_helper_poll_disable(dev);
> > dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
> > -   amdgpu_device_suspend(dev, true, true);
> > +   amdgpu_device_suspend(dev, true);
> > +   pci_save_state(dev->pdev);
> > +   /* Shut down the device */
> > +   pci_disable_device(dev->pdev);
> > +   pci_set_power_state(dev->pdev, PCI_D3cold);
> > dev->switch_power_state = DRM_SWITCH_POWER_OFF;
> > }
> >  }
> > @@ -3198,7 +3208,7 @@ void amdgpu_device_fini(struct amdgpu_device
> *adev)
> >   * Returns 0 for success or an error on failure.
> >   * Called at driver suspend.
> >   */
> > -int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool
> > fbcon)
> > +int amdgpu_device_suspend(struct drm_device *dev, bool fbcon)
> >  {
> > struct amdgpu_device *adev;
> > struct drm_crtc *crtc;
> > @@ -3281,13 +3291,6 @@ int amdgpu_device_suspend(struct drm_device
> *dev, bool suspend, bool fbcon)
> >  */
> > amdgpu_bo_evict_vram(adev);
> >
> > -   if (suspend) {
> > -   pci_save_state(dev->pdev);
> > -   /* Shut down the device */
> > -   pci_disable_device(dev->pdev);
> > -   pci_set_power_state(dev->pdev, PCI_D3hot);
> > -   }
> > -
> > return 0;
> >  }
> >
> > @@ -3302,7 +3305,7 @@ int amdgpu_device_suspend(struct drm_device
>

RE: [PATCH] drm/amdgpu/gfx10: remove outdated comments

2019-11-26 Thread Liu, Zhan

Reviewed-by: Zhan Liu 

> -Original Message-
> From: amd-gfx  On Behalf Of
> Xiaojie Yuan
> Sent: 2019/November/26, Tuesday 4:44 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Xiao, Jack ; Yuan, Xiaojie
> ; Zhang, Hawking 
> Subject: [PATCH] drm/amdgpu/gfx10: remove outdated comments
> 
> Signed-off-by: Xiaojie Yuan 
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ---
>  1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 2c5dc9b58e23..6bd8d06dbde9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -46,9 +46,6 @@
>   * Navi10 has two graphic rings to share each graphic pipe.
>   * 1. Primary ring
>   * 2. Async ring
> - *
> - * In bring-up phase, it just used primary ring so set gfx ring number as 1 
> at
> - * first.
>   */
>  #define GFX10_NUM_GFX_RINGS  2
>  #define GFX10_MEC_HPD_SIZE   2048
> --
> 2.20.1
> 
> ___
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> amd-gfx@lists.freedesktop.org

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Re: [PATCH] drm/amd/display: Null check aconnector in event_property_validate

2019-11-25 Thread Liu, Zhan

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Zhan Liu 


From: amd-gfx  on behalf of Bhawanpreet 
Lakha 
Sent: Monday, November 25, 2019 10:40:24 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Lakha, Bhawanpreet 
Subject: [PATCH] drm/amd/display: Null check aconnector in 
event_property_validate

[Why]
previously event_property_validate was only called after we enabled the display.
But after "Refactor HDCP to handle multiple displays per link" this function
can be called at any time. In certain cases we don't have a aconnector

[How]
Null check aconnector and exit early. This is ok because we only need to check 
the
ENABLED->DESIRED transition if a connector exists.

Fixes :cc5dae9f6286 drm/amd/display: Refactor HDCP to handle multiple displays 
per link
Signed-off-by: Bhawanpreet Lakha 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index f6864a51891a..ae329335dfcc 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -225,6 +225,9 @@ static void event_property_validate(struct work_struct 
*work)
 struct mod_hdcp_display_query query;
 struct amdgpu_dm_connector *aconnector = hdcp_work->aconnector;

+   if (!aconnector)
+   return;
+
 mutex_lock(_work->mutex);

 query.encryption_status = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
--
2.17.1

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RE: [PATCH] drm/amdkfd: Remove duplicate functions update_mqd_hiq()

2019-11-21 Thread Liu, Zhan

Looks good to me.

Reviewed-by: Zhan Liu 

> -Original Message-
> From: amd-gfx  On Behalf Of
> Yong Zhao
> Sent: 2019/November/21, Thursday 4:25 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhao, Yong 
> Subject: [PATCH] drm/amdkfd: Remove duplicate functions
> update_mqd_hiq()
> 
> The functions are the same as update_mqd().
> 
> Change-Id: Ic8d8f23cdde6b7806ab766ddf3d71fa668cca5fb
> Signed-off-by: Yong Zhao 
> ---
>  drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c | 16 ++--
> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c  | 16 ++--
> drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c  |  4 
>  3 files changed, 4 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
> index 8d21325b5cbb..7832ec6e480b 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v10.c
> @@ -282,18 +282,6 @@ static void init_mqd_hiq(struct mqd_manager *mm,
> void **mqd,
>   1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
>  }
> 
> -static void update_mqd_hiq(struct mqd_manager *mm, void *mqd,
> - struct queue_properties *q)
> -{
> - struct v10_compute_mqd *m;
> -
> - update_mqd(mm, mqd, q);
> -
> - /* TODO: what's the point? update_mqd already does this. */
> - m = get_mqd(mqd);
> - m->cp_hqd_vmid = q->vmid;
> -}
> -
>  static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
>   struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
>   struct queue_properties *q)
> @@ -422,7 +410,7 @@ struct mqd_manager *mqd_manager_init_v10(enum
> KFD_MQD_TYPE type,
>   mqd->init_mqd = init_mqd_hiq;
>   mqd->free_mqd = free_mqd_hiq_sdma;
>   mqd->load_mqd = load_mqd;
> - mqd->update_mqd = update_mqd_hiq;
> + mqd->update_mqd = update_mqd;
>   mqd->destroy_mqd = destroy_mqd;
>   mqd->is_occupied = is_occupied;
>   mqd->mqd_size = sizeof(struct v10_compute_mqd); @@ -
> 436,7 +424,7 @@ struct mqd_manager *mqd_manager_init_v10(enum
> KFD_MQD_TYPE type,
>   mqd->init_mqd = init_mqd_hiq;
>   mqd->free_mqd = free_mqd;
>   mqd->load_mqd = load_mqd;
> - mqd->update_mqd = update_mqd_hiq;
> + mqd->update_mqd = update_mqd;
>   mqd->destroy_mqd = destroy_mqd;
>   mqd->is_occupied = is_occupied;
>   mqd->mqd_size = sizeof(struct v10_compute_mqd); diff --git
> a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> index df77d67ec9aa..aa9010995eaf 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c
> @@ -325,18 +325,6 @@ static void init_mqd_hiq(struct mqd_manager *mm,
> void **mqd,
>   1 << CP_HQD_PQ_CONTROL__KMD_QUEUE__SHIFT;
>  }
> 
> -static void update_mqd_hiq(struct mqd_manager *mm, void *mqd,
> - struct queue_properties *q)
> -{
> - struct v9_mqd *m;
> -
> - update_mqd(mm, mqd, q);
> -
> - /* TODO: what's the point? update_mqd already does this. */
> - m = get_mqd(mqd);
> - m->cp_hqd_vmid = q->vmid;
> -}
> -
>  static void init_mqd_sdma(struct mqd_manager *mm, void **mqd,
>   struct kfd_mem_obj *mqd_mem_obj, uint64_t *gart_addr,
>   struct queue_properties *q)
> @@ -462,7 +450,7 @@ struct mqd_manager *mqd_manager_init_v9(enum
> KFD_MQD_TYPE type,
>   mqd->init_mqd = init_mqd_hiq;
>   mqd->free_mqd = free_mqd_hiq_sdma;
>   mqd->load_mqd = load_mqd;
> - mqd->update_mqd = update_mqd_hiq;
> + mqd->update_mqd = update_mqd;
>   mqd->destroy_mqd = destroy_mqd;
>   mqd->is_occupied = is_occupied;
>   mqd->mqd_size = sizeof(struct v9_mqd); @@ -475,7 +463,7
> @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE
> type,
>   mqd->init_mqd = init_mqd_hiq;
>   mqd->free_mqd = free_mqd;
>   mqd->load_mqd = load_mqd;
> - mqd->update_mqd = update_mqd_hiq;
> + mqd->update_mqd = update_mqd;
>   mqd->destroy_mqd = destroy_mqd;
>   mqd->is_occupied = is_occupied;
>   mqd->mqd_size = sizeof(struct v9_mqd); diff --git
> a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> index 3b6b5671964c..a5e8ff1e5945 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c
> @@ -312,11 +312,7 @@ static void init_mqd_hiq(struct mqd_manager *mm,
> void **mqd,  static void update_mqd_hiq(struct mqd_manager *mm, void
> *mqd,
>   struct queue_properties *q)
>  {
> - struct vi_mqd *m;
>   __update_mqd(mm,

RE: Rebasing of amd-staging-drm-next

2019-11-16 Thread Liu, Zhan

Hi Martin,

Probably you are missing a building package. You can give it another try after 
installing the following tools:
sudo apt install kernel-package libncurses5-dev pkg-config libssl-dev 
libelf-dev build-essential bison flex

Could you also elaborate more on what building errors did you encounter, and 
which branch (and which latest commit) were you using? May be I can help you 
with it.

Thanks,
Zhan

> -Original Message-
> From: amd-gfx  On Behalf Of Alex
> Deucher
> Sent: 2019/November/16, Saturday 11:28 AM
> To: Babutzka, Martin 
> Cc: amd-gfx list 
> Subject: Re: Rebasing of amd-staging-drm-next
> 
> It roughly follows drm-next.  If you want something more up to date, you can
> use my drm-next branch:
> https://cgit.freedesktop.org/~agd5f/linux/log/?h=drm-next
> 
> Alex
> 
> On Sat, Nov 16, 2019 at 11:25 AM Babutzka, Martin
>  wrote:
> >
> > Dear AMD developers,
> >
> > Are there plans to rebase the staging kennel to 5.4? Would be great
> because 5.3 does not builds properly for me.
> >
> > Many regards,
> > Martin
> >
> >
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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RE: [PATCH] drm/amd/display: remove "setting DIG_MODE twice" workaround

2019-11-04 Thread Liu, Zhan

Thank you Nick for the advice. I just reverted the original commit.

Zhan

> -Original Message-
> From: Kazlauskas, Nicholas 
> Sent: 2019/November/04, Monday 11:53 AM
> To: Liu, Zhan ; amd-gfx@lists.freedesktop.org; Wu,
> Hersen 
> Subject: Re: [PATCH] drm/amd/display: remove "setting DIG_MODE twice"
> workaround
> 
> On 2019-11-04 11:06 a.m., Liu, Zhan wrote:
> > [Why]
> > The root cause of Navi14 HDMI pink screen issue has been found.
> > There is no need to set DIG_MODE twice anymore.
> >
> > [How]
> > Remove "setting DIG_MODE" twice workaround.
> >
> > Signed-off-by: Zhan Liu 
> 
> Please use git to revert the commit instead:
> 
> eg.
> 
> git revert 
> 
> Then add the reasoning to the revert commit message.
> 
> Thanks,
> 
> Nicholas Kazlauskas
> 
> > ---
> >   drivers/gpu/drm/amd/display/dc/core/dc_link.c | 9 -
> >   1 file changed, 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> > index cc94c1a73daa..12ba6fdf89b7 100644
> > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> > @@ -3027,15 +3027,6 @@ void core_link_enable_stream(
> >  
> > CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
> >  COLOR_DEPTH_UNDEFINED);
> >
> > -   /* This second call is needed to reconfigure the DIG
> > -* as a workaround for the incorrect value being applied
> > -* from transmitter control.
> > -*/
> > -   if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
> > -   stream->link->link_enc->funcs->setup(
> > -   stream->link->link_enc,
> > -   pipe_ctx->stream->signal);
> > -
> >   #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> >  if (pipe_ctx->stream->timing.flags.DSC) {
> >  if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
> > --
> > 2.21.0
> > ___
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> >

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[PATCH] drm/amd/display: remove "setting DIG_MODE twice" workaround

2019-11-04 Thread Liu, Zhan

[Why]
The root cause of Navi14 HDMI pink screen issue has been found.
There is no need to set DIG_MODE twice anymore.

[How]
Remove "setting DIG_MODE" twice workaround.

Signed-off-by: Zhan Liu 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 9 -
 1 file changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index cc94c1a73daa..12ba6fdf89b7 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -3027,15 +3027,6 @@ void core_link_enable_stream(
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
COLOR_DEPTH_UNDEFINED);

-   /* This second call is needed to reconfigure the DIG
-* as a workaround for the incorrect value being applied
-* from transmitter control.
-*/
-   if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
-   stream->link->link_enc->funcs->setup(
-   stream->link->link_enc,
-   pipe_ctx->stream->signal);
-
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
if (pipe_ctx->stream->timing.flags.DSC) {
if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
--
2.21.0
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RE: [PATCH] drm/amd/display: Add ENGINE_ID_DIGD condition check for Navi14

2019-11-01 Thread Liu, Zhan

Thank you Hersen. Please check the updated patch:

From: Liu, Zhan  
Sent: Friday, November 1, 2019 9:18 PM
To: amd-gfx@lists.freedesktop.org; Kazlauskas, Nicholas 
; Lakha, Bhawanpreet ; 
Li, Roman ; Liu, Zhan ; Siqueira, Rodrigo 
; Wentland, Harry ; Wu, 
Hersen ; Zuo, Jerry 
Cc: Yeh, Eagle ; Lazare, Jordan 
Subject: [PATCH] drm/amd/display: Add ENGINE_ID_DIGD condition check for Navi14

From: Zhan liu 
Date: Fri, 1 Nov 2019 21:10:17 -0400
Subject: [PATCH] drm/amd/display: Add ENGINE_ID_DIGD condition check for Navi14

[Why]
Navi10 has 6 PHY, but Navi14 only has 5 PHY, that is because there is no 
ENGINE_ID_DIGD in Navi14. Without this patch, many HDMI related issues (e.g. 
HDMI S3 resume failure, HDMI pink screen on boot) will be observed.

[How]
If eng_id is larger than ENGINE_ID_DIGD, then add eng_id by 1.

Signed-off-by: Zhan liu 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 +++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 924c2e303588..cf886483e380 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1152,6 +1152,11 @@ struct stream_encoder *dcn20_stream_encoder_create(
if (!enc1)
return NULL;

+   if (ASIC_REV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
+   if (eng_id >= ENGINE_ID_DIGD)
+   eng_id++;
+   }
+
dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
_enc_regs[eng_id],
_shift, _mask);
--
2.21.0

> -Original Message-
> From: Wu, Hersen 
> Sent: 2019/November/01, Friday 9:23 PM
> To: Liu, Zhan ; amd-gfx@lists.freedesktop.org;
> Kazlauskas, Nicholas ; Lakha, Bhawanpreet
> ; Li, Roman ;
> Siqueira, Rodrigo ; Wentland, Harry
> ; Zuo, Jerry 
> Cc: Yeh, Eagle ; Lazare, Jordan
> 
> Subject: RE: [PATCH] drm/amd/display: Add ENGINE_ID_DIGD condition
> check for Navi14
> 
> Hi Zhan,
> 
> The function is shared by NV10,12,14.
> 
> Please add ASIC ID check  for the DIG D skip.
> 
> Thanks!
> Hersen
> 
> 
> -Original Message-
> From: Liu, Zhan 
> Sent: Friday, November 1, 2019 9:18 PM
> To: amd-gfx@lists.freedesktop.org; Kazlauskas, Nicholas
> ; Lakha, Bhawanpreet
> ; Li, Roman ; Liu,
> Zhan ; Siqueira, Rodrigo ;
> Wentland, Harry ; Wu, Hersen
> ; Zuo, Jerry 
> Cc: Yeh, Eagle ; Lazare, Jordan
> 
> Subject: [PATCH] drm/amd/display: Add ENGINE_ID_DIGD condition check
> for Navi14
> 
> From: Zhan liu 
> Date: Fri, 1 Nov 2019 21:10:17 -0400
> Subject: [PATCH] drm/amd/display: Add ENGINE_ID_DIGD condition check
> for Navi14
> 
> [Why]
> Navi10 has 6 PHY, but Navi14 only has 5 PHY, that is because there is no
> ENGINE_ID_DIGD in Navi14. Without this patch, many HDMI related issues
> (e.g. HDMI S3 resume failure, HDMI pink screen on boot) will be observed.
> 
> [How]
> If eng_id is larger than ENGINE_ID_DIGD, then add eng_id by 1.
> 
> Signed-off-by: Zhan liu 
> ---
>  drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> index 924c2e303588..cf886483e380 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
> @@ -1152,6 +1152,9 @@ struct stream_encoder
> *dcn20_stream_encoder_create(
> if (!enc1)
> return NULL;
> 
> +   if (eng_id >= ENGINE_ID_DIGD)
> +   eng_id++;
> +
> dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
> _enc_regs[eng_id],
> _shift, _mask);
> --
> 2.21.0
> 
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> 
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[PATCH] drm/amd/display: Add ENGINE_ID_DIGD condition check for Navi14

2019-11-01 Thread Liu, Zhan

From: Zhan liu 
Date: Fri, 1 Nov 2019 21:10:17 -0400
Subject: [PATCH] drm/amd/display: Add ENGINE_ID_DIGD condition check for Navi14

[Why]
Navi10 has 6 PHY, but Navi14 only has 5 PHY, that is
because there is no ENGINE_ID_DIGD in Navi14. Without
this patch, many HDMI related issues (e.g. HDMI S3
resume failure, HDMI pink screen on boot) will be
observed.

[How]
If eng_id is larger than ENGINE_ID_DIGD, then
add eng_id by 1.

Signed-off-by: Zhan liu 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 924c2e303588..cf886483e380 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1152,6 +1152,9 @@ struct stream_encoder *dcn20_stream_encoder_create(
if (!enc1)
return NULL;

+   if (eng_id >= ENGINE_ID_DIGD)
+   eng_id++;
+
dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
_enc_regs[eng_id],
_shift, _mask);
--
2.21.0

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[PATCH] drm/amd/display: Change Navi14's DWB flag to 1

2019-10-21 Thread Liu, Zhan

[PATCH] drm/amd/display: Change Navi14's DWB flag to 1

[Why]
DWB (Display Writeback) flag needs to be enabled as 1, or system
will throw out a few warnings when creating dcn20 resource pool.
Also, Navi14's dwb setting needs to match Navi10's,
which has already been set to 1.

[How]
Change value of num_dwb from 0 to 1.

Signed-off-by: Zhan Liu 
---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 914e378bcda4..d4937c475e7c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -816,7 +816,7 @@ static const struct resource_caps res_cap_nv14 = {
.num_audio = 6,
.num_stream_encoder = 5,
.num_pll = 5,
-   .num_dwb = 0,
+   .num_dwb = 1,
.num_ddc = 5,
 };

--
2.21.0

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RE: [PATCH v2] drm/amd/display: Modify display link stream setup sequence.

2019-10-17 Thread Liu, Zhan

Thx! Will do it.

Zhan

From: Kazlauskas, Nicholas 
Sent: 2019/October/17, Thursday 4:51 PM
To: Liu, Zhan ; amd-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2] drm/amd/display: Modify display link stream setup 
sequence.

This is actually setting DIG mode a second time, right? I don't think this is 
what sets GC_SEND.

Please mention that this is setting the DIG_MODE to the correct value after 
having been overridden by the call to transmitter control in your patch 
description. Also correct the HACK comment to mention that this second call is 
needed to reconfigure the DIG as a workaround for the incorrect value being 
applied from transmitter control. Specifics help in source.

I don't think there is a case where we'd want HDMI changed to DVI so it's 
probably fine to leave this as is for now...

With those fixed, you can add my:

Reviewed-by: Nicholas Kazlauskas 
mailto:nicholas.kazlaus...@amd.com>>

Thanks,

Nicholas Kazlauskas

From: amd-gfx 
mailto:amd-gfx-boun...@lists.freedesktop.org>>
 on behalf of Liu, Zhan mailto:zhan@amd.com>>
Sent: Thursday, October 17, 2019, 3:04 PM
To: amd-gfx@lists.freedesktop.org<mailto:amd-gfx@lists.freedesktop.org>; Liu, 
Zhan
Subject: [PATCH v2] drm/amd/display: Modify display link stream setup sequence.

[Why]
This patch is for fixing Navi14 pink screen issue. With this
patch, stream->link->link_enc->funcs->setup will be called
twice: this will make sure GC_SEND is set to 1. Though we
still need to look into why the issue only happens on
Linux, but not on Windows side.

[How]
Call stream->link->link_enc->funcs->setup twice.

Signed-off-by: Zhan liu mailto:zhan@amd.com>>
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 935053664160..8683e8613ec2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2842,6 +2842,12 @@ void core_link_enable_stream(
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
COLOR_DEPTH_UNDEFINED);

+   /* Hack on Navi14: fixes Navi14 HDMI pink screen issue */
+   if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
+   stream->link->link_enc->funcs->setup(
+   stream->link->link_enc,
+   pipe_ctx->stream->signal);
+
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
if (pipe_ctx->stream->timing.flags.DSC) {
if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
--
2.17.0
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[PATCH v2] drm/amd/display: Modify display link stream setup sequence.

2019-10-17 Thread Liu, Zhan

[Why]
This patch is for fixing Navi14 pink screen issue. With this
patch, stream->link->link_enc->funcs->setup will be called
twice: this will make sure GC_SEND is set to 1. Though we
still need to look into why the issue only happens on
Linux, but not on Windows side.

[How]
Call stream->link->link_enc->funcs->setup twice.

Signed-off-by: Zhan liu 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 935053664160..8683e8613ec2 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2842,6 +2842,12 @@ void core_link_enable_stream(
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
COLOR_DEPTH_UNDEFINED);

+   /* Hack on Navi14: fixes Navi14 HDMI pink screen issue */
+   if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
+   stream->link->link_enc->funcs->setup(
+   stream->link->link_enc,
+   pipe_ctx->stream->signal);
+
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
if (pipe_ctx->stream->timing.flags.DSC) {
if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
--
2.17.0
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RE: [PATCH] drm/amd/display: Modify display link stream setup sequence.

2019-10-17 Thread Liu, Zhan

Inline.

> -Original Message-
> From: Kazlauskas, Nicholas 
> Sent: 2019/October/17, Thursday 9:37 AM
> To: Liu, Zhan ; amd-gfx@lists.freedesktop.org
> Subject: Re: [PATCH] drm/amd/display: Modify display link stream setup
> sequence.
> 
> On 2019-10-17 12:28 a.m., Liu, Zhan wrote:
> > From: Zhan Liu 
> >
> > [Why]
> > When a specific kind of connector is detected,
> > DC needs to set the attribute of the stream.
> > This step needs to be done before enabling link,
> > or some bugs (e.g. display won't light up)
> > will be observed.
> >
> > [How]
> > Setting the attribute of the stream first, then
> > enabling stream.
> >
> > Signed-off-by: Zhan Liu 
> 
> NAK:
> 
> 1. It's difficult to understand what issue this change is attempting to
> solve and why it actually does it. Specifics would help here.

Some of the details are IP-sensitive, that's why I choose not to include 
details.

> 
> 2. It affects a common code path for all ASICs which has been tested and
> known to be working correctly for those test cases.

As we discussed before, considering Navi10 and Navi14 are using the same DC 
code, and the issue is only happening on Navi14, its more likely the issue is a 
BIOS issue. However, if we want to fix it on display side, we can only do some 
kinds of workaround to fix it. Another alternative is to do stream setup twice, 
but there is no point to repeat the setup two times. 

If we really worry about all AISCs will be influenced, we can guard the section 
as a Navi14 specific code, and treat this patch as a "hack".

> 
> 3. The description is incorrect - the link enable/stream enable were
> both previously happening after the stream setup. What's changed in the
> patch is the link enable now happens before the link setup.
> 
> Both of these calls internally go through the command table to VBIOS so
> what behavior differences you're seeing may be caused by the input
> parameters to the ATOM_ENCODER_CMD_STREAM_SETUP or
> TRANSMITTER_CONTROL_ENABLE commands or the actual execution of
> those
> commands.
> 
> Nicholas Kazlauskas
> 
> > ---
> >   drivers/gpu/drm/amd/display/dc/core/dc_link.c | 20 +--
> >   1 file changed, 10 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> > index fb18681b502b..713caab82837 100644
> > --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> > +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> > @@ -2745,16 +2745,6 @@ void core_link_enable_stream(
> >  dc_is_virtual_signal(pipe_ctx->stream->signal))
> >  return;
> >
> > -   if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
> > -   stream->link->link_enc->funcs->setup(
> > -   stream->link->link_enc,
> > -   pipe_ctx->stream->signal);
> > -   pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
> > -   pipe_ctx->stream_res.stream_enc,
> > -   pipe_ctx->stream_res.tg->inst,
> > -   stream->timing.timing_3d_format !=
> TIMING_3D_FORMAT_NONE);
> > -   }
> > -
> >  if (dc_is_dp_signal(pipe_ctx->stream->signal))
> >  pipe_ctx->stream_res.stream_enc->funcs-
> >dp_set_stream_attribute(
> >  pipe_ctx->stream_res.stream_enc,
> > @@ -2841,6 +2831,16 @@ void core_link_enable_stream(
> >  
> > CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
> >  COLOR_DEPTH_UNDEFINED);
> >
> > +   if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
> > +   stream->link->link_enc->funcs->setup(
> > +   stream->link->link_enc,
> > +   pipe_ctx->stream->signal);
> > +   pipe_ctx->stream_res.stream_enc->funcs-
> >setup_stereo_sync(
> > +   pipe_ctx->stream_res.stream_enc,
> > +   pipe_ctx->stream_res.tg->inst,
> > +   stream->timing.timing_3d_format !=
> TIMING_3D_FORMAT_NONE);
> > +   }
> > +
> >   #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
> >  if (pipe_ctx->stream->timing.flags.DSC) {
> >  if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
> > --
> > 2.17.1
> > ___
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> > amd-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> >

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[PATCH] drm/amd/display: Modify display link stream setup sequence.

2019-10-16 Thread Liu, Zhan

From: Zhan Liu 

[Why]
When a specific kind of connector is detected,
DC needs to set the attribute of the stream.
This step needs to be done before enabling link,
or some bugs (e.g. display won't light up)
will be observed.

[How]
Setting the attribute of the stream first, then
enabling stream.

Signed-off-by: Zhan Liu 
---
 drivers/gpu/drm/amd/display/dc/core/dc_link.c | 20 +--
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c 
b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index fb18681b502b..713caab82837 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -2745,16 +2745,6 @@ void core_link_enable_stream(
dc_is_virtual_signal(pipe_ctx->stream->signal))
return;

-   if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
-   stream->link->link_enc->funcs->setup(
-   stream->link->link_enc,
-   pipe_ctx->stream->signal);
-   pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
-   pipe_ctx->stream_res.stream_enc,
-   pipe_ctx->stream_res.tg->inst,
-   stream->timing.timing_3d_format != 
TIMING_3D_FORMAT_NONE);
-   }
-
if (dc_is_dp_signal(pipe_ctx->stream->signal))
pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
pipe_ctx->stream_res.stream_enc,
@@ -2841,6 +2831,16 @@ void core_link_enable_stream(
CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
COLOR_DEPTH_UNDEFINED);

+   if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
+   stream->link->link_enc->funcs->setup(
+   stream->link->link_enc,
+   pipe_ctx->stream->signal);
+   
pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
+   pipe_ctx->stream_res.stream_enc,
+   pipe_ctx->stream_res.tg->inst,
+   stream->timing.timing_3d_format != 
TIMING_3D_FORMAT_NONE);
+   }
+
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
if (pipe_ctx->stream->timing.flags.DSC) {
if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
--
2.17.1
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RE: [PATCH] drm/amd/include: add aux timeout vega registers

2019-10-04 Thread Liu, Zhan

Looks good to me.

Reviewed-by: Zhan Liu 

-Original Message-
From: amd-gfx  On Behalf Of 
roman...@amd.com
Sent: 2019/October/04, Friday 3:45 PM
To: amd-gfx@lists.freedesktop.org
Cc: Berthe, Abdoulaye ; Liu, Zhan ; 
Li, Roman ; Wentland, Harry ; 
Deucher, Alexander ; Lakha, Bhawanpreet 

Subject: [PATCH] drm/amd/include: add aux timeout vega registers

From: Roman Li 

DC needs them to support configurable aux timeout on vega

Signed-off-by: Roman Li 
---
 drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h 
b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h
index bcd190a..832d7b2 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dce/dce_12_0_sh_mask.h
@@ -35549,7 +35549,11 @@
 #define DP_AUX0_AUX_DPHY_RX_CONTROL0__AUX_RX_DETECTION_THRESHOLD_MASK  
   0x7000L
 //DP_AUX0_AUX_DPHY_RX_CONTROL1
 #define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP__SHIFT 
   0x0
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN__SHIFT
   0x8
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL__SHIFT
   0xf
 #define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_PRECHARGE_SKIP_MASK   
   0x00FFL
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MASK  
   0x7F00L
+#define DP_AUX0_AUX_DPHY_RX_CONTROL1__AUX_RX_TIMEOUT_LEN_MUL_MASK  
   0x00018000L
 //DP_AUX0_AUX_DPHY_TX_STATUS
 #define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_ACTIVE__SHIFT   
   0x0
 #define DP_AUX0_AUX_DPHY_TX_STATUS__AUX_TX_STATE__SHIFT
   0x4
-- 
2.7.4

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RE: [PATCH 87/87] drm/amd/display: Force uclk to max for every state

2019-07-18 Thread Liu, Zhan



Reviewed-by: Zhan Liu 




-Original Message-
From: amd-gfx  On Behalf Of 
sunpeng...@amd.com
Sent: Monday, July 15, 2019 5:21 PM
To: amd-gfx@lists.freedesktop.org
Cc: Li, Sun peng (Leo) ; Kazlauskas, Nicholas 

Subject: [PATCH 87/87] drm/amd/display: Force uclk to max for every state

From: Nicholas Kazlauskas 

Workaround for now to avoid underflow.

The uclk switch time should really be bumped up to 404, but doing so would 
expose p-state hang issues for higher bandwidth display configurations.

Change-Id: I98060fc9c4eeece07ef54e13a144def88a3c3d21
Signed-off-by: Nicholas Kazlauskas 
Signed-off-by: Leo Li 
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c   |  6 +++---
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c  | 10 ++
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 983a1bd56272..74697cef5dfe 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -912,11 +912,11 @@ void dm_pp_get_funcs(
/* todo set_pme_wa_enable cause 4k@6ohz display not light up */
funcs->nv_funcs.set_pme_wa_enable = NULL;
/* todo debug waring message */
-   funcs->nv_funcs.set_hard_min_uclk_by_freq = NULL;
+   funcs->nv_funcs.set_hard_min_uclk_by_freq = 
+pp_nv_set_hard_min_uclk_by_freq;
/* todo  compare data with window driver*/
-   funcs->nv_funcs.get_maximum_sustainable_clocks = NULL;
+   funcs->nv_funcs.get_maximum_sustainable_clocks = 
+pp_nv_get_maximum_sustainable_clocks;
/*todo  compare data with window driver */
-   funcs->nv_funcs.get_uclk_dpm_states = NULL;
+   funcs->nv_funcs.get_uclk_dpm_states = pp_nv_get_uclk_dpm_states;
break;
 #endif
default:
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index 2cf788a3704e..44537651f0a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -2707,6 +2707,9 @@ static void cap_soc_clocks(
&& max_clocks.uClockInKhz != 0)
bb->clock_limits[i].dram_speed_mts = 
(max_clocks.uClockInKhz / 1000) * 16;
 
+   // HACK: Force every uclk to max for now to "disable" uclk 
switching.
+   bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 
1000) 
+* 16;
+
if ((bb->clock_limits[i].fabricclk_mhz > 
(max_clocks.fabricClockInKhz / 1000))
&& max_clocks.fabricClockInKhz 
!= 0)
bb->clock_limits[i].fabricclk_mhz = 
(max_clocks.fabricClockInKhz / 1000); @@ -2922,6 +2925,8 @@ static bool 
init_soc_bounding_box(struct dc *dc,
le32_to_cpu(bb->vmm_page_size_bytes);
dcn2_0_soc.dram_clock_change_latency_us =

fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
+   // HACK!! Lower uclock latency switch time so we don't switch
+   dcn2_0_soc.dram_clock_change_latency_us = 10;
dcn2_0_soc.writeback_dram_clock_change_latency_us =

fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
dcn2_0_soc.return_bus_width_bytes =
@@ -2963,6 +2968,7 @@ static bool init_soc_bounding_box(struct dc *dc,
struct pp_smu_nv_clock_table max_clocks = {0};
unsigned int uclk_states[8] = {0};
unsigned int num_states = 0;
+   int i;
enum pp_smu_status status;
bool clock_limits_available = false;
bool uclk_states_available = false;
@@ -2984,6 +2990,10 @@ static bool init_soc_bounding_box(struct dc *dc,
clock_limits_available = (status == PP_SMU_RESULT_OK);
}
 
+   // HACK: Use the max uclk_states value for all elements.
+   for (i = 0; i < num_states; i++)
+   uclk_states[i] = uclk_states[num_states - 1];
+
if (clock_limits_available && uclk_states_available && 
num_states)
update_bounding_box(dc, _0_soc, _clocks, 
uclk_states, num_states);
else if (clock_limits_available)
--
2.22.0

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