Re: [PATCH] drm/amd/display: Update DCN302 SR Exit Latency

2021-04-08 Thread R, Bindu 
[AMD Official Use Only - Internal Distribution Only]

​Hi Jay,
   Could you please add few details on the root cause, in the [Why/How] section?

Thanks,
Bindu

From: Aurabindo Pillai 
Sent: Thursday, April 8, 2021 11:48 AM
To: amd-gfx@lists.freedesktop.org 
Cc: Pillai, Aurabindo ; R, Bindu ; 
Aberback, Joshua 
Subject: [PATCH] drm/amd/display: Update DCN302 SR Exit Latency

From: Joshua Aberback 

[Why]
Update SR Exit Latency to fix screen flickering caused due to OTG
underflow

Signed-off-by: Joshua Aberback 
Acked-by: Aurabindo Pillai 
---
 drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
index a928c1d9a557..fc2dea243d1b 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn302/dcn302_resource.c
@@ -164,7 +164,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc = {

 .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
 .num_states = 1,
-   .sr_exit_time_us = 12,
+   .sr_exit_time_us = 15.5,
 .sr_enter_plus_exit_time_us = 20,
 .urgent_latency_us = 4.0,
 .urgent_latency_pixel_data_only_us = 4.0,
--
2.31.1

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Re: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

2021-03-22 Thread R, Bindu 
[AMD Official Use Only - Internal Distribution Only]

​Hi,
The updated patch has been merged and is available with commit ID 
"ef5c594461650de0a18aa0bfd240189991790d7e".
Somehow missed to mail the updated version, attached is the updated patch, 
please review and let me know if any changes required.

Thanks,
Bindu

 ​

From: Michel Dänzer 
Sent: Monday, March 22, 2021 5:32 AM
To: R, Bindu ; Lakha, Bhawanpreet ; 
amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Zhou1, Tao 
; Feng, Kenneth 
Subject: Re: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

On 2021-03-20 1:31 a.m., R, Bindu wrote:
>
> The Update patch has been submitted.

Submitted where? Still can't see it.


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From ef5c594461650de0a18aa0bfd240189991790d7e Mon Sep 17 00:00:00 2001
From: Bindu Ramamurthy 
Date: Tue, 16 Mar 2021 17:08:47 -0400
Subject: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

[Why]
idle optimization was being disabled after commit.

[How]
check vblank count for display off and enable idle optimization based on this count.
Also,check added to ensure vblank count does not decrement, when count reaches 0.

Signed-off-by: Bindu Ramamurthy 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6e7a333abbe0..f455fc3aa561 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -987,7 +987,7 @@ static void event_mall_stutter(struct work_struct *work)
 
 	if (vblank_work->enable)
 		dm->active_vblank_irq_count++;
-	else
+	else if(dm->active_vblank_irq_count)
 		dm->active_vblank_irq_count--;
 
 	dc_allow_idle_optimizations(
@@ -8705,9 +8705,14 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
 		dm_enable_per_frame_crtc_master_sync(dc_state);
 		mutex_lock(>dc_lock);
 		WARN_ON(!dc_commit_state(dm->dc, dc_state));
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+   /* Allow idle optimization when vblank count is 0 for display off */
+   if (dm->active_vblank_irq_count == 0)
+   dc_allow_idle_optimizations(dm->dc,true);
+#endif
 		mutex_unlock(>dc_lock);
 	}
-
+			   
 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 
-- 
2.25.1

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Re: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

2021-03-19 Thread R, Bindu 
[AMD Official Use Only - Internal Distribution Only]

The Update patch has been submitted.

​Regards,
Bindu

From: Michel Dänzer 
Sent: Friday, March 19, 2021 6:31 AM
To: R, Bindu ; Lakha, Bhawanpreet ; 
amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Zhou1, Tao 
; Feng, Kenneth 
Subject: Re: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

On 2021-03-19 1:44 a.m., R, Bindu wrote:
>
> ​Hi All,
>Thanks for the inputs, have updated the patch to include these changes.

Updated where? I can't find an updated patch.


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Re: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

2021-03-18 Thread R, Bindu 
[AMD Official Use Only - Internal Distribution Only]

​Hi All,
   Thanks for the inputs, have updated the patch to include these changes.

Regards,
Bindu


From: Lakha, Bhawanpreet 
Sent: Wednesday, March 17, 2021 1:02 PM
To: Michel Dänzer ; R, Bindu ; 
amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Feng, Kenneth 
; Zhou1, Tao 
Subject: Re: [PATCH] drm/amd/display: Allow idle optimization based on vblank.


[AMD Official Use Only - Internal Distribution Only]

Hi Bindu,

dc_allow_idle_optimizations() should be called within mutex_lock(>dc_lock). 
Please call it right after WARN_ON(!dc_commit_state(dm->dc, dc_state)) but 
before unlock().

Bhawan

From: amd-gfx  on behalf of Michel 
Dänzer 
Sent: March 17, 2021 7:37 AM
To: R, Bindu ; amd-gfx@lists.freedesktop.org 

Cc: Deucher, Alexander ; Feng, Kenneth 
; Zhou1, Tao ; Lakha, Bhawanpreet 

Subject: Re: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

On 2021-03-17 12:49 a.m., Bindu Ramamurthy wrote:
> [Why]
> idle optimization was being disabled after commit.
>
> [How]
> check vblank count for display off and enable idle optimization based on this 
> count.
>
> Signed-off-by: Bindu Ramamurthy 
> ---
>  drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
> b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 553e39f9538c..56a55143ad2d 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -987,7 +987,7 @@ static void event_mall_stutter(struct work_struct *work)
>
>if (vblank_work->enable)
>dm->active_vblank_irq_count++;
> - else
> + else if(dm->active_vblank_irq_count)
>dm->active_vblank_irq_count--;

The commit log should explain why this part is needed.


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Re: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

2021-03-17 Thread R, Bindu 
[AMD Public Use]

Thanks Guchun, yes this would require CONFIG_DRM_AMD_DC_DCN flag, will update 
it.

Regards,
Bindu

From: Chen, Guchun 
Sent: Tuesday, March 16, 2021 11:32 PM
To: Feng, Kenneth ; R, Bindu ; 
amd-gfx@lists.freedesktop.org 
Cc: Deucher, Alexander ; Zhou1, Tao 
; Lakha, Bhawanpreet ; R, Bindu 

Subject: RE: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

[AMD Public Use]

+/* Allow idle optimization when vblank count is 0 for display off */
+if (dm->active_vblank_irq_count == 0)
+   dc_allow_idle_optimizations(dm->dc,true);
+

Above part needs to be guarded by CONFIG_DRM_AMD_DC_DCN?

Regards,
Guchun

-Original Message-
From: amd-gfx  On Behalf Of Feng, Kenneth
Sent: Wednesday, March 17, 2021 9:45 AM
To: R, Bindu ; amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Zhou1, Tao 
; Lakha, Bhawanpreet ; R, Bindu 

Subject: RE: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Kenneth Feng 


-Original Message-
From: amd-gfx  On Behalf Of Bindu 
Ramamurthy
Sent: Wednesday, March 17, 2021 7:50 AM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander ; Lakha, Bhawanpreet 
; Zhou1, Tao ; Feng, Kenneth 
; R, Bindu 
Subject: [PATCH] drm/amd/display: Allow idle optimization based on vblank.

[CAUTION: External Email]

[Why]
idle optimization was being disabled after commit.

[How]
check vblank count for display off and enable idle optimization based on this 
count.

Signed-off-by: Bindu Ramamurthy 
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 
b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 553e39f9538c..56a55143ad2d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -987,7 +987,7 @@ static void event_mall_stutter(struct work_struct *work)

if (vblank_work->enable)
dm->active_vblank_irq_count++;
-   else
+   else if(dm->active_vblank_irq_count)
dm->active_vblank_irq_count--;

dc_allow_idle_optimizations(
@@ -8694,7 +8694,10 @@ static void amdgpu_dm_atomic_commit_tail(struct 
drm_atomic_state *state)
WARN_ON(!dc_commit_state(dm->dc, dc_state));
mutex_unlock(>dc_lock);
}
-
+/* Allow idle optimization when vblank count is 0 for display off */
+if (dm->active_vblank_irq_count == 0)
+   dc_allow_idle_optimizations(dm->dc,true);
+
for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);

--
2.25.1

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Re: [PATCH 08/13] drm/amd/display: Synchronize displays with different timings

2021-02-22 Thread R, Bindu 
[AMD Official Use Only - Internal Distribution Only]

​Hi Nils,
   We have incorporated the review comments and the updated patch would be 
applied with this promotion.

 @ Stempen, Vladimir,
 Thanks for your support.

Regards,
Bindu

From: R, Bindu 
Sent: Monday, February 22, 2021 8:43 AM
To: Nils Wallménius 
Cc: amd-gfx@lists.freedesktop.org ; Stempen, 
Vladimir ; Brol, Eryk ; Li, Sun 
peng (Leo) ; Wentland, Harry ; 
Zhuo, Qingqing ; Siqueira, Rodrigo 
; Jacob, Anson ; Pillai, 
Aurabindo ; Lakha, Bhawanpreet 

Subject: Re: [PATCH 08/13] drm/amd/display: Synchronize displays with different 
timings

Hi Nils,​
   ​Thanks for the inputs.

@ Stempen, Vladimir<mailto:vladimir.stem...@amd.com>,
  ​ As the array 'prime_numbers' has constant values defined, we can mark 
this as static const. Would you like to change the count calculation -or- 
retain the same limit iteration ? All the patches would be merged to upstream 
by today. please suggest.

Thanks,
Bindu

From: Nils Wallménius 
Sent: Sunday, February 21, 2021 1:21 AM
To: R, Bindu 
Cc: amd-gfx@lists.freedesktop.org ; Stempen, 
Vladimir ; Brol, Eryk ; Li, Sun 
peng (Leo) ; Wentland, Harry ; 
Zhuo, Qingqing ; Siqueira, Rodrigo 
; Jacob, Anson ; Pillai, 
Aurabindo ; Lakha, Bhawanpreet 

Subject: Re: [PATCH 08/13] drm/amd/display: Synchronize displays with different 
timings

Hi Bindu, an inline comment below.

Den fre 19 feb. 2021 23:16Bindu Ramamurthy 
mailto:bind...@amd.com>> skrev:
From: Vladimir Stempen 
mailto:vladimir.stem...@amd.com>>

[why]
 Vendor based fan noise improvement

[how]
Report timing synchronizable when DP streams time frame
difference is less than 0.05 percent. Adjust DP  DTOs and
sync displays using  MASTER_UPDATE_LOCK_DB_X_Y

Signed-off-by: Vladimir Stempen 
mailto:vladimir.stem...@amd.com>>
Acked-by: Bindu Ramamurthy mailto:bind...@amd.com>>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  28 ++-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |  43 
 drivers/gpu/drm/amd/display/dc/dc.h   |   3 +
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h  |   1 +
 drivers/gpu/drm/amd/display/dc/dc_stream.h|   3 +
 .../drm/amd/display/dc/dce/dce_clock_source.c |  52 +++-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 225 ++
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |   5 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |   2 +
 .../display/dc/dcn10/dcn10_stream_encoder.c   |   1 -
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |   1 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 123 ++
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   8 +-
 .../dc/dcn30/dcn30_dio_stream_encoder.c   |   1 -
 .../gpu/drm/amd/display/dc/inc/clock_source.h |   5 +
 .../amd/display/dc/inc/hw/timing_generator.h  |  12 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   3 +
 drivers/gpu/drm/amd/display/dc/inc/resource.h |   4 +
 18 files changed, 505 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2f56fa2c0bf4..39df5d2c0108 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1102,6 +1102,7 @@ static void program_timing_sync(

for (i = 0; i < pipe_count; i++) {
int group_size = 1;
+   enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE;
struct pipe_ctx *pipe_set[MAX_PIPES];

if (!unsynced_pipes[i])
@@ -1116,10 +1117,22 @@ static void program_timing_sync(
for (j = i + 1; j < pipe_count; j++) {
if (!unsynced_pipes[j])
continue;
-
-   if (resource_are_streams_timing_synchronizable(
+   if (sync_type != TIMING_SYNCHRONIZABLE &&
+   dc->hwss.enable_vblanks_synchronization &&
+   
unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks &&
+   resource_are_vblanks_synchronizable(
+   unsynced_pipes[j]->stream,
+   pipe_set[0]->stream)) {
+   sync_type = VBLANK_SYNCHRONIZABLE;
+   pipe_set[group_size] = unsynced_pipes[j];
+   unsynced_pipes[j] = NULL;
+   group_size++;
+   } else
+   if (sync_type != VBLANK_SYNCHRONIZABLE &&
+   resource_are_streams_timing_synchronizable(
unsynced_pipes[j]->stream,
pipe_set[0]->stream)) {
+   sync_type = TIMING_SYNCHRONIZABLE;
pipe_s

Re: [PATCH 08/13] drm/amd/display: Synchronize displays with different timings

2021-02-22 Thread R, Bindu 
[AMD Official Use Only - Internal Distribution Only]

Hi Nils,?
   ?Thanks for the inputs.

@ Stempen, Vladimir<mailto:vladimir.stem...@amd.com>,
  ? As the array 'prime_numbers' has constant values defined, we can mark 
this as static const. Would you like to change the count calculation -or- 
retain the same limit iteration ? All the patches would be merged to upstream 
by today. please suggest.

Thanks,
Bindu

From: Nils Wallménius 
Sent: Sunday, February 21, 2021 1:21 AM
To: R, Bindu 
Cc: amd-gfx@lists.freedesktop.org ; Stempen, 
Vladimir ; Brol, Eryk ; Li, Sun 
peng (Leo) ; Wentland, Harry ; 
Zhuo, Qingqing ; Siqueira, Rodrigo 
; Jacob, Anson ; Pillai, 
Aurabindo ; Lakha, Bhawanpreet 

Subject: Re: [PATCH 08/13] drm/amd/display: Synchronize displays with different 
timings

Hi Bindu, an inline comment below.

Den fre 19 feb. 2021 23:16Bindu Ramamurthy 
mailto:bind...@amd.com>> skrev:
From: Vladimir Stempen 
mailto:vladimir.stem...@amd.com>>

[why]
 Vendor based fan noise improvement

[how]
Report timing synchronizable when DP streams time frame
difference is less than 0.05 percent. Adjust DP  DTOs and
sync displays using  MASTER_UPDATE_LOCK_DB_X_Y

Signed-off-by: Vladimir Stempen 
mailto:vladimir.stem...@amd.com>>
Acked-by: Bindu Ramamurthy mailto:bind...@amd.com>>
---
 drivers/gpu/drm/amd/display/dc/core/dc.c  |  28 ++-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |  43 
 drivers/gpu/drm/amd/display/dc/dc.h   |   3 +
 drivers/gpu/drm/amd/display/dc/dc_hw_types.h  |   1 +
 drivers/gpu/drm/amd/display/dc/dc_stream.h|   3 +
 .../drm/amd/display/dc/dce/dce_clock_source.c |  52 +++-
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 225 ++
 .../amd/display/dc/dcn10/dcn10_hw_sequencer.h |   5 +
 .../gpu/drm/amd/display/dc/dcn10/dcn10_optc.h |   2 +
 .../display/dc/dcn10/dcn10_stream_encoder.c   |   1 -
 .../gpu/drm/amd/display/dc/dcn20/dcn20_init.c |   1 +
 .../gpu/drm/amd/display/dc/dcn20/dcn20_optc.c | 123 ++
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |   8 +-
 .../dc/dcn30/dcn30_dio_stream_encoder.c   |   1 -
 .../gpu/drm/amd/display/dc/inc/clock_source.h |   5 +
 .../amd/display/dc/inc/hw/timing_generator.h  |  12 +
 .../gpu/drm/amd/display/dc/inc/hw_sequencer.h |   3 +
 drivers/gpu/drm/amd/display/dc/inc/resource.h |   4 +
 18 files changed, 505 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c 
b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 2f56fa2c0bf4..39df5d2c0108 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1102,6 +1102,7 @@ static void program_timing_sync(

for (i = 0; i < pipe_count; i++) {
int group_size = 1;
+   enum timing_synchronization_type sync_type = NOT_SYNCHRONIZABLE;
struct pipe_ctx *pipe_set[MAX_PIPES];

if (!unsynced_pipes[i])
@@ -1116,10 +1117,22 @@ static void program_timing_sync(
for (j = i + 1; j < pipe_count; j++) {
if (!unsynced_pipes[j])
continue;
-
-   if (resource_are_streams_timing_synchronizable(
+   if (sync_type != TIMING_SYNCHRONIZABLE &&
+   dc->hwss.enable_vblanks_synchronization &&
+   
unsynced_pipes[j]->stream_res.tg->funcs->align_vblanks &&
+   resource_are_vblanks_synchronizable(
+   unsynced_pipes[j]->stream,
+   pipe_set[0]->stream)) {
+   sync_type = VBLANK_SYNCHRONIZABLE;
+   pipe_set[group_size] = unsynced_pipes[j];
+   unsynced_pipes[j] = NULL;
+   group_size++;
+   } else
+   if (sync_type != VBLANK_SYNCHRONIZABLE &&
+   resource_are_streams_timing_synchronizable(
unsynced_pipes[j]->stream,
pipe_set[0]->stream)) {
+   sync_type = TIMING_SYNCHRONIZABLE;
pipe_set[group_size] = unsynced_pipes[j];
unsynced_pipes[j] = NULL;
group_size++;
@@ -1145,7 +1158,6 @@ static void program_timing_sync(
}
}

-
for (k = 0; k < group_size; k++) {
struct dc_stream_status *status = 
dc_stream_get_status_from_state(ctx, pipe_set[k]->stream);

@@ -1175,8 +1187,14 @@ static void program_timing_sync(
}

if (group_size > 1) {
-   dc->h