[PATCH] drm/amdgpu: turn back rlcg write for gfx_v10
There is no need to use amdgpu_mm_wreg_mmio_rlc()
during initialization time because this interface
is only designed for debugfs case to access the
registers which are only permitted by RLCG during
run-time. Therefore, turn back rlcg write for gfx_v10.
If we not turn back it, it will raise amdgpu load failure.
[ 54.904333] amdgpu: SMU driver if version not matched
[ 54.904393] amdgpu: SMU is initialized successfully!
[ 54.905971] [drm] kiq ring mec 2 pipe 1 q 0
[ 55.115416] amdgpu :00:06.0: [drm:amdgpu_ring_test_helper [amdgpu]]
*ERROR* ring gfx_0.0.0 test failed (-110)
[ 55.118877] [drm:amdgpu_device_init [amdgpu]] *ERROR* hw_init of IP block
failed -110
[ 55.126587] amdgpu :00:06.0: amdgpu_device_ip_init failed
[ 55.133466] amdgpu :00:06.0: Fatal error during GPU init
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 449408cfd018..bd5dd4f64311 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4577,13 +4577,11 @@ static int gfx_v10_0_init_csb(struct amdgpu_device
*adev)
adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
/* csib */
- /* amdgpu_mm_wreg_mmio_rlc will fall back to mmio if doesn't support
rlcg_write */
- amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0,
mmRLC_CSIB_ADDR_HI),
-adev->gfx.rlc.clear_state_gpu_addr >> 32, 0);
- amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0,
mmRLC_CSIB_ADDR_LO),
-adev->gfx.rlc.clear_state_gpu_addr &
0xfffc, 0);
- amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0,
mmRLC_CSIB_LENGTH),
-adev->gfx.rlc.clear_state_size, 0);
+ WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
+adev->gfx.rlc.clear_state_gpu_addr >> 32);
+ WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
+adev->gfx.rlc.clear_state_gpu_addr & 0xfffc);
+ WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH,
adev->gfx.rlc.clear_state_size);
return 0;
}
@@ -5192,7 +5190,7 @@ static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device
*adev, bool enable)
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
- amdgpu_mm_wreg_mmio_rlc(adev, SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL),
tmp, 0);
+ WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
for (i = 0; i < adev->usec_timeout; i++) {
if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: protect ring overrun
Wait for the oldest sequence on the ring
to be signaled in order to make sure there
will be no command overrun.
v2: fix coding stype and remove abs operation
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 10 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 22 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 8 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 1 -
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 1 -
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 14 +++---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 8 +++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 +++-
9 files changed, 61 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 7531527067df..397bd5fa77cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -192,14 +192,22 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct
dma_fence **f,
* Used For polling fence.
* Returns 0 on success, -ENOMEM on failure.
*/
-int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s)
+int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
+ uint32_t timeout)
{
uint32_t seq;
+ signed long r = 0;
if (!s)
return -EINVAL;
seq = ++ring->fence_drv.sync_seq;
+ r = amdgpu_fence_wait_polling(ring,
+ seq - ring->fence_drv.num_fences_mask,
+ timeout);
+ if (r < 1)
+ return -ETIMEDOUT;
+
amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
seq, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index a721b0e0ff69..0103acc57474 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -675,13 +675,15 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev,
uint32_t reg)
spin_lock_irqsave(>ring_lock, flags);
if (amdgpu_device_wb_get(adev, _val_offs)) {
- spin_unlock_irqrestore(>ring_lock, flags);
pr_err("critical bug! too many kiq readers\n");
- goto failed_kiq_read;
+ goto failed_unlock;
}
amdgpu_ring_alloc(ring, 32);
amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
- amdgpu_fence_emit_polling(ring, );
+ r = amdgpu_fence_emit_polling(ring, , MAX_KIQ_REG_WAIT);
+ if (r)
+ goto failed_undo;
+
amdgpu_ring_commit(ring);
spin_unlock_irqrestore(>ring_lock, flags);
@@ -712,7 +714,13 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev,
uint32_t reg)
amdgpu_device_wb_free(adev, reg_val_offs);
return value;
+failed_undo:
+ amdgpu_ring_undo(ring);
+failed_unlock:
+ spin_unlock_irqrestore(>ring_lock, flags);
failed_kiq_read:
+ if (reg_val_offs)
+ amdgpu_device_wb_free(adev, reg_val_offs);
pr_err("failed to read reg:%x\n", reg);
return ~0;
}
@@ -730,7 +738,10 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t
reg, uint32_t v)
spin_lock_irqsave(>ring_lock, flags);
amdgpu_ring_alloc(ring, 32);
amdgpu_ring_emit_wreg(ring, reg, v);
- amdgpu_fence_emit_polling(ring, );
+ r = amdgpu_fence_emit_polling(ring, , MAX_KIQ_REG_WAIT);
+ if (r)
+ goto failed_undo;
+
amdgpu_ring_commit(ring);
spin_unlock_irqrestore(>ring_lock, flags);
@@ -759,6 +770,9 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t
reg, uint32_t v)
return;
+failed_undo:
+ amdgpu_ring_undo(ring);
+ spin_unlock_irqrestore(>ring_lock, flags);
failed_kiq_write:
pr_err("failed to write reg:%x\n", reg);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 137d3d2b46e8..be218754629a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -118,7 +118,8 @@ void amdgpu_fence_driver_suspend(struct amdgpu_device
*adev);
void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence,
unsigned flags);
-int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s);
+int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
+ uint32_t timeout);
bool amdgpu_fence_process(struct amdgpu_ring *ring);
int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/a
[PATCH] drm/amdgpu: protect ring overrun
Wait for the oldest sequence on the ring
to be signaled in order to make sure there
will be no command overrun.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 7 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 17 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 8 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 -
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 8 +++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 +++-
6 files changed, 51 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 7531527067df..5462ea83d8b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -200,6 +200,13 @@ int amdgpu_fence_emit_polling(struct amdgpu_ring *ring,
uint32_t *s)
return -EINVAL;
seq = ++ring->fence_drv.sync_seq;
+ if ((abs(seq - ring->fence_drv.num_fences_mask) >
+ ring->fence_drv.num_fences_mask) &&
+ (amdgpu_fence_wait_polling(ring,
+ seq - ring->fence_drv.num_fences_mask,
+ MAX_KIQ_REG_WAIT) < 1))
+return -ETIME;
+
amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
seq, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index a721b0e0ff69..7087333681f6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -681,7 +681,14 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev,
uint32_t reg)
}
amdgpu_ring_alloc(ring, 32);
amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
- amdgpu_fence_emit_polling(ring, );
+ r = amdgpu_fence_emit_polling(ring, );
+ if (r) {
+ amdgpu_ring_undo(ring);
+ amdgpu_device_wb_free(adev, reg_val_offs);
+ spin_unlock_irqrestore(>ring_lock, flags);
+ goto failed_kiq_read;
+ }
+
amdgpu_ring_commit(ring);
spin_unlock_irqrestore(>ring_lock, flags);
@@ -730,7 +737,13 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t
reg, uint32_t v)
spin_lock_irqsave(>ring_lock, flags);
amdgpu_ring_alloc(ring, 32);
amdgpu_ring_emit_wreg(ring, reg, v);
- amdgpu_fence_emit_polling(ring, );
+ r = amdgpu_fence_emit_polling(ring, );
+ if (r) {
+ amdgpu_ring_undo(ring);
+ spin_unlock_irqrestore(>ring_lock, flags);
+ goto failed_kiq_write;
+ }
+
amdgpu_ring_commit(ring);
spin_unlock_irqrestore(>ring_lock, flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 8c10084f44ef..12d181ac7e78 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -60,7 +60,13 @@ void amdgpu_virt_kiq_reg_write_reg_wait(struct amdgpu_device
*adev,
amdgpu_ring_alloc(ring, 32);
amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1,
ref, mask);
- amdgpu_fence_emit_polling(ring, );
+ r = amdgpu_fence_emit_polling(ring, );
+ if (r) {
+ amdgpu_ring_undo(ring);
+ spin_unlock_irqrestore(>ring_lock, flags);
+ goto failed_kiq;
+ }
+
amdgpu_ring_commit(ring);
spin_unlock_irqrestore(>ring_lock, flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 5b1549f167b0..650b7a67d3bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4068,7 +4068,14 @@ static uint64_t gfx_v9_0_kiq_read_clock(struct
amdgpu_device *adev)
reg_val_offs * 4));
amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
reg_val_offs * 4));
- amdgpu_fence_emit_polling(ring, );
+ r = amdgpu_fence_emit_polling(ring, );
+ if (r) {
+ amdgpu_ring_undo(ring);
+ amdgpu_device_wb_free(adev, reg_val_offs);
+ spin_unlock_irqrestore(>ring_lock, flags);
+ goto failed_kiq_read;
+ }
+
amdgpu_ring_commit(ring);
spin_unlock_irqrestore(>ring_lock, flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 30b75d79efdb..71430f2a2374 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -427,7 +427,13 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct
amdgpu_device *adev,
amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
kiq->pmf->kiq_invalidate_tlbs(r
[PATCH] drm/amdgpu: protect kiq overrun
Wait for the oldest sequence on the kiq ring
to be signaled in order to make sure there
will be no kiq overrun.
v2: remove unused the variable and correct
kiq max_sub_num value
Signed-off-by: Yintian Tao
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 6
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 6
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 30 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 6
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 7 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +
8 files changed, 71 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 691c89705bcd..fac8b9713dfc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -325,6 +325,12 @@ static int kgd_hiq_mqd_load(struct kgd_dev *kgd, void *mqd,
mec, pipe, queue_id);
spin_lock(>gfx.kiq.ring_lock);
+ r = amdgpu_gfx_kiq_is_avail(>gfx.kiq);
+ if (r) {
+ pr_err("critical bug! too many kiq submission\n");
+ goto out_unlock;
+ }
+
r = amdgpu_ring_alloc(kiq_ring, 7);
if (r) {
pr_err("Failed to alloc KIQ (%d).\n", r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index df841c2ac5e7..fd42c126510f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -323,6 +323,12 @@ int kgd_gfx_v9_hiq_mqd_load(struct kgd_dev *kgd, void *mqd,
mec, pipe, queue_id);
spin_lock(>gfx.kiq.ring_lock);
+ r = amdgpu_gfx_kiq_is_avail(>gfx.kiq);
+ if (r) {
+ pr_err("critical bug! too many kiq submissions\n");
+ goto out_unlock;
+ }
+
r = amdgpu_ring_alloc(kiq_ring, 7);
if (r) {
pr_err("Failed to alloc KIQ (%d).\n", r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index a721b0e0ff69..84e66c45df37 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -321,6 +321,9 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
AMDGPU_RING_PRIO_DEFAULT);
if (r)
dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
+ else
+ kiq->max_sub_num = (ring->ring_size / 4) /
+ (ring->funcs->align_mask + 1);
return r;
}
@@ -663,6 +666,21 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
return 0;
}
+int amdgpu_gfx_kiq_is_avail(struct amdgpu_kiq *kiq)
+{
+ uint32_t seq = 0;
+ signed long r = 0;
+
+ seq = abs(kiq->ring.fence_drv.sync_seq - kiq->max_sub_num);
+ if (seq > kiq->max_sub_num) {
+ r = amdgpu_fence_wait_polling(>ring, seq,
+ MAX_KIQ_REG_WAIT);
+ return r < 1 ? -ETIME : 0;
+ }
+
+ return 0;
+}
+
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
{
signed long r, cnt = 0;
@@ -674,6 +692,12 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev,
uint32_t reg)
BUG_ON(!ring->funcs->emit_rreg);
spin_lock_irqsave(>ring_lock, flags);
+ r = amdgpu_gfx_kiq_is_avail(>gfx.kiq);
+ if (r) {
+ spin_unlock_irqrestore(>ring_lock, flags);
+ goto failed_kiq_read;
+ }
+
if (amdgpu_device_wb_get(adev, _val_offs)) {
spin_unlock_irqrestore(>ring_lock, flags);
pr_err("critical bug! too many kiq readers\n");
@@ -728,6 +752,12 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t
reg, uint32_t v)
BUG_ON(!ring->funcs->emit_wreg);
spin_lock_irqsave(>ring_lock, flags);
+ r = amdgpu_gfx_kiq_is_avail(>gfx.kiq);
+ if (r) {
+ spin_unlock_irqrestore(>ring_lock, flags);
+ goto failed_kiq_write;
+ }
+
amdgpu_ring_alloc(ring, 32);
amdgpu_ring_emit_wreg(ring, reg, v);
amdgpu_fence_emit_polling(ring, );
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index ee698f0246d8..1ee59a927bd9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -103,6 +103,7 @@ struct amdgpu_kiq {
struct amdgpu_ring ring;
struct amdgpu_irq_src irq;
const struct kiq_pm4_funcs *pmf;
+ uint32_tmax_sub_num;
};
/
[PATCH] drm/amdgpu: protect kiq overrun
Wait for the oldest to be signaled to make sure
there will be no kiq overrun.
Signed-off-by: Yintian Tao
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 8 -
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 8 -
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 30 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 6
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 7 +
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +
8 files changed, 73 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 691c89705bcd..72a5d7e15494 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -311,7 +311,7 @@ static int kgd_hiq_mqd_load(struct kgd_dev *kgd, void *mqd,
struct amdgpu_device *adev = get_amdgpu_device(kgd);
struct amdgpu_ring *kiq_ring = >gfx.kiq.ring;
struct v10_compute_mqd *m;
- uint32_t mec, pipe;
+ uint32_t mec, pipe, seq = 0;
int r;
m = get_mqd(mqd);
@@ -325,6 +325,12 @@ static int kgd_hiq_mqd_load(struct kgd_dev *kgd, void *mqd,
mec, pipe, queue_id);
spin_lock(>gfx.kiq.ring_lock);
+ r = amdgpu_gfx_kiq_is_avail(>gfx.kiq);
+ if (r) {
+ pr_err("critical bug! too many kiq submission\n");
+ goto out_unlock;
+ }
+
r = amdgpu_ring_alloc(kiq_ring, 7);
if (r) {
pr_err("Failed to alloc KIQ (%d).\n", r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index df841c2ac5e7..332f72b2d334 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -309,7 +309,7 @@ int kgd_gfx_v9_hiq_mqd_load(struct kgd_dev *kgd, void *mqd,
struct amdgpu_device *adev = get_amdgpu_device(kgd);
struct amdgpu_ring *kiq_ring = >gfx.kiq.ring;
struct v9_mqd *m;
- uint32_t mec, pipe;
+ uint32_t mec, pipe, seq = 0;
int r;
m = get_mqd(mqd);
@@ -323,6 +323,12 @@ int kgd_gfx_v9_hiq_mqd_load(struct kgd_dev *kgd, void *mqd,
mec, pipe, queue_id);
spin_lock(>gfx.kiq.ring_lock);
+ r = amdgpu_gfx_kiq_is_avail(>gfx.kiq);
+ if (r) {
+ pr_err("critical bug! too many kiq submissions\n");
+ goto out_unlock;
+ }
+
r = amdgpu_ring_alloc(kiq_ring, 7);
if (r) {
pr_err("Failed to alloc KIQ (%d).\n", r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index a721b0e0ff69..387b1a8ed4df 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -321,6 +321,9 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
AMDGPU_RING_PRIO_DEFAULT);
if (r)
dev_warn(adev->dev, "(%d) failed to init kiq ring\n", r);
+ else
+ kiq->max_sub_num = (ring->ring_size / 4) /
+ ring->funcs->align_mask;
return r;
}
@@ -663,6 +666,21 @@ int amdgpu_gfx_cp_ecc_error_irq(struct amdgpu_device *adev,
return 0;
}
+int amdgpu_gfx_kiq_is_avail(struct amdgpu_kiq *kiq)
+{
+ uint32_t seq = 0;
+ signed long r = 0;
+
+ seq = abs(kiq->ring.fence_drv.sync_seq - kiq->max_sub_num);
+ if (seq > kiq->max_sub_num) {
+ r = amdgpu_fence_wait_polling(>ring, seq,
+ MAX_KIQ_REG_WAIT);
+ return r < 1 ? -ETIME : 0;
+ }
+
+ return 0;
+}
+
uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
{
signed long r, cnt = 0;
@@ -674,6 +692,12 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev,
uint32_t reg)
BUG_ON(!ring->funcs->emit_rreg);
spin_lock_irqsave(>ring_lock, flags);
+ r = amdgpu_gfx_kiq_is_avail(>gfx.kiq);
+ if (r) {
+ spin_unlock_irqrestore(>ring_lock, flags);
+ goto failed_kiq_read;
+ }
+
if (amdgpu_device_wb_get(adev, _val_offs)) {
spin_unlock_irqrestore(>ring_lock, flags);
pr_err("critical bug! too many kiq readers\n");
@@ -728,6 +752,12 @@ void amdgpu_kiq_wreg(struct amdgpu_device *adev, uint32_t
reg, uint32_t v)
BUG_ON(!ring->funcs->emit_wreg);
spin_lock_irqsave(>ring_lock, flags);
+ r = amdgpu_gfx_kiq_is_avail(>gfx.kiq);
+ if (r) {
+ spin_unlock_irqrestore(>ring_lock, flags);
+ goto failed
[PATCH] drm/amdgpu: request reg_val_offs each kiq read reg
According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 through KIQ
4. client-B poll the seqno-1
5. the kiq complete these two read operation
6. client-A to read the register at the wb buffer and
get REG-1 value
Therefore, use amdgpu_device_wb_get() to request reg_val_offs
for each kiq read register.
v2: fix the error remove
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 19 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +++--
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 7 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 27
7 files changed, 41 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4e1d4cfe7a9f..7ee5a4da398a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -526,7 +526,7 @@ static inline void amdgpu_set_ib_value(struct
amdgpu_cs_parser *p,
/*
* Writeback
*/
-#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for
amdgpu-owned rings. */
+#define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for
amdgpu-owned rings. */
struct amdgpu_wb {
struct amdgpu_bo*wb_obj;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index ea576b4260a4..d5a59d7c48d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -304,10 +304,6 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
spin_lock_init(>ring_lock);
- r = amdgpu_device_wb_get(adev, >reg_val_offs);
- if (r)
- return r;
-
ring->adev = NULL;
ring->ring_obj = NULL;
ring->use_doorbell = true;
@@ -331,7 +327,6 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
{
- amdgpu_device_wb_free(ring->adev, ring->adev->gfx.kiq.reg_val_offs);
amdgpu_ring_fini(ring);
}
@@ -672,15 +667,20 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev,
uint32_t reg)
{
signed long r, cnt = 0;
unsigned long flags;
- uint32_t seq;
+ uint32_t seq, reg_val_offs = 0, value = 0;
struct amdgpu_kiq *kiq = >gfx.kiq;
struct amdgpu_ring *ring = >ring;
BUG_ON(!ring->funcs->emit_rreg);
spin_lock_irqsave(>ring_lock, flags);
+ if (amdgpu_device_wb_get(adev, _val_offs)) {
+ spin_unlock_irqrestore(>ring_lock, flags);
+ pr_err("critical bug! too more kiq readers\n");
+ goto failed_kiq_read;
+ }
amdgpu_ring_alloc(ring, 32);
- amdgpu_ring_emit_rreg(ring, reg);
+ amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
amdgpu_fence_emit_polling(ring, );
amdgpu_ring_commit(ring);
spin_unlock_irqrestore(>ring_lock, flags);
@@ -707,7 +707,10 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev,
uint32_t reg)
if (cnt > MAX_KIQ_REG_TRY)
goto failed_kiq_read;
- return adev->wb.wb[kiq->reg_val_offs];
+ mb();
+ value = adev->wb.wb[reg_val_offs];
+ amdgpu_device_wb_free(adev, reg_val_offs);
+ return value;
failed_kiq_read:
pr_err("failed to read reg:%x\n", reg);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 634746829024..ee698f0246d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -103,7 +103,6 @@ struct amdgpu_kiq {
struct amdgpu_ring ring;
struct amdgpu_irq_src irq;
const struct kiq_pm4_funcs *pmf;
- uint32_treg_val_offs;
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index f61664ee4940..137d3d2b46e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -181,7 +181,8 @@ struct amdgpu_ring_funcs {
void (*end_use)(struct amdgpu_ring *ring);
void (*emit_switch_buffer) (struct amdgpu_ring *ring);
void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
- void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
+ void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
+ uint32_t reg_val_offs);
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
void (*emit_reg_wait)(s
[PATCH] drm/amdgpu: request reg_val_offs each kiq read reg
According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 through KIQ
4. client-B poll the seqno-1
5. the kiq complete these two read operation
6. client-A to read the register at the wb buffer and
get REG-1 value
Therefore, use amdgpu_device_wb_get() to request reg_val_offs
for each kiq read register.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 19 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +++--
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 7 +++---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 27
7 files changed, 41 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4e1d4cfe7a9f..7ee5a4da398a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -526,7 +526,7 @@ static inline void amdgpu_set_ib_value(struct
amdgpu_cs_parser *p,
/*
* Writeback
*/
-#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for
amdgpu-owned rings. */
+#define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for
amdgpu-owned rings. */
struct amdgpu_wb {
struct amdgpu_bo*wb_obj;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index ea576b4260a4..d5a59d7c48d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -304,10 +304,6 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
spin_lock_init(>ring_lock);
- r = amdgpu_device_wb_get(adev, >reg_val_offs);
- if (r)
- return r;
-
ring->adev = NULL;
ring->ring_obj = NULL;
ring->use_doorbell = true;
@@ -331,7 +327,6 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
{
- amdgpu_device_wb_free(ring->adev, ring->adev->gfx.kiq.reg_val_offs);
amdgpu_ring_fini(ring);
}
@@ -672,15 +667,20 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev,
uint32_t reg)
{
signed long r, cnt = 0;
unsigned long flags;
- uint32_t seq;
+ uint32_t seq, reg_val_offs = 0, value = 0;
struct amdgpu_kiq *kiq = >gfx.kiq;
struct amdgpu_ring *ring = >ring;
BUG_ON(!ring->funcs->emit_rreg);
spin_lock_irqsave(>ring_lock, flags);
+ if (amdgpu_device_wb_get(adev, _val_offs)) {
+ spin_unlock_irqrestore(>ring_lock, flags);
+ pr_err("critical bug! too more kiq readers\n");
+ goto failed_kiq_read;
+ }
amdgpu_ring_alloc(ring, 32);
- amdgpu_ring_emit_rreg(ring, reg);
+ amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
amdgpu_fence_emit_polling(ring, );
amdgpu_ring_commit(ring);
spin_unlock_irqrestore(>ring_lock, flags);
@@ -707,7 +707,10 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev,
uint32_t reg)
if (cnt > MAX_KIQ_REG_TRY)
goto failed_kiq_read;
- return adev->wb.wb[kiq->reg_val_offs];
+ mb();
+ value = adev->wb.wb[reg_val_offs];
+ amdgpu_device_wb_free(adev, reg_val_offs);
+ return value;
failed_kiq_read:
pr_err("failed to read reg:%x\n", reg);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 634746829024..ee698f0246d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -103,7 +103,6 @@ struct amdgpu_kiq {
struct amdgpu_ring ring;
struct amdgpu_irq_src irq;
const struct kiq_pm4_funcs *pmf;
- uint32_treg_val_offs;
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index f61664ee4940..137d3d2b46e8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -181,7 +181,8 @@ struct amdgpu_ring_funcs {
void (*end_use)(struct amdgpu_ring *ring);
void (*emit_switch_buffer) (struct amdgpu_ring *ring);
void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
- void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
+ void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
+ uint32_t reg_val_offs);
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
void (*emit_reg_wait)(struct amdgpu_ring *
[PATCH] drm/amdgpu: refine kiq access register
According to the current kiq access register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 through KIQ
4. client-B poll the seqno-1
5. the kiq complete these two read operation
6. client-A to read the register at the wb buffer and
get REG-1 value
And if there are multiple clients to frequently write
registers through KIQ which may raise the KIQ ring buffer
overwritten problem.
Therefore, allocate fixed number wb slot for rreg use
and limit the submit number which depends on the kiq
ring_size in order to prevent the overwritten problem.
v2: directly use amdgpu_device_wb_get() for each read instead
of to reserve fixde number slot.
if there is no enough kiq ring buffer or rreg slot then
directly print error log and return instead of busy waiting
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 +-
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 13 ++-
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 13 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 83 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 13 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 8 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 8 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 35 +---
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 13 ++-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 13 ++-
12 files changed, 167 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4e1d4cfe7a9f..1157c1a0b888 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -526,7 +526,7 @@ static inline void amdgpu_set_ib_value(struct
amdgpu_cs_parser *p,
/*
* Writeback
*/
-#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for
amdgpu-owned rings. */
+#define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for
amdgpu-owned rings. */
struct amdgpu_wb {
struct amdgpu_bo*wb_obj;
@@ -1028,6 +1028,12 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device
*adev);
int emu_soc_asic_init(struct amdgpu_device *adev);
+int amdgpu_gfx_kiq_lock(struct amdgpu_kiq *kiq, bool read,
+ unsigned long *flags);
+void amdgpu_gfx_kiq_unlock(struct amdgpu_kiq *kiq, unsigned long *flags);
+
+void amdgpu_gfx_kiq_consume(struct amdgpu_kiq *kiq, uint32_t *offs);
+void amdgpu_gfx_kiq_restore(struct amdgpu_kiq *kiq, uint32_t *offs);
/*
* Registers read & write functions.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 691c89705bcd..a65d6a1abc04 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -309,9 +309,11 @@ static int kgd_hiq_mqd_load(struct kgd_dev *kgd, void *mqd,
uint32_t doorbell_off)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ struct amdgpu_kiq *kiq = >gfx.kiq;
struct amdgpu_ring *kiq_ring = >gfx.kiq.ring;
struct v10_compute_mqd *m;
uint32_t mec, pipe;
+ unsigned long flags = 0;
int r;
m = get_mqd(mqd);
@@ -324,13 +326,19 @@ static int kgd_hiq_mqd_load(struct kgd_dev *kgd, void
*mqd,
pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
mec, pipe, queue_id);
- spin_lock(>gfx.kiq.ring_lock);
+ r = amdgpu_gfx_kiq_lock(kiq, false, );
+ if (r) {
+ pr_err("failed to lock kiq\n");
+ goto out_unlock;
+ }
+
r = amdgpu_ring_alloc(kiq_ring, 7);
if (r) {
pr_err("Failed to alloc KIQ (%d).\n", r);
goto out_unlock;
}
+ amdgpu_gfx_kiq_consume(kiq, NULL);
amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
amdgpu_ring_write(kiq_ring,
PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
@@ -350,8 +358,9 @@ static int kgd_hiq_mqd_load(struct kgd_dev *kgd, void *mqd,
amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi);
amdgpu_ring_commit(kiq_ring);
+ amdgpu_gfx_kiq_restore(kiq, NULL);
out_unlock:
- spin_unlock(>gfx.kiq.ring_lock);
+ amdgpu_gfx_kiq_unlock(>gfx.kiq, );
release_queue(kgd);
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index df841c2ac5e7..4435bd716edd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/am
[PATCH] drm/amdgpu: refine kiq access register
According to the current kiq access register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 through KIQ
4. client-B poll the seqno-1
5. the kiq complete these two read operation
6. client-A to read the register at the wb buffer and
get REG-1 value
And if there are multiple clients to frequently write
registers through KIQ which may raise the KIQ ring buffer
overwritten problem.
Therefore, allocate fixed number wb slot for rreg use
and limit the submit number which depends on the kiq
ring_size in order to prevent the overwritten problem.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 +-
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c| 12 +-
.../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 12 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 129 --
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 13 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 8 +-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 8 +-
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 34 +++--
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c| 12 +-
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 12 +-
12 files changed, 211 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 4e1d4cfe7a9f..4530e0de4257 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -526,7 +526,7 @@ static inline void amdgpu_set_ib_value(struct
amdgpu_cs_parser *p,
/*
* Writeback
*/
-#define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for
amdgpu-owned rings. */
+#define AMDGPU_MAX_WB 256 /* Reserve at most 256 WB slots for
amdgpu-owned rings. */
struct amdgpu_wb {
struct amdgpu_bo*wb_obj;
@@ -1028,6 +1028,11 @@ bool amdgpu_device_has_dc_support(struct amdgpu_device
*adev);
int emu_soc_asic_init(struct amdgpu_device *adev);
+int amdgpu_gfx_kiq_lock(struct amdgpu_kiq *kiq, bool read);
+void amdgpu_gfx_kiq_unlock(struct amdgpu_kiq *kiq);
+
+void amdgpu_gfx_kiq_consume(struct amdgpu_kiq *kiq, uint32_t *offs);
+void amdgpu_gfx_kiq_restore(struct amdgpu_kiq *kiq, uint32_t *offs);
/*
* Registers read & write functions.
*/
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 691c89705bcd..034c9f416499 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -309,6 +309,7 @@ static int kgd_hiq_mqd_load(struct kgd_dev *kgd, void *mqd,
uint32_t doorbell_off)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ struct amdgpu_kiq *kiq = >gfx.kiq;
struct amdgpu_ring *kiq_ring = >gfx.kiq.ring;
struct v10_compute_mqd *m;
uint32_t mec, pipe;
@@ -324,13 +325,19 @@ static int kgd_hiq_mqd_load(struct kgd_dev *kgd, void
*mqd,
pr_debug("kfd: set HIQ, mec:%d, pipe:%d, queue:%d.\n",
mec, pipe, queue_id);
- spin_lock(>gfx.kiq.ring_lock);
+ r = amdgpu_gfx_kiq_lock(kiq, false);
+ if (r) {
+ pr_err("failed to lock kiq\n");
+ goto out_unlock;
+ }
+
r = amdgpu_ring_alloc(kiq_ring, 7);
if (r) {
pr_err("Failed to alloc KIQ (%d).\n", r);
goto out_unlock;
}
+ amdgpu_gfx_kiq_consume(kiq, NULL);
amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
amdgpu_ring_write(kiq_ring,
PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
@@ -350,8 +357,9 @@ static int kgd_hiq_mqd_load(struct kgd_dev *kgd, void *mqd,
amdgpu_ring_write(kiq_ring, m->cp_hqd_pq_wptr_poll_addr_hi);
amdgpu_ring_commit(kiq_ring);
+ amdgpu_gfx_kiq_restore(kiq, NULL);
out_unlock:
- spin_unlock(>gfx.kiq.ring_lock);
+ amdgpu_gfx_kiq_unlock(>gfx.kiq);
release_queue(kgd);
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index df841c2ac5e7..f243d9990ced 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -307,6 +307,7 @@ int kgd_gfx_v9_hiq_mqd_load(struct kgd_dev *kgd, void *mqd,
uint32_t doorbell_off)
{
struct amdgpu_device *adev = get_amdgpu_device(kgd);
+ struct amdgpu_kiq *kiq = >gfx.kiq;
struct amdgpu_ring *kiq_ring = >gfx.kiq.ring;
struct v9_mqd *m;
uint32_t mec, pipe;
@@ -32
[PATCH] drm/amdgpu: only update spm vmid at first time
Original idea is from Monk which only update spm vmid
at first time which can release the frequent r/w register
burden under virtualization.
v2: set spm_vmid_updated to false when job timedout
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 ++
3 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 35c381ec0423..3bf59dfef05d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -50,6 +50,9 @@ static void amdgpu_job_timedout(struct drm_sched_job *s_job)
DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n",
ti.process_name, ti.tgid, ti.task_name, ti.pid);
+ if (job->vm)
+ job->vm->spm_vmid_updated = false;
+
if (amdgpu_device_should_recover_gpu(ring->adev)) {
amdgpu_device_gpu_recover(ring->adev, job);
} else {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index accbb34ea670..636a6d23fd96 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1080,11 +1080,14 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct
amdgpu_job *job,
struct dma_fence *fence = NULL;
bool pasid_mapping_needed = false;
unsigned patch_offset = 0;
- bool update_spm_vmid_needed = (job->vm &&
(job->vm->reserved_vmid[vmhub] != NULL));
+ bool update_spm_vmid_needed = (job->vm &&
(job->vm->reserved_vmid[vmhub] != NULL) &&
+ !job->vm->spm_vmid_updated);
int r;
- if (update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid)
+ if (update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid) {
adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
+ job->vm->spm_vmid_updated = true;
+ }
if (amdgpu_vmid_had_gpu_reset(adev, id)) {
gds_switch_needed = true;
@@ -2797,6 +2800,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct
amdgpu_vm *vm,
int r, i;
vm->va = RB_ROOT_CACHED;
+ vm->spm_vmid_updated = false;
for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
vm->reserved_vmid[i] = NULL;
INIT_LIST_HEAD(>evicted);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index ea771d84bf2b..02409e0ecf2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -319,6 +319,8 @@ struct amdgpu_vm {
boolbulk_moveable;
/* Flag to indicate if VM is used for compute */
boolis_compute_context;
+ /* flag to represent whether spm vmid has been updated */
+ boolspm_vmid_updated;
};
struct amdgpu_vm_manager {
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: update spm register through mmio
According to UMD design, only running performance analysis
benchmark just like RGP, GPA and so on need to update spm
register and others will not support this feature.
Therefore, we can directly access spm register through mmio.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c| 4 +++-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c| 4 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 3 +++
4 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index accbb34ea670..820f560adc33 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1083,7 +1083,9 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct
amdgpu_job *job,
bool update_spm_vmid_needed = (job->vm &&
(job->vm->reserved_vmid[vmhub] != NULL));
int r;
- if (update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid)
+ if ((!amdgpu_sriov_vf(adev) || amdgpu_passthrough(adev) ||
+amdgpu_sriov_is_pp_one_vf(adev)) &&
+ update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid)
adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
if (amdgpu_vmid_had_gpu_reset(adev, id)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 0a03e2ad5d95..bfb873f023c7 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7032,12 +7032,12 @@ static void gfx_v10_0_update_spm_vmid(struct
amdgpu_device *adev, unsigned vmid)
{
u32 data;
- data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
+ data = RREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL);
data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) <<
RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
- WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
+ WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
}
static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 84fcf842316d..514efc4fe269 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4950,12 +4950,12 @@ static void gfx_v9_0_update_spm_vmid(struct
amdgpu_device *adev, unsigned vmid)
{
u32 data;
- data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
+ data = RREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL);
data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) <<
RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
- WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
+ WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
}
static bool gfx_v9_0_check_rlcg_range(struct amdgpu_device *adev,
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index c893c645a4b2..56d02aa690a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -35,6 +35,9 @@
#define RREG32_SOC15(ip, inst, reg) \
RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
+#define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
+ RREG32_NO_KIQ(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
+
#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) +
offset)
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: refine kiq read register
According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 through KIQ
4. client-B poll the seqno-1
5. the kiq complete these two read operation
6. client-A to read the register at the wb buffer and
get REG-1 value
Therefore, directly make kiq write the register value at
the ring buffer then there will be no race condition for
the wb buffer.
v2: supply the read_clock and move the reg_val_offs back
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 11 --
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +++--
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 14 +---
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 14 +---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 28
6 files changed, 33 insertions(+), 40 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index ea576b4260a4..4e1c0239e561 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -304,10 +304,6 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
spin_lock_init(>ring_lock);
- r = amdgpu_device_wb_get(adev, >reg_val_offs);
- if (r)
- return r;
-
ring->adev = NULL;
ring->ring_obj = NULL;
ring->use_doorbell = true;
@@ -331,7 +327,6 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
{
- amdgpu_device_wb_free(ring->adev, ring->adev->gfx.kiq.reg_val_offs);
amdgpu_ring_fini(ring);
}
@@ -675,12 +670,14 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev,
uint32_t reg)
uint32_t seq;
struct amdgpu_kiq *kiq = >gfx.kiq;
struct amdgpu_ring *ring = >ring;
+ uint64_t reg_val_offs = 0;
BUG_ON(!ring->funcs->emit_rreg);
spin_lock_irqsave(>ring_lock, flags);
amdgpu_ring_alloc(ring, 32);
- amdgpu_ring_emit_rreg(ring, reg);
+ reg_val_offs = (ring->wptr & ring->buf_mask) + 30;
+ amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
amdgpu_fence_emit_polling(ring, );
amdgpu_ring_commit(ring);
spin_unlock_irqrestore(>ring_lock, flags);
@@ -707,7 +704,7 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev,
uint32_t reg)
if (cnt > MAX_KIQ_REG_TRY)
goto failed_kiq_read;
- return adev->wb.wb[kiq->reg_val_offs];
+ return ring->ring[reg_val_offs];
failed_kiq_read:
pr_err("failed to read reg:%x\n", reg);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 634746829024..ee698f0246d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -103,7 +103,6 @@ struct amdgpu_kiq {
struct amdgpu_ring ring;
struct amdgpu_irq_src irq;
const struct kiq_pm4_funcs *pmf;
- uint32_treg_val_offs;
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index f61664ee4940..a3d88f2aa9f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -181,7 +181,8 @@ struct amdgpu_ring_funcs {
void (*end_use)(struct amdgpu_ring *ring);
void (*emit_switch_buffer) (struct amdgpu_ring *ring);
void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
- void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
+ void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
+ uint64_t reg_val_offs);
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
uint32_t val, uint32_t mask);
@@ -265,7 +266,7 @@ struct amdgpu_ring {
#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
-#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
+#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r),
(d), (v), (m))
#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m)
(r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
diff --git
[PATCH] drm/amdgpu: refine kiq read register
According to the current kiq read register method,
there will be race condition when using KIQ to read
register if multiple clients want to read at same time
just like the expample below:
1. client-A start to read REG-0 throguh KIQ
2. client-A poll the seqno-0
3. client-B start to read REG-1 through KIQ
4. client-B poll the seqno-1
5. the kiq complete these two read operation
6. client-A to read the register at the wb buffer and
get REG-1 value
Therefore, directly make kiq write the register value at
the ring buffer then there will be no race condition for
the wb buffer.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 11 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 5 +++--
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 11 ++-
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c| 12 ++--
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c| 25
6 files changed, 32 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index ea576b4260a4..1253dd1ba42c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -304,10 +304,6 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
spin_lock_init(>ring_lock);
- r = amdgpu_device_wb_get(adev, >reg_val_offs);
- if (r)
- return r;
-
ring->adev = NULL;
ring->ring_obj = NULL;
ring->use_doorbell = true;
@@ -331,7 +327,6 @@ int amdgpu_gfx_kiq_init_ring(struct amdgpu_device *adev,
void amdgpu_gfx_kiq_free_ring(struct amdgpu_ring *ring)
{
- amdgpu_device_wb_free(ring->adev, ring->adev->gfx.kiq.reg_val_offs);
amdgpu_ring_fini(ring);
}
@@ -675,12 +670,14 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev,
uint32_t reg)
uint32_t seq;
struct amdgpu_kiq *kiq = >gfx.kiq;
struct amdgpu_ring *ring = >ring;
+ uint64_t reg_val_offs = 0;
BUG_ON(!ring->funcs->emit_rreg);
spin_lock_irqsave(>ring_lock, flags);
amdgpu_ring_alloc(ring, 32);
- amdgpu_ring_emit_rreg(ring, reg);
+ reg_val_offs = (ring->wptr & ring->buf_mask) + 16;
+ amdgpu_ring_emit_rreg(ring, reg, reg_val_offs);
amdgpu_fence_emit_polling(ring, );
amdgpu_ring_commit(ring);
spin_unlock_irqrestore(>ring_lock, flags);
@@ -707,7 +704,7 @@ uint32_t amdgpu_kiq_rreg(struct amdgpu_device *adev,
uint32_t reg)
if (cnt > MAX_KIQ_REG_TRY)
goto failed_kiq_read;
- return adev->wb.wb[kiq->reg_val_offs];
+ return ring->ring[reg_val_offs];
failed_kiq_read:
pr_err("failed to read reg:%x\n", reg);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
index 634746829024..ee698f0246d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
@@ -103,7 +103,6 @@ struct amdgpu_kiq {
struct amdgpu_ring ring;
struct amdgpu_irq_src irq;
const struct kiq_pm4_funcs *pmf;
- uint32_treg_val_offs;
};
/*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index f61664ee4940..a3d88f2aa9f4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -181,7 +181,8 @@ struct amdgpu_ring_funcs {
void (*end_use)(struct amdgpu_ring *ring);
void (*emit_switch_buffer) (struct amdgpu_ring *ring);
void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
- void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg);
+ void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
+ uint64_t reg_val_offs);
void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
uint32_t val, uint32_t mask);
@@ -265,7 +266,7 @@ struct amdgpu_ring {
#define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
#define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
#define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
-#define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
+#define amdgpu_ring_emit_rreg(r, d, o) (r)->funcs->emit_rreg((r), (d), (o))
#define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
#define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r),
(d), (v), (m))
#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m)
(r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/
[PATCH] drm/amdgpu: resume kiq access debugfs
If there is no GPU hang, user still can access
debugfs through kiq.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 12 +---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 2 ++
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 6a81c2ee7c7b..8c10084f44ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -335,17 +335,23 @@ void amdgpu_detect_virtualization(struct amdgpu_device
*adev)
}
}
-bool amdgpu_virt_can_access_debugfs(struct amdgpu_device *adev)
+bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
{
return amdgpu_sriov_is_debug(adev) ? true : false;
}
+bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
+{
+ return amdgpu_sriov_is_normal(adev) ? true : false;
+}
+
int amdgpu_virt_enable_access_debugfs(struct amdgpu_device *adev)
{
- if (!amdgpu_sriov_vf(adev))
+ if (!amdgpu_sriov_vf(adev) ||
+ amdgpu_virt_access_debugfs_is_kiq(adev))
return 0;
- if (amdgpu_virt_can_access_debugfs(adev))
+ if (amdgpu_virt_access_debugfs_is_mmio(adev))
adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
else
return -EPERM;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 8f20e6dbd7a9..de27308802c9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -299,6 +299,8 @@ static inline bool is_virtual_machine(void)
((adev)->virt.gim_feature & AMDGIM_FEATURE_PP_ONE_VF)
#define amdgpu_sriov_is_debug(adev) \
((!adev->in_gpu_reset) && adev->virt.tdr_debug)
+#define amdgpu_sriov_is_normal(adev) \
+ ((!adev->in_gpu_reset) && (!adev->virt.tdr_debug))
bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev);
void amdgpu_virt_init_setting(struct amdgpu_device *adev);
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: restrict debugfs register access under SR-IOV
Under bare metal, there is no more else to take
care of the GPU register access through MMIO.
Under Virtualization, to access GPU register is
implemented through KIQ during run-time due to
world-switch.
Therefore, under SR-IOV user can only access
debugfs to r/w GPU registers when meets all
three conditions below.
- amdgpu_gpu_recovery=0
- TDR happened
- in_gpu_reset=0
v2: merge amdgpu_virt_can_access_debugfs() into
amdgpu_virt_enable_access_debugfs()
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 73 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 8 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c| 26
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h| 7 ++
4 files changed, 108 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index c0f9a651dc06..1a4894fa3693 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -152,11 +152,16 @@ static int amdgpu_debugfs_process_reg_op(bool read,
struct file *f,
if (r < 0)
return r;
+ r = amdgpu_virt_enable_access_debugfs(adev);
+ if (r < 0)
+ return r;
+
if (use_bank) {
if ((sh_bank != 0x && sh_bank >=
adev->gfx.config.max_sh_per_se) ||
(se_bank != 0x && se_bank >=
adev->gfx.config.max_shader_engines)) {
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
return -EINVAL;
}
mutex_lock(>grbm_idx_mutex);
@@ -207,6 +212,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct
file *f,
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
return result;
}
@@ -255,6 +261,10 @@ static ssize_t amdgpu_debugfs_regs_pcie_read(struct file
*f, char __user *buf,
if (r < 0)
return r;
+ r = amdgpu_virt_enable_access_debugfs(adev);
+ if (r < 0)
+ return r;
+
while (size) {
uint32_t value;
@@ -263,6 +273,7 @@ static ssize_t amdgpu_debugfs_regs_pcie_read(struct file
*f, char __user *buf,
if (r) {
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
return r;
}
@@ -275,6 +286,7 @@ static ssize_t amdgpu_debugfs_regs_pcie_read(struct file
*f, char __user *buf,
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
return result;
}
@@ -304,6 +316,10 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file
*f, const char __user
if (r < 0)
return r;
+ r = amdgpu_virt_enable_access_debugfs(adev);
+ if (r < 0)
+ return r;
+
while (size) {
uint32_t value;
@@ -311,6 +327,7 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file
*f, const char __user
if (r) {
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
return r;
}
@@ -325,6 +342,7 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file
*f, const char __user
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
return result;
}
@@ -354,6 +372,10 @@ static ssize_t amdgpu_debugfs_regs_didt_read(struct file
*f, char __user *buf,
if (r < 0)
return r;
+ r = amdgpu_virt_enable_access_debugfs(adev);
+ if (r < 0)
+ return r;
+
while (size) {
uint32_t value;
@@ -362,6 +384,7 @@ static ssize_t amdgpu_debugfs_regs_didt_read(struct file
*f, char __user *buf,
if (r) {
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
return r;
}
@@ -374,6 +397,7 @@ static ssize_t amdgpu_debugfs_regs_didt_read(struct file
*f, char __user *buf,
pm_runtime_mark_last_busy(adev->ddev->dev
[PATCH] drm/amdgpu: restrict debugfs register access under SR-IOV
Under bare metal, there is no more else to take
care of the GPU register access through MMIO.
Under Virtualization, to access GPU register is
implemented through KIQ during run-time due to
world-switch.
Therefore, under SR-IOV user can only access
debugfs to r/w GPU registers when meets all
three conditions below.
- amdgpu_gpu_recovery=0
- TDR happened
- in_gpu_reset=0
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 83 -
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 7 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c| 23 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h| 7 ++
4 files changed, 114 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index c0f9a651dc06..4f9780aabf5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -152,11 +152,17 @@ static int amdgpu_debugfs_process_reg_op(bool read,
struct file *f,
if (r < 0)
return r;
+ if (!amdgpu_virt_can_access_debugfs(adev))
+ return -EINVAL;
+ else
+ amdgpu_virt_enable_access_debugfs(adev);
+
if (use_bank) {
if ((sh_bank != 0x && sh_bank >=
adev->gfx.config.max_sh_per_se) ||
(se_bank != 0x && se_bank >=
adev->gfx.config.max_shader_engines)) {
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
return -EINVAL;
}
mutex_lock(>grbm_idx_mutex);
@@ -207,6 +213,7 @@ static int amdgpu_debugfs_process_reg_op(bool read, struct
file *f,
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
return result;
}
@@ -255,6 +262,11 @@ static ssize_t amdgpu_debugfs_regs_pcie_read(struct file
*f, char __user *buf,
if (r < 0)
return r;
+ if (!amdgpu_virt_can_access_debugfs(adev))
+ return -EINVAL;
+ else
+ amdgpu_virt_enable_access_debugfs(adev);
+
while (size) {
uint32_t value;
@@ -263,6 +275,7 @@ static ssize_t amdgpu_debugfs_regs_pcie_read(struct file
*f, char __user *buf,
if (r) {
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
return r;
}
@@ -275,6 +288,7 @@ static ssize_t amdgpu_debugfs_regs_pcie_read(struct file
*f, char __user *buf,
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
return result;
}
@@ -304,6 +318,11 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file
*f, const char __user
if (r < 0)
return r;
+ if (!amdgpu_virt_can_access_debugfs(adev))
+ return -EINVAL;
+ else
+ amdgpu_virt_enable_access_debugfs(adev);
+
while (size) {
uint32_t value;
@@ -311,6 +330,7 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file
*f, const char __user
if (r) {
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
return r;
}
@@ -325,6 +345,7 @@ static ssize_t amdgpu_debugfs_regs_pcie_write(struct file
*f, const char __user
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
return result;
}
@@ -354,6 +375,11 @@ static ssize_t amdgpu_debugfs_regs_didt_read(struct file
*f, char __user *buf,
if (r < 0)
return r;
+ if (!amdgpu_virt_can_access_debugfs(adev))
+ return -EINVAL;
+ else
+ amdgpu_virt_enable_access_debugfs(adev);
+
while (size) {
uint32_t value;
@@ -362,6 +388,7 @@ static ssize_t amdgpu_debugfs_regs_didt_read(struct file
*f, char __user *buf,
if (r) {
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
+ amdgpu_virt_disable_access_debugfs(adev);
return r;
}
@@ -374,6 +401,7 @@ st
[PATCH] drm/amdgpu: skip access sdma_v5_0 registers under SRIOV
Due to the new L1.0b0c011b policy, many SDMA registers are blocked which raise
the violation warning. There are total 6 pair register needed to be skipped
when driver init and de-init.
mmSDMA0/1_CNTL
mmSDMA0/1_F32_CNTL
mmSDMA0/1_UTCL1_PAGE
mmSDMA0/1_UTCL1_CNTL
mmSDMA0/1_CHICKEN_BITS,
mmSDMA0/1_SEM_WAIT_FAIL_TIMER_CNTL
Signed-off-by: Yintian Tao
Change-Id: I9d5087582ceb5f629d37bf856533d00c179e6de3
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 110 +
1 file changed, 75 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index b3c30616d6b4..d7c0269059b0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -88,6 +88,29 @@ static const struct soc15_reg_golden
golden_settings_sdma_5[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_UTCL1_PAGE, 0x00ff,
0x000c5c00)
};
+static const struct soc15_reg_golden golden_settings_sdma_5_sriov[] = {
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC1_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC2_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC4_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC5_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC6_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC7_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_GFX_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_PAGE_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC0_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC1_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC2_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC4_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC5_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC6_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC7_RB_WPTR_POLL_CNTL,
0xfff7, 0x00403000),
+};
+
static const struct soc15_reg_golden golden_settings_sdma_nv10[] = {
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL,
0xfff0, 0x00403000),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA1_RLC3_RB_WPTR_POLL_CNTL,
0xfff0, 0x00403000),
@@ -141,9 +164,14 @@ static void sdma_v5_0_init_golden_registers(struct
amdgpu_device *adev)
(const
u32)ARRAY_SIZE(golden_settings_sdma_nv14));
break;
case CHIP_NAVI12:
- soc15_program_register_sequence(adev,
- golden_settings_sdma_5,
- (const
u32)ARRAY_SIZE(golden_settings_sdma_5));
+ if (amdgpu_sriov_vf(adev))
+ soc15_program_register_sequence(adev,
+
golden_settings_sdma_5_sriov,
+ (const
u32)ARRAY_SIZE(golden_settings_sdma_5_sriov));
+ else
+ soc15_program_register_sequence(adev,
+ golden_settings_sdma_5,
+ (const
u32)ARRAY_SIZE(golden_settings_sdma_5));
soc15_program_register_sequence(adev,
golden_settings_sdma_nv12,
(const
u32)ARRAY_SIZE(golden_settings_sdma_nv12));
@@ -557,9 +585,12 @@ static void sdma_v5_0_ctx_switch_enable(struct
amdgpu_device *adev, bool enable)
}
for (i = 0; i < adev->sdma.num_instances; i++) {
- f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_CNTL));
- f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
- AUTO_CTXSW_ENABLE, enable ? 1 : 0);
+ if (!amdgpu_sriov_vf(adev)) {
+ f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
mmSDMA
[PATCH] drm/amdgpu: hold the reference of finished fence
There is one one corner case at dma_fence_signal_locked which will raise the NULL pointer problem just like below. ->dma_fence_signal ->dma_fence_signal_locked ->test_and_set_bit here trigger dma_fence_release happen due to the zero of fence refcount. ->dma_fence_put ->dma_fence_release ->drm_sched_fence_release_scheduled ->call_rcu here make the union fled “cb_list” at finished fence to NULL because struct rcu_head contains two pointer which is same as struct list_head cb_list Therefore, to hold the reference of finished fence at drm_sched_process_job to prevent the null pointer during finished fence dma_fence_signal [ 732.912867] BUG: kernel NULL pointer dereference, address: 0008 [ 732.914815] #PF: supervisor write access in kernel mode [ 732.915731] #PF: error_code(0x0002) - not-present page [ 732.916621] PGD 0 P4D 0 [ 732.917072] Oops: 0002 [#1] SMP PTI [ 732.917682] CPU: 7 PID: 0 Comm: swapper/7 Tainted: G OE 5.4.0-rc7 #1 [ 732.918980] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.8.2-0-g33fbe13 by qemu-project.org 04/01/2014 [ 732.920906] RIP: 0010:dma_fence_signal_locked+0x3e/0x100 [ 732.938569] Call Trace: [ 732.939003] [ 732.939364] dma_fence_signal+0x29/0x50 [ 732.940036] drm_sched_fence_finished+0x12/0x20 [gpu_sched] [ 732.940996] drm_sched_process_job+0x34/0xa0 [gpu_sched] [ 732.941910] dma_fence_signal_locked+0x85/0x100 [ 732.942692] dma_fence_signal+0x29/0x50 [ 732.943457] amdgpu_fence_process+0x99/0x120 [amdgpu] [ 732.944393] sdma_v4_0_process_trap_irq+0x81/0xa0 [amdgpu] v2: hold the finished fence at drm_sched_process_job instead of amdgpu_fence_process v3: resume the blank line Signed-off-by: Yintian Tao --- drivers/gpu/drm/scheduler/sched_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c index a18eabf692e4..8e731ed0d9d9 100644 --- a/drivers/gpu/drm/scheduler/sched_main.c +++ b/drivers/gpu/drm/scheduler/sched_main.c @@ -651,7 +651,9 @@ static void drm_sched_process_job(struct dma_fence *f, struct dma_fence_cb *cb) trace_drm_sched_process_job(s_fence); + dma_fence_get(_fence->finished); drm_sched_fence_finished(s_fence); + dma_fence_put(_fence->finished); wake_up_interruptible(>wake_up_worker); } -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: hold the reference of finished fence
There is one one corner case at dma_fence_signal_locked
which will raise the NULL pointer problem just like below.
->dma_fence_signal
->dma_fence_signal_locked
->test_and_set_bit
here trigger dma_fence_release happen due to the zero of fence refcount.
->dma_fence_put
->dma_fence_release
->drm_sched_fence_release_scheduled
->call_rcu
here make the union fled “cb_list” at finished fence
to NULL because struct rcu_head contains two pointer
which is same as struct list_head cb_list
Therefore, to hold the reference of finished fence at drm_sched_process_job
to prevent the null pointer during finished fence dma_fence_signal
[ 732.912867] BUG: kernel NULL pointer dereference, address: 0008
[ 732.914815] #PF: supervisor write access in kernel mode
[ 732.915731] #PF: error_code(0x0002) - not-present page
[ 732.916621] PGD 0 P4D 0
[ 732.917072] Oops: 0002 [#1] SMP PTI
[ 732.917682] CPU: 7 PID: 0 Comm: swapper/7 Tainted: G OE
5.4.0-rc7 #1
[ 732.918980] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS
rel-1.8.2-0-g33fbe13 by qemu-project.org 04/01/2014
[ 732.920906] RIP: 0010:dma_fence_signal_locked+0x3e/0x100
[ 732.938569] Call Trace:
[ 732.939003]
[ 732.939364] dma_fence_signal+0x29/0x50
[ 732.940036] drm_sched_fence_finished+0x12/0x20 [gpu_sched]
[ 732.940996] drm_sched_process_job+0x34/0xa0 [gpu_sched]
[ 732.941910] dma_fence_signal_locked+0x85/0x100
[ 732.942692] dma_fence_signal+0x29/0x50
[ 732.943457] amdgpu_fence_process+0x99/0x120 [amdgpu]
[ 732.944393] sdma_v4_0_process_trap_irq+0x81/0xa0 [amdgpu]
v2: hold the finished fence at drm_sched_process_job instead of
amdgpu_fence_process
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1 -
drivers/gpu/drm/scheduler/sched_main.c| 2 ++
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 7531527067df..8570b9b9e0db 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -52,7 +52,6 @@
struct amdgpu_fence {
struct dma_fence base;
-
/* RB, DMA, etc. */
struct amdgpu_ring *ring;
};
diff --git a/drivers/gpu/drm/scheduler/sched_main.c
b/drivers/gpu/drm/scheduler/sched_main.c
index a18eabf692e4..8e731ed0d9d9 100644
--- a/drivers/gpu/drm/scheduler/sched_main.c
+++ b/drivers/gpu/drm/scheduler/sched_main.c
@@ -651,7 +651,9 @@ static void drm_sched_process_job(struct dma_fence *f,
struct dma_fence_cb *cb)
trace_drm_sched_process_job(s_fence);
+ dma_fence_get(_fence->finished);
drm_sched_fence_finished(s_fence);
+ dma_fence_put(_fence->finished);
wake_up_interruptible(>wake_up_worker);
}
--
2.17.1
___
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: hold the reference of finished fence
There is one one corner case at dma_fence_signal_locked
which will raise the NULL pointer problem just like below.
->dma_fence_signal
->dma_fence_signal_locked
->test_and_set_bit
here trigger dma_fence_release happen due to the zero of fence refcount.
->dma_fence_put
->dma_fence_release
->drm_sched_fence_release_scheduled
->call_rcu
here make the union fled “cb_list” at finished fence
to NULL because struct rcu_head contains two pointer
which is same as struct list_head cb_list
Therefore, to hold the reference of finished fence at amdgpu_job_run
to prevent the null pointer during dma_fence_signal
[ 732.912867] BUG: kernel NULL pointer dereference, address: 0008
[ 732.914815] #PF: supervisor write access in kernel mode
[ 732.915731] #PF: error_code(0x0002) - not-present page
[ 732.916621] PGD 0 P4D 0
[ 732.917072] Oops: 0002 [#1] SMP PTI
[ 732.917682] CPU: 7 PID: 0 Comm: swapper/7 Tainted: G OE
5.4.0-rc7 #1
[ 732.918980] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS
rel-1.8.2-0-g33fbe13 by qemu-project.org 04/01/2014
[ 732.920906] RIP: 0010:dma_fence_signal_locked+0x3e/0x100
[ 732.938569] Call Trace:
[ 732.939003]
[ 732.939364] dma_fence_signal+0x29/0x50
[ 732.940036] drm_sched_fence_finished+0x12/0x20 [gpu_sched]
[ 732.940996] drm_sched_process_job+0x34/0xa0 [gpu_sched]
[ 732.941910] dma_fence_signal_locked+0x85/0x100
[ 732.942692] dma_fence_signal+0x29/0x50
[ 732.943457] amdgpu_fence_process+0x99/0x120 [amdgpu]
[ 732.944393] sdma_v4_0_process_trap_irq+0x81/0xa0 [amdgpu]
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 19 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 3 +++
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index 7531527067df..03573eff660a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -52,7 +52,7 @@
struct amdgpu_fence {
struct dma_fence base;
-
+ struct dma_fence *finished;
/* RB, DMA, etc. */
struct amdgpu_ring *ring;
};
@@ -149,6 +149,7 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct
dma_fence **f,
seq = ++ring->fence_drv.sync_seq;
fence->ring = ring;
+ fence->finished = NULL;
dma_fence_init(>base, _fence_ops,
>fence_drv.lock,
adev->fence_context + ring->idx,
@@ -182,6 +183,21 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct
dma_fence **f,
return 0;
}
+void amdgpu_fence_get_finished(struct dma_fence *base,
+ struct dma_fence *finished)
+{
+ struct amdgpu_fence *afence = to_amdgpu_fence(base);
+
+ afence->finished = dma_fence_get(finished);
+}
+
+void amdgpu_fence_put_finished(struct dma_fence *base)
+{
+ struct amdgpu_fence *afence = to_amdgpu_fence(base);
+
+ dma_fence_put(afence->finished);
+}
+
/**
* amdgpu_fence_emit_polling - emit a fence on the requeste ring
*
@@ -276,6 +292,7 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring)
BUG();
dma_fence_put(fence);
+ amdgpu_fence_put_finished(fence);
pm_runtime_mark_last_busy(adev->ddev->dev);
pm_runtime_put_autosuspend(adev->ddev->dev);
} while (last_seq != seq);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 4981e443a884..deb2aeeadfb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -229,6 +229,8 @@ static struct dma_fence *amdgpu_job_run(struct
drm_sched_job *sched_job)
);
if (r)
DRM_ERROR("Error scheduling IBs (%d)\n", r);
+ else
+ amdgpu_fence_get_finished(fence, finished);
}
/* if gpu reset, hw fence will be replaced here */
dma_fence_put(job->fence);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 448c76cbf3ed..fd4da91859aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -96,6 +96,9 @@ void amdgpu_fence_driver_suspend(struct amdgpu_device *adev);
void amdgpu_fence_driver_resume(struct amdgpu_device *adev);
int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence,
unsigned flags);
+void amdgpu_fence_get_finished(struct dma_fence *base,
+ struct dma_fence *finished);
+void amdgpu_fence_put_finished(struct dma_fence *base);
int amdgpu_fence_emit_polling(struct amdgpu_ring
[PATCH] drm/amdgpu: miss PRT case when bo update
Originally, only the PTE valid is taken in consider.
The PRT case is missied when bo update which raise problem.
We need add condition for PRT case.
v2: add PRT condition for amdgpu_vm_bo_update_mapping, too
v3: fix one typo error
Signed-off-by: Yintian Tao
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 73398831196f..6157f6a9dcc8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1446,7 +1446,7 @@ static int amdgpu_vm_update_ptes(struct
amdgpu_vm_update_params *params,
uint64_t incr, entry_end, pe_start;
struct amdgpu_bo *pt;
- if (flags & AMDGPU_PTE_VALID) {
+ if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
/* make sure that the page tables covering the
* address range are actually allocated
*/
@@ -1603,7 +1603,7 @@ static int amdgpu_vm_bo_update_mapping(struct
amdgpu_device *adev,
goto error_unlock;
}
- if (flags & AMDGPU_PTE_VALID) {
+ if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
struct amdgpu_bo *root = vm->root.base.bo;
if (!dma_fence_is_signaled(vm->last_direct))
@@ -1718,7 +1718,7 @@ static int amdgpu_vm_bo_split_mapping(struct
amdgpu_device *adev,
AMDGPU_GPU_PAGES_IN_CPU_PAGE;
}
- } else if (flags & AMDGPU_PTE_VALID) {
+ } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
addr += bo_adev->vm_manager.vram_base_offset;
addr += pfn << PAGE_SHIFT;
}
--
2.17.1
___
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[PATCH] drm/amdgpu: miss PRT case when bo update
Originally, only the PTE valid is taken in consider.
The PRT case is missied when bo update which raise problem.
We need add condition for PRT case.
v2: add PRT condition for amdgpu_vm_bo_update_mapping, too
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 73398831196f..87e6085542f9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1446,7 +1446,7 @@ static int amdgpu_vm_update_ptes(struct
amdgpu_vm_update_params *params,
uint64_t incr, entry_end, pe_start;
struct amdgpu_bo *pt;
- if (flags & AMDGPU_PTE_VALID) {
+ if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
/* make sure that the page tables covering the
* address range are actually allocated
*/
@@ -1603,7 +1603,7 @@ static int amdgpu_vm_bo_update_mapping(struct
amdgpu_device *adev,
goto error_unlock;
}
- if (flags & AMDGPU_PTE_VALID) {
+ if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT) {
struct amdgpu_bo *root = vm->root.base.bo;
if (!dma_fence_is_signaled(vm->last_direct))
@@ -1718,7 +1718,7 @@ static int amdgpu_vm_bo_split_mapping(struct
amdgpu_device *adev,
AMDGPU_GPU_PAGES_IN_CPU_PAGE;
}
- } else if (flags & AMDGPU_PTE_VALID) {
+ } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
addr += bo_adev->vm_manager.vram_base_offset;
addr += pfn << PAGE_SHIFT;
}
--
2.17.1
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[PATCH] drm/amdgpu: miss PRT case when bo update
Originally, only the PTE valid is taken in consider.
The PRT case is missied when bo update which raise problem.
We need add condition for PRT case.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 73398831196f..7a3e4514a00c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1446,7 +1446,7 @@ static int amdgpu_vm_update_ptes(struct
amdgpu_vm_update_params *params,
uint64_t incr, entry_end, pe_start;
struct amdgpu_bo *pt;
- if (flags & AMDGPU_PTE_VALID) {
+ if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
/* make sure that the page tables covering the
* address range are actually allocated
*/
@@ -1605,7 +1605,6 @@ static int amdgpu_vm_bo_update_mapping(struct
amdgpu_device *adev,
if (flags & AMDGPU_PTE_VALID) {
struct amdgpu_bo *root = vm->root.base.bo;
-
if (!dma_fence_is_signaled(vm->last_direct))
amdgpu_bo_fence(root, vm->last_direct, true);
@@ -1718,7 +1717,7 @@ static int amdgpu_vm_bo_split_mapping(struct
amdgpu_device *adev,
AMDGPU_GPU_PAGES_IN_CPU_PAGE;
}
- } else if (flags & AMDGPU_PTE_VALID) {
+ } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
addr += bo_adev->vm_manager.vram_base_offset;
addr += pfn << PAGE_SHIFT;
}
--
2.17.1
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[PATCH] drm/amdgpu: clean wptr on wb when gpu recovery
The TDR will be randomly failed due to compute ring
test failure. If the compute ring wptr & 0x7ff(ring_buf_mask)
is 0x100 then after map mqd the compute ring rptr will be
synced with 0x100. And the ring test packet size is also 0x100.
Then after invocation of amdgpu_ring_commit, the cp will not
really handle the packet on the ring buffer because rptr is equal to wptr.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 44f00ecea322..5df1a6d45457 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3508,6 +3508,7 @@ static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring
*ring)
/* reset ring buffer */
ring->wptr = 0;
+ atomic64_set((atomic64_t *)>wb.wb[ring->wptr_offs], 0);
amdgpu_ring_clear_ring(ring);
} else {
amdgpu_ring_clear_ring(ring);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 4135e4126e82..ac22490e8656 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3664,6 +3664,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring
*ring)
/* reset ring buffer */
ring->wptr = 0;
+ atomic64_set((atomic64_t *)>wb.wb[ring->wptr_offs], 0);
amdgpu_ring_clear_ring(ring);
} else {
amdgpu_ring_clear_ring(ring);
--
2.17.1
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[PATCH] drm/amdgpu: release drm_device after amdgpu_driver_unload_kms
If we release drm_device before amdgpu_driver_unload_kms,
then it will raise the error below. Therefore, we need to
place it before amdgpu_driver_unload_kms.
[ 43.055736] Memory manager not clean during takedown.
[ 43.055777] WARNING: CPU: 1 PID: 2807 at
/build/linux-hwe-9KJ07q/linux-hwe-4.18.0/drivers/gpu/drm/drm_mm.c:913
drm_mm_takedown+0x24/0x30 [drm]
[ 43.055778] Modules linked in: amdgpu(OE-) amd_sched(OE) amdttm(OE)
amdkcl(OE) amd_iommu_v2 drm_kms_helper drm i2c_algo_bit fb_sys_fops syscopyarea
sysfillrect sysimgblt snd_hda_codec_generic nfit kvm_intel kvm irqbypass
crct10dif_pclmul crc32_pclmul snd_hda_intel snd_hda_codec snd_hda_core
snd_hwdep snd_pcm ghash_clmulni_intel snd_seq_midi snd_seq_midi_event pcbc
snd_rawmidi snd_seq snd_seq_device aesni_intel snd_timer joydev aes_x86_64
crypto_simd cryptd glue_helper snd soundcore input_leds mac_hid serio_raw
qemu_fw_cfg binfmt_misc sch_fq_codel nfsd auth_rpcgss nfs_acl lockd grace
sunrpc parport_pc ppdev lp parport ip_tables x_tables autofs4 hid_generic
floppy usbhid psmouse hid i2c_piix4 e1000 pata_acpi
[ 43.055819] CPU: 1 PID: 2807 Comm: modprobe Tainted: G OE
4.18.0-15-generic #16~18.04.1-Ubuntu
[ 43.055820] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS
1.12.0-1 04/01/2014
[ 43.055830] RIP: 0010:drm_mm_takedown+0x24/0x30 [drm]
[ 43.055831] Code: 84 00 00 00 00 00 0f 1f 44 00 00 48 8b 47 38 48 83 c7 38
48 39 c7 75 02 f3 c3 55 48 c7 c7 38 33 80 c0 48 89 e5 e8 1c 41 ec d0 <0f> 0b 5d
c3 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55 48 89 e5 41
[ 43.055857] RSP: 0018:ae33c1393d28 EFLAGS: 00010286
[ 43.055859] RAX: RBX: 9651b4a29800 RCX: 0006
[ 43.055860] RDX: 0007 RSI: 0096 RDI: 9651bfc964b0
[ 43.055861] RBP: ae33c1393d28 R08: 02a6 R09: 0004
[ 43.055861] R10: ae33c1393d20 R11: 0001 R12: 9651ba6cb000
[ 43.055863] R13: 9651b7f4 R14: c0de3a10 R15: 9651ba5c6460
[ 43.055864] FS: 7f1d3c08d540() GS:9651bfc8()
knlGS:
[ 43.055865] CS: 0010 DS: ES: CR0: 80050033
[ 43.055866] CR2: 5630a5831640 CR3: 00012e274004 CR4: 003606e0
[ 43.055870] DR0: DR1: DR2:
[ 43.055871] DR3: DR6: fffe0ff0 DR7: 0400
[ 43.055871] Call Trace:
[ 43.055885] drm_vma_offset_manager_destroy+0x1b/0x30 [drm]
[ 43.055894] drm_gem_destroy+0x19/0x40 [drm]
[ 43.055903] drm_dev_fini+0x7f/0x90 [drm]
[ 43.055911] drm_dev_release+0x2b/0x40 [drm]
[ 43.055919] drm_dev_unplug+0x64/0x80 [drm]
[ 43.055994] amdgpu_pci_remove+0x39/0x70 [amdgpu]
[ 43.055998] pci_device_remove+0x3e/0xc0
[ 43.056001] device_release_driver_internal+0x18a/0x260
[ 43.056003] driver_detach+0x3f/0x80
[ 43.056004] bus_remove_driver+0x59/0xd0
[ 43.056006] driver_unregister+0x2c/0x40
[ 43.056008] pci_unregister_driver+0x22/0xa0
[ 43.056087] amdgpu_exit+0x15/0x57c [amdgpu]
[ 43.056090] __x64_sys_delete_module+0x146/0x280
[ 43.056094] do_syscall_64+0x5a/0x120
v2: put drm_dev_put after pci_set_drvdata
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 02d80b9dbfe1..bec4337156a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1138,10 +1138,10 @@ amdgpu_pci_remove(struct pci_dev *pdev)
#endif
DRM_ERROR("Hotplug removal is not supported\n");
drm_dev_unplug(dev);
- drm_dev_put(dev);
amdgpu_driver_unload_kms(dev);
pci_disable_device(pdev);
pci_set_drvdata(pdev, NULL);
+ drm_dev_put(dev);
}
static void
--
2.17.1
___
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[PATCH] drm/amdgpu: miss to remove pp_sclk file
Miss to remove pp_sclk file Signed-off-by: Yintian Tao --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c index 9deff8cc9723..a43fc1c8ffd0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -3471,6 +3471,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev) device_remove_file(adev->dev, _attr_pp_cur_state); device_remove_file(adev->dev, _attr_pp_force_state); device_remove_file(adev->dev, _attr_pp_table); + device_remove_file(adev->dev, _attr_pp_sclk); device_remove_file(adev->dev, _attr_pp_dpm_sclk); device_remove_file(adev->dev, _attr_pp_dpm_mclk); -- 2.17.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: no need to clean debugfs at amdgpu
drm_minor_unregister will invoke drm_debugfs_cleanup
to clean all the child node under primary minor node.
We don't need to invoke amdgpu_debugfs_fini and
amdgpu_debugfs_regs_cleanup to clean agian.
Otherwise, it will raise the NULL pointer like below.
[ 45.046029] BUG: unable to handle kernel NULL pointer dereference at
00a8
[ 45.047256] PGD 0 P4D 0
[ 45.047713] Oops: 0002 [#1] SMP PTI
[ 45.048198] CPU: 0 PID: 2796 Comm: modprobe Tainted: GW OE
4.18.0-15-generic #16~18.04.1-Ubuntu
[ 45.049538] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS
1.12.0-1 04/01/2014
[ 45.050651] RIP: 0010:down_write+0x1f/0x40
[ 45.051194] Code: 90 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55 48 89
e5 53 48 89 fb e8 ce d9 ff ff 48 ba 01 00 00 00 ff ff ff ff 48 89 d8 48 0f
c1 10 85 d2 74 05 e8 53 1c ff ff 65 48 8b 04 25 00 5c 01
[ 45.053702] RSP: 0018:ad8f4133fd40 EFLAGS: 00010246
[ 45.054384] RAX: 00a8 RBX: 00a8 RCX: a011327dd814
[ 45.055349] RDX: 0001 RSI: 0001 RDI: 00a8
[ 45.056346] RBP: ad8f4133fd48 R08: R09: c0690a00
[ 45.057326] R10: ad8f4133fd58 R11: 0001 R12: a0113cff0300
[ 45.058266] R13: a0113c0a R14: c0c02a10 R15: a0113e5c7860
[ 45.059221] FS: 7f60d46f9540() GS:a0113fc0()
knlGS:
[ 45.060809] CS: 0010 DS: ES: CR0: 80050033
[ 45.061826] CR2: 00a8 CR3: 000136250004 CR4: 003606f0
[ 45.062913] DR0: DR1: DR2:
[ 45.064404] DR3: DR6: fffe0ff0 DR7: 0400
[ 45.065897] Call Trace:
[ 45.066426] debugfs_remove+0x36/0xa0
[ 45.067131] amdgpu_debugfs_ring_fini+0x15/0x20 [amdgpu]
[ 45.068019] amdgpu_debugfs_fini+0x2c/0x50 [amdgpu]
[ 45.068756] amdgpu_pci_remove+0x49/0x70 [amdgpu]
[ 45.069439] pci_device_remove+0x3e/0xc0
[ 45.070037] device_release_driver_internal+0x18a/0x260
[ 45.070842] driver_detach+0x3f/0x80
[ 45.071325] bus_remove_driver+0x59/0xd0
[ 45.071850] driver_unregister+0x2c/0x40
[ 45.072377] pci_unregister_driver+0x22/0xa0
[ 45.073043] amdgpu_exit+0x15/0x57c [amdgpu]
[ 45.073683] __x64_sys_delete_module+0x146/0x280
[ 45.074369] do_syscall_64+0x5a/0x120
[ 45.074916] entry_SYSCALL_64_after_hwframe+0x44/0xa9
v2: remove all debugfs cleanup/fini code at amdgpu
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 30 -
drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c| 7 -
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 10 ---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 -
7 files changed, 51 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
index 3bb74056b9d2..abc148280ba5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
@@ -992,18 +992,6 @@ int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
return 0;
}
-void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
-{
- unsigned i;
-
- for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
- if (adev->debugfs_regs[i]) {
- debugfs_remove(adev->debugfs_regs[i]);
- adev->debugfs_regs[i] = NULL;
- }
- }
-}
-
static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
{
struct drm_info_node *node = (struct drm_info_node *) m->private;
@@ -1339,31 +1327,13 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev)
ARRAY_SIZE(amdgpu_debugfs_list));
}
-void amdgpu_debugfs_fini(struct amdgpu_device *adev)
-{
- int i;
-
- for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
- struct amdgpu_ring *ring = adev->rings[i];
-
- if (!ring)
- continue;
-
- amdgpu_debugfs_ring_fini(ring);
- }
- amdgpu_ttm_debugfs_fini(adev);
- debugfs_remove(adev->debugfs_preempt);
-}
-
#else
int amdgpu_debugfs_init(struct amdgpu_device *adev)
{
return 0;
}
-void amdgpu_debugfs_fini(struct amdgpu_device *adev) { }
int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
{
return 0;
}
-void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h
index b382527e359a..de12d1101526 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h
@@ -32,7 +32,6 @@ struct amdgpu_debugfs {
};
int amdgpu_debugfs_regs_init(st
[PATCH] drm/amdgpu: release drm_device after amdgpu_driver_unload_kms
If we release drm_device before amdgpu_driver_unload_kms,
then it will raise the error below. Therefore, we need to
place it before amdgpu_driver_unload_kms.
[ 43.055736] Memory manager not clean during takedown.
[ 43.055777] WARNING: CPU: 1 PID: 2807 at
/build/linux-hwe-9KJ07q/linux-hwe-4.18.0/drivers/gpu/drm/drm_mm.c:913
drm_mm_takedown+0x24/0x30 [drm]
[ 43.055778] Modules linked in: amdgpu(OE-) amd_sched(OE) amdttm(OE)
amdkcl(OE) amd_iommu_v2 drm_kms_helper drm i2c_algo_bit fb_sys_fops syscopyarea
sysfillrect sysimgblt snd_hda_codec_generic nfit kvm_intel kvm irqbypass
crct10dif_pclmul crc32_pclmul snd_hda_intel snd_hda_codec snd_hda_core
snd_hwdep snd_pcm ghash_clmulni_intel snd_seq_midi snd_seq_midi_event pcbc
snd_rawmidi snd_seq snd_seq_device aesni_intel snd_timer joydev aes_x86_64
crypto_simd cryptd glue_helper snd soundcore input_leds mac_hid serio_raw
qemu_fw_cfg binfmt_misc sch_fq_codel nfsd auth_rpcgss nfs_acl lockd grace
sunrpc parport_pc ppdev lp parport ip_tables x_tables autofs4 hid_generic
floppy usbhid psmouse hid i2c_piix4 e1000 pata_acpi
[ 43.055819] CPU: 1 PID: 2807 Comm: modprobe Tainted: G OE
4.18.0-15-generic #16~18.04.1-Ubuntu
[ 43.055820] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS
1.12.0-1 04/01/2014
[ 43.055830] RIP: 0010:drm_mm_takedown+0x24/0x30 [drm]
[ 43.055831] Code: 84 00 00 00 00 00 0f 1f 44 00 00 48 8b 47 38 48 83 c7 38
48 39 c7 75 02 f3 c3 55 48 c7 c7 38 33 80 c0 48 89 e5 e8 1c 41 ec d0 <0f> 0b 5d
c3 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55 48 89 e5 41
[ 43.055857] RSP: 0018:ae33c1393d28 EFLAGS: 00010286
[ 43.055859] RAX: RBX: 9651b4a29800 RCX: 0006
[ 43.055860] RDX: 0007 RSI: 0096 RDI: 9651bfc964b0
[ 43.055861] RBP: ae33c1393d28 R08: 02a6 R09: 0004
[ 43.055861] R10: ae33c1393d20 R11: 0001 R12: 9651ba6cb000
[ 43.055863] R13: 9651b7f4 R14: c0de3a10 R15: 9651ba5c6460
[ 43.055864] FS: 7f1d3c08d540() GS:9651bfc8()
knlGS:
[ 43.055865] CS: 0010 DS: ES: CR0: 80050033
[ 43.055866] CR2: 5630a5831640 CR3: 00012e274004 CR4: 003606e0
[ 43.055870] DR0: DR1: DR2:
[ 43.055871] DR3: DR6: fffe0ff0 DR7: 0400
[ 43.055871] Call Trace:
[ 43.055885] drm_vma_offset_manager_destroy+0x1b/0x30 [drm]
[ 43.055894] drm_gem_destroy+0x19/0x40 [drm]
[ 43.055903] drm_dev_fini+0x7f/0x90 [drm]
[ 43.055911] drm_dev_release+0x2b/0x40 [drm]
[ 43.055919] drm_dev_unplug+0x64/0x80 [drm]
[ 43.055994] amdgpu_pci_remove+0x39/0x70 [amdgpu]
[ 43.055998] pci_device_remove+0x3e/0xc0
[ 43.056001] device_release_driver_internal+0x18a/0x260
[ 43.056003] driver_detach+0x3f/0x80
[ 43.056004] bus_remove_driver+0x59/0xd0
[ 43.056006] driver_unregister+0x2c/0x40
[ 43.056008] pci_unregister_driver+0x22/0xa0
[ 43.056087] amdgpu_exit+0x15/0x57c [amdgpu]
[ 43.056090] __x64_sys_delete_module+0x146/0x280
[ 43.056094] do_syscall_64+0x5a/0x120
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 02d80b9dbfe1..01a1082b5cab 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1138,8 +1138,8 @@ amdgpu_pci_remove(struct pci_dev *pdev)
#endif
DRM_ERROR("Hotplug removal is not supported\n");
drm_dev_unplug(dev);
- drm_dev_put(dev);
amdgpu_driver_unload_kms(dev);
+ drm_dev_put(dev);
pci_disable_device(pdev);
pci_set_drvdata(pdev, NULL);
}
--
2.17.1
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[PATCH] drm/amdgpu: no need to clean debugfs at amdgpu
drm_minor_unregister will invoke drm_debugfs_cleanup
to clean all the child node under primary minor node.
We don't need to invoke amdgpu_debugfs_fini and
amdgpu_debugfs_regs_cleanup to clean agian.
Otherwise, it will raise the NULL pointer like below.
[ 45.046029] BUG: unable to handle kernel NULL pointer dereference at
00a8
[ 45.047256] PGD 0 P4D 0
[ 45.047713] Oops: 0002 [#1] SMP PTI
[ 45.048198] CPU: 0 PID: 2796 Comm: modprobe Tainted: GW OE
4.18.0-15-generic #16~18.04.1-Ubuntu
[ 45.049538] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS
1.12.0-1 04/01/2014
[ 45.050651] RIP: 0010:down_write+0x1f/0x40
[ 45.051194] Code: 90 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55 48 89
e5 53 48 89 fb e8 ce d9 ff ff 48 ba 01 00 00 00 ff ff ff ff 48 89 d8 48 0f
c1 10 85 d2 74 05 e8 53 1c ff ff 65 48 8b 04 25 00 5c 01
[ 45.053702] RSP: 0018:ad8f4133fd40 EFLAGS: 00010246
[ 45.054384] RAX: 00a8 RBX: 00a8 RCX: a011327dd814
[ 45.055349] RDX: 0001 RSI: 0001 RDI: 00a8
[ 45.056346] RBP: ad8f4133fd48 R08: R09: c0690a00
[ 45.057326] R10: ad8f4133fd58 R11: 0001 R12: a0113cff0300
[ 45.058266] R13: a0113c0a R14: c0c02a10 R15: a0113e5c7860
[ 45.059221] FS: 7f60d46f9540() GS:a0113fc0()
knlGS:
[ 45.060809] CS: 0010 DS: ES: CR0: 80050033
[ 45.061826] CR2: 00a8 CR3: 000136250004 CR4: 003606f0
[ 45.062913] DR0: DR1: DR2:
[ 45.064404] DR3: DR6: fffe0ff0 DR7: 0400
[ 45.065897] Call Trace:
[ 45.066426] debugfs_remove+0x36/0xa0
[ 45.067131] amdgpu_debugfs_ring_fini+0x15/0x20 [amdgpu]
[ 45.068019] amdgpu_debugfs_fini+0x2c/0x50 [amdgpu]
[ 45.068756] amdgpu_pci_remove+0x49/0x70 [amdgpu]
[ 45.069439] pci_device_remove+0x3e/0xc0
[ 45.070037] device_release_driver_internal+0x18a/0x260
[ 45.070842] driver_detach+0x3f/0x80
[ 45.071325] bus_remove_driver+0x59/0xd0
[ 45.071850] driver_unregister+0x2c/0x40
[ 45.072377] pci_unregister_driver+0x22/0xa0
[ 45.073043] amdgpu_exit+0x15/0x57c [amdgpu]
[ 45.073683] __x64_sys_delete_module+0x146/0x280
[ 45.074369] do_syscall_64+0x5a/0x120
[ 45.074916] entry_SYSCALL_64_after_hwframe+0x44/0xa9
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c| 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 8ef8a49b9255..351096ab4301 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3237,7 +3237,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
- amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count);
if (adev->ucode_sysfs_en)
amdgpu_ucode_sysfs_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 7cf5f597b90a..02d80b9dbfe1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -1139,7 +1139,6 @@ amdgpu_pci_remove(struct pci_dev *pdev)
DRM_ERROR("Hotplug removal is not supported\n");
drm_dev_unplug(dev);
drm_dev_put(dev);
- amdgpu_debugfs_fini(adev);
amdgpu_driver_unload_kms(dev);
pci_disable_device(pdev);
pci_set_drvdata(pdev, NULL);
--
2.17.1
___
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[PATCH] drm/amd/powerplay: skip disable dynamic state management
Under sriov, the disable operation is no allowed.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 253860d30b20..9454ab50f9a1 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -99,6 +99,9 @@ int phm_disable_dynamic_state_management(struct pp_hwmgr
*hwmgr)
PHM_FUNC_CHECK(hwmgr);
+ if (!hwmgr->not_vf)
+ return 0;
+
if (!smum_is_dpm_running(hwmgr)) {
pr_info("dpm has been disabled\n");
return 0;
--
2.17.1
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[PATCH] drm/amd/powerplay: skip soc clk setting under pp one vf
Under sriov pp one vf mode, there is no need to set
soc clk under pp one vf because smu firmware will depend
on the mclk to set the appropriate soc clk for it.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 148446570e21..92a65e3daff4 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3538,7 +3538,8 @@ static int vega10_upload_dpm_bootup_level(struct pp_hwmgr
*hwmgr)
if (!data->registry_data.mclk_dpm_key_disabled) {
if (data->smc_state_table.mem_boot_level !=
data->dpm_table.mem_table.dpm_state.soft_min_level) {
- if (data->smc_state_table.mem_boot_level ==
NUM_UCLK_DPM_LEVELS - 1) {
+ if ((data->smc_state_table.mem_boot_level ==
NUM_UCLK_DPM_LEVELS - 1)
+ && hwmgr->not_vf) {
socclk_idx =
vega10_get_soc_index_for_max_uclk(hwmgr);
smum_send_msg_to_smc_with_parameter(hwmgr,
PPSMC_MSG_SetSoftMinSocclkByIndex,
--
2.17.1
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[PATCH] drm/amd/powerplay: enable pp one vf mode for vega10
Originally, due to the restriction from PSP and SMU, VF has
to send message to hypervisor driver to handle powerplay
change which is complicated and redundant. Currently, SMU
and PSP can support VF to directly handle powerplay
change by itself. Therefore, the old code about the handshake
between VF and PF to handle powerplay will be removed and VF
will use new the registers below to handshake with SMU.
mmMP1_SMN_C2PMSG_101: register to handle SMU message
mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
mmMP1_SMN_C2PMSG_103: register to handle SMU response
v2: remove module parameter pp_one_vf
v3: fix the parens
v4: forbid vf to change smu feature
v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute
v6: change skip condition at vega10_copy_table_to_smc
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 16 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 -
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 182 --
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 51 -
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 14 +-
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 78
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 4 -
drivers/gpu/drm/amd/amdgpu/soc15.c| 8 +-
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 4 +-
.../drm/amd/powerplay/hwmgr/hardwaremanager.c | 15 +-
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 16 ++
drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c | 30 +--
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 156 ++-
.../amd/powerplay/hwmgr/vega10_powertune.c| 3 +
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
.../drm/amd/powerplay/smumgr/smu9_smumgr.c| 56 --
.../drm/amd/powerplay/smumgr/vega10_smumgr.c | 14 ++
17 files changed, 352 insertions(+), 300 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7324a5fc5ccb..47b4f359f07c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
}
}
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_virt_init_data_exchange(adev);
+
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r);
@@ -1921,11 +1924,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
amdgpu_amdkfd_device_init(adev);
init_failed:
- if (amdgpu_sriov_vf(adev)) {
- if (!r)
- amdgpu_virt_init_data_exchange(adev);
+ if (amdgpu_sriov_vf(adev))
amdgpu_virt_release_full_gpu(adev, true);
- }
return r;
}
@@ -2825,7 +2825,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
- mutex_init(>virt.dpm_mutex);
mutex_init(>psp.mutex);
r = amdgpu_device_check_arguments(adev);
@@ -3044,9 +3043,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
amdgpu_fbdev_init(adev);
- if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
- amdgpu_pm_virt_sysfs_init(adev);
-
r = amdgpu_pm_sysfs_init(adev);
if (r) {
adev->pm_sysfs_en = false;
@@ -3191,8 +3187,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
- if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
- amdgpu_pm_virt_sysfs_fini(adev);
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count);
@@ -3673,6 +3667,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device
*adev,
if (r)
goto error;
+ amdgpu_virt_init_data_exchange(adev);
/* we need recover gart prior to run SMC/CP/SDMA resume */
amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
@@ -3690,7 +3685,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device
*adev,
amdgpu_amdkfd_post_reset(adev);
error:
- amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
amdgpu_inc_vram_lost(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5ec1415d1755..3a0ea9096498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -703,10 +703,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
if (adev->pm.dpm_enabled) {
[PATCH] drm/amd/powerplay: enable pp one vf mode for vega10
Originally, due to the restriction from PSP and SMU, VF has
to send message to hypervisor driver to handle powerplay
change which is complicated and redundant. Currently, SMU
and PSP can support VF to directly handle powerplay
change by itself. Therefore, the old code about the handshake
between VF and PF to handle powerplay will be removed and VF
will use new the registers below to handshake with SMU.
mmMP1_SMN_C2PMSG_101: register to handle SMU message
mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
mmMP1_SMN_C2PMSG_103: register to handle SMU response
v2: remove module parameter pp_one_vf
v3: fix the parens
v4: forbid vf to change smu feature
v5: use hwmon_attributes_visible to skip sepicified hwmon atrribute
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 16 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 -
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 182 --
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 51 -
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 14 +-
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 78
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 4 -
drivers/gpu/drm/amd/amdgpu/soc15.c| 8 +-
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 4 +-
.../drm/amd/powerplay/hwmgr/hardwaremanager.c | 15 +-
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 16 ++
drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c | 30 +--
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 156 ++-
.../amd/powerplay/hwmgr/vega10_powertune.c| 3 +
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
.../drm/amd/powerplay/smumgr/smu9_smumgr.c| 56 --
.../drm/amd/powerplay/smumgr/vega10_smumgr.c | 14 ++
17 files changed, 352 insertions(+), 300 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7324a5fc5ccb..47b4f359f07c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
}
}
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_virt_init_data_exchange(adev);
+
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r);
@@ -1921,11 +1924,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
amdgpu_amdkfd_device_init(adev);
init_failed:
- if (amdgpu_sriov_vf(adev)) {
- if (!r)
- amdgpu_virt_init_data_exchange(adev);
+ if (amdgpu_sriov_vf(adev))
amdgpu_virt_release_full_gpu(adev, true);
- }
return r;
}
@@ -2825,7 +2825,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
- mutex_init(>virt.dpm_mutex);
mutex_init(>psp.mutex);
r = amdgpu_device_check_arguments(adev);
@@ -3044,9 +3043,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
amdgpu_fbdev_init(adev);
- if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
- amdgpu_pm_virt_sysfs_init(adev);
-
r = amdgpu_pm_sysfs_init(adev);
if (r) {
adev->pm_sysfs_en = false;
@@ -3191,8 +3187,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
- if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
- amdgpu_pm_virt_sysfs_fini(adev);
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count);
@@ -3673,6 +3667,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device
*adev,
if (r)
goto error;
+ amdgpu_virt_init_data_exchange(adev);
/* we need recover gart prior to run SMC/CP/SDMA resume */
amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
@@ -3690,7 +3685,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device
*adev,
amdgpu_amdkfd_post_reset(adev);
error:
- amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
amdgpu_inc_vram_lost(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5ec1415d1755..3a0ea9096498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -703,10 +703,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
if (adev->pm.dpm_enabled) {
dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev,
false)
[PATCH] drm/amd/powerplay: enable pp one vf mode for vega10
Originally, due to the restriction from PSP and SMU, VF has
to send message to hypervisor driver to handle powerplay
change which is complicated and redundant. Currently, SMU
and PSP can support VF to directly handle powerplay
change by itself. Therefore, the old code about the handshake
between VF and PF to handle powerplay will be removed and VF
will use new the registers below to handshake with SMU.
mmMP1_SMN_C2PMSG_101: register to handle SMU message
mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
mmMP1_SMN_C2PMSG_103: register to handle SMU response
v2: remove module parameter pp_one_vf
v3: fix the parens
v4: forbid vf to change smu feature
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 16 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 -
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 235 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 51
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 14 +-
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 78 --
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 4 -
drivers/gpu/drm/amd/amdgpu/soc15.c| 8 +-
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 4 +-
.../drm/amd/powerplay/hwmgr/hardwaremanager.c | 15 +-
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 16 ++
drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c | 30 +--
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 162
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
.../drm/amd/powerplay/smumgr/smu9_smumgr.c| 56 -
.../drm/amd/powerplay/smumgr/vega10_smumgr.c | 14 ++
16 files changed, 406 insertions(+), 302 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b9ca7e728d3e..465156a12d88 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
}
}
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_virt_init_data_exchange(adev);
+
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r);
@@ -1921,11 +1924,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
amdgpu_amdkfd_device_init(adev);
init_failed:
- if (amdgpu_sriov_vf(adev)) {
- if (!r)
- amdgpu_virt_init_data_exchange(adev);
+ if (amdgpu_sriov_vf(adev))
amdgpu_virt_release_full_gpu(adev, true);
- }
return r;
}
@@ -2819,7 +2819,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
- mutex_init(>virt.dpm_mutex);
mutex_init(>psp.mutex);
r = amdgpu_device_check_arguments(adev);
@@ -3040,9 +3039,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
amdgpu_fbdev_init(adev);
- if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
- amdgpu_pm_virt_sysfs_init(adev);
-
r = amdgpu_pm_sysfs_init(adev);
if (r) {
adev->pm_sysfs_en = false;
@@ -3187,8 +3183,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
- if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
- amdgpu_pm_virt_sysfs_fini(adev);
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count);
@@ -3669,6 +3663,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device
*adev,
if (r)
goto error;
+ amdgpu_virt_init_data_exchange(adev);
/* we need recover gart prior to run SMC/CP/SDMA resume */
amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
@@ -3686,7 +3681,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device
*adev,
amdgpu_amdkfd_post_reset(adev);
error:
- amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
amdgpu_inc_vram_lost(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5ec1415d1755..3a0ea9096498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -703,10 +703,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
if (adev->pm.dpm_enabled) {
dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev,
false) * 10;
dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev,
false) * 10;
- } else if (amdgp
[PATCH] drm/amd/powerplay: avoid null pointer
because some asics have no smu.ppt_funcs
we need add one check for it otherwise
it will raise null pointer problem.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index a21ee035ca57..b8a42ebb2f5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -160,7 +160,8 @@ static ssize_t amdgpu_get_dpm_state(struct device *dev,
enum amd_pm_state_type pm;
if (is_support_sw_smu(adev)) {
- if (adev->smu.ppt_funcs->get_current_power_state)
+ if (adev->smu.ppt_funcs &&
+ adev->smu.ppt_funcs->get_current_power_state)
pm = smu_get_current_power_state(>smu);
else
pm = adev->pm.dpm.user_state;
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/powerplay: enable pp one vf mode for vega10
Originally, due to the restriction from PSP and SMU, VF has
to send message to hypervisor driver to handle powerplay
change which is complicated and redundant. Currently, SMU
and PSP can support VF to directly handle powerplay
change by itself. Therefore, the old code about the handshake
between VF and PF to handle powerplay will be removed and VF
will use new the registers below to handshake with SMU.
mmMP1_SMN_C2PMSG_101: register to handle SMU message
mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
mmMP1_SMN_C2PMSG_103: register to handle SMU response
v2: remove module parameter pp_one_vf
v3: separte one fix into another patch and fix the parens
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 13 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 -
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 118 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 51 --
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 14 +-
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 78 -
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 4 -
drivers/gpu/drm/amd/amdgpu/soc15.c| 8 +-
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 4 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 24 +--
.../drm/amd/powerplay/hwmgr/hardwaremanager.c | 15 +-
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 7 +
drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c | 30 ++--
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 157 --
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
.../drm/amd/powerplay/smumgr/smu9_smumgr.c| 56 +--
.../drm/amd/powerplay/smumgr/vega10_smumgr.c | 6 +
17 files changed, 279 insertions(+), 311 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b9ca7e728d3e..30eb42593a20 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
}
}
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_virt_init_data_exchange(adev);
+
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r);
@@ -1922,8 +1925,6 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
init_failed:
if (amdgpu_sriov_vf(adev)) {
- if (!r)
- amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
}
@@ -2819,7 +2820,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
- mutex_init(>virt.dpm_mutex);
mutex_init(>psp.mutex);
r = amdgpu_device_check_arguments(adev);
@@ -3040,9 +3040,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
amdgpu_fbdev_init(adev);
- if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
- amdgpu_pm_virt_sysfs_init(adev);
-
r = amdgpu_pm_sysfs_init(adev);
if (r) {
adev->pm_sysfs_en = false;
@@ -3187,8 +3184,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
- if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
- amdgpu_pm_virt_sysfs_fini(adev);
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count);
@@ -3669,6 +3664,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device
*adev,
if (r)
goto error;
+ amdgpu_virt_init_data_exchange(adev);
/* we need recover gart prior to run SMC/CP/SDMA resume */
amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
@@ -3686,7 +3682,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device
*adev,
amdgpu_amdkfd_post_reset(adev);
error:
- amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
amdgpu_inc_vram_lost(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5ec1415d1755..3a0ea9096498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -703,10 +703,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
if (adev->pm.dpm_enabled) {
dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev,
false) * 10;
dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev,
false) * 10;
- } else if (amdgpu_sriov_vf(adev) &
[PATCH] drm/amd/powerplay: enable pp one vf mode for vega10
Originally, due to the restriction from PSP and SMU, VF has
to send message to hypervisor driver to handle powerplay
change which is complicated and redundant. Currently, SMU
and PSP can support VF to directly handle powerplay
change by itself. Therefore, the old code about the handshake
between VF and PF to handle powerplay will be removed and VF
will use new the registers below to handshake with SMU.
mmMP1_SMN_C2PMSG_101: register to handle SMU message
mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
mmMP1_SMN_C2PMSG_103: register to handle SMU response
v2: remove module parameter pp_one_vf
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 13 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 -
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 121 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 51 --
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 14 +-
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 78 -
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 4 -
drivers/gpu/drm/amd/amdgpu/soc15.c| 8 +-
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 4 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 24 +--
.../drm/amd/powerplay/hwmgr/hardwaremanager.c | 15 +-
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 7 +
drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c | 30 ++--
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 157 --
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
.../drm/amd/powerplay/smumgr/smu9_smumgr.c| 55 --
.../drm/amd/powerplay/smumgr/vega10_smumgr.c | 6 +
17 files changed, 280 insertions(+), 312 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b9ca7e728d3e..30eb42593a20 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1880,6 +1880,9 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
}
}
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_virt_init_data_exchange(adev);
+
r = amdgpu_ib_pool_init(adev);
if (r) {
dev_err(adev->dev, "IB initialization failed (%d).\n", r);
@@ -1922,8 +1925,6 @@ static int amdgpu_device_ip_init(struct amdgpu_device
*adev)
init_failed:
if (amdgpu_sriov_vf(adev)) {
- if (!r)
- amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
}
@@ -2819,7 +2820,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
- mutex_init(>virt.dpm_mutex);
mutex_init(>psp.mutex);
r = amdgpu_device_check_arguments(adev);
@@ -3040,9 +3040,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
amdgpu_fbdev_init(adev);
- if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
- amdgpu_pm_virt_sysfs_init(adev);
-
r = amdgpu_pm_sysfs_init(adev);
if (r) {
adev->pm_sysfs_en = false;
@@ -3187,8 +3184,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
- if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
- amdgpu_pm_virt_sysfs_fini(adev);
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count);
@@ -3669,6 +3664,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device
*adev,
if (r)
goto error;
+ amdgpu_virt_init_data_exchange(adev);
/* we need recover gart prior to run SMC/CP/SDMA resume */
amdgpu_gtt_mgr_recover(>mman.bdev.man[TTM_PL_TT]);
@@ -3686,7 +3682,6 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device
*adev,
amdgpu_amdkfd_post_reset(adev);
error:
- amdgpu_virt_init_data_exchange(adev);
amdgpu_virt_release_full_gpu(adev, true);
if (!r && adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) {
amdgpu_inc_vram_lost(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5ec1415d1755..3a0ea9096498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -703,10 +703,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
if (adev->pm.dpm_enabled) {
dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev,
false) * 10;
dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev,
false) * 10;
- } else if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
-
[PATCH] drm/amd/powerplay: enable pp one vf mode for vega10
Originally, due to the restriction from PSP and SMU, VF has
to send message to hypervisor driver to handle powerplay
change which is complicated and redundant. Currently, SMU
and PSP can support VF to directly handle powerplay
change by itself. Therefore, the old code about the handshake
between VF and PF to handle powerplay will be removed and VF
will use new the registers below to handshake with SMU.
mmMP1_SMN_C2PMSG_101: register to handle SMU message
mmMP1_SMN_C2PMSG_102: register to handle SMU parameter
mmMP1_SMN_C2PMSG_103: register to handle SMU response
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c| 6 -
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 -
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c| 121 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 51 --
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 14 +-
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 78 -
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 4 -
drivers/gpu/drm/amd/amdgpu/soc15.c| 2 +-
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 7 +-
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c| 24 +--
.../drm/amd/powerplay/hwmgr/hardwaremanager.c | 15 +-
drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c | 4 +
drivers/gpu/drm/amd/powerplay/hwmgr/pp_psm.c | 30 ++--
.../drm/amd/powerplay/hwmgr/vega10_hwmgr.c| 157 --
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 1 +
.../drm/amd/powerplay/smumgr/smu9_smumgr.c| 55 --
.../drm/amd/powerplay/smumgr/vega10_smumgr.c | 6 +
19 files changed, 281 insertions(+), 306 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 50bab33cba39..3f00c2e0b0e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -114,6 +114,7 @@ struct amdgpu_mgpu_info
/*
* Modules parameters.
*/
+extern int amdgpu_pp_one_vf;
extern int amdgpu_modeset;
extern int amdgpu_vram_limit;
extern int amdgpu_vis_vram_limit;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b9ca7e728d3e..62fa5f074ebd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2819,7 +2819,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
- mutex_init(>virt.dpm_mutex);
mutex_init(>psp.mutex);
r = amdgpu_device_check_arguments(adev);
@@ -3040,9 +3039,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
amdgpu_fbdev_init(adev);
- if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
- amdgpu_pm_virt_sysfs_init(adev);
-
r = amdgpu_pm_sysfs_init(adev);
if (r) {
adev->pm_sysfs_en = false;
@@ -3187,8 +3183,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
- if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
- amdgpu_pm_virt_sysfs_fini(adev);
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index d1e9946ac218..f6a4642cf9b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -135,6 +135,7 @@ int amdgpu_lbpw = -1;
int amdgpu_compute_multipipe = -1;
int amdgpu_gpu_recovery = -1; /* auto */
int amdgpu_emu_mode = 0;
+int amdgpu_pp_one_vf;
uint amdgpu_smu_memory_pool_size = 0;
/* FBC (bit 0) disabled by default*/
uint amdgpu_dc_feature_mask = 0;
@@ -152,6 +153,12 @@ struct amdgpu_mgpu_info mgpu_info = {
int amdgpu_ras_enable = -1;
uint amdgpu_ras_mask = 0x;
+/**
+ * DOC: pp_one_vf (int)
+ * Enable VF to adjust the powerplay. The default is 0 (disable it).
+ */
+MODULE_PARM_DESC(pp_one_vf, "One vf mode support (0 = disable (default), 1 =
enable)");
+module_param_named(pp_one_vf, amdgpu_pp_one_vf, int, 0600);
/**
* DOC: vramlimit (int)
* Restrict the total amount of VRAM in MiB for testing. The default is 0
(Use full VRAM).
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5ec1415d1755..3a0ea9096498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -703,10 +703,6 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
if (adev->pm.dpm_enabled) {
dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev,
false) * 10;
dev_
[PATCH] drm/amdgpu: not remove sysfs if not create sysfs
When load amdgpu failed before create pm_sysfs and ucode_sysfs,
the pm_sysfs and ucode_sysfs should not be removed.
Otherwise, there will be warning call trace just like below.
[ 24.836386] [drm] VCE initialized successfully.
[ 24.841352] amdgpu :00:07.0: amdgpu_device_ip_init failed
[ 25.370383] amdgpu :00:07.0: Fatal error during GPU init
[ 25.889575] [drm] amdgpu: finishing device.
[ 26.069128] amdgpu :00:07.0: [drm:amdgpu_ring_test_helper [amdgpu]]
*ERROR* ring kiq_2.1.0 test failed (-110)
[ 26.070110] [drm:gfx_v9_0_hw_fini [amdgpu]] *ERROR* KCQ disable failed
[ 26.200309] [TTM] Finalizing pool allocator
[ 26.200314] [TTM] Finalizing DMA pool allocator
[ 26.200349] [TTM] Zone kernel: Used memory at exit: 0 KiB
[ 26.200351] [TTM] Zone dma32: Used memory at exit: 0 KiB
[ 26.200353] [drm] amdgpu: ttm finalized
[ 26.205329] [ cut here ]
[ 26.205330] sysfs group 'fw_version' not found for kobject ':00:07.0'
[ 26.205347] WARNING: CPU: 0 PID: 1228 at fs/sysfs/group.c:256
sysfs_remove_group+0x80/0x90
[ 26.205348] Modules linked in: amdgpu(OE+) gpu_sched(OE) ttm(OE)
drm_kms_helper(OE) drm(OE) i2c_algo_bit fb_sys_fops syscopyarea sysfillrect
sysimgblt rpcsec_gss_krb5 auth_rpcgss nfsv4 nfs lockd grace fscache binfmt_misc
snd_hda_codec_generic ledtrig_audio crct10dif_pclmul snd_hda_intel crc32_pclmul
snd_hda_codec ghash_clmulni_intel snd_hda_core snd_hwdep snd_pcm snd_timer
input_leds snd joydev soundcore serio_raw pcspkr evbug aesni_intel aes_x86_64
crypto_simd cryptd mac_hid glue_helper sunrpc ip_tables x_tables autofs4
8139too psmouse 8139cp mii i2c_piix4 pata_acpi floppy
[ 26.205369] CPU: 0 PID: 1228 Comm: modprobe Tainted: G OE
5.2.0-rc1 #1
[ 26.205370] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS
Ubuntu-1.8.2-1ubuntu1 04/01/2014
[ 26.205372] RIP: 0010:sysfs_remove_group+0x80/0x90
[ 26.205374] Code: e8 35 b9 ff ff 5b 41 5c 41 5d 5d c3 48 89 df e8 f6 b5 ff
ff eb c6 49 8b 55 00 49 8b 34 24 48 c7 c7 48 7a 70 98 e8 60 63 d3 ff <0f> 0b eb
d7 66 90 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55
[ 26.205375] RSP: 0018:bee242b0b908 EFLAGS: 00010282
[ 26.205376] RAX: RBX: RCX: 0006
[ 26.205377] RDX: 0007 RSI: 0092 RDI: 97ad6f817380
[ 26.205377] RBP: bee242b0b920 R08: 98f520c4 R09: 02b3
[ 26.205378] R10: bee242b0b8f8 R11: 02b3 R12: c0e58240
[ 26.205379] R13: 97ad6d1fe0b0 R14: 97ad4db954c8 R15: 97ad4db7fff0
[ 26.205380] FS: 7ff3d8a1c4c0() GS:97ad6f80()
knlGS:
[ 26.205381] CS: 0010 DS: ES: CR0: 80050033
[ 26.205381] CR2: 7f9b2ef1df04 CR3: 00042aab8001 CR4: 003606f0
[ 26.205384] DR0: DR1: DR2:
[ 26.205385] DR3: DR6: fffe0ff0 DR7: 0400
[ 26.205385] Call Trace:
[ 26.205461] amdgpu_ucode_sysfs_fini+0x18/0x20 [amdgpu]
[ 26.205518] amdgpu_device_fini+0x3b4/0x560 [amdgpu]
[ 26.205573] amdgpu_driver_unload_kms+0x4f/0xa0 [amdgpu]
[ 26.205623] amdgpu_driver_load_kms+0xcd/0x250 [amdgpu]
[ 26.205637] drm_dev_register+0x12b/0x1c0 [drm]
[ 26.205695] amdgpu_pci_probe+0x12a/0x1e0 [amdgpu]
[ 26.205699] local_pci_probe+0x47/0xa0
[ 26.205701] pci_device_probe+0x106/0x1b0
[ 26.205704] really_probe+0x21a/0x3f0
[ 26.205706] driver_probe_device+0x11c/0x140
[ 26.205707] device_driver_attach+0x58/0x60
[ 26.205709] __driver_attach+0xc3/0x140
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h| 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c3a394d841a8..958e8005a6cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1041,6 +1041,9 @@ struct amdgpu_device {
uint64_tunique_id;
uint64_tdf_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS];
+
+ boolpm_sysfs_en;
+ boolucode_sysfs_en;
};
static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index e7a175a6a448..3da1f84db274 100755
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3013,12 +3013,18 @@ int amdgpu_device_init(struct amdgpu_device *adev,
amdgpu_pm_virt_sysfs_init(adev);
r = amdgpu_pm_sysfs_init(adev);
- if (r)
+ if (r) {
+ adev->pm_sysfs_en = false;
DRM_ERROR("registering pm debugfs fail
[PATCH] drm/amdgpu: put flush_dealyed_work at first
There is one regression from 042f3d7b745cd76aa
To put flush_delayed_work after adev->shutdown = true
which will make amdgpu_ih_process not response the irq
At last, all ib ring tests will be failed just like below
[drm] amdgpu: finishing device.
[drm] Fence fallback timer expired on ring gfx
[drm] Fence fallback timer expired on ring comp_1.0.0
[drm] Fence fallback timer expired on ring comp_1.1.0
[drm] Fence fallback timer expired on ring comp_1.2.0
[drm] Fence fallback timer expired on ring comp_1.3.0
[drm] Fence fallback timer expired on ring comp_1.0.1
amdgpu :00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed
on comp_1.1.1 (-110).
amdgpu :00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed
on comp_1.2.1 (-110).
amdgpu :00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed
on comp_1.3.1 (-110).
amdgpu :00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed
on sdma0 (-110).
amdgpu :00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed
on sdma1 (-110).
amdgpu :00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed
on uvd_enc_0.0 (-110).
amdgpu :00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed
on vce0 (-110).
[drm:amdgpu_device_delayed_init_work_handler [amdgpu]] *ERROR* ib ring test
failed (-110).
v2: replace cancel_delayed_work_sync() with flush_delayed_work()
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 17be6389adf7..b7ab5224ae23 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3109,9 +3109,8 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
int r;
DRM_INFO("amdgpu: finishing device.\n");
- adev->shutdown = true;
-
flush_delayed_work(>delayed_init_work);
+ adev->shutdown = true;
/* disable all interrupts */
amdgpu_irq_disable_all(adev);
@@ -3130,7 +3129,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
adev->firmware.gpu_info_fw = NULL;
}
adev->accel_working = false;
- cancel_delayed_work_sync(>delayed_init_work);
/* free i2c buses */
if (!amdgpu_device_has_dc_support(adev))
amdgpu_i2c_fini(adev);
--
2.17.1
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: put cancel dealyed work at first
There is one regression from 042f3d7b745cd76aa
and one improvement here.
-regression:
put flush_delayed_work after adev->shutdown = true
which will make amdgpu_ih_process not response the irq
At last, all ib ring tests will be failed just like below
[drm] amdgpu: finishing device.
[drm] Fence fallback timer expired on ring gfx
[drm] Fence fallback timer expired on ring comp_1.0.0
[drm] Fence fallback timer expired on ring comp_1.1.0
[drm] Fence fallback timer expired on ring comp_1.2.0
[drm] Fence fallback timer expired on ring comp_1.3.0
[drm] Fence fallback timer expired on ring comp_1.0.1
amdgpu :00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed
on comp_1.1.1 (-110).
amdgpu :00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed
on comp_1.2.1 (-110).
amdgpu :00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed
on comp_1.3.1 (-110).
amdgpu :00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed
on sdma0 (-110).
amdgpu :00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed
on sdma1 (-110).
amdgpu :00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed
on uvd_enc_0.0 (-110).
amdgpu :00:07.0: [drm:amdgpu_ib_ring_tests [amdgpu]] *ERROR* IB test failed
on vce0 (-110).
[drm:amdgpu_device_delayed_init_work_handler [amdgpu]] *ERROR* ib ring test
failed (-110).
-improvement:
In fact, there is cancel_delayed_work_sync in this fucntion
So there is no need to invoke flush_delayed_work before
cancel_delayed_work_sync. Just put cancel at first
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 17be6389adf7..a2454c3efc65 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3109,10 +3109,9 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
int r;
DRM_INFO("amdgpu: finishing device.\n");
+ cancel_delayed_work_sync(>delayed_init_work);
adev->shutdown = true;
- flush_delayed_work(>delayed_init_work);
-
/* disable all interrupts */
amdgpu_irq_disable_all(adev);
if (adev->mode_info.mode_config_initialized){
@@ -3130,7 +3129,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
adev->firmware.gpu_info_fw = NULL;
}
adev->accel_working = false;
- cancel_delayed_work_sync(>delayed_init_work);
/* free i2c buses */
if (!amdgpu_device_has_dc_support(adev))
amdgpu_i2c_fini(adev);
--
2.17.1
___
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[PATCH] drm/amdgpu: register pm sysfs for sriov
we need register pm sysfs for virt in order
to support dpm level modification because
smu ip block will not be added under SRIOV
Signed-off-by: Yintian Tao
Change-Id: Ib0e13934c0c33da00f9d2add6be25a373c6fb957
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 61 --
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h | 2 +
3 files changed, 65 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d00fd5d..9b9d387 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2695,6 +2695,9 @@ int amdgpu_device_init(struct amdgpu_device *adev,
amdgpu_fbdev_init(adev);
+ if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
+ amdgpu_virt_pm_sysfs_init(adev);
+
r = amdgpu_pm_sysfs_init(adev);
if (r)
DRM_ERROR("registering pm debugfs failed (%d).\n", r);
@@ -2816,6 +2819,9 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
+ if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
+ amdgpu_virt_pm_sysfs_fini(adev);
+
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count);
amdgpu_ucode_sysfs_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index a73e190..93e5205 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -269,8 +269,11 @@ static ssize_t
amdgpu_get_dpm_forced_performance_level(struct device *dev,
struct amdgpu_device *adev = ddev->dev_private;
enum amd_dpm_forced_level level = 0xff;
- if ((adev->flags & AMD_IS_PX) &&
-(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
+ if ((adev->flags & AMD_IS_PX) &&
+ (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return snprintf(buf, PAGE_SIZE, "off\n");
if (is_support_sw_smu(adev))
@@ -308,9 +311,11 @@ static ssize_t
amdgpu_set_dpm_forced_performance_level(struct device *dev,
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return -EINVAL;
- if (is_support_sw_smu(adev))
+ if (!amdgpu_sriov_vf(adev) && is_support_sw_smu(adev))
current_level = smu_get_performance_level(>smu);
- else if (adev->powerplay.pp_funcs->get_performance_level)
+ else if (!amdgpu_sriov_vf(adev) &&
+adev->powerplay.pp_funcs &&
+adev->powerplay.pp_funcs->get_performance_level)
current_level = amdgpu_dpm_get_performance_level(adev);
if (strncmp("low", buf, strlen("low")) == 0) {
@@ -885,6 +890,9 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
int ret;
uint32_t mask = 0;
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
ret = amdgpu_read_mask(buf, count, );
if (ret)
return ret;
@@ -907,6 +915,10 @@ static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
+ if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
+ adev->virt.ops->get_pp_clk)
+ return adev->virt.ops->get_pp_clk(adev,PP_MCLK,buf);
+
if (is_support_sw_smu(adev))
return smu_print_clk_levels(>smu, PP_MCLK, buf);
else if (adev->powerplay.pp_funcs->print_clock_levels)
@@ -925,6 +937,9 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
int ret;
uint32_t mask = 0;
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
ret = amdgpu_read_mask(buf, count, );
if (ret)
return ret;
@@ -2698,6 +2713,44 @@ void amdgpu_pm_print_power_states(struct amdgpu_device
*adev)
}
+int amdgpu_virt_pm_sysfs_init(struct amdgpu_device *adev)
+{
+ int ret = 0;
+
+ if (!(amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev)))
+ return ret;
+
+ ret = device_create_file(adev->dev, _attr_pp_dpm_sclk);
+ if (ret) {
+ DRM_ERROR("failed to create device file pp_dpm_sclk\n");
+ return ret;
+ }
+
+ ret = device_create_file(adev->dev, _attr_pp_dpm_mclk);
+ if (ret) {
+ DRM_ERROR("failed to create device file pp_dpm_mclk\n");
+ return ret;
+ }
+
+ ret = device_create_file(adev->dev,
_attr_power_d
[PATCH] drm/amdgpu: register pm sysfs for sriov
we need register pm sysfs for virt in order
to support dpm level modification because
smu ip block will not be added under SRIOV
Signed-off-by: Yintian Tao
Change-Id: Ib0e13934c0c33da00f9d2add6be25a373c6fb957
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 61 --
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.h | 2 +
3 files changed, 65 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d00fd5d..9b9d387 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2695,6 +2695,9 @@ int amdgpu_device_init(struct amdgpu_device *adev,
amdgpu_fbdev_init(adev);
+ if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
+ amdgpu_virt_pm_sysfs_init(adev);
+
r = amdgpu_pm_sysfs_init(adev);
if (r)
DRM_ERROR("registering pm debugfs failed (%d).\n", r);
@@ -2816,6 +2819,9 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
iounmap(adev->rmmio);
adev->rmmio = NULL;
amdgpu_device_doorbell_fini(adev);
+ if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev))
+ amdgpu_virt_pm_sysfs_fini(adev);
+
amdgpu_debugfs_regs_cleanup(adev);
device_remove_file(adev->dev, _attr_pcie_replay_count);
amdgpu_ucode_sysfs_fini(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index a73e190..b6f16d45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -269,8 +269,11 @@ static ssize_t
amdgpu_get_dpm_forced_performance_level(struct device *dev,
struct amdgpu_device *adev = ddev->dev_private;
enum amd_dpm_forced_level level = 0xff;
- if ((adev->flags & AMD_IS_PX) &&
-(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
+ if ((adev->flags & AMD_IS_PX) &&
+ (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return snprintf(buf, PAGE_SIZE, "off\n");
if (is_support_sw_smu(adev))
@@ -308,9 +311,11 @@ static ssize_t
amdgpu_set_dpm_forced_performance_level(struct device *dev,
(ddev->switch_power_state != DRM_SWITCH_POWER_ON))
return -EINVAL;
- if (is_support_sw_smu(adev))
+ if (!amdgpu_sriov_vf(adev) && is_support_sw_smu(adev))
current_level = smu_get_performance_level(>smu);
- else if (adev->powerplay.pp_funcs->get_performance_level)
+ else if (!amdgpu_sriov_vf(adev) &&
+adev->powerplay.pp_funcs &&
+adev->powerplay.pp_funcs->get_performance_level)
current_level = amdgpu_dpm_get_performance_level(adev);
if (strncmp("low", buf, strlen("low")) == 0) {
@@ -907,6 +912,10 @@ static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
+ if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
+ adev->virt.ops->get_pp_clk)
+ return adev->virt.ops->get_pp_clk(adev,PP_MCLK,buf);
+
if (is_support_sw_smu(adev))
return smu_print_clk_levels(>smu, PP_MCLK, buf);
else if (adev->powerplay.pp_funcs->print_clock_levels)
@@ -925,6 +934,9 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
int ret;
uint32_t mask = 0;
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
ret = amdgpu_read_mask(buf, count, );
if (ret)
return ret;
@@ -965,6 +977,9 @@ static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
int ret;
uint32_t mask = 0;
+ if (amdgpu_sriov_vf(adev))
+ return 0;
+
ret = amdgpu_read_mask(buf, count, );
if (ret)
return ret;
@@ -2698,6 +2713,44 @@ void amdgpu_pm_print_power_states(struct amdgpu_device
*adev)
}
+int amdgpu_virt_pm_sysfs_init(struct amdgpu_device *adev)
+{
+ int ret = 0;
+
+ if (!(amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev)))
+ return ret;
+
+ ret = device_create_file(adev->dev, _attr_pp_dpm_sclk);
+ if (ret) {
+ DRM_ERROR("failed to create device file pp_dpm_sclk\n");
+ return ret;
+ }
+
+ ret = device_create_file(adev->dev, _attr_pp_dpm_mclk);
+ if (ret) {
+ DRM_ERROR("failed to create device file pp_dpm_mclk\n");
+ return ret;
+ }
+
+ ret = device_create_file(adev->dev,
_attr_power_d
[PATCH] drm/amdgpu/gfx9: ensure mqd data take effect when gpu reset
We should ensure mqd data take effect when gpu reset. Otherwise, it will rasie ring ib tests failure. Signed-off-by: Yintian Tao Signed-off-by: Monk Liu --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 2e9cac1..bea641d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -3123,6 +3123,8 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) if (adev->gfx.mec.mqd_backup[mqd_idx]) memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation)); + /* clean gpu table status */ + amdgpu_gmc_flush_gpu_tlb(adev, 0, 0); /* reset ring buffer */ ring->wptr = 0; amdgpu_ring_clear_ring(ring); @@ -3147,6 +3149,8 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation)); } + /* make sure mqd data landed into VRAM */ + amdgpu_asic_flush_hdp(adev, NULL); return 0; } -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu/gfx9: reset compute ring wptr when gpu reset
We need reset compute ring wptr to zero when gpu reset
in order to prevent CP hang.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 2e9cac1..25211ba 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3175,6 +3175,7 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring
*ring)
/* reset ring buffer */
ring->wptr = 0;
+ amdgpu_ring_set_wptr(ring);
amdgpu_ring_clear_ring(ring);
} else {
amdgpu_ring_clear_ring(ring);
--
2.7.4
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[PATCH] drm/amdgpu: no read DF register under SRIOV and set correct vram width
PART1:
Under SRIOV, reading DF register has chance to lead to
AER error in host side, just skip reading it.
PART2:
For Vega10 SR-IOV, vram_width can't be read from ATOM as
RAVEN, and DF related registers is not readable, seems hardcord
is the only way to set the correct vram_width.
Signed-off-by: Trigger Huang
Signed-off-by: Monk Liu
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index c221570..b5bf9ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -837,7 +837,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
if (amdgpu_emu_mode != 1)
adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
- if (!adev->gmc.vram_width) {
+ if (!adev->gmc.vram_width && !amdgpu_sriov_vf(adev)) {
/* hbm memory channel size */
if (adev->flags & AMD_IS_APU)
chansize = 64;
@@ -848,6 +848,13 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
adev->gmc.vram_width = numchan * chansize;
}
+ /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
+* and DF related registers is not readable, seems hardcord is the
+* only way to set the correct vram_width */
+ if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) {
+ adev->gmc.vram_width = 2048;
+ }
+
/* size in MB on si */
adev->gmc.mc_vram_size =
adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
--
2.7.4
___
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[PATCH] drm/amdgpu: don't read DF register for SRIOV
Under SRIOV, reading DF register has chance to lead to
AER error in host side, just skip reading it.
Signed-off-by: Monk Liu
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index a417763..b5bf9ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -837,7 +837,7 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
if (amdgpu_emu_mode != 1)
adev->gmc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
- if (!adev->gmc.vram_width) {
+ if (!adev->gmc.vram_width && !amdgpu_sriov_vf(adev)) {
/* hbm memory channel size */
if (adev->flags & AMD_IS_APU)
chansize = 64;
--
2.7.4
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[PATCH] drm/amdgpu: set correct vram_width for vega10 under sriov
For Vega10 SR-IOV, vram_width can't be read from ATOM as
RAVEN, and DF related registers is not readable, seems hardcord
is the only way to set the correct vram_width
Signed-off-by: Trigger Huang
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index c221570..a417763 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -848,6 +848,13 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
adev->gmc.vram_width = numchan * chansize;
}
+ /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
+* and DF related registers is not readable, seems hardcord is the
+* only way to set the correct vram_width */
+ if (amdgpu_sriov_vf(adev) && (adev->asic_type == CHIP_VEGA10)) {
+ adev->gmc.vram_width = 2048;
+ }
+
/* size in MB on si */
adev->gmc.mc_vram_size =
adev->nbio_funcs->get_memsize(adev) * 1024ULL * 1024ULL;
--
2.7.4
___
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[PATCH] drm/amdgpu: skip fw pri bo alloc for SRIOV
PSP fw primary buffer is not used under SRIOV.
Therefore, we don't need to allocate memory for it.
v2: remove superfluous check for amdgpu_bo_free_kernel().
Signed-off-by: Yintian Tao
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index c567a55..af9835c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -905,13 +905,16 @@ static int psp_load_fw(struct amdgpu_device *adev)
if (!psp->cmd)
return -ENOMEM;
- ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
- AMDGPU_GEM_DOMAIN_GTT,
- >fw_pri_bo,
- >fw_pri_mc_addr,
- >fw_pri_buf);
- if (ret)
- goto failed;
+ /* this fw pri bo is not used under SRIOV */
+ if (!amdgpu_sriov_vf(psp->adev)) {
+ ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
+ AMDGPU_GEM_DOMAIN_GTT,
+ >fw_pri_bo,
+ >fw_pri_mc_addr,
+ >fw_pri_buf);
+ if (ret)
+ goto failed;
+ }
ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
--
2.7.4
___
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: skip fw pri bo alloc for SRIOV
PSP fw primary buffer is not used under SRIOV
Therefore, we don't need to allocate memory for it.
Signed-off-by: Yintian Tao
Signed-off-by: Monk Liu
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index c567a55..d3c77d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -905,13 +905,16 @@ static int psp_load_fw(struct amdgpu_device *adev)
if (!psp->cmd)
return -ENOMEM;
- ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
- AMDGPU_GEM_DOMAIN_GTT,
- >fw_pri_bo,
- >fw_pri_mc_addr,
- >fw_pri_buf);
- if (ret)
- goto failed;
+ /* this fw pri bo is not used under SRIOV */
+ if (!amdgpu_sriov_vf(psp->adev)) {
+ ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
+ AMDGPU_GEM_DOMAIN_GTT,
+ >fw_pri_bo,
+ >fw_pri_mc_addr,
+ >fw_pri_buf);
+ if (ret)
+ goto failed;
+ }
ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_VRAM,
@@ -1012,8 +1015,9 @@ static int psp_hw_fini(void *handle)
psp_ring_destroy(psp, PSP_RING_TYPE__KM);
amdgpu_bo_free_kernel(>tmr_bo, >tmr_mc_addr, >tmr_buf);
- amdgpu_bo_free_kernel(>fw_pri_bo,
- >fw_pri_mc_addr, >fw_pri_buf);
+ if (!amdgpu_sriov_vf(psp->adev))
+ amdgpu_bo_free_kernel(>fw_pri_bo,
+ >fw_pri_mc_addr, >fw_pri_buf);
amdgpu_bo_free_kernel(>fence_buf_bo,
>fence_buf_mc_addr, >fence_buf);
amdgpu_bo_free_kernel(>asd_shared_bo, >asd_shared_mc_addr,
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: disable DRIVER_ATOMIC under SRIOV
Under SRIOV, we need disable DRIVER_ATOMIC. Otherwise, it will trigger WARN_ON at drm_universal_plane_init. Change-Id: I96a78d6e45b3a67ab9b9534e7071ae5daacc0f4f Signed-off-by: Yintian Tao --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 7e7f9ed..7d484fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -36,6 +36,7 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev) /* enable virtual display */ adev->mode_info.num_crtc = 1; adev->enable_virtual_display = true; + adev->ddev->driver->driver_features &= ~DRIVER_ATOMIC; adev->cg_flags = 0; adev->pg_flags = 0; } -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: support dpm level modification under virtualization v3
Under vega10 virtualuzation, smu ip block will not be added.
Therefore, we need add pp clk query and force dpm level function
at amdgpu_virt_ops to support the feature.
v2: add get_pp_clk existence check and use kzalloc to allocate buf
v3: return -ENOMEM for allocation failure and correct the coding style
Change-Id: I713419c57b854082f6f739f1d32a055c7115e620
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 4 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 15 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 49 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 11 +
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 78 ++
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 6 +++
7 files changed, 164 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3ff8899..bb0fd5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2486,6 +2486,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
+ mutex_init(>virt.dpm_mutex);
amdgpu_device_check_arguments(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 6190495..29ec28f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -727,6 +727,10 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
if (adev->pm.dpm_enabled) {
dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev,
false) * 10;
dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev,
false) * 10;
+ } else if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
+ adev->virt.ops->get_pp_clk) {
+ dev_info.max_engine_clock = amdgpu_virt_get_sclk(adev,
false) * 10;
+ dev_info.max_memory_clock = amdgpu_virt_get_mclk(adev,
false) * 10;
} else {
dev_info.max_engine_clock = adev->clock.default_sclk *
10;
dev_info.max_memory_clock = adev->clock.default_mclk *
10;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 5540259..0162d1e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -380,6 +380,17 @@ static ssize_t
amdgpu_set_dpm_forced_performance_level(struct device *dev,
goto fail;
}
+if (amdgpu_sriov_vf(adev)) {
+if (amdgim_is_hwperf(adev) &&
+adev->virt.ops->force_dpm_level) {
+mutex_lock(>pm.mutex);
+adev->virt.ops->force_dpm_level(adev, level);
+mutex_unlock(>pm.mutex);
+return count;
+} else
+return -EINVAL;
+}
+
if (current_level == level)
return count;
@@ -843,6 +854,10 @@ static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
+ if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
+ adev->virt.ops->get_pp_clk)
+ return adev->virt.ops->get_pp_clk(adev, PP_SCLK, buf);
+
if (is_support_sw_smu(adev))
return smu_print_clk_levels(>smu, PP_SCLK, buf);
else if (adev->powerplay.pp_funcs->print_clock_levels)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 462a04e..7e7f9ed 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -375,4 +375,53 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device
*adev)
}
}
+static uint32_t parse_clk(char *buf, bool min)
+{
+char *ptr = buf;
+uint32_t clk = 0;
+
+do {
+ptr = strchr(ptr, ':');
+if (!ptr)
+break;
+ptr+=2;
+clk = simple_strtoul(ptr, NULL, 10);
+} while (!min);
+
+return clk * 100;
+}
+
+uint32_t amdgpu_virt_get_sclk(struct amdgpu_device *adev, bool lowest)
+{
+ char *buf = NULL;
+ uint32_t clk = 0;
+
+ buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ adev->virt.ops->get_pp_clk(adev, PP_SCLK, buf);
+ clk = parse_clk(buf, lowest);
+
+ kfree(buf);
+
+ return clk;
+}
+
+uint32_t amdgpu_virt_get_mclk(stru
[PATCH] drm/amdgpu: support dpm level modification under virtualization v2
Under vega10 virtualuzation, smu ip block will not be added.
Therefore, we need add pp clk query and force dpm level function
at amdgpu_virt_ops to support the feature.
v2: add get_pp_clk existence check and use kzalloc to allocate buf
Change-Id: I713419c57b854082f6f739f1d32a055c7115e620
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 4 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 15 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 49 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 11 +
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 78 ++
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 6 +++
7 files changed, 164 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3ff8899..bb0fd5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2486,6 +2486,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
+ mutex_init(>virt.dpm_mutex);
amdgpu_device_check_arguments(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 6190495..29ec28f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -727,6 +727,10 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
if (adev->pm.dpm_enabled) {
dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev,
false) * 10;
dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev,
false) * 10;
+ } else if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
+ adev->virt.ops->get_pp_clk) {
+ dev_info.max_engine_clock = amdgpu_virt_get_sclk(adev,
false) * 10;
+ dev_info.max_memory_clock = amdgpu_virt_get_mclk(adev,
false) * 10;
} else {
dev_info.max_engine_clock = adev->clock.default_sclk *
10;
dev_info.max_memory_clock = adev->clock.default_mclk *
10;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 5540259..0162d1e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -380,6 +380,17 @@ static ssize_t
amdgpu_set_dpm_forced_performance_level(struct device *dev,
goto fail;
}
+if (amdgpu_sriov_vf(adev)) {
+if (amdgim_is_hwperf(adev) &&
+adev->virt.ops->force_dpm_level) {
+mutex_lock(>pm.mutex);
+adev->virt.ops->force_dpm_level(adev, level);
+mutex_unlock(>pm.mutex);
+return count;
+} else
+return -EINVAL;
+}
+
if (current_level == level)
return count;
@@ -843,6 +854,10 @@ static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
+ if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
+ adev->virt.ops->get_pp_clk)
+ return adev->virt.ops->get_pp_clk(adev, PP_SCLK, buf);
+
if (is_support_sw_smu(adev))
return smu_print_clk_levels(>smu, PP_SCLK, buf);
else if (adev->powerplay.pp_funcs->print_clock_levels)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 462a04e..efdb6b7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -375,4 +375,53 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device
*adev)
}
}
+static uint32_t parse_clk(char *buf, bool min)
+{
+char *ptr = buf;
+uint32_t clk = 0;
+
+do {
+ptr = strchr(ptr, ':');
+if (!ptr)
+break;
+ptr+=2;
+clk = simple_strtoul(ptr, NULL, 10);
+} while (!min);
+
+return clk * 100;
+}
+
+uint32_t amdgpu_virt_get_sclk(struct amdgpu_device *adev, bool lowest)
+{
+char *buf = NULL;
+ uint32_t clk = 0;
+
+ buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
+ if (NULL == buf)
+ return -EINVAL;
+
+adev->virt.ops->get_pp_clk(adev, PP_SCLK, buf);
+clk = parse_clk(buf, lowest);
+
+ kfree(buf);
+
+ return clk;
+}
+
+uint32_t amdgpu_virt_get_mclk(struct amdgpu_device *adev, bool lowest)
+{
+
[PATCH] drm/amdgpu: support dpm level modification under virtualization
Under vega10 virtualuzation, smu ip block will not be added.
Therefore, we need add pp clk query and force dpm level function
at amdgpu_virt_ops to support the feature.
Change-Id: I713419c57b854082f6f739f1d32a055c7115e620
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c| 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 15 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 33 +
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 11 +
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c | 78 ++
drivers/gpu/drm/amd/amdgpu/mxgpu_ai.h | 6 +++
7 files changed, 147 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 3ff8899..bb0fd5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2486,6 +2486,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
mutex_init(>virt.vf_errors.lock);
hash_init(adev->mn_hash);
mutex_init(>lock_reset);
+ mutex_init(>virt.dpm_mutex);
amdgpu_device_check_arguments(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 6190495..1353955 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -727,6 +727,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void
*data, struct drm_file
if (adev->pm.dpm_enabled) {
dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev,
false) * 10;
dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev,
false) * 10;
+ } else if (amdgpu_sriov_vf(adev)) {
+ dev_info.max_engine_clock = amdgpu_virt_get_sclk(adev,
false) * 10;
+ dev_info.max_memory_clock = amdgpu_virt_get_mclk(adev,
false) * 10;
} else {
dev_info.max_engine_clock = adev->clock.default_sclk *
10;
dev_info.max_memory_clock = adev->clock.default_mclk *
10;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 5540259..0162d1e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -380,6 +380,17 @@ static ssize_t
amdgpu_set_dpm_forced_performance_level(struct device *dev,
goto fail;
}
+if (amdgpu_sriov_vf(adev)) {
+if (amdgim_is_hwperf(adev) &&
+adev->virt.ops->force_dpm_level) {
+mutex_lock(>pm.mutex);
+adev->virt.ops->force_dpm_level(adev, level);
+mutex_unlock(>pm.mutex);
+return count;
+} else
+return -EINVAL;
+}
+
if (current_level == level)
return count;
@@ -843,6 +854,10 @@ static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = ddev->dev_private;
+ if (amdgpu_sriov_vf(adev) && amdgim_is_hwperf(adev) &&
+ adev->virt.ops->get_pp_clk)
+ return adev->virt.ops->get_pp_clk(adev, PP_SCLK, buf);
+
if (is_support_sw_smu(adev))
return smu_print_clk_levels(>smu, PP_SCLK, buf);
else if (adev->powerplay.pp_funcs->print_clock_levels)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 462a04e..ae4b2a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -375,4 +375,37 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device
*adev)
}
}
+static uint32_t parse_clk(char *buf, bool min)
+{
+char *ptr = buf;
+uint32_t clk = 0;
+
+do {
+ptr = strchr(ptr, ':');
+if (!ptr)
+break;
+ptr+=2;
+clk = simple_strtoul(ptr, NULL, 10);
+} while (!min);
+
+return clk * 100;
+}
+
+uint32_t amdgpu_virt_get_sclk(struct amdgpu_device *adev, bool lowest)
+{
+char buf[512] = {0};
+
+adev->virt.ops->get_pp_clk(adev, PP_SCLK, buf);
+
+return parse_clk(buf, lowest);
+}
+
+uint32_t amdgpu_virt_get_mclk(struct amdgpu_device *adev, bool lowest)
+{
+char buf[512] = {0};
+
+adev->virt.ops->get_pp_clk(adev, PP_MCLK, buf);
+
+return parse_clk(buf, lowest);
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 722deef..584947b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -57,6
[PATCH] drm/amdgpu: move full access into amdgpu_device_ip_suspend
It will be more safe to make full-acess include both phase1 and phase2.
Then accessing special registeris wherever at phase1 or phase2 will not
block any shutdown and suspend process under virtualization.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c23339d..6bb0e47 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1932,9 +1932,6 @@ static int amdgpu_device_ip_suspend_phase1(struct
amdgpu_device *adev)
{
int i, r;
- if (amdgpu_sriov_vf(adev))
- amdgpu_virt_request_full_gpu(adev, false);
-
amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
@@ -1953,9 +1950,6 @@ static int amdgpu_device_ip_suspend_phase1(struct
amdgpu_device *adev)
}
}
- if (amdgpu_sriov_vf(adev))
- amdgpu_virt_release_full_gpu(adev, false);
-
return 0;
}
@@ -2007,11 +2001,17 @@ int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
{
int r;
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_virt_request_full_gpu(adev, false);
+
r = amdgpu_device_ip_suspend_phase1(adev);
if (r)
return r;
r = amdgpu_device_ip_suspend_phase2(adev);
+ if (amdgpu_sriov_vf(adev))
+ amdgpu_virt_release_full_gpu(adev, false);
+
return r;
}
--
2.7.4
___
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: move set pg state to suspend phase2
Under virtualization, We have to require full-acess gpu at
suspend phase2 due to some special register access. In order
to guarantee it, we should move set pg and cg state to suspend
phase2 to make registers access at one full-acess lifecycle.
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 42 ++
1 file changed, 31 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index c9557d9..2d95769 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1713,10 +1713,11 @@ static int amdgpu_device_set_cg_state(struct
amdgpu_device *adev,
i = state == AMD_CG_STATE_GATE ? j : adev->num_ip_blocks - j -
1;
if (!adev->ip_blocks[i].status.valid)
continue;
- /* skip CG for VCE/UVD, it's handled specially */
+ /* skip CG for VCE/UVD and DCE, it's handled specially */
if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
+ adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE &&
adev->ip_blocks[i].version->funcs->set_clockgating_state) {
/* enable clockgating to save power */
r =
adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
@@ -1743,10 +1744,11 @@ static int amdgpu_device_set_pg_state(struct
amdgpu_device *adev, enum amd_power
i = state == AMD_PG_STATE_GATE ? j : adev->num_ip_blocks - j -
1;
if (!adev->ip_blocks[i].status.valid)
continue;
- /* skip CG for VCE/UVD, it's handled specially */
+ /* skip CG for VCE/UVD and DCE, it's handled specially */
if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCN &&
+ adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_DCE &&
adev->ip_blocks[i].version->funcs->set_powergating_state) {
/* enable powergating to save power */
r =
adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
@@ -1932,17 +1934,29 @@ static int amdgpu_device_ip_suspend_phase1(struct
amdgpu_device *adev)
{
int i, r;
- if (amdgpu_sriov_vf(adev))
- amdgpu_virt_request_full_gpu(adev, false);
-
- amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
- amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
-
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.valid)
continue;
/* displays are handled separately */
if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) {
+ if
(adev->ip_blocks[i].version->funcs->set_powergating_state) {
+ r =
adev->ip_blocks[i].version->funcs->set_powergating_state((void *)adev,
+
AMD_PG_STATE_UNGATE);
+ if (r) {
+ DRM_ERROR("set_powergating_state(gate)
of IP block <%s> failed %d\n",
+
adev->ip_blocks[i].version->funcs->name, r);
+ return r;
+ }
+ }
+ /* ungate blocks so that suspend can properly shut them
down */
+ if
(adev->ip_blocks[i].version->funcs->set_clockgating_state) {
+ r =
adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
+
AMD_CG_STATE_UNGATE);
+ if (r) {
+
DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
+
adev->ip_blocks[i].version->funcs->name, r);
+ }
+ }
/* XXX handle errors */
r = adev->ip_blocks[i].version->funcs->suspend(
[PATCH] drm/powerplay: enable dpm under pass-through
Repeat enable dpm under pass-through because there is no actually
hardware-fini and real power-off when guest vm shutdown or reboot.
Otherwise, under pass-through it will be failed to populate populate
and upload SCLK MCLK DPM levels due to zero of pcie_speed_table.count.
Change-Id: I7cbc55c650867d00e19241ceea5d98f78b5ac3f5
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
index 53207e7..6ef3c87 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
@@ -75,10 +75,12 @@ int phm_set_power_state(struct pp_hwmgr *hwmgr,
int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr)
{
+ struct amdgpu_device *adev = NULL;
int ret = -EINVAL;;
PHM_FUNC_CHECK(hwmgr);
+ adev = hwmgr->adev;
- if (smum_is_dpm_running(hwmgr)) {
+ if (smum_is_dpm_running(hwmgr) && !amdgpu_passthrough(adev)) {
pr_info("dpm has been enabled\n");
return 0;
}
--
2.7.4
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[PATCH] drm/amdgpu: remove fulll access for suspend phase1
There is no need for gpu full access for suspend phase1
because under virtualization there is no hw register access
for dce block.
Change-Id: Ie1154e2065182ba968732af87f866f11141a102b
Signed-off-by: Yintian Tao
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index d84ac23..5da20b1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1968,9 +1968,6 @@ static int amdgpu_device_ip_suspend_phase1(struct
amdgpu_device *adev)
{
int i, r;
- if (amdgpu_sriov_vf(adev))
- amdgpu_virt_request_full_gpu(adev, false);
-
for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
if (!adev->ip_blocks[i].status.valid)
continue;
@@ -1995,9 +1992,6 @@ static int amdgpu_device_ip_suspend_phase1(struct
amdgpu_device *adev)
}
}
- if (amdgpu_sriov_vf(adev))
- amdgpu_virt_release_full_gpu(adev, false);
-
return 0;
}
--
2.7.4
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[PATCH] drm/amdpgu: access register without KIQ
there is no need to access register such as mmSMC_IND_INDEX_11 and mmSMC_IND_DATA_11 through KIQ because they are VF-copy. Change-Id: I88302dc5945e0b0fa2e6411081fb798aab4fdb5e Signed-off-by: Yintian Tao Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 29fbb91..5a30bf7 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -112,8 +112,8 @@ static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg) u32 r; spin_lock_irqsave(>smc_idx_lock, flags); - WREG32(mmSMC_IND_INDEX_11, (reg)); - r = RREG32(mmSMC_IND_DATA_11); + WREG32_NO_KIQ(mmSMC_IND_INDEX_11, (reg)); + r = RREG32_NO_KIQ(mmSMC_IND_DATA_11); spin_unlock_irqrestore(>smc_idx_lock, flags); return r; } -- 2.7.4 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amd/powerplay: fix typo error for '3be7be08ac'
Due to typo error, it will cause compile error so fix it.
Change-Id: Iabe7158e08e6aef155ca3394cafc6eb4256a0030
Signed-off-by: Yintian Tao <yt...@amd.com>
---
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index 7dc4cee..25dd778 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -648,7 +648,7 @@ int smu7_init(struct pp_hwmgr *hwmgr)
int smu7_smu_fini(struct pp_hwmgr *hwmgr)
{
- struct smu7_smumgr smu_data = (struct smu7_smumgr
*)(hwmgr->smu_backend);
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr
*)(hwmgr->smu_backend);
smu_free_memory(hwmgr->device, smu_data->header_buffer.handle);
if (!cgs_is_virtualization_enabled(hwmgr->device))
--
2.7.4
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[PATCH] drm/amd/powerplay: fix memory leakage when reload
add smu_free_memory when smu fini to prevent memory leakage
Change-Id: Id9103d8b54869b63f22a9af53d9fbc3b7a221191
Signed-off-by: Yintian Tao <yt...@amd.com>
---
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
index c49a6f2..925217e 100644
--- a/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
+++ b/drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
@@ -607,6 +607,12 @@ int smu7_init(struct pp_smumgr *smumgr)
int smu7_smu_fini(struct pp_smumgr *smumgr)
{
+ struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(smumgr->backend);
+
+ smu_free_memory(smumgr->device, smu_data->header_buffer.handle);
+ if (!cgs_is_virtualization_enabled(smumgr->device))
+ smu_free_memory(smumgr->device, smu_data->smu_buffer.handle);
+
if (smumgr->backend) {
kfree(smumgr->backend);
smumgr->backend = NULL;
--
2.7.4
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[PATCH] drm/amdgpu: Fix no irq process when evict vram
When unload amdgpu driver we use sdma to evict vram but there is no
irq process after sdma completed work which raises that waiting for the
fence costs 2s which will trigger VFLR under SRIOV and at last make
unload driver failed.The reason is that the shutdown varible in adev
is set to true before evict vram, it cause ISR directly return without
processing.Therefore, we need set the varible after evict vram.
Change-Id: I7bf75481aa0744b99c41672b49670adc70b478bd
Signed-off-by: Yintian Tao <yt...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a269bbc..80934ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2458,7 +2458,6 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
int r;
DRM_INFO("amdgpu: finishing device.\n");
- adev->shutdown = true;
if (adev->mode_info.mode_config_initialized)
drm_crtc_force_disable_all(adev->ddev);
@@ -2466,6 +2465,7 @@ void amdgpu_device_fini(struct amdgpu_device *adev)
amdgpu_fence_driver_fini(adev);
amdgpu_fbdev_fini(adev);
r = amdgpu_fini(adev);
+ adev->shutdown = true;
if (adev->firmware.gpu_info_fw) {
release_firmware(adev->firmware.gpu_info_fw);
adev->firmware.gpu_info_fw = NULL;
--
2.7.4
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[PATCH] drm/amdgpu: correct wptr initialization for sdma
If doorbell is used for wptr update, we also need to use it to initialize wptr to 0. Change-Id: Ieb31a6726a9ac8d45e51f0370ef5f77dc5ec7c06 Signed-off-by: Yintian Tao <yt...@amd.com> --- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index cfd968e..a154faf 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -643,8 +643,9 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); /* Initialize the ring buffer's read and write pointers */ + ring->wptr = 0; WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0); - WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); + sdma_v3_0_ring_set_wptr(ring); WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0); WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0); -- 1.9.1 ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
[PATCH] drm/amdgpu: correct wptr initialization for sdma
If doorbell is used for wptr update, we also need to use it
to initialize wptr to 0.
Change-Id: Ieb31a6726a9ac8d45e51f0370ef5f77dc5ec7c06
Signed-off-by: Yintian Tao <yt...@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index cfd968e..7b6d3e9 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -643,8 +643,9 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
/* Initialize the ring buffer's read and write pointers */
+ ring->wptr = 0;
WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
- WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
+ sdma_v3_0_ring_set_wptr(ring);
WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
@@ -659,9 +660,6 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >>
8);
WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr
>> 40);
- ring->wptr = 0;
- WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i],
lower_32_bits(ring->wptr) << 2);
-
doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
if (ring->use_doorbell) {
--
1.9.1
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