Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
As explained before we don't need a GART mapping any more for small allocations. Additional to that we want it to support early bringup where no VRAM is attached to the ASIC. Regards, Christian. Am 30.08.2018 um 05:48 schrieb Xiao, Jack: Can you explain what the benefits can be gained from AGP aperture enablement? Otherwise, it would increase our maintenance workload. Regards, Jack -Original Message- From: Christian König Sent: Wednesday, August 29, 2018 4:47 PM To: Kuehling, Felix ; Koenig, Christian ; Xiao, Jack ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9 Completely agree with Felix here. It makes system memory access slightly simpler, but I would say that you accidentally corrupt the GART table and that you accidentally corrupt the the AGP aperture is equally likely. Regards, Christian. Am 28.08.2018 um 20:12 schrieb Felix Kuehling: The GPU always has access to the entire guest physical address space. You can just program arbitrary addresses into page table entries and set the system bit. That's how GART and GPUVM mappings work. They will not go through the AGP aperture. And there is no mechanism (other than an IOMMU) to protect system memory from GPU access. Regards, Felix On 2018-08-28 07:41 AM, Christian König wrote: Well that is indeed true, but we still have IOMMU between the GPU and the system memory. So we should still catch issues when something goes terrible wrong. Additional to that only the system domain, e.g. kernel copies, page table updates etc are allowed to use it. Regards, Christian. Am 28.08.2018 um 09:06 schrieb Xiao, Jack: I mean it has risk to make GPU allowed to access to most system memory without explicit claiming, it's easier to mask problem. Regards, Jack -Original Message- From: Koenig, Christian Sent: Tuesday, August 28, 2018 2:46 PM To: Xiao, Jack ; Kuehling, Felix ; Christian König ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9 This series patches seems to make AGP aperture allowed to access any system memory (16GB) bypass GPU VM protection. The system aperture should only be active in the system domain, or otherwise applications would have access to local memory as well. There are some bits in the VM registers to enable/disable that, but when we would have that setting incorrect we would see quite a bunch of other problems. Might still be a good idea to double check if all the bits are setup correctly. Regards, Christian. Am 28.08.2018 um 07:31 schrieb Xiao, Jack: This series patches seems to make AGP aperture allowed to access any system memory (16GB) bypass GPU VM protection. If someone made a wrong logic requesting an illegal address which occasionally was located inside AGP aperture, but without any VM protection, the illegal address would be finally translated into a system memory address; if GPU read/wrote such system memory address, the system memory address might belong to kernel or any user application, the r/w operation would result in any unpredictable issue. The most important is that such kind of issue is so hard to be addressed. Is it worth doing this, but exposing risk? Regards, Jack -Original Message- From: amd-gfx On Behalf Of Felix Kuehling Sent: Tuesday, August 28, 2018 3:03 AM To: Christian König ; amd-gfx@lists.freedesktop.org; Koenig, Christian Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9 The point of this series seems to be to allow access to small system memory BOs (one page) without a GART mapping. I'm guessing that reduces pressure on the GART and removes the need for HDP and TLB flushes. Why does Patch 10 only enable that on GFXv9? Is there less benefit on older chips? Is this related to your recent changes to allow page tables in system memory? See my replies to patch 6 and 8. Other than that, the series is Acked-by: Felix Kuehling Regards, Felix On 2018-08-27 12:53 PM, Christian König wrote: Only use the lower address space on GMC9 for the system domain. Otherwise we would need to sign extend GMC addresses. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e44b5191735d..d982956c8329 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; - /* Set the internal MC address mask - * This is the max address of the GPU's - * internal address space. + /* Use only the lower range for the internal MC address mask. This is + * the max address of the GPU's internal address space. */ - adev->gmc.mc_mask = 0xULL; /* 48 bit
RE: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
Can you explain what the benefits can be gained from AGP aperture enablement? Otherwise, it would increase our maintenance workload. Regards, Jack -Original Message- From: Christian König Sent: Wednesday, August 29, 2018 4:47 PM To: Kuehling, Felix ; Koenig, Christian ; Xiao, Jack ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9 Completely agree with Felix here. It makes system memory access slightly simpler, but I would say that you accidentally corrupt the GART table and that you accidentally corrupt the the AGP aperture is equally likely. Regards, Christian. Am 28.08.2018 um 20:12 schrieb Felix Kuehling: > The GPU always has access to the entire guest physical address space. > You can just program arbitrary addresses into page table entries and > set the system bit. That's how GART and GPUVM mappings work. They will > not go through the AGP aperture. And there is no mechanism (other than > an > IOMMU) to protect system memory from GPU access. > > Regards, > Felix > > > On 2018-08-28 07:41 AM, Christian König wrote: >> Well that is indeed true, but we still have IOMMU between the GPU and >> the system memory. >> >> So we should still catch issues when something goes terrible wrong. >> >> Additional to that only the system domain, e.g. kernel copies, page >> table updates etc are allowed to use it. >> >> Regards, >> Christian. >> >> Am 28.08.2018 um 09:06 schrieb Xiao, Jack: >>> I mean it has risk to make GPU allowed to access to most system >>> memory without explicit claiming, it's easier to mask problem. >>> >>> Regards, >>> Jack >>> >>> -Original Message- >>> From: Koenig, Christian >>> Sent: Tuesday, August 28, 2018 2:46 PM >>> To: Xiao, Jack ; Kuehling, Felix >>> ; Christian König >>> ; amd-gfx@lists.freedesktop.org >>> Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address >>> space on GMC9 >>> >>>> This series patches seems to make AGP aperture allowed to access >>>> any system memory (16GB) bypass GPU VM protection. >>> The system aperture should only be active in the system domain, or >>> otherwise applications would have access to local memory as well. >>> >>> There are some bits in the VM registers to enable/disable that, but >>> when we would have that setting incorrect we would see quite a bunch >>> of other problems. >>> >>> Might still be a good idea to double check if all the bits are setup >>> correctly. >>> >>> Regards, >>> Christian. >>> >>> Am 28.08.2018 um 07:31 schrieb Xiao, Jack: >>>> This series patches seems to make AGP aperture allowed to access >>>> any system memory (16GB) bypass GPU VM protection. >>>> If someone made a wrong logic requesting an illegal address which >>>> occasionally was located inside AGP aperture, but without any VM >>>> protection, the illegal address would be finally translated into a >>>> system memory address; if GPU read/wrote such system memory >>>> address, the system memory address might belong to kernel or any >>>> user application, the r/w operation would result in any unpredictable >>>> issue. >>>> The most important is that such kind of issue is so hard to be >>>> addressed. >>>> Is it worth doing this, but exposing risk? >>>> >>>> Regards, >>>> Jack >>>> >>>> -Original Message- >>>> From: amd-gfx On Behalf Of >>>> Felix Kuehling >>>> Sent: Tuesday, August 28, 2018 3:03 AM >>>> To: Christian König ; >>>> amd-gfx@lists.freedesktop.org; Koenig, Christian >>>> >>>> Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address >>>> space on GMC9 >>>> >>>> The point of this series seems to be to allow access to small >>>> system memory BOs (one page) without a GART mapping. I'm guessing >>>> that reduces pressure on the GART and removes the need for HDP and >>>> TLB flushes. Why does Patch 10 only enable that on GFXv9? Is there >>>> less benefit on older chips? >>>> >>>> Is this related to your recent changes to allow page tables in >>>> system memory? >>>> >>>> See my replies to patch 6 and 8. Other than that, the series is >>>> Acked-by: Felix Kuehling >>>> >>
Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
Completely agree with Felix here. It makes system memory access slightly simpler, but I would say that you accidentally corrupt the GART table and that you accidentally corrupt the the AGP aperture is equally likely. Regards, Christian. Am 28.08.2018 um 20:12 schrieb Felix Kuehling: The GPU always has access to the entire guest physical address space. You can just program arbitrary addresses into page table entries and set the system bit. That's how GART and GPUVM mappings work. They will not go through the AGP aperture. And there is no mechanism (other than an IOMMU) to protect system memory from GPU access. Regards, Felix On 2018-08-28 07:41 AM, Christian König wrote: Well that is indeed true, but we still have IOMMU between the GPU and the system memory. So we should still catch issues when something goes terrible wrong. Additional to that only the system domain, e.g. kernel copies, page table updates etc are allowed to use it. Regards, Christian. Am 28.08.2018 um 09:06 schrieb Xiao, Jack: I mean it has risk to make GPU allowed to access to most system memory without explicit claiming, it's easier to mask problem. Regards, Jack -Original Message- From: Koenig, Christian Sent: Tuesday, August 28, 2018 2:46 PM To: Xiao, Jack ; Kuehling, Felix ; Christian König ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9 This series patches seems to make AGP aperture allowed to access any system memory (16GB) bypass GPU VM protection. The system aperture should only be active in the system domain, or otherwise applications would have access to local memory as well. There are some bits in the VM registers to enable/disable that, but when we would have that setting incorrect we would see quite a bunch of other problems. Might still be a good idea to double check if all the bits are setup correctly. Regards, Christian. Am 28.08.2018 um 07:31 schrieb Xiao, Jack: This series patches seems to make AGP aperture allowed to access any system memory (16GB) bypass GPU VM protection. If someone made a wrong logic requesting an illegal address which occasionally was located inside AGP aperture, but without any VM protection, the illegal address would be finally translated into a system memory address; if GPU read/wrote such system memory address, the system memory address might belong to kernel or any user application, the r/w operation would result in any unpredictable issue. The most important is that such kind of issue is so hard to be addressed. Is it worth doing this, but exposing risk? Regards, Jack -Original Message- From: amd-gfx On Behalf Of Felix Kuehling Sent: Tuesday, August 28, 2018 3:03 AM To: Christian König ; amd-gfx@lists.freedesktop.org; Koenig, Christian Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9 The point of this series seems to be to allow access to small system memory BOs (one page) without a GART mapping. I'm guessing that reduces pressure on the GART and removes the need for HDP and TLB flushes. Why does Patch 10 only enable that on GFXv9? Is there less benefit on older chips? Is this related to your recent changes to allow page tables in system memory? See my replies to patch 6 and 8. Other than that, the series is Acked-by: Felix Kuehling Regards, Felix On 2018-08-27 12:53 PM, Christian König wrote: Only use the lower address space on GMC9 for the system domain. Otherwise we would need to sign extend GMC addresses. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e44b5191735d..d982956c8329 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; - /* Set the internal MC address mask - * This is the max address of the GPU's - * internal address space. + /* Use only the lower range for the internal MC address mask. This is + * the max address of the GPU's internal address space. */ - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ + adev->gmc.mc_mask = 0x7fffULL; /* set DMA mask + need_dma32 flags. * PCIE - can handle 44-bits. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
> Well that is indeed true, but we still have IOMMU between the GPU and the > system memory. Some platform hasn't IOMMU, or IOMMU isn’t enabled by default. If such kind of issue was reported by customer, it was so hard to narrow down. > Additional to that only the system domain, e.g. kernel copies, page table > updates etc are allowed to use it. What was the motivation of this series patch? I guess it is for performance improvement, right? But AGP aperture memory is translated as mtype=UC same with GART (mtype=UC). The more overhead on GART is gpuVM pagetable walker, but I guess the overhead is little. Regards, Jack -Original Message- From: Christian König Sent: Tuesday, August 28, 2018 7:42 PM To: Xiao, Jack ; Koenig, Christian ; Kuehling, Felix ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9 Well that is indeed true, but we still have IOMMU between the GPU and the system memory. So we should still catch issues when something goes terrible wrong. Additional to that only the system domain, e.g. kernel copies, page table updates etc are allowed to use it. Regards, Christian. Am 28.08.2018 um 09:06 schrieb Xiao, Jack: > I mean it has risk to make GPU allowed to access to most system memory > without explicit claiming, it's easier to mask problem. > > Regards, > Jack > > -Original Message- > From: Koenig, Christian > Sent: Tuesday, August 28, 2018 2:46 PM > To: Xiao, Jack ; Kuehling, Felix > ; Christian König > ; amd-gfx@lists.freedesktop.org > Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address > space on GMC9 > >> This series patches seems to make AGP aperture allowed to access any system >> memory (16GB) bypass GPU VM protection. > The system aperture should only be active in the system domain, or otherwise > applications would have access to local memory as well. > > There are some bits in the VM registers to enable/disable that, but when we > would have that setting incorrect we would see quite a bunch of other > problems. > > Might still be a good idea to double check if all the bits are setup > correctly. > > Regards, > Christian. > > Am 28.08.2018 um 07:31 schrieb Xiao, Jack: >> This series patches seems to make AGP aperture allowed to access any system >> memory (16GB) bypass GPU VM protection. >> If someone made a wrong logic requesting an illegal address which >> occasionally was located inside AGP aperture, but without any VM >> protection, the illegal address would be finally translated into a >> system memory address; if GPU read/wrote such system memory address, the >> system memory address might belong to kernel or any user application, the >> r/w operation would result in any unpredictable issue. >> The most important is that such kind of issue is so hard to be addressed. >> Is it worth doing this, but exposing risk? >> >> Regards, >> Jack >> >> -Original Message----- >> From: amd-gfx On Behalf Of >> Felix Kuehling >> Sent: Tuesday, August 28, 2018 3:03 AM >> To: Christian König ; >> amd-gfx@lists.freedesktop.org; Koenig, Christian >> >> Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address >> space on GMC9 >> >> The point of this series seems to be to allow access to small system memory >> BOs (one page) without a GART mapping. I'm guessing that reduces pressure on >> the GART and removes the need for HDP and TLB flushes. Why does Patch 10 >> only enable that on GFXv9? Is there less benefit on older chips? >> >> Is this related to your recent changes to allow page tables in system memory? >> >> See my replies to patch 6 and 8. Other than that, the series is >> Acked-by: Felix Kuehling >> >> Regards, >> Felix >> >> >> On 2018-08-27 12:53 PM, Christian König wrote: >>> Only use the lower address space on GMC9 for the system domain. >>> Otherwise we would need to sign extend GMC addresses. >>> >>> Signed-off-by: Christian König >>> --- >>>drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ >>>1 file changed, 3 insertions(+), 4 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>> index e44b5191735d..d982956c8329 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>> @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) >>> if (r) >>> return r; >>> >>> - /* Set the internal MC addr
Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
The GPU always has access to the entire guest physical address space. You can just program arbitrary addresses into page table entries and set the system bit. That's how GART and GPUVM mappings work. They will not go through the AGP aperture. And there is no mechanism (other than an IOMMU) to protect system memory from GPU access. Regards, Felix On 2018-08-28 07:41 AM, Christian König wrote: > Well that is indeed true, but we still have IOMMU between the GPU and > the system memory. > > So we should still catch issues when something goes terrible wrong. > > Additional to that only the system domain, e.g. kernel copies, page > table updates etc are allowed to use it. > > Regards, > Christian. > > Am 28.08.2018 um 09:06 schrieb Xiao, Jack: >> I mean it has risk to make GPU allowed to access to most system >> memory without explicit claiming, it's easier to mask problem. >> >> Regards, >> Jack >> >> -Original Message- >> From: Koenig, Christian >> Sent: Tuesday, August 28, 2018 2:46 PM >> To: Xiao, Jack ; Kuehling, Felix >> ; Christian König >> ; amd-gfx@lists.freedesktop.org >> Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address >> space on GMC9 >> >>> This series patches seems to make AGP aperture allowed to access any >>> system memory (16GB) bypass GPU VM protection. >> The system aperture should only be active in the system domain, or >> otherwise applications would have access to local memory as well. >> >> There are some bits in the VM registers to enable/disable that, but >> when we would have that setting incorrect we would see quite a bunch >> of other problems. >> >> Might still be a good idea to double check if all the bits are setup >> correctly. >> >> Regards, >> Christian. >> >> Am 28.08.2018 um 07:31 schrieb Xiao, Jack: >>> This series patches seems to make AGP aperture allowed to access any >>> system memory (16GB) bypass GPU VM protection. >>> If someone made a wrong logic requesting an illegal address which >>> occasionally was located inside AGP aperture, but without any VM >>> protection, the illegal address would be finally translated into a >>> system memory address; if GPU read/wrote such system memory address, >>> the system memory address might belong to kernel or any user >>> application, the r/w operation would result in any unpredictable issue. >>> The most important is that such kind of issue is so hard to be >>> addressed. >>> Is it worth doing this, but exposing risk? >>> >>> Regards, >>> Jack >>> >>> -Original Message- >>> From: amd-gfx On Behalf Of >>> Felix Kuehling >>> Sent: Tuesday, August 28, 2018 3:03 AM >>> To: Christian König ; >>> amd-gfx@lists.freedesktop.org; Koenig, Christian >>> >>> Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address >>> space on GMC9 >>> >>> The point of this series seems to be to allow access to small system >>> memory BOs (one page) without a GART mapping. I'm guessing that >>> reduces pressure on the GART and removes the need for HDP and TLB >>> flushes. Why does Patch 10 only enable that on GFXv9? Is there less >>> benefit on older chips? >>> >>> Is this related to your recent changes to allow page tables in >>> system memory? >>> >>> See my replies to patch 6 and 8. Other than that, the series is >>> Acked-by: Felix Kuehling >>> >>> Regards, >>> Felix >>> >>> >>> On 2018-08-27 12:53 PM, Christian König wrote: >>>> Only use the lower address space on GMC9 for the system domain. >>>> Otherwise we would need to sign extend GMC addresses. >>>> >>>> Signed-off-by: Christian König >>>> --- >>>> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ >>>> 1 file changed, 3 insertions(+), 4 deletions(-) >>>> >>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>>> index e44b5191735d..d982956c8329 100644 >>>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >>>> @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) >>>> if (r) >>>> return r; >>>> - /* Set the internal MC address mask >>>> - * This is the max address of the GPU's >>>> - * internal address space. >>>> + /* Use only the lower range for the internal MC address mask. >>>> This is >>>> + * the max address of the GPU's internal address space. >>>> */ >>>> - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ >>>> + adev->gmc.mc_mask = 0x7fffULL; >>>> /* set DMA mask + need_dma32 flags. >>>> * PCIE - can handle 44-bits. >>> ___ >>> amd-gfx mailing list >>> amd-gfx@lists.freedesktop.org >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
On 2018-08-28 02:53 AM, Christian König wrote: > Am 28.08.2018 um 06:21 schrieb zhoucm1: >> >> >> On 2018年08月28日 03:03, Felix Kuehling wrote: >>> The point of this series seems to be to allow access to small system >>> memory BOs (one page) without a GART mapping. I'm guessing that reduces >>> pressure on the GART and removes the need for HDP and TLB flushes. >> I think if adding these explain/reason to comments are better to >> enable AGP apperture. If that's true, it's really a clever idea. > > Well that is one use case. Another one is that we can enable dGPU > without any VRAM. > > That is really important for emulation and early ASIC testing. > >> >> Regards, >> David Zhou >> >>> Why >>> does Patch 10 only enable that on GFXv9? Is there less benefit on older >>> chips? > > Can easily be enabled on older chips as well, but I haven't yet had > time to test it. But on older ASICs, page tables are typically bigger than one page. So you'd still get GART mappings for them. BTW, how do you make sure those page tables are physically contiguous in the first place? >>> >>> Is this related to your recent changes to allow page tables in system >>> memory? > > Yes, as it turned out that otherwise results in a huge bunch of extra > GART mappings. Oh, so the point is to avoid GART mappings for page tables, which are a single page on GFXv9. Now it makes sense. I was wondering what the killer use case was. Thanks, Felix > > Regards, > Christian. > >>> >>> See my replies to patch 6 and 8. Other than that, the series is >>> Acked-by: Felix Kuehling >>> >>> Regards, >>> Felix >>> >>> >>> On 2018-08-27 12:53 PM, Christian König wrote: Only use the lower address space on GMC9 for the system domain. Otherwise we would need to sign extend GMC addresses. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e44b5191735d..d982956c8329 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; - /* Set the internal MC address mask - * This is the max address of the GPU's - * internal address space. + /* Use only the lower range for the internal MC address mask. This is + * the max address of the GPU's internal address space. */ - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ + adev->gmc.mc_mask = 0x7fffULL; /* set DMA mask + need_dma32 flags. * PCIE - can handle 44-bits. >>> ___ >>> amd-gfx mailing list >>> amd-gfx@lists.freedesktop.org >>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx >> > ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
Well that is indeed true, but we still have IOMMU between the GPU and the system memory. So we should still catch issues when something goes terrible wrong. Additional to that only the system domain, e.g. kernel copies, page table updates etc are allowed to use it. Regards, Christian. Am 28.08.2018 um 09:06 schrieb Xiao, Jack: I mean it has risk to make GPU allowed to access to most system memory without explicit claiming, it's easier to mask problem. Regards, Jack -Original Message- From: Koenig, Christian Sent: Tuesday, August 28, 2018 2:46 PM To: Xiao, Jack ; Kuehling, Felix ; Christian König ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9 This series patches seems to make AGP aperture allowed to access any system memory (16GB) bypass GPU VM protection. The system aperture should only be active in the system domain, or otherwise applications would have access to local memory as well. There are some bits in the VM registers to enable/disable that, but when we would have that setting incorrect we would see quite a bunch of other problems. Might still be a good idea to double check if all the bits are setup correctly. Regards, Christian. Am 28.08.2018 um 07:31 schrieb Xiao, Jack: This series patches seems to make AGP aperture allowed to access any system memory (16GB) bypass GPU VM protection. If someone made a wrong logic requesting an illegal address which occasionally was located inside AGP aperture, but without any VM protection, the illegal address would be finally translated into a system memory address; if GPU read/wrote such system memory address, the system memory address might belong to kernel or any user application, the r/w operation would result in any unpredictable issue. The most important is that such kind of issue is so hard to be addressed. Is it worth doing this, but exposing risk? Regards, Jack -Original Message- From: amd-gfx On Behalf Of Felix Kuehling Sent: Tuesday, August 28, 2018 3:03 AM To: Christian König ; amd-gfx@lists.freedesktop.org; Koenig, Christian Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9 The point of this series seems to be to allow access to small system memory BOs (one page) without a GART mapping. I'm guessing that reduces pressure on the GART and removes the need for HDP and TLB flushes. Why does Patch 10 only enable that on GFXv9? Is there less benefit on older chips? Is this related to your recent changes to allow page tables in system memory? See my replies to patch 6 and 8. Other than that, the series is Acked-by: Felix Kuehling Regards, Felix On 2018-08-27 12:53 PM, Christian König wrote: Only use the lower address space on GMC9 for the system domain. Otherwise we would need to sign extend GMC addresses. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e44b5191735d..d982956c8329 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; - /* Set the internal MC address mask -* This is the max address of the GPU's -* internal address space. + /* Use only the lower range for the internal MC address mask. This is +* the max address of the GPU's internal address space. */ - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ + adev->gmc.mc_mask = 0x7fffULL; /* set DMA mask + need_dma32 flags. * PCIE - can handle 44-bits. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
I mean it has risk to make GPU allowed to access to most system memory without explicit claiming, it's easier to mask problem. Regards, Jack -Original Message- From: Koenig, Christian Sent: Tuesday, August 28, 2018 2:46 PM To: Xiao, Jack ; Kuehling, Felix ; Christian König ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9 > This series patches seems to make AGP aperture allowed to access any system > memory (16GB) bypass GPU VM protection. The system aperture should only be active in the system domain, or otherwise applications would have access to local memory as well. There are some bits in the VM registers to enable/disable that, but when we would have that setting incorrect we would see quite a bunch of other problems. Might still be a good idea to double check if all the bits are setup correctly. Regards, Christian. Am 28.08.2018 um 07:31 schrieb Xiao, Jack: > This series patches seems to make AGP aperture allowed to access any system > memory (16GB) bypass GPU VM protection. > If someone made a wrong logic requesting an illegal address which > occasionally was located inside AGP aperture, but without any VM > protection, the illegal address would be finally translated into a > system memory address; if GPU read/wrote such system memory address, the > system memory address might belong to kernel or any user application, the r/w > operation would result in any unpredictable issue. > The most important is that such kind of issue is so hard to be addressed. > Is it worth doing this, but exposing risk? > > Regards, > Jack > > -Original Message- > From: amd-gfx On Behalf Of > Felix Kuehling > Sent: Tuesday, August 28, 2018 3:03 AM > To: Christian König ; > amd-gfx@lists.freedesktop.org; Koenig, Christian > > Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address > space on GMC9 > > The point of this series seems to be to allow access to small system memory > BOs (one page) without a GART mapping. I'm guessing that reduces pressure on > the GART and removes the need for HDP and TLB flushes. Why does Patch 10 only > enable that on GFXv9? Is there less benefit on older chips? > > Is this related to your recent changes to allow page tables in system memory? > > See my replies to patch 6 and 8. Other than that, the series is > Acked-by: Felix Kuehling > > Regards, > Felix > > > On 2018-08-27 12:53 PM, Christian König wrote: >> Only use the lower address space on GMC9 for the system domain. >> Otherwise we would need to sign extend GMC addresses. >> >> Signed-off-by: Christian König >> --- >> drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ >> 1 file changed, 3 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> index e44b5191735d..d982956c8329 100644 >> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c >> @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) >> if (r) >> return r; >> >> -/* Set the internal MC address mask >> - * This is the max address of the GPU's >> - * internal address space. >> +/* Use only the lower range for the internal MC address mask. This is >> + * the max address of the GPU's internal address space. >> */ >> -adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ >> +adev->gmc.mc_mask = 0x7fffULL; >> >> /* set DMA mask + need_dma32 flags. >> * PCIE - can handle 44-bits. > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
Am 28.08.2018 um 06:21 schrieb zhoucm1: On 2018年08月28日 03:03, Felix Kuehling wrote: The point of this series seems to be to allow access to small system memory BOs (one page) without a GART mapping. I'm guessing that reduces pressure on the GART and removes the need for HDP and TLB flushes. I think if adding these explain/reason to comments are better to enable AGP apperture. If that's true, it's really a clever idea. Well that is one use case. Another one is that we can enable dGPU without any VRAM. That is really important for emulation and early ASIC testing. Regards, David Zhou Why does Patch 10 only enable that on GFXv9? Is there less benefit on older chips? Can easily be enabled on older chips as well, but I haven't yet had time to test it. Is this related to your recent changes to allow page tables in system memory? Yes, as it turned out that otherwise results in a huge bunch of extra GART mappings. Regards, Christian. See my replies to patch 6 and 8. Other than that, the series is Acked-by: Felix Kuehling Regards, Felix On 2018-08-27 12:53 PM, Christian König wrote: Only use the lower address space on GMC9 for the system domain. Otherwise we would need to sign extend GMC addresses. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e44b5191735d..d982956c8329 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; - /* Set the internal MC address mask - * This is the max address of the GPU's - * internal address space. + /* Use only the lower range for the internal MC address mask. This is + * the max address of the GPU's internal address space. */ - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ + adev->gmc.mc_mask = 0x7fffULL; /* set DMA mask + need_dma32 flags. * PCIE - can handle 44-bits. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
This series patches seems to make AGP aperture allowed to access any system memory (16GB) bypass GPU VM protection. The system aperture should only be active in the system domain, or otherwise applications would have access to local memory as well. There are some bits in the VM registers to enable/disable that, but when we would have that setting incorrect we would see quite a bunch of other problems. Might still be a good idea to double check if all the bits are setup correctly. Regards, Christian. Am 28.08.2018 um 07:31 schrieb Xiao, Jack: This series patches seems to make AGP aperture allowed to access any system memory (16GB) bypass GPU VM protection. If someone made a wrong logic requesting an illegal address which occasionally was located inside AGP aperture, but without any VM protection, the illegal address would be finally translated into a system memory address; if GPU read/wrote such system memory address, the system memory address might belong to kernel or any user application, the r/w operation would result in any unpredictable issue. The most important is that such kind of issue is so hard to be addressed. Is it worth doing this, but exposing risk? Regards, Jack -Original Message- From: amd-gfx On Behalf Of Felix Kuehling Sent: Tuesday, August 28, 2018 3:03 AM To: Christian König ; amd-gfx@lists.freedesktop.org; Koenig, Christian Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9 The point of this series seems to be to allow access to small system memory BOs (one page) without a GART mapping. I'm guessing that reduces pressure on the GART and removes the need for HDP and TLB flushes. Why does Patch 10 only enable that on GFXv9? Is there less benefit on older chips? Is this related to your recent changes to allow page tables in system memory? See my replies to patch 6 and 8. Other than that, the series is Acked-by: Felix Kuehling Regards, Felix On 2018-08-27 12:53 PM, Christian König wrote: Only use the lower address space on GMC9 for the system domain. Otherwise we would need to sign extend GMC addresses. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e44b5191735d..d982956c8329 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; - /* Set the internal MC address mask -* This is the max address of the GPU's -* internal address space. + /* Use only the lower range for the internal MC address mask. This is +* the max address of the GPU's internal address space. */ - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ + adev->gmc.mc_mask = 0x7fffULL; /* set DMA mask + need_dma32 flags. * PCIE - can handle 44-bits. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
RE: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
This series patches seems to make AGP aperture allowed to access any system memory (16GB) bypass GPU VM protection. If someone made a wrong logic requesting an illegal address which occasionally was located inside AGP aperture, but without any VM protection, the illegal address would be finally translated into a system memory address; if GPU read/wrote such system memory address, the system memory address might belong to kernel or any user application, the r/w operation would result in any unpredictable issue. The most important is that such kind of issue is so hard to be addressed. Is it worth doing this, but exposing risk? Regards, Jack -Original Message- From: amd-gfx On Behalf Of Felix Kuehling Sent: Tuesday, August 28, 2018 3:03 AM To: Christian König ; amd-gfx@lists.freedesktop.org; Koenig, Christian Subject: Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9 The point of this series seems to be to allow access to small system memory BOs (one page) without a GART mapping. I'm guessing that reduces pressure on the GART and removes the need for HDP and TLB flushes. Why does Patch 10 only enable that on GFXv9? Is there less benefit on older chips? Is this related to your recent changes to allow page tables in system memory? See my replies to patch 6 and 8. Other than that, the series is Acked-by: Felix Kuehling Regards, Felix On 2018-08-27 12:53 PM, Christian König wrote: > Only use the lower address space on GMC9 for the system domain. > Otherwise we would need to sign extend GMC addresses. > > Signed-off-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index e44b5191735d..d982956c8329 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) > if (r) > return r; > > - /* Set the internal MC address mask > - * This is the max address of the GPU's > - * internal address space. > + /* Use only the lower range for the internal MC address mask. This is > + * the max address of the GPU's internal address space. >*/ > - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ > + adev->gmc.mc_mask = 0x7fffULL; > > /* set DMA mask + need_dma32 flags. >* PCIE - can handle 44-bits. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
On 2018年08月28日 03:03, Felix Kuehling wrote: The point of this series seems to be to allow access to small system memory BOs (one page) without a GART mapping. I'm guessing that reduces pressure on the GART and removes the need for HDP and TLB flushes. I think if adding these explain/reason to comments are better to enable AGP apperture. If that's true, it's really a clever idea. Regards, David Zhou Why does Patch 10 only enable that on GFXv9? Is there less benefit on older chips? Is this related to your recent changes to allow page tables in system memory? See my replies to patch 6 and 8. Other than that, the series is Acked-by: Felix Kuehling Regards, Felix On 2018-08-27 12:53 PM, Christian König wrote: Only use the lower address space on GMC9 for the system domain. Otherwise we would need to sign extend GMC addresses. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e44b5191735d..d982956c8329 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; - /* Set the internal MC address mask -* This is the max address of the GPU's -* internal address space. + /* Use only the lower range for the internal MC address mask. This is +* the max address of the GPU's internal address space. */ - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ + adev->gmc.mc_mask = 0x7fffULL; /* set DMA mask + need_dma32 flags. * PCIE - can handle 44-bits. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
On 08/28/2018 09:56 AM, Zhang, Jerry (Junwei) wrote: On 08/28/2018 12:53 AM, Christian König wrote: Only use the lower address space on GMC9 for the system domain. Otherwise we would need to sign extend GMC addresses. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e44b5191735d..d982956c8329 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; -/* Set the internal MC address mask - * This is the max address of the GPU's - * internal address space. +/* Use only the lower range for the internal MC address mask. This is + * the max address of the GPU's internal address space. */ -adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ +adev->gmc.mc_mask = 0x7fffULL; do we need to update vm_size as 128T at the same time? Likely no, since we use that for system domain only. BTW, how do we decide it's size limitation. looks we always use that less than 40bit? Jerry Jerry /* set DMA mask + need_dma32 flags. * PCIE - can handle 44-bits. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
On 08/28/2018 12:53 AM, Christian König wrote: Only use the lower address space on GMC9 for the system domain. Otherwise we would need to sign extend GMC addresses. Signed-off-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e44b5191735d..d982956c8329 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; - /* Set the internal MC address mask -* This is the max address of the GPU's -* internal address space. + /* Use only the lower range for the internal MC address mask. This is +* the max address of the GPU's internal address space. */ - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ + adev->gmc.mc_mask = 0x7fffULL; do we need to update vm_size as 128T at the same time? Jerry /* set DMA mask + need_dma32 flags. * PCIE - can handle 44-bits. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
The point of this series seems to be to allow access to small system memory BOs (one page) without a GART mapping. I'm guessing that reduces pressure on the GART and removes the need for HDP and TLB flushes. Why does Patch 10 only enable that on GFXv9? Is there less benefit on older chips? Is this related to your recent changes to allow page tables in system memory? See my replies to patch 6 and 8. Other than that, the series is Acked-by: Felix Kuehling Regards, Felix On 2018-08-27 12:53 PM, Christian König wrote: > Only use the lower address space on GMC9 for the system domain. > Otherwise we would need to sign extend GMC addresses. > > Signed-off-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index e44b5191735d..d982956c8329 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) > if (r) > return r; > > - /* Set the internal MC address mask > - * This is the max address of the GPU's > - * internal address space. > + /* Use only the lower range for the internal MC address mask. This is > + * the max address of the GPU's internal address space. >*/ > - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ > + adev->gmc.mc_mask = 0x7fffULL; > > /* set DMA mask + need_dma32 flags. >* PCIE - can handle 44-bits. ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
Re: [PATCH 01/10] drm/amdgpu: use only the lower address space on GMC9
On Mon, Aug 27, 2018 at 12:56 PM Christian König wrote: > > Only use the lower address space on GMC9 for the system domain. > Otherwise we would need to sign extend GMC addresses. > > Signed-off-by: Christian König > --- > drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > index e44b5191735d..d982956c8329 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c > @@ -938,11 +938,10 @@ static int gmc_v9_0_sw_init(void *handle) > if (r) > return r; > > - /* Set the internal MC address mask > -* This is the max address of the GPU's > -* internal address space. > + /* Use only the lower range for the internal MC address mask. This is > +* the max address of the GPU's internal address space. > */ Update this comment to note the sign extension requirements and note that this max address is only for the system context (vmid 0). With that fixed: Reviewed-by: Alex Deucher Alex > - adev->gmc.mc_mask = 0xULL; /* 48 bit MC */ > + adev->gmc.mc_mask = 0x7fffULL; > > /* set DMA mask + need_dma32 flags. > * PCIE - can handle 44-bits. > -- > 2.17.1 > > ___ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx ___ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx
