Re: [ARTIQ] clock recovery on Metlino and Kasli

2016-06-30 Thread Grzegorz Kasprowicz 
Well, one can do this, there were discussion about replacing of VCXO with 
internall PLL (there is Xilinx note about it)
But it requires additional work in gateware and it is not trivial to make it 
working reliably.
Greg

-Original Message-
From: Sébastien Bourdeauducq [mailto:s...@m-labs.hk] 
Sent: Thursday, June 30, 2016 5:57 AM
To: Grzegorz Kasprowicz ; j arl 
Cc: Robert Jördens ; artiq@lists.m-labs.hk
Subject: Re: clock recovery on Metlino and Kasli

Hi,

my question was whether one can get rid of all those 6 parts and replace them 
with a Si5324 circuit (instead of #1 and supporting parts) and internal FPGA 
PLL(s) (instead of #2 and supporting parts). Why did you design it that way - 
what do all those additional parts bring exactly?

Sébastien


On Thursday, June 30, 2016 12:06 AM, Grzegorz Kasprowicz wrote:
> Hi
> The idea is to use SPEC board design: 
> http://www.ohwr.org/projects/spec/wiki
> It's well debugged. I designed it a few years ago and it's already 
> 4-th revision.
> The WR components are:
> 1. 25MHz VCXO VM53S3-25.000-2.5/-30+75 + CDCM61004RHBT PLL chip. The 
> two can be replaced by 125MHz VCXO.
> 2. 20MHz helper VCXO for DDMTD : LF VCXO026156 3. 2x DAC AD5662BRMZ-1 
> 4. 3V LDO : LP5951MF-3.0/NOPB 5. 2.5V reference: LM336M-2.5/NOPB 6. 
> some LRC passives Greg
>
>
>
>
> On 29 June 2016 at 15:56, j arl  > wrote:
>
> As the topic shifted from backplane logic, I've moved to this
> conversation to a new thread.
>
> On Tuesday, June 28, 2016 04:02 PM, Grzegorz Kasprowicz wrote:
> > For synchronisation over fibre we can use existing White Rabbit core.
> > The card requires only 2 VCXO oscillators and FPGA logic. The WR core
> > consumes 50% of small Spartan 45T. It ensures 1ns timing accuracy.
>
> >We probably won't use White Rabbit as-is, but the basic principle will
> >be the same. It can be a good idea to include those VCXOs on boards
> that
> >may be synchronized over fiber (Kasli/Metlino), though can't we use
> >instead a Si5324 for jitter cleanup and FPGA PLLs for DDMTD?
>
> Heads up that the clock synchronization for Metlino resides on
> Metlino_clk (Tongue 2) not Metlino_motherboard (Tongue 3-4). So
> headers need to provide whatever io is required. Greg already has a
> layout for a Metlino_clk board that has White Rabbit components on it.
>
> Greg, do you have a short list of components required for
> WhiteRabbit-type clock recovery?  -Joe
>
>

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Re: [ARTIQ] clock recovery on Metlino and Kasli

2016-06-30 Thread Grzegorz Kasprowicz 
OK

On 30 June 2016 at 10:50, Sébastien Bourdeauducq  wrote:

> On Thursday, June 30, 2016 04:49 PM, Grzegorz Kasprowicz wrote:
>
>> In case of WR it already worked quite well 6 years ago but later on this
>> circuit was modified several times:)
>> All the time little things.
>> So since we have more important things to do I'd leave it as it is.
>>
>
> Since we are not going to use White Rabbit, I propose removing them. I do
> not have a strong opinion about this since the complexity/part count should
> be small.
>
> Sébastien
>
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Re: [ARTIQ] clock recovery on Metlino and Kasli

2016-06-30 Thread Sébastien Bourdeauducq 

On Thursday, June 30, 2016 04:49 PM, Grzegorz Kasprowicz wrote:

In case of WR it already worked quite well 6 years ago but later on this
circuit was modified several times:)
All the time little things.
So since we have more important things to do I'd leave it as it is.


Since we are not going to use White Rabbit, I propose removing them. I 
do not have a strong opinion about this since the complexity/part count 
should be small.


Sébastien
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Re: [ARTIQ] clock recovery on Metlino and Kasli

2016-06-29 Thread Sébastien Bourdeauducq 

Hi,

my question was whether one can get rid of all those 6 parts and replace 
them with a Si5324 circuit (instead of #1 and supporting parts) and 
internal FPGA PLL(s) (instead of #2 and supporting parts). Why did you 
design it that way - what do all those additional parts bring exactly?


Sébastien


On Thursday, June 30, 2016 12:06 AM, Grzegorz Kasprowicz wrote:

Hi
The idea is to use SPEC board design: http://www.ohwr.org/projects/spec/wiki
It's well debugged. I designed it a few years ago and it's already 4-th
revision.
The WR components are:
1. 25MHz VCXO VM53S3-25.000-2.5/-30+75 + CDCM61004RHBT PLL chip. The two
can be replaced by 125MHz VCXO.
2. 20MHz helper VCXO for DDMTD : LF VCXO026156
3. 2x DAC AD5662BRMZ-1
4. 3V LDO : LP5951MF-3.0/NOPB
5. 2.5V reference: LM336M-2.5/NOPB
6. some LRC passives
Greg




On 29 June 2016 at 15:56, j arl > wrote:

As the topic shifted from backplane logic, I've moved to this
conversation to a new thread.

On Tuesday, June 28, 2016 04:02 PM, Grzegorz Kasprowicz wrote:
> For synchronisation over fibre we can use existing White Rabbit core.
> The card requires only 2 VCXO oscillators and FPGA logic. The WR core
> consumes 50% of small Spartan 45T. It ensures 1ns timing accuracy.

>We probably won't use White Rabbit as-is, but the basic principle will
>be the same. It can be a good idea to include those VCXOs on boards
that
>may be synchronized over fiber (Kasli/Metlino), though can't we use
>instead a Si5324 for jitter cleanup and FPGA PLLs for DDMTD?

Heads up that the clock synchronization for Metlino resides on
Metlino_clk (Tongue 2) not Metlino_motherboard (Tongue 3-4). So
headers need to provide whatever io is required. Greg already has a
layout for a Metlino_clk board that has White Rabbit components on it.

Greg, do you have a short list of components required for
WhiteRabbit-type clock recovery?  -Joe



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[ARTIQ] clock recovery on Metlino and Kasli

2016-06-29 Thread j arl 
As the topic shifted from backplane logic, I've moved to this
conversation to a new thread.

On Tuesday, June 28, 2016 04:02 PM, Grzegorz Kasprowicz wrote:
> For synchronisation over fibre we can use existing White Rabbit core.
> The card requires only 2 VCXO oscillators and FPGA logic. The WR core
> consumes 50% of small Spartan 45T. It ensures 1ns timing accuracy.

>We probably won't use White Rabbit as-is, but the basic principle will
>be the same. It can be a good idea to include those VCXOs on boards that
>may be synchronized over fiber (Kasli/Metlino), though can't we use
>instead a Si5324 for jitter cleanup and FPGA PLLs for DDMTD?

Heads up that the clock synchronization for Metlino resides on
Metlino_clk (Tongue 2) not Metlino_motherboard (Tongue 3-4). So
headers need to provide whatever io is required. Greg already has a
layout for a Metlino_clk board that has White Rabbit components on it.

Greg, do you have a short list of components required for
WhiteRabbit-type clock recovery?  -Joe
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Re: [ARTIQ] clock recovery on Metlino and Kasli

2016-06-29 Thread Grzegorz Kasprowicz 
Hi
The idea is to use SPEC board design: http://www.ohwr.org/projects/spec/wiki
It's well debugged. I designed it a few years ago and it's already 4-th
revision.
The WR components are:
1. 25MHz VCXO VM53S3-25.000-2.5/-30+75 + CDCM61004RHBT PLL chip. The two
can be replaced by 125MHz VCXO.
2. 20MHz helper VCXO for DDMTD : LF VCXO026156
3. 2x DAC AD5662BRMZ-1
4. 3V LDO : LP5951MF-3.0/NOPB
5. 2.5V reference: LM336M-2.5/NOPB
6. some LRC passives
Greg




On 29 June 2016 at 15:56, j arl  wrote:

> As the topic shifted from backplane logic, I've moved to this
> conversation to a new thread.
>
> On Tuesday, June 28, 2016 04:02 PM, Grzegorz Kasprowicz wrote:
> > For synchronisation over fibre we can use existing White Rabbit core.
> > The card requires only 2 VCXO oscillators and FPGA logic. The WR core
> > consumes 50% of small Spartan 45T. It ensures 1ns timing accuracy.
>
> >We probably won't use White Rabbit as-is, but the basic principle will
> >be the same. It can be a good idea to include those VCXOs on boards that
> >may be synchronized over fiber (Kasli/Metlino), though can't we use
> >instead a Si5324 for jitter cleanup and FPGA PLLs for DDMTD?
>
> Heads up that the clock synchronization for Metlino resides on
> Metlino_clk (Tongue 2) not Metlino_motherboard (Tongue 3-4). So
> headers need to provide whatever io is required. Greg already has a
> layout for a Metlino_clk board that has White Rabbit components on it.
>
> Greg, do you have a short list of components required for
> WhiteRabbit-type clock recovery?  -Joe
>
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