Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6
Sébastien, Given the relatively low cost of the Artix-7 FPGAs, my preference is generally to go as big and as fast as reasonably possible. I don't want to find that, for example, we can't fit a hard FPU/fancy servo on Kasli because we saved $50 on the FPGA. Also, since gateware development is usually much more expensive than hardware, I'd rather go for dumb/inefficient gateware on big FPGAs than have to optimise the gateware to fit on a smaller FPGA. The fact that going for a 75T/100T gives us access to 12EEMs/Kasli (4 on the BP) rather than 10EEMs/Kasli (only 2 on the BP) for the 50T is an added benefit. Having said all that, if you think the 50T in the -2 speed grade won't be a limitation then I'm happy to go along with your recommendation... T From: ARTIQ [artiq-boun...@lists.m-labs.hk] on behalf of artiq-requ...@lists.m-labs.hk [artiq-requ...@lists.m-labs.hk] Sent: 29 June 2017 11:00 To: artiq@lists.m-labs.hk Subject: ARTIQ Digest, Vol 37, Issue 6 Send ARTIQ mailing list submissions to artiq@lists.m-labs.hk To subscribe or unsubscribe via the World Wide Web, visit https://ssl.serverraum.org/lists/listinfo/artiq or, via email, send a message with subject or body 'help' to artiq-requ...@lists.m-labs.hk You can reach the person managing the list at artiq-ow...@lists.m-labs.hk When replying, please edit your Subject line so it is more specific than "Re: Contents of ARTIQ digest..." Today's Topics: 1. Kasli FPGA selection (Sébastien Bourdeauducq) -- Message: 1 Date: Thu, 29 Jun 2017 12:23:04 +0800 From: Sébastien Bourdeauducq To: Thomas Harty Cc: "artiq@lists.m-labs.hk" , Grzegorz Kasprowicz Subject: [ARTIQ] Kasli FPGA selection Message-ID: <25ce5ee0-1bbb-3b7c-851d-3e1bc9e29...@m-labs.hk> Content-Type: text/plain; charset=utf-8; format=flowed On Wednesday, June 28, 2017 04:52 PM, Thomas Harty wrote: > Have we settled on the 50T as the FPGA for the first version of Kasli, > and what speed grade? I would advocate for the 50T in -2 speed grade for two main reasons: a) I don't think we need that much FPGA resources for the 100T to be needed. b) -2 speed grade transceivers go to 6.25Gbps whereas -1 speed grade ones go to 3.75Gbps. In addition to a significant increase in bandwidth, the -2 transceivers can use the same configuration on the Metlino/Sayma side which is used for the backplane (5Gbps). Otherwise we would have to generate another set of Ultrascale transceiver settings (and shave a yak) and potentially deal with weird RTIO frequency ratios in a hybrid MTCA/Eurocard Sinara system. Sébastien -- Subject: Digest Footer ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq -- End of ARTIQ Digest, Vol 37, Issue 6 ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6
I second Tom's thoughts here -- I would go for the largest Artix-7 we can reasonably accommodate, just for flexibility. Going with the -2 speed grade sounds like it makes a lot of sense. Best, Daniel From: ARTIQ on behalf of Thomas Harty via ARTIQ Sent: Thursday, June 29, 2017 4:16:32 AM To: artiq@lists.m-labs.hk Subject: Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6 Sébastien, Given the relatively low cost of the Artix-7 FPGAs, my preference is generally to go as big and as fast as reasonably possible. I don't want to find that, for example, we can't fit a hard FPU/fancy servo on Kasli because we saved $50 on the FPGA. Also, since gateware development is usually much more expensive than hardware, I'd rather go for dumb/inefficient gateware on big FPGAs than have to optimise the gateware to fit on a smaller FPGA. The fact that going for a 75T/100T gives us access to 12EEMs/Kasli (4 on the BP) rather than 10EEMs/Kasli (only 2 on the BP) for the 50T is an added benefit. Having said all that, if you think the 50T in the -2 speed grade won't be a limitation then I'm happy to go along with your recommendation... T From: ARTIQ [artiq-boun...@lists.m-labs.hk] on behalf of artiq-requ...@lists.m-labs.hk [artiq-requ...@lists.m-labs.hk] Sent: 29 June 2017 11:00 To: artiq@lists.m-labs.hk Subject: ARTIQ Digest, Vol 37, Issue 6 Send ARTIQ mailing list submissions to artiq@lists.m-labs.hk To subscribe or unsubscribe via the World Wide Web, visit https://ssl.serverraum.org/lists/listinfo/artiq or, via email, send a message with subject or body 'help' to artiq-requ...@lists.m-labs.hk You can reach the person managing the list at artiq-ow...@lists.m-labs.hk When replying, please edit your Subject line so it is more specific than "Re: Contents of ARTIQ digest..." Today's Topics: 1. Kasli FPGA selection (Sébastien Bourdeauducq) -- Message: 1 Date: Thu, 29 Jun 2017 12:23:04 +0800 From: Sébastien Bourdeauducq To: Thomas Harty Cc: "artiq@lists.m-labs.hk" , Grzegorz Kasprowicz Subject: [ARTIQ] Kasli FPGA selection Message-ID: <25ce5ee0-1bbb-3b7c-851d-3e1bc9e29...@m-labs.hk> Content-Type: text/plain; charset=utf-8; format=flowed On Wednesday, June 28, 2017 04:52 PM, Thomas Harty wrote: > Have we settled on the 50T as the FPGA for the first version of Kasli, > and what speed grade? I would advocate for the 50T in -2 speed grade for two main reasons: a) I don't think we need that much FPGA resources for the 100T to be needed. b) -2 speed grade transceivers go to 6.25Gbps whereas -1 speed grade ones go to 3.75Gbps. In addition to a significant increase in bandwidth, the -2 transceivers can use the same configuration on the Metlino/Sayma side which is used for the backplane (5Gbps). Otherwise we would have to generate another set of Ultrascale transceiver settings (and shave a yak) and potentially deal with weird RTIO frequency ratios in a hybrid MTCA/Eurocard Sinara system. Sébastien -- Subject: Digest Footer ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq -- End of ARTIQ Digest, Vol 37, Issue 6 ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6
On Thursday, June 29, 2017 06:16 PM, Thomas Harty via ARTIQ wrote: The fact that going for a 75T/100T gives us access to 12EEMs/Kasli (4 on the BP) rather than 10EEMs/Kasli (only 2 on the BP) for the 50T is an added benefit. Kasli was meant to be a simple and low-cost board without a backplane, and you are now using the backplane as an argument... ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6
Octopart Avnet costs for 1 unit XC7A100T-2CSG324C $131.22 XC7A50T-2CSG324C $74.98 Greg, What is the cost differential between 50T-2 and 100T-2 assuming Xilinx open source pricing? -Joe ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6
Usually one can expect half of octopart prices. So the difference would be about 30$ On 29 June 2017 at 21:43, Joe Britton via ARTIQ wrote: > Octopart Avnet costs for 1 unit > > XC7A100T-2CSG324C $131.22 > XC7A50T-2CSG324C $74.98 > > Greg, What is the cost differential between 50T-2 and 100T-2 assuming > Xilinx open source pricing? -Joe > ___ > ARTIQ mailing list > https://ssl.serverraum.org/lists/listinfo/artiq > ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq
Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 7
no/Sayma > side which is used for the backplane (5Gbps). Otherwise we would have to > generate another set of Ultrascale transceiver settings (and shave a > yak) and potentially deal with weird RTIO frequency ratios in a hybrid > MTCA/Eurocard Sinara system. > > Sébastien > > > -- > > Subject: Digest Footer > > ___ > ARTIQ mailing list > https://ssl.serverraum.org/lists/listinfo/artiq > > -- > > End of ARTIQ Digest, Vol 37, Issue 6 > > > > -- > > Message: 2 > Date: Thu, 29 Jun 2017 12:27:17 + > From: "Slichter, Daniel H. (Fed)" > To: "'artiq@lists.m-labs.hk'" > Subject: Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6 > Message-ID: > > > > Content-Type: text/plain; charset="iso-8859-1" > > I second Tom's thoughts here -- I would go for the largest Artix-7 we can > reasonably accommodate, just for flexibility. Going with the -2 speed grade > sounds like it makes a lot of sense. > > > Best, > > Daniel > > > From: ARTIQ on behalf of Thomas Harty via > ARTIQ > Sent: Thursday, June 29, 2017 4:16:32 AM > To: artiq@lists.m-labs.hk > Subject: Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6 > > Sébastien, > > Given the relatively low cost of the Artix-7 FPGAs, my preference is > generally to go as big and as fast as reasonably possible. I don't want to > find that, for example, we can't fit a hard FPU/fancy servo on Kasli because > we saved $50 on the FPGA. Also, since gateware development is usually much > more expensive than hardware, I'd rather go for dumb/inefficient gateware on > big FPGAs than have to optimise the gateware to fit on a smaller FPGA. > > The fact that going for a 75T/100T gives us access to 12EEMs/Kasli (4 on the > BP) rather than 10EEMs/Kasli (only 2 on the BP) for the 50T is an added > benefit. > > Having said all that, if you think the 50T in the -2 speed grade won't be a > limitation then I'm happy to go along with your recommendation... > > T > > > From: ARTIQ [artiq-boun...@lists.m-labs.hk] on behalf of > artiq-requ...@lists.m-labs.hk [artiq-requ...@lists.m-labs.hk] > Sent: 29 June 2017 11:00 > To: artiq@lists.m-labs.hk > Subject: ARTIQ Digest, Vol 37, Issue 6 > > Send ARTIQ mailing list submissions to >artiq@lists.m-labs.hk > > To subscribe or unsubscribe via the World Wide Web, visit >https://ssl.serverraum.org/lists/listinfo/artiq > or, via email, send a message with subject or body 'help' to >artiq-requ...@lists.m-labs.hk > > You can reach the person managing the list at >artiq-ow...@lists.m-labs.hk > > When replying, please edit your Subject line so it is more specific > than "Re: Contents of ARTIQ digest..." > > > Today's Topics: > > 1. Kasli FPGA selection (Sébastien Bourdeauducq) > > > -- > > Message: 1 > Date: Thu, 29 Jun 2017 12:23:04 +0800 > From: Sébastien Bourdeauducq > To: Thomas Harty > Cc: "artiq@lists.m-labs.hk" , Grzegorz >Kasprowicz > Subject: [ARTIQ] Kasli FPGA selection > Message-ID: <25ce5ee0-1bbb-3b7c-851d-3e1bc9e29...@m-labs.hk> > Content-Type: text/plain; charset=utf-8; format=flowed > > On Wednesday, June 28, 2017 04:52 PM, Thomas Harty wrote: >> Have we settled on the 50T as the FPGA for the first version of Kasli, >> and what speed grade? > > I would advocate for the 50T in -2 speed grade for two main reasons: > a) I don't think we need that much FPGA resources for the 100T to be needed. > b) -2 speed grade transceivers go to 6.25Gbps whereas -1 speed grade > ones go to 3.75Gbps. In addition to a significant increase in bandwidth, > the -2 transceivers can use the same configuration on the Metlino/Sayma > side which is used for the backplane (5Gbps). Otherwise we would have to > generate another set of Ultrascale transceiver settings (and shave a > yak) and potentially deal with weird RTIO frequency ratios in a hybrid > MTCA/Eurocard Sinara system. > > Sébastien > > > -- > > Subject: Digest Footer > > ___ > ARTIQ mailing list > https://ssl.serverraum.org/lists/listinfo/artiq > > -- > > End of ARTIQ Digest, Vol 37, Issue 6 > *
Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 7
rset=utf-8; format=flowed >> >> On Wednesday, June 28, 2017 04:52 PM, Thomas Harty wrote: >>> Have we settled on the 50T as the FPGA for the first version of Kasli, >>> and what speed grade? >> >> I would advocate for the 50T in -2 speed grade for two main reasons: >> a) I don't think we need that much FPGA resources for the 100T to be needed. >> b) -2 speed grade transceivers go to 6.25Gbps whereas -1 speed grade >> ones go to 3.75Gbps. In addition to a significant increase in bandwidth, >> the -2 transceivers can use the same configuration on the Metlino/Sayma >> side which is used for the backplane (5Gbps). Otherwise we would have to >> generate another set of Ultrascale transceiver settings (and shave a >> yak) and potentially deal with weird RTIO frequency ratios in a hybrid >> MTCA/Eurocard Sinara system. >> >> Sébastien >> >> >> -- >> >> Subject: Digest Footer >> >> ___ >> ARTIQ mailing list >> https://ssl.serverraum.org/lists/listinfo/artiq >> >> -- >> >> End of ARTIQ Digest, Vol 37, Issue 6 >> >> >> >> -- >> >> Message: 2 >> Date: Thu, 29 Jun 2017 12:27:17 + >> From: "Slichter, Daniel H. (Fed)" >> To: "'artiq@lists.m-labs.hk'" >> Subject: Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6 >> Message-ID: >> >> >> >> Content-Type: text/plain; charset="iso-8859-1" >> >> I second Tom's thoughts here -- I would go for the largest Artix-7 we can >> reasonably accommodate, just for flexibility. Going with the -2 speed grade >> sounds like it makes a lot of sense. >> >> >> Best, >> >> Daniel >> >> >> From: ARTIQ on behalf of Thomas Harty via >> ARTIQ >> Sent: Thursday, June 29, 2017 4:16:32 AM >> To: artiq@lists.m-labs.hk >> Subject: Re: [ARTIQ] ARTIQ Digest, Vol 37, Issue 6 >> >> Sébastien, >> >> Given the relatively low cost of the Artix-7 FPGAs, my preference is >> generally to go as big and as fast as reasonably possible. I don't want to >> find that, for example, we can't fit a hard FPU/fancy servo on Kasli because >> we saved $50 on the FPGA. Also, since gateware development is usually much >> more expensive than hardware, I'd rather go for dumb/inefficient gateware on >> big FPGAs than have to optimise the gateware to fit on a smaller FPGA. >> >> The fact that going for a 75T/100T gives us access to 12EEMs/Kasli (4 on the >> BP) rather than 10EEMs/Kasli (only 2 on the BP) for the 50T is an added >> benefit. >> >> Having said all that, if you think the 50T in the -2 speed grade won't be a >> limitation then I'm happy to go along with your recommendation... >> >> T >> >> >> From: ARTIQ [artiq-boun...@lists.m-labs.hk] on behalf of >> artiq-requ...@lists.m-labs.hk [artiq-requ...@lists.m-labs.hk] >> Sent: 29 June 2017 11:00 >> To: artiq@lists.m-labs.hk >> Subject: ARTIQ Digest, Vol 37, Issue 6 >> >> Send ARTIQ mailing list submissions to >>artiq@lists.m-labs.hk >> >> To subscribe or unsubscribe via the World Wide Web, visit >>https://ssl.serverraum.org/lists/listinfo/artiq >> or, via email, send a message with subject or body 'help' to >>artiq-requ...@lists.m-labs.hk >> >> You can reach the person managing the list at >>artiq-ow...@lists.m-labs.hk >> >> When replying, please edit your Subject line so it is more specific >> than "Re: Contents of ARTIQ digest..." >> >> >> Today's Topics: >> >> 1. Kasli FPGA selection (Sébastien Bourdeauducq) >> >> >> -- >> >> Message: 1 >> Date: Thu, 29 Jun 2017 12:23:04 +0800 >> From: Sébastien Bourdeauducq >> To: Thomas Harty >> Cc: "artiq@lists.m-labs.hk" , Grzegorz >>Kasprowicz >> Subject: [ARTIQ] Kasli FPGA selection >> Message-ID: <25ce5ee0-1bbb-3b7c-851d-3e1bc9e29...@m-labs.hk> >> Content-Type: text/plain; charset=utf-8; format=flowed >> >> On Wednesday, June 28, 2017 04:52 PM, Thomas Harty wrote: >>> Have we settled on the 50T as the FPGA for the first version of Kasli,
[ARTIQ] program files for testing Sinara
I've posted some of the ARTIQ program files I'm using to test the Sinara gateware/software. https://github.com/jbqubit/sinara-testing -Joe ___ ARTIQ mailing list https://ssl.serverraum.org/lists/listinfo/artiq