[PATCH 3/3] ci: add a job for testing 64BIT MIPS with labgrid
Signed-off-by: Denis Orlov --- .github/workflows/test-labgrid-pytest.yml | 4 1 file changed, 4 insertions(+) diff --git a/.github/workflows/test-labgrid-pytest.yml b/.github/workflows/test-labgrid-pytest.yml index 2c74150066..674e4251d1 100644 --- a/.github/workflows/test-labgrid-pytest.yml +++ b/.github/workflows/test-labgrid-pytest.yml @@ -26,6 +26,10 @@ jobs: lgenv: test/mips/qemu-malta_defconfig.yaml defconfig: qemu-malta_defconfig + - ARCH: mips +lgenv: test/mips/qemu-malta64el_defconfig.yaml +defconfig: qemu-malta64el_defconfig + - ARCH: x86 lgenv: test/x86/efi_defconfig.yaml defconfig: efi_defconfig -- 2.41.0
[PATCH 2/3] test: mips: add QEMU Malta 64le labgrid config
Signed-off-by: Denis Orlov
---
test/mips/qemu-malta64el_defconfig.yaml | 22 ++
1 file changed, 22 insertions(+)
create mode 100644 test/mips/qemu-malta64el_defconfig.yaml
diff --git a/test/mips/qemu-malta64el_defconfig.yaml
b/test/mips/qemu-malta64el_defconfig.yaml
new file mode 100644
index 00..22562d5b7a
--- /dev/null
+++ b/test/mips/qemu-malta64el_defconfig.yaml
@@ -0,0 +1,22 @@
+targets:
+ main:
+drivers:
+ QEMUDriver:
+qemu_bin: qemu
+machine: malta
+cpu: 5KEf
+memory: 256M
+bios: barebox-qemu-malta.img.swapped
+extra_args: ''
+ BareboxDriver:
+prompt: 'barebox@[^:]+:[^ ]+ '
+bootstring: 'commandline:'
+ BareboxTestStrategy: {}
+features:
+ - virtio-pci
+images:
+ barebox-qemu-malta.img.swapped: !template
"$LG_BUILDDIR/images/barebox-qemu-malta.img.swapped"
+tools:
+ qemu: /usr/bin/qemu-system-mips64el
+imports:
+ - ../strategy.py
--
2.41.0
[PATCH 1/3] MIPS: add qemu-malta64el_defconfig
This defconfig will compile barebox for Malta board and MIPS64 5KEc/5KEf CPUs, emulatable in QEMU. The analogous 32-bit defconfig uses big endian CPU as the default one. So, for the sake of variety, and to improve the coverage of options, set the CPU as little endian for this one. Signed-off-by: Denis Orlov --- arch/mips/configs/qemu-malta64el_defconfig | 87 ++ 1 file changed, 87 insertions(+) create mode 100644 arch/mips/configs/qemu-malta64el_defconfig diff --git a/arch/mips/configs/qemu-malta64el_defconfig b/arch/mips/configs/qemu-malta64el_defconfig new file mode 100644 index 00..5fb090a646 --- /dev/null +++ b/arch/mips/configs/qemu-malta64el_defconfig @@ -0,0 +1,87 @@ +CONFIG_BOARD_QEMU_MALTA=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS64_R2=y +CONFIG_64BIT=y +CONFIG_IMAGE_COMPRESSION_XZKERN=y +CONFIG_BAREBOX_MAX_IMAGE_SIZE=0x40 +CONFIG_STACK_SIZE=0x7000 +CONFIG_EXPERIMENTAL=y +CONFIG_BAUDRATE=38400 +CONFIG_HUSH_FANCY_PROMPT=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_MENU=y +CONFIG_BOOTM_SHOW_TYPE=y +CONFIG_CONSOLE_ALLOW_COLOR=y +CONFIG_PARTITION=y +CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y +CONFIG_CMD_DMESG=y +CONFIG_LONGHELP=y +CONFIG_CMD_IOMEM=y +CONFIG_CMD_IMD=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_GO=y +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADY=y +CONFIG_CMD_RESET=y +CONFIG_CMD_PARTITION=y +CONFIG_CMD_EXPORT=y +CONFIG_CMD_DEFAULTENV=y +CONFIG_CMD_LOADENV=y +CONFIG_CMD_PRINTENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_SHA1SUM=y +CONFIG_CMD_SHA256SUM=y +CONFIG_CMD_UNCOMPRESS=y +CONFIG_CMD_SLEEP=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MIITOOL=y +CONFIG_CMD_PING=y +CONFIG_CMD_TFTP=y +CONFIG_CMD_ECHO_E=y +CONFIG_CMD_EDIT=y +CONFIG_CMD_LOGIN=y +CONFIG_CMD_MENU=y +CONFIG_CMD_MENU_MANAGEMENT=y +CONFIG_CMD_PASSWD=y +CONFIG_CMD_FBTEST=y +CONFIG_CMD_READLINE=y +CONFIG_CMD_TIMEOUT=y +CONFIG_CMD_CRC=y +CONFIG_CMD_CRC_CMP=y +CONFIG_CMD_FLASH=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_OF_NODE=y +CONFIG_CMD_OF_PROPERTY=y +CONFIG_CMD_OFTREE=y +CONFIG_CMD_TIME=y +CONFIG_NET=y +CONFIG_NET_NFS=y +CONFIG_NET_NETCONSOLE=y +CONFIG_OFDEVICE=y +CONFIG_OF_BAREBOX_DRIVERS=y +CONFIG_DRIVER_NET_RTL8139=y +# CONFIG_SPI is not set +CONFIG_I2C=y +CONFIG_I2C_GPIO=y +CONFIG_MTD=y +CONFIG_DRIVER_CFI=y +# CONFIG_DRIVER_CFI_AMD is not set +# CONFIG_DRIVER_CFI_BANK_WIDTH_1 is not set +# CONFIG_DRIVER_CFI_BANK_WIDTH_2 is not set +CONFIG_CFI_BUFFER_WRITE=y +CONFIG_VIDEO=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_DRIVER_VIDEO_BOCHS_PCI=y +CONFIG_GPIO_MALTA_FPGA_I2C=y +CONFIG_PCI=y +CONFIG_PCI_DEBUG=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_FS_CRAMFS=y +CONFIG_FS_TFTP=y +CONFIG_FS_FAT=y +CONFIG_FS_FAT_WRITE=y +CONFIG_FS_FAT_LFN=y -- 2.41.0
[PATCH 0/3] Add CI for MIPS64
This adds a necessary defconfig and labgrid configuration file together with the corresponding CI job for building and testing the MIPS image with 64BIT option set. I've decided against giving the defconfig a generic name such as mips64_defconfig. For now, only Malta running in QEMU is really supported, so naming it as that seems more fitting for me. And if more MIPS64 boards will get support in the future, then this defconfig might be renamed appropriately. Denis Orlov (3): MIPS: add qemu-malta64el_defconfig test: mips: add QEMU Malta 64le labgrid config ci: add a job for testing 64BIT MIPS with labgrid .github/workflows/test-labgrid-pytest.yml | 4 + arch/mips/configs/qemu-malta64el_defconfig | 87 ++ test/mips/qemu-malta64el_defconfig.yaml| 22 ++ 3 files changed, 113 insertions(+) create mode 100644 arch/mips/configs/qemu-malta64el_defconfig create mode 100644 test/mips/qemu-malta64el_defconfig.yaml -- 2.41.0
Re: [PATCH 09/18] cdev: record whether partition is parsed from OF
On 31.05.23 19:04, Marco Felsch wrote:
> Hi Ahmad,
>
> On 23-05-31, Ahmad Fatoum wrote:
>> Later code will make it possible to define a on-disk-described partition
>> in the DT as well. For this reason, we can't assumed
>> DEVFS_PARTITION_FROM_TABLE to mean !DT, so let's add a dedicated flag
>> for that.
>>
>> Signed-off-by: Ahmad Fatoum
>> ---
>> drivers/of/partition.c | 5 +++--
>> fs/fs.c| 2 ++
>> include/driver.h | 5 +++--
>> 3 files changed, 8 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/of/partition.c b/drivers/of/partition.c
>> index a70e503cec9e..15943502ce17 100644
>> --- a/drivers/of/partition.c
>> +++ b/drivers/of/partition.c
>> @@ -74,6 +74,7 @@ struct cdev *of_parse_partition(struct cdev *cdev, struct
>> device_node *node)
>> }
>>
>> new->device_node = node;
>> +new->flags |= DEVFS_PARTITION_FROM_OF;
>>
>> if (IS_ENABLED(CONFIG_NVMEM) && of_device_is_compatible(node,
>> "nvmem-cells")) {
>> struct nvmem_device *nvmem = nvmem_partition_register(new);
>> @@ -162,7 +163,7 @@ int of_fixup_partitions(struct device_node *np, struct
>> cdev *cdev)
>> return 0;
>>
>> list_for_each_entry(partcdev, >partitions, partition_entry) {
>> -if (partcdev->flags & DEVFS_PARTITION_FROM_TABLE)
>> +if (!(partcdev->flags & DEVFS_PARTITION_FROM_OF))
>
> Even though the code is already 'open-coded' I would suggest a macro like:
>
> is_of_partition_cdev() or cdev_is_of_partition().
DEVFS_PARTITION_FROM_OF is set in this file and it's read in this file.
I don't think having an indirection through a helper would bring much
benefit.
>
> Reviewed-by: Marco Felsch
>
>> continue;
>> n_parts++;
>> }
>> @@ -213,7 +214,7 @@ int of_fixup_partitions(struct device_node *np, struct
>> cdev *cdev)
>> u8 tmp[16 * 16]; /* Up to 64-bit address + 64-bit size */
>> loff_t partoffset;
>>
>> -if (partcdev->flags & DEVFS_PARTITION_FROM_TABLE)
>> +if (!(partcdev->flags & DEVFS_PARTITION_FROM_OF))
>> continue;
>>
>> if (partcdev->mtd)
>> diff --git a/fs/fs.c b/fs/fs.c
>> index 1820e48393af..9d8aab268ca4 100644
>> --- a/fs/fs.c
>> +++ b/fs/fs.c
>> @@ -88,6 +88,8 @@ void cdev_print(const struct cdev *cdev)
>> printf(" fixed-partition");
>> if (cdev->flags & DEVFS_PARTITION_READONLY)
>> printf(" readonly-partition");
>> +if (cdev->flags & DEVFS_PARTITION_FROM_OF)
>> +printf(" of-partition");
>> if (cdev->flags & DEVFS_PARTITION_FROM_TABLE)
>> printf(" table-partition");
>> if (cdev->flags & DEVFS_IS_MCI_MAIN_PART_DEV)
>> diff --git a/include/driver.h b/include/driver.h
>> index 42e513a15603..118d2adb6750 100644
>> --- a/include/driver.h
>> +++ b/include/driver.h
>> @@ -584,8 +584,9 @@ extern struct list_head cdev_list;
>> #define DEVFS_PARTITION_FIXED (1U << 0)
>> #define DEVFS_PARTITION_READONLY(1U << 1)
>> #define DEVFS_IS_CHARACTER_DEV (1U << 3)
>> -#define DEVFS_PARTITION_FROM_TABLE (1U << 4)
>> -#define DEVFS_IS_MCI_MAIN_PART_DEV (1U << 5)
>> +#define DEVFS_IS_MCI_MAIN_PART_DEV (1U << 4)
>> +#define DEVFS_PARTITION_FROM_OF (1U << 5)
>> +#define DEVFS_PARTITION_FROM_TABLE (1U << 6)
>>
>> struct cdev *devfs_add_partition(const char *devname, loff_t offset,
>> loff_t size, unsigned int flags, const char *name);
>> --
>> 2.39.2
>>
>>
>>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 11/18] block: parse partition table on block device registration
On 01.06.23 09:42, Sascha Hauer wrote:
> On Wed, May 31, 2023 at 04:59:20PM +0200, Ahmad Fatoum wrote:
>> Every instance where we register a block device, it's followed by an
>> attempt to parse the partition table, most often with a warning when
>> it fails. Thus let's move partition table parsing into
>> blockdevice_register.
>>
>> Signed-off-by: Ahmad Fatoum
>> ---
>> arch/sandbox/board/hostfile.c | 4
>> common/block.c| 6 ++
>> drivers/ata/disk_ata_drive.c | 5 -
>> drivers/block/efi-block-io.c | 9 +
>> drivers/block/virtio_blk.c| 8 +---
>> drivers/mci/mci-core.c| 6 --
>> drivers/nvme/host/core.c | 5 -
>> drivers/usb/storage/usb.c | 5 -
>> 8 files changed, 8 insertions(+), 40 deletions(-)
>>
>> diff --git a/arch/sandbox/board/hostfile.c b/arch/sandbox/board/hostfile.c
>> index d0f400787d7a..a1ab06b87770 100644
>> --- a/arch/sandbox/board/hostfile.c
>> +++ b/arch/sandbox/board/hostfile.c
>> @@ -166,10 +166,6 @@ static int hf_probe(struct device *dev)
>> if (err)
>> return err;
>>
>> -err = parse_partition_table(>blk);
>> -if (err)
>> -dev_warn(dev, "No partition table found\n");
>> -
>> dev_info(dev, "registered as block device\n");
>> } else {
>> cdev->name = np->name;
>> diff --git a/common/block.c b/common/block.c
>> index c39269d3a692..98adcfdf3dab 100644
>> --- a/common/block.c
>> +++ b/common/block.c
>> @@ -6,6 +6,7 @@
>> */
>> #include
>> #include
>> +#include
>> #include
>> #include
>> #include
>> @@ -408,6 +409,11 @@ int blockdevice_register(struct block_device *blk)
>>
>> cdev_create_default_automount(>cdev);
>>
>> +/* Lack of partition table is unusual, but not a failure */
>> +ret = parse_partition_table(blk);
>> +if (ret)
>> +dev_warn(blk->dev, "No partition table found\n");
>
> This is not changed in this series, so it's ok like this, but should
> this really be a warning? Using a raw device without a partition table
> seems like a legitimate usecase.
parse_partition_table returns 0 when no partition table exists. Now that
I looked into it, all errors already have an error print, so duplicating
it is unnecessary. I will drop the dev_warn altogether for v2.
>
> Sascha
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 17/18] common: partitions: efi: record type UUID in cdev
On 31.05.23 21:31, Marco Felsch wrote:
> Hi Ahmad,
>
> On 23-05-31, Ahmad Fatoum wrote:
>> We already record DOS partition type in cdev, so let's do the same for
>> GPT Type UUID. This will be used in a later commit to identify
>> barebox-state partitions.
>>
>> Signed-off-by: Ahmad Fatoum
>> ---
>> common/partitions.c| 2 +-
>> common/partitions/efi.c| 1 +
>> common/partitions/parser.h | 5 -
>> fs/fs.c| 2 ++
>> include/driver.h | 6 +-
>> 5 files changed, 13 insertions(+), 3 deletions(-)
>>
>> diff --git a/common/partitions.c b/common/partitions.c
>> index b579559672a0..e3e8a9f3044d 100644
>> --- a/common/partitions.c
>> +++ b/common/partitions.c
>> @@ -50,7 +50,7 @@ static int register_one_partition(struct block_device *blk,
>>
>> cdev->flags |= DEVFS_PARTITION_FROM_TABLE;
>>
>> -cdev->dos_partition_type = part->dos_partition_type;
>> +cdev->typeuuid = part->typeuuid;
>
> Even though it's an union I would prefer to make it easier for the
> reader (without checking the header and noticing that it is an union).
> So the above code would be:
>
> if (blkdev_is_gpt_partitioned(blk))
> cdev->typeuuid = part->typeuuid;
> else if (blkdev_is_mbr_partitioned(blk))
> cdev->dos_partition_type = part->dos_partition_type;
I don't think this is implementable without a runtime cost. I'd leave
it as is.
>
> with
>
> static inline blkdev_is_gpt_partitioned(struct block_device *blkdev)
> {
> return cdev_is_gpt_partitioned(>cdev);
> }
>
> Regards,
> Marco
>
>> strcpy(cdev->partuuid, part->partuuid);
>>
>> free(partition_name);
>> diff --git a/common/partitions/efi.c b/common/partitions/efi.c
>> index df63b82afe24..2756337ab284 100644
>> --- a/common/partitions/efi.c
>> +++ b/common/partitions/efi.c
>> @@ -471,6 +471,7 @@ static void efi_partition(void *buf, struct block_device
>> *blk,
>> pentry->size++;
>> part_set_efi_name([i], pentry->name);
>> snprintf(pentry->partuuid, sizeof(pentry->partuuid), "%pUl",
>> [i].unique_partition_guid);
>> +pentry->typeuuid = ptes[i].partition_type_guid;
>> pd->used_entries++;
>> }
>> }
>> diff --git a/common/partitions/parser.h b/common/partitions/parser.h
>> index f2f692f7903b..9cc41a7573fe 100644
>> --- a/common/partitions/parser.h
>> +++ b/common/partitions/parser.h
>> @@ -17,10 +17,13 @@
>>
>> struct partition {
>> char name[MAX_PARTITION_NAME];
>> -u8 dos_partition_type;
>> char partuuid[MAX_UUID_STR];
>> uint64_t first_sec;
>> uint64_t size;
>> +union {
>> +u8 dos_partition_type;
>> +guid_t typeuuid;
>> +};
>> };
>>
>> struct partition_desc {
>> diff --git a/fs/fs.c b/fs/fs.c
>> index 9a92e6e251e5..16cc072adfaf 100644
>> --- a/fs/fs.c
>> +++ b/fs/fs.c
>> @@ -110,6 +110,8 @@ void cdev_print(const struct cdev *cdev)
>> nbytes += printf("Filetype: %s\t",
>> file_type_to_string(cdev->filetype));
>> if (cdev_is_mbr_partitioned(cdev->master))
>> nbytes += printf("DOS parttype: 0x%02x\t",
>> cdev->dos_partition_type);
>> +else if (cdev_is_gpt_partitioned(cdev->master))
>> +nbytes += printf("GPT typeuuid: %pUl\t", >typeuuid);
>> if (*cdev->partuuid || *cdev->diskuuid)
>> nbytes += printf("%sUUID: %s", cdev_is_partition(cdev) ? "PART"
>> : "DISK",
>> cdev_is_partition(cdev) ? cdev->partuuid :
>> cdev->diskuuid);
>> diff --git a/include/driver.h b/include/driver.h
>> index 5f2eae65466f..6407f7d6ba36 100644
>> --- a/include/driver.h
>> +++ b/include/driver.h
>> @@ -8,6 +8,7 @@
>>
>> #include
>> #include
>> +#include
>> #include
>> #include
>>
>> @@ -536,12 +537,15 @@ struct cdev {
>> unsigned int flags;
>> int open;
>> struct mtd_info *mtd;
>> -u8 dos_partition_type;
>> struct cdev *link;
>> struct list_head link_entry, links;
>> struct list_head partition_entry, partitions;
>> struct cdev *master;
>> enum filetype filetype;
>> +union {
>> +u8 dos_partition_type;
>> +guid_t typeuuid;
>> +};
>> };
>>
>> int devfs_create(struct cdev *);
>> --
>> 2.39.2
>>
>>
>>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH v2 3/3] ARM: i.MX8MM: add Phytec i.MX8 SoM support
On 06.06.23 16:53, Marc Kleine-Budde wrote:
> Signed-off-by: Marc Kleine-Budde
> ---
> arch/arm/boards/Makefile |1 +
> arch/arm/boards/phytec-som-imx8mm/Makefile |4 +
> arch/arm/boards/phytec-som-imx8mm/board.c | 40 +
> .../flash-header-imx8mm-phyboard-polis-rdk.imxcfg |7 +
> arch/arm/boards/phytec-som-imx8mm/lowlevel.c | 130 ++
> arch/arm/boards/phytec-som-imx8mm/lowlevel.h |8 +
> arch/arm/boards/phytec-som-imx8mm/lpddr4-timing.c | 1852
>
> arch/arm/dts/Makefile |1 +
> arch/arm/dts/imx8mm-phyboard-polis-rdk.dts | 60 +
> arch/arm/mach-imx/Kconfig | 48 +
> images/Makefile.imx|5 +
> 11 files changed, 2156 insertions(+)
>
> diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
> index 2877debad535..1222ef80feb1 100644
> --- a/arch/arm/boards/Makefile
> +++ b/arch/arm/boards/Makefile
> @@ -95,6 +95,7 @@ obj-$(CONFIG_MACH_PHYTEC_SOM_AM335X)+=
> phytec-som-am335x/
> obj-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += phytec-som-imx6/
> obj-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += phytec-phycore-imx7/
> obj-$(CONFIG_MACH_PHYTEC_PHYCORE_STM32MP1) += phytec-phycore-stm32mp1/
> +obj-$(CONFIG_MACH_PHYTEC_SOM_IMX8MM) += phytec-som-imx8mm/
> obj-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += phytec-som-imx8mq/
> obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += plathome-openblocks-ax3/
> obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6)+= plathome-openblocks-a6/
> diff --git a/arch/arm/boards/phytec-som-imx8mm/Makefile
> b/arch/arm/boards/phytec-som-imx8mm/Makefile
> new file mode 100644
> index ..10abebc53921
> --- /dev/null
> +++ b/arch/arm/boards/phytec-som-imx8mm/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +
> +lwl-y += lowlevel.o lpddr4-timing.o
> +obj-y += board.o
> diff --git a/arch/arm/boards/phytec-som-imx8mm/board.c
> b/arch/arm/boards/phytec-som-imx8mm/board.c
> new file mode 100644
> index ..52f821f5fa30
> --- /dev/null
> +++ b/arch/arm/boards/phytec-som-imx8mm/board.c
> @@ -0,0 +1,40 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +static int phyboard_polis_rdk_probe(struct device *dev)
> +{
> + int emmc_bbu_flag = 0;
> + int sd_bbu_flag = 0;
> +
> + if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() ==
> 1) {
> + of_device_enable_path("/chosen/environment-sd");
> + sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
> + } else {
> + of_device_enable_path("/chosen/environment-emmc");
> + emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
> + }
> +
> + imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2",
> emmc_bbu_flag);
> + imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox",
> sd_bbu_flag);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id phyboard_polis_rdk_of_match[] = {
> + { .compatible = "phytec,imx8mm-phyboard-polis-rdk" },
> + { /* sentinel */ },
> +};
> +BAREBOX_DEEP_PROBE_ENABLE(phyboard_polis_rdk_of_match);
> +
> +static struct driver phyboard_polis_rdkboard_driver = {
> + .name = "board-phyboard-polis-rdk",
> + .probe = phyboard_polis_rdk_probe,
> + .of_compatible = DRV_OF_COMPAT(phyboard_polis_rdk_of_match),
> +};
> +coredevice_platform_driver(phyboard_polis_rdkboard_driver);
> diff --git
> a/arch/arm/boards/phytec-som-imx8mm/flash-header-imx8mm-phyboard-polis-rdk.imxcfg
>
> b/arch/arm/boards/phytec-som-imx8mm/flash-header-imx8mm-phyboard-polis-rdk.imxcfg
> new file mode 100644
> index ..10606ce29c96
> --- /dev/null
> +++
> b/arch/arm/boards/phytec-som-imx8mm/flash-header-imx8mm-phyboard-polis-rdk.imxcfg
> @@ -0,0 +1,7 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +
> +soc imx8mm
> +
> +loadaddr 0x007e1000
> +max_load_size 0x3f000
> +ivtofs 0x400
> diff --git a/arch/arm/boards/phytec-som-imx8mm/lowlevel.c
> b/arch/arm/boards/phytec-som-imx8mm/lowlevel.c
> new file mode 100644
> index ..d66f6f79f1c4
> --- /dev/null
> +++ b/arch/arm/boards/phytec-som-imx8mm/lowlevel.c
> @@ -0,0 +1,130 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "lowlevel.h"
> +
> +extern char __dtb_z_imx8mm_phyboard_polis_rdk_start[];
> +
> +#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
> +
> +static void setup_uart(void)
> +{
> + void __iomem *uart = IOMEM(MX8M_UART3_BASE_ADDR);
> +
> + imx8m_early_setup_uart_clock();
> +
> + imx8mm_setup_pad(IMX8MM_PAD_UART3_TXD_UART3_TX | UART_PAD_CTRL);
[PATCH v2 3/3] ARM: i.MX8MM: add Phytec i.MX8 SoM support
Signed-off-by: Marc Kleine-Budde
---
arch/arm/boards/Makefile |1 +
arch/arm/boards/phytec-som-imx8mm/Makefile |4 +
arch/arm/boards/phytec-som-imx8mm/board.c | 40 +
.../flash-header-imx8mm-phyboard-polis-rdk.imxcfg |7 +
arch/arm/boards/phytec-som-imx8mm/lowlevel.c | 130 ++
arch/arm/boards/phytec-som-imx8mm/lowlevel.h |8 +
arch/arm/boards/phytec-som-imx8mm/lpddr4-timing.c | 1852
arch/arm/dts/Makefile |1 +
arch/arm/dts/imx8mm-phyboard-polis-rdk.dts | 60 +
arch/arm/mach-imx/Kconfig | 48 +
images/Makefile.imx|5 +
11 files changed, 2156 insertions(+)
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 2877debad535..1222ef80feb1 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -95,6 +95,7 @@ obj-$(CONFIG_MACH_PHYTEC_SOM_AM335X) +=
phytec-som-am335x/
obj-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += phytec-som-imx6/
obj-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += phytec-phycore-imx7/
obj-$(CONFIG_MACH_PHYTEC_PHYCORE_STM32MP1) += phytec-phycore-stm32mp1/
+obj-$(CONFIG_MACH_PHYTEC_SOM_IMX8MM) += phytec-som-imx8mm/
obj-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += phytec-som-imx8mq/
obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += plathome-openblocks-ax3/
obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += plathome-openblocks-a6/
diff --git a/arch/arm/boards/phytec-som-imx8mm/Makefile
b/arch/arm/boards/phytec-som-imx8mm/Makefile
new file mode 100644
index ..10abebc53921
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx8mm/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o lpddr4-timing.o
+obj-y += board.o
diff --git a/arch/arm/boards/phytec-som-imx8mm/board.c
b/arch/arm/boards/phytec-som-imx8mm/board.c
new file mode 100644
index ..52f821f5fa30
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx8mm/board.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix
+
+#include
+#include
+#include
+#include
+#include
+
+static int phyboard_polis_rdk_probe(struct device *dev)
+{
+ int emmc_bbu_flag = 0;
+ int sd_bbu_flag = 0;
+
+ if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() ==
1) {
+ of_device_enable_path("/chosen/environment-sd");
+ sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ } else {
+ of_device_enable_path("/chosen/environment-emmc");
+ emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ }
+
+ imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2",
emmc_bbu_flag);
+ imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox",
sd_bbu_flag);
+
+ return 0;
+}
+
+static const struct of_device_id phyboard_polis_rdk_of_match[] = {
+ { .compatible = "phytec,imx8mm-phyboard-polis-rdk" },
+ { /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(phyboard_polis_rdk_of_match);
+
+static struct driver phyboard_polis_rdkboard_driver = {
+ .name = "board-phyboard-polis-rdk",
+ .probe = phyboard_polis_rdk_probe,
+ .of_compatible = DRV_OF_COMPAT(phyboard_polis_rdk_of_match),
+};
+coredevice_platform_driver(phyboard_polis_rdkboard_driver);
diff --git
a/arch/arm/boards/phytec-som-imx8mm/flash-header-imx8mm-phyboard-polis-rdk.imxcfg
b/arch/arm/boards/phytec-som-imx8mm/flash-header-imx8mm-phyboard-polis-rdk.imxcfg
new file mode 100644
index ..10606ce29c96
--- /dev/null
+++
b/arch/arm/boards/phytec-som-imx8mm/flash-header-imx8mm-phyboard-polis-rdk.imxcfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+soc imx8mm
+
+loadaddr 0x007e1000
+max_load_size 0x3f000
+ivtofs 0x400
diff --git a/arch/arm/boards/phytec-som-imx8mm/lowlevel.c
b/arch/arm/boards/phytec-som-imx8mm/lowlevel.c
new file mode 100644
index ..d66f6f79f1c4
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx8mm/lowlevel.c
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "lowlevel.h"
+
+extern char __dtb_z_imx8mm_phyboard_polis_rdk_start[];
+
+#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
+
+static void setup_uart(void)
+{
+ void __iomem *uart = IOMEM(MX8M_UART3_BASE_ADDR);
+
+ imx8m_early_setup_uart_clock();
+
+ imx8mm_setup_pad(IMX8MM_PAD_UART3_TXD_UART3_TX | UART_PAD_CTRL);
+ imx8m_uart_setup(uart);
+
+ pbl_set_putc(imx_uart_putc, uart);
+ putc_ll('>');
+}
+
+#define EEPROM_ADDR 0x51
+#define EEPROM_ADDR_FALLBACK 0x59
+
+static void phyboard_polis_rdk_ddr_init(void)
+{
+ struct pbl_i2c *i2c;
+ int size = 0xf;
+ int ret;
+
+
[PATCH v2 2/3] common: board: phytec: import SoM detection for imx8m based SoM from u-boot
This patch imports and cleans up the SoM detection for imx8m based SoM
from u-boot.
Signed-off-by: Marc Kleine-Budde
---
common/boards/Kconfig | 7 +
common/boards/Makefile | 1 +
common/boards/phytec/Makefile | 4 +
common/boards/phytec/phytec-som-detection.c| 209 +
common/boards/phytec/phytec-som-imx8m-detection.c | 151 +++
include/boards/phytec/phytec-som-detection.h | 69 +++
include/boards/phytec/phytec-som-imx8m-detection.h | 19 ++
7 files changed, 460 insertions(+)
diff --git a/common/boards/Kconfig b/common/boards/Kconfig
index e27273b7671d..b240548b484d 100644
--- a/common/boards/Kconfig
+++ b/common/boards/Kconfig
@@ -2,3 +2,10 @@
config BOARD_QEMU_VIRT
bool
+
+config BOARD_PHYTEC_SOM_DETECTION
+ bool
+
+config BOARD_PHYTEC_SOM_IMX8M_DETECTION
+ bool
+ select BOARD_PHYTEC_SOM_DETECTION
diff --git a/common/boards/Makefile b/common/boards/Makefile
index 5b4e429c13e9..2a96ce6aec5c 100644
--- a/common/boards/Makefile
+++ b/common/boards/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_BOARD_QEMU_VIRT) += qemu-virt/
+obj-y += phytec/
diff --git a/common/boards/phytec/Makefile b/common/boards/phytec/Makefile
new file mode 100644
index ..741a0e2eb704
--- /dev/null
+++ b/common/boards/phytec/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-$(CONFIG_BOARD_PHYTEC_SOM_DETECTION) += phytec-som-detection.o
+lwl-$(CONFIG_BOARD_PHYTEC_SOM_IMX8M_DETECTION) += phytec-som-imx8m-detection.o
diff --git a/common/boards/phytec/phytec-som-detection.c
b/common/boards/phytec/phytec-som-detection.c
new file mode 100644
index ..e338639d03e9
--- /dev/null
+++ b/common/boards/phytec/phytec-som-detection.c
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet
+ */
+
+#include
+#include
+#include
+
+struct phytec_eeprom_data eeprom_data;
+
+#define POLY (0x1070U << 3)
+
+static u8 _crc8(u16 data)
+{
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ if (data & 0x8000)
+ data = data ^ POLY;
+ data = data << 1;
+ }
+
+ return data >> 8;
+}
+
+static unsigned int crc8(unsigned int crc, const u8 *vptr, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ crc = _crc8((crc ^ vptr[i]) << 8);
+
+ return crc;
+}
+
+const char *phytec_get_opt(const struct phytec_eeprom_data *data)
+{
+ const char *opt;
+
+ if (!data)
+ data = _data;
+
+ switch (data->api_rev) {
+ case PHYTEC_API_REV0:
+ case PHYTEC_API_REV1:
+ opt = data->data.data_api0.opt;
+ break;
+ case PHYTEC_API_REV2:
+ opt = data->data.data_api2.opt;
+ break;
+ default:
+ opt = NULL;
+ break;
+ };
+
+ return opt;
+}
+
+static int phytec_eeprom_data_init(struct pbl_i2c *i2c,
+ struct phytec_eeprom_data *data,
+ int addr, u8 phytec_som_type)
+{
+ unsigned int crc;
+ const char *opt;
+ int *ptr;
+ int ret = -1, i;
+ u8 som;
+
+ if (!data)
+ data = _data;
+
+ eeprom_read(i2c, addr, I2C_ADDR_16_BIT, data, sizeof(struct
phytec_eeprom_data));
+
+ if (data->api_rev == 0xff) {
+ pr_err("%s: EEPROM is not flashed. Prototype?\n", __func__);
+ return -EINVAL;
+ }
+
+ for (i = 0, ptr = (int *)data;
+i < sizeof(struct phytec_eeprom_data);
+i += sizeof(ptr), ptr++)
+ if (*ptr != 0x0)
+ break;
+
+ if (i == sizeof(struct phytec_eeprom_data)) {
+ pr_err("%s: EEPROM data is all zero. Erased?\n", __func__);
+ return -EINVAL;
+ }
+
+ if (data->api_rev > PHYTEC_API_REV2) {
+ pr_err("%s: EEPROM API revision %u not supported\n",
+ __func__, data->api_rev);
+ return -EINVAL;
+ }
+
+ /* We are done here for early revisions */
+ if (data->api_rev <= PHYTEC_API_REV1)
+ return 0;
+
+ crc = crc8(0, (const unsigned char *)data,
+ sizeof(struct phytec_eeprom_data));
+ pr_debug("%s: crc: %x\n", __func__, crc);
+
+ if (crc) {
+ pr_err("%s: CRC mismatch. EEPROM data is not usable\n",
__func__);
+ return -EINVAL;
+ }
+
+ som = data->data.data_api2.som_no;
+ pr_debug("%s: som id: %u\n", __func__, som);
+ opt = phytec_get_opt(data);
+ if (!opt)
+ return -EINVAL;
+
+ if (IS_ENABLED(CONFIG_BOARD_PHYTEC_SOM_IMX8M_DETECTION))
+ ret = phytec_imx8m_detect(som, opt,
[PATCH v2 0/3] ARM: i.MX8MM: add Phytec i.MX8 SoM support
This series adds support for the Phytec i.MX8 SoM. It a minimal i2c EEPROM read helper for the PBL and import + adopts the Phytec SOM detection from u-boot. The Phytec SOM detection reads and parses the EEPROM on the SOM to figure out the size of the populated RAM. Signed-off-by: Marc Kleine-Budde --- Changes in v2: - make several pointers to "struct phytec_eeprom" const - phytec_print_som_info(): use printf() instead of pr_cont() - let phytec_imx8m_detect() return int instead of u8 - fix typo in phytec_get_imx8m_spi()'s comment - rename struct phytec_api0_data::pad -> __pad - move include/phytec-som-* to include/boards/phytec - Link to v1: https://lore.barebox.org/20230606-phytec-som-imx8mm-v1-0-b9c2bf70b...@pengutronix.de --- Marc Kleine-Budde (3): i2c: add for PBL use common: board: phytec: import SoM detection for imx8m based SoM from u-boot ARM: i.MX8MM: add Phytec i.MX8 SoM support arch/arm/boards/Makefile |1 + arch/arm/boards/phytec-som-imx8mm/Makefile |4 + arch/arm/boards/phytec-som-imx8mm/board.c | 40 + .../flash-header-imx8mm-phyboard-polis-rdk.imxcfg |7 + arch/arm/boards/phytec-som-imx8mm/lowlevel.c | 130 ++ arch/arm/boards/phytec-som-imx8mm/lowlevel.h |8 + arch/arm/boards/phytec-som-imx8mm/lpddr4-timing.c | 1852 arch/arm/dts/Makefile |1 + arch/arm/dts/imx8mm-phyboard-polis-rdk.dts | 60 + arch/arm/mach-imx/Kconfig | 48 + common/boards/Kconfig |7 + common/boards/Makefile |1 + common/boards/phytec/Makefile |4 + common/boards/phytec/phytec-som-detection.c| 209 +++ common/boards/phytec/phytec-som-imx8m-detection.c | 151 ++ images/Makefile.imx|5 + include/boards/phytec/phytec-som-detection.h | 69 + include/boards/phytec/phytec-som-imx8m-detection.h | 19 + include/pbl/eeprom.h | 34 + 19 files changed, 2650 insertions(+) --- base-commit: d95b1da1ac49476565382e40bbeb56cd5ad29f4d change-id: 20230606-phytec-som-imx8mm-2c90276fb58c Best regards, -- Marc Kleine-Budde
[PATCH v2 1/3] i2c: add for PBL use
Add a small helper to read a single page of EEPROM data.
Signed-off-by: Marc Kleine-Budde
---
include/pbl/eeprom.h | 34 ++
1 file changed, 34 insertions(+)
diff --git a/include/pbl/eeprom.h b/include/pbl/eeprom.h
new file mode 100644
index ..df868b1a37fb
--- /dev/null
+++ b/include/pbl/eeprom.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __PBL_EEPROM_H_
+#define __PBL_EEPROM_H_
+
+#include
+#include
+
+static inline void eeprom_read(struct pbl_i2c *i2c, u16 client_addr, u32 addr,
void *buf, u16 count)
+{
+ u8 msgbuf[2];
+ struct i2c_msg msg[] = {
+ {
+ .addr = client_addr,
+ .buf = msgbuf,
+ }, {
+ .addr = client_addr,
+ .flags = I2C_M_RD,
+ .buf = buf,
+ .len = count,
+ },
+ };
+ int ret, i = 0;
+
+ if (addr & I2C_ADDR_16_BIT)
+ msgbuf[i++] = addr >> 8;
+ msgbuf[i++] = addr;
+ msg[0].len = i;
+
+ ret = pbl_i2c_xfer(i2c, msg, ARRAY_SIZE(msg));
+ if (ret != ARRAY_SIZE(msg))
+ pr_err("Failed to read from eeprom@%x: %d\n", client_addr, ret);
+}
+
+#endif
--
2.39.2
Re: [PATCH v2] Porting barebox to a new SoC
Hello Lior, On 06.06.23 14:54, Lior Weintraub wrote: > Hello Ahmad, > > I managed to build a bl31.bin file from TF-A. > This is just a preliminary implementation (basically all functions I had to > implement are empty) so I'm hoping it will allow running a bare minimum > initial Linux kernel. As long as the TF-A implements the informational parts (e.g. PSCI_VERSION), I think that should be ok. > I tried to follow how imx8mq-bl31.bin was added into barebox and I think I > got it right. > I have several indications that the BL31 is behaving as expected. Nice. A simple sanity check would be to implement SYSTEM_RESET and call it from barebox using the PSCI client reset driver. > The initial implementation (without BL31) was running PBL from SRAM (address > 0xC0__), > decompressed barebox into DRAM (@ 0x07E0_) and jumped to barebox. > From ARM registers inspection we can see that we are @ EL3 > > Now with the inclusion of BL31, it starts @ SRAM (as before) but then test > that we are in EL3 and if so, > copy full image (PBL+Barebox) into DRAM address 0x0800_, Sounds good. > copy BL31.bin into DRAM address 0x1000_ and jumps there. You can do that, but keep in mind that BL31 will always be invoked at EL3, so you'll want to use hardware mechanisms to ensure that you can't just overwrite it from lower exception levels. If you have a DDR firewall, you could place it into DDR, but I'd suggest just keeping it in SRAM. That way you only need to configure your address space controller so SRAM is secure-world only. This also simplifies later logic, because you no longer need to mark the DDR region where TF-A is as reserved. (If you don't do that, you risk Linux accessing it, which can lead to crashes). > The execution of BL31 does its thing and then sets execution level to EL2 and > jumps to DRAM address 0x0800_ (hard coded address we used on BL31 TF-A > compilation). That's fine. I'd just jump to address 0 though if that's the start of your DRAM. > We now see the PBL starts running again (now from DRAM), skips the BL31 > loading (because it sees that we are not in EL3) and continue as before. Sounds good. > PBL decompressed barebox into DRAM address 0x07E0_ and jump to barebox. Sounds even better. > From ARM registers inspection we can see that we are @ EL2 Nice. :-) > Few questions: > 1. Any comments or thoughts about the above flow? See above, but sounds good overall. > 2. Are we ready now to try loading kernel and rootfs? If so how? Did you already flesh out your DT? It needs to contain GIC, timer and arm,psci-1.0 at the very least. Then you need a boot medium. If it's something like eMMC, you can configure QEMU to provide a memory-mapped SD/MMC controller and enable the driver for that in barebox. If it's something more esoteric, you can just use virtio block or cfi-flash, both of which are supported in barebox and QEMU and are in used with the default QEMU virt machine. Assuming you have a file system in a virtio block device and you have enabled it on QEMU side with virtio-mmio transport and barebox has the relevant virtio-mmio node in its device tree, you can then boot with: global.linux.bootargs.earlycon=earlycon bootm -o /mnt/virtioblk0.0/boot/mydevicetree.dtb \ -r /mnt/virtioblk0.0/boot/myinitrd.img /mnt/virtioblk0.0/boot/mykernel.gz (Don't forget to add stdout-path = to your DT, so kernel can find the console to use with earlycon) If you aren't familiar with virtioblk or cfi-flash try building barebox for multi_v8_defconfig and then start it in QEMU to play around with it: qemu-system-aarch64 -M virt,highmem=off -cpu cortex-a57 -m 1024M -kernel build/images/barebox-dt-2nd.img \ -serial mon:stdio -trace file=/dev/null -nographic > 3. Is it OK (or even recommended) to change BL31 so that it will enter EL1 > instead of EL2 (as we do not plan to use virtualization). Always enter kernel at EL2. Let Linux worry about going from EL2 to EL1 > Thanks again for your kind support, > Cheers, > Lior. Cheers, Ahmad > > >> -Original Message- >> From: Ahmad Fatoum >> Sent: Thursday, June 1, 2023 3:36 PM >> To: Lior Weintraub ; Ahmad Fatoum ; >> barebox@lists.infradead.org >> Subject: Re: [PATCH v2] Porting barebox to a new SoC >> >> CAUTION: External Sender >> >> Hello Lior, >> >> On 01.06.23 13:45, Lior Weintraub wrote: >>> Hello Ahmad, >>> >>> Very interesting stuff. >>> >>> We actually did started TF-A integration few months ago and tested it on the >> QEMU running ARM virt machine. >>> The TF-A compilation didn't include BL31 image (probably this explains the >> "ERROR: BL2: Failed to load image id 3"). >> >> I wouldn't recommend using TF-A as BL2. I am quite content with how >> it's done on NXP's i.MX SoCs, which is the flow I described at the >> end of my last mail. Instead of loading a FIP, TF-A would just >> return to DRAM (or maintain LR on TF-A entry and return to it). >> >>> For this code
Re: [PATCH 2/3] common: board: phytec: import SoM detection for imx8m based SoM from u-boot
On 06.06.2023 14:51:05, Ahmad Fatoum wrote:
> On 06.06.23 12:50, Marc Kleine-Budde wrote:
> > This patch imports and cleans up the SoM detection for imx8n based SoM
> > from u-boot.
> >
> > Signed-off-by: Marc Kleine-Budde
> > ---
> > common/boards/Kconfig | 7 +
> > common/boards/Makefile| 1 +
> > common/boards/phytec/Makefile | 4 +
> > common/boards/phytec/phytec-som-detection.c | 209
> > ++
> > common/boards/phytec/phytec-som-imx8m-detection.c | 151
> > include/phytec-som-detection.h| 69 +++
> > include/phytec-som-imx8m-detection.h | 19 ++
> > 7 files changed, 460 insertions(+)
> >
> > diff --git a/common/boards/Kconfig b/common/boards/Kconfig
> > index e27273b7671d..b240548b484d 100644
> > --- a/common/boards/Kconfig
> > +++ b/common/boards/Kconfig
> > @@ -2,3 +2,10 @@
> >
> > config BOARD_QEMU_VIRT
> > bool
> > +
> > +config BOARD_PHYTEC_SOM_DETECTION
> > + bool
> > +
> > +config BOARD_PHYTEC_SOM_IMX8M_DETECTION
> > + bool
> > + select BOARD_PHYTEC_SOM_DETECTION
> > diff --git a/common/boards/Makefile b/common/boards/Makefile
> > index 5b4e429c13e9..2a96ce6aec5c 100644
> > --- a/common/boards/Makefile
> > +++ b/common/boards/Makefile
> > @@ -1,3 +1,4 @@
> > # SPDX-License-Identifier: GPL-2.0-only
> >
> > obj-$(CONFIG_BOARD_QEMU_VIRT) += qemu-virt/
> > +obj-y += phytec/
> > diff --git a/common/boards/phytec/Makefile b/common/boards/phytec/Makefile
> > new file mode 100644
> > index ..741a0e2eb704
> > --- /dev/null
> > +++ b/common/boards/phytec/Makefile
> > @@ -0,0 +1,4 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +
> > +lwl-$(CONFIG_BOARD_PHYTEC_SOM_DETECTION) += phytec-som-detection.o
> > +lwl-$(CONFIG_BOARD_PHYTEC_SOM_IMX8M_DETECTION) +=
> > phytec-som-imx8m-detection.o
> > diff --git a/common/boards/phytec/phytec-som-detection.c
> > b/common/boards/phytec/phytec-som-detection.c
> > new file mode 100644
> > index ..d9479f8ced69
> > --- /dev/null
> > +++ b/common/boards/phytec/phytec-som-detection.c
> > @@ -0,0 +1,209 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2020 PHYTEC Messtechnik GmbH
> > + * Author: Teresa Remmet
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +
> > +struct phytec_eeprom_data eeprom_data;
> > +
> > +#define POLY (0x1070U << 3)
> > +
> > +static u8 _crc8(u16 data)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < 8; i++) {
> > + if (data & 0x8000)
> > + data = data ^ POLY;
> > + data = data << 1;
> > + }
> > +
> > + return data >> 8;
> > +}
> > +
> > +static unsigned int crc8(unsigned int crc, const u8 *vptr, int len)
> > +{
> > + int i;
> > +
> > + for (i = 0; i < len; i++)
> > + crc = _crc8((crc ^ vptr[i]) << 8);
> > +
> > + return crc;
> > +}
>
> There's already a crc8 implementation. Why can't you reuse it?
It's a lookup table based approach and not pbl ready.
> > +
> > +char *phytec_get_opt(struct phytec_eeprom_data *data)
>
> const return and const argument?
fixed
> > +{
> > + char *opt;
> > +
> > + if (!data)
> > + data = _data;
> > +
> > + switch (data->api_rev) {
> > + case PHYTEC_API_REV0:
> > + case PHYTEC_API_REV1:
> > + opt = data->data.data_api0.opt;
> > + break;
> > + case PHYTEC_API_REV2:
> > + opt = data->data.data_api2.opt;
> > + break;
> > + default:
> > + opt = NULL;
> > + break;
> > + };
> > +
> > + return opt;
> > +}
> > +
> > +static int phytec_eeprom_data_init(struct pbl_i2c *i2c,
> > + struct phytec_eeprom_data *data,
> > + int addr, u8 phytec_som_type)
> > +{
> > + unsigned int crc;
> > + char *opt;
> > + int *ptr;
> > + int ret = -1, i;
> > + u8 som;
> > +
> > + if (!data)
> > + data = _data;
> > +
> > + eeprom_read(i2c, addr, I2C_ADDR_16_BIT, data, sizeof(struct
> > phytec_eeprom_data));
> > +
> > + if (data->api_rev == 0xff) {
> > + pr_err("%s: EEPROM is not flashed. Prototype?\n", __func__);
> > + return -EINVAL;
> > + }
> > +
> > + for (i = 0, ptr = (int *)data;
> > +i < sizeof(struct phytec_eeprom_data);
> > +i += sizeof(ptr), ptr++)
> > + if (*ptr != 0x0)
> > + break;
> > +
> > + if (i == sizeof(struct phytec_eeprom_data)) {
> > + pr_err("%s: EEPROM data is all zero. Erased?\n", __func__);
> > + return -EINVAL;
> > + }
> > +
> > + if (data->api_rev > PHYTEC_API_REV2) {
> > + pr_err("%s: EEPROM API revision %u not supported\n",
> > + __func__, data->api_rev);
> > + return -EINVAL;
> > + }
> > +
> > + /* We are done here for early revisions */
> > + if (data->api_rev <= PHYTEC_API_REV1)
> > +
RE: [PATCH v2] Porting barebox to a new SoC
Hello Ahmad, I managed to build a bl31.bin file from TF-A. This is just a preliminary implementation (basically all functions I had to implement are empty) so I'm hoping it will allow running a bare minimum initial Linux kernel. I tried to follow how imx8mq-bl31.bin was added into barebox and I think I got it right. I have several indications that the BL31 is behaving as expected. The initial implementation (without BL31) was running PBL from SRAM (address 0xC0__), decompressed barebox into DRAM (@ 0x07E0_) and jumped to barebox. From ARM registers inspection we can see that we are @ EL3 Now with the inclusion of BL31, it starts @ SRAM (as before) but then test that we are in EL3 and if so, copy full image (PBL+Barebox) into DRAM address 0x0800_, copy BL31.bin into DRAM address 0x1000_ and jumps there. The execution of BL31 does its thing and then sets execution level to EL2 and jumps to DRAM address 0x0800_ (hard coded address we used on BL31 TF-A compilation). We now see the PBL starts running again (now from DRAM), skips the BL31 loading (because it sees that we are not in EL3) and continue as before. PBL decompressed barebox into DRAM address 0x07E0_ and jump to barebox. From ARM registers inspection we can see that we are @ EL2 Few questions: 1. Any comments or thoughts about the above flow? 2. Are we ready now to try loading kernel and rootfs? If so how? 3. Is it OK (or even recommended) to change BL31 so that it will enter EL1 instead of EL2 (as we do not plan to use virtualization). Thanks again for your kind support, Cheers, Lior. > -Original Message- > From: Ahmad Fatoum > Sent: Thursday, June 1, 2023 3:36 PM > To: Lior Weintraub ; Ahmad Fatoum ; > barebox@lists.infradead.org > Subject: Re: [PATCH v2] Porting barebox to a new SoC > > CAUTION: External Sender > > Hello Lior, > > On 01.06.23 13:45, Lior Weintraub wrote: > > Hello Ahmad, > > > > Very interesting stuff. > > > > We actually did started TF-A integration few months ago and tested it on the > QEMU running ARM virt machine. > > The TF-A compilation didn't include BL31 image (probably this explains the > "ERROR: BL2: Failed to load image id 3"). > > I wouldn't recommend using TF-A as BL2. I am quite content with how > it's done on NXP's i.MX SoCs, which is the flow I described at the > end of my last mail. Instead of loading a FIP, TF-A would just > return to DRAM (or maintain LR on TF-A entry and return to it). > > > For this code to run we used the following QEMU command: > > > > qemu-system-aarch64 -nographic -machine virt,secure=on -cpu cortex- > a53,rvbar=0x00 \ > >-smp 1 -m 1024 -bios bl1.bin -d unimp -semihosting-config > enable=on,target=native \ > >-monitor telnet:localhost:1235,server,nowait -gdb tcp::1236 > > > > Output: > > NOTICE: bl1_early_platform_set > > NOTICE: Booting Trusted Firmware > > NOTICE: BL1: v2.7(debug):831de6588 > > NOTICE: BL1: Built : 12:40:08, May 28 2023 > > INFO:BL1: RAM 0xe0ee000 - 0xe0f6000 > > INFO:BL1: cortex_a53: CPU workaround for 835769 was applied > > INFO:BL1: cortex_a53: CPU workaround for 843419 was applied > > INFO:BL1: cortex_a53: CPU workaround for 855873 was applied > > INFO:BL1: cortex_a53: CPU workaround for 1530924 was applied > > INFO:BL1: Loading BL2 > > WARNING: Firmware Image Package header check failed. > > INFO:Loading image id=1 at address 0xe07b000 > > INFO:Image id=1 loaded: 0xe07b000 - 0xe081201 > > NOTICE: BL1: Booting BL2 > > INFO:Entry point address = 0xe07b000 > > INFO:SPSR = 0x3c5 > > NOTICE: BL2: v2.7(debug):831de6588 > > NOTICE: BL2: Built : 12:40:08, May 28 2023 > > INFO:BL2: Doing platform setup > > INFO:BL2: Loading image id 3 > > WARNING: Firmware Image Package header check failed. > > WARNING: Failed to obtain reference to image id=3 (-2) > > ERROR: BL2: Failed to load image id 3 (-2) > > > > When we tried to modify the TF-A code to use our SoC (e.g. change the start > address to 0xC0_0400_ and use UART on 0xD0_0030_7000) it crashed > with seg. Fault. > > Try building your BL31 as position-independent executable. The code doing > fixed text area may be hardcoded to 32-bit. See here for an example > of turning on PIE: > > https://ddec1-0-en- > ctp.trendmicro.com:443/wis/clicktime/v1/query?url=https%3a%2f%2freview > .trustedfirmware.org%2fc%2fTF%2dA%2ftrusted%2dfirmware%2da%2f%2b > %2f16370=0b12ecfc-4ee1-4f0b-90e0- > 54ceaf590ca1=860a7ebb9feba264acc79b6e38eb59582349362c- > c3cc24ae937d0a564120b663c7b93f60c48f01b5 > > > We didn't continue with this development effort and decided we will write > our own BootROM as BL1 > > Ye, I don't think TF-A is a good candidate for a BL1 (are there even > other users that user TF-A that way?). > > > and use that to load u-boot or barebox > > That's ok. You just need BL31 to provide you runtime services (or maintain > your > Linux SoC support patches for ever). > > > Now I understand we
Re: [PATCH 2/3] common: board: phytec: import SoM detection for imx8m based SoM from u-boot
On 06.06.23 12:50, Marc Kleine-Budde wrote:
> This patch imports and cleans up the SoM detection for imx8n based SoM
> from u-boot.
>
> Signed-off-by: Marc Kleine-Budde
> ---
> common/boards/Kconfig | 7 +
> common/boards/Makefile| 1 +
> common/boards/phytec/Makefile | 4 +
> common/boards/phytec/phytec-som-detection.c | 209
> ++
> common/boards/phytec/phytec-som-imx8m-detection.c | 151
> include/phytec-som-detection.h| 69 +++
> include/phytec-som-imx8m-detection.h | 19 ++
> 7 files changed, 460 insertions(+)
>
> diff --git a/common/boards/Kconfig b/common/boards/Kconfig
> index e27273b7671d..b240548b484d 100644
> --- a/common/boards/Kconfig
> +++ b/common/boards/Kconfig
> @@ -2,3 +2,10 @@
>
> config BOARD_QEMU_VIRT
> bool
> +
> +config BOARD_PHYTEC_SOM_DETECTION
> + bool
> +
> +config BOARD_PHYTEC_SOM_IMX8M_DETECTION
> + bool
> + select BOARD_PHYTEC_SOM_DETECTION
> diff --git a/common/boards/Makefile b/common/boards/Makefile
> index 5b4e429c13e9..2a96ce6aec5c 100644
> --- a/common/boards/Makefile
> +++ b/common/boards/Makefile
> @@ -1,3 +1,4 @@
> # SPDX-License-Identifier: GPL-2.0-only
>
> obj-$(CONFIG_BOARD_QEMU_VIRT)+= qemu-virt/
> +obj-y += phytec/
> diff --git a/common/boards/phytec/Makefile b/common/boards/phytec/Makefile
> new file mode 100644
> index ..741a0e2eb704
> --- /dev/null
> +++ b/common/boards/phytec/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +
> +lwl-$(CONFIG_BOARD_PHYTEC_SOM_DETECTION) += phytec-som-detection.o
> +lwl-$(CONFIG_BOARD_PHYTEC_SOM_IMX8M_DETECTION) +=
> phytec-som-imx8m-detection.o
> diff --git a/common/boards/phytec/phytec-som-detection.c
> b/common/boards/phytec/phytec-som-detection.c
> new file mode 100644
> index ..d9479f8ced69
> --- /dev/null
> +++ b/common/boards/phytec/phytec-som-detection.c
> @@ -0,0 +1,209 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020 PHYTEC Messtechnik GmbH
> + * Author: Teresa Remmet
> + */
> +
> +#include
> +#include
> +#include
> +
> +struct phytec_eeprom_data eeprom_data;
> +
> +#define POLY (0x1070U << 3)
> +
> +static u8 _crc8(u16 data)
> +{
> + int i;
> +
> + for (i = 0; i < 8; i++) {
> + if (data & 0x8000)
> + data = data ^ POLY;
> + data = data << 1;
> + }
> +
> + return data >> 8;
> +}
> +
> +static unsigned int crc8(unsigned int crc, const u8 *vptr, int len)
> +{
> + int i;
> +
> + for (i = 0; i < len; i++)
> + crc = _crc8((crc ^ vptr[i]) << 8);
> +
> + return crc;
> +}
There's already a crc8 implementation. Why can't you reuse it?
> +
> +char *phytec_get_opt(struct phytec_eeprom_data *data)
const return and const argument?
> +{
> + char *opt;
> +
> + if (!data)
> + data = _data;
> +
> + switch (data->api_rev) {
> + case PHYTEC_API_REV0:
> + case PHYTEC_API_REV1:
> + opt = data->data.data_api0.opt;
> + break;
> + case PHYTEC_API_REV2:
> + opt = data->data.data_api2.opt;
> + break;
> + default:
> + opt = NULL;
> + break;
> + };
> +
> + return opt;
> +}
> +
> +static int phytec_eeprom_data_init(struct pbl_i2c *i2c,
> +struct phytec_eeprom_data *data,
> +int addr, u8 phytec_som_type)
> +{
> + unsigned int crc;
> + char *opt;
> + int *ptr;
> + int ret = -1, i;
> + u8 som;
> +
> + if (!data)
> + data = _data;
> +
> + eeprom_read(i2c, addr, I2C_ADDR_16_BIT, data, sizeof(struct
> phytec_eeprom_data));
> +
> + if (data->api_rev == 0xff) {
> + pr_err("%s: EEPROM is not flashed. Prototype?\n", __func__);
> + return -EINVAL;
> + }
> +
> + for (i = 0, ptr = (int *)data;
> + i < sizeof(struct phytec_eeprom_data);
> + i += sizeof(ptr), ptr++)
> + if (*ptr != 0x0)
> + break;
> +
> + if (i == sizeof(struct phytec_eeprom_data)) {
> + pr_err("%s: EEPROM data is all zero. Erased?\n", __func__);
> + return -EINVAL;
> + }
> +
> + if (data->api_rev > PHYTEC_API_REV2) {
> + pr_err("%s: EEPROM API revision %u not supported\n",
> +__func__, data->api_rev);
> + return -EINVAL;
> + }
> +
> + /* We are done here for early revisions */
> + if (data->api_rev <= PHYTEC_API_REV1)
> + return 0;
> +
> + crc = crc8(0, (const unsigned char *)data,
> +sizeof(struct phytec_eeprom_data));
> + pr_debug("%s: crc: %x\n", __func__, crc);
> +
> + if (crc) {
> + pr_err("%s: CRC mismatch. EEPROM data is not usable\n",
> __func__);
> + return
[PATCH] ci: test-defconfigs: build with -Werror
CI builds a lot of code and warnings can go unnoticed. Ensure this won't
happen anymore.
Signed-off-by: Ahmad Fatoum
---
.github/workflows/build-defconfigs.yml | 3 ++-
test/kconfig/enable_werror.kconf | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
create mode 100644 test/kconfig/enable_werror.kconf
diff --git a/.github/workflows/build-defconfigs.yml
b/.github/workflows/build-defconfigs.yml
index ff9264721d87..335976f18d06 100644
--- a/.github/workflows/build-defconfigs.yml
+++ b/.github/workflows/build-defconfigs.yml
@@ -40,4 +40,5 @@ jobs:
./test/generate-dummy-fw.sh
./MAKEALL -O build-${{matrix.arch}} -k
test/kconfig/disable_size_check.kconf \
--k test/kconfig/disable_target_tools.kconf '${{matrix.config}}'
+-k test/kconfig/disable_target_tools.kconf \
+-k test/kconfig/enable_werror.kconf '${{matrix.config}}'
diff --git a/test/kconfig/enable_werror.kconf b/test/kconfig/enable_werror.kconf
new file mode 100644
index ..f54ff6cdaab8
--- /dev/null
+++ b/test/kconfig/enable_werror.kconf
@@ -0,0 +1 @@
+CONFIG_WERROR=y
--
2.39.2
Re: [PATCH 1/3] i2c: add for PBL use
On 06.06.2023 13:21:48, Sascha Hauer wrote:
> On Tue, Jun 06, 2023 at 12:50:02PM +0200, Marc Kleine-Budde wrote:
> > Add a small helper to read a single page of EEPROM data.
> >
> > Signed-off-by: Marc Kleine-Budde
> > ---
> > include/pbl/eeprom.h | 34 ++
> > 1 file changed, 34 insertions(+)
> >
> > diff --git a/include/pbl/eeprom.h b/include/pbl/eeprom.h
> > new file mode 100644
> > index ..b713cf154c99
> > --- /dev/null
> > +++ b/include/pbl/eeprom.h
> > @@ -0,0 +1,34 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +#ifndef __PBL_EEPROM_H_
> > +#define __PBL_EEPROM_H_
> > +
> > +#include
> > +#include
> > +
> > +static inline void eeprom_read(struct pbl_i2c *i2c, u16 client_addr, u32
> > addr, void *buf, u16 count)
> > +{
> > + u8 msgbuf[2];
> > + struct i2c_msg msg[] = {
> > + {
> > + .addr = client_addr,
> > + .buf = msgbuf,
> > + }, {
> > + .addr = client_addr,
> > + .flags = I2C_M_RD,
> > + .buf = buf,
> > + .len = count,
> > + },
> > + };
> > + int ret, i = 0;
> > +
> > + if (addr & I2C_ADDR_16_BIT)
> > + msgbuf[i++] = addr >> 8;
> > + msgbuf[i++] = addr;
> > + msg->len = i;
>
> I wasn't aware that an array can be accessed as a pointer.
It's C, that's all just syntactic sugar :)
> I would prefer msg[0].len = i here.
That's copied from i2c_read_reg(), will change, though.
Marc
--
Pengutronix e.K. | Marc Kleine-Budde |
Embedded Linux | https://www.pengutronix.de |
Vertretung Nürnberg | Phone: +49-5121-206917-129 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
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Description: PGP signature
Re: [PATCH master 4/7] net: gianfar: fix out of bounds read of local variable
On 06.06.23 11:33, Sascha Hauer wrote:
> On Mon, Jun 05, 2023 at 08:29:36AM +0200, Ahmad Fatoum wrote:
>> The MAC address will be written to two 32-bit registers. Because
>> MAC_ADDR_LEN == 6, this meant two bytes out-of-bounds where written to
>> the hardware register. Fix this by having them be in-bound and always
>> initialized to zero.
>>
>> Signed-off-by: Ahmad Fatoum
>> ---
>> drivers/net/gianfar.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c
>> index 4b374b4a50de..10a95324920b 100644
>> --- a/drivers/net/gianfar.c
>> +++ b/drivers/net/gianfar.c
>> @@ -234,7 +234,7 @@ static int gfar_set_ethaddr(struct eth_device *edev,
>> const unsigned char *mac)
>> {
>> struct gfar_private *priv = edev->priv;
>> void __iomem *regs = priv->regs;
>> -char tmpbuf[MAC_ADDR_LEN];
>> +char tmpbuf[8] = {};
>
> I would prefer to adopt the Linux commit fixing this code which apart
> from the out-of-bounds access also has endianess fixes and makes the
> code simpler:
>
> ---8<---
>
> From 35cc52aacd65886a2ae46e68f727cadd09a3e8f2 Mon Sep 17 00:00:00 2001
> From: Sascha Hauer
> Date: Tue, 6 Jun 2023 11:29:51 +0200
> Subject: [PATCH] net: gianfar: make MAC addr setup endian safe, cleanup
>
> This is an adoption of Linux commit:
>
> | commit 83bfc3c4765c35ef0dfff8a3d6dedab88f3f50ea
> | Author: Claudiu Manoil
> | Date: Tue Oct 7 10:44:33 2014 +0300
> |
> | gianfar: Make MAC addr setup endian safe, cleanup
> |
> | Fix the 32-bit memory access that is not endian safe,
> | i.e. not giving the desired byte layout for a LE CPU:
> | tempval = *((u32 *) (tmpbuf + 4)), where 'char tmpbuf[]'.
> |
> | Get rid of rendundant local vars (tmpbuf[] and idx) and
> | forced casts. Cleanup comments.
> |
> | Signed-off-by: Claudiu Manoil
> | Signed-off-by: David S. Miller
>
> Signed-off-by: Sascha Hauer
Reviewed-by: Ahmad Fatoum
> ---
> drivers/net/gianfar.c | 10 ++
> 1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c
> index 4b374b4a50..1a07059db4 100644
> --- a/drivers/net/gianfar.c
> +++ b/drivers/net/gianfar.c
> @@ -234,19 +234,13 @@ static int gfar_set_ethaddr(struct eth_device *edev,
> const unsigned char *mac)
> {
> struct gfar_private *priv = edev->priv;
> void __iomem *regs = priv->regs;
> - char tmpbuf[MAC_ADDR_LEN];
> uint tempval;
> - int ix;
> -
> - for (ix = 0; ix < MAC_ADDR_LEN; ix++)
> - tmpbuf[MAC_ADDR_LEN - 1 - ix] = mac[ix];
>
> - tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
> - tmpbuf[3];
> + tempval = (mac[5] << 24) | (mac[4] << 16) | (mac[3] << 8) | mac[2];
>
> out_be32(regs + GFAR_MACSTRADDR1_OFFSET, tempval);
>
> - tempval = *((uint *)(tmpbuf + 4));
> + tempval = (mac[1] << 24) | (mac[0] << 16);
>
> out_be32(regs + GFAR_MACSTRADDR2_OFFSET, tempval);
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 1/3] i2c: add for PBL use
On Tue, Jun 06, 2023 at 12:50:02PM +0200, Marc Kleine-Budde wrote:
> Add a small helper to read a single page of EEPROM data.
>
> Signed-off-by: Marc Kleine-Budde
> ---
> include/pbl/eeprom.h | 34 ++
> 1 file changed, 34 insertions(+)
>
> diff --git a/include/pbl/eeprom.h b/include/pbl/eeprom.h
> new file mode 100644
> index ..b713cf154c99
> --- /dev/null
> +++ b/include/pbl/eeprom.h
> @@ -0,0 +1,34 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __PBL_EEPROM_H_
> +#define __PBL_EEPROM_H_
> +
> +#include
> +#include
> +
> +static inline void eeprom_read(struct pbl_i2c *i2c, u16 client_addr, u32
> addr, void *buf, u16 count)
> +{
> + u8 msgbuf[2];
> + struct i2c_msg msg[] = {
> + {
> + .addr = client_addr,
> + .buf = msgbuf,
> + }, {
> + .addr = client_addr,
> + .flags = I2C_M_RD,
> + .buf = buf,
> + .len = count,
> + },
> + };
> + int ret, i = 0;
> +
> + if (addr & I2C_ADDR_16_BIT)
> + msgbuf[i++] = addr >> 8;
> + msgbuf[i++] = addr;
> + msg->len = i;
I wasn't aware that an array can be accessed as a pointer. I would
prefer msg[0].len = i here.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
[PATCH 3/3] ARM: i.MX8MM: add Phytec i.MX8 SoM support
Signed-off-by: Marc Kleine-Budde
---
arch/arm/boards/Makefile |1 +
arch/arm/boards/phytec-som-imx8mm/Makefile |4 +
arch/arm/boards/phytec-som-imx8mm/board.c | 40 +
.../flash-header-imx8mm-phyboard-polis-rdk.imxcfg |7 +
arch/arm/boards/phytec-som-imx8mm/lowlevel.c | 130 ++
arch/arm/boards/phytec-som-imx8mm/lowlevel.h |8 +
arch/arm/boards/phytec-som-imx8mm/lpddr4-timing.c | 1852
arch/arm/dts/Makefile |1 +
arch/arm/dts/imx8mm-phyboard-polis-rdk.dts | 60 +
arch/arm/mach-imx/Kconfig | 48 +
images/Makefile.imx|5 +
11 files changed, 2156 insertions(+)
diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 2877debad535..1222ef80feb1 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -95,6 +95,7 @@ obj-$(CONFIG_MACH_PHYTEC_SOM_AM335X) +=
phytec-som-am335x/
obj-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += phytec-som-imx6/
obj-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += phytec-phycore-imx7/
obj-$(CONFIG_MACH_PHYTEC_PHYCORE_STM32MP1) += phytec-phycore-stm32mp1/
+obj-$(CONFIG_MACH_PHYTEC_SOM_IMX8MM) += phytec-som-imx8mm/
obj-$(CONFIG_MACH_PHYTEC_SOM_IMX8MQ) += phytec-som-imx8mq/
obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += plathome-openblocks-ax3/
obj-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_A6) += plathome-openblocks-a6/
diff --git a/arch/arm/boards/phytec-som-imx8mm/Makefile
b/arch/arm/boards/phytec-som-imx8mm/Makefile
new file mode 100644
index ..10abebc53921
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx8mm/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-y += lowlevel.o lpddr4-timing.o
+obj-y += board.o
diff --git a/arch/arm/boards/phytec-som-imx8mm/board.c
b/arch/arm/boards/phytec-som-imx8mm/board.c
new file mode 100644
index ..52f821f5fa30
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx8mm/board.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: 2022 Ahmad Fatoum, Pengutronix
+
+#include
+#include
+#include
+#include
+#include
+
+static int phyboard_polis_rdk_probe(struct device *dev)
+{
+ int emmc_bbu_flag = 0;
+ int sd_bbu_flag = 0;
+
+ if (bootsource_get() == BOOTSOURCE_MMC && bootsource_get_instance() ==
1) {
+ of_device_enable_path("/chosen/environment-sd");
+ sd_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ } else {
+ of_device_enable_path("/chosen/environment-emmc");
+ emmc_bbu_flag = BBU_HANDLER_FLAG_DEFAULT;
+ }
+
+ imx8m_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2",
emmc_bbu_flag);
+ imx8m_bbu_internal_mmc_register_handler("SD", "/dev/mmc1.barebox",
sd_bbu_flag);
+
+ return 0;
+}
+
+static const struct of_device_id phyboard_polis_rdk_of_match[] = {
+ { .compatible = "phytec,imx8mm-phyboard-polis-rdk" },
+ { /* sentinel */ },
+};
+BAREBOX_DEEP_PROBE_ENABLE(phyboard_polis_rdk_of_match);
+
+static struct driver phyboard_polis_rdkboard_driver = {
+ .name = "board-phyboard-polis-rdk",
+ .probe = phyboard_polis_rdk_probe,
+ .of_compatible = DRV_OF_COMPAT(phyboard_polis_rdk_of_match),
+};
+coredevice_platform_driver(phyboard_polis_rdkboard_driver);
diff --git
a/arch/arm/boards/phytec-som-imx8mm/flash-header-imx8mm-phyboard-polis-rdk.imxcfg
b/arch/arm/boards/phytec-som-imx8mm/flash-header-imx8mm-phyboard-polis-rdk.imxcfg
new file mode 100644
index ..10606ce29c96
--- /dev/null
+++
b/arch/arm/boards/phytec-som-imx8mm/flash-header-imx8mm-phyboard-polis-rdk.imxcfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+soc imx8mm
+
+loadaddr 0x007e1000
+max_load_size 0x3f000
+ivtofs 0x400
diff --git a/arch/arm/boards/phytec-som-imx8mm/lowlevel.c
b/arch/arm/boards/phytec-som-imx8mm/lowlevel.c
new file mode 100644
index ..def49fd49493
--- /dev/null
+++ b/arch/arm/boards/phytec-som-imx8mm/lowlevel.c
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "lowlevel.h"
+
+extern char __dtb_z_imx8mm_phyboard_polis_rdk_start[];
+
+#define UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_3P3V_45_OHM)
+
+static void setup_uart(void)
+{
+ void __iomem *uart = IOMEM(MX8M_UART3_BASE_ADDR);
+
+ imx8m_early_setup_uart_clock();
+
+ imx8mm_setup_pad(IMX8MM_PAD_UART3_TXD_UART3_TX | UART_PAD_CTRL);
+ imx8m_uart_setup(uart);
+
+ pbl_set_putc(imx_uart_putc, uart);
+ putc_ll('>');
+}
+
+#define EEPROM_ADDR 0x51
+#define EEPROM_ADDR_FALLBACK 0x59
+
+static void phyboard_polis_rdk_ddr_init(void)
+{
+ struct pbl_i2c *i2c;
+ int size = 0xf;
+ int ret;
+
+
[PATCH 2/3] common: board: phytec: import SoM detection for imx8m based SoM from u-boot
This patch imports and cleans up the SoM detection for imx8n based SoM
from u-boot.
Signed-off-by: Marc Kleine-Budde
---
common/boards/Kconfig | 7 +
common/boards/Makefile| 1 +
common/boards/phytec/Makefile | 4 +
common/boards/phytec/phytec-som-detection.c | 209 ++
common/boards/phytec/phytec-som-imx8m-detection.c | 151
include/phytec-som-detection.h| 69 +++
include/phytec-som-imx8m-detection.h | 19 ++
7 files changed, 460 insertions(+)
diff --git a/common/boards/Kconfig b/common/boards/Kconfig
index e27273b7671d..b240548b484d 100644
--- a/common/boards/Kconfig
+++ b/common/boards/Kconfig
@@ -2,3 +2,10 @@
config BOARD_QEMU_VIRT
bool
+
+config BOARD_PHYTEC_SOM_DETECTION
+ bool
+
+config BOARD_PHYTEC_SOM_IMX8M_DETECTION
+ bool
+ select BOARD_PHYTEC_SOM_DETECTION
diff --git a/common/boards/Makefile b/common/boards/Makefile
index 5b4e429c13e9..2a96ce6aec5c 100644
--- a/common/boards/Makefile
+++ b/common/boards/Makefile
@@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_BOARD_QEMU_VIRT) += qemu-virt/
+obj-y += phytec/
diff --git a/common/boards/phytec/Makefile b/common/boards/phytec/Makefile
new file mode 100644
index ..741a0e2eb704
--- /dev/null
+++ b/common/boards/phytec/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+lwl-$(CONFIG_BOARD_PHYTEC_SOM_DETECTION) += phytec-som-detection.o
+lwl-$(CONFIG_BOARD_PHYTEC_SOM_IMX8M_DETECTION) += phytec-som-imx8m-detection.o
diff --git a/common/boards/phytec/phytec-som-detection.c
b/common/boards/phytec/phytec-som-detection.c
new file mode 100644
index ..d9479f8ced69
--- /dev/null
+++ b/common/boards/phytec/phytec-som-detection.c
@@ -0,0 +1,209 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 PHYTEC Messtechnik GmbH
+ * Author: Teresa Remmet
+ */
+
+#include
+#include
+#include
+
+struct phytec_eeprom_data eeprom_data;
+
+#define POLY (0x1070U << 3)
+
+static u8 _crc8(u16 data)
+{
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ if (data & 0x8000)
+ data = data ^ POLY;
+ data = data << 1;
+ }
+
+ return data >> 8;
+}
+
+static unsigned int crc8(unsigned int crc, const u8 *vptr, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ crc = _crc8((crc ^ vptr[i]) << 8);
+
+ return crc;
+}
+
+char *phytec_get_opt(struct phytec_eeprom_data *data)
+{
+ char *opt;
+
+ if (!data)
+ data = _data;
+
+ switch (data->api_rev) {
+ case PHYTEC_API_REV0:
+ case PHYTEC_API_REV1:
+ opt = data->data.data_api0.opt;
+ break;
+ case PHYTEC_API_REV2:
+ opt = data->data.data_api2.opt;
+ break;
+ default:
+ opt = NULL;
+ break;
+ };
+
+ return opt;
+}
+
+static int phytec_eeprom_data_init(struct pbl_i2c *i2c,
+ struct phytec_eeprom_data *data,
+ int addr, u8 phytec_som_type)
+{
+ unsigned int crc;
+ char *opt;
+ int *ptr;
+ int ret = -1, i;
+ u8 som;
+
+ if (!data)
+ data = _data;
+
+ eeprom_read(i2c, addr, I2C_ADDR_16_BIT, data, sizeof(struct
phytec_eeprom_data));
+
+ if (data->api_rev == 0xff) {
+ pr_err("%s: EEPROM is not flashed. Prototype?\n", __func__);
+ return -EINVAL;
+ }
+
+ for (i = 0, ptr = (int *)data;
+i < sizeof(struct phytec_eeprom_data);
+i += sizeof(ptr), ptr++)
+ if (*ptr != 0x0)
+ break;
+
+ if (i == sizeof(struct phytec_eeprom_data)) {
+ pr_err("%s: EEPROM data is all zero. Erased?\n", __func__);
+ return -EINVAL;
+ }
+
+ if (data->api_rev > PHYTEC_API_REV2) {
+ pr_err("%s: EEPROM API revision %u not supported\n",
+ __func__, data->api_rev);
+ return -EINVAL;
+ }
+
+ /* We are done here for early revisions */
+ if (data->api_rev <= PHYTEC_API_REV1)
+ return 0;
+
+ crc = crc8(0, (const unsigned char *)data,
+ sizeof(struct phytec_eeprom_data));
+ pr_debug("%s: crc: %x\n", __func__, crc);
+
+ if (crc) {
+ pr_err("%s: CRC mismatch. EEPROM data is not usable\n",
__func__);
+ return -EINVAL;
+ }
+
+ som = data->data.data_api2.som_no;
+ pr_debug("%s: som id: %u\n", __func__, som);
+ opt = phytec_get_opt(data);
+ if (!opt)
+ return -EINVAL;
+
+ if (IS_ENABLED(CONFIG_BOARD_PHYTEC_SOM_IMX8M_DETECTION))
+ ret = phytec_imx8m_detect(som, opt, phytec_som_type);
+
+ if
[PATCH 1/3] i2c: add for PBL use
Add a small helper to read a single page of EEPROM data.
Signed-off-by: Marc Kleine-Budde
---
include/pbl/eeprom.h | 34 ++
1 file changed, 34 insertions(+)
diff --git a/include/pbl/eeprom.h b/include/pbl/eeprom.h
new file mode 100644
index ..b713cf154c99
--- /dev/null
+++ b/include/pbl/eeprom.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __PBL_EEPROM_H_
+#define __PBL_EEPROM_H_
+
+#include
+#include
+
+static inline void eeprom_read(struct pbl_i2c *i2c, u16 client_addr, u32 addr,
void *buf, u16 count)
+{
+ u8 msgbuf[2];
+ struct i2c_msg msg[] = {
+ {
+ .addr = client_addr,
+ .buf = msgbuf,
+ }, {
+ .addr = client_addr,
+ .flags = I2C_M_RD,
+ .buf = buf,
+ .len = count,
+ },
+ };
+ int ret, i = 0;
+
+ if (addr & I2C_ADDR_16_BIT)
+ msgbuf[i++] = addr >> 8;
+ msgbuf[i++] = addr;
+ msg->len = i;
+
+ ret = pbl_i2c_xfer(i2c, msg, ARRAY_SIZE(msg));
+ if (ret != ARRAY_SIZE(msg))
+ pr_err("Failed to read from eeprom@%x: %d\n", client_addr, ret);
+}
+
+#endif
--
2.39.2
[PATCH 0/3] ARM: i.MX8MM: add Phytec i.MX8 SoM support
This series adds support for the Phytec i.MX8 SoM. It a minimal i2c EEPROM read helper for the PBL and import + adopts the Phytec SOM detection from u-boot. The Phytec SOM detection reads and parses the EEPROM on the SOM to figure out the size of the populated RAM. Signed-off-by: Marc Kleine-Budde --- Marc Kleine-Budde (3): i2c: add for PBL use common: board: phytec: import SoM detection for imx8m based SoM from u-boot ARM: i.MX8MM: add Phytec i.MX8 SoM support arch/arm/boards/Makefile |1 + arch/arm/boards/phytec-som-imx8mm/Makefile |4 + arch/arm/boards/phytec-som-imx8mm/board.c | 40 + .../flash-header-imx8mm-phyboard-polis-rdk.imxcfg |7 + arch/arm/boards/phytec-som-imx8mm/lowlevel.c | 130 ++ arch/arm/boards/phytec-som-imx8mm/lowlevel.h |8 + arch/arm/boards/phytec-som-imx8mm/lpddr4-timing.c | 1852 arch/arm/dts/Makefile |1 + arch/arm/dts/imx8mm-phyboard-polis-rdk.dts | 60 + arch/arm/mach-imx/Kconfig | 48 + common/boards/Kconfig |7 + common/boards/Makefile |1 + common/boards/phytec/Makefile |4 + common/boards/phytec/phytec-som-detection.c| 209 +++ common/boards/phytec/phytec-som-imx8m-detection.c | 151 ++ images/Makefile.imx|5 + include/pbl/eeprom.h | 34 + include/phytec-som-detection.h | 69 + include/phytec-som-imx8m-detection.h | 19 + 19 files changed, 2650 insertions(+) --- base-commit: e7a35fb8e6f74d03fc8bed997c025d0eee2b88e0 change-id: 20230606-phytec-som-imx8mm-2c90276fb58c Best regards, -- Marc Kleine-Budde
Re: [PATCH v2] net: phy: add driver for MotorComm PHY
Hi Yegor, On Tue, Jun 06, 2023 at 10:21:39AM +0200, Yegor Yefremov wrote: > Hi Sascha, > > > > + ret = phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe); > > + if (ret < 0) > > + goto err_restore_page; > > + > > + /* leave pll enabled in sleep */ > > + ret = phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL); > > + if (ret < 0) > > + goto err_restore_page; > > + > > + ret = phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP); > > + if (ret < 0) > > + goto err_restore_page; > > + > > +err_restore_page: > > + return phy_restore_page(phydev, oldpage, ret); > > As for this approach, it is also used by some other drivers in the Linux > kernel: > > drivers/net/phy/realtek.c > drivers/net/phy/icplus.c It's ok like this. I didn't realize phy_restore_page() takes ret as argument and returns it. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH v2] net: phy: add driver for MotorComm PHY
On Tue, Jun 06, 2023 at 10:17:18AM +0200, yegorsli...@googlemail.com wrote: > From: Yegor Yefremov > > The driver corresponds to the kernel 6.1.27. > > Signed-off-by: Yegor Yefremov > --- > Changes: > v1 -> v2: add the related kernel version > > drivers/net/phy/Kconfig | 5 ++ > drivers/net/phy/Makefile| 1 + > drivers/net/phy/motorcomm.c | 128 > 3 files changed, 134 insertions(+) > create mode 100644 drivers/net/phy/motorcomm.c Applied, thanks Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH v2 1/2] net: phy: add phy_modify_mmd_indirect convenience function
On Mon, Jun 05, 2023 at 02:57:47PM +0200, Roland Hieber wrote:
> Add a read-modify-write convenience helper similar to phy_modify() for
> setting single bits in MMD registers.
>
> Signed-off-by: Roland Hieber
> ---
> PATCH v1 -> v2: new in v2
>
> drivers/net/phy/phy.c | 23 +++
> include/linux/phy.h | 2 ++
> 2 files changed, 25 insertions(+)
Applied, thanks
Sascha
>
> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> index 54dbbca7255a..cbdd5bbfb607 100644
> --- a/drivers/net/phy/phy.c
> +++ b/drivers/net/phy/phy.c
> @@ -882,6 +882,29 @@ void phy_write_mmd_indirect(struct phy_device *phydev,
> int prtad, int devad,
> phy_write(phydev, MII_MMD_DATA, data);
> }
>
> +/**
> + * phy_modify_mmd_indirect - Convenience function for modifying a MMD
> register
> + * @phydev: phy device
> + * @prtad: MMD Address
> + * @devad: MMD DEVAD
> + * @mask: bit mask of bits to clear
> + * @set: new value of bits set in @mask
> + *
> + */
> +int phy_modify_mmd_indirect(struct phy_device *phydev, int prtad, int devad,
> +u16 mask, u16 set)
> +{
> + int ret;
> +
> + ret = phy_read_mmd_indirect(phydev, prtad, devad);
> + if (ret < 0)
> + return ret;
> +
> + phy_write_mmd_indirect(phydev, prtad, devad, (ret & ~mask) | set);
> +
> + return 0;
> +}
> +
> int genphy_config_init(struct phy_device *phydev)
> {
> int val;
> diff --git a/include/linux/phy.h b/include/linux/phy.h
> index 5c3ad91d5ecc..509bf72de918 100644
> --- a/include/linux/phy.h
> +++ b/include/linux/phy.h
> @@ -409,6 +409,8 @@ int phy_scan_fixups(struct phy_device *phydev);
> int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, int devad);
> void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, int devad,
> u16 data);
> +int phy_modify_mmd_indirect(struct phy_device *phydev, int prtad, int devad,
> + u16 mask, u16 set);
>
> static inline bool phy_acquired(struct phy_device *phydev)
> {
> --
> 2.39.2
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH] partitions: efi: Continue partition enumeration on invalid pte
On Mon, Jun 05, 2023 at 12:11:05PM +0200, Christopher Ebner wrote:
> The efi partition enumeration stops, if a partition entry is
> invalid or non-existent.
> Later partitions which would be valid are therefore not enumerated.
> This can be the case, eg. if a device with the following
> partitions is enumerated: p1, p2, p4, p5, p6.
> Skipping the invalid entry instead of exiting the enumeration fixes
> this problem.
>
> Signed-off-by: Christopher Ebner
> ---
> common/partitions/efi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks
Sascha
>
> diff --git a/common/partitions/efi.c b/common/partitions/efi.c
> index ffdbd9a56f..0411a8b248 100644
> --- a/common/partitions/efi.c
> +++ b/common/partitions/efi.c
> @@ -460,7 +460,7 @@ static void efi_partition(void *buf, struct block_device
> *blk,
> for (i = 0; i < nb_part; i++) {
> if (!is_pte_valid([i], last_lba(blk))) {
> dev_dbg(blk->dev, "Invalid pte %d\n", i);
> - return;
> + continue;
> }
>
> pentry = >parts[pd->used_entries];
> --
> 2.25.1
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH RFT] ARM64: cpu: support 64-bit stack top in ENTRY_FUNCTION_WITHSTACK
On Thu, Jun 01, 2023 at 10:53:33AM +0200, Ahmad Fatoum wrote: > On 01.06.23 10:33, Lior Weintraub wrote: > > Hi Ahmad, > > Thanks for the patch. > > I have checked it and can verify it is working correctly. > > Great! I am replying with: > > Tested-by: Lior Weintraub > > So the scripts pulling patches from the mailing list will automatically > collect the tag and fold it into the commit message. That doesn't work, presumably for good reasons: NOTE: some trailers ignored due to from/email mismatches: ! Trailer: Tested-by: Lior Weintraub Msg From: Ahmad Fatoum Added the Tested-by manually. Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH] common: add CONFIG_WERROR option
On Mon, Jun 05, 2023 at 08:37:55AM +0200, Ahmad Fatoum wrote: > For development, it may be useful to enforce warning-free builds. > Add a Kconfig option for this. > > Signed-off-by: Ahmad Fatoum > --- > This can be enabled for CI, once my other series with warning > fixes is merged. > --- > Makefile | 4 > common/Kconfig | 14 ++ > 2 files changed, 18 insertions(+) Applied, thanks Sascha > > diff --git a/Makefile b/Makefile > index 4fdb8f1b41af..af5c1448b378 100644 > --- a/Makefile > +++ b/Makefile > @@ -648,6 +648,8 @@ endif > # Force gcc to behave correct even for buggy distributions > KBUILD_CFLAGS += $(call cc-option, -fno-stack-protector) > > +KBUILD_CFLAGS-$(CONFIG_WERROR) += -Werror > + > # This warning generated too much noise in a regular build. > # Use make W=1 to enable this warning (see scripts/Makefile.build) > KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable) > @@ -692,6 +694,8 @@ KBUILD_CFLAGS += $(call cc-option,-Wno-pointer-sign,) > # change __FILE__ to the relative path from the srctree > KBUILD_CFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=) > > +KBUILD_CFLAGS += $(KBUILD_CFLAGS-y) > + > include-y +=scripts/Makefile.ubsan > include-$(CONFIG_KASAN) += scripts/Makefile.kasan > > diff --git a/common/Kconfig b/common/Kconfig > index 11aabbb509df..5cfe717aa70d 100644 > --- a/common/Kconfig > +++ b/common/Kconfig > @@ -1701,6 +1701,20 @@ config COMPILE_TEST > say Y here. If you are a user, say N here to avoid being prompted for > inclusion of unrelated drivers. > > +config WERROR > + bool "Compile barebox with warnings as errors" > + default COMPILE_TEST > + help > + A barebox build should not cause any compiler warnings, and this > + enables the '-Werror' flags to enforce that rule by default. > + > + However, if you have a new (or very old) compiler with odd and > + unusual warnings, or you have some architecture with problems, > + you may need to disable this config option in order to > + successfully build barebox. > + > + If in doubt, say Y. > + > endmenu > > source "common/efi/Kconfig" > -- > 2.39.2 > > > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 01/14] gitignore: don't ignore files in .github/ directory
On Mon, Jun 05, 2023 at 08:36:10AM +0200, Ahmad Fatoum wrote: > The directory holds our workflow files and it shouldn't require git add > -f to add new files there. > > Signed-off-by: Ahmad Fatoum > --- > .gitignore | 1 + > 1 file changed, 1 insertion(+) Applied, thanks Sascha > > diff --git a/.gitignore b/.gitignore > index dd36d5083b17..d2487d548376 100644 > --- a/.gitignore > +++ b/.gitignore > @@ -52,6 +52,7 @@ Module.symvers > # > !.gitignore > !.mailmap > +!.github/ > > # > # Generated include files > -- > 2.39.2 > > > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 04/17] MIPS: o32: provide ta0..ta3 register definitions
On Tue, 6 Jun 2023 at 11:13, Ahmad Fatoum wrote: > > On 05.06.23 22:10, Denis Orlov wrote: > > This allows to write generic assembly code that will compile under both > > o32 and n64 ABIs, as otherwise the register definitions would conflict. > > > > Taken from Linux kernel sources, commit 'MIPS: O32: Provide definition > > of registers ta0 .. ta3.' (3ba1e543ab4b02640d396098f2f6a199560d5f2d). > > > > Signed-off-by: Denis Orlov > > Reviewed-by: Ahmad Fatoum > > I must say, this file looks odd though. _MIPS_SIM is apparently > defined by the compiler and it's compared against _MIPS_SIM_ABI32, > which barebox defines... AFAICS, the compiler defines _MIPS_SIM with the value of some number, _MIPS_SIM_ABI32, on the other hand, gives a symbolic representation (as another define) for this number. This just adds more sense to what we are actually comparing against. But this header also seems to be quite old, maybe nowadays there is a better way to check for those. Regards, Denis > > > --- > > arch/mips/include/asm/regdef.h | 6 ++ > > 1 file changed, 6 insertions(+) > > > > diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h > > index 1300251661..df87582e8e 100644 > > --- a/arch/mips/include/asm/regdef.h > > +++ b/arch/mips/include/asm/regdef.h > > @@ -3,6 +3,8 @@ > > * Copyright (C) 1985 MIPS Computer Systems, Inc. > > * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle > > * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. > > + * Copyright (C) 2011 Wind River Systems, > > + * written by Ralf Baechle > > */ > > #ifndef _ASM_REGDEF_H > > #define _ASM_REGDEF_H > > @@ -27,9 +29,13 @@ > > #define t2 $10 > > #define t3 $11 > > #define t4 $12 > > +#define ta0 $12 > > #define t5 $13 > > +#define ta1 $13 > > #define t6 $14 > > +#define ta2 $14 > > #define t7 $15 > > +#define ta3 $15 > > #define s0 $16 /* callee saved */ > > #define s1 $17 > > #define s2 $18 > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | >
Re: [PATCH master 1/7] ddr: imx8m: align function definition with prototype
On Mon, Jun 05, 2023 at 08:29:33AM +0200, Ahmad Fatoum wrote: > The values of enum dram_type and enum ddrc_type are defined, so they > don't overlap, which allows ddr_cfg_phy() to accept them OR-d. > > It's thus wrong to use only one enum of them in the prototype, so adjust > it with the definition. > > Signed-off-by: Ahmad Fatoum > --- > include/soc/imx8m/ddr.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Applied, thanks Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH master 4/7] net: gianfar: fix out of bounds read of local variable
On Mon, Jun 05, 2023 at 08:29:36AM +0200, Ahmad Fatoum wrote:
> The MAC address will be written to two 32-bit registers. Because
> MAC_ADDR_LEN == 6, this meant two bytes out-of-bounds where written to
> the hardware register. Fix this by having them be in-bound and always
> initialized to zero.
>
> Signed-off-by: Ahmad Fatoum
> ---
> drivers/net/gianfar.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c
> index 4b374b4a50de..10a95324920b 100644
> --- a/drivers/net/gianfar.c
> +++ b/drivers/net/gianfar.c
> @@ -234,7 +234,7 @@ static int gfar_set_ethaddr(struct eth_device *edev,
> const unsigned char *mac)
> {
> struct gfar_private *priv = edev->priv;
> void __iomem *regs = priv->regs;
> - char tmpbuf[MAC_ADDR_LEN];
> + char tmpbuf[8] = {};
I would prefer to adopt the Linux commit fixing this code which apart
from the out-of-bounds access also has endianess fixes and makes the
code simpler:
---8<---
>From 35cc52aacd65886a2ae46e68f727cadd09a3e8f2 Mon Sep 17 00:00:00 2001
From: Sascha Hauer
Date: Tue, 6 Jun 2023 11:29:51 +0200
Subject: [PATCH] net: gianfar: make MAC addr setup endian safe, cleanup
This is an adoption of Linux commit:
| commit 83bfc3c4765c35ef0dfff8a3d6dedab88f3f50ea
| Author: Claudiu Manoil
| Date: Tue Oct 7 10:44:33 2014 +0300
|
| gianfar: Make MAC addr setup endian safe, cleanup
|
| Fix the 32-bit memory access that is not endian safe,
| i.e. not giving the desired byte layout for a LE CPU:
| tempval = *((u32 *) (tmpbuf + 4)), where 'char tmpbuf[]'.
|
| Get rid of rendundant local vars (tmpbuf[] and idx) and
| forced casts. Cleanup comments.
|
| Signed-off-by: Claudiu Manoil
| Signed-off-by: David S. Miller
Signed-off-by: Sascha Hauer
---
drivers/net/gianfar.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c
index 4b374b4a50..1a07059db4 100644
--- a/drivers/net/gianfar.c
+++ b/drivers/net/gianfar.c
@@ -234,19 +234,13 @@ static int gfar_set_ethaddr(struct eth_device *edev,
const unsigned char *mac)
{
struct gfar_private *priv = edev->priv;
void __iomem *regs = priv->regs;
- char tmpbuf[MAC_ADDR_LEN];
uint tempval;
- int ix;
-
- for (ix = 0; ix < MAC_ADDR_LEN; ix++)
- tmpbuf[MAC_ADDR_LEN - 1 - ix] = mac[ix];
- tempval = (tmpbuf[0] << 24) | (tmpbuf[1] << 16) | (tmpbuf[2] << 8) |
- tmpbuf[3];
+ tempval = (mac[5] << 24) | (mac[4] << 16) | (mac[3] << 8) | mac[2];
out_be32(regs + GFAR_MACSTRADDR1_OFFSET, tempval);
- tempval = *((uint *)(tmpbuf + 4));
+ tempval = (mac[1] << 24) | (mac[0] << 16);
out_be32(regs + GFAR_MACSTRADDR2_OFFSET, tempval);
--
2.39.2
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 11/17] MIPS: Makefile: sign-extend TEXT_BASE value on CONFIG_64BIT
On Tue, 6 Jun 2023 at 12:04, Ahmad Fatoum wrote: > > On 05.06.23 22:10, Denis Orlov wrote: > > The code that uses TEXT_BASE will fail on reading truncated 32-bit > > address if running with 64BIT enabled. As we only support running from > > compatibility segments (i.e. no 'proper' 64-bit base addresses), simply > > make sure the value is sign-extended when passing it as a define. > > Below is not really a sign extension. e.g. 0x_ would be turned > into 0x___. Is that ok? Yeah, we can only handle KSEG0/KSEG1 segments, i.e. text base should be somewhere in 0x8000_/0xa000_. So for those, this might be considered a sign extension, I guess. Regards, Denis > > > > > Signed-off-by: Denis Orlov > > --- > > arch/mips/Makefile | 8 +++- > > 1 file changed, 7 insertions(+), 1 deletion(-) > > > > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > > index bad6e574c4..65a00379ab 100644 > > --- a/arch/mips/Makefile > > +++ b/arch/mips/Makefile > > @@ -57,7 +57,13 @@ cflags-$(CONFIG_CPU_MIPS64_R1) += $(call > > cc-option,-march=mips64,-mips64 -U_MIPS > > cflags-$(CONFIG_CPU_MIPS64_R2) += $(call > > cc-option,-march=mips64r2,-mips64r2 -U_MIPS_ISA > > -D_MIPS_ISA=_MIPS_ISA_MIPS64) -Wa,-mips64r2 -Wa,--trap > > cflags-$(CONFIG_CPU_GS232) += $(call > > cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA > > -D_MIPS_ISA=_MIPS_ISA_MIPS32) -Wa,-mips32r2 -Wa,--trap > > > > -KBUILD_CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE) > > +ifdef CONFIG_64BIT > > +MIPS_TEXT_BASE = $(subst 0x,0x,$(CONFIG_TEXT_BASE)) > > +else > > +MIPS_TEXT_BASE = $(CONFIG_TEXT_BASE) > > +endif > > + > > +KBUILD_CPPFLAGS += -DTEXT_BASE=$(MIPS_TEXT_BASE) > > > > ifndef CONFIG_MODULES > > # Add cleanup flags > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | >
Re: [PATCH 02/17] MIPS: malta: use CKSEG instead of KSEG macros
On Tue, 6 Jun 2023 at 11:03, Ahmad Fatoum wrote:
>
> On 05.06.23 22:10, Denis Orlov wrote:
> > KSEG macro is not available when compiling with CONFIG_64BIT enabled, so
> > use CKSEG instead.
>
> If they're interchangeable, why do we need KSEG?
Hmm, I think maybe we don't. We can replace every instance of KSEG with
CKSEG without any change in functionality, except for the fact that the
latter will compile with 64BIT enabled. Overall, it seems that a lot of
MIPS-specific headers were taken from Linux as is back when the support
for MIPS was being added to barebox. Those were already old and crufty
back then but there are also a lot of definitions that we neither need
nor use, yet which unnecessarily complicate the code. I might try
cleaning up those headers sometime in the future.
Regards,
Denis
>
> >
> > Signed-off-by: Denis Orlov
> > ---
> > arch/mips/boards/qemu-malta/lowlevel.S | 4 ++--
> > arch/mips/mach-malta/pci.c | 2 +-
> > 2 files changed, 3 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/mips/boards/qemu-malta/lowlevel.S
> > b/arch/mips/boards/qemu-malta/lowlevel.S
> > index 98821e0426..541d62fc2a 100644
> > --- a/arch/mips/boards/qemu-malta/lowlevel.S
> > +++ b/arch/mips/boards/qemu-malta/lowlevel.S
> > @@ -56,14 +56,14 @@ __start:
> >*/
> >
> > /* move GT64120 registers to 0x1be0 */
> > - li t1, KSEG1ADDR(GT_DEF_BASE)
> > + li t1, CKSEG1ADDR(GT_DEF_BASE)
> > li t0, GT_LD(MIPS_GT_BASE)
> > sw t0, GT_ISD_OFS(t1)
> >
> > /*
> >* setup MEM-to-PCI0 mapping
> >*/
> > - li t1, KSEG1ADDR(MIPS_GT_BASE)
> > + li t1, CKSEG1ADDR(MIPS_GT_BASE)
> >
> > /* setup PCI0 io window */
> > li t0, GT_LD(0x1800)
> > diff --git a/arch/mips/mach-malta/pci.c b/arch/mips/mach-malta/pci.c
> > index 113b94fe23..0ab239f509 100644
> > --- a/arch/mips/mach-malta/pci.c
> > +++ b/arch/mips/mach-malta/pci.c
> > @@ -136,7 +136,7 @@ static int gt64xxx_pci0_pcibios_write(struct pci_bus
> > *bus, unsigned int devfn,
> > static resource_size_t gt64xxx_res_start(struct pci_bus *bus,
> >resource_size_t res_addr)
> > {
> > - return KSEG0ADDR(res_addr);
> > + return CKSEG0ADDR(res_addr);
> > }
> >
> > struct pci_ops gt64xxx_pci0_ops = {
>
> --
> Pengutronix e.K. | |
> Steuerwalder Str. 21 | http://www.pengutronix.de/ |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
>
Re: [PATCH v4 1/2] commands: add pwm manipulation command
Hi Marc,
I applied this with some small changes.
On Fri, Jun 02, 2023 at 02:53:05PM +1000, Marc Reilly wrote:
> +static int do_pwm_cmd(int argc, char *argv[])
> +{
> + struct pwm_device *pwm = NULL;
> + struct pwm_state state, orig_state;
> + int error = 0;
> + char *devname = NULL;
> + int duty = -1, period = -1;
> + int freq = -1, width = -1;
> + bool invert_polarity = false, stop = false;
> + bool use_default_width = false;
> + bool verbose = false;
> + int opt;
> +
> + while ((opt = getopt(argc, argv, "d:D:P:f:w:F:isv")) > 0) {
> + switch (opt) {
> + case 'd':
> + devname = optarg;
> + break;
> + case 'D':
> + duty = simple_strtol(optarg, NULL, 0);
> + break;
> + case 'P':
> + period = simple_strtol(optarg, NULL, 0);
> + break;
> + case 'F':
> + /* convenience option for changing frequency without
> + * having to specify duty width */
> + use_default_width = true;
> + /* fallthrough */
> + case 'f':
> + freq = simple_strtol(optarg, NULL, 0);
> + break;
> + case 'w':
> + width = simple_strtol(optarg, NULL, 0);
> + break;
> + case 'i':
> + invert_polarity = true;
> + break;
> + case 's':
> + stop = true;
> + break;
> + case 'v':
> + verbose = true;
> + break;
default:
return COMMAND_ERROR_USAGE;
> + }
> + }
> +
> + if (!devname) {
> + printf(" need to specify a device\n");
> + return COMMAND_ERROR_USAGE;
> + }
> + if ((freq == 0) || (period == 0)) {
> + printf(" period or freqency needs to be non-zero\n");
> + return COMMAND_ERROR_USAGE;
> + }
> + if (freq >= 0 && period >= 0) {
> + printf(" specify period or frequency, not both\n");
> + return COMMAND_ERROR_USAGE;
> + }
> + if (duty >= 0 && width >= 0) {
> + printf(" specify duty or width, not both\n");
> + return COMMAND_ERROR_USAGE;
> + }
> + if (width > 100) {
> + printf(" width (%% duty cycle) can't be more than 100%%\n");
> + return COMMAND_ERROR_USAGE;
> + }
> +
> + pwm = pwm_request(devname);
> + if (!pwm) {
> + printf(" pwm device %s not found\n", devname);
> + return -ENODEV;
> + }
> +
> + pwm_get_state(pwm, );
> +
> + /* argc will be at least 3 with a valid devname */
> + if (verbose || (argc <= 3)) {
> + printf("pwm params for '%s':\n", devname);
> + printf(" period : %u (ns)\n", state.period_ns);
> + printf(" duty : %u (ns)\n", state.duty_ns);
> + printf(" enabled : %d\n", state.p_enable);
> + printf(" polarity : %s\n", state.polarity == 0 ? "Normal" :
> "Inverted");
> + printf(" freq : %lu (Hz)\n",
> HZ_FROM_NANOSECONDS(state.period_ns));
This results in a division by zero crash on a disabled PWM. I changed
this to:
if (state.period_ns)
printf(" freq : %lu (Hz)\n",
HZ_FROM_NANOSECONDS(state.period_ns));
else
printf(" freq : -\n");
> +BAREBOX_CMD_HELP_OPT("-d string", "device name (eg 'pwm0')")
> +BAREBOX_CMD_HELP_OPT("-D number", "duty cycle (ns)")
> +BAREBOX_CMD_HELP_OPT("-P number", "period (ns)")
> +BAREBOX_CMD_HELP_OPT("-f number", "frequency (Hz)")
> +BAREBOX_CMD_HELP_OPT("-w number", "duty cycle (%) - the on 'width' of each
> cycle")
Replaced 'number' with and similar.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 14/17] MIPS: pbl_macros: use generic load/store macros in copy_to_link_location
On 05.06.23 22:10, Denis Orlov wrote: > This may speed up this code a little on MIPS64, however this also allows > us to get rid of unnecessary macro definition there, simplifying the > code a tiny bit. > > Signed-off-by: Denis Orlov Reviewed-by: Ahmad Fatoum > --- > arch/mips/include/asm/pbl_macros.h | 21 ++--- > 1 file changed, 10 insertions(+), 11 deletions(-) > > diff --git a/arch/mips/include/asm/pbl_macros.h > b/arch/mips/include/asm/pbl_macros.h > index ce169a1554..f8629d3f2c 100644 > --- a/arch/mips/include/asm/pbl_macros.h > +++ b/arch/mips/include/asm/pbl_macros.h > @@ -120,22 +120,21 @@ > PTR_SUBUt2, t1, t0 /* t2 <- size of pbl */ > PTR_ADDUa2, a0, t2 /* a2 <- source end address */ > > -#define WSIZE4 > copy_loop: > /* copy from source address [a0] */ > - lw ta0, WSIZE * 0(a0) > - lw ta1, WSIZE * 1(a0) > - lw ta2, WSIZE * 2(a0) > - lw ta3, WSIZE * 3(a0) > + LONG_L ta0, LONGSIZE * 0(a0) > + LONG_L ta1, LONGSIZE * 1(a0) > + LONG_L ta2, LONGSIZE * 2(a0) > + LONG_L ta3, LONGSIZE * 3(a0) > /* copy to target address [a1] */ > - sw ta0, WSIZE * 0(a1) > - sw ta1, WSIZE * 1(a1) > - sw ta2, WSIZE * 2(a1) > - sw ta3, WSIZE * 3(a1) > - PTR_ADDIa0, WSIZE * 4 > + LONG_S ta0, LONGSIZE * 0(a1) > + LONG_S ta1, LONGSIZE * 1(a1) > + LONG_S ta2, LONGSIZE * 2(a1) > + LONG_S ta3, LONGSIZE * 3(a1) > + PTR_ADDIa0, LONGSIZE * 4 > PTR_SUBUt3, a0, a2 > blezt3, copy_loop > - PTR_ADDI a1, WSIZE * 4 > + PTR_ADDI a1, LONGSIZE * 4 > > copy_loop_exit: > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 12/17] MIPS: enable 64-bit kernel segment addressing on CONFIG_64BIT
On 05.06.23 22:10, Denis Orlov wrote: > This allows using addresses from XKPHYS segment. This is needed as we > access hardware registers through this segment in 64BIT configuration, > but this also lets us peek/poke bigger memory address space using > commands that work with memory on 64BIT. > > With this commit, malta with 64-bit CPU finally boots into 64BIT barebox > in QEMU. > > Signed-off-by: Denis Orlov Reviewed-by: Ahmad Fatoum > --- > arch/mips/boot/start.S | 2 ++ > arch/mips/include/asm/pbl_macros.h | 11 +++ > 2 files changed, 13 insertions(+) > > diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S > index 5f134f9ae9..30828ad9ef 100644 > --- a/arch/mips/boot/start.S > +++ b/arch/mips/boot/start.S > @@ -26,6 +26,8 @@ EXPORT(_start) > > mips_disable_interrupts > > + mips64_enable_64bit_addressing > + > copy_to_link_location _start > > stack_setup > diff --git a/arch/mips/include/asm/pbl_macros.h > b/arch/mips/include/asm/pbl_macros.h > index 1fba690c8c..ce169a1554 100644 > --- a/arch/mips/include/asm/pbl_macros.h > +++ b/arch/mips/include/asm/pbl_macros.h > @@ -152,6 +152,17 @@ > .setpop > .endm > > + .macro mips64_enable_64bit_addressing > +#ifdef CONFIG_64BIT > + .setpush > + .setnoreorder > + mfc0k0, CP0_STATUS > + or k0, ST0_KX > + mtc0k0, CP0_STATUS > + .setpop > +#endif > + .endm > + > .macro mips_barebox_10h > .setpush > .setnoreorder -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 11/17] MIPS: Makefile: sign-extend TEXT_BASE value on CONFIG_64BIT
On 05.06.23 22:10, Denis Orlov wrote: > The code that uses TEXT_BASE will fail on reading truncated 32-bit > address if running with 64BIT enabled. As we only support running from > compatibility segments (i.e. no 'proper' 64-bit base addresses), simply > make sure the value is sign-extended when passing it as a define. Below is not really a sign extension. e.g. 0x_ would be turned into 0x___. Is that ok? > > Signed-off-by: Denis Orlov > --- > arch/mips/Makefile | 8 +++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > index bad6e574c4..65a00379ab 100644 > --- a/arch/mips/Makefile > +++ b/arch/mips/Makefile > @@ -57,7 +57,13 @@ cflags-$(CONFIG_CPU_MIPS64_R1) += $(call > cc-option,-march=mips64,-mips64 -U_MIPS > cflags-$(CONFIG_CPU_MIPS64_R2) += $(call cc-option,-march=mips64r2,-mips64r2 > -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS64) -Wa,-mips64r2 -Wa,--trap > cflags-$(CONFIG_CPU_GS232) += $(call cc-option,-march=mips32r2,-mips32r2 > -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) -Wa,-mips32r2 -Wa,--trap > > -KBUILD_CPPFLAGS += -DTEXT_BASE=$(CONFIG_TEXT_BASE) > +ifdef CONFIG_64BIT > +MIPS_TEXT_BASE = $(subst 0x,0x,$(CONFIG_TEXT_BASE)) > +else > +MIPS_TEXT_BASE = $(CONFIG_TEXT_BASE) > +endif > + > +KBUILD_CPPFLAGS += -DTEXT_BASE=$(MIPS_TEXT_BASE) > > ifndef CONFIG_MODULES > # Add cleanup flags -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 00/17] MIPS: fix and improve 64BIT support
Hello Ahmad, On Tue, 6 Jun 2023 at 11:02, Ahmad Fatoum wrote: > > Hello Denis, > > On 05.06.23 22:10, Denis Orlov wrote: > > The existing 64BIT support for MIPS was somewhat incomplete with no > > board having MIPS64 CPUs specified to be available as targets. Define > > Malta as supporting those and fix all the compilation and linking > > errors. Make some optional features available with 64BIT too. > > Would be cool to test this in CI. Could you add: > > - a defconfig that enables this board (I'd call it mips64_defconfig > and if another MIPS64 SoC is added, we will add it there, like > we do now for e.g. multi_v8_defconfig on ARM) > > - a Labgrid env file that configures QEMU appropriately > See test/mips/qemu-malta_defconfig.yaml for an example Good idea, will do that and send another patch a bit later. > > If you like, you can go further and send a patch adding it to > CI's test-labgrid-pytest.yml workflow, but I can do that too. Yeah, that sounds interesting, will also try to do that. Regards, Denis > > Cheers, > Ahmad > > > > > Denis Orlov (17): > > MIPS: malta: allow to choose MIPS64 target CPU in config > > MIPS: malta: use CKSEG instead of KSEG macros > > MIPS: reloc: fix relocation with CONFIG_64BIT enabled > > MIPS: o32: provide ta0..ta3 register definitions > > MIPS: pbl: use o32/n64 compatible register definitions > > MIPS: pbl: fix linking errors with CONFIG_64BIT > > MIPS: use MIPS32/MIPS64 generic instruction macros > > MIPS: malta: fix GT64120 base virtual address on 64BIT > > MIPS: fix addresses of exception vectors in 64-bit mode > > MIPS: fix *ADDR macro usage warnings on CONFIG_64BIT > > MIPS: Makefile: sign-extend TEXT_BASE value on CONFIG_64BIT > > MIPS: enable 64-bit kernel segment addressing on CONFIG_64BIT > > MIPS: traps: fix passing wrong sp when returning from exception > > MIPS: pbl_macros: use generic load/store macros in > > copy_to_link_location > > MIPS: add 64-bit support for optimized string functions > > MIPS: make setjmp/longjmp/initjmp available in 64BIT builds > > MIPS: main_entry-pbl: fix conversion warnings on CONFIG_64BIT > > > > arch/mips/Kconfig | 6 +- > > arch/mips/Makefile| 14 +++-- > > arch/mips/boards/qemu-malta/lowlevel.S| 4 +- > > arch/mips/boot/main_entry-pbl.c | 11 ++-- > > arch/mips/boot/main_entry.c | 2 +- > > arch/mips/boot/start.S| 4 +- > > arch/mips/include/asm/asm.h | 10 +-- > > arch/mips/include/asm/debug_ll_ns16550.h | 6 +- > > arch/mips/include/asm/dma.h | 16 ++--- > > arch/mips/include/asm/io.h| 2 +- > > arch/mips/include/asm/pbl_macros.h| 62 +++ > > arch/mips/include/asm/pbl_nmon.h | 10 +-- > > arch/mips/include/asm/regdef.h| 6 ++ > > arch/mips/include/asm/setjmp.h| 2 +- > > arch/mips/lib/genex.S | 8 +-- > > arch/mips/lib/memcpy.S| 37 +-- > > arch/mips/lib/reloc.c | 7 +-- > > arch/mips/lib/setjmp.S| 48 +++--- > > arch/mips/lib/traps.c | 2 +- > > .../mach-malta/include/mach/mach-gt64120.h| 2 +- > > arch/mips/mach-malta/pci.c| 2 +- > > 21 files changed, 156 insertions(+), 105 deletions(-) > > > > -- > Pengutronix e.K. | | > Steuerwalder Str. 21 | http://www.pengutronix.de/ | > 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | >
Re: [PATCH 09/17] MIPS: fix addresses of exception vectors in 64-bit mode
On 05.06.23 22:10, Denis Orlov wrote:
> Do not (accidentally?) truncate addresses when setting them in the
> handler array.
>
> Signed-off-by: Denis Orlov
Reviewed-by: Ahmad Fatoum
> ---
> arch/mips/boot/main_entry.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/mips/boot/main_entry.c b/arch/mips/boot/main_entry.c
> index 2c18bc81c3..d061a0e987 100644
> --- a/arch/mips/boot/main_entry.c
> +++ b/arch/mips/boot/main_entry.c
> @@ -22,7 +22,7 @@ unsigned long exception_handlers[32];
>
> static void set_except_vector(int n, void *addr)
> {
> - unsigned handler = (unsigned long) addr;
> + unsigned long handler = (unsigned long) addr;
>
> exception_handlers[n] = handler;
Nitpick: This could be combined into one line, but you need not resend
just for this change.
> }
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 08/17] MIPS: malta: fix GT64120 base virtual address on 64BIT
On 05.06.23 22:10, Denis Orlov wrote: > Use CKSEG1ADDR for it to be properly converted to the 64-bit > sign-extended address when building with CONFIG_64BIT set. > > Signed-off-by: Denis Orlov Reviewd-by: Ahmad Fatoum > --- > arch/mips/mach-malta/include/mach/mach-gt64120.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/mips/mach-malta/include/mach/mach-gt64120.h > b/arch/mips/mach-malta/include/mach/mach-gt64120.h > index e7d230655c..20ac4d94d6 100644 > --- a/arch/mips/mach-malta/include/mach/mach-gt64120.h > +++ b/arch/mips/mach-malta/include/mach/mach-gt64120.h > @@ -12,6 +12,6 @@ > > #define MIPS_GT_BASE 0x1be0 > > -#define GT64120_BASE0xbbe0 > +#define GT64120_BASECKSEG1ADDR(MIPS_GT_BASE) > > #endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */ -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 07/17] MIPS: use MIPS32/MIPS64 generic instruction macros
On 05.06.23 22:10, Denis Orlov wrote: > Use PTR_* for various arithmetic operations on pointers, and also use > PTR_LA instead of simple 'la' instruction, as it will correctly handle > loading 64-bit addresses from non-32-bit-compatible virtual memory > segments. > > This fixes "la used to load 64-bit address; recommend using dla instead" > warnings when compiling assembly code with CONFIG_64BIT. > > Signed-off-by: Denis Orlov Reviewed-by: Ahmad Fatoum > --- > arch/mips/boot/start.S | 2 +- > arch/mips/include/asm/asm.h | 10 +- > arch/mips/include/asm/debug_ll_ns16550.h | 6 +++--- > arch/mips/include/asm/pbl_macros.h | 22 +++--- > arch/mips/lib/genex.S| 8 > 5 files changed, 24 insertions(+), 24 deletions(-) > > diff --git a/arch/mips/boot/start.S b/arch/mips/boot/start.S > index c1cd2d9dd5..5f134f9ae9 100644 > --- a/arch/mips/boot/start.S > +++ b/arch/mips/boot/start.S > @@ -34,7 +34,7 @@ EXPORT(_start) > movea0, s0 > movea1, s1 > movea2, s2 > - la v0, relocate_code > + PTR_LA v0, relocate_code > jal v0 >nop > > diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h > index 69931662ff..c699542a55 100644 > --- a/arch/mips/include/asm/asm.h > +++ b/arch/mips/include/asm/asm.h > @@ -94,10 +94,10 @@ EXPORT(symbol) > copy_to_link_location symbol; \ > stack_setup;\ > \ > - la a0, __dtb_ ## dtb##_start; \ > - la a1, __dtb_ ## dtb##_end;\ > - li a2, ram_size; \ > - la v0, pbl_main_entry; \ > + PTR_LA a0, __dtb_ ## dtb##_start; \ > + PTR_LA a1, __dtb_ ## dtb##_end;\ > + PTR_LI a2, ram_size; \ > + PTR_LA v0, pbl_main_entry; \ > jal v0; \ >nop; \ > \ > @@ -122,7 +122,7 @@ EXPORT(symbol) > /* Call some code from .text section. \ >* It is needed to keep same linker script for \ >* all images. */ \ > - la v0, mips_dead_end; \ > + PTR_LA v0, mips_dead_end; \ > jal v0; \ >nop; > > diff --git a/arch/mips/include/asm/debug_ll_ns16550.h > b/arch/mips/include/asm/debug_ll_ns16550.h > index 703bfaee77..7cfd844cb6 100644 > --- a/arch/mips/include/asm/debug_ll_ns16550.h > +++ b/arch/mips/include/asm/debug_ll_ns16550.h > @@ -60,7 +60,7 @@ static inline void PUTC_LL(char ch) > > .macro debug_ll_ns16550_init divisor=DEBUG_LL_UART_DIVISOR > #ifdef CONFIG_DEBUG_LL > - la t0, DEBUG_LL_UART_ADDR > + PTR_LA t0, DEBUG_LL_UART_ADDR > > li t1, UART_LCR_DLAB /* DLAB on */ > sb t1, UART_LCR(t0)/* Write it out */ > @@ -83,7 +83,7 @@ static inline void PUTC_LL(char ch) > .setpush > .setreorder > > - la t0, DEBUG_LL_UART_ADDR > + PTR_LA t0, DEBUG_LL_UART_ADDR > > 201: lbu t1, UART_LSR(t0)/* get line status */ > andit1, t1, UART_LSR_THRE /* check for transmitter empty */ > @@ -126,7 +126,7 @@ static inline void PUTC_LL(char ch) > .setpush > .setreorder > > - la t0, DEBUG_LL_UART_ADDR > + PTR_LA t0, DEBUG_LL_UART_ADDR > > /* get line status and check for data present */ > lbu t1, UART_LSR(t0) > diff --git a/arch/mips/include/asm/pbl_macros.h > b/arch/mips/include/asm/pbl_macros.h > index e60af38442..1fba690c8c 100644 > --- a/arch/mips/include/asm/pbl_macros.h > +++ b/arch/mips/include/asm/pbl_macros.h > @@ -73,7 +73,7 @@ > .macro pbl_probe_mem ret1 ret2 addr > .setpush > .setnoreorder > - la \ret1, \addr > + PTR_LA \ret1, \addr > sw zero, 0(\ret1) > li \ret2, 0x12345678 > sw \ret2, 0(\ret1) > @@ -97,7 +97,7 @@ > move\temp, ra # preserve ra beforehand > bal 255f >nop > -255: addiu \rd, ra, \label - 255b # label is assumed to be > +255: PTR_ADDIU \rd, ra, \label - 255b # label is assumed to be > movera, \temp # within pc +/- 32KB > .setpop > .endm > @@ -110,15 +110,15 @@ > ADR a0, \start_addr, t1 /* a0 <- pc-relative > position of start_addr */ > > - la a1, \start_addr /* a1 <- link (RAM) start_addr address */ > + PTR_LA a1, \start_addr /* a1 <- link (RAM) start_addr address */
Re: [PATCH v2] net: phy: add driver for MotorComm PHY
Hi Sascha,
On Tue, Jun 6, 2023 at 10:17 AM wrote:
>
> From: Yegor Yefremov
>
> The driver corresponds to the kernel 6.1.27.
>
> Signed-off-by: Yegor Yefremov
> ---
> Changes:
> v1 -> v2: add the related kernel version
>
> drivers/net/phy/Kconfig | 5 ++
> drivers/net/phy/Makefile| 1 +
> drivers/net/phy/motorcomm.c | 128
> 3 files changed, 134 insertions(+)
> create mode 100644 drivers/net/phy/motorcomm.c
>
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index cd20e1de27..e95e2a3228 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -50,6 +50,11 @@ config MICREL_PHY
> help
> Supports the KSZ9021, VSC8201, KS8001 PHYs.
>
> +config MOTORCOMM_PHY
> + bool "Driver for Motorcomm PHYs"
> + help
> + Currently supports the YT8511 PHY.
> +
> config NATIONAL_PHY
> bool "Driver for National Semiconductor PHYs"
> help
> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> index 83f46f11d3..26e4ad884d 100644
> --- a/drivers/net/phy/Makefile
> +++ b/drivers/net/phy/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_DAVICOM_PHY) += davicom.o
> obj-$(CONFIG_LXT_PHY) += lxt.o
> obj-$(CONFIG_MARVELL_PHY) += marvell.o
> obj-$(CONFIG_MICREL_PHY) += micrel.o
> +obj-$(CONFIG_MOTORCOMM_PHY)+= motorcomm.o
> obj-$(CONFIG_NATIONAL_PHY) += national.o
> obj-$(CONFIG_REALTEK_PHY) += realtek.o
> obj-$(CONFIG_SMSC_PHY) += smsc.o
> diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
> new file mode 100644
> index 00..4bcd84342c
> --- /dev/null
> +++ b/drivers/net/phy/motorcomm.c
> @@ -0,0 +1,128 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * drivers/net/phy/motorcomm.c
> + *
> + * Driver for Motorcomm PHYs
> + *
> + * Author: Peter Geis
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +
> +#define PHY_ID_YT8511 0x010a
> +
> +#define YT8511_PAGE_SELECT 0x1e
> +#define YT8511_PAGE0x1f
> +#define YT8511_EXT_CLK_GATE0x0c
> +#define YT8511_EXT_DELAY_DRIVE 0x0d
> +#define YT8511_EXT_SLEEP_CTRL 0x27
> +
> +/* 2b00 25m from pll
> + * 2b01 25m from xtl *default*
> + * 2b10 62.m from pll
> + * 2b11 125m from pll
> + */
> +#define YT8511_CLK_125M(BIT(2) | BIT(1))
> +#define YT8511_PLLON_SLP BIT(14)
> +
> +/* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
> +#define YT8511_DELAY_RXBIT(0)
> +
> +/* TX Gig-E Delay is bits 7:4, default 0x5
> + * TX Fast-E Delay is bits 15:12, default 0xf
> + * Delay = 150ps * N - 250ps
> + * On = 2000ps, off = 50ps
> + */
> +#define YT8511_DELAY_GE_TX_EN (0xf << 4)
> +#define YT8511_DELAY_GE_TX_DIS (0x2 << 4)
> +#define YT8511_DELAY_FE_TX_EN (0xf << 12)
> +#define YT8511_DELAY_FE_TX_DIS (0x2 << 12)
> +
> +static int yt8511_read_page(struct phy_device *phydev)
> +{
> + return phy_read(phydev, YT8511_PAGE_SELECT);
> +};
> +
> +static int yt8511_write_page(struct phy_device *phydev, int page)
> +{
> + return phy_write(phydev, YT8511_PAGE_SELECT, page);
> +};
> +
> +static int yt8511_config_init(struct phy_device *phydev)
> +{
> + int oldpage, ret = 0;
> + unsigned int ge, fe;
> +
> + oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE);
> + if (oldpage < 0)
> + goto err_restore_page;
> +
> + /* set rgmii delay mode */
> + switch (phydev->interface) {
> + case PHY_INTERFACE_MODE_RGMII:
> + ge = YT8511_DELAY_GE_TX_DIS;
> + fe = YT8511_DELAY_FE_TX_DIS;
> + break;
> + case PHY_INTERFACE_MODE_RGMII_RXID:
> + ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS;
> + fe = YT8511_DELAY_FE_TX_DIS;
> + break;
> + case PHY_INTERFACE_MODE_RGMII_TXID:
> + ge = YT8511_DELAY_GE_TX_EN;
> + fe = YT8511_DELAY_FE_TX_EN;
> + break;
> + case PHY_INTERFACE_MODE_RGMII_ID:
> + ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN;
> + fe = YT8511_DELAY_FE_TX_EN;
> + break;
> + default: /* do not support other modes */
> + ret = -EOPNOTSUPP;
> + goto err_restore_page;
> + }
> +
> + ret = phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX |
> YT8511_DELAY_GE_TX_EN), ge);
> + if (ret < 0)
> + goto err_restore_page;
> +
> + /* set clock mode to 125mhz */
> + ret = phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M);
> + if (ret < 0)
> + goto err_restore_page;
> +
> + /* fast ethernet delay is in a separate page */
> + ret = phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE);
> + if (ret < 0)
> + goto err_restore_page;
> +
> + ret = phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe);
> + if (ret < 0)
> +
Re: [PATCH 05/17] MIPS: pbl: use o32/n64 compatible register definitions
On 05.06.23 22:10, Denis Orlov wrote: > This allows to compile PBL code with n64 ABI, which we use when > CONFIG_64BIT is set. > > Signed-off-by: Denis Orlov Reviewed-by: Ahmad Fatoum > --- > arch/mips/include/asm/pbl_macros.h | 28 ++-- > arch/mips/include/asm/pbl_nmon.h | 10 +- > 2 files changed, 19 insertions(+), 19 deletions(-) > > diff --git a/arch/mips/include/asm/pbl_macros.h > b/arch/mips/include/asm/pbl_macros.h > index c62910ff60..e60af38442 100644 > --- a/arch/mips/include/asm/pbl_macros.h > +++ b/arch/mips/include/asm/pbl_macros.h > @@ -30,9 +30,9 @@ > .set noreorder > li t9, \addr > li t8, \val > - lw t7, 0(t9) > - or t7, t8 > - sw t7, 0(t9) > + lw ta3, 0(t9) > + or ta3, t8 > + sw ta3, 0(t9) > .setpop > .endm > > @@ -41,10 +41,10 @@ > .set noreorder > li t9, \addr > li t8, \clr > - lw t7, 0(t9) > + lw ta3, 0(t9) > not t8, t8 > - and t7, t8 > - sw t7, 0(t9) > + and ta3, t8 > + sw ta3, 0(t9) > .setpop > .endm > > @@ -123,15 +123,15 @@ > #define WSIZE4 > copy_loop: > /* copy from source address [a0] */ > - lw t4, WSIZE * 0(a0) > - lw t5, WSIZE * 1(a0) > - lw t6, WSIZE * 2(a0) > - lw t7, WSIZE * 3(a0) > + lw ta0, WSIZE * 0(a0) > + lw ta1, WSIZE * 1(a0) > + lw ta2, WSIZE * 2(a0) > + lw ta3, WSIZE * 3(a0) > /* copy to target address [a1] */ > - sw t4, WSIZE * 0(a1) > - sw t5, WSIZE * 1(a1) > - sw t6, WSIZE * 2(a1) > - sw t7, WSIZE * 3(a1) > + sw ta0, WSIZE * 0(a1) > + sw ta1, WSIZE * 1(a1) > + sw ta2, WSIZE * 2(a1) > + sw ta3, WSIZE * 3(a1) > addia0, WSIZE * 4 > subut3, a0, a2 > blezt3, copy_loop > diff --git a/arch/mips/include/asm/pbl_nmon.h > b/arch/mips/include/asm/pbl_nmon.h > index 0e4ec39967..7c8ec9d204 100644 > --- a/arch/mips/include/asm/pbl_nmon.h > +++ b/arch/mips/include/asm/pbl_nmon.h > @@ -39,12 +39,12 @@ > .setpush > .setreorder > > - movet6, a0 > - li t5, 32 > + moveta2, a0 > + li ta1, 32 > > 202: > - addit5, t5, -4 > - srlva0, t6, t5 > + addita1, ta1, -4 > + srlva0, ta2, ta1 > > /* output one hex digit */ > andia0, a0, 15 > @@ -57,7 +57,7 @@ > > debug_ll_outc_a0 > > - bgtzt5, 202b > + bgtzta1, 202b > > .setpop > #endif /* CONFIG_DEBUG_LL */ -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
[PATCH v2] net: phy: add driver for MotorComm PHY
From: Yegor Yefremov
The driver corresponds to the kernel 6.1.27.
Signed-off-by: Yegor Yefremov
---
Changes:
v1 -> v2: add the related kernel version
drivers/net/phy/Kconfig | 5 ++
drivers/net/phy/Makefile| 1 +
drivers/net/phy/motorcomm.c | 128
3 files changed, 134 insertions(+)
create mode 100644 drivers/net/phy/motorcomm.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index cd20e1de27..e95e2a3228 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -50,6 +50,11 @@ config MICREL_PHY
help
Supports the KSZ9021, VSC8201, KS8001 PHYs.
+config MOTORCOMM_PHY
+ bool "Driver for Motorcomm PHYs"
+ help
+ Currently supports the YT8511 PHY.
+
config NATIONAL_PHY
bool "Driver for National Semiconductor PHYs"
help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 83f46f11d3..26e4ad884d 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_DAVICOM_PHY) += davicom.o
obj-$(CONFIG_LXT_PHY) += lxt.o
obj-$(CONFIG_MARVELL_PHY) += marvell.o
obj-$(CONFIG_MICREL_PHY) += micrel.o
+obj-$(CONFIG_MOTORCOMM_PHY)+= motorcomm.o
obj-$(CONFIG_NATIONAL_PHY) += national.o
obj-$(CONFIG_REALTEK_PHY) += realtek.o
obj-$(CONFIG_SMSC_PHY) += smsc.o
diff --git a/drivers/net/phy/motorcomm.c b/drivers/net/phy/motorcomm.c
new file mode 100644
index 00..4bcd84342c
--- /dev/null
+++ b/drivers/net/phy/motorcomm.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * drivers/net/phy/motorcomm.c
+ *
+ * Driver for Motorcomm PHYs
+ *
+ * Author: Peter Geis
+ */
+
+#include
+#include
+#include
+#include
+
+#define PHY_ID_YT8511 0x010a
+
+#define YT8511_PAGE_SELECT 0x1e
+#define YT8511_PAGE0x1f
+#define YT8511_EXT_CLK_GATE0x0c
+#define YT8511_EXT_DELAY_DRIVE 0x0d
+#define YT8511_EXT_SLEEP_CTRL 0x27
+
+/* 2b00 25m from pll
+ * 2b01 25m from xtl *default*
+ * 2b10 62.m from pll
+ * 2b11 125m from pll
+ */
+#define YT8511_CLK_125M(BIT(2) | BIT(1))
+#define YT8511_PLLON_SLP BIT(14)
+
+/* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */
+#define YT8511_DELAY_RXBIT(0)
+
+/* TX Gig-E Delay is bits 7:4, default 0x5
+ * TX Fast-E Delay is bits 15:12, default 0xf
+ * Delay = 150ps * N - 250ps
+ * On = 2000ps, off = 50ps
+ */
+#define YT8511_DELAY_GE_TX_EN (0xf << 4)
+#define YT8511_DELAY_GE_TX_DIS (0x2 << 4)
+#define YT8511_DELAY_FE_TX_EN (0xf << 12)
+#define YT8511_DELAY_FE_TX_DIS (0x2 << 12)
+
+static int yt8511_read_page(struct phy_device *phydev)
+{
+ return phy_read(phydev, YT8511_PAGE_SELECT);
+};
+
+static int yt8511_write_page(struct phy_device *phydev, int page)
+{
+ return phy_write(phydev, YT8511_PAGE_SELECT, page);
+};
+
+static int yt8511_config_init(struct phy_device *phydev)
+{
+ int oldpage, ret = 0;
+ unsigned int ge, fe;
+
+ oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE);
+ if (oldpage < 0)
+ goto err_restore_page;
+
+ /* set rgmii delay mode */
+ switch (phydev->interface) {
+ case PHY_INTERFACE_MODE_RGMII:
+ ge = YT8511_DELAY_GE_TX_DIS;
+ fe = YT8511_DELAY_FE_TX_DIS;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_RXID:
+ ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS;
+ fe = YT8511_DELAY_FE_TX_DIS;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_TXID:
+ ge = YT8511_DELAY_GE_TX_EN;
+ fe = YT8511_DELAY_FE_TX_EN;
+ break;
+ case PHY_INTERFACE_MODE_RGMII_ID:
+ ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN;
+ fe = YT8511_DELAY_FE_TX_EN;
+ break;
+ default: /* do not support other modes */
+ ret = -EOPNOTSUPP;
+ goto err_restore_page;
+ }
+
+ ret = phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX |
YT8511_DELAY_GE_TX_EN), ge);
+ if (ret < 0)
+ goto err_restore_page;
+
+ /* set clock mode to 125mhz */
+ ret = phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M);
+ if (ret < 0)
+ goto err_restore_page;
+
+ /* fast ethernet delay is in a separate page */
+ ret = phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE);
+ if (ret < 0)
+ goto err_restore_page;
+
+ ret = phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe);
+ if (ret < 0)
+ goto err_restore_page;
+
+ /* leave pll enabled in sleep */
+ ret = phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL);
+ if (ret < 0)
+ goto err_restore_page;
+
+ ret = phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP);
+ if (ret < 0)
+ goto err_restore_page;
+
Re: [PATCH 04/17] MIPS: o32: provide ta0..ta3 register definitions
On 05.06.23 22:10, Denis Orlov wrote: > This allows to write generic assembly code that will compile under both > o32 and n64 ABIs, as otherwise the register definitions would conflict. > > Taken from Linux kernel sources, commit 'MIPS: O32: Provide definition > of registers ta0 .. ta3.' (3ba1e543ab4b02640d396098f2f6a199560d5f2d). > > Signed-off-by: Denis Orlov Reviewed-by: Ahmad Fatoum I must say, this file looks odd though. _MIPS_SIM is apparently defined by the compiler and it's compared against _MIPS_SIM_ABI32, which barebox defines... > --- > arch/mips/include/asm/regdef.h | 6 ++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h > index 1300251661..df87582e8e 100644 > --- a/arch/mips/include/asm/regdef.h > +++ b/arch/mips/include/asm/regdef.h > @@ -3,6 +3,8 @@ > * Copyright (C) 1985 MIPS Computer Systems, Inc. > * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle > * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc. > + * Copyright (C) 2011 Wind River Systems, > + * written by Ralf Baechle > */ > #ifndef _ASM_REGDEF_H > #define _ASM_REGDEF_H > @@ -27,9 +29,13 @@ > #define t2 $10 > #define t3 $11 > #define t4 $12 > +#define ta0 $12 > #define t5 $13 > +#define ta1 $13 > #define t6 $14 > +#define ta2 $14 > #define t7 $15 > +#define ta3 $15 > #define s0 $16 /* callee saved */ > #define s1 $17 > #define s2 $18 -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 03/17] MIPS: reloc: fix relocation with CONFIG_64BIT enabled
On 05.06.23 22:10, Denis Orlov wrote:
> Use CKSEG instead of KSEG, allowing it to compile on 64BIT
> configurations. Also make sure that we do not truncate target
> relocation address by writing it into a 32-bit wide variable.
>
> Signed-off-by: Denis Orlov
Reviewd-by: Ahmad Fatoum
> ---
> arch/mips/lib/reloc.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/arch/mips/lib/reloc.c b/arch/mips/lib/reloc.c
> index b084a88be7..3c845a9663 100644
> --- a/arch/mips/lib/reloc.c
> +++ b/arch/mips/lib/reloc.c
> @@ -108,8 +108,7 @@ static void apply_reloc(unsigned int type, void *addr,
> long off)
>
> void relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
> {
> - unsigned long addr, length, bss_len;
> - u32 relocaddr, new_stack;
> + unsigned long addr, length, bss_len, relocaddr, new_stack;
> uint8_t *buf;
> unsigned int type;
> long off;
> @@ -121,9 +120,9 @@ void relocate_code(void *fdt, u32 fdt_size, u32 ram_size)
> length = __bss_stop - __image_start;
> relocaddr = ALIGN_DOWN(ram_size - length, SZ_64K);
> if (IS_ENABLED(CONFIG_MMU)) {
> - relocaddr = KSEG0ADDR(relocaddr);
> + relocaddr = CKSEG0ADDR(relocaddr);
> } else {
> - relocaddr = KSEG1ADDR(relocaddr);
> + relocaddr = CKSEG1ADDR(relocaddr);
> }
> new_stack = relocaddr - MALLOC_SIZE - 16;
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 01/17] MIPS: malta: allow to choose MIPS64 target CPU in config
On 05.06.23 22:10, Denis Orlov wrote: > QEMU is able to emulate malta machine with a variety of MIPS CPUs, > including MIPS64 ones, so allow to compile barebox for such > configurations. > > Signed-off-by: Denis Orlov Reviewed-by: Ahmad Fatoum > --- > arch/mips/Kconfig | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 70d85690da..ab8c8cf176 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -70,8 +70,11 @@ config MACH_MIPS_MALTA > select CSRC_R4K_LIB > select DRIVER_SERIAL_NS16550 > select SYS_HAS_CPU_MIPS32_R1 > + select SYS_HAS_CPU_MIPS64_R1 > select SYS_HAS_CPU_MIPS32_R2 > + select SYS_HAS_CPU_MIPS64_R2 > select SYS_SUPPORTS_32BIT_KERNEL > + select SYS_SUPPORTS_64BIT_KERNEL > select SYS_SUPPORTS_BIG_ENDIAN > select SYS_SUPPORTS_LITTLE_ENDIAN > select HAS_DEBUG_LL -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 02/17] MIPS: malta: use CKSEG instead of KSEG macros
On 05.06.23 22:10, Denis Orlov wrote:
> KSEG macro is not available when compiling with CONFIG_64BIT enabled, so
> use CKSEG instead.
If they're interchangeable, why do we need KSEG?
>
> Signed-off-by: Denis Orlov
> ---
> arch/mips/boards/qemu-malta/lowlevel.S | 4 ++--
> arch/mips/mach-malta/pci.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/mips/boards/qemu-malta/lowlevel.S
> b/arch/mips/boards/qemu-malta/lowlevel.S
> index 98821e0426..541d62fc2a 100644
> --- a/arch/mips/boards/qemu-malta/lowlevel.S
> +++ b/arch/mips/boards/qemu-malta/lowlevel.S
> @@ -56,14 +56,14 @@ __start:
>*/
>
> /* move GT64120 registers to 0x1be0 */
> - li t1, KSEG1ADDR(GT_DEF_BASE)
> + li t1, CKSEG1ADDR(GT_DEF_BASE)
> li t0, GT_LD(MIPS_GT_BASE)
> sw t0, GT_ISD_OFS(t1)
>
> /*
>* setup MEM-to-PCI0 mapping
>*/
> - li t1, KSEG1ADDR(MIPS_GT_BASE)
> + li t1, CKSEG1ADDR(MIPS_GT_BASE)
>
> /* setup PCI0 io window */
> li t0, GT_LD(0x1800)
> diff --git a/arch/mips/mach-malta/pci.c b/arch/mips/mach-malta/pci.c
> index 113b94fe23..0ab239f509 100644
> --- a/arch/mips/mach-malta/pci.c
> +++ b/arch/mips/mach-malta/pci.c
> @@ -136,7 +136,7 @@ static int gt64xxx_pci0_pcibios_write(struct pci_bus
> *bus, unsigned int devfn,
> static resource_size_t gt64xxx_res_start(struct pci_bus *bus,
>resource_size_t res_addr)
> {
> - return KSEG0ADDR(res_addr);
> + return CKSEG0ADDR(res_addr);
> }
>
> struct pci_ops gt64xxx_pci0_ops = {
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH 00/17] MIPS: fix and improve 64BIT support
Hello Denis, On 05.06.23 22:10, Denis Orlov wrote: > The existing 64BIT support for MIPS was somewhat incomplete with no > board having MIPS64 CPUs specified to be available as targets. Define > Malta as supporting those and fix all the compilation and linking > errors. Make some optional features available with 64BIT too. Would be cool to test this in CI. Could you add: - a defconfig that enables this board (I'd call it mips64_defconfig and if another MIPS64 SoC is added, we will add it there, like we do now for e.g. multi_v8_defconfig on ARM) - a Labgrid env file that configures QEMU appropriately See test/mips/qemu-malta_defconfig.yaml for an example If you like, you can go further and send a patch adding it to CI's test-labgrid-pytest.yml workflow, but I can do that too. Cheers, Ahmad > > Denis Orlov (17): > MIPS: malta: allow to choose MIPS64 target CPU in config > MIPS: malta: use CKSEG instead of KSEG macros > MIPS: reloc: fix relocation with CONFIG_64BIT enabled > MIPS: o32: provide ta0..ta3 register definitions > MIPS: pbl: use o32/n64 compatible register definitions > MIPS: pbl: fix linking errors with CONFIG_64BIT > MIPS: use MIPS32/MIPS64 generic instruction macros > MIPS: malta: fix GT64120 base virtual address on 64BIT > MIPS: fix addresses of exception vectors in 64-bit mode > MIPS: fix *ADDR macro usage warnings on CONFIG_64BIT > MIPS: Makefile: sign-extend TEXT_BASE value on CONFIG_64BIT > MIPS: enable 64-bit kernel segment addressing on CONFIG_64BIT > MIPS: traps: fix passing wrong sp when returning from exception > MIPS: pbl_macros: use generic load/store macros in > copy_to_link_location > MIPS: add 64-bit support for optimized string functions > MIPS: make setjmp/longjmp/initjmp available in 64BIT builds > MIPS: main_entry-pbl: fix conversion warnings on CONFIG_64BIT > > arch/mips/Kconfig | 6 +- > arch/mips/Makefile| 14 +++-- > arch/mips/boards/qemu-malta/lowlevel.S| 4 +- > arch/mips/boot/main_entry-pbl.c | 11 ++-- > arch/mips/boot/main_entry.c | 2 +- > arch/mips/boot/start.S| 4 +- > arch/mips/include/asm/asm.h | 10 +-- > arch/mips/include/asm/debug_ll_ns16550.h | 6 +- > arch/mips/include/asm/dma.h | 16 ++--- > arch/mips/include/asm/io.h| 2 +- > arch/mips/include/asm/pbl_macros.h| 62 +++ > arch/mips/include/asm/pbl_nmon.h | 10 +-- > arch/mips/include/asm/regdef.h| 6 ++ > arch/mips/include/asm/setjmp.h| 2 +- > arch/mips/lib/genex.S | 8 +-- > arch/mips/lib/memcpy.S| 37 +-- > arch/mips/lib/reloc.c | 7 +-- > arch/mips/lib/setjmp.S| 48 +++--- > arch/mips/lib/traps.c | 2 +- > .../mach-malta/include/mach/mach-gt64120.h| 2 +- > arch/mips/mach-malta/pci.c| 2 +- > 21 files changed, 156 insertions(+), 105 deletions(-) > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
Re: [PATCH v2 0/2] dma: rework streaming DMA interface
On Mon, Jun 05, 2023 at 12:45:00AM +0300, Denis Orlov wrote: > This fixes issues with streaming DMA on MIPS and more or less properly > fixes support for non 1-to-1 mappings via 'dma-ranges' device tree > property. > > It needs to be tested properly on non-MIPS architectures as I only > have tested the compilation for some of those. > > The differences from RFC include merging two parts of the patch and > dropping changes not really related to the matter at hand. > > Denis Orlov (2): > dma: rework dma_sync_single_for_*() interface > net: macb: remove const from dev pointer in macb_device Looks good to me, thanks for working on this. Applied to next, let's see what the autobuilder says to it. Sascha > > arch/arm/cpu/dma_32.c | 17 +++--- > arch/arm/cpu/dma_64.c | 13 +++-- > arch/arm/cpu/mmu-common.c | 9 ++-- > arch/arm/include/asm/dma.h | 12 ++--- > arch/arm/mach-bcm283x/mbox.c| 4 +- > arch/kvx/lib/dma-default.c | 16 +++--- > arch/mips/lib/dma-default.c | 18 +++ > arch/riscv/cpu/dma.c| 23 + > arch/sandbox/include/asm/dma.h | 12 ++--- > arch/x86/include/asm/dma.h | 12 ++--- > drivers/crypto/caam/caam-blobgen.c | 28 +- > drivers/crypto/caam/caamrng.c | 6 +-- > drivers/crypto/caam/rng_self_test.c | 6 +-- > drivers/dma/Makefile| 1 - > drivers/dma/map.c | 39 -- > drivers/mci/dove-sdhci.c| 8 +-- > drivers/mci/stm32_sdmmc2.c | 8 +-- > drivers/mci/tegra-sdmmc.c | 8 +-- > drivers/net/ag71xx.c| 8 +-- > drivers/net/arc_emac.c | 10 ++-- > drivers/net/at91_ether.c| 11 ++-- > drivers/net/bcmgenet.c | 4 +- > drivers/net/cpsw.c | 8 +-- > drivers/net/davinci_emac.c | 8 +-- > drivers/net/designware.c| 10 ++-- > drivers/net/designware_eqos.c | 6 ++- > drivers/net/e1000/main.c| 4 +- > drivers/net/fec_imx.c | 4 +- > drivers/net/fsl-fman.c | 7 +-- > drivers/net/macb.c | 22 > drivers/net/mvneta.c| 8 +-- > drivers/net/orion-gbe.c | 8 +-- > drivers/net/r8169_main.c| 10 ++-- > drivers/usb/gadget/udc/fsl_udc.c| 8 +-- > drivers/usb/host/ohci-hcd.c | 7 +-- > include/dma.h | 80 ++--- > 36 files changed, 237 insertions(+), 226 deletions(-) > delete mode 100644 drivers/dma/map.c > > -- > 2.41.0 > > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
