Re: Troubles running qemu64 target
Hi Guillaume & Andrew, Le ven. 29 juin 2018 à 01:46, Andrey Smirnov a écrit : > > Guillaume: > > I haven't used QEMU ARM64 version of the code, but I have spent some > time on i.MX8M which is ARM64 as well. See my comments below. > > On Thu, Jun 28, 2018 at 6:46 AM ranquet guillaume > wrote: > > > > Hello. > > > > I'm pretty new to barebox and I'm having some troubles running the > > qemu64 target. > > to top it off, I'm also new to the ARM world... and this is my first > > attempt at looking at a bootloader... > > > > I'm having trouble porting some hardware to barebox... and while I'm > > waiting for a JTAG probe, I though I could have some fun with qemu64 > > :) > > > > The boot stops pretty early in the flow. way before anything can be > > printed on the serial. I have attached gdb to the qemu-system. > > The "qemu-system" seems to be stuck when trying to execute an stp with > > the stack pointer as the destination. > > > > I'm having the feeling that I have a configuration issue because sp = 0x0 > > > > x270x0 0 > > x280x0 0 > > x290x0 0 > > x300x0 0 > > sp 0x0 0x0 > > pc 0x4000 0x4000 > > cpsr 0x43c5 1073742789 > > fpsr 0x0 0 > > fpcr 0x0 0 > > (gdb) disassemble > > Dump of assembler code for function start: > > => 0x4000 <+0>: b 0x4048 > >0x4004 <+4>: nop > >0x4008 <+8>: nop > >0x400c <+12>:nop > > ... > > 0x4048 <+72>:b 0x40013444 > > > > > > then we are branching to > > Dump of assembler code for function barebox_arm_reset_vector: > > => 0x40013444 <+0>: stp x29, x30, [sp, #-16]! > >0x40013448 <+4>: mov x29, sp > > The above looks like barebox_arm_reset_vector's preamble to me, which > it would have since: > > a) It is not declared as __naked > > b) AFAIK, __naked is not supported on AArch64 version of GCC, so even > if it was it wouldn't help > > >0x4001344c <+8>: bl 0x4050 > > > > with sp still equals to 0x0. > > > > stepping from there seems to get me "stuck"... > > when interrupting gdb (Ctrl-C) and dumping the registers, I'm getting > > the feeling I'm out of barebox code with pc equals 0x200 > > > > x290x0 0 > > x300x0 0 > > sp 0x0 0x0 > > pc 0x2000x200 > > cpsr 0x3c5965 > > fpsr 0x0 0 > > > > > > It's probably some kind of configuration issue...? though I see no > > code to set sp before that stp instruction. > > IMHO this doesn't look like a configuration issue and I agree there's > no code to set SP up. > > > I tried toying with the memory map, setting stack and text base > > addresses, but it doesn't seem to fix my issue. > > Or maybe it's okay to decrement sp while it's equal to 0x0? > > AFAIK, it would be OK if underlying emulated hardware had any kind of > memory mapped at the end of address space (sp would wrap in that > case), but as far as I can tell QEMU ARM64 virt platform doesn't, > which I think is the reason you are seeing the result you are seeing. > > > Any ideas? comments? > > I am not sure about the proper way to resolve this, I'd be curious to > hear from Raphael (original author, CC'd in this reply) and how this > worked for him first. However you can very quickly verify/disprove > your bad SP value theory by doing: > > set $sp=0xBFF0 > > before letting the processor hit those SP instructions when you step > through it and see if barebox runs fine after that. > > Thanks, > Andrey Smirnov > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox Thank you for adding in CC. I have looked at bit at this issue, indeed the fact that " barebox_arm_reset_vector" is not naked, is not good. I did not catch this issue by the time I have get my work merged, because it was not crashing (don't know why...). I have test with the master branch and barebox crashs but I can have some serial output: barebox 2018.06.0-00145-gfe040e0-dirty #1 Fri Jun 29 09:06:54 DST 2018 Board: ARM QEMU virt64 DABT (current EL) exception (ESR 0x944b) at 0x elr: 4100cad8 lr : 4100cac4 x0 : 00f0 x1 : 0001 x2 : bffefd2c x3 : x4 : 0008 x5 : x6 : 40c06710 x7 : Anyway, the qemu virt board is broken. I will try to work a bit on this in the week end. Andrew, how do you set up the stack on the imx8 board ? Thanks, Raphael ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v4 0/12] Add basic support for arm64
Hi, 2016-07-04 9:27 GMT+02:00 Sascha Hauer : > Hi Raphael, > > On Wed, Jun 29, 2016 at 10:22:07AM +0200, Raphael Poggi wrote: >> This patch series introduces a basic support for arm64. >> >> The arm64 code is merged in the current arch/arm directory. >> I try to be iterative in the merge process, and find correct solutions >> to handle both architecture at some places. >> >> I test the patch series by compiling arm64 virt machine and arm32 >> vexpress-a9 and test it >> in qemu, everything seems to work. > > > I'm happy with te general structure now. There surely still is much work > to do for full aarch64 support, but the current state does not disturb arm32 > and > I think the remaining issues can be fixed in tree. I can merge this > series if you like, or I could delay merging in case you want to > continue working on this series without having to create incremental > patches. > > Finally could you provide a qemu command line to start the image? A > patch adding Documentation/boards/aarch64-qemu-virt.rst similar to > Documentation/boards/digic.rst would be nice. No problem, I will send a v5 (adding this patch) today, and then it would be fine to merge this series. Thanks, Raphaël > > Sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v3 03/14] arm: introduce lib64 for arm64 related stuff
2016-06-29 8:00 GMT+02:00 Sascha Hauer :
> On Tue, Jun 28, 2016 at 09:15:06AM +0200, Raphaël Poggi wrote:
>> 2016-06-28 8:47 GMT+02:00 Sascha Hauer :
>> > On Fri, Jun 24, 2016 at 02:23:50PM +0200, Raphael Poggi wrote:
>> >> Signed-off-by: Raphael Poggi
>> >> ---
>> >> arch/arm/lib64/Makefile| 10 +
>> >> arch/arm/lib64/armlinux.c | 104
>> >> arch/arm/lib64/asm-offsets.c | 16 ++
>> >> arch/arm/lib64/barebox.lds.S | 125 +
>> >> arch/arm/lib64/bootm.c | 572
>> >> +
>> >> arch/arm/lib64/copy_template.S | 192 ++
>> >> arch/arm/lib64/div0.c | 27 ++
>> >> arch/arm/lib64/memcpy.S| 74 ++
>> >> arch/arm/lib64/memset.S| 215
>> >> 9 files changed, 1335 insertions(+)
>> >> create mode 100644 arch/arm/lib64/Makefile
>> >> create mode 100644 arch/arm/lib64/armlinux.c
>> >> create mode 100644 arch/arm/lib64/asm-offsets.c
>> >> create mode 100644 arch/arm/lib64/barebox.lds.S
>> >> create mode 100644 arch/arm/lib64/bootm.c
>> >> create mode 100644 arch/arm/lib64/copy_template.S
>> >> create mode 100644 arch/arm/lib64/div0.c
>> >> create mode 100644 arch/arm/lib64/memcpy.S
>> >> create mode 100644 arch/arm/lib64/memset.S
>> >>
>> >> diff --git a/arch/arm/lib64/Makefile b/arch/arm/lib64/Makefile
>> >> new file mode 100644
>> >> index 000..a424293
>> >> --- /dev/null
>> >> +++ b/arch/arm/lib64/Makefile
>> >> @@ -0,0 +1,10 @@
>> >> +obj-$(CONFIG_ARM_LINUX) += armlinux.o
>> >> +obj-$(CONFIG_BOOTM) += bootm.o
>> >> +obj-y+= div0.o
>> >> +obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memcpy.o
>> >> +obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memset.o
>> >> +extra-y += barebox.lds
>> >> +
>> >> +pbl-y+= lib1funcs.o
>> >> +pbl-y+= ashldi3.o
>> >> +pbl-y+= div0.o
>> >> diff --git a/arch/arm/lib64/armlinux.c b/arch/arm/lib64/armlinux.c
>> >> new file mode 100644
>> >> index 000..c70e079
>> >> --- /dev/null
>> >> +++ b/arch/arm/lib64/armlinux.c
>> >> @@ -0,0 +1,104 @@
>> >> +/*
>> >> + * (C) Copyright 2002
>> >> + * Sysgo Real-Time Solutions, GmbH
>> >> + * Marius Groeger
>> >> + *
>> >> + * Copyright (C) 2001 Erik Mouw (j.a.k.m...@its.tudelft.nl)
>> >> + *
>> >> + * This program is free software; you can redistribute it and/or modify
>> >> + * it under the terms of the GNU General Public License as published by
>> >> + * the Free Software Foundation; either version 2 of the License, or
>> >> + * (at your option) any later version.
>> >> + *
>> >> + * This program is distributed in the hope that it will be useful,
>> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> >> + * GNU General Public License for more details.
>> >> + */
>> >> +
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +#include
>> >> +
>> >> +static void *armlinux_bootparams = NULL;
>> >> +
>> >> +static int armlinux_architecture;
>> >> +static u32 armlinux_system_rev;
>> >> +static u64 armlinux_system_serial;
>> >> +
>> >> +BAREBOX_MAGICVAR(armlinux_architecture, "ARM machine ID");
>> >> +BAREBOX_MAGICVAR(armlinux_system_rev, "ARM system revision");
>> >> +BAREBOX_MAGICVAR(armlinux_system_serial, "ARM system serial");
>> >> +
>> >> +void armlinux_set_architecture(int architecture)
>> >> +{
>> >> + export_env_ull("armlinux_archite
Re: [PATCH v3 03/14] arm: introduce lib64 for arm64 related stuff
2016-06-28 8:47 GMT+02:00 Sascha Hauer :
> On Fri, Jun 24, 2016 at 02:23:50PM +0200, Raphael Poggi wrote:
>> Signed-off-by: Raphael Poggi
>> ---
>> arch/arm/lib64/Makefile| 10 +
>> arch/arm/lib64/armlinux.c | 104
>> arch/arm/lib64/asm-offsets.c | 16 ++
>> arch/arm/lib64/barebox.lds.S | 125 +
>> arch/arm/lib64/bootm.c | 572
>> +
>> arch/arm/lib64/copy_template.S | 192 ++
>> arch/arm/lib64/div0.c | 27 ++
>> arch/arm/lib64/memcpy.S| 74 ++
>> arch/arm/lib64/memset.S| 215
>> 9 files changed, 1335 insertions(+)
>> create mode 100644 arch/arm/lib64/Makefile
>> create mode 100644 arch/arm/lib64/armlinux.c
>> create mode 100644 arch/arm/lib64/asm-offsets.c
>> create mode 100644 arch/arm/lib64/barebox.lds.S
>> create mode 100644 arch/arm/lib64/bootm.c
>> create mode 100644 arch/arm/lib64/copy_template.S
>> create mode 100644 arch/arm/lib64/div0.c
>> create mode 100644 arch/arm/lib64/memcpy.S
>> create mode 100644 arch/arm/lib64/memset.S
>>
>> diff --git a/arch/arm/lib64/Makefile b/arch/arm/lib64/Makefile
>> new file mode 100644
>> index 000..a424293
>> --- /dev/null
>> +++ b/arch/arm/lib64/Makefile
>> @@ -0,0 +1,10 @@
>> +obj-$(CONFIG_ARM_LINUX) += armlinux.o
>> +obj-$(CONFIG_BOOTM) += bootm.o
>> +obj-y+= div0.o
>> +obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memcpy.o
>> +obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memset.o
>> +extra-y += barebox.lds
>> +
>> +pbl-y+= lib1funcs.o
>> +pbl-y+= ashldi3.o
>> +pbl-y+= div0.o
>> diff --git a/arch/arm/lib64/armlinux.c b/arch/arm/lib64/armlinux.c
>> new file mode 100644
>> index 000..c70e079
>> --- /dev/null
>> +++ b/arch/arm/lib64/armlinux.c
>> @@ -0,0 +1,104 @@
>> +/*
>> + * (C) Copyright 2002
>> + * Sysgo Real-Time Solutions, GmbH
>> + * Marius Groeger
>> + *
>> + * Copyright (C) 2001 Erik Mouw (j.a.k.m...@its.tudelft.nl)
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +static void *armlinux_bootparams = NULL;
>> +
>> +static int armlinux_architecture;
>> +static u32 armlinux_system_rev;
>> +static u64 armlinux_system_serial;
>> +
>> +BAREBOX_MAGICVAR(armlinux_architecture, "ARM machine ID");
>> +BAREBOX_MAGICVAR(armlinux_system_rev, "ARM system revision");
>> +BAREBOX_MAGICVAR(armlinux_system_serial, "ARM system serial");
>> +
>> +void armlinux_set_architecture(int architecture)
>> +{
>> + export_env_ull("armlinux_architecture", architecture);
>> + armlinux_architecture = architecture;
>> +}
>> +
>> +int armlinux_get_architecture(void)
>> +{
>> + getenv_uint("armlinux_architecture", &armlinux_architecture);
>> +
>> + return armlinux_architecture;
>> +}
>> +
>> +void armlinux_set_revision(unsigned int rev)
>> +{
>> + export_env_ull("armlinux_system_rev", rev);
>> + armlinux_system_rev = rev;
>> +}
>> +
>> +unsigned int armlinux_get_revision(void)
>> +{
>> + getenv_uint("armlinux_system_rev", &armlinux_system_rev);
>> +
>> + return armlinux_system_rev;
>> +}
>> +
>> +void armlinux_set_serial(u64 serial)
>> +{
>> + export_env_ull("armlinux_system_serial", serial);
>> + armlinux_system_serial = serial;
>> +}
>> +
>> +u64 armlinux_get_serial(void)
>> +{
>> + getenv_ull("armlinux_system_serial", &armlinux_system_serial);
>> +
>> + return armlinux_system_serial;
>> +}
>> +
>> +void armlinux_set_bootparams(void *params)
>> +{
>> + armlinux_bootparams = params;
>> +}
>
> All of the above is not needed. Sorry, it seems I overlooked this last
> time.
Ok for that, I will only let the "start_linux" function.
>
>> diff --git a/arch/arm/lib64/bootm.c b/arch/arm/lib64/bootm.c
>
> I still think this file should not be here. You can always copy/modify
> it from the arm32 bootm.c once you need it, but at the moment this file
> is the reason this patch can't be applied. I'd really like to
> review/apply a "arm64: Add bootm code" patch once it's ready.
I understand, but since bootm is needed for booting (especially via
do_bootm_linux)
and also lib/bootm.c is not compiled in arm64 case, how can I use
lib/bootm.c in
Re: [PATCH v3 06/14] arm: cpu: start: arm64 does not support relocation
2016-06-28 8:50 GMT+02:00 Sascha Hauer : > On Fri, Jun 24, 2016 at 02:23:53PM +0200, Raphael Poggi wrote: >> For now, the relocation is not supported in arm64, so >> enclosed call to "setup_c" with #if directive >> >> Signed-off-by: Raphael Poggi >> --- >> arch/arm/cpu/start.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/arm/cpu/start.c b/arch/arm/cpu/start.c >> index e037d91..5051115 100644 >> --- a/arch/arm/cpu/start.c >> +++ b/arch/arm/cpu/start.c >> @@ -151,7 +151,9 @@ __noreturn void barebox_non_pbl_start(unsigned long >> membase, >> relocate_to_adr(barebox_base); >> } >> >> +#if __LINUX_ARM_ARCH__ <= 7 >> setup_c(); >> +#endif > > setup_c not only relocates the binary, it also clears the bss segment. > Where is this done on arm64? It is not done...I forgot about that. I will create a setupc_64.S, in the first time, this will only clear bss. Later, we could also add relocation support. Raphaël > > Sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re:
Hi Sascha, Beside the comments on [PATCH 01/12] and [PATCH 03/12], do you have any comments about the series ? I have a v3 series ready to be sent (with your recent suggestions). Thanks, Raphaël 2016-06-14 9:06 GMT+02:00 Raphael Poggi : > Change since v1: > PATCH 2/12: remove hunk which belongs to patch adding mach-qemu > > PATCH 3/12: remove unused files > > PATCH 4/12: create lowlevel64 > > PATCH 11/12:create pgtables64 (nothing in common with the arm32 > version) > > PATCH 12/12:rename "mach-virt" => "mach-qemu" > rename board "qemu_virt64" > remove board env files > > > Hello, > > This patch series introduces a basic support for arm64. > > The arm64 code is merged in the current arch/arm directory. > I try to be iterative in the merge process, and find correct solutions > to handle both architecture at some places. > > I test the patch series by compiling arm64 virt machine and arm32 vexpress-a9 > and test it > in qemu, everything seems to work. > > Thanks, > Raphaël > > arch/arm/Kconfig | 28 ++ > arch/arm/Makefile | 30 +- > arch/arm/boards/Makefile | 1 + > arch/arm/boards/qemu-virt64/Kconfig| 8 + > arch/arm/boards/qemu-virt64/Makefile | 1 + > arch/arm/boards/qemu-virt64/init.c | 67 > arch/arm/configs/qemu_virt64_defconfig | 55 +++ > arch/arm/cpu/Kconfig | 29 +- > arch/arm/cpu/Makefile | 26 +- > arch/arm/cpu/cache-armv8.S | 168 + > arch/arm/cpu/cache.c | 19 + > arch/arm/cpu/cpu.c | 5 + > arch/arm/cpu/cpuinfo.c | 58 ++- > arch/arm/cpu/exceptions_64.S | 127 +++ > arch/arm/cpu/interrupts.c | 47 +++ > arch/arm/cpu/lowlevel_64.S | 40 ++ > arch/arm/cpu/mmu.h | 54 +++ > arch/arm/cpu/mmu_64.c | 333 + > arch/arm/cpu/start.c | 2 + > arch/arm/include/asm/bitops.h | 5 + > arch/arm/include/asm/cache.h | 9 + > arch/arm/include/asm/mmu.h | 14 +- > arch/arm/include/asm/pgtable64.h | 140 +++ > arch/arm/include/asm/system.h | 46 ++- > arch/arm/include/asm/system_info.h | 38 ++ > arch/arm/lib64/Makefile| 10 + > arch/arm/lib64/armlinux.c | 275 ++ > arch/arm/lib64/asm-offsets.c | 16 + > arch/arm/lib64/barebox.lds.S | 125 +++ > arch/arm/lib64/bootm.c | 572 > + > arch/arm/lib64/copy_template.S | 192 ++ > arch/arm/lib64/div0.c | 27 ++ > arch/arm/lib64/memcpy.S| 74 > arch/arm/lib64/memset.S| 215 +++ > arch/arm/lib64/module.c| 98 + > arch/arm/mach-qemu/Kconfig | 18 + > arch/arm/mach-qemu/Makefile| 2 + > arch/arm/mach-qemu/include/mach/debug_ll.h | 24 ++ > arch/arm/mach-qemu/include/mach/devices.h | 13 + > arch/arm/mach-qemu/virt_devices.c | 30 ++ > arch/arm/mach-qemu/virt_lowlevel.c | 19 + > 41 files changed, 3044 insertions(+), 16 deletions(-) > > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v2 01/12] arm: add armv8 Kconfig entries
2016-06-15 8:33 GMT+02:00 Sascha Hauer : > Hi Raphael, > > On Tue, Jun 14, 2016 at 09:06:35AM +0200, Raphael Poggi wrote: >> Signed-off-by: Raphael Poggi >> --- >> arch/arm/Kconfig | 23 +++ >> arch/arm/cpu/Kconfig | 29 - >> 2 files changed, 51 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig >> index 1fc887b..986fdaa 100644 >> --- a/arch/arm/Kconfig >> +++ b/arch/arm/Kconfig >> @@ -315,6 +315,29 @@ config ARM_BOARD_APPEND_ATAG >> >> endmenu >> >> +choice >> + prompt "Barebox code model" >> + help >> + You should only select this option if you have a workload that >> + actually benefits from 64-bit processing or if your machine has >> + large memory. You will only be presented a single option in this >> + menu if your system does not support both 32-bit and 64-bit modes. >> + >> +config 32BIT >> + bool "32-bit barebox" >> + depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL >> + help >> + Select this option if you want to build a 32-bit barebox. >> + >> +config 64BIT >> + bool "64-bit barebox" >> + depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL >> + select ARCH_DMA_ADDR_T_64BIT >> + help >> + Select this option if you want to build a 64-bit barebox. >> + >> +endchoice >> + >> menu "ARM specific settings" >> >> config ARM_OPTIMZED_STRING_FUNCTIONS >> diff --git a/arch/arm/cpu/Kconfig b/arch/arm/cpu/Kconfig > > arm64 needs 64bit pointers. You could merge the following to this patch > to make resource_size_t 64bit wide and to get rid of the "warning: cast > from pointer to integer of different size [-Wpointer-to-int-cast]" > warnings. Ok, thanks > > Sascha > > From 599547f4054ca715f66a83bf49dc9293e3cc0af0 Mon Sep 17 00:00:00 2001 > From: Sascha Hauer > Date: Wed, 15 Jun 2016 08:29:51 +0200 > Subject: [PATCH] arm64: select PHYS_ADDR_T_64BIT > > Signed-off-by: Sascha Hauer > --- > arch/arm/cpu/Kconfig | 4 > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/cpu/Kconfig b/arch/arm/cpu/Kconfig > index fd327a8..c90501e 100644 > --- a/arch/arm/cpu/Kconfig > +++ b/arch/arm/cpu/Kconfig > @@ -1,9 +1,13 @@ > comment "Processor Type" > > +config PHYS_ADDR_T_64BIT > + bool > + > config CPU_32 > bool > > config CPU_64 > + select PHYS_ADDR_T_64BIT > bool > > # Select CPU types depending on the architecture selected. This selects > -- > 2.8.1 > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v2 03/12] arm: introduce lib64 for arm64 related stuff
Hi,
2016-06-15 8:15 GMT+02:00 Sascha Hauer :
> On Tue, Jun 14, 2016 at 09:06:37AM +0200, Raphael Poggi wrote:
>> diff --git a/arch/arm/lib64/Makefile b/arch/arm/lib64/Makefile
>> new file mode 100644
>> index 000..a424293
>> --- /dev/null
>> +++ b/arch/arm/lib64/Makefile
>> @@ -0,0 +1,10 @@
>> +obj-$(CONFIG_ARM_LINUX) += armlinux.o
>> +obj-$(CONFIG_BOOTM) += bootm.o
>> +obj-y+= div0.o
>> +obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memcpy.o
>> +obj-$(CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS) += memset.o
>> +extra-y += barebox.lds
>> +
>> +pbl-y+= lib1funcs.o
>> +pbl-y+= ashldi3.o
>> +pbl-y+= div0.o
>> diff --git a/arch/arm/lib64/armlinux.c b/arch/arm/lib64/armlinux.c
>> new file mode 100644
>> index 000..21a2292
>> --- /dev/null
>> +++ b/arch/arm/lib64/armlinux.c
>> @@ -0,0 +1,275 @@
>
> [...]
>
>> +static void setup_tags(unsigned long initrd_address,
>> + unsigned long initrd_size, int swap)
>> +{
>> + const char *commandline = linux_bootargs_get();
>> +
>> + setup_start_tag();
>> + setup_memory_tags();
>> + setup_commandline_tag(commandline, swap);
>> +
>> + if (initrd_size)
>> + setup_initrd_tag(initrd_address, initrd_size);
>> +
>> + setup_revision_tag();
>> + setup_serial_tag();
>> +#ifdef CONFIG_ARM_BOARD_APPEND_ATAG
>> + if (atag_appender != NULL)
>> + params = atag_appender(params);
>> +#endif
>> + setup_end_tag();
>> +
>> + printf("commandline: %s\n"
>> +"arch_number: %d\n", commandline, armlinux_get_architecture());
>> +
>> +}
>
> All the code around ATAGs can be removed. ARM64 is device tree only and
> won't ever need this.
Ok, I have done some rework of this part and remove all *_tags functions.
>
>> +
>> +void start_linux(void *adr, int swap, unsigned long initrd_address,
>> + unsigned long initrd_size, void *oftree)
>> +{
>> + void (*kernel)(int zero, int arch, void *params) = adr;
>> + void *params = NULL;
>> + int architecture;
>> +
>> + if (oftree) {
>> + pr_debug("booting kernel with devicetree\n");
>> + params = oftree;
>> + } else {
>> + setup_tags(initrd_address, initrd_size, swap);
>> + params = armlinux_get_bootparams();
>> + }
>> + architecture = armlinux_get_architecture();
>> +
>> + shutdown_barebox();
>> +
>> + kernel(0, architecture, params);
>> +}
>
>> diff --git a/arch/arm/lib64/bootm.c b/arch/arm/lib64/bootm.c
>
> This file is an exact copy of arch/arm/lib/bootm.c as of a324fb5a, so it
> seems that either the 32bit version works for arm64 or this is untested.
>
> Have you already booted a kernel? Does it work? Although starting a
> kernel is admittedly a key feature for a bootloader, we could drop the
> code from the initial arm64 porting effort if it doesn't work yet.
I have made some rework for booting a kernel, and bootm remains the
same as arch/arm/lib/bootm.c.
However, I think it is better to conserve the two files, because in a
near future it will be useful to add support of arm64 Image format in
arch/arm/lib64/bootm.c.
>
>> diff --git a/arch/arm/lib64/module.c b/arch/arm/lib64/module.c
>
> Please drop this file. I suppose it won't work on arm64 anyway, so
> there's no need to carry a nonworking copy of arm32 module support in
> the arm64 tree.
Ok
>
> Sascha
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
>
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Re: [PATCH 12/12] arm: boards: add virt board
2016-06-07 14:59 GMT+02:00 Antony Pavlov : > On Tue, 7 Jun 2016 13:53:49 +0200 > Raphaël Poggi wrote: > >> 2016-06-07 13:00 GMT+02:00 Antony Pavlov : >> > On Thu, 2 Jun 2016 10:06:58 +0200 >> > Raphael Poggi wrote: >> > >> >> Add qemu virt board which emulates arm64 board. >> >> >> >> Signed-off-by: Raphael Poggi >> >> --- >> >> arch/arm/Kconfig | 9 >> >> arch/arm/boards/Makefile | 1 + >> >> arch/arm/boards/virt/Kconfig | 8 >> > >> > Can we use a more descriptive 'qemu-virt' name for this machine/board >> > instead of 'virt'? >> >> Qemu virt machine support armv7 and armv8 cpu, maybe we can use the >> name "mach-qemu" for the machine and "qemu-virt64" for the board. >> >> With this approach we use a generic name for the machine (since qemu >> virt machine support armv7/armv8, we do not need to distinguish >> between arm/arm64), >> and made the distinction arm/arm64 only in board name. >> >> This also lets the possibility, for someone who wants to add support >> for qemu virt arm32 board, to not create another machine folder. >> >> What do you think about that ? > > So you are proposing to introduce these directories: > > arch/arm/boards/qemu-virt64/ > arch/arm/mach-qemu/ Yes, exactly. > > I propose to use 'arch/arm/mach-qemu-virt' for machine dir, > because qemu supports several arm-based machines, not only the virt machine. > > On the other hand the 'mach-qemu-virt' name is too long > and 'mach-qemu' may be is a better solution. "mach-qemu-virt" seems too long. Another proposition: we can choose "mach-qemu", and to distinguish qemu machine use the same way as mach-at91, ie: arch/arm/mach-qemu/ --> virt_devices.c --> virt_lowlevel.c --> etc... This also implies to add some Kconfig entries to handle the multiple qemu machines. > > >> > >> >> arch/arm/boards/virt/Makefile | 1 + >> >> arch/arm/boards/virt/env/bin/_update | 36 >> >> arch/arm/boards/virt/env/bin/boot | 38 + >> > >> > ... skipped ... >> > >> > -- >> > Best regards, >> > Antony Pavlov >> > >> > ___ >> > barebox mailing list >> > barebox@lists.infradead.org >> > http://lists.infradead.org/mailman/listinfo/barebox > > > -- > -- > Best regards, > Antony Pavlov > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 12/12] arm: boards: add virt board
2016-06-07 13:00 GMT+02:00 Antony Pavlov : > On Thu, 2 Jun 2016 10:06:58 +0200 > Raphael Poggi wrote: > >> Add qemu virt board which emulates arm64 board. >> >> Signed-off-by: Raphael Poggi >> --- >> arch/arm/Kconfig | 9 >> arch/arm/boards/Makefile | 1 + >> arch/arm/boards/virt/Kconfig | 8 > > Can we use a more descriptive 'qemu-virt' name for this machine/board instead > of 'virt'? Qemu virt machine support armv7 and armv8 cpu, maybe we can use the name "mach-qemu" for the machine and "qemu-virt64" for the board. With this approach we use a generic name for the machine (since qemu virt machine support armv7/armv8, we do not need to distinguish between arm/arm64), and made the distinction arm/arm64 only in board name. This also lets the possibility, for someone who wants to add support for qemu virt arm32 board, to not create another machine folder. What do you think about that ? Raphaël > >> arch/arm/boards/virt/Makefile | 1 + >> arch/arm/boards/virt/env/bin/_update | 36 >> arch/arm/boards/virt/env/bin/boot | 38 + > > ... skipped ... > > -- > Best regards, > Antony Pavlov > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 12/12] arm: boards: add virt board
akefile b/arch/arm/boards/virt/Makefile
>> new file mode 100644
>> index 000..eb072c0
>> --- /dev/null
>> +++ b/arch/arm/boards/virt/Makefile
>> @@ -0,0 +1 @@
>> +obj-y += init.o
>> diff --git a/arch/arm/boards/virt/env/bin/_update
>> b/arch/arm/boards/virt/env/bin/_update
>
> Please drop these environment files. New boards for sure should use
> defenv2 and normally for this you don't need any board specific
> environment files.
>
>> diff --git a/arch/arm/boards/virt/init.c b/arch/arm/boards/virt/init.c
>> new file mode 100644
>> index 000..9626067
>> --- /dev/null
>> +++ b/arch/arm/boards/virt/init.c
>> @@ -0,0 +1,67 @@
>> +/*
>> + * Copyright (C) 2016 Raphaël Poggi
>> + *
>> + * GPLv2 only
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +static int virt_mem_init(void)
>> +{
>> + virt_add_ddram(SZ_512M);
>> +
>> + add_cfi_flash_device(0, 0x, SZ_4M, 0);
>> +
>> + devfs_add_partition("nor0", 0x0, 0x4, DEVFS_PARTITION_FIXED,
>> "self0");
>> + devfs_add_partition("nor0", 0x4, 0x2, DEVFS_PARTITION_FIXED,
>> "env0");
>> +
>> + return 0;
>> +}
>> +mem_initcall(virt_mem_init);
>> +
>> +static int virt_console_init(void)
>> +{
>> + virt_register_uart(0);
>> +
>> + return 0;
>> +}
>> +console_initcall(virt_console_init);
>> +
>> +static int virt_core_init(void)
>> +{
>> + char *hostname = "virt";
>> +
>> + if (cpu_is_cortex_a53())
>> + hostname = "virt-a53";
>> + else if (cpu_is_cortex_a57())
>> + hostname = "virt-a57";
>> +
>> + barebox_set_model("ARM QEMU virt");
>> + barebox_set_hostname(hostname);
>> +
>> + return 0;
>> +}
>> +postcore_initcall(virt_core_init);
>> +
>> +static int virt_mmu_enable(void)
>> +{
>> + /* Mapping all periph range */
>> + arch_remap_range(0x0900, 0x0100, PMD_SECT_DEF_CACHED);
>> +
>> + /* Mapping all flash range */
>> + arch_remap_range(0x, 0x0800, PMD_SECT_DEF_CACHED);
>
> Hm, mapping the peripherals and the flash cached? This seems wrong.
> Either the mapping does not work or your periphals do not work ;)
You are right, in fact I figure out that qemu does not handle
instruction or data cache, that's why it was working...
>
>> +
>> + mmu_enable();
>> +
>> + return 0;
>> +}
>> +postmmu_initcall(virt_mmu_enable);
>> diff --git a/arch/arm/mach-virt/reset.c b/arch/arm/mach-virt/reset.c
>> new file mode 100644
>> index 000..fb895eb
>> --- /dev/null
>> +++ b/arch/arm/mach-virt/reset.c
>> @@ -0,0 +1,24 @@
>> +/*
>> + * Copyright (C) 2016 Raphaël Poggi
>> + *
>> + * GPLv2 only
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +static void virt_reset_soc(struct restart_handler *rst)
>> +{
>> + hang();
>> +}
>> +
>> +static int restart_register_feature(void)
>> +{
>> + restart_handler_register_fn(virt_reset_soc);
>> +
>> + return 0;
>> +}
>> +coredevice_initcall(restart_register_feature);
>
> You can drop this. When no restart_handler is registered then hang() is
> the default behaviour anyway.
>
> Sascha
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
>
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Re: [PATCH 0/12] Add basic support for arm64
Hi, 2016-06-03 11:16 GMT+02:00 Sascha Hauer : > On Thu, Jun 02, 2016 at 10:06:46AM +0200, Raphael Poggi wrote: >> Hello, >> >> This patch series introduces a basic support for arm64. >> >> The arm64 code is merged in the current arch/arm directory. >> I try to be iterative in the merge process, and find correct solutions >> to handle both architecture at some places. >> >> I test the patch series by compiling arm64 virt machine and arm32 >> vexpress-a9 and test it >> in qemu, everything seems to work. > > Overall this looks quite good already and I think we can soon start > merging the first steps. What's important for me is that arm32 is > unaffected by the changes (seems to be the case for this series) and > that we do not merge code that does not work and is only present because > it's copied from arm32 Thanks for the code review, I will fix and rework all the points you raised and send a v2. I will take care to don't add code which will be unused (like I did in lib64 directory...) for arm64. Raphaël > > Sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 02/12] arm: Makefile: rework makefile to handle armv8
2016-06-03 9:27 GMT+02:00 Sascha Hauer : > On Thu, Jun 02, 2016 at 10:06:48AM +0200, Raphael Poggi wrote: >> Signed-off-by: Raphael Poggi >> --- >> arch/arm/Makefile | 30 -- >> 1 file changed, 28 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm/Makefile b/arch/arm/Makefile >> index 5ccdb83..df4832f 100644 >> --- a/arch/arm/Makefile >> +++ b/arch/arm/Makefile >> @@ -1,7 +1,11 @@ >> >> CPPFLAGS += -D__ARM__ -fno-strict-aliasing >> # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb: >> +ifeq ($(CONFIG_CPU_V8),y) >> +CPPFLAGS +=$(call cc-option,-maarch64,) >> +else >> CPPFLAGS +=$(call cc-option,-marm,) >> +endif >> >> ifeq ($(CONFIG_CPU_BIG_ENDIAN),y) >> CPPFLAGS += -mbig-endian >> @@ -17,7 +21,9 @@ endif >> # at least some of the code would be executed with MMU off, lets be >> # conservative and instruct the compiler not to generate any unaligned >> # accesses >> +ifeq ($(CONFIG_CPU_V8),n) >> CFLAGS += -mno-unaligned-access >> +endif >> >> >> # This selects which instruction set is used. >> @@ -33,12 +39,17 @@ arch-$(CONFIG_CPU_32v4T) :=-D__LINUX_ARM_ARCH__=4 >> -march=armv4t >> tune-$(CONFIG_CPU_ARM920T) :=-mtune=arm9tdmi >> tune-$(CONFIG_CPU_ARM926T) :=-mtune=arm9tdmi >> tune-$(CONFIG_CPU_XSCALE):=$(call >> cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale >> +arch-$(CONFIG_CPU_64v8) := -D__LINUX_ARM_ARCH__=8 $(call >> cc-option,-march=armv8-a) > > Can we move this above the arch-$(CONFIG_CPU_32v7) line? Yes, no problem. > >> >> +ifeq ($(CONFIG_CPU_V8), y) >> +CFLAGS_ABI :=-mabi=lp64 >> +else >> ifeq ($(CONFIG_AEABI),y) >> CFLAGS_ABI :=-mabi=aapcs-linux -mno-thumb-interwork >> else >> CFLAGS_ABI :=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) $(call >> cc-option,-mno-thumb-interwork,) >> endif >> +endif >> >> ifeq ($(CONFIG_ARM_UNWIND),y) >> CFLAGS_ABI +=-funwind-tables >> @@ -51,8 +62,13 @@ CFLAGS_THUMB2 :=-mthumb $(AFLAGS_AUTOIT) >> $(AFLAGS_NOWARN) >> AFLAGS_THUMB2:=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb >> endif >> >> +ifeq ($(CONFIG_CPU_V8), y) >> +CPPFLAGS += $(CFLAGS_ABI) $(arch-y) $(tune-y) >> +AFLAGS += -include asm/unified.h >> +else >> CPPFLAGS += $(CFLAGS_ABI) $(arch-y) $(tune-y) -msoft-float $(CFLAGS_THUMB2) >> AFLAGS += -include asm/unified.h -msoft-float $(AFLAGS_THUMB2) >> +endif >> >> # Machine directory name. This list is sorted alphanumerically >> # by CONFIG_* macro name. >> @@ -78,6 +94,7 @@ machine-$(CONFIG_ARCH_VEXPRESS) := vexpress >> machine-$(CONFIG_ARCH_TEGRA) := tegra >> machine-$(CONFIG_ARCH_UEMD) := uemd >> machine-$(CONFIG_ARCH_ZYNQ) := zynq >> +machine-$(CONFIG_ARCH_VIRT) := virt > > This hunk belongs to the patch adding mach-virt. Oops you are right, I will correct it in v2. > > Otherwise this looks fine to me. > > Sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH] bitops: fls64: add missing include
2016-04-14 9:58 GMT+02:00 Sascha Hauer : > On Wed, Apr 13, 2016 at 04:18:58PM +0200, Raphael Poggi wrote: >> Signed-off-by: Raphael Poggi >> --- >> include/asm-generic/bitops/fls64.h | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/include/asm-generic/bitops/fls64.h >> b/include/asm-generic/bitops/fls64.h >> index 86d403f..e8eff76 100644 >> --- a/include/asm-generic/bitops/fls64.h >> +++ b/include/asm-generic/bitops/fls64.h >> @@ -2,6 +2,7 @@ >> #define _ASM_GENERIC_BITOPS_FLS64_H_ >> >> #include >> +#include > > This is wrong. This include must not be here to give the architecture > the chance to provide an optimized version of __fls(), but the generic > version of fls64(). This may not be clear in barebox context since all > users use the generic version, but in the kernel there are some > architectures implementing their own version of __fls() while others use > the generic variant: > > arch/mips/include/asm/bitops.h:480:static inline unsigned long __fls(unsigned > long word) > ... > #include > > arch/metag/include/asm/bitops.h:118:#include > ... > #include > > Sascha > > > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | Ok, I understand how it works now, Thank you, Raphaël ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: support of arm64 architecture
Hi, Thank you for your answer. At the beginning, I have tried to add arm64 specific code on the arm architecture folder, but it becomes a mess... Nevertheless, I can give an another try with this solution and then we can decide. 2016-04-08 19:30 GMT+02:00 Sascha Hauer : > Hi Raphaël, > > On Fri, Apr 08, 2016 at 02:01:21PM +0200, Raphaël Poggi wrote: >> Hi all, >> >> I am working on porting barebox on arm64 architecture. >> >> So I have some questions about it: >> >> - Is there any interest for barebox to support this architecture ? > > Definitely, yes. > >> >> - My port is running at EL1 for the moment, does the bootloader have >> to run at EL3 ? If yes, do you have hint to achieve this ? >> I think UEFI is running at EL3, but I am confused about that, >> what is the difference between UEFI and barebox ? Are they both >> booloader ? (I guess it is a "noob" question :/) > > UEFI is an interface to the firmware whereas barebox is a firmware. We > could implement a UEFI interface for barebox (the U-Boot guys already > did this). Also barebox can run on top of firmware with a (U)Efi > interface. > >> >> - I have some issues with malloc, when I use tlsf all malloc failed, >> but not with dlmalloc implementation, do you have an idea about this ? > > Do you have TLSF_64BIT defined? You may have defined it automatically > when you have CONFIG_64BIT defined, but if not tlsf malloc will not > work. > >> >> >> At the moment the current limitations of my port are : >> - MMU not implemented >> - barebox running at EL1 >> - barebox env not working >> - only test on qemu >> >> If you want to test it: >> https://github.com/raphui/barebox/tree/dev/armv8a_cleanup > > From a first look it the arm64 code looks very familiar. Do you think we > could merge it into the arm architecture rather than creating a new > architecture? > > I don't know in which exception level barebox should finally run in, but > I don't think that's a showstopper. > > Sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
support of arm64 architecture
Hi all, I am working on porting barebox on arm64 architecture. So I have some questions about it: - Is there any interest for barebox to support this architecture ? - My port is running at EL1 for the moment, does the bootloader have to run at EL3 ? If yes, do you have hint to achieve this ? I think UEFI is running at EL3, but I am confused about that, what is the difference between UEFI and barebox ? Are they both booloader ? (I guess it is a "noob" question :/) - I have some issues with malloc, when I use tlsf all malloc failed, but not with dlmalloc implementation, do you have an idea about this ? At the moment the current limitations of my port are : - MMU not implemented - barebox running at EL1 - barebox env not working - only test on qemu If you want to test it: https://github.com/raphui/barebox/tree/dev/armv8a_cleanup I can also send a patch with [RFC] tag is needed. If you have any suggestions or questions, tell me. Thank you, Raphaël Poggi ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 1/2] arm: at91: fix ecc_mode on non atmel boards
Good catch, I ACK this patch.
2015-01-06 12:37 GMT+01:00 Jean-Christophe PLAGNIOL-VILLARD
:
> since
> commit 54bcca52cb4cbbecd1403b9091fe651bd0fd
> Author: Raphaël Poggi
>
> mtd: atmel_nand: retrieve ecc_mode from pdata
>
> break most of the non atmel AT91 boards that did not provide a ecc_mode
> params in the nand pdata
>
> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD
> Cc: Raphaël Poggi
> ---
> arch/arm/boards/animeo_ip/init.c | 1 +
> arch/arm/boards/pm9261/init.c | 1 +
> arch/arm/boards/pm9263/init.c | 1 +
> arch/arm/boards/pm9g45/init.c | 1 +
> arch/arm/boards/qil-a926x/init.c | 1 +
> arch/arm/boards/telit-evk-pro3/init.c | 2 ++
> arch/arm/boards/tny-a926x/init.c | 1 +
> arch/arm/boards/usb-a926x/init.c | 1 +
> 8 files changed, 9 insertions(+)
>
> diff --git a/arch/arm/boards/animeo_ip/init.c
> b/arch/arm/boards/animeo_ip/init.c
> index ca64d6d..495dc18 100644
> --- a/arch/arm/boards/animeo_ip/init.c
> +++ b/arch/arm/boards/animeo_ip/init.c
> @@ -93,6 +93,7 @@ static struct atmel_nand_data nand_pdata = {
> .det_pin= -EINVAL,
> .rdy_pin= AT91_PIN_PC13,
> .enable_pin = AT91_PIN_PC14,
> + .ecc_mode = NAND_ECC_SOFT,
> .bus_width_16 = 0,
> .on_flash_bbt = 1,
> };
> diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c
> index 09d7f80..63f4f19 100644
> --- a/arch/arm/boards/pm9261/init.c
> +++ b/arch/arm/boards/pm9261/init.c
> @@ -50,6 +50,7 @@ static struct atmel_nand_data nand_pdata = {
> .det_pin= -EINVAL,
> .rdy_pin= AT91_PIN_PA16,
> .enable_pin = AT91_PIN_PC14,
> + .ecc_mode = NAND_ECC_SOFT,
> #if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
> .bus_width_16 = 1,
> #else
> diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c
> index 3dca9e4..2b6b089 100644
> --- a/arch/arm/boards/pm9263/init.c
> +++ b/arch/arm/boards/pm9263/init.c
> @@ -50,6 +50,7 @@ static struct atmel_nand_data nand_pdata = {
> .det_pin= -EINVAL,
> .rdy_pin= AT91_PIN_PB30,
> .enable_pin = AT91_PIN_PD15,
> + .ecc_mode = NAND_ECC_SOFT,
> #if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
> .bus_width_16 = 1,
> #else
> diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c
> index 1e43be5..524fe53 100644
> --- a/arch/arm/boards/pm9g45/init.c
> +++ b/arch/arm/boards/pm9g45/init.c
> @@ -49,6 +49,7 @@ static struct atmel_nand_data nand_pdata = {
> .det_pin= -EINVAL,
> .rdy_pin= AT91_PIN_PD3,
> .enable_pin = AT91_PIN_PC14,
> + .ecc_mode = NAND_ECC_SOFT,
> .bus_width_16 = 0,
> .on_flash_bbt = 1,
> };
> diff --git a/arch/arm/boards/qil-a926x/init.c
> b/arch/arm/boards/qil-a926x/init.c
> index 99a9604..4f01e2d 100644
> --- a/arch/arm/boards/qil-a926x/init.c
> +++ b/arch/arm/boards/qil-a926x/init.c
> @@ -43,6 +43,7 @@ static struct atmel_nand_data nand_pdata = {
> .det_pin= -EINVAL,
> .rdy_pin= AT91_PIN_PC13,
> .enable_pin = AT91_PIN_PC14,
> + .ecc_mode = NAND_ECC_SOFT,
> .on_flash_bbt = 1,
> };
>
> diff --git a/arch/arm/boards/telit-evk-pro3/init.c
> b/arch/arm/boards/telit-evk-pro3/init.c
> index e094ea7..ea63b1a 100644
> --- a/arch/arm/boards/telit-evk-pro3/init.c
> +++ b/arch/arm/boards/telit-evk-pro3/init.c
> @@ -18,6 +18,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -33,6 +34,7 @@ static struct atmel_nand_data nand_pdata = {
> .det_pin= -EINVAL,
> .rdy_pin= AT91_PIN_PC13,
> .enable_pin = AT91_PIN_PC14,
> + .ecc_mode = NAND_ECC_SOFT,
> .on_flash_bbt = 1,
> };
>
> diff --git a/arch/arm/boards/tny-a926x/init.c
> b/arch/arm/boards/tny-a926x/init.c
> index ac86457..256f8ba 100644
> --- a/arch/arm/boards/tny-a926x/init.c
> +++ b/arch/arm/boards/tny-a926x/init.c
> @@ -55,6 +55,7 @@ static struct atmel_nand_data nand_pdata = {
> .det_pin= -EINVAL,
> .rdy_pin= AT91_PIN_PC13,
> .enable_pin = AT91_PIN_PC14,
> + .ecc_mode = NAND_ECC_SOFT,
> .on_flash_bbt = 1,
> };
>
> diff --git a/arch/arm/boards/usb-a926x/init.c
> b/arch/arm/boards/usb-a926x/init.c
> index 4a28af0..f0e1157 100644
> --- a/arch/arm/boards/usb-a926x/init.c
> +++ b/arch/arm/boards/usb-a926x/init.c
> @@ -59,6 +59,7 @@ static struct atmel_nand_data nand_pdata =
[PATCH] of: fdt: fix typo in header
Signed-off-by: Raphaël Poggi --- drivers/of/fdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c index 8e4c775..cfe1833 100644 --- a/drivers/of/fdt.c +++ b/drivers/of/fdt.c @@ -1,5 +1,5 @@ /* - * dtb.c - flat devicetree functions + * fdt.c - flat devicetree functions * * Copyright (c) 2013 Sascha Hauer , Pengutronix * -- 2.1.0 ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH] i2c: at91: add support of device tree
Signed-off-by: Raphaël Poggi
---
drivers/i2c/busses/i2c-at91.c | 41 ++---
1 file changed, 34 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 9490822..a2236ed 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -376,18 +376,44 @@ static struct platform_device_id at91_twi_devtypes[] = {
}
};
+static struct of_device_id at91_twi_dt_ids[] = {
+ {
+ .compatible = "atmel,at91rm9200-i2c",
+ .data = (unsigned long) &at91rm9200_config,
+ } , {
+ .compatible = "atmel,at91sam9260-i2c",
+ .data = (unsigned long) &at91sam9260_config,
+ } , {
+ .compatible = "atmel,at91sam9261-i2c",
+ .data = (unsigned long) &at91sam9261_config,
+ } , {
+ .compatible = "atmel,at91sam9g20-i2c",
+ .data = (unsigned long) &at91sam9g20_config,
+ } , {
+ .compatible = "atmel,at91sam9g10-i2c",
+ .data = (unsigned long) &at91sam9g10_config,
+ }, {
+ .compatible = "atmel,at91sam9x5-i2c",
+ .data = (unsigned long) &at91sam9x5_config,
+ }, {
+ /* sentinel */
+ }
+};
+
static int at91_twi_probe(struct device_d *dev)
{
struct at91_twi_dev *i2c_at91;
struct at91_twi_pdata *i2c_data;
- int rc;
+ int rc = 0;
u32 bus_clk_rate;
i2c_at91 = xzalloc(sizeof(struct at91_twi_dev));
rc = dev_get_drvdata(dev, (unsigned long *)&i2c_data);
- if (rc)
+ if (rc < 0) {
+ dev_err(dev, "failed to retrieve driver data\n");
goto out_free;
+ }
i2c_at91->pdata = i2c_data;
@@ -398,7 +424,7 @@ static int at91_twi_probe(struct device_d *dev)
goto out_free;
}
- i2c_at91->clk = clk_get(dev, "twi_clk");
+ i2c_at91->clk = clk_get(dev, NULL);
if (IS_ERR(i2c_at91->clk)) {
dev_err(dev, "no clock defined\n");
rc = -ENODEV;
@@ -427,17 +453,18 @@ static int at91_twi_probe(struct device_d *dev)
return 0;
out_adap_fail:
-clk_disable(i2c_at91->clk);
-clk_put(i2c_at91->clk);
+ clk_disable(i2c_at91->clk);
+ clk_put(i2c_at91->clk);
out_free:
-kfree(i2c_at91);
-return rc;
+ kfree(i2c_at91);
+ return rc;
}
static struct driver_d at91_twi_driver = {
.name = "at91-twi",
.probe = at91_twi_probe,
.id_table = at91_twi_devtypes,
+ .of_compatible = DRV_OF_COMPAT(at91_twi_dt_ids),
};
device_platform_driver(at91_twi_driver);
--
2.1.0
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[PATCH] I2C: at91: fix the method for interrupt
From: Bo Shen
As the i2c-at91 driver won't work in the interrupt mode,
so need to poll the interrupts.
Signed-off-by: Bo Shen
---
drivers/i2c/busses/i2c-at91.c | 38 +++---
1 file changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index a2236ed..deb4ea4 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -174,24 +174,32 @@ static void at91_twi_read_next_byte(struct at91_twi_dev
*dev)
static int at91_twi_wait_completion(struct at91_twi_dev *dev)
{
uint64_t start = get_time_ns();
- unsigned int status = at91_twi_read(dev, AT91_TWI_SR);
- unsigned int irqstatus = at91_twi_read(dev, AT91_TWI_IMR);
+ unsigned int status;
+ unsigned int irqstatus;
+
+ do {
+ status = at91_twi_read(dev, AT91_TWI_SR);
+ irqstatus = at91_twi_read(dev, AT91_TWI_IMR);
+
+ if (!(status & irqstatus)) {
+ if (is_timeout(start, AT91_I2C_TIMEOUT)) {
+ dev_warn(&dev->adapter.dev, "timeout waiting
for bus ready\n");
+ return -ETIMEDOUT;
+ } else {
+ continue;
+ }
+ }
- if (irqstatus & AT91_TWI_RXRDY)
- at91_twi_read_next_byte(dev);
- else if (irqstatus & AT91_TWI_TXRDY)
- at91_twi_write_next_byte(dev);
- else
- dev_warn(&dev->adapter.dev, "neither rx and tx are ready\n");
+ if (irqstatus & AT91_TWI_RXRDY)
+ at91_twi_read_next_byte(dev);
+ else if (irqstatus & AT91_TWI_TXRDY)
+ at91_twi_write_next_byte(dev);
+ else
+ dev_warn(&dev->adapter.dev, "neither rx and tx are
ready\n");
- dev->transfer_status |= status;
+ dev->transfer_status |= status;
- while (!(at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_TXCOMP)) {
- if (is_timeout(start, AT91_I2C_TIMEOUT)) {
- dev_warn(&dev->adapter.dev, "timeout waiting for bus
ready\n");
- return -ETIMEDOUT;
- }
- }
+ } while (!(at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_TXCOMP));
at91_disable_twi_interrupts(dev);
--
2.1.0
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[PATCH] i2c: at91: add at91sam9x5 config
Signed-off-by: Raphaël Poggi
---
drivers/i2c/busses/i2c-at91.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 2ce3fa3..9490822 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -346,23 +346,32 @@ static struct at91_twi_pdata at91sam9g10_config = {
.has_unre_flag = false,
};
+static struct at91_twi_pdata at91sam9x5_config = {
+ .clk_max_div = 7,
+ .clk_offset = 4,
+ .has_unre_flag = false,
+};
+
static struct platform_device_id at91_twi_devtypes[] = {
{
- .name = "i2c-at91rm9200",
+ .name = "at91rm9200-i2c",
.driver_data = (unsigned long) &at91rm9200_config,
}, {
- .name = "i2c-at91sam9261",
+ .name = "at91sam9261-i2c",
.driver_data = (unsigned long) &at91sam9261_config,
}, {
- .name = "i2c-at91sam9260",
+ .name = "at91sam9260-i2c",
.driver_data = (unsigned long) &at91sam9260_config,
}, {
- .name = "i2c-at91sam9g20",
+ .name = "at91sam9g20-i2c",
.driver_data = (unsigned long) &at91sam9g20_config,
}, {
- .name = "i2c-at91sam9g10",
+ .name = "at91sam9g10-i2c",
.driver_data = (unsigned long) &at91sam9g10_config,
}, {
+ .name = "at91sam9x5-i2c",
+ .driver_data = (unsigned long) &at91sam9x5_config,
+ }, {
/* sentinel */
}
};
--
2.1.0
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[PATCH] i2c: at91: fix coding style issue
Signed-off-by: Raphaël Poggi
---
drivers/i2c/busses/i2c-at91.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 399f6a9..2ce3fa3 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -186,8 +186,8 @@ static int at91_twi_wait_completion(struct at91_twi_dev
*dev)
dev->transfer_status |= status;
- while(!(at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_TXCOMP)) {
- if(is_timeout(start, AT91_I2C_TIMEOUT)) {
+ while (!(at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_TXCOMP)) {
+ if (is_timeout(start, AT91_I2C_TIMEOUT)) {
dev_warn(&dev->adapter.dev, "timeout waiting for bus
ready\n");
return -ETIMEDOUT;
}
--
2.1.0
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Re: [PATCH 8/9] ARM: at91: add sama5d4 soc support #2
_PA26, 0);/* LCDVSYNC */
> + at91_set_A_periph(AT91_PIN_PA27, 0);/* LCDHSYNC */
> + at91_set_A_periph(AT91_PIN_PA28, 0);/* LCDDOTCK */
> + at91_set_A_periph(AT91_PIN_PA29, 0);/* LCDDEN */
> +
> + at91_set_A_periph(AT91_PIN_PA2, 0); /* LCDD2 */
> + at91_set_A_periph(AT91_PIN_PA3, 0); /* LCDD3 */
> + at91_set_A_periph(AT91_PIN_PA4, 0); /* LCDD4 */
> + at91_set_A_periph(AT91_PIN_PA5, 0); /* LCDD5 */
> + at91_set_A_periph(AT91_PIN_PA6, 0); /* LCDD6 */
> + at91_set_A_periph(AT91_PIN_PA7, 0); /* LCDD7 */
> +
> + at91_set_A_periph(AT91_PIN_PA10, 0);/* LCDD10 */
> + at91_set_A_periph(AT91_PIN_PA11, 0);/* LCDD11 */
> + at91_set_A_periph(AT91_PIN_PA12, 0);/* LCDD12 */
> + at91_set_A_periph(AT91_PIN_PA13, 0);/* LCDD13 */
> + at91_set_A_periph(AT91_PIN_PA14, 0);/* LCDD14 */
> + at91_set_A_periph(AT91_PIN_PA15, 0);/* LCDD15 */
> +
> + at91_set_A_periph(AT91_PIN_PA18, 0);/* LCDD18 */
> + at91_set_A_periph(AT91_PIN_PA19, 0);/* LCDD19 */
> + at91_set_A_periph(AT91_PIN_PA20, 0);/* LCDD20 */
> + at91_set_A_periph(AT91_PIN_PA21, 0);/* LCDD21 */
> + at91_set_A_periph(AT91_PIN_PA22, 0);/* LCDD22 */
> + at91_set_A_periph(AT91_PIN_PA23, 0);/* LCDD23 */
> +
> + add_generic_device("atmel_hlcdfb", DEVICE_ID_SINGLE, NULL,
> +SAMA5D4_BASE_LCDC, SZ_4K, IORESOURCE_MEM, data);
> +}
> +#else
> +void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data) {}
> +#endif
> +
> +/*
> + * UART
> + * */
> +#if defined(CONFIG_DRIVER_SERIAL_ATMEL)
> +resource_size_t __init at91_configure_dbgu(void)
> +{
> + at91_set_A_periph(AT91_PIN_PB25, 1);/* TXD1 */
> + at91_set_A_periph(AT91_PIN_PB24, 0);/* RXD1 */
> +
> + return SAMA5D4_BASE_DBGU;
> +}
> +
> +resource_size_t __init at91_configure_usart0(unsigned pins)
> +{
> + at91_set_A_periph(AT91_PIN_PD13, 1);/* TXD1 */
> + at91_set_A_periph(AT91_PIN_PD12, 0);/* RXD1 */
> +
> + return SAMA5D4_BASE_USART0;
> +}
> +
> +resource_size_t __init at91_configure_usart1(unsigned pins)
> +{
> + at91_set_A_periph(AT91_PIN_PD17, 1);/* TXD1 */
> + at91_set_A_periph(AT91_PIN_PD16, 0);/* RXD1 */
> +
> + return SAMA5D4_BASE_USART1;
> +}
> +
> +
> +resource_size_t __init at91_configure_usart2(unsigned pins)
> +{
> + at91_set_B_periph(AT91_PIN_PB5, 1); /* TXD1 */
> + at91_set_B_periph(AT91_PIN_PB4, 0); /* RXD1 */
> +
> + return SAMA5D4_BASE_USART2;
> +}
> +
> +resource_size_t __init at91_configure_usart3(unsigned pins)
> +{
> + at91_set_B_periph(AT91_PIN_PE17, 1);/* TXD1 */
> + at91_set_B_periph(AT91_PIN_PE16, 0);/* RXD1 */
> +
> + return SAMA5D4_BASE_USART3;
> +}
> +
> +resource_size_t __init at91_configure_usart4(unsigned pins)
> +{
> + at91_set_B_periph(AT91_PIN_PE27, 1);/* TXD1 */
> + at91_set_B_periph(AT91_PIN_PE26, 0);/* RXD1 */
> +
> + return SAMA5D4_BASE_USART4;
> +}
> +
> +resource_size_t __init at91_configure_usart5(unsigned pins)
> +{
> + at91_set_B_periph(AT91_PIN_PE30, 1);/* TXD1 */
> + at91_set_B_periph(AT91_PIN_PE29, 0);/* RXD1 */
> +
> + return SAMA5D4_BASE_UART0;
> +}
> +
> +resource_size_t __init at91_configure_usart6(unsigned pins)
> +{
> + at91_set_C_periph(AT91_PIN_PC26, 1);/* TXD1 */
> + at91_set_C_periph(AT91_PIN_PC25, 0);/* RXD1 */
> +
> + return SAMA5D4_BASE_UART1;
> +}
> +#endif
> --
> 2.1.0.24.g4109c28
>
>
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Thanks,
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[PATCH] i2c: at91: add support of device tree
Signed-off-by: Raphaël Poggi
---
drivers/i2c/busses/i2c-at91.c | 91 ++-
1 file changed, 73 insertions(+), 18 deletions(-)
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 399f6a9..6494401 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -186,8 +186,8 @@ static int at91_twi_wait_completion(struct at91_twi_dev
*dev)
dev->transfer_status |= status;
- while(!(at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_TXCOMP)) {
- if(is_timeout(start, AT91_I2C_TIMEOUT)) {
+ while (!(at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_TXCOMP)) {
+ if (is_timeout(start, AT91_I2C_TIMEOUT)) {
dev_warn(&dev->adapter.dev, "timeout waiting for bus
ready\n");
return -ETIMEDOUT;
}
@@ -346,41 +346,95 @@ static struct at91_twi_pdata at91sam9g10_config = {
.has_unre_flag = false,
};
+static struct at91_twi_pdata at91sam9x5_config = {
+ .clk_max_div = 7,
+ .clk_offset = 4,
+ .has_unre_flag = false,
+};
+
static struct platform_device_id at91_twi_devtypes[] = {
{
- .name = "i2c-at91rm9200",
+ .name = "at91rm9200-i2c",
.driver_data = (unsigned long) &at91rm9200_config,
}, {
- .name = "i2c-at91sam9261",
+ .name = "at91sam9261-i2c",
.driver_data = (unsigned long) &at91sam9261_config,
}, {
- .name = "i2c-at91sam9260",
+ .name = "at91sam9260-i2c",
.driver_data = (unsigned long) &at91sam9260_config,
}, {
- .name = "i2c-at91sam9g20",
+ .name = "at91sam9g20-i2c",
.driver_data = (unsigned long) &at91sam9g20_config,
}, {
- .name = "i2c-at91sam9g10",
+ .name = "at91sam9g10-i2c",
.driver_data = (unsigned long) &at91sam9g10_config,
}, {
+ .name = "at91sam9x5-i2c",
+ .driver_data = (unsigned long) &at91sam9x5_config,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct of_device_id at91_twi_dt_ids[] = {
+ {
+ .compatible = "atmel,at91rm9200-i2c",
+ .data = (unsigned long) &at91rm9200_config,
+ } , {
+ .compatible = "atmel,at91sam9260-i2c",
+ .data = (unsigned long) &at91sam9260_config,
+ } , {
+ .compatible = "atmel,at91sam9261-i2c",
+ .data = (unsigned long) &at91sam9261_config,
+ } , {
+ .compatible = "atmel,at91sam9g20-i2c",
+ .data = (unsigned long) &at91sam9g20_config,
+ } , {
+ .compatible = "atmel,at91sam9g10-i2c",
+ .data = (unsigned long) &at91sam9g10_config,
+ }, {
+ .compatible = "atmel,at91sam9x5-i2c",
+ .data = (unsigned long) &at91sam9x5_config,
+ }, {
/* sentinel */
}
};
+static struct at91_twi_pdata *at91_twi_get_driver_data(struct device_d *dev)
+{
+ struct at91_twi_pdata *i2c_data = NULL;
+ int rc;
+
+ if (dev->device_node) {
+ const struct of_device_id *match;
+ match = of_match_node(at91_twi_dt_ids, dev->device_node);
+ if (!match)
+ i2c_data = NULL;
+ else
+ i2c_data = (struct at91_twi_pdata *)match->data;
+ } else {
+ rc = dev_get_drvdata(dev, (unsigned long *)&i2c_data);
+ if (rc)
+ i2c_data = NULL;
+ }
+
+ return i2c_data;
+}
+
static int at91_twi_probe(struct device_d *dev)
{
struct at91_twi_dev *i2c_at91;
- struct at91_twi_pdata *i2c_data;
- int rc;
+ int rc = 0;
u32 bus_clk_rate;
i2c_at91 = xzalloc(sizeof(struct at91_twi_dev));
- rc = dev_get_drvdata(dev, (unsigned long *)&i2c_data);
- if (rc)
+ i2c_at91->pdata = at91_twi_get_driver_data(dev);
+ if (!i2c_at91->pdata) {
+ dev_err(dev, "failed to retrieve driver data\n");
+ rc = -ENODEV;
goto out_free;
-
- i2c_at91->pdata = i2c_data;
+ }
i2c_at91->base = dev_request_mem_region(dev, 0);
if (!i2c_at91->base) {
@@ -389,7 +443,7 @@ static int at91_twi_probe(struct device_d *dev)
goto out_free;
}
- i2c_at91->clk = clk_get(dev, "twi_clk");
+ i2c_at91->clk = clk_get(dev, NULL);
if (IS_ERR(i2c_at91->clk)) {
dev_
[PATCH] I2C: at91: fix the method for interrupt
From: Bo Shen
As the i2c-at91 driver won't work in the interrupt mode,
so need to poll the interrupts.
Signed-off-by: Bo Shen
---
drivers/i2c/busses/i2c-at91.c | 38 +++---
1 file changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 6494401..d9224de 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -174,24 +174,32 @@ static void at91_twi_read_next_byte(struct at91_twi_dev
*dev)
static int at91_twi_wait_completion(struct at91_twi_dev *dev)
{
uint64_t start = get_time_ns();
- unsigned int status = at91_twi_read(dev, AT91_TWI_SR);
- unsigned int irqstatus = at91_twi_read(dev, AT91_TWI_IMR);
+ unsigned int status;
+ unsigned int irqstatus;
+
+ do {
+ status = at91_twi_read(dev, AT91_TWI_SR);
+ irqstatus = at91_twi_read(dev, AT91_TWI_IMR);
+
+ if (!(status & irqstatus)) {
+ if (is_timeout(start, AT91_I2C_TIMEOUT)) {
+ dev_warn(&dev->adapter.dev, "timeout waiting
for bus ready\n");
+ return -ETIMEDOUT;
+ } else {
+ continue;
+ }
+ }
- if (irqstatus & AT91_TWI_RXRDY)
- at91_twi_read_next_byte(dev);
- else if (irqstatus & AT91_TWI_TXRDY)
- at91_twi_write_next_byte(dev);
- else
- dev_warn(&dev->adapter.dev, "neither rx and tx are ready\n");
+ if (irqstatus & AT91_TWI_RXRDY)
+ at91_twi_read_next_byte(dev);
+ else if (irqstatus & AT91_TWI_TXRDY)
+ at91_twi_write_next_byte(dev);
+ else
+ dev_warn(&dev->adapter.dev, "neither rx and tx are
ready\n");
- dev->transfer_status |= status;
+ dev->transfer_status |= status;
- while (!(at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_TXCOMP)) {
- if (is_timeout(start, AT91_I2C_TIMEOUT)) {
- dev_warn(&dev->adapter.dev, "timeout waiting for bus
ready\n");
- return -ETIMEDOUT;
- }
- }
+ } while (!(at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_TXCOMP));
at91_disable_twi_interrupts(dev);
--
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Re: AT91 pinctrl/gpio fixes
I am only able to test with the at91sam9m10g45ek board, and the compile + pinctrl/gpio are working well, in device tree and non device tree case. I just needed to add my v2 patch for the gpio clocks registration. I'm sorry to have broken the build of the others Atmel boards. Next time I will take care of that. Thanks, Raphaël 2014-09-09 10:19 GMT+02:00 Sascha Hauer : > On Mon, Sep 08, 2014 at 03:36:16PM +0200, Raphaël Poggi wrote: >> Hello, I just send patchs, to fix all this issues. > > Not really all, there are still some compile errors in a board you > don't compile test. As a result I applied a mixture of our patches > to master: > > 5a5ba5a ARM: AT91: Make gpio mux functions inline > a918dbf ARM: AT91: Add missing include > 5dc6c89 pinctrl: at91: retrieve device id in non dtb probe > 9c885a2 pinctrl: at91: fix the pin_to_controller function > 9732308 pinctrl: at91: add driver data > > It now builds fine. Could you do some runtime tests to see if it > also works? > > Sascha > > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v2] pinctrl: at91: add driver data
This commit adds the driver data for the gpio-at91 driver.
Signed-off-by: Raphaël Poggi
---
drivers/pinctrl/pinctrl-at91.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index d3423d0..3c6b38c 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -606,8 +606,10 @@ static struct gpio_ops at91_gpio_ops = {
static struct of_device_id at91_gpio_dt_ids[] = {
{
.compatible = "atmel,at91rm9200-gpio",
+ .data = (unsigned long)&at91rm9200_ops,
}, {
.compatible = "atmel,at91sam9x5-gpio",
+ .data = (unsigned long)&at91sam9x5_ops,
}, {
/* sentinel */
},
@@ -629,6 +631,12 @@ static int at91_gpio_probe(struct device_d *dev)
at91_gpio = &gpio_chip[alias_idx];
+ ret = dev_get_drvdata(dev, (unsigned long *)&at91_gpio->ops);
+ if (ret) {
+ dev_err(dev, "dev_get_drvdata failed: %d\n", ret);
+ return ret;
+ }
+
clk = clk_get(dev, NULL);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
@@ -667,8 +675,10 @@ static int at91_gpio_probe(struct device_d *dev)
static struct platform_device_id at91_gpio_ids[] = {
{
.name = "at91rm9200-gpio",
+ .driver_data = (unsigned long)&at91rm9200_ops,
}, {
.name = "at91sam9x5-gpio",
+ .driver_data = (unsigned long)&at91sam9x5_ops,
}, {
/* sentinel */
},
--
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[PATCH v2] mach-at91: declare device tree clock
This commit use the clkdev_add_physbase function, to declare device tree and
non device tree gpio clocks.
Signed-off-by: Raphaël Poggi
---
arch/arm/mach-at91/at91sam9g45.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 9a50deb..584ef9d 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -192,11 +192,6 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
- CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk),
- CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk),
- CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
- CLKDEV_DEV_ID("at91rm9200-gpio3", &pioDE_clk),
- CLKDEV_DEV_ID("at91rm9200-gpio4", &pioDE_clk),
CLKDEV_DEV_ID("at91-pit", &mck),
CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk),
};
@@ -238,6 +233,14 @@ static void __init at91sam9g45_register_clocks(void)
clkdev_add_table(usart_clocks_lookups,
ARRAY_SIZE(usart_clocks_lookups));
+ clkdev_add_physbase(&twi0_clk, 0xfff84000, NULL);
+ clkdev_add_physbase(&twi1_clk, 0xfff88000, NULL);
+ clkdev_add_physbase(&pioA_clk, 0xf200, NULL);
+ clkdev_add_physbase(&pioB_clk, 0xf400, NULL);
+ clkdev_add_physbase(&pioC_clk, 0xf600, NULL);
+ clkdev_add_physbase(&pioDE_clk, 0xf800, NULL);
+ clkdev_add_physbase(&pioDE_clk, 0xfa00, NULL);
+
if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
clk_register(&vdec_clk);
--
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Re: AT91 pinctrl/gpio fixes
Hello, I just send patchs, to fix all this issues. 2014-09-08 15:23 GMT+02:00 Sascha Hauer : > Unfortunately the transition to pinctrl for AT91 caused some damage. > The 926x do not compile anymore. Even when this is fixed the boards > won't work since the new pinctrl driver uses of_alias_get_id() even > for the platform case to translate the device into a gpio chip. > > Sascha > > > Sascha Hauer (4): > ARM: AT91: Add missing include > ARM: AT91: Make gpio mux functions inline > pinctrl: AT91: Only use of_alias_get_id when probed from devicetree > pinctrl: AT91: use alias_idx to calculate the base gpio number > > arch/arm/mach-at91/at91sam926x_lowlevel_init.c | 2 +- > arch/arm/mach-at91/include/mach/gpio.h | 42 > -- > drivers/pinctrl/pinctrl-at91.c | 9 -- > 3 files changed, 27 insertions(+), 26 deletions(-) > > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH] mach-at91: declare device tree clock
This commit use the clkdev_add_physbase function, to declare device tree and
non device tree gpio clocks.
Signed-off-by: Raphaël Poggi
---
arch/arm/mach-at91/at91sam9g45.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 9a50deb..f8d069f 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -192,11 +192,6 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
- CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk),
- CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk),
- CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
- CLKDEV_DEV_ID("at91rm9200-gpio3", &pioDE_clk),
- CLKDEV_DEV_ID("at91rm9200-gpio4", &pioDE_clk),
CLKDEV_DEV_ID("at91-pit", &mck),
CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk),
};
@@ -238,6 +233,14 @@ static void __init at91sam9g45_register_clocks(void)
clkdev_add_table(usart_clocks_lookups,
ARRAY_SIZE(usart_clocks_lookups));
+ clkdev_add_physbase(&twi0_clk, 0xfff84000, NULL);
+ clkdev_add_physbase(&twi1_clk, 0xfff88000, NULL);
+clkdev_add_physbase(&pioA_clk, 0xf200, NULL);
+clkdev_add_physbase(&pioB_clk, 0xf400, NULL);
+clkdev_add_physbase(&pioC_clk, 0xf600, NULL);
+clkdev_add_physbase(&pioDE_clk, 0xf800, NULL);
+clkdev_add_physbase(&pioDE_clk, 0xfa00, NULL);
+
if (cpu_is_at91sam9m10() || cpu_is_at91sam9m11())
clk_register(&vdec_clk);
--
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[PATCH] pinctrl: at91: add driver data
This commit adds the driver data for the gpio-at91 driver.
Signed-off-by: Raphaël Poggi
---
drivers/pinctrl/pinctrl-at91.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index d3423d0..29e54cf 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -606,8 +606,10 @@ static struct gpio_ops at91_gpio_ops = {
static struct of_device_id at91_gpio_dt_ids[] = {
{
.compatible = "atmel,at91rm9200-gpio",
+.data = (unsigned long)&at91rm9200_ops,
}, {
.compatible = "atmel,at91sam9x5-gpio",
+ .data = (unsigned long)&at91sam9x5_ops,
}, {
/* sentinel */
},
@@ -629,6 +631,12 @@ static int at91_gpio_probe(struct device_d *dev)
at91_gpio = &gpio_chip[alias_idx];
+ ret = dev_get_drvdata(dev, (unsigned long *)&at91_gpio->ops);
+if (ret) {
+dev_err(dev, "dev_get_drvdata failed: %d\n", ret);
+return ret;
+}
+
clk = clk_get(dev, NULL);
if (IS_ERR(clk)) {
ret = PTR_ERR(clk);
@@ -667,8 +675,10 @@ static int at91_gpio_probe(struct device_d *dev)
static struct platform_device_id at91_gpio_ids[] = {
{
.name = "at91rm9200-gpio",
+.driver_data = (unsigned long)&at91rm9200_ops,
}, {
.name = "at91sam9x5-gpio",
+ .driver_data = (unsigned long)&at91sam9x5_ops,
}, {
/* sentinel */
},
--
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[PATCH] pinctrl: at91: fix the pin_to_controller function
Other functions use pin_to_controller to retrieve a at91_gpio_chip structure,
so fix pin_to_controller to return the correct value.
Signed-off-by: Raphaël Poggi
---
drivers/pinctrl/pinctrl-at91.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index e212f7a..3dc81c7 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -71,11 +71,11 @@ static int gpio_banks;
static struct at91_gpio_chip gpio_chip[MAX_GPIO_BANKS];
-static inline void __iomem *pin_to_controller(unsigned pin)
+static inline struct at91_gpio_chip *pin_to_controller(unsigned pin)
{
pin /= MAX_NB_GPIO_PER_BANK;
if (likely(pin < gpio_banks))
- return gpio_chip[pin].regbase;
+ return &gpio_chip[pin];
return NULL;
}
--
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[PATCH] pinctrl: at91: retrieve device id in non dtb probe
We need to retrieve the device id in device tree/non device tree case.
Signed-off-by: Raphaël Poggi
---
drivers/pinctrl/pinctrl-at91.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 3dc81c7..d3423d0 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -618,9 +618,14 @@ static int at91_gpio_probe(struct device_d *dev)
struct at91_gpio_chip *at91_gpio;
struct clk *clk;
int ret;
- int alias_idx = of_alias_get_id(dev->device_node, "gpio");
+ int alias_idx;
- BUG_ON(dev->id > MAX_GPIO_BANKS);
+ if (dev->device_node)
+ alias_idx = of_alias_get_id(dev->device_node, "gpio");
+ else
+ alias_idx = dev->id;
+
+ BUG_ON(alias_idx > MAX_GPIO_BANKS);
at91_gpio = &gpio_chip[alias_idx];
@@ -646,7 +651,7 @@ static int at91_gpio_probe(struct device_d *dev)
at91_gpio->chip.ops = &at91_gpio_ops;
at91_gpio->chip.ngpio = MAX_NB_GPIO_PER_BANK;
at91_gpio->chip.dev = dev;
- at91_gpio->chip.base = dev->id * MAX_NB_GPIO_PER_BANK;
+ at91_gpio->chip.base = alias_idx * MAX_NB_GPIO_PER_BANK;
ret = gpiochip_add(&at91_gpio->chip);
if (ret) {
--
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Re: [PATCH v3 2/3] pinctrl: at91: add pinctrl driver
Perfect thank you, so I just have to send one patch for the gpio clock registration. 2014-09-04 11:26 GMT+02:00 Sascha Hauer : > On Wed, Sep 03, 2014 at 05:10:33PM +0200, Raphaël Poggi wrote: >> This patch is perfect :-). You just miss to check the return value in >> at91_gpio_probe. >> >> Do I have to integrate this patch in mine ? or you will apply it yourself ? > > I just added the return value check, squashed the patch into your > pinctrl driver patch and applied to -next. > > Sascha > > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH v3 2/3] pinctrl: at91: add pinctrl driver
This patch is perfect :-). You just miss to check the return value in
at91_gpio_probe.
Do I have to integrate this patch in mine ? or you will apply it yourself ?
2014-09-03 15:52 GMT+02:00 Sascha Hauer :
> On Wed, Sep 03, 2014 at 01:23:14PM +0200, Raphaël Poggi wrote:
>> Sounds good, but files like at91samXXX_devices.c need gpio functions.
>> I think the problem is that the mach-at91/gpio.c file include a gpio
>> driver which not belong to be here, the right place is in the
>> driver/pinctrl (like my patch). But all files like
>> at91samXXX_devices.c are using the functions from this gpio driver.
>>
>> So I think we have to:
>>
>> 1. Rewrite mach-at91/gpio.c and populate it with basic gpio functions
>> (cf. http://lxr.free-electrons.com/source/arch/arm/mach-at91/gpio.c
>> from line 130 to 425).
>> 2. Replace in at91samXXX_devices.c files, reference of functions from
>> the gpio driver by these basic new functions.
>>
>> By this way, when AT91 code are registering the gpio subsystem, we use
>> the pinctrl/gpio driver and also we avoid duplicate code.
>>
>> Let me know if I am on the right way or not.
>
> Isn't it possible to move the functions into the pinctrl driver like
> done in the following patch? It's not that nice to call from
> architecture code directly into the driver code, but I think it should
> work. We do the same for i.MX.
>
> Sascha
>
> ---8<-
>
> From a351ae7f3815d3e555290380c70d0cb35b04e7a3 Mon Sep 17 00:00:00 2001
> From: Sascha Hauer
> Date: Wed, 3 Sep 2014 15:51:05 +0200
> Subject: [PATCH] ARM: AT91: move arch/arm/mach-at91/gpio.c functions to
> pinctrl driver
>
> Signed-off-by: Sascha Hauer
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/mach-at91/Makefile| 2 +-
> arch/arm/mach-at91/gpio.c | 670
> -
> drivers/pinctrl/Kconfig| 2 +-
> drivers/pinctrl/pinctrl-at91.c | 246 ---
> 5 files changed, 203 insertions(+), 718 deletions(-)
> delete mode 100644 arch/arm/mach-at91/gpio.c
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 9f34e10..13f0bd4 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -37,6 +37,7 @@ config ARCH_AT91
> select HAS_DEBUG_LL
> select HAVE_MACH_ARM_HEAD
> select HAVE_CLK
> + select PINCTRL_AT91
>
> config ARCH_BCM2835
> bool "Broadcom BCM2835 boards"
> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> index ab80e5f..8599f50 100644
> --- a/arch/arm/mach-at91/Makefile
> +++ b/arch/arm/mach-at91/Makefile
> @@ -1,4 +1,4 @@
> -obj-y += setup.o clock.o gpio.o irq_fixup.o
> +obj-y += setup.o clock.o irq_fixup.o
> obj-$(CONFIG_CMD_AT91_BOOT_TEST) += boot_test_cmd.o
>
> obj-$(CONFIG_AT91_BOOTSTRAP) += bootstrap.o
> diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
> deleted file mode 100644
> index 402634b..000
> --- a/arch/arm/mach-at91/gpio.c
> +++ /dev/null
> @@ -1,670 +0,0 @@
> -/*
> - * Copyright (C) 2005 HP Labs
> - * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD
>
> - *
> - * See file CREDITS for list of people who contributed to this
> - * project.
> - *
> - * This program is free software; you can redistribute it and/or
> - * modify it under the terms of the GNU General Public License as
> - * published by the Free Software Foundation; either version 2 of
> - * the License, or (at your option) any later version.
> - *
> - * This program is distributed in the hope that it will be useful,
> - * but WITHOUT ANY WARRANTY; without even the implied warranty of
> - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> - * GNU General Public License for more details.
> - *
> - */
> -
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -
> -#include
> -
> -#define MAX_GPIO_BANKS 5
> -
> -static int gpio_banks = 0;
> -
> -/*
> - * Functionnality can change with newer chips
> - */
> -struct at91_gpio_chip {
> - struct gpio_chipchip;
> - void __iomem*regbase; /* PIO bank virtual address */
> - struct at91_pinctrl_mux_ops *ops; /* ops */
> -};
> -
> -#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
> -
> -static struct at91_gpio_chip gpio_chip[MAX_GPIO_BANKS];
> -
> -static inline struct at91_gpio_chip *pin_to_controller(unsigned pin)
> -{
> -
Re: [PATCH v3 2/3] pinctrl: at91: add pinctrl driver
Sounds good, but files like at91samXXX_devices.c need gpio functions.
I think the problem is that the mach-at91/gpio.c file include a gpio
driver which not belong to be here, the right place is in the
driver/pinctrl (like my patch). But all files like
at91samXXX_devices.c are using the functions from this gpio driver.
So I think we have to:
1. Rewrite mach-at91/gpio.c and populate it with basic gpio functions
(cf. http://lxr.free-electrons.com/source/arch/arm/mach-at91/gpio.c
from line 130 to 425).
2. Replace in at91samXXX_devices.c files, reference of functions from
the gpio driver by these basic new functions.
By this way, when AT91 code are registering the gpio subsystem, we use
the pinctrl/gpio driver and also we avoid duplicate code.
Let me know if I am on the right way or not.
Raphaël
2014-09-03 8:56 GMT+02:00 Sascha Hauer :
> On Tue, Sep 02, 2014 at 01:07:59PM +0200, Raphaël Poggi wrote:
>> +static int at91_gpio_probe(struct device_d *dev)
>> +{
>> + struct at91_gpio_chip *at91_gpio;
>> + struct clk *clk;
>> + int ret;
>> + int alias_idx = of_alias_get_id(dev->device_node, "gpio");
>> +
>> + BUG_ON(dev->id > MAX_GPIO_BANKS);
>> +
>> + at91_gpio = &gpio_chip[alias_idx];
>> +
>> + clk = clk_get(dev, NULL);
>> + if (IS_ERR(clk)) {
>> + ret = PTR_ERR(clk);
>> + dev_err(dev, "clock not found: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + ret = clk_enable(clk);
>> + if (ret < 0) {
>> + dev_err(dev, "clock failed to enable: %d\n", ret);
>> + clk_put(clk);
>> + return ret;
>> + }
>> +
>> + gpio_banks = max(gpio_banks, alias_idx + 1);
>> + at91_gpio->regbase = dev_request_mem_region(dev, 0);
>
> Please check the return value.
>
> This driver duplicates the existing Atmel GPIO driver. Shouldn't the
> existing driver be dropped? If yes, you should also make sure that this
> driver is compiled unconditionally on Atmel SoCs and add a
>
> if (!IS_ENABLED(CONFIG_PINCTRL))
> return 0;
>
> to at91_pinctrl_init() to reduce the overhead when pinctrl is disabled.
>
> Sascha
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
>
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Re: [PATCH] mtd: atmel_nand: fix null pointer dereference
I think this patch could be squash in [PATCH v3 3/3] mtd: atmel_nand:
add support for device tree
2014-09-02 21:02 GMT+02:00 Raphaël Poggi :
> We need to allocate pdata for device tree and non device tree probe.
> In device tree probe we use pdata to fill structure member with dts data.
> In non device tree probe we use the pdata to handle platform_data.
>
> Signed-off-by: Raphaël Poggi
> ---
> drivers/mtd/nand/atmel_nand.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
> index 910ecc3..1e7c6c6 100644
> --- a/drivers/mtd/nand/atmel_nand.c
> +++ b/drivers/mtd/nand/atmel_nand.c
> @@ -1194,6 +1194,10 @@ static int __init atmel_nand_probe(struct device_d
> *dev)
> if (!host)
> return -ENOMEM;
>
> + pdata = kzalloc(sizeof(struct atmel_nand_data), GFP_KERNEL);
> + if (!pdata)
> + return -ENOMEM;
> +
> host->io_base = dev_request_mem_region(dev, 0);
>
> mtd = &host->mtd;
> @@ -1206,10 +1210,6 @@ static int __init atmel_nand_probe(struct device_d
> *dev)
> if (res)
> goto err_no_card;
> } else {
> - pdata = kzalloc(sizeof(struct atmel_nand_data), GFP_KERNEL);
> - if (!pdata)
> - return -ENOMEM;
> -
> memcpy(host->board, dev->platform_data, sizeof(struct
> atmel_nand_data));
> }
>
> --
> 1.8.3.2
>
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[PATCH] mtd: atmel_nand: fix null pointer dereference
We need to allocate pdata for device tree and non device tree probe.
In device tree probe we use pdata to fill structure member with dts data.
In non device tree probe we use the pdata to handle platform_data.
Signed-off-by: Raphaël Poggi
---
drivers/mtd/nand/atmel_nand.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 910ecc3..1e7c6c6 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1194,6 +1194,10 @@ static int __init atmel_nand_probe(struct device_d *dev)
if (!host)
return -ENOMEM;
+ pdata = kzalloc(sizeof(struct atmel_nand_data), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
host->io_base = dev_request_mem_region(dev, 0);
mtd = &host->mtd;
@@ -1206,10 +1210,6 @@ static int __init atmel_nand_probe(struct device_d *dev)
if (res)
goto err_no_card;
} else {
- pdata = kzalloc(sizeof(struct atmel_nand_data), GFP_KERNEL);
- if (!pdata)
- return -ENOMEM;
-
memcpy(host->board, dev->platform_data, sizeof(struct
atmel_nand_data));
}
--
1.8.3.2
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[PATCH v3 2/3] pinctrl: at91: add pinctrl driver
This driver is based on mach-at91/gpio.c and linux pinctrl driver.
The driver contains the gpio and pinctrl parts (like in linux) because the two
parts
share some structures and logics.
Signed-off-by: Raphaël Poggi
---
drivers/pinctrl/Kconfig|6 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-at91.c | 527
3 files changed, 534 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-at91.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index dffaa4e..ce55c7b 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -7,6 +7,12 @@ config PINCTRL
from the devicetree. Legacy drivers here may not need this core
support but instead provide their own SoC specific APIs
+config PINCTRL_AT91
+ select PINCTRL
+ bool
+ help
+ The pinmux controller found on AT91 SoCs.
+
config PINCTRL_IMX_IOMUX_V1
select PINCTRL if OFDEVICE
bool
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 566ba11..3ea8649 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_PINCTRL) += pinctrl.o
+obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_IMX_IOMUX_V1) += imx-iomux-v1.o
obj-$(CONFIG_PINCTRL_IMX_IOMUX_V2) += imx-iomux-v2.o
obj-$(CONFIG_PINCTRL_IMX_IOMUX_V3) += imx-iomux-v3.o
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
new file mode 100644
index 000..433862a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -0,0 +1,527 @@
+/*
+ * Copyright (C) 2005 HP Labs
+ * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD
+ * Copyright (C) 2014 Raphaël Poggi
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include
+
+struct at91_pinctrl {
+ struct pinctrl_device pctl;
+ struct at91_pinctrl_mux_ops *ops;
+};
+
+struct at91_gpio_chip {
+ struct gpio_chipchip;
+ void __iomem*regbase; /* PIO bank virtual address */
+ struct at91_pinctrl_mux_ops *ops; /* ops */
+};
+
+enum at91_mux {
+ AT91_MUX_GPIO = 0,
+ AT91_MUX_PERIPH_A = 1,
+ AT91_MUX_PERIPH_B = 2,
+ AT91_MUX_PERIPH_C = 3,
+ AT91_MUX_PERIPH_D = 4,
+};
+
+#define MAX_GPIO_BANKS 5
+#define to_at91_pinctrl(c) container_of(c, struct at91_pinctrl, pctl);
+#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
+
+#define PULL_UP (1 << 0)
+#define MULTI_DRIVE (1 << 1)
+#define DEGLITCH(1 << 2)
+#define PULL_DOWN (1 << 3)
+#define DIS_SCHMIT (1 << 4)
+#define DEBOUNCE(1 << 16)
+#define DEBOUNCE_VAL_SHIFT 17
+#define DEBOUNCE_VAL(0x3fff << DEBOUNCE_VAL_SHIFT)
+
+static int gpio_banks;
+
+static struct at91_gpio_chip gpio_chip[MAX_GPIO_BANKS];
+
+static inline void __iomem *pin_to_controller(struct at91_pinctrl *info,
unsigned pin)
+{
+ pin /= MAX_NB_GPIO_PER_BANK;
+ if (likely(pin < gpio_banks))
+ return gpio_chip[pin].regbase;
+
+ return NULL;
+}
+
+/**
+ * struct at91_pinctrl_mux_ops - describes an At91 mux ops group
+ * on new IP with support for periph C and D the way to mux in
+ * periph A and B has changed
+ * So provide the right call back
+ * if not present means the IP does not support it
+ * @get_periph: return the periph mode configured
+ * @mux_A_periph: mux as periph A
+ * @mux_B_periph: mux as periph B
+ * @mux_C_periph: mux as periph C
+ * @mux_D_periph: mux as periph D
+ * @set_deglitch: enable/disable deglitch
+ * @set_debounce: enable/disable debounce
+ * @set_pulldown: enable/disable pulldown
+ * @disable_schmitt_trig: disable schmitt trigger
+ */
+struct at91_pinctrl_mux_ops {
+ enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_A_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_B_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_C_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_D_periph)(void __iomem *pio, unsigned mask);
+ bool (*get_deglitch)(void __iomem *pio, unsigned pin);
+ void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on);
+ bool (*
[PATCH v3 1/3] arm: mach-at91: move gpio.h to include folder
This commit add functions from mach-at91/gpio.h in include/mach/gpio.h.
This allow to use these functions outside the mach-at91 folder.
Signed-off-by: Raphaël Poggi
---
arch/arm/mach-at91/gpio.c |2 +-
arch/arm/mach-at91/gpio.h | 148 ---
arch/arm/mach-at91/include/mach/gpio.h | 149
3 files changed, 150 insertions(+), 149 deletions(-)
delete mode 100644 arch/arm/mach-at91/gpio.h
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 4f2c76e..402634b 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -32,7 +32,7 @@
#include
#include
-#include "gpio.h"
+#include
#define MAX_GPIO_BANKS 5
diff --git a/arch/arm/mach-at91/gpio.h b/arch/arm/mach-at91/gpio.h
deleted file mode 100644
index d40628b..000
--- a/arch/arm/mach-at91/gpio.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD
- *
- * Under GPLv2 only
- */
-
-#ifndef __AT91_GPIO_H__
-#define __AT91_GPIO_H__
-
-#ifndef __gpio_init
-#define __gpio_init
-#endif
-
-#define MAX_NB_GPIO_PER_BANK 32
-
-static inline unsigned pin_to_bank(unsigned pin)
-{
- return pin / MAX_NB_GPIO_PER_BANK;
-}
-
-static inline unsigned pin_to_bank_offset(unsigned pin)
-{
- return pin % MAX_NB_GPIO_PER_BANK;
-}
-
-static inline unsigned pin_to_mask(unsigned pin)
-{
- return 1 << pin_to_bank_offset(pin);
-}
-
-static __gpio_init void at91_mux_disable_interrupt(void __iomem *pio, unsigned
mask)
-{
- __raw_writel(mask, pio + PIO_IDR);
-}
-
-static __gpio_init void at91_mux_set_pullup(void __iomem *pio, unsigned mask,
bool on)
-{
- __raw_writel(mask, pio + (on ? PIO_PUER : PIO_PUDR));
-}
-
-static __gpio_init void at91_mux_set_multidrive(void __iomem *pio, unsigned
mask, bool on)
-{
- __raw_writel(mask, pio + (on ? PIO_MDER : PIO_MDDR));
-}
-
-static __gpio_init void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
-{
- __raw_writel(mask, pio + PIO_ASR);
-}
-
-static __gpio_init void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
-{
- __raw_writel(mask, pio + PIO_BSR);
-}
-
-static __gpio_init void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned
mask)
-{
-
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
- pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
- pio + PIO_ABCDSR2);
-}
-
-static __gpio_init void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned
mask)
-{
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
- pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
- pio + PIO_ABCDSR2);
-}
-
-static __gpio_init void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned
mask)
-{
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
-}
-
-static __gpio_init void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned
mask)
-{
- __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
- __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
-}
-
-static __gpio_init void at91_mux_set_deglitch(void __iomem *pio, unsigned
mask, bool is_on)
-{
- __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
-}
-
-static __gpio_init void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned
mask, bool is_on)
-{
- if (is_on)
- __raw_writel(mask, pio + PIO_IFSCDR);
- at91_mux_set_deglitch(pio, mask, is_on);
-}
-
-static __gpio_init void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned
mask,
- bool is_on, u32 div)
-{
- if (is_on) {
- __raw_writel(mask, pio + PIO_IFSCER);
- __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
- __raw_writel(mask, pio + PIO_IFER);
- } else {
- __raw_writel(mask, pio + PIO_IFDR);
- }
-}
-
-static __gpio_init void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned
mask, bool is_on)
-{
- __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
-}
-
-static __gpio_init void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio,
unsigned mask)
-{
- __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
-}
-
-static __gpio_init void at91_mux_gpio_disable(void __iomem *pio, unsigned mask)
-{
- __raw_writel(mask, pio + PIO_PDR);
-}
-
-static __gpio_init void at91_mux_gpio_enable(void __iomem *pio, unsigned mask)
-{
- __raw_writel(mask, pio + PIO_PER);
-}
-
-static __gpio_init void at91_mux_gpio_input(void __iomem *pio, unsigned mask,
bool input)
-{
-
[PATCH v3 0/3] Add atmel pinctrl driver
Change since v2: * Move all functions from mach-at91/gpio.h to match-at91/include/gpio.h * Remove pinctrl-at91.h file in patch Change since v1: * Fix coding style issue * Register gpio clocks with CLKDEV_DEV_ID instead of CLKDEV_CON_DEV_ID This patchset add atmel pinctrl/gpio driver and the corresponding clocks for the at91sam9g45 device. The pinctrl driver also include the gpio driver (like in linux) because the gpio and pinctrl parts share same structures. Raphaël Poggi (3): (1) arm: mach-at91: move gpio.h to include folder (2) pinctrl: at91: add pinctrl driver (3) at91sam9g45: add device tree gpio clocks arch/arm/mach-at91/at91sam9g45.c |5 + arch/arm/mach-at91/gpio.c |2 +- arch/arm/mach-at91/gpio.h | 148 - arch/arm/mach-at91/include/mach/gpio.h | 149 + drivers/pinctrl/Kconfig|6 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/pinctrl-at91.c | 527 7 files changed, 689 insertions(+), 149 deletions(-) ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v3 3/3] at91sam9g45: add device tree gpio clocks
Signed-off-by: Raphaël Poggi
---
arch/arm/mach-at91/at91sam9g45.c |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index d19d26a..8c020fa 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -201,6 +201,11 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
CLKDEV_DEV_ID("at91rm9200-gpio3", &pioDE_clk),
CLKDEV_DEV_ID("at91rm9200-gpio4", &pioDE_clk),
+ CLKDEV_DEV_ID("f200.gpio", &pioA_clk),
+ CLKDEV_DEV_ID("f400.gpio", &pioB_clk),
+ CLKDEV_DEV_ID("f600.gpio", &pioC_clk),
+ CLKDEV_DEV_ID("f800.gpio", &pioDE_clk),
+ CLKDEV_DEV_ID("fa00.gpio", &pioDE_clk),
CLKDEV_DEV_ID("at91-pit", &mck),
CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk),
};
--
1.7.9.5
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Re: [PATCH v2 1/2] pinctrl: at91: add pinctrl driver
Hi,
I can add all the functions from mach-at91/gpio.h in
mach-at91/include/gpio.h and remove mach-at91/gpio.h. Is this a valid
solution ?
2014-09-01 12:08 GMT+02:00 Sascha Hauer :
> On Tue, Aug 05, 2014 at 01:09:16PM -0700, Raphaël Poggi wrote:
>> diff --git a/drivers/pinctrl/pinctrl-at91.h b/drivers/pinctrl/pinctrl-at91.h
>> new file mode 100644
>> index 000..e719fb8
>> --- /dev/null
>> +++ b/drivers/pinctrl/pinctrl-at91.h
>> @@ -0,0 +1,148 @@
>> +/*
>> + * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD
>>
>> + *
>> + * Under GPLv2 only
>> + */
>> +
>> +#ifndef __AT91_GPIO_H__
>> +#define __AT91_GPIO_H__
>> +
>> +#ifndef __gpio_init
>> +#define __gpio_init
>> +#endif
>> +
>> +#define MAX_NB_GPIO_PER_BANK 32
>> +
>> +static inline unsigned pin_to_bank(unsigned pin)
>> +{
>> + return pin / MAX_NB_GPIO_PER_BANK;
>> +}
>> +
>> +static inline unsigned pin_to_bank_offset(unsigned pin)
>> +{
>> + return pin % MAX_NB_GPIO_PER_BANK;
>> +}
>> +
>> +static inline unsigned pin_to_mask(unsigned pin)
>> +{
>> + return 1 << pin_to_bank_offset(pin);
>> +}
>> +
>> +static inline void at91_mux_disable_interrupt(void __iomem *pio, unsigned
>> mask)
>> +{
>> + __raw_writel(mask, pio + PIO_IDR);
>> +}
>> +
>> +static inline void at91_mux_set_pullup(void __iomem *pio, unsigned mask,
>> bool on)
>> +{
>> + __raw_writel(mask, pio + (on ? PIO_PUER : PIO_PUDR));
>> +}
>> +
>> +static inline void at91_mux_set_multidrive(void __iomem *pio, unsigned
>> mask, bool on)
>> +{
>> + __raw_writel(mask, pio + (on ? PIO_MDER : PIO_MDDR));
>> +}
>> +
>> +static inline void at91_mux_set_A_periph(void __iomem *pio, unsigned mask)
>> +{
>> + __raw_writel(mask, pio + PIO_ASR);
>> +}
>> +
>> +static inline void at91_mux_set_B_periph(void __iomem *pio, unsigned mask)
>> +{
>> + __raw_writel(mask, pio + PIO_BSR);
>> +}
>> +
>> +static inline void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned
>> mask)
>> +{
>> +
>> + __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
>> + pio + PIO_ABCDSR1);
>> + __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
>> + pio + PIO_ABCDSR2);
>> +}
>> +
>> +static inline void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned
>> mask)
>> +{
>> + __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
>> + pio + PIO_ABCDSR1);
>> + __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
>> + pio + PIO_ABCDSR2);
>> +}
>> +
>> +static inline void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned
>> mask)
>> +{
>> + __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio +
>> PIO_ABCDSR1);
>> + __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
>> +}
>> +
>> +static inline void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned
>> mask)
>> +{
>> + __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
>> + __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
>> +}
>> +
>> +static inline void at91_mux_set_deglitch(void __iomem *pio, unsigned mask,
>> bool is_on)
>> +{
>> + __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
>> +}
>> +
>> +static inline void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned
>> mask, bool is_on)
>> +{
>> + if (is_on)
>> + __raw_writel(mask, pio + PIO_IFSCDR);
>> + at91_mux_set_deglitch(pio, mask, is_on);
>> +}
>> +
>> +static inline void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned
>> mask,
>> + bool is_on, u32 div)
>> +{
>> + if (is_on) {
>> + __raw_writel(mask, pio + PIO_IFSCER);
>> + __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
>> + __raw_writel(mask, pio + PIO_IFER);
>> + } else {
>> + __raw_writel(mask, pio + PIO_IFDR);
>> + }
>> +}
>> +
>> +static inline void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned
>> mask, bool is_on)
>> +{
>> + __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
>>
[PATCH v3 2/3] mtd: atmel_nand: retrieve ecc_mode from pdata
By retrieving the ecc_mode from pdata we can use the same code for device tree
and
non device tree probing. Which was not possible before, because ecc_mode was
arbitrarily set to
NAND_ECC_SOFT.
Signed-off-by: Raphaël Poggi
---
arch/arm/boards/at91sam9260ek/init.c|1 +
arch/arm/boards/at91sam9261ek/init.c|1 +
arch/arm/boards/at91sam9263ek/init.c|1 +
arch/arm/boards/at91sam9m10g45ek/init.c |1 +
arch/arm/boards/at91sam9m10ihd/init.c |1 +
drivers/mtd/nand/atmel_nand.c |2 +-
6 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boards/at91sam9260ek/init.c
b/arch/arm/boards/at91sam9260ek/init.c
index 1298dde..76e0195 100644
--- a/arch/arm/boards/at91sam9260ek/init.c
+++ b/arch/arm/boards/at91sam9260ek/init.c
@@ -51,6 +51,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PC13,
.enable_pin = AT91_PIN_PC14,
+ .ecc_mode = NAND_ECC_SOFT,
.on_flash_bbt = 1,
};
diff --git a/arch/arm/boards/at91sam9261ek/init.c
b/arch/arm/boards/at91sam9261ek/init.c
index 9ebc16a..7b8ce98 100644
--- a/arch/arm/boards/at91sam9261ek/init.c
+++ b/arch/arm/boards/at91sam9261ek/init.c
@@ -46,6 +46,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PC15,
.enable_pin = AT91_PIN_PC14,
+ .ecc_mode = NAND_ECC_SOFT,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
.bus_width_16 = 1,
#else
diff --git a/arch/arm/boards/at91sam9263ek/init.c
b/arch/arm/boards/at91sam9263ek/init.c
index 889b4c2..c8a9d5c 100644
--- a/arch/arm/boards/at91sam9263ek/init.c
+++ b/arch/arm/boards/at91sam9263ek/init.c
@@ -43,6 +43,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PA22,
.enable_pin = AT91_PIN_PD15,
+ .ecc_mode = NAND_ECC_SOFT,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
.bus_width_16 = 1,
#else
diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c
b/arch/arm/boards/at91sam9m10g45ek/init.c
index 6503ebb..cdd7806 100644
--- a/arch/arm/boards/at91sam9m10g45ek/init.c
+++ b/arch/arm/boards/at91sam9m10g45ek/init.c
@@ -67,6 +67,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PC8,
.enable_pin = AT91_PIN_PC14,
+ .ecc_mode = NAND_ECC_SOFT,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
.bus_width_16 = 1,
#else
diff --git a/arch/arm/boards/at91sam9m10ihd/init.c
b/arch/arm/boards/at91sam9m10ihd/init.c
index fc37af4..a432e5c 100644
--- a/arch/arm/boards/at91sam9m10ihd/init.c
+++ b/arch/arm/boards/at91sam9m10ihd/init.c
@@ -44,6 +44,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PC15,
.enable_pin = AT91_PIN_PC14,
+ .ecc_mode = NAND_ECC_SOFT,
.bus_width_16 = 0,
.on_flash_bbt = 1,
};
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 220ec5c..2246602 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1157,7 +1157,7 @@ static int __init atmel_nand_probe(struct device_d *dev)
}
}
- nand_chip->ecc.mode = NAND_ECC_SOFT;
+ nand_chip->ecc.mode = pdata->ecc_mode;
if (IS_ENABLED(CONFIG_NAND_ECC_HW) &&
pdata->ecc_mode == NAND_ECC_HW) {
--
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[PATCH v3 1/3] mtd: nand: add has_pmecc member
By adding this structure member, we can retrieve the pmecc config, through the
device tree.
Signed-off-by: Raphaël Poggi
---
arch/arm/boards/at91sam9n12ek/init.c|1 +
arch/arm/boards/at91sam9x5ek/init.c |1 +
arch/arm/boards/sama5d3_xplained/init.c |1 +
arch/arm/boards/sama5d3xek/init.c |1 +
arch/arm/mach-at91/include/mach/board.h |1 +
drivers/mtd/nand/atmel_nand.c |2 +-
6 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boards/at91sam9n12ek/init.c
b/arch/arm/boards/at91sam9n12ek/init.c
index a206d6b..818a598 100644
--- a/arch/arm/boards/at91sam9n12ek/init.c
+++ b/arch/arm/boards/at91sam9n12ek/init.c
@@ -47,6 +47,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PD5,
.enable_pin = AT91_PIN_PD4,
+ .has_pmecc = 1,
.ecc_mode = NAND_ECC_HW,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 2,
diff --git a/arch/arm/boards/at91sam9x5ek/init.c
b/arch/arm/boards/at91sam9x5ek/init.c
index 62e5652..183ddc7 100644
--- a/arch/arm/boards/at91sam9x5ek/init.c
+++ b/arch/arm/boards/at91sam9x5ek/init.c
@@ -57,6 +57,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PD5,
.enable_pin = AT91_PIN_PD4,
+ .has_pmecc = 1,
.ecc_mode = NAND_ECC_HW,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 2,
diff --git a/arch/arm/boards/sama5d3_xplained/init.c
b/arch/arm/boards/sama5d3_xplained/init.c
index ae18863..b182802 100644
--- a/arch/arm/boards/sama5d3_xplained/init.c
+++ b/arch/arm/boards/sama5d3_xplained/init.c
@@ -48,6 +48,7 @@ static struct atmel_nand_data nand_pdata = {
.rdy_pin= -EINVAL,
.enable_pin = -EINVAL,
.ecc_mode = NAND_ECC_HW,
+ .has_pmecc = 1,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 4,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
diff --git a/arch/arm/boards/sama5d3xek/init.c
b/arch/arm/boards/sama5d3xek/init.c
index 743197f..49d2b37 100644
--- a/arch/arm/boards/sama5d3xek/init.c
+++ b/arch/arm/boards/sama5d3xek/init.c
@@ -63,6 +63,7 @@ static struct atmel_nand_data nand_pdata = {
.rdy_pin= -EINVAL,
.enable_pin = -EINVAL,
.ecc_mode = NAND_ECC_HW,
+ .has_pmecc = 1,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 4,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
diff --git a/arch/arm/mach-at91/include/mach/board.h
b/arch/arm/mach-at91/include/mach/board.h
index aa0fdae..e2307ed 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -63,6 +63,7 @@ struct atmel_nand_data {
u8 bus_width_16; /* buswidth is 16 bit */
u8 ecc_mode; /* NAND_ECC_* */
u8 on_flash_bbt; /* Use flash based bbt */
+ u8 has_pmecc; /* Use PMECC */
u8 bus_on_d0;
u8 pmecc_corr_cap;
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 337e225..220ec5c 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1219,7 +1219,7 @@ static int __init atmel_nand_probe(struct device_d *dev)
if (IS_ENABLED(CONFIG_NAND_ECC_HW) &&
nand_chip->ecc.mode == NAND_ECC_HW) {
- if (IS_ENABLED(CONFIG_NAND_ATMEL_PMECC))
+ if (IS_ENABLED(CONFIG_NAND_ATMEL_PMECC) && pdata->has_pmecc)
res = atmel_pmecc_nand_init_params(dev, host);
else
res = atmel_hw_nand_init_params(dev, host);
--
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[PATCH v3 3/3] mtd: atmel_nand: add support for device tree
Signed-off-by: Raphaël Poggi
---
drivers/mtd/nand/atmel_nand.c | 111 -
1 file changed, 110 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 2246602..910ecc3 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -28,6 +28,10 @@
#include
#include
+#include
+#include
+#include
+
#include
#include
@@ -1038,6 +1042,92 @@ static void atmel_nand_hwctl(struct mtd_info *mtd, int
mode)
#endif
}
+static int atmel_nand_of_init(struct atmel_nand_host *host, struct device_node
*np)
+{
+ u32 val;
+ u32 offset[2];
+ int ecc_mode;
+ struct atmel_nand_data *board = host->board;
+ enum of_gpio_flags flags = 0;
+
+ if (!IS_ENABLED(CONFIG_OFDEVICE))
+ return -ENOSYS;
+
+ if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
+ if (val >= 32) {
+ dev_err(host->dev, "invalid addr-offset %u\n", val);
+ return -EINVAL;
+ }
+ board->ale = val;
+ }
+
+ if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
+ if (val >= 32) {
+ dev_err(host->dev, "invalid cmd-offset %u\n", val);
+ return -EINVAL;
+ }
+ board->cle = val;
+ }
+
+ ecc_mode = of_get_nand_ecc_mode(np);
+
+ board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
+
+ board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
+
+ if (of_get_nand_bus_width(np) == 16)
+ board->bus_width_16 = 1;
+
+ board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
+ board->enable_pin = of_get_gpio(np, 1);
+ board->det_pin = of_get_gpio(np, 2);
+
+ board->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
+
+ if (!(board->ecc_mode == NAND_ECC_HW) || !board->has_pmecc)
+ return 0; /* Not using PMECC */
+
+ /* use PMECC, get correction capability, sector size and lookup
+ * table offset.
+ * If correction bits and sector size are not specified, then
+ * find
+ * them from NAND ONFI parameters.
+ */
+ if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
+ if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
(val != 24)) {
+ dev_err(host->dev, "Unsupported PMECC correction
capability: %d"
+ " should be 2, 4, 8, 12 or 24\n", val);
+ return -EINVAL;
+ }
+
+ board->pmecc_corr_cap = (u8)val;
+ }
+
+ if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
+ if ((val != 512) && (val != 1024)) {
+ dev_err(host->dev, "Unsupported PMECC sector
size: %d"
+ " should be 512 or 1024 bytes\n", val);
+ return -EINVAL;
+ }
+
+ board->pmecc_sector_size = (u16)val;
+ }
+
+ if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
offset, 2) != 0) {
+ dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
+ return -EINVAL;
+ }
+
+ if (!offset[0] && !offset[1]) {
+ dev_err(host->dev, "Invalid PMECC lookup table offset\n");
+ return -EINVAL;
+ }
+
+ board->pmecc_lookup_table_offset = (board->pmecc_sector_size == 512) ?
offset[0] : offset[1];
+
+ return 0;
+}
+
static int atmel_hw_nand_init_params(struct device_d *dev,
struct atmel_nand_host *host)
{
@@ -1093,7 +1183,7 @@ static int atmel_hw_nand_init_params(struct device_d *dev,
*/
static int __init atmel_nand_probe(struct device_d *dev)
{
- struct atmel_nand_data *pdata = dev->platform_data;
+ struct atmel_nand_data *pdata = NULL;
struct atmel_nand_host *host;
struct mtd_info *mtd;
struct nand_chip *nand_chip;
@@ -,6 +1201,18 @@ static int __init atmel_nand_probe(struct device_d *dev)
host->board = pdata;
host->dev = dev;
+ if (dev->device_node) {
+ res = atmel_nand_of_init(host, dev->device_node);
+ if (res)
+ goto err_no_card;
+ } else {
+ pdata = kzalloc(sizeof(struct atmel_nand_data), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ memcpy(host->board, dev->platform_data,
[PATCH v3 0/3] Add device tree support of Atmel NAND driver
Change since v2: * Combine in one patch the creation and initialisation of "has_pmecc" structure member * Combine patch "[PATCH 3/5] mtd: atmel_nand: retrieve ecc_mode from pdata" and "[PATCH 4/5] board: atmel: initialise ecc_mode" * Let NAND_ATMEL_PMECC config, but change the test in atmel_nand Change since v1: * Reorder patchs * Fix some clean style issue. This patchset adds the device tree support for the Atmel NAND driver. The first patch add the has_pmecc structure member to be able to retrieve pmecc from device tree and adds the has_pmecc on boards which need it. The second patch retrieves the ecc_mode from the plateform data, and remove this code: nand_chip->ecc.mode = NAND_ECC_SOFT; which arbitrary sets the ecc.mode to NAND_ECC_SOFT and changes the value depending of the config and plateform data. With this, we can use the same logics for device tree and non device tree probing of the driver. It also adds the ecc_mode on boards which are missing it (boards which use NAND_ECC_SOFT). The third patch adds the device tree in the atmel_nand driver. Raphaël Poggi (4): (1) mtd: nand: add has_pmecc member (2) mtd: atmel_nand: retrieve ecc_mode from pdata (3) mtd: atmel_nand: add support for device tree arch/arm/boards/at91sam9260ek/init.c|1 + arch/arm/boards/at91sam9261ek/init.c|1 + arch/arm/boards/at91sam9263ek/init.c|1 + arch/arm/boards/at91sam9m10g45ek/init.c |1 + arch/arm/boards/at91sam9m10ihd/init.c |1 + arch/arm/boards/at91sam9n12ek/init.c|1 + arch/arm/boards/at91sam9x5ek/init.c |1 + arch/arm/boards/sama5d3_xplained/init.c |1 + arch/arm/boards/sama5d3xek/init.c |1 + arch/arm/mach-at91/include/mach/board.h |1 + drivers/mtd/nand/atmel_nand.c | 115 ++- 11 files changed, 122 insertions(+), 3 deletions(-) ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v3 3/3] I2C: at91: fix the method for interrupt
From: Bo Shen
As the i2c-at91 driver won't work in the interrupt mode,
so need to poll the interrupts.
Signed-off-by: Bo Shen
---
drivers/i2c/busses/i2c-at91.c | 38 +++---
1 file changed, 23 insertions(+), 15 deletions(-)
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 651cfc7..e62f1db 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -174,24 +174,32 @@ static void at91_twi_read_next_byte(struct at91_twi_dev
*dev)
static int at91_twi_wait_completion(struct at91_twi_dev *dev)
{
uint64_t start = get_time_ns();
- unsigned int status = at91_twi_read(dev, AT91_TWI_SR);
- unsigned int irqstatus = at91_twi_read(dev, AT91_TWI_IMR);
+ unsigned int status;
+ unsigned int irqstatus;
+
+ do {
+ status = at91_twi_read(dev, AT91_TWI_SR);
+ irqstatus = at91_twi_read(dev, AT91_TWI_IMR);
+
+ if (!(status & irqstatus)) {
+ if (is_timeout(start, AT91_I2C_TIMEOUT)) {
+ dev_warn(&dev->adapter.dev, "timeout waiting
for bus ready\n");
+ return -ETIMEDOUT;
+ } else {
+ continue;
+ }
+ }
- if (irqstatus & AT91_TWI_RXRDY)
- at91_twi_read_next_byte(dev);
- else if (irqstatus & AT91_TWI_TXRDY)
- at91_twi_write_next_byte(dev);
- else
- dev_warn(&dev->adapter.dev, "neither rx and tx are ready\n");
+ if (irqstatus & AT91_TWI_RXRDY)
+ at91_twi_read_next_byte(dev);
+ else if (irqstatus & AT91_TWI_TXRDY)
+ at91_twi_write_next_byte(dev);
+ else
+ dev_warn(&dev->adapter.dev, "neither rx and tx are
ready\n");
- dev->transfer_status |= status;
+ dev->transfer_status |= status;
- while (!(at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_TXCOMP)) {
- if (is_timeout(start, AT91_I2C_TIMEOUT)) {
- dev_warn(&dev->adapter.dev, "timeout waiting for bus
ready\n");
- return -ETIMEDOUT;
- }
- }
+ } while (!(at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_TXCOMP));
at91_disable_twi_interrupts(dev);
--
1.7.9.5
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[PATCH v3 1/3] i2c: at91: add support of device tree
Signed-off-by: Raphaël Poggi
---
drivers/i2c/busses/i2c-at91.c | 92 -
1 file changed, 73 insertions(+), 19 deletions(-)
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 399f6a9..651cfc7 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -186,8 +186,8 @@ static int at91_twi_wait_completion(struct at91_twi_dev
*dev)
dev->transfer_status |= status;
- while(!(at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_TXCOMP)) {
- if(is_timeout(start, AT91_I2C_TIMEOUT)) {
+ while (!(at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_TXCOMP)) {
+ if (is_timeout(start, AT91_I2C_TIMEOUT)) {
dev_warn(&dev->adapter.dev, "timeout waiting for bus
ready\n");
return -ETIMEDOUT;
}
@@ -346,41 +346,94 @@ static struct at91_twi_pdata at91sam9g10_config = {
.has_unre_flag = false,
};
+static struct at91_twi_pdata at91sam9x5_config = {
+ .clk_max_div = 7,
+ .clk_offset = 4,
+ .has_unre_flag = false,
+};
+
static struct platform_device_id at91_twi_devtypes[] = {
{
- .name = "i2c-at91rm9200",
+ .name = "at91rm9200-i2c",
.driver_data = (unsigned long) &at91rm9200_config,
}, {
- .name = "i2c-at91sam9261",
+ .name = "at91sam9261-i2c",
.driver_data = (unsigned long) &at91sam9261_config,
}, {
- .name = "i2c-at91sam9260",
+ .name = "at91sam9260-i2c",
.driver_data = (unsigned long) &at91sam9260_config,
}, {
- .name = "i2c-at91sam9g20",
+ .name = "at91sam9g20-i2c",
.driver_data = (unsigned long) &at91sam9g20_config,
}, {
- .name = "i2c-at91sam9g10",
+ .name = "at91sam9g10-i2c",
.driver_data = (unsigned long) &at91sam9g10_config,
}, {
+ .name = "at91sam9x5-i2c",
+ .driver_data = (unsigned long) &at91sam9x5_config,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct of_device_id at91_twi_dt_ids[] = {
+ {
+ .compatible = "atmel,at91rm9200-i2c",
+ .data = (unsigned long) &at91rm9200_config,
+ } , {
+ .compatible = "atmel,at91sam9260-i2c",
+ .data = (unsigned long) &at91sam9260_config,
+ } , {
+ .compatible = "atmel,at91sam9261-i2c",
+ .data = (unsigned long) &at91sam9261_config,
+ } , {
+ .compatible = "atmel,at91sam9g20-i2c",
+ .data = (unsigned long) &at91sam9g20_config,
+ } , {
+ .compatible = "atmel,at91sam9g10-i2c",
+ .data = (unsigned long) &at91sam9g10_config,
+ }, {
+ .compatible = "atmel,at91sam9x5-i2c",
+ .data = (unsigned long) &at91sam9x5_config,
+ }, {
/* sentinel */
}
};
+static struct at91_twi_pdata *at91_twi_get_driver_data(struct device_d *dev)
+{
+ struct at91_twi_pdata *i2c_data = NULL;
+ int rc;
+
+ if (dev->device_node) {
+ const struct of_device_id *match;
+ match = of_match_node(at91_twi_dt_ids, dev->device_node);
+ if (!match)
+ i2c_data = NULL;
+ else
+ i2c_data = (struct at91_twi_pdata *)match->data;
+ } else {
+ rc = dev_get_drvdata(dev, (unsigned long *)&i2c_data);
+ if (rc)
+ i2c_data = NULL;
+ }
+
+ return i2c_data;
+}
+
static int at91_twi_probe(struct device_d *dev)
{
struct at91_twi_dev *i2c_at91;
- struct at91_twi_pdata *i2c_data;
- int rc;
+ int rc = 0;
u32 bus_clk_rate;
i2c_at91 = xzalloc(sizeof(struct at91_twi_dev));
- rc = dev_get_drvdata(dev, (unsigned long *)&i2c_data);
- if (rc)
- goto out_free;
-
- i2c_at91->pdata = i2c_data;
+ i2c_at91->pdata = at91_twi_get_driver_data(dev);
+ if (!i2c_at91->pdata) {
+ dev_err(dev, "failed to retrieve driver data\n");
+ rc = -ENODEV;
+ }
i2c_at91->base = dev_request_mem_region(dev, 0);
if (!i2c_at91->base) {
@@ -389,7 +442,7 @@ static int at91_twi_probe(struct device_d *dev)
goto out_free;
}
- i2c_at91->clk = clk_get(dev, "twi_clk");
+ i2c_at91->clk = clk_get(dev, NULL);
if (IS_ERR(i2c_at91->clk)) {
dev_
[PATCH v3 0/2] Add device tree support of i2c Atmel driver
Change since v2: * Register i2c clocks with CLKDEV_DEV_ID instead of CLKDEV_CON_DEV_ID. * Fix some coding style issue. * Add Bo Shen patch, which fix the interrupt mode. * Rename the name of ids table. (from i2c-at91sam9xxx to at91sam9xxx-i2c) Change since v1: * Squash the commit [1] which adds the sam9x5 config. This patcheset adds the device tree support for i2c Atmel driver and the corresping clocks for the at91sam9g45 device. Raphaël Poggi (2) : (1) i2c: at91: add support of device tree (2) at91sam9g45: clock: add i2c clocks Bo Shen (1): (1) I2C: at91: fix the method for interrupt arch/arm/mach-at91/at91sam9g45.c |4 ++ drivers/i2c/busses/i2c-at91.c| 126 -- 2 files changed, 98 insertions(+), 32 deletions(-) [1]: http://lists.infradead.org/pipermail/barebox/2014-August/020493.html ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v3 2/3] at91sam9g45: clock: add i2c clocks
Add the device tree and non device tree at91 i2c clocks.
Signed-off-by: Raphaël Poggi
---
arch/arm/mach-at91/at91sam9g45.c |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 9a50deb..d19d26a 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -192,6 +192,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
+ CLKDEV_DEV_ID("at91sam9g10-i2c0", &twi0_clk),
+ CLKDEV_DEV_ID("at91sam9g10-i2c1", &twi1_clk),
+ CLKDEV_DEV_ID("fff84000.i2c", &twi0_clk),
+ CLKDEV_DEV_ID("fff88000.i2c", &twi1_clk),
CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk),
CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk),
CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
--
1.7.9.5
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Re: [PATCH V2 0/2] Add device tree support of i2c Atmel driver
All right, thanks. Raphaël Poggi 2014-08-06 9:33 GMT+02:00 Bo Shen : > Hi Raphaël Poggi, > > > On 08/06/2014 03:16 PM, Raphaël Poggi wrote: >> >> Ok, about the "signed-off", do I have to let your name ? or my name + >> your name ? Sorry if my question seems stupid, but i'm new to open >> source development. > > > I think, you can first "git am" my patch, and then apply your patch and > generate the series and send it, then there won't have "signed-off" issue. > (In general, keep my "signed-off" and add your "signed-off" if you prefer). > > > Best Regards, > Bo Shen > > > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 1/5] mtd: nand: remove NAND_ATMEL_PMECC
Ok, I did it because we need a structure member to retrieve
"atmel,has-pmecc" from device tree.
Is this ok if I add the has_pmecc member (feed by atmel_nand_of_init),
let the NAND_ATMEL_PMECC, and the if will be like :
if (IS_ENABLED(CONFIG_NAND_ATMEL_PMECC) || pdata->has_pmecc)
With this we can handle device tree/non device tree probing.
Or maybe you have a better idea.
Best regards,
Raphaël Poggi
2014-08-06 6:08 GMT+02:00 Jean-Christophe PLAGNIOL-VILLARD
:
> On 11:14 Tue 05 Aug , Rapha??l Poggi wrote:
>> By removing this CONFIG_, we can use a structure member to retrieve the
>> config,
>> either through the plateform data or through the device tree. So we can
>> handle cases
>> when the driver is probed using device tree or not.
> NACK
>
> this is use to reduce barebox size
>
> keep the NAND_ATMEL_PMECC
>
> so we choose to enable it or not
>
> Best Regards,
> J.
>>
>> Signed-off-by: Raphaël Poggi
>> ---
>> arch/arm/mach-at91/include/mach/board.h |1 +
>> drivers/mtd/nand/Kconfig|8
>> drivers/mtd/nand/atmel_nand.c |2 +-
>> 3 files changed, 2 insertions(+), 9 deletions(-)
>>
>> diff --git a/arch/arm/mach-at91/include/mach/board.h
>> b/arch/arm/mach-at91/include/mach/board.h
>> index aa0fdae..e2307ed 100644
>> --- a/arch/arm/mach-at91/include/mach/board.h
>> +++ b/arch/arm/mach-at91/include/mach/board.h
>> @@ -63,6 +63,7 @@ struct atmel_nand_data {
>> u8 bus_width_16; /* buswidth is 16 bit */
>> u8 ecc_mode; /* NAND_ECC_* */
>> u8 on_flash_bbt; /* Use flash based bbt */
>> + u8 has_pmecc; /* Use PMECC */
>> u8 bus_on_d0;
>>
>> u8 pmecc_corr_cap;
>> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
>> index 04fe3c8..d49eae3 100644
>> --- a/drivers/mtd/nand/Kconfig
>> +++ b/drivers/mtd/nand/Kconfig
>> @@ -95,14 +95,6 @@ config NAND_ATMEL
>> prompt "Atmel (AT91SAM9xxx) NAND driver"
>> depends on ARCH_AT91
>>
>> -config NAND_ATMEL_PMECC
>> - bool
>> - prompt "PMECC support"
>> - depends on NAND_ATMEL
>> - select NAND_ECC_HW
>> - help
>> - Support for PMECC present on the SoC sam9x5 and sam9n12
>> -
>> config NAND_S3C24XX
>> bool
>> prompt "Samsung S3C24XX NAND driver"
>> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
>> index 337e225..3ec6450 100644
>> --- a/drivers/mtd/nand/atmel_nand.c
>> +++ b/drivers/mtd/nand/atmel_nand.c
>> @@ -1219,7 +1219,7 @@ static int __init atmel_nand_probe(struct device_d
>> *dev)
>>
>> if (IS_ENABLED(CONFIG_NAND_ECC_HW) &&
>> nand_chip->ecc.mode == NAND_ECC_HW) {
>> - if (IS_ENABLED(CONFIG_NAND_ATMEL_PMECC))
>> + if (pdata->has_pmecc)
>> res = atmel_pmecc_nand_init_params(dev, host);
>> else
>> res = atmel_hw_nand_init_params(dev, host);
>> --
>> 1.7.9.5
>>
>>
>> ___
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>
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Re: [PATCH V2 0/2] Add device tree support of i2c Atmel driver
Ok, about the "signed-off", do I have to let your name ? or my name + your name ? Sorry if my question seems stupid, but i'm new to open source development. 2014-08-06 3:06 GMT+02:00 Bo Shen : > Hi Raphaël Poggi, > > > On 08/06/2014 04:05 AM, Raphaël Poggi wrote: >> >> I am ready to send a v3. Are you going to send your fix or you want me >> to squash it in v3 ? > > > Please send it together with your patch. > Thanks. > >> Best Regards, >> Raphaël Poggi > > > Best Regards, > Bo Shen > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 1/2] pinctrl: at91: add pinctrl driver
Ok, let's do it like that Best regards, Raphaël Poggi 2014-08-06 5:48 GMT+02:00 Jean-Christophe PLAGNIOL-VILLARD : > > On Aug 6, 2014, at 11:46 AM, Jean-Christophe PLAGNIOL-VILLARD > wrote: > >> >> On Aug 5, 2014, at 7:38 PM, Raphaël Poggi wrote: >> >>> >>> Ok, so I drop my patch ? Or your version is very similar of my patch >>> and you can review mine to improve/clean it ? >> >> I’ve a patch series to have dt on at91, my patch for the pinctrl is not >> finish >> > > sorry I mean my patch series is not yet fully clean > >> give me few days to send it and we see after >> >> Best Regards, >> J. >>> >>> Best regards, >>> Raphaël Poggi >>> >>> 2014-08-05 12:26 GMT+02:00 Jean-Christophe PLAGNIOL-VILLARD >>> : >>>> >>>> On Aug 5, 2014, at 2:37 AM, Raphaël Poggi wrote: >>>> >>>>> >>>>> I have planned to add device tree support for the AT91 port. >>>>> >>>>> So I port the pinctrl driver from linux to barebox to be able to use >>>>> the pinctrl in device tree, but maybe I made a mistake and there is >>>>> another solution. >>>>> >>>> >>>> I’ve a version already that I need to update and send >>>> >>>> Best Regards, >>>> J. >>>>> Best Regards, >>>>> Raphaël >>>>> >>>>> 2014-08-04 20:26 GMT+02:00 Jean-Christophe PLAGNIOL-VILLARD >>>>> : >>>>>> why do we need it on barebox? >>>>>> >>>>>> this driver was design for dt-only in linux >>>>>> >>>>>> Best Regards, >>>>>> J. >>>>>> On Aug 1, 2014, at 9:24 PM, Raphaël Poggi wrote: >>>>>> >>>>>>> This driver is based on mach-at91/gpio.c and linux pinctrl driver. >>>>>>> The driver contains the gpio and pinctrl parts (like in linux) because >>>>>>> the two parts >>>>>>> share some structures and logics. >>>>>>> >>>>>>> Signed-off-by: Raphaël Poggi >>>>>>> --- >>>>>>> drivers/pinctrl/Kconfig|6 + >>>>>>> drivers/pinctrl/Makefile |1 + >>>>>>> drivers/pinctrl/pinctrl-at91.c | 529 >>>>>>> >>>>>>> drivers/pinctrl/pinctrl-at91.h | 148 +++ >>>>>>> 4 files changed, 684 insertions(+) >>>>>>> create mode 100644 drivers/pinctrl/pinctrl-at91.c >>>>>>> create mode 100644 drivers/pinctrl/pinctrl-at91.h >>>>>>> >>>>>>> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig >>>>>>> index dffaa4e..ce55c7b 100644 >>>>>>> --- a/drivers/pinctrl/Kconfig >>>>>>> +++ b/drivers/pinctrl/Kconfig >>>>>>> @@ -7,6 +7,12 @@ config PINCTRL >>>>>>> from the devicetree. Legacy drivers here may not need this core >>>>>>> support but instead provide their own SoC specific APIs >>>>>>> >>>>>>> +config PINCTRL_AT91 >>>>>>> + select PINCTRL >>>>>>> + bool >>>>>>> + help >>>>>>> + The pinmux controller found on AT91 SoCs. >>>>>>> + >>>>>>> config PINCTRL_IMX_IOMUX_V1 >>>>>>>select PINCTRL if OFDEVICE >>>>>>>bool >>>>>>> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile >>>>>>> index 566ba11..3ea8649 100644 >>>>>>> --- a/drivers/pinctrl/Makefile >>>>>>> +++ b/drivers/pinctrl/Makefile >>>>>>> @@ -1,4 +1,5 @@ >>>>>>> obj-$(CONFIG_PINCTRL) += pinctrl.o >>>>>>> +obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o >>>>>>> obj-$(CONFIG_PINCTRL_IMX_IOMUX_V1) += imx-iomux-v1.o >>>>>>> obj-$(CONFIG_PINCTRL_IMX_IOMUX_V2) += imx-iomux-v2.o >>>>>>> obj-$(CONFIG_PINCTRL_IMX_IOMUX_V3) += imx-iomux-v3.o >>>>>>> diff --git a/drivers/pinctrl/pinctrl-at91.c >>>>>>> b/drivers/pinctrl/pinctrl-at91.c >>>>>>> new file mode 100644 >>>>>>> index 00
[PATCH v2 1/2] pinctrl: at91: add pinctrl driver
This driver is based on mach-at91/gpio.c and linux pinctrl driver.
The driver contains the gpio and pinctrl parts (like in linux) because the two
parts
share some structures and logics.
Signed-off-by: Raphaël Poggi
---
drivers/pinctrl/Kconfig| 6 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-at91.c | 528 +
drivers/pinctrl/pinctrl-at91.h | 148
4 files changed, 683 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-at91.c
create mode 100644 drivers/pinctrl/pinctrl-at91.h
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index dffaa4e..ce55c7b 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -7,6 +7,12 @@ config PINCTRL
from the devicetree. Legacy drivers here may not need this core
support but instead provide their own SoC specific APIs
+config PINCTRL_AT91
+ select PINCTRL
+ bool
+ help
+ The pinmux controller found on AT91 SoCs.
+
config PINCTRL_IMX_IOMUX_V1
select PINCTRL if OFDEVICE
bool
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 566ba11..3ea8649 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_PINCTRL) += pinctrl.o
+obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_IMX_IOMUX_V1) += imx-iomux-v1.o
obj-$(CONFIG_PINCTRL_IMX_IOMUX_V2) += imx-iomux-v2.o
obj-$(CONFIG_PINCTRL_IMX_IOMUX_V3) += imx-iomux-v3.o
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
new file mode 100644
index 000..895bf42
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -0,0 +1,528 @@
+/*
+ * Copyright (C) 2005 HP Labs
+ * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD
+ * Copyright (C) 2014 Raphaël Poggi
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+
+#include "pinctrl-at91.h"
+
+struct at91_pinctrl {
+ struct pinctrl_device pctl;
+ struct at91_pinctrl_mux_ops *ops;
+};
+
+struct at91_gpio_chip {
+ struct gpio_chipchip;
+ void __iomem*regbase; /* PIO bank virtual address */
+ struct at91_pinctrl_mux_ops *ops; /* ops */
+};
+
+enum at91_mux {
+ AT91_MUX_GPIO = 0,
+ AT91_MUX_PERIPH_A = 1,
+ AT91_MUX_PERIPH_B = 2,
+ AT91_MUX_PERIPH_C = 3,
+ AT91_MUX_PERIPH_D = 4,
+};
+
+#define MAX_GPIO_BANKS 5
+#define to_at91_pinctrl(c) container_of(c, struct at91_pinctrl, pctl);
+#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
+
+#define PULL_UP (1 << 0)
+#define MULTI_DRIVE (1 << 1)
+#define DEGLITCH(1 << 2)
+#define PULL_DOWN (1 << 3)
+#define DIS_SCHMIT (1 << 4)
+#define DEBOUNCE(1 << 16)
+#define DEBOUNCE_VAL_SHIFT 17
+#define DEBOUNCE_VAL(0x3fff << DEBOUNCE_VAL_SHIFT)
+
+static int gpio_banks;
+
+static struct at91_gpio_chip gpio_chip[MAX_GPIO_BANKS];
+
+static inline void __iomem *pin_to_controller(struct at91_pinctrl *info,
unsigned pin)
+{
+ pin /= MAX_NB_GPIO_PER_BANK;
+ if (likely(pin < gpio_banks))
+ return gpio_chip[pin].regbase;
+
+ return NULL;
+}
+
+/**
+ * struct at91_pinctrl_mux_ops - describes an At91 mux ops group
+ * on new IP with support for periph C and D the way to mux in
+ * periph A and B has changed
+ * So provide the right call back
+ * if not present means the IP does not support it
+ * @get_periph: return the periph mode configured
+ * @mux_A_periph: mux as periph A
+ * @mux_B_periph: mux as periph B
+ * @mux_C_periph: mux as periph C
+ * @mux_D_periph: mux as periph D
+ * @set_deglitch: enable/disable deglitch
+ * @set_debounce: enable/disable debounce
+ * @set_pulldown: enable/disable pulldown
+ * @disable_schmitt_trig: disable schmitt trigger
+ */
+struct at91_pinctrl_mux_ops {
+ enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_A_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_B_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_C_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_D_periph)(void __iomem *pio, unsigned mask);
+ bool (*get_d
[PATCH v2 0/2] Add atmel pinctrl driver
Change since v1: * Fix coding style issue. * Register gpio clocks with CLKDEV_DEV_ID instead of CLKDEV_CON_DEV_ID This patchset add atmel pinctrl/gpio driver and the corresponding clocks for the at91sam9g45 device. The pinctrl driver also include the gpio driver (like in linux) because the gpio and pinctrl parts share same structures. Raphaël Poggi (2) : (1) pinctrl: at91: add pinctrl driver (2) at91sam9g45: add device tree gpio clocks arch/arm/mach-at91/at91sam9g45.c | 5 ++ drivers/pinctrl/Kconfig | 6 ++ drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-at91.c | 528 +++ drivers/pinctrl/pinctrl-at91.h | 148 ++ 5 files changed, 688 insertions(+) ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v2 2/2] at91sam9g45: add device tree gpio clocks
Signed-off-by: Raphaël Poggi
---
arch/arm/mach-at91/at91sam9g45.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index d19d26a..8c020fa 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -201,6 +201,11 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
CLKDEV_DEV_ID("at91rm9200-gpio3", &pioDE_clk),
CLKDEV_DEV_ID("at91rm9200-gpio4", &pioDE_clk),
+ CLKDEV_DEV_ID("f200.gpio", &pioA_clk),
+ CLKDEV_DEV_ID("f400.gpio", &pioB_clk),
+ CLKDEV_DEV_ID("f600.gpio", &pioC_clk),
+ CLKDEV_DEV_ID("f800.gpio", &pioDE_clk),
+ CLKDEV_DEV_ID("fa00.gpio", &pioDE_clk),
CLKDEV_DEV_ID("at91-pit", &mck),
CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk),
};
--
1.8.3.2
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Re: [PATCH V2 0/2] Add device tree support of i2c Atmel driver
I am ready to send a v3. Are you going to send your fix or you want me to squash it in v3 ? Best Regards, Raphaël Poggi 2014-08-05 10:32 GMT+02:00 Raphaël Poggi : > Hello, > > The patch works fine for me. Thanks for your review/help. > > Best Regards, > Raphaël Poggi > > 2014-08-05 8:55 GMT+02:00 Bo Shen : >> Hi Raphaël Poggi, >> >> >> On 08/04/2014 05:29 PM, Bo Shen wrote: >>> >>> Hi Raphaël Poggi, >>> >>> On 08/04/2014 05:22 PM, Raphaël Poggi wrote: >>>> >>>> Hi, >>>> >>>> I have tested it on a custom board which use a sam9m10 and it >>>> worked... Tell me more when we have found something suspicious. >>> >>> >>> I tested on sama5d3xek with qt1070 connect to i2c, and the i2c host >>> register successfully, however can not access qt1070, if I use i2c-gpio >>> driver, it works well. >>> >>> I am still working on it, if any news, I will let you know. >> >> >> I have re-write the interrupt function as the enclosed patch. Then, the i2c >> host driver works properly. >> >> Can you help test it also on your board? >> >> Thanks. >> >> >>> Best Regards, >>> Bo Shen >>> >>>> Thanks for your test. >>>> >>>> Raphaël Poggi >>>> >> >> Best Regards, >> Bo Shen ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 1/2] pinctrl: at91: add pinctrl driver
Ok, so I drop my patch ? Or your version is very similar of my patch and you can review mine to improve/clean it ? Best regards, Raphaël Poggi 2014-08-05 12:26 GMT+02:00 Jean-Christophe PLAGNIOL-VILLARD : > > On Aug 5, 2014, at 2:37 AM, Raphaël Poggi wrote: > >> >> I have planned to add device tree support for the AT91 port. >> >> So I port the pinctrl driver from linux to barebox to be able to use >> the pinctrl in device tree, but maybe I made a mistake and there is >> another solution. >> > > I’ve a version already that I need to update and send > > Best Regards, > J. >> Best Regards, >> Raphaël >> >> 2014-08-04 20:26 GMT+02:00 Jean-Christophe PLAGNIOL-VILLARD >> : >>> why do we need it on barebox? >>> >>> this driver was design for dt-only in linux >>> >>> Best Regards, >>> J. >>> On Aug 1, 2014, at 9:24 PM, Raphaël Poggi wrote: >>> >>>> This driver is based on mach-at91/gpio.c and linux pinctrl driver. >>>> The driver contains the gpio and pinctrl parts (like in linux) because the >>>> two parts >>>> share some structures and logics. >>>> >>>> Signed-off-by: Raphaël Poggi >>>> --- >>>> drivers/pinctrl/Kconfig|6 + >>>> drivers/pinctrl/Makefile |1 + >>>> drivers/pinctrl/pinctrl-at91.c | 529 >>>> >>>> drivers/pinctrl/pinctrl-at91.h | 148 +++ >>>> 4 files changed, 684 insertions(+) >>>> create mode 100644 drivers/pinctrl/pinctrl-at91.c >>>> create mode 100644 drivers/pinctrl/pinctrl-at91.h >>>> >>>> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig >>>> index dffaa4e..ce55c7b 100644 >>>> --- a/drivers/pinctrl/Kconfig >>>> +++ b/drivers/pinctrl/Kconfig >>>> @@ -7,6 +7,12 @@ config PINCTRL >>>>from the devicetree. Legacy drivers here may not need this core >>>>support but instead provide their own SoC specific APIs >>>> >>>> +config PINCTRL_AT91 >>>> + select PINCTRL >>>> + bool >>>> + help >>>> + The pinmux controller found on AT91 SoCs. >>>> + >>>> config PINCTRL_IMX_IOMUX_V1 >>>> select PINCTRL if OFDEVICE >>>> bool >>>> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile >>>> index 566ba11..3ea8649 100644 >>>> --- a/drivers/pinctrl/Makefile >>>> +++ b/drivers/pinctrl/Makefile >>>> @@ -1,4 +1,5 @@ >>>> obj-$(CONFIG_PINCTRL) += pinctrl.o >>>> +obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o >>>> obj-$(CONFIG_PINCTRL_IMX_IOMUX_V1) += imx-iomux-v1.o >>>> obj-$(CONFIG_PINCTRL_IMX_IOMUX_V2) += imx-iomux-v2.o >>>> obj-$(CONFIG_PINCTRL_IMX_IOMUX_V3) += imx-iomux-v3.o >>>> diff --git a/drivers/pinctrl/pinctrl-at91.c >>>> b/drivers/pinctrl/pinctrl-at91.c >>>> new file mode 100644 >>>> index 000..a92a898 >>>> --- /dev/null >>>> +++ b/drivers/pinctrl/pinctrl-at91.c >>>> @@ -0,0 +1,529 @@ >>>> +/* >>>> + * Copyright (C) 2005 HP Labs >>>> + * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD >>>> >>>> + * Copyright (C) 2014 Raphaël Poggi >>>> + * >>>> + * See file CREDITS for list of people who contributed to this >>>> + * project. >>>> + * >>>> + * This program is free software; you can redistribute it and/or >>>> + * modify it under the terms of the GNU General Public License as >>>> + * published by the Free Software Foundation; either version 2 of >>>> + * the License, or (at your option) any later version. >>>> + * >>>> + * This program is distributed in the hope that it will be useful, >>>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >>>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >>>> + * GNU General Public License for more details. >>>> + * >>>> + */ >>>> + >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> +#include >>>> + >>>&g
Re: [PATCH v2 0/5] Add device tree support of Atmel NAND driver
I forget to add a "v2" tag on the patches, do I need to resend all the serie ? Thanks, Raphaël Poggi 2014-08-05 11:14 GMT+02:00 Raphaël Poggi : > Change since v1: > * Reorder patchs > * Fix some clean style issue. > > This patchset adds the device tree support for the Atmel NAND driver. > > The first patch removes the NAND_ATMEL_PMECC config. With this removal > we can manage in a better way the device tree / non device tree probing of > the driver, because the plateform data > and device tree share the same structure member and logics. > > The second patch adds the has_pmecc on boards which need it. > > The third patch retrieves the ecc_mode from the plateform data and remove > this code: > > nand_chip->ecc.mode = NAND_ECC_SOFT; > > which arbitrary sets the ecc.mode to NAND_ECC_SOFT and changes the value > depending of the config and plateform data. > With this, we can use the same logics for device tree and non device tree > probing of the driver. > > The fourth patch adds the ecc_mode on boards which are missing it (boards > which use NAND_ECC_SOFT). > > The fifth patch adds the device tree in the atmel_nand driver. > > Raphaël Poggi (5) : > (1) mtd: nand: remove NAND_ATMEL_PMECC > (2) board: atmel: initialise the has_pmecc member > (3) mtd: atmel_nand: retrieve ecc_mode from pdata > (4) board: atmel: initialise ecc_mode > (5) mtd: atmel_nand: add support for device tree > > arch/arm/boards/at91sam9260ek/init.c|1 + > arch/arm/boards/at91sam9261ek/init.c|1 + > arch/arm/boards/at91sam9263ek/init.c|1 + > arch/arm/boards/at91sam9m10g45ek/init.c |1 + > arch/arm/boards/at91sam9m10ihd/init.c |1 + > arch/arm/boards/at91sam9n12ek/init.c|1 + > arch/arm/boards/at91sam9x5ek/init.c |1 + > arch/arm/boards/sama5d3_xplained/init.c |1 + > arch/arm/boards/sama5d3xek/init.c |1 + > arch/arm/mach-at91/include/mach/board.h |1 + > drivers/mtd/nand/Kconfig|8 --- > drivers/mtd/nand/atmel_nand.c | 115 > ++- > 12 files changed, 122 insertions(+), 11 deletions(-) > > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 3/5] mtd: atmel_nand: retrieve ecc_mode from pdata
By retrieving the ecc_mode from pdata we can use the same code for device tree
and
non device tree probing. Which was not possible before, because ecc_mode was
arbitrarily set to
NAND_ECC_SOFT.
Signed-off-by: Raphaël Poggi
---
drivers/mtd/nand/atmel_nand.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 3ec6450..780d266 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1157,7 +1157,7 @@ static int __init atmel_nand_probe(struct device_d *dev)
}
}
- nand_chip->ecc.mode = NAND_ECC_SOFT;
+ nand_chip->ecc.mode = pdata->ecc_mode;
if (IS_ENABLED(CONFIG_NAND_ECC_HW) &&
pdata->ecc_mode == NAND_ECC_HW) {
--
1.7.9.5
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[PATCH 4/5] board: atmel: initialise ecc_mode
This commit initialise the ecc_mode (NAND_ECC_SOFT) on atmel board init which
missing it.
Signed-off-by: Raphaël Poggi
---
arch/arm/boards/at91sam9260ek/init.c|1 +
arch/arm/boards/at91sam9261ek/init.c|1 +
arch/arm/boards/at91sam9263ek/init.c|1 +
arch/arm/boards/at91sam9m10g45ek/init.c |1 +
arch/arm/boards/at91sam9m10ihd/init.c |1 +
5 files changed, 5 insertions(+)
diff --git a/arch/arm/boards/at91sam9260ek/init.c
b/arch/arm/boards/at91sam9260ek/init.c
index 1298dde..76e0195 100644
--- a/arch/arm/boards/at91sam9260ek/init.c
+++ b/arch/arm/boards/at91sam9260ek/init.c
@@ -51,6 +51,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PC13,
.enable_pin = AT91_PIN_PC14,
+ .ecc_mode = NAND_ECC_SOFT,
.on_flash_bbt = 1,
};
diff --git a/arch/arm/boards/at91sam9261ek/init.c
b/arch/arm/boards/at91sam9261ek/init.c
index 9ebc16a..7b8ce98 100644
--- a/arch/arm/boards/at91sam9261ek/init.c
+++ b/arch/arm/boards/at91sam9261ek/init.c
@@ -46,6 +46,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PC15,
.enable_pin = AT91_PIN_PC14,
+ .ecc_mode = NAND_ECC_SOFT,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
.bus_width_16 = 1,
#else
diff --git a/arch/arm/boards/at91sam9263ek/init.c
b/arch/arm/boards/at91sam9263ek/init.c
index 889b4c2..c8a9d5c 100644
--- a/arch/arm/boards/at91sam9263ek/init.c
+++ b/arch/arm/boards/at91sam9263ek/init.c
@@ -43,6 +43,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PA22,
.enable_pin = AT91_PIN_PD15,
+ .ecc_mode = NAND_ECC_SOFT,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
.bus_width_16 = 1,
#else
diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c
b/arch/arm/boards/at91sam9m10g45ek/init.c
index 6503ebb..cdd7806 100644
--- a/arch/arm/boards/at91sam9m10g45ek/init.c
+++ b/arch/arm/boards/at91sam9m10g45ek/init.c
@@ -67,6 +67,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PC8,
.enable_pin = AT91_PIN_PC14,
+ .ecc_mode = NAND_ECC_SOFT,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
.bus_width_16 = 1,
#else
diff --git a/arch/arm/boards/at91sam9m10ihd/init.c
b/arch/arm/boards/at91sam9m10ihd/init.c
index fc37af4..a432e5c 100644
--- a/arch/arm/boards/at91sam9m10ihd/init.c
+++ b/arch/arm/boards/at91sam9m10ihd/init.c
@@ -44,6 +44,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PC15,
.enable_pin = AT91_PIN_PC14,
+ .ecc_mode = NAND_ECC_SOFT,
.bus_width_16 = 0,
.on_flash_bbt = 1,
};
--
1.7.9.5
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[PATCH 2/5] board: atmel: initialise the has_pmecc member
---
arch/arm/boards/at91sam9n12ek/init.c|1 +
arch/arm/boards/at91sam9x5ek/init.c |1 +
arch/arm/boards/sama5d3_xplained/init.c |1 +
arch/arm/boards/sama5d3xek/init.c |1 +
4 files changed, 4 insertions(+)
diff --git a/arch/arm/boards/at91sam9n12ek/init.c
b/arch/arm/boards/at91sam9n12ek/init.c
index a206d6b..818a598 100644
--- a/arch/arm/boards/at91sam9n12ek/init.c
+++ b/arch/arm/boards/at91sam9n12ek/init.c
@@ -47,6 +47,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PD5,
.enable_pin = AT91_PIN_PD4,
+ .has_pmecc = 1,
.ecc_mode = NAND_ECC_HW,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 2,
diff --git a/arch/arm/boards/at91sam9x5ek/init.c
b/arch/arm/boards/at91sam9x5ek/init.c
index 62e5652..183ddc7 100644
--- a/arch/arm/boards/at91sam9x5ek/init.c
+++ b/arch/arm/boards/at91sam9x5ek/init.c
@@ -57,6 +57,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PD5,
.enable_pin = AT91_PIN_PD4,
+ .has_pmecc = 1,
.ecc_mode = NAND_ECC_HW,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 2,
diff --git a/arch/arm/boards/sama5d3_xplained/init.c
b/arch/arm/boards/sama5d3_xplained/init.c
index ae18863..b182802 100644
--- a/arch/arm/boards/sama5d3_xplained/init.c
+++ b/arch/arm/boards/sama5d3_xplained/init.c
@@ -48,6 +48,7 @@ static struct atmel_nand_data nand_pdata = {
.rdy_pin= -EINVAL,
.enable_pin = -EINVAL,
.ecc_mode = NAND_ECC_HW,
+ .has_pmecc = 1,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 4,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
diff --git a/arch/arm/boards/sama5d3xek/init.c
b/arch/arm/boards/sama5d3xek/init.c
index 743197f..49d2b37 100644
--- a/arch/arm/boards/sama5d3xek/init.c
+++ b/arch/arm/boards/sama5d3xek/init.c
@@ -63,6 +63,7 @@ static struct atmel_nand_data nand_pdata = {
.rdy_pin= -EINVAL,
.enable_pin = -EINVAL,
.ecc_mode = NAND_ECC_HW,
+ .has_pmecc = 1,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 4,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
--
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[PATCH 1/5] mtd: nand: remove NAND_ATMEL_PMECC
By removing this CONFIG_, we can use a structure member to retrieve the config,
either through the plateform data or through the device tree. So we can handle
cases
when the driver is probed using device tree or not.
Signed-off-by: Raphaël Poggi
---
arch/arm/mach-at91/include/mach/board.h |1 +
drivers/mtd/nand/Kconfig|8
drivers/mtd/nand/atmel_nand.c |2 +-
3 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/board.h
b/arch/arm/mach-at91/include/mach/board.h
index aa0fdae..e2307ed 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -63,6 +63,7 @@ struct atmel_nand_data {
u8 bus_width_16; /* buswidth is 16 bit */
u8 ecc_mode; /* NAND_ECC_* */
u8 on_flash_bbt; /* Use flash based bbt */
+ u8 has_pmecc; /* Use PMECC */
u8 bus_on_d0;
u8 pmecc_corr_cap;
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 04fe3c8..d49eae3 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -95,14 +95,6 @@ config NAND_ATMEL
prompt "Atmel (AT91SAM9xxx) NAND driver"
depends on ARCH_AT91
-config NAND_ATMEL_PMECC
- bool
- prompt "PMECC support"
- depends on NAND_ATMEL
- select NAND_ECC_HW
- help
- Support for PMECC present on the SoC sam9x5 and sam9n12
-
config NAND_S3C24XX
bool
prompt "Samsung S3C24XX NAND driver"
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 337e225..3ec6450 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1219,7 +1219,7 @@ static int __init atmel_nand_probe(struct device_d *dev)
if (IS_ENABLED(CONFIG_NAND_ECC_HW) &&
nand_chip->ecc.mode == NAND_ECC_HW) {
- if (IS_ENABLED(CONFIG_NAND_ATMEL_PMECC))
+ if (pdata->has_pmecc)
res = atmel_pmecc_nand_init_params(dev, host);
else
res = atmel_hw_nand_init_params(dev, host);
--
1.7.9.5
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[PATCH v2 0/5] Add device tree support of Atmel NAND driver
Change since v1: * Reorder patchs * Fix some clean style issue. This patchset adds the device tree support for the Atmel NAND driver. The first patch removes the NAND_ATMEL_PMECC config. With this removal we can manage in a better way the device tree / non device tree probing of the driver, because the plateform data and device tree share the same structure member and logics. The second patch adds the has_pmecc on boards which need it. The third patch retrieves the ecc_mode from the plateform data and remove this code: nand_chip->ecc.mode = NAND_ECC_SOFT; which arbitrary sets the ecc.mode to NAND_ECC_SOFT and changes the value depending of the config and plateform data. With this, we can use the same logics for device tree and non device tree probing of the driver. The fourth patch adds the ecc_mode on boards which are missing it (boards which use NAND_ECC_SOFT). The fifth patch adds the device tree in the atmel_nand driver. Raphaël Poggi (5) : (1) mtd: nand: remove NAND_ATMEL_PMECC (2) board: atmel: initialise the has_pmecc member (3) mtd: atmel_nand: retrieve ecc_mode from pdata (4) board: atmel: initialise ecc_mode (5) mtd: atmel_nand: add support for device tree arch/arm/boards/at91sam9260ek/init.c|1 + arch/arm/boards/at91sam9261ek/init.c|1 + arch/arm/boards/at91sam9263ek/init.c|1 + arch/arm/boards/at91sam9m10g45ek/init.c |1 + arch/arm/boards/at91sam9m10ihd/init.c |1 + arch/arm/boards/at91sam9n12ek/init.c|1 + arch/arm/boards/at91sam9x5ek/init.c |1 + arch/arm/boards/sama5d3_xplained/init.c |1 + arch/arm/boards/sama5d3xek/init.c |1 + arch/arm/mach-at91/include/mach/board.h |1 + drivers/mtd/nand/Kconfig|8 --- drivers/mtd/nand/atmel_nand.c | 115 ++- 12 files changed, 122 insertions(+), 11 deletions(-) ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 5/5] mtd: atmel_nand: add support for device tree
Signed-off-by: Raphaël Poggi
---
drivers/mtd/nand/atmel_nand.c | 111 -
1 file changed, 110 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 780d266..a5d05d8 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -28,6 +28,10 @@
#include
#include
+#include
+#include
+#include
+
#include
#include
@@ -1038,6 +1042,92 @@ static void atmel_nand_hwctl(struct mtd_info *mtd, int
mode)
#endif
}
+static int atmel_nand_of_init(struct atmel_nand_host *host, struct device_node
*np)
+{
+ u32 val;
+ u32 offset[2];
+ int ecc_mode;
+ struct atmel_nand_data *board = host->board;
+ enum of_gpio_flags flags = 0;
+
+ if (!IS_ENABLED(CONFIG_OFDEVICE))
+ return -ENOSYS;
+
+ if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
+ if (val >= 32) {
+ dev_err(host->dev, "invalid addr-offset %u\n", val);
+ return -EINVAL;
+ }
+ board->ale = val;
+ }
+
+ if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
+ if (val >= 32) {
+ dev_err(host->dev, "invalid cmd-offset %u\n", val);
+ return -EINVAL;
+ }
+ board->cle = val;
+ }
+
+ ecc_mode = of_get_nand_ecc_mode(np);
+
+ board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
+
+ board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
+
+ if (of_get_nand_bus_width(np) == 16)
+ board->bus_width_16 = 1;
+
+ board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
+ board->enable_pin = of_get_gpio(np, 1);
+ board->det_pin = of_get_gpio(np, 2);
+
+ board->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
+
+ if (!(board->ecc_mode == NAND_ECC_HW) || !board->has_pmecc)
+ return 0; /* Not using PMECC */
+
+ /* use PMECC, get correction capability, sector size and lookup
+ * table offset.
+ * If correction bits and sector size are not specified, then
+ * find
+ * them from NAND ONFI parameters.
+ */
+ if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
+ if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
(val != 24)) {
+ dev_err(host->dev, "Unsupported PMECC correction
capability: %d"
+ " should be 2, 4, 8, 12 or 24\n", val);
+ return -EINVAL;
+ }
+
+ board->pmecc_corr_cap = (u8)val;
+ }
+
+ if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
+ if ((val != 512) && (val != 1024)) {
+ dev_err(host->dev, "Unsupported PMECC sector
size: %d"
+ " should be 512 or 1024 bytes\n", val);
+ return -EINVAL;
+ }
+
+ board->pmecc_sector_size = (u16)val;
+ }
+
+ if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
offset, 2) != 0) {
+ dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
+ return -EINVAL;
+ }
+
+ if (!offset[0] && !offset[1]) {
+ dev_err(host->dev, "Invalid PMECC lookup table offset\n");
+ return -EINVAL;
+ }
+
+ board->pmecc_lookup_table_offset = (board->pmecc_sector_size == 512) ?
offset[0] : offset[1];
+
+ return 0;
+}
+
static int atmel_hw_nand_init_params(struct device_d *dev,
struct atmel_nand_host *host)
{
@@ -1093,7 +1183,7 @@ static int atmel_hw_nand_init_params(struct device_d *dev,
*/
static int __init atmel_nand_probe(struct device_d *dev)
{
- struct atmel_nand_data *pdata = dev->platform_data;
+ struct atmel_nand_data *pdata = NULL;
struct atmel_nand_host *host;
struct mtd_info *mtd;
struct nand_chip *nand_chip;
@@ -,6 +1201,18 @@ static int __init atmel_nand_probe(struct device_d *dev)
host->board = pdata;
host->dev = dev;
+ if (dev->device_node) {
+ res = atmel_nand_of_init(host, dev->device_node);
+ if (res)
+ goto err_no_card;
+ } else {
+ pdata = kzalloc(sizeof(struct atmel_nand_data), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ memcpy(host->board, dev->platform_data,
Re: [PATCH V2 0/2] Add device tree support of i2c Atmel driver
Hello, The patch works fine for me. Thanks for your review/help. Best Regards, Raphaël Poggi 2014-08-05 8:55 GMT+02:00 Bo Shen : > Hi Raphaël Poggi, > > > On 08/04/2014 05:29 PM, Bo Shen wrote: >> >> Hi Raphaël Poggi, >> >> On 08/04/2014 05:22 PM, Raphaël Poggi wrote: >>> >>> Hi, >>> >>> I have tested it on a custom board which use a sam9m10 and it >>> worked... Tell me more when we have found something suspicious. >> >> >> I tested on sama5d3xek with qt1070 connect to i2c, and the i2c host >> register successfully, however can not access qt1070, if I use i2c-gpio >> driver, it works well. >> >> I am still working on it, if any news, I will let you know. > > > I have re-write the interrupt function as the enclosed patch. Then, the i2c > host driver works properly. > > Can you help test it also on your board? > > Thanks. > > >> Best Regards, >> Bo Shen >> >>> Thanks for your test. >>> >>> Raphaël Poggi >>> > > Best Regards, > Bo Shen ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
Re: [PATCH 1/2] pinctrl: at91: add pinctrl driver
I have planned to add device tree support for the AT91 port.
So I port the pinctrl driver from linux to barebox to be able to use
the pinctrl in device tree, but maybe I made a mistake and there is
another solution.
Best Regards,
Raphaël
2014-08-04 20:26 GMT+02:00 Jean-Christophe PLAGNIOL-VILLARD
:
> why do we need it on barebox?
>
> this driver was design for dt-only in linux
>
> Best Regards,
> J.
> On Aug 1, 2014, at 9:24 PM, Raphaël Poggi wrote:
>
>> This driver is based on mach-at91/gpio.c and linux pinctrl driver.
>> The driver contains the gpio and pinctrl parts (like in linux) because the
>> two parts
>> share some structures and logics.
>>
>> Signed-off-by: Raphaël Poggi
>> ---
>> drivers/pinctrl/Kconfig|6 +
>> drivers/pinctrl/Makefile |1 +
>> drivers/pinctrl/pinctrl-at91.c | 529
>>
>> drivers/pinctrl/pinctrl-at91.h | 148 +++
>> 4 files changed, 684 insertions(+)
>> create mode 100644 drivers/pinctrl/pinctrl-at91.c
>> create mode 100644 drivers/pinctrl/pinctrl-at91.h
>>
>> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
>> index dffaa4e..ce55c7b 100644
>> --- a/drivers/pinctrl/Kconfig
>> +++ b/drivers/pinctrl/Kconfig
>> @@ -7,6 +7,12 @@ config PINCTRL
>> from the devicetree. Legacy drivers here may not need this core
>> support but instead provide their own SoC specific APIs
>>
>> +config PINCTRL_AT91
>> + select PINCTRL
>> + bool
>> + help
>> + The pinmux controller found on AT91 SoCs.
>> +
>> config PINCTRL_IMX_IOMUX_V1
>> select PINCTRL if OFDEVICE
>> bool
>> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
>> index 566ba11..3ea8649 100644
>> --- a/drivers/pinctrl/Makefile
>> +++ b/drivers/pinctrl/Makefile
>> @@ -1,4 +1,5 @@
>> obj-$(CONFIG_PINCTRL) += pinctrl.o
>> +obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
>> obj-$(CONFIG_PINCTRL_IMX_IOMUX_V1) += imx-iomux-v1.o
>> obj-$(CONFIG_PINCTRL_IMX_IOMUX_V2) += imx-iomux-v2.o
>> obj-$(CONFIG_PINCTRL_IMX_IOMUX_V3) += imx-iomux-v3.o
>> diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
>> new file mode 100644
>> index 000..a92a898
>> --- /dev/null
>> +++ b/drivers/pinctrl/pinctrl-at91.c
>> @@ -0,0 +1,529 @@
>> +/*
>> + * Copyright (C) 2005 HP Labs
>> + * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD
>>
>> + * Copyright (C) 2014 Raphaël Poggi
>> + *
>> + * See file CREDITS for list of people who contributed to this
>> + * project.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include
>> +
>> +#include
>> +
>> +#include "pinctrl-at91.h"
>> +
>> +struct at91_pinctrl {
>> +struct pinctrl_device pctl;
>> +struct at91_pinctrl_mux_ops *ops;
>> +};
>> +
>> +struct at91_gpio_chip {
>> + struct gpio_chipchip;
>> + void __iomem*regbase; /* PIO bank virtual address */
>> + struct at91_pinctrl_mux_ops *ops; /* ops */
>> +};
>> +
>> +enum at91_mux {
>> + AT91_MUX_GPIO = 0,
>> + AT91_MUX_PERIPH_A = 1,
>> + AT91_MUX_PERIPH_B = 2,
>> + AT91_MUX_PERIPH_C = 3,
>> + AT91_MUX_PERIPH_D = 4,
>> +};
>> +
>> +#define MAX_GPIO_BANKS 5
>> +#define to_at91_pinctrl(c) container_of(c, struct at91_pinctrl, pctl);
>> +#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
>> +
>> +#define PULL_UP (1 << 0)
>> +#define MULTI_DRIVE (1 << 1)
>> +#define DEGLITCH(1 << 2)
>> +#define PULL_DOWN (1 << 3)
>> +#define DIS_SCHMIT (1 << 4)
&
Re: [PATCH 1/5] mtd: atmel_nand: add support for device tree
Hi Sascha,
Thanks for your review.
I will send a v2 with the modification. I will also reorder patches in
the patchset.
Raphaël
2014-08-04 19:43 GMT+02:00 Sascha Hauer :
> On Fri, Aug 01, 2014 at 03:23:20PM +0200, Raphaël Poggi wrote:
>> Signed-off-by: Raphaël Poggi
>> ---
>> drivers/mtd/nand/atmel_nand.c | 108
>> -
>> 1 file changed, 107 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
>> index 337e225..b7b0e3a 100644
>> --- a/drivers/mtd/nand/atmel_nand.c
>> +++ b/drivers/mtd/nand/atmel_nand.c
>> @@ -28,6 +28,10 @@
>> #include
>> #include
>>
>> +#include
>> +#include
>> +#include
>> +
>> #include
>> #include
>>
>> @@ -1038,6 +1042,89 @@ static void atmel_nand_hwctl(struct mtd_info *mtd,
>> int mode)
>> #endif
>> }
>>
>> +static int atmel_nand_of_init(struct atmel_nand_host *host, struct
>> device_node *np)
>> +{
>> + u32 val;
>> + u32 offset[2];
>> + int ecc_mode;
>> + struct atmel_nand_data *board = host->board;
>> + enum of_gpio_flags flags = 0;
>
> Please add a:
>
> if (!IS_ENABLED(CONFIG_OFDEVICE))
> return -ENOSYS;
>
> to this function. It will allow the compiler to throw it away when
> device tree support is disabled.
>
>> +
>> + if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
>> +if (val >= 32) {
>
> Please fix the coding style. First indentation here is a tab, but the
> second is 4 spaces. Indentation should be tabs generally.
>
>> + dev_err(host->dev, "invalid addr-offset %u\n", val);
>> + return -EINVAL;
>> + }
>> + board->ale = val;
>> + }
>> +
>> + if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
>> + if (val >= 32) {
>> + dev_err(host->dev, "invalid cmd-offset %u\n", val);
>> + return -EINVAL;
>> + }
>> + board->cle = val;
>> + }
>> +
>> + ecc_mode = of_get_nand_ecc_mode(np);
>> +
>> + board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
>> +
>> + board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
>> +
>> + if (of_get_nand_bus_width(np) == 16)
>> + board->bus_width_16 = 1;
>> +
>> + board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
>> + board->enable_pin = of_get_gpio(np, 1);
>> + board->det_pin = of_get_gpio(np, 2);
>> +
>> + board->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
>> +
>> + if (!(board->ecc_mode == NAND_ECC_HW) || !board->has_pmecc)
>> + return 0; /* Not using PMECC */
>> +
>> + /* use PMECC, get correction capability, sector size and lookup
>> + * table offset.
>> + * If correction bits and sector size are not specified, then
>> + * find
>> + * them from NAND ONFI parameters.
>> + */
>> + if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
>> + if ((val != 2) && (val != 4) && (val != 8) && (val != 12) && (val
>> != 24)) {
>> + dev_err(host->dev, "Unsupported PMECC correction capability:
>> %d"
>> + " should be 2, 4, 8, 12 or 24\n", val);
>> + return -EINVAL;
>> + }
>> +
>> + board->pmecc_corr_cap = (u8)val;
>> + }
>> +
>> + if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
>> + if ((val != 512) && (val != 1024)) {
>> + dev_err(host->dev, "Unsupported PMECC sector size: %d"
>> + " should be 512 or 1024 bytes\n", val);
>> + return -EINVAL;
>> + }
>> +
>> + board->pmecc_sector_size = (u16)val;
>> + }
>> +
>> + if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
>> offset, 2) != 0) {
>> + dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
>> + return -EINVAL;
>> + }
>> +
>> + if (!offset[0] && !offset[1]) {
>> + dev_err(host->dev, "Invalid PMECC lookup table
Re: [PATCH V2 1/2] i2c: at91: add support of device tree
> Hi Raphaël Poggi,
>
> On 08/04/2014 04:31 PM, Raphaël Poggi wrote:
> >Signed-off-by: Raphaël Poggi
> >---
> > drivers/i2c/busses/i2c-at91.c | 66
> > -
> > 1 file changed, 58 insertions(+), 8 deletions(-)
> >
> >diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
> >index 399f6a9..944a8b3 100644
> >--- a/drivers/i2c/busses/i2c-at91.c
> >+++ b/drivers/i2c/busses/i2c-at91.c
> >@@ -346,6 +346,12 @@ static struct at91_twi_pdata at91sam9g10_config = {
> > .has_unre_flag = false,
> > };
> >
> >+static struct at91_twi_pdata at91sam9x5_config = {
> >+.clk_max_div = 7,
> >+.clk_offset = 4,
> >+.has_unre_flag = false,
> >+};
> >+
>
> Can you add this also for non device tree?
Ok no problem.
>
> > static struct platform_device_id at91_twi_devtypes[] = {
> > {
> > .name = "i2c-at91rm9200",
> >@@ -367,20 +373,63 @@ static struct platform_device_id at91_twi_devtypes[] =
> >{
> > }
> > };
> >
> >+static struct of_device_id at91_twi_dt_ids[] = {
> >+{
> >+.compatible = "atmel,at91rm9200-i2c",
> >+.data = (unsigned long) &at91rm9200_config,
> >+} , {
> >+.compatible = "atmel,at91sam9260-i2c",
> >+.data = (unsigned long) &at91sam9260_config,
> >+} , {
> >+.compatible = "atmel,at91sam9261-i2c",
> >+.data = (unsigned long) &at91sam9261_config,
> >+} , {
> >+.compatible = "atmel,at91sam9g20-i2c",
> >+.data = (unsigned long) &at91sam9g20_config,
> >+} , {
> >+.compatible = "atmel,at91sam9g10-i2c",
> >+.data = (unsigned long) &at91sam9g10_config,
> >+}, {
> >+.compatible = "atmel,at91sam9x5-i2c",
> >+.data = (unsigned long) &at91sam9x5_config,
> >+}, {
> >+/* sentinel */
> >+}
> >+};
> >+
> >+static struct at91_twi_pdata *at91_twi_get_driver_data(struct device_d *dev)
> >+{
> >+struct at91_twi_pdata *i2c_data = NULL;
> >+int rc;
> >+
> >+if (dev->device_node) {
> >+const struct of_device_id *match;
> >+match = of_match_node(at91_twi_dt_ids, dev->device_node);
> >+if (!match)
> >+i2c_data = NULL;
> >+else
> >+i2c_data = (struct at91_twi_pdata *)match->data;
> >+}
> >+else {
>
> Maybe better if: } else {
Ok
>
> >+rc = dev_get_drvdata(dev, (unsigned long *)&i2c_data);
> >+if (rc)
> >+i2c_data = NULL;
> >+}
> >+
> >+return i2c_data;
> >+}
> >+
> > static int at91_twi_probe(struct device_d *dev)
> > {
> > struct at91_twi_dev *i2c_at91;
> >-struct at91_twi_pdata *i2c_data;
> >-int rc;
> >+int rc = 0;
> > u32 bus_clk_rate;
> >
> > i2c_at91 = xzalloc(sizeof(struct at91_twi_dev));
> >
> >-rc = dev_get_drvdata(dev, (unsigned long *)&i2c_data);
> >-if (rc)
> >-goto out_free;
> >-
> >-i2c_at91->pdata = i2c_data;
> >+i2c_at91->pdata = at91_twi_get_driver_data(dev);
> >+if (!i2c_at91->pdata)
> >+goto out_free;
>
> Maybe add error information will be better.
Yes, you're right.
>
> Btw, do you use "tab" for alignment?
Yes, but maybe my vim config is wrong ? (set tabstop=4, set shiftwidth=4, set
softtabstop=4)
>
> > i2c_at91->base = dev_request_mem_region(dev, 0);
> > if (!i2c_at91->base) {
> >@@ -389,7 +438,7 @@ static int at91_twi_probe(struct device_d *dev)
> > goto out_free;
> > }
> >
> >-i2c_at91->clk = clk_get(dev, "twi_clk");
> >+i2c_at91->clk = clk_get(dev, NULL);
> > if (IS_ERR(i2c_at91->clk)) {
> > dev_err(dev, "no clock defined\n");
> > rc = -ENODEV;
> >@@ -429,6 +478,7 @@ static struct driver_d at91_twi_driver = {
> > .name = "at91-twi",
> > .probe = at91_twi_probe,
> > .id_table = at91_twi_devtypes,
> >+.of_compatible = DRV_OF_COMPAT(at91_twi_dt_ids),
> > };
> > device_platform_driver(at91_twi_driver);
> >
> >
>
> Best Regards,
> Bo Shen
>
Thanks for you review,
Raphaël Poggi
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Re: [PATCH V2 2/2] at91sam9g45: clock: add i2c clocks
Hi,
I have used CLKDEV_CON_DEV_ID because it is like that in Linux, but ok
I will replace it by CLKDEV_DEV_ID.
Btw, can you explain me why in Linux it's CLKDEV_CON_DEV_ID ? (just by
curiosity)
Thanks,
Raphaël Poggi
2014-08-04 11:17 GMT+02:00 Bo Shen :
> Hi Raphaël Poggi,
>
>
> On 08/04/2014 04:31 PM, Raphaël Poggi wrote:
>>
>> Add the device tree and non device tree at91 i2c clocks.
>>
>> Signed-off-by: Raphaël Poggi
>> ---
>> arch/arm/mach-at91/at91sam9g45.c |4
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm/mach-at91/at91sam9g45.c
>> b/arch/arm/mach-at91/at91sam9g45.c
>> index f6031f0..d0f950c 100644
>> --- a/arch/arm/mach-at91/at91sam9g45.c
>> +++ b/arch/arm/mach-at91/at91sam9g45.c
>> @@ -192,6 +192,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
>> CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk),
>> CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
>> CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
>> + CLKDEV_CON_DEV_ID(NULL, "at91-twi0", &twi0_clk),
>
>
> s/CLKDEV_CON_DEV_ID/CLKDEV_DEV_ID (also for the following).
>
> the DEV_ID should be presented in the id_table in the driver.
>
>
>> + CLKDEV_CON_DEV_ID(NULL, "at91-twi1", &twi1_clk),
>> + CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
>> + CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
>> CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk),
>> CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk),
>> CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
>>
>
> Best Regards,
> Bo Shen
>
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Re: [PATCH V2 0/2] Add device tree support of i2c Atmel driver
Hi, I have tested it on a custom board which use a sam9m10 and it worked... Tell me more when we have found something suspicious. Thanks for your test. Raphaël Poggi 2014-08-04 11:11 GMT+02:00 Bo Shen : > Hi Raphaël Poggi, > I try to manage to make the i2c driver work, however, failed for non > device tree. > I am still checking it. However, some comments for the patches. > > Best Regards, > Bo Shen > > > On 08/04/2014 04:31 PM, Raphaël Poggi wrote: >> >> Change since v1: >> * Squash the commit [1] which adds the sam9x5 config. >> >> This patcheset adds the device tree support for i2c Atmel driver and the >> corresping clocks >> for the at91sam9g45 device. >> >> Raphaël Poggi (2) : >> (1) i2c: at91: add support of device tree >> (2) at91sam9g45: clock: add i2c clocks >> >> arch/arm/mach-at91/at91sam9g45.c |4 +++ >> drivers/i2c/busses/i2c-at91.c| 66 >> +- >> 2 files changed, 62 insertions(+), 8 deletions(-) >> >> [1]: http://lists.infradead.org/pipermail/barebox/2014-August/020493.html > > > Best Regards, > Bo Shen > > > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH V2 0/2] Add device tree support of i2c Atmel driver
Change since v1: * Squash the commit [1] which adds the sam9x5 config. This patcheset adds the device tree support for i2c Atmel driver and the corresping clocks for the at91sam9g45 device. Raphaël Poggi (2) : (1) i2c: at91: add support of device tree (2) at91sam9g45: clock: add i2c clocks arch/arm/mach-at91/at91sam9g45.c |4 +++ drivers/i2c/busses/i2c-at91.c| 66 +- 2 files changed, 62 insertions(+), 8 deletions(-) [1]: http://lists.infradead.org/pipermail/barebox/2014-August/020493.html ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH V2 1/2] i2c: at91: add support of device tree
Signed-off-by: Raphaël Poggi
---
drivers/i2c/busses/i2c-at91.c | 66 -
1 file changed, 58 insertions(+), 8 deletions(-)
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 399f6a9..944a8b3 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -346,6 +346,12 @@ static struct at91_twi_pdata at91sam9g10_config = {
.has_unre_flag = false,
};
+static struct at91_twi_pdata at91sam9x5_config = {
+ .clk_max_div = 7,
+ .clk_offset = 4,
+ .has_unre_flag = false,
+};
+
static struct platform_device_id at91_twi_devtypes[] = {
{
.name = "i2c-at91rm9200",
@@ -367,20 +373,63 @@ static struct platform_device_id at91_twi_devtypes[] = {
}
};
+static struct of_device_id at91_twi_dt_ids[] = {
+ {
+ .compatible = "atmel,at91rm9200-i2c",
+ .data = (unsigned long) &at91rm9200_config,
+ } , {
+ .compatible = "atmel,at91sam9260-i2c",
+ .data = (unsigned long) &at91sam9260_config,
+ } , {
+ .compatible = "atmel,at91sam9261-i2c",
+ .data = (unsigned long) &at91sam9261_config,
+ } , {
+ .compatible = "atmel,at91sam9g20-i2c",
+ .data = (unsigned long) &at91sam9g20_config,
+ } , {
+ .compatible = "atmel,at91sam9g10-i2c",
+ .data = (unsigned long) &at91sam9g10_config,
+ }, {
+ .compatible = "atmel,at91sam9x5-i2c",
+ .data = (unsigned long) &at91sam9x5_config,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct at91_twi_pdata *at91_twi_get_driver_data(struct device_d *dev)
+{
+struct at91_twi_pdata *i2c_data = NULL;
+int rc;
+
+if (dev->device_node) {
+ const struct of_device_id *match;
+ match = of_match_node(at91_twi_dt_ids, dev->device_node);
+ if (!match)
+ i2c_data = NULL;
+ else
+ i2c_data = (struct at91_twi_pdata *)match->data;
+}
+else {
+ rc = dev_get_drvdata(dev, (unsigned long *)&i2c_data);
+ if (rc)
+ i2c_data = NULL;
+}
+
+return i2c_data;
+}
+
static int at91_twi_probe(struct device_d *dev)
{
struct at91_twi_dev *i2c_at91;
- struct at91_twi_pdata *i2c_data;
- int rc;
+ int rc = 0;
u32 bus_clk_rate;
i2c_at91 = xzalloc(sizeof(struct at91_twi_dev));
- rc = dev_get_drvdata(dev, (unsigned long *)&i2c_data);
- if (rc)
- goto out_free;
-
- i2c_at91->pdata = i2c_data;
+ i2c_at91->pdata = at91_twi_get_driver_data(dev);
+ if (!i2c_at91->pdata)
+ goto out_free;
i2c_at91->base = dev_request_mem_region(dev, 0);
if (!i2c_at91->base) {
@@ -389,7 +438,7 @@ static int at91_twi_probe(struct device_d *dev)
goto out_free;
}
- i2c_at91->clk = clk_get(dev, "twi_clk");
+ i2c_at91->clk = clk_get(dev, NULL);
if (IS_ERR(i2c_at91->clk)) {
dev_err(dev, "no clock defined\n");
rc = -ENODEV;
@@ -429,6 +478,7 @@ static struct driver_d at91_twi_driver = {
.name = "at91-twi",
.probe = at91_twi_probe,
.id_table = at91_twi_devtypes,
+ .of_compatible = DRV_OF_COMPAT(at91_twi_dt_ids),
};
device_platform_driver(at91_twi_driver);
--
1.7.9.5
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[PATCH V2 2/2] at91sam9g45: clock: add i2c clocks
Add the device tree and non device tree at91 i2c clocks.
Signed-off-by: Raphaël Poggi
---
arch/arm/mach-at91/at91sam9g45.c |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index f6031f0..d0f950c 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -192,6 +192,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
+ CLKDEV_CON_DEV_ID(NULL, "at91-twi0", &twi0_clk),
+ CLKDEV_CON_DEV_ID(NULL, "at91-twi1", &twi1_clk),
+ CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
+ CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk),
CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk),
CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
--
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Re: [PATCH 0/2] Add initial support of at91sam9m10g45ek device tree
Ah yes, sorry. I'll send a v2 to correct this. Thanks, Raphaël 2014-08-01 18:59 GMT+02:00 Sascha Hauer : > On Fri, Aug 01, 2014 at 03:42:16PM +0200, Raphael Poggi wrote: >> This patchset add the initial support of the at91sam9m10g45ek device tree, >> and >> add the pinctrl device tree binding file. >> >> Raphaël Poggi (2) : >> (1) dt-bindings: pinctrl: add at91 file >> (2) dts: at91: initial support of at91sam9m10g45ek dts >> >> >> arch/arm/dts/Makefile |1 + >> arch/arm/dts/at91sam9g45.dtsi | 105 >> >> arch/arm/dts/at91sam9m10g45ek.dts | 22 >> include/dt-bindings/pinctrl/at91.h | 35 > > We already have all these files in the tree. You shouldn't have to > duplicate them. Just create a stub under arch/arm/dts/ including the > real files. > > Sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0| > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- | > > ___ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH] of_mtd: add soft_bch and hw_oob_first ecc modes
Signed-off-by: Raphaël Poggi
---
drivers/of/of_mtd.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/of/of_mtd.c b/drivers/of/of_mtd.c
index 239f1f9..46eef67 100644
--- a/drivers/of/of_mtd.c
+++ b/drivers/of/of_mtd.c
@@ -20,6 +20,8 @@ static const char *nand_ecc_modes[] = {
[NAND_ECC_SOFT] = "soft",
[NAND_ECC_HW] = "hw",
[NAND_ECC_HW_SYNDROME] = "hw_syndrome",
+ [NAND_ECC_HW_OOB_FIRST] = "hw_oob_first",
+ [NAND_ECC_SOFT_BCH] = "soft_bch",
};
/**
--
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[PATCH] i2c: at91: add at91sam9x5 config
Signed-off-by: Raphaël Poggi
---
drivers/i2c/busses/i2c-at91.c |6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 399f6a9..4aa4e4e 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -346,6 +346,12 @@ static struct at91_twi_pdata at91sam9g10_config = {
.has_unre_flag = false,
};
+static struct at91_twi_pdata at91sam9x5_config = {
+ .clk_max_div = 7,
+ .clk_offset = 4,
+ .has_unre_flag = false,
+};
+
static struct platform_device_id at91_twi_devtypes[] = {
{
.name = "i2c-at91rm9200",
--
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[PATCH 0/2] Add atmel pinctrl driver
This patchset add atmel pinctrl/gpio driver and the corresponding clocks for the at91sam9g45 device. The pinctrl driver also include the gpio driver (like in linux) because the gpio and pinctrl parts share same structures. Raphaël Poggi (2) : (1) pinctrl: at91: add pinctrl driver (2) at91sam9g45: add device tree gpio clocks arch/arm/mach-at91/at91sam9g45.c |5 + drivers/pinctrl/Kconfig |6 + drivers/pinctrl/Makefile |1 + drivers/pinctrl/pinctrl-at91.c | 529 ++ drivers/pinctrl/pinctrl-at91.h | 148 +++ 5 files changed, 689 insertions(+) ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 2/2] at91sam9g45: add device tree gpio clocks
Signed-off-by: Raphaël Poggi
---
arch/arm/mach-at91/at91sam9g45.c |5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 9a50deb..f6031f0 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -197,6 +197,11 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
CLKDEV_DEV_ID("at91rm9200-gpio3", &pioDE_clk),
CLKDEV_DEV_ID("at91rm9200-gpio4", &pioDE_clk),
+ CLKDEV_CON_DEV_ID(NULL, "f200.gpio", &pioA_clk),
+ CLKDEV_CON_DEV_ID(NULL, "f400.gpio", &pioB_clk),
+ CLKDEV_CON_DEV_ID(NULL, "f600.gpio", &pioC_clk),
+ CLKDEV_CON_DEV_ID(NULL, "f800.gpio", &pioDE_clk),
+ CLKDEV_CON_DEV_ID(NULL, "fa00.gpio", &pioDE_clk),
CLKDEV_DEV_ID("at91-pit", &mck),
CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk),
};
--
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[PATCH 1/2] pinctrl: at91: add pinctrl driver
This driver is based on mach-at91/gpio.c and linux pinctrl driver.
The driver contains the gpio and pinctrl parts (like in linux) because the two
parts
share some structures and logics.
Signed-off-by: Raphaël Poggi
---
drivers/pinctrl/Kconfig|6 +
drivers/pinctrl/Makefile |1 +
drivers/pinctrl/pinctrl-at91.c | 529
drivers/pinctrl/pinctrl-at91.h | 148 +++
4 files changed, 684 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-at91.c
create mode 100644 drivers/pinctrl/pinctrl-at91.h
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index dffaa4e..ce55c7b 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -7,6 +7,12 @@ config PINCTRL
from the devicetree. Legacy drivers here may not need this core
support but instead provide their own SoC specific APIs
+config PINCTRL_AT91
+ select PINCTRL
+ bool
+ help
+ The pinmux controller found on AT91 SoCs.
+
config PINCTRL_IMX_IOMUX_V1
select PINCTRL if OFDEVICE
bool
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 566ba11..3ea8649 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -1,4 +1,5 @@
obj-$(CONFIG_PINCTRL) += pinctrl.o
+obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_IMX_IOMUX_V1) += imx-iomux-v1.o
obj-$(CONFIG_PINCTRL_IMX_IOMUX_V2) += imx-iomux-v2.o
obj-$(CONFIG_PINCTRL_IMX_IOMUX_V3) += imx-iomux-v3.o
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
new file mode 100644
index 000..a92a898
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -0,0 +1,529 @@
+/*
+ * Copyright (C) 2005 HP Labs
+ * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD
+ * Copyright (C) 2014 Raphaël Poggi
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include
+
+#include "pinctrl-at91.h"
+
+struct at91_pinctrl {
+struct pinctrl_device pctl;
+struct at91_pinctrl_mux_ops*ops;
+};
+
+struct at91_gpio_chip {
+ struct gpio_chipchip;
+ void __iomem*regbase; /* PIO bank virtual address */
+ struct at91_pinctrl_mux_ops *ops; /* ops */
+};
+
+enum at91_mux {
+ AT91_MUX_GPIO = 0,
+ AT91_MUX_PERIPH_A = 1,
+ AT91_MUX_PERIPH_B = 2,
+ AT91_MUX_PERIPH_C = 3,
+ AT91_MUX_PERIPH_D = 4,
+};
+
+#define MAX_GPIO_BANKS 5
+#define to_at91_pinctrl(c) container_of(c, struct at91_pinctrl, pctl);
+#define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
+
+#define PULL_UP (1 << 0)
+#define MULTI_DRIVE (1 << 1)
+#define DEGLITCH(1 << 2)
+#define PULL_DOWN (1 << 3)
+#define DIS_SCHMIT (1 << 4)
+#define DEBOUNCE(1 << 16)
+#define DEBOUNCE_VAL_SHIFT 17
+#define DEBOUNCE_VAL(0x3fff << DEBOUNCE_VAL_SHIFT)
+
+static int gpio_banks = 0;
+
+static struct at91_gpio_chip gpio_chip[MAX_GPIO_BANKS];
+
+static inline void __iomem *pin_to_controller(struct at91_pinctrl *info,
unsigned pin)
+{
+ pin /= MAX_NB_GPIO_PER_BANK;
+ if (likely(pin < gpio_banks))
+ return gpio_chip[pin].regbase;
+
+ return NULL;
+}
+
+/**
+ * struct at91_pinctrl_mux_ops - describes an At91 mux ops group
+ * on new IP with support for periph C and D the way to mux in
+ * periph A and B has changed
+ * So provide the right call back
+ * if not present means the IP does not support it
+ * @get_periph: return the periph mode configured
+ * @mux_A_periph: mux as periph A
+ * @mux_B_periph: mux as periph B
+ * @mux_C_periph: mux as periph C
+ * @mux_D_periph: mux as periph D
+ * @set_deglitch: enable/disable deglitch
+ * @set_debounce: enable/disable debounce
+ * @set_pulldown: enable/disable pulldown
+ * @disable_schmitt_trig: disable schmitt trigger
+ */
+struct at91_pinctrl_mux_ops {
+ enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_A_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_B_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_C_periph)(void __iomem *pio, unsigned mask);
+ void (*mux_D_periph)(void __iomem *pio, unsigned mask);
+ bool (*get_d
[PATCH 4/5] mtd: atmel_nand: retrieve ecc_mode from pdata
By retrieving the ecc_mode from pdata we can use the same code for device tree
and
non device tree probing. Which was not possible before, because ecc_mode was
arbitrarily set to
NAND_ECC_SOFT.
Signed-off-by: Raphaël Poggi
---
drivers/mtd/nand/atmel_nand.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index eba7125..82bee92 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1208,7 +1208,7 @@ static int __init atmel_nand_probe(struct device_d *dev)
goto err_no_card;
}
else {
- pdata = dev->platform_data;
+ memcpy(host->board, dev->platform_data, sizeof(struct
atmel_nand_data));
}
nand_chip->priv = host; /* link the private data structures */
@@ -1257,7 +1257,7 @@ static int __init atmel_nand_probe(struct device_d *dev)
}
}
- nand_chip->ecc.mode = NAND_ECC_SOFT;
+ nand_chip->ecc.mode = pdata->ecc_mode;
if (IS_ENABLED(CONFIG_NAND_ECC_HW) &&
pdata->ecc_mode == NAND_ECC_HW) {
--
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[PATCH 5/5] board: atmel: initialise ecc_mode
This commit initialise the ecc_mode (NAND_ECC_SOFT) on atmel board init which
missing it.
Signed-off-by: Raphaël Poggi
---
arch/arm/boards/at91sam9260ek/init.c|1 +
arch/arm/boards/at91sam9261ek/init.c|1 +
arch/arm/boards/at91sam9263ek/init.c|1 +
arch/arm/boards/at91sam9m10g45ek/init.c |1 +
arch/arm/boards/at91sam9m10ihd/init.c |1 +
5 files changed, 5 insertions(+)
diff --git a/arch/arm/boards/at91sam9260ek/init.c
b/arch/arm/boards/at91sam9260ek/init.c
index 1298dde..76e0195 100644
--- a/arch/arm/boards/at91sam9260ek/init.c
+++ b/arch/arm/boards/at91sam9260ek/init.c
@@ -51,6 +51,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PC13,
.enable_pin = AT91_PIN_PC14,
+ .ecc_mode = NAND_ECC_SOFT,
.on_flash_bbt = 1,
};
diff --git a/arch/arm/boards/at91sam9261ek/init.c
b/arch/arm/boards/at91sam9261ek/init.c
index 9ebc16a..7b8ce98 100644
--- a/arch/arm/boards/at91sam9261ek/init.c
+++ b/arch/arm/boards/at91sam9261ek/init.c
@@ -46,6 +46,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PC15,
.enable_pin = AT91_PIN_PC14,
+ .ecc_mode = NAND_ECC_SOFT,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
.bus_width_16 = 1,
#else
diff --git a/arch/arm/boards/at91sam9263ek/init.c
b/arch/arm/boards/at91sam9263ek/init.c
index 889b4c2..c8a9d5c 100644
--- a/arch/arm/boards/at91sam9263ek/init.c
+++ b/arch/arm/boards/at91sam9263ek/init.c
@@ -43,6 +43,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PA22,
.enable_pin = AT91_PIN_PD15,
+ .ecc_mode = NAND_ECC_SOFT,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
.bus_width_16 = 1,
#else
diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c
b/arch/arm/boards/at91sam9m10g45ek/init.c
index 6503ebb..cdd7806 100644
--- a/arch/arm/boards/at91sam9m10g45ek/init.c
+++ b/arch/arm/boards/at91sam9m10g45ek/init.c
@@ -67,6 +67,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PC8,
.enable_pin = AT91_PIN_PC14,
+ .ecc_mode = NAND_ECC_SOFT,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
.bus_width_16 = 1,
#else
diff --git a/arch/arm/boards/at91sam9m10ihd/init.c
b/arch/arm/boards/at91sam9m10ihd/init.c
index fc37af4..a432e5c 100644
--- a/arch/arm/boards/at91sam9m10ihd/init.c
+++ b/arch/arm/boards/at91sam9m10ihd/init.c
@@ -44,6 +44,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PC15,
.enable_pin = AT91_PIN_PC14,
+ .ecc_mode = NAND_ECC_SOFT,
.bus_width_16 = 0,
.on_flash_bbt = 1,
};
--
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[PATCH 1/5] mtd: atmel_nand: add support for device tree
Signed-off-by: Raphaël Poggi
---
drivers/mtd/nand/atmel_nand.c | 108 -
1 file changed, 107 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index 337e225..b7b0e3a 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -28,6 +28,10 @@
#include
#include
+#include
+#include
+#include
+
#include
#include
@@ -1038,6 +1042,89 @@ static void atmel_nand_hwctl(struct mtd_info *mtd, int
mode)
#endif
}
+static int atmel_nand_of_init(struct atmel_nand_host *host, struct device_node
*np)
+{
+ u32 val;
+ u32 offset[2];
+ int ecc_mode;
+ struct atmel_nand_data *board = host->board;
+ enum of_gpio_flags flags = 0;
+
+ if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
+ if (val >= 32) {
+ dev_err(host->dev, "invalid addr-offset %u\n", val);
+ return -EINVAL;
+ }
+ board->ale = val;
+ }
+
+ if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
+ if (val >= 32) {
+ dev_err(host->dev, "invalid cmd-offset %u\n", val);
+ return -EINVAL;
+ }
+ board->cle = val;
+ }
+
+ ecc_mode = of_get_nand_ecc_mode(np);
+
+ board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
+
+ board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
+
+ if (of_get_nand_bus_width(np) == 16)
+ board->bus_width_16 = 1;
+
+ board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
+ board->enable_pin = of_get_gpio(np, 1);
+ board->det_pin = of_get_gpio(np, 2);
+
+ board->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
+
+ if (!(board->ecc_mode == NAND_ECC_HW) || !board->has_pmecc)
+ return 0; /* Not using PMECC */
+
+ /* use PMECC, get correction capability, sector size and lookup
+ * table offset.
+ * If correction bits and sector size are not specified, then
+ * find
+ * them from NAND ONFI parameters.
+ */
+ if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
+ if ((val != 2) && (val != 4) && (val != 8) && (val != 12) && (val
!= 24)) {
+ dev_err(host->dev, "Unsupported PMECC correction capability: %d"
+ " should be 2, 4, 8, 12 or 24\n", val);
+ return -EINVAL;
+ }
+
+ board->pmecc_corr_cap = (u8)val;
+ }
+
+ if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
+ if ((val != 512) && (val != 1024)) {
+ dev_err(host->dev, "Unsupported PMECC sector size: %d"
+ " should be 512 or 1024 bytes\n", val);
+ return -EINVAL;
+ }
+
+ board->pmecc_sector_size = (u16)val;
+ }
+
+ if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
offset, 2) != 0) {
+ dev_err(host->dev, "Cannot get PMECC lookup table offset\n");
+ return -EINVAL;
+ }
+
+ if (!offset[0] && !offset[1]) {
+ dev_err(host->dev, "Invalid PMECC lookup table offset\n");
+ return -EINVAL;
+ }
+
+ board->pmecc_lookup_table_offset = (board->pmecc_sector_size == 512) ?
offset[0] : offset[1];
+
+ return 0;
+}
+
static int atmel_hw_nand_init_params(struct device_d *dev,
struct atmel_nand_host *host)
{
@@ -1093,7 +1180,7 @@ static int atmel_hw_nand_init_params(struct device_d *dev,
*/
static int __init atmel_nand_probe(struct device_d *dev)
{
- struct atmel_nand_data *pdata = dev->platform_data;
+ struct atmel_nand_data *pdata;
struct atmel_nand_host *host;
struct mtd_info *mtd;
struct nand_chip *nand_chip;
@@ -1104,6 +1191,10 @@ static int __init atmel_nand_probe(struct device_d *dev)
if (!host)
return -ENOMEM;
+ pdata = kzalloc(sizeof(struct atmel_nand_data), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
host->io_base = dev_request_mem_region(dev, 0);
mtd = &host->mtd;
@@ -,6 +1202,15 @@ static int __init atmel_nand_probe(struct device_d *dev)
host->board = pdata;
host->dev = dev;
+ if (dev->device_node) {
+ res = atmel_nand_of_init(host, dev->device_node);
+ if (res)
+ goto err_no_card;
+ }
+ else {
+ pdata = dev->platform_data;
+ }
+
nand_chip->priv = host; /* link the pri
[PATCH 0/5] Add device tree support of Atmel NAND driver
This patchset adds the device tree support for the Atmel NAND driver. The first patch adds the device tree in the atmel_nand driver. The second patch removes the NAND_ATMEL_PMECC config. With this removal we can manage in a better way the device tree / non device tree probing of the driver, because the plateform data and device tree share the same structure member and logics. The third patch adds the has_pmecc on boards which need it. The fourth patch retrieves the ecc_mode from the plateform data and remove this code: nand_chip->ecc.mode = NAND_ECC_SOFT; which arbitrary sets the ecc.mode to NAND_ECC_SOFT and changes the value depending of the config and plateform data. With this, we can use the same logics for device tree and non device tree probing of the driver. The fifth patch adds the ecc_mode on boards which are missing it (boards which use NAND_ECC_SOFT). Raphaël Poggi (5) : (1) mtd: atmel_nand: add support for device tree (2) mtd: nand: remove NAND_ATMEL_PMECC (3) board: atmel: initialise the has_pmecc member (4) mtd: atmel_nand: retrieve ecc_mode from pdata (5) board: atmel: initialise ecc_mode arch/arm/boards/at91sam9260ek/init.c|1 + arch/arm/boards/at91sam9261ek/init.c|1 + arch/arm/boards/at91sam9263ek/init.c|1 + arch/arm/boards/at91sam9m10g45ek/init.c |1 + arch/arm/boards/at91sam9m10ihd/init.c |1 + arch/arm/boards/at91sam9n12ek/init.c|1 + arch/arm/boards/at91sam9x5ek/init.c |1 + arch/arm/boards/sama5d3_xplained/init.c |1 + arch/arm/boards/sama5d3xek/init.c |1 + arch/arm/mach-at91/include/mach/board.h |1 + drivers/mtd/nand/Kconfig|8 --- drivers/mtd/nand/atmel_nand.c | 112 ++- 12 files changed, 119 insertions(+), 11 deletions(-) ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 3/5] board: atmel: initialise the has_pmecc member
---
arch/arm/boards/at91sam9n12ek/init.c|1 +
arch/arm/boards/at91sam9x5ek/init.c |1 +
arch/arm/boards/sama5d3_xplained/init.c |1 +
arch/arm/boards/sama5d3xek/init.c |1 +
4 files changed, 4 insertions(+)
diff --git a/arch/arm/boards/at91sam9n12ek/init.c
b/arch/arm/boards/at91sam9n12ek/init.c
index a206d6b..818a598 100644
--- a/arch/arm/boards/at91sam9n12ek/init.c
+++ b/arch/arm/boards/at91sam9n12ek/init.c
@@ -47,6 +47,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PD5,
.enable_pin = AT91_PIN_PD4,
+ .has_pmecc = 1,
.ecc_mode = NAND_ECC_HW,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 2,
diff --git a/arch/arm/boards/at91sam9x5ek/init.c
b/arch/arm/boards/at91sam9x5ek/init.c
index 62e5652..183ddc7 100644
--- a/arch/arm/boards/at91sam9x5ek/init.c
+++ b/arch/arm/boards/at91sam9x5ek/init.c
@@ -57,6 +57,7 @@ static struct atmel_nand_data nand_pdata = {
.det_pin= -EINVAL,
.rdy_pin= AT91_PIN_PD5,
.enable_pin = AT91_PIN_PD4,
+ .has_pmecc = 1,
.ecc_mode = NAND_ECC_HW,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 2,
diff --git a/arch/arm/boards/sama5d3_xplained/init.c
b/arch/arm/boards/sama5d3_xplained/init.c
index ae18863..b182802 100644
--- a/arch/arm/boards/sama5d3_xplained/init.c
+++ b/arch/arm/boards/sama5d3_xplained/init.c
@@ -48,6 +48,7 @@ static struct atmel_nand_data nand_pdata = {
.rdy_pin= -EINVAL,
.enable_pin = -EINVAL,
.ecc_mode = NAND_ECC_HW,
+ .has_pmecc = 1,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 4,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
diff --git a/arch/arm/boards/sama5d3xek/init.c
b/arch/arm/boards/sama5d3xek/init.c
index 743197f..49d2b37 100644
--- a/arch/arm/boards/sama5d3xek/init.c
+++ b/arch/arm/boards/sama5d3xek/init.c
@@ -63,6 +63,7 @@ static struct atmel_nand_data nand_pdata = {
.rdy_pin= -EINVAL,
.enable_pin = -EINVAL,
.ecc_mode = NAND_ECC_HW,
+ .has_pmecc = 1,
.pmecc_sector_size = 512,
.pmecc_corr_cap = 4,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
--
1.7.9.5
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[PATCH 2/5] mtd: nand: remove NAND_ATMEL_PMECC
By removing this CONFIG_, we can use a structure member to retrieve the config,
either through the plateform data or through the device tree. So we can handle
cases
when the driver is probed using device tree or not.
Signed-off-by: Raphaël Poggi
---
arch/arm/mach-at91/include/mach/board.h |1 +
drivers/mtd/nand/Kconfig|8
drivers/mtd/nand/atmel_nand.c |2 +-
3 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/board.h
b/arch/arm/mach-at91/include/mach/board.h
index aa0fdae..e2307ed 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -63,6 +63,7 @@ struct atmel_nand_data {
u8 bus_width_16; /* buswidth is 16 bit */
u8 ecc_mode; /* NAND_ECC_* */
u8 on_flash_bbt; /* Use flash based bbt */
+ u8 has_pmecc; /* Use PMECC */
u8 bus_on_d0;
u8 pmecc_corr_cap;
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 04fe3c8..d49eae3 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -95,14 +95,6 @@ config NAND_ATMEL
prompt "Atmel (AT91SAM9xxx) NAND driver"
depends on ARCH_AT91
-config NAND_ATMEL_PMECC
- bool
- prompt "PMECC support"
- depends on NAND_ATMEL
- select NAND_ECC_HW
- help
- Support for PMECC present on the SoC sam9x5 and sam9n12
-
config NAND_S3C24XX
bool
prompt "Samsung S3C24XX NAND driver"
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index b7b0e3a..eba7125 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1319,7 +1319,7 @@ static int __init atmel_nand_probe(struct device_d *dev)
if (IS_ENABLED(CONFIG_NAND_ECC_HW) &&
nand_chip->ecc.mode == NAND_ECC_HW) {
- if (IS_ENABLED(CONFIG_NAND_ATMEL_PMECC))
+ if (pdata->has_pmecc)
res = atmel_pmecc_nand_init_params(dev, host);
else
res = atmel_hw_nand_init_params(dev, host);
--
1.7.9.5
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[PATCH 2/2] at91sam9g45: clock: add i2c clocks
Add the device tree and non device tree at91 i2c clocks.
Signed-off-by: Raphaël Poggi
---
arch/arm/mach-at91/at91sam9g45.c |4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index f6031f0..d0f950c 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -192,6 +192,10 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk),
+ CLKDEV_CON_DEV_ID(NULL, "at91-twi0", &twi0_clk),
+ CLKDEV_CON_DEV_ID(NULL, "at91-twi1", &twi1_clk),
+ CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
+ CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk),
CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk),
CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk),
--
1.7.9.5
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[PATCH 0/2] Add device tree support of i2c Atmel driver
This patcheset adds the device tree support for i2c Atmel driver and the corresping clocks for the at91sam9g45 device. Raphaël Poggi (2) : (1) i2c: at91: add support of device tree (2) at91sam9g45: clock: add i2c clocks arch/arm/mach-at91/at91sam9g45.c |4 +++ drivers/i2c/busses/i2c-at91.c| 60 +- 2 files changed, 56 insertions(+), 8 deletions(-) ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH 1/2] i2c: at91: add support of device tree
Signed-off-by: Raphaël Poggi
---
drivers/i2c/busses/i2c-at91.c | 60 +++--
1 file changed, 52 insertions(+), 8 deletions(-)
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index 4aa4e4e..944a8b3 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -373,20 +373,63 @@ static struct platform_device_id at91_twi_devtypes[] = {
}
};
+static struct of_device_id at91_twi_dt_ids[] = {
+ {
+ .compatible = "atmel,at91rm9200-i2c",
+ .data = (unsigned long) &at91rm9200_config,
+ } , {
+ .compatible = "atmel,at91sam9260-i2c",
+ .data = (unsigned long) &at91sam9260_config,
+ } , {
+ .compatible = "atmel,at91sam9261-i2c",
+ .data = (unsigned long) &at91sam9261_config,
+ } , {
+ .compatible = "atmel,at91sam9g20-i2c",
+ .data = (unsigned long) &at91sam9g20_config,
+ } , {
+ .compatible = "atmel,at91sam9g10-i2c",
+ .data = (unsigned long) &at91sam9g10_config,
+ }, {
+ .compatible = "atmel,at91sam9x5-i2c",
+ .data = (unsigned long) &at91sam9x5_config,
+ }, {
+ /* sentinel */
+ }
+};
+
+static struct at91_twi_pdata *at91_twi_get_driver_data(struct device_d *dev)
+{
+struct at91_twi_pdata *i2c_data = NULL;
+int rc;
+
+if (dev->device_node) {
+ const struct of_device_id *match;
+ match = of_match_node(at91_twi_dt_ids, dev->device_node);
+ if (!match)
+ i2c_data = NULL;
+ else
+ i2c_data = (struct at91_twi_pdata *)match->data;
+}
+else {
+ rc = dev_get_drvdata(dev, (unsigned long *)&i2c_data);
+ if (rc)
+ i2c_data = NULL;
+}
+
+return i2c_data;
+}
+
static int at91_twi_probe(struct device_d *dev)
{
struct at91_twi_dev *i2c_at91;
- struct at91_twi_pdata *i2c_data;
- int rc;
+ int rc = 0;
u32 bus_clk_rate;
i2c_at91 = xzalloc(sizeof(struct at91_twi_dev));
- rc = dev_get_drvdata(dev, (unsigned long *)&i2c_data);
- if (rc)
- goto out_free;
-
- i2c_at91->pdata = i2c_data;
+ i2c_at91->pdata = at91_twi_get_driver_data(dev);
+ if (!i2c_at91->pdata)
+ goto out_free;
i2c_at91->base = dev_request_mem_region(dev, 0);
if (!i2c_at91->base) {
@@ -395,7 +438,7 @@ static int at91_twi_probe(struct device_d *dev)
goto out_free;
}
- i2c_at91->clk = clk_get(dev, "twi_clk");
+ i2c_at91->clk = clk_get(dev, NULL);
if (IS_ERR(i2c_at91->clk)) {
dev_err(dev, "no clock defined\n");
rc = -ENODEV;
@@ -435,6 +478,7 @@ static struct driver_d at91_twi_driver = {
.name = "at91-twi",
.probe = at91_twi_probe,
.id_table = at91_twi_devtypes,
+ .of_compatible = DRV_OF_COMPAT(at91_twi_dt_ids),
};
device_platform_driver(at91_twi_driver);
--
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at91: device tree
Hi all ! In barebox, atmel AT91 boards don't have device tree support(neither atmel drivers like: atmel_nand). I am currently working on adding device tree support especially on at91sam9m10g45ek board (the only atmel board, I have for testing) and corresponding drivers (i2c, nand, spi, etc...). I wonder if barebox community is interested to add device tree support for atmel or if there is already somebody who works on it. Thanks, Raphaël Poggi ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
[PATCH v2] i2c: add Atmel AT91 driver
Signed-off-by: Raphaël Poggi
---
drivers/i2c/busses/Kconfig|4 +
drivers/i2c/busses/Makefile |1 +
drivers/i2c/busses/i2c-at91.c | 437 +
3 files changed, 442 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-at91.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 370abb0..5b75449 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -12,6 +12,10 @@ config I2C_GPIO
This is a very simple bitbanging I2C driver utilizing the
arch-neutral GPIO API to control the SCL and SDA lines.
+config I2C_AT91
+ bool "AT91 I2C Master driver"
+ depends on ARCH_AT91
+
config I2C_IMX
bool "MPC85xx/i.MX I2C Master driver"
depends on (ARCH_IMX && !ARCH_IMX1) || ARCH_MPC85XX
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 9823d1b..cc72b7c 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_I2C_AT91) += i2c-at91.o
obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
obj-$(CONFIG_I2C_IMX) += i2c-imx.o
obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
new file mode 100644
index 000..399f6a9
--- /dev/null
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -0,0 +1,437 @@
+/*
+ * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
+ *
+ * Copyright (C) 2011 Weinmann Medical GmbH
+ * Author: Nikolaus Voss
+ *
+ * Evolved from original work by:
+ * Copyright (C) 2004 Rick Bronson
+ * Converted to 2.6 by Andrew Victor
+ *
+ * Borrowed heavily from original work by:
+ * Copyright (C) 2000 Philip Edelbrock
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DEFAULT_TWI_CLK_HZ 10 /* max 400 Kbits/s */
+#define AT91_I2C_TIMEOUT (100 * MSECOND) /* transfer timeout */
+#define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if
transfer size is bigger than this threshold */
+
+/* AT91 TWI register definitions */
+#defineAT91_TWI_CR 0x /* Control Register */
+#defineAT91_TWI_START 0x0001 /* Send a Start Condition */
+#defineAT91_TWI_STOP 0x0002 /* Send a Stop Condition */
+#defineAT91_TWI_MSEN 0x0004 /* Master Transfer Enable */
+#defineAT91_TWI_SVDIS 0x0020 /* Slave Transfer Disable */
+#defineAT91_TWI_QUICK 0x0040 /* SMBus quick command */
+#defineAT91_TWI_SWRST 0x0080 /* Software Reset */
+
+#defineAT91_TWI_MMR0x0004 /* Master Mode Register */
+#defineAT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size
*/
+#defineAT91_TWI_MREAD 0x1000 /* Master Read Direction */
+
+#defineAT91_TWI_IADR 0x000c /* Internal Address Register */
+
+#defineAT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg
*/
+
+#defineAT91_TWI_SR 0x0020 /* Status Register */
+#defineAT91_TWI_TXCOMP 0x0001 /* Transmission Complete */
+#defineAT91_TWI_RXRDY 0x0002 /* Receive Holding Register
Ready */
+#defineAT91_TWI_TXRDY 0x0004 /* Transmit Holding Register
Ready */
+
+#defineAT91_TWI_OVRE 0x0040 /* Overrun Error */
+#defineAT91_TWI_UNRE 0x0080 /* Underrun Error */
+#defineAT91_TWI_NACK 0x0100 /* Not Acknowledged */
+
+#defineAT91_TWI_IER0x0024 /* Interrupt Enable Register */
+#defineAT91_TWI_IDR0x0028 /* Interrupt Disable Register */
+#defineAT91_TWI_IMR0x002c /* Interrupt Mask Register */
+#defineAT91_TWI_RHR0x0030 /* Receive Holding Register */
+#defineAT91_TWI_THR0x0034 /* Transmit Holding Register */
+
+struct at91_twi_pdata {
+ unsigned clk_max_div;
+ unsigned clk_offset;
+ bool has_unre_flag;
+};
+
+struct at91_twi_dev {
+ struct device *dev;
+ void __iomem *base;
+ struct clk *clk;
+ u8 *buf;
+ size_t buf_len;
+ struct i2c_msg *msg;
+ unsigned imr;
+ unsigned transfer_status;
+ struct i2c_adapter adapter;
+ unsigned twi_cwgr_reg;
+ struct at91_twi_pdata *pdata;
+};
+
+#define to_at91_twi_dev(a) container_of(a, struct at91_twi_dev, adapter)
+
+static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
+{
+ return __raw_readl(dev->base + reg);
+}
+
+static void at91_twi_write(st
Re: [PATCH] i2c: add Atmel AT91 driver
Hi Sascha,
Thanks for your review, I'll correct these and send a v2.
Raphaël
2014-07-24 11:34 GMT+02:00 Sascha Hauer :
> Hi Raphaël,
>
> Looks mostly fine to me. Two small comments:
>
> On Wed, Jul 23, 2014 at 12:09:04PM -0700, Raphaël Poggi wrote:
>> +
>> +static int at91_twi_probe(struct device_d *dev)
>> +{
>> + struct at91_twi_dev *i2c_at91;
>> + struct at91_twi_pdata *i2c_data;
>> + int rc;
>> + u32 bus_clk_rate;
>> +
>> + i2c_at91 = kzalloc(sizeof(struct at91_twi_dev), GFP_KERNEL);
>> + if (!i2c_at91) {
>> + rc = -ENOMEM;
>> + goto out_free;
>> + }
>
> You can safely use xzalloc here and skip the result check.
>
>> +
>> + rc = dev_get_drvdata(dev, (unsigned long *)&i2c_data);
>> + if (rc)
>> + goto out_free;
>> +
>> + i2c_at91->pdata = i2c_data;
>> +
>> + i2c_at91->base = dev_request_mem_region(dev, 0);
>> + if (IS_ERR(i2c_at91->base))
>> + return PTR_ERR(i2c_at91->base);
>
> dev_request_mem_region returns NULL on error, not an error pointer.
>
> Sascha
>
> --
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[PATCH] i2c: add Atmel AT91 driver
Signed-off-by: Raphaël Poggi
---
drivers/i2c/busses/Kconfig| 4 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-at91.c | 438 ++
3 files changed, 443 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-at91.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 370abb0..5b75449 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -12,6 +12,10 @@ config I2C_GPIO
This is a very simple bitbanging I2C driver utilizing the
arch-neutral GPIO API to control the SCL and SDA lines.
+config I2C_AT91
+ bool "AT91 I2C Master driver"
+ depends on ARCH_AT91
+
config I2C_IMX
bool "MPC85xx/i.MX I2C Master driver"
depends on (ARCH_IMX && !ARCH_IMX1) || ARCH_MPC85XX
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 9823d1b..cc72b7c 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_I2C_AT91) += i2c-at91.o
obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
obj-$(CONFIG_I2C_IMX) += i2c-imx.o
obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
new file mode 100644
index 000..d743469
--- /dev/null
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -0,0 +1,438 @@
+/*
+ * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
+ *
+ * Copyright (C) 2011 Weinmann Medical GmbH
+ * Author: Nikolaus Voss
+ *
+ * Evolved from original work by:
+ * Copyright (C) 2004 Rick Bronson
+ * Converted to 2.6 by Andrew Victor
+ *
+ * Borrowed heavily from original work by:
+ * Copyright (C) 2000 Philip Edelbrock
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define DEFAULT_TWI_CLK_HZ 10 /* max 400 Kbits/s */
+#define AT91_I2C_TIMEOUT (100 * MSECOND) /* transfer timeout */
+#define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if
transfer size is bigger than this threshold */
+
+/* AT91 TWI register definitions */
+#defineAT91_TWI_CR 0x /* Control Register */
+#defineAT91_TWI_START 0x0001 /* Send a Start Condition */
+#defineAT91_TWI_STOP 0x0002 /* Send a Stop Condition */
+#defineAT91_TWI_MSEN 0x0004 /* Master Transfer Enable */
+#defineAT91_TWI_SVDIS 0x0020 /* Slave Transfer Disable */
+#defineAT91_TWI_QUICK 0x0040 /* SMBus quick command */
+#defineAT91_TWI_SWRST 0x0080 /* Software Reset */
+
+#defineAT91_TWI_MMR0x0004 /* Master Mode Register */
+#defineAT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size
*/
+#defineAT91_TWI_MREAD 0x1000 /* Master Read Direction */
+
+#defineAT91_TWI_IADR 0x000c /* Internal Address Register */
+
+#defineAT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg
*/
+
+#defineAT91_TWI_SR 0x0020 /* Status Register */
+#defineAT91_TWI_TXCOMP 0x0001 /* Transmission Complete */
+#defineAT91_TWI_RXRDY 0x0002 /* Receive Holding Register
Ready */
+#defineAT91_TWI_TXRDY 0x0004 /* Transmit Holding Register
Ready */
+
+#defineAT91_TWI_OVRE 0x0040 /* Overrun Error */
+#defineAT91_TWI_UNRE 0x0080 /* Underrun Error */
+#defineAT91_TWI_NACK 0x0100 /* Not Acknowledged */
+
+#defineAT91_TWI_IER0x0024 /* Interrupt Enable Register */
+#defineAT91_TWI_IDR0x0028 /* Interrupt Disable Register */
+#defineAT91_TWI_IMR0x002c /* Interrupt Mask Register */
+#defineAT91_TWI_RHR0x0030 /* Receive Holding Register */
+#defineAT91_TWI_THR0x0034 /* Transmit Holding Register */
+
+struct at91_twi_pdata {
+ unsigned clk_max_div;
+ unsigned clk_offset;
+ bool has_unre_flag;
+};
+
+struct at91_twi_dev {
+ struct device *dev;
+ void __iomem *base;
+ struct clk *clk;
+ u8 *buf;
+ size_t buf_len;
+ struct i2c_msg *msg;
+ unsigned imr;
+ unsigned transfer_status;
+ struct i2c_adapter adapter;
+ unsigned twi_cwgr_reg;
+ struct at91_twi_pdata *pdata;
+};
+
+#define to_at91_twi_dev(a) container_of(a, struct at91_twi_dev, adapter)
+
+static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
+{
+ return __raw_readl(dev->base + reg);
+}
+
+static void at91_twi_write(st
Re: [PATCH 2/2] mtd: atmel_nand: enable PMECC for 8k page nand
Thanks for your Acked.
Yes you're right, so I split this into 2 commits and send a v2.
Best regards,
Raphaël Poggi
2014-07-17 12:05 GMT+02:00 Bo Shen :
> Hi Raphael,
>
>
> On 07/17/2014 04:51 PM, Raphael Poggi wrote:
>>
>> Enable the PMECC to support 8k page.
>>
>> Signed-off-by: Raphaël Poggi
>
>
> Acked-by: Bo Shen
>
>
>> ---
>> drivers/mtd/nand/atmel_nand.c |4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
>> index fa596ed..36a60d1 100644
>> --- a/drivers/mtd/nand/atmel_nand.c
>> +++ b/drivers/mtd/nand/atmel_nand.c
>> @@ -796,7 +796,9 @@ static int __init atmel_pmecc_nand_init_params(struct
>> device_d *dev,
>> switch (mtd->writesize) {
>> case 2048:
>> case 4096:
>> - host->pmecc_degree = PMECC_GF_DIMENSION_13;
>> + case 8192:
>> + host->pmecc_degree = (sector_size == 512) ?
>> + PMECC_GF_DIMENSION_13 :
>> PMECC_GF_DIMENSION_14;
>
>
> Actually, this is a fix + 8K page support.
> If some commit message or split into two patches will be better.
>
>
>> host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
>> host->pmecc_sector_number = mtd->writesize / sector_size;
>> host->pmecc_bytes_per_sector = pmecc_get_ecc_bytes(
>>
>
> Best Regards,
> Bo Shen
>
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Re: [PATCH] mtd: atmel_nand: add SOFT_BCH support
Hi,
Thanks for applied, yes I changed the 20us to 40us for handle 8k page
NAND. I will send patchs about that.
2014-07-17 7:30 GMT+02:00 Sascha Hauer :
> On Tue, Jul 15, 2014 at 11:16:40AM +0200, Raphael Poggi wrote:
>> To use soft ecc with nand with 8k page, we need the BCH support.
>> This commit adds the possibilty for atmel_nand to enable SOFT_BCH.
>>
>> Signed-off-by: Raphaël Poggi
>> ---
>> drivers/mtd/nand/atmel_nand.c |5 +
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
>> index e9b2af7..d542a83 100644
>> --- a/drivers/mtd/nand/atmel_nand.c
>> +++ b/drivers/mtd/nand/atmel_nand.c
>> @@ -1164,6 +1164,11 @@ static int __init atmel_nand_probe(struct device_d
>> *dev)
>> nand_chip->ecc.mode = NAND_ECC_HW;
>> }
>>
>> + if (IS_ENABLED(CONFIG_NAND_ECC_BCH) &&
>> + pdata->ecc_mode == NAND_ECC_SOFT_BCH) {
>> + nand_chip->ecc.mode = NAND_ECC_SOFT_BCH;
>> + }
>> +
>> nand_chip->chip_delay = 40; /* 40us command delay time */
>
> The mainline code has 20us here. Do you need that change?
>
> Anyway, applied this patch.
>
> Sascha
>
>
> --
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> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0|
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917- |
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Nand with 256 oob
Hi all !
I want to use barebox with nand support (Soft ECC) on a custom board
based on SAM9M10, but the nand has a 256 oob size and it is not
supported on barebox.
Barebox fails, because there is no oob scheme defined for 256 size.
if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
switch (mtd->oobsize) {
case 8:
chip->ecc.layout = &nand_oob_8;
break;
case 16:
chip->ecc.layout = &nand_oob_16;
break;
case 64:
chip->ecc.layout = &nand_oob_64;
break;
case 128:
chip->ecc.layout = &nand_oob_128;
break;
default:
pr_warn("No oob scheme defined for oobsize %d\n",
mtd->oobsize);
BUG();
}
}
I have found this oob_256 scheme but I don't know if it's correct or not.
static struct nand_ecclayout nand_oob_256 = {
.eccbytes = 96,
.eccpos = {
160, 161, 162, 163, 164, 165, 166, 167,
168, 169, 170, 171, 172, 173, 174, 175,
176, 177, 178, 179, 180, 181, 182, 183,
184, 185, 186, 187, 188, 189, 190, 191,
192, 193, 194, 195, 196, 197, 198, 199,
200, 201, 202, 203, 204, 205, 206, 207,
208, 209, 210, 211, 212, 213, 214, 215,
216, 217, 218, 219, 220, 221, 222, 223,
224, 225, 226, 227, 228, 229, 230, 231,
232, 233, 234, 235, 236, 237, 238, 239,
240, 241, 242, 243, 244, 245, 246, 247,
248, 249, 250, 251, 252, 253, 254, 255},
.oobfree = {
{.offset = 2,
.length = 158}}
};
Can we use this scheme ? Or there is another solution ?
Thanks,
Raphaël
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Re: [PATCH 1/2] sama5d3x: fix HSMC MODE register offset and add TIMINGS register
Hi all !
So what's the status of these patch? Matteo, are you working on a v2
patch series ?
Raphaël
2014-06-25 8:42 GMT+02:00 Sascha Hauer :
> On Wed, Jun 25, 2014 at 09:45:49AM +0800, Bo Shen wrote:
>> Hi Matteo,
>> Thanks for your patch.
>>
>> Hi Jean-Christophe PLAGNIOL-VILLARD,
>> For this patch series, can you give some comments (maybe the
>> question from I need more discussion)? Thanks.
>>
>> On 06/24/2014 07:26 PM, Matteo Fortini wrote:
>> >As stated in section 29.19.35 of SAMA5D3 Series Datasheet,
>> >MODE register has offset 0x10 and at offset 0x0C there is
>> >a TIMINGS register.
>> >
>> >Signed-off-by: Matteo Fortini
>> >---
>> > arch/arm/mach-at91/include/mach/at91sam9_smc.h | 35
>> > +-
>> > arch/arm/mach-at91/sam9_smc.c | 21
>> > 2 files changed, 55 insertions(+), 1 deletion(-)
>> >
>> >diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
>> >b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
>> >index d5cf5f7..e4f0f54 100644
>> >--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
>> >+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
>> >@@ -45,10 +45,24 @@ struct sam9_smc_config {
>> > u8 tdf_cycles:4;
>> > };
>> >
>> >+struct sam9_smc_sama5d3_extra_config {
>>
>> Nitpick: I am thinking another name, maybe: sama5d3_timing_config (?)
>>
>> >+/* Timings register */
>> >+u8 tclr;
>> >+u8 tadl;
>> >+u8 tar;
>> >+u8 ocms;
>> >+u8 trr;
>> >+u8 twb;
>> >+u8 rbnsel;
>> >+u8 nfsel;
>> >+};
>> >+
>> > extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config
>> > *config);
>> > extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config);
>> > extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config
>> > *config);
>> > extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config
>> > *config);
>> >+
>> >+extern void sam9_smc_sama5d3_configure(int id, int cs, struct
>> >sam9_smc_config *config, struct sam9_smc_sama5d3_extra_config
>> >*sama5d3_extra_config);
>>
>> Ditto
>>
>> > #endif
>> >
>> > #define AT91_SMC_SETUP 0x00/*
>> > Setup Register for CS n */
>> >@@ -77,7 +91,25 @@ extern void sam9_smc_write_mode(int id, int cs, struct
>> >sam9_smc_config *config);
>> > #defineAT91_SMC_NRDCYCLE (0x1ff << 16)
>> > /* Total Read Cycle Length */
>> > #defineAT91_SMC_NRDCYCLE_(x) ((x) << 16)
>> >
>> >-#define AT91_SMC_MODE 0x0c/*
>> >Mode Register for CS n */
>> >+#define AT91_SMC_TIMINGS0x0c/* Timings
>> >register for CS n */
>> >+#define AT91_SMC_TCLR (0x0f << 0)
>> > /* CLE to REN Low Delay */
>> >+#define AT91_SMC_TCLR_(x) ((x) << 0)
>> >+#define AT91_SMC_TADL (0x0f << 4)
>> > /* ALE to Data Start */
>> >+#define AT91_SMC_TADL_(x) ((x) << 4)
>> >+#define AT91_SMC_TAR(0x0f << 8)
>> > /* ALE to REN Low Delay */
>> >+#define AT91_SMC_TAR_(x)((x) << 8)
>> >+#define AT91_SMC_OCMS (0x1 << 12)
>> > /* Off Chip Memory Scrambling Enable */
>> >+#define AT91_SMC_OCMS_(x) ((x) << 12)
>> >+#define AT91_SMC_TRR(0x0f << 16)
>> > /* Ready to REN Low Delay */
>> >+#define AT91_SMC_TRR_(x)((x) << 16)
>> >+#define AT91_SMC_TWB(0x0f << 24)
>> > /* WEN High to REN to Busy */
>> >+#define AT91_SMC_TWB_(x)((x) << 24)
>> >+#define AT91_SMC_RBNSEL (0x07 << 28)
>> > /* Ready/Busy Line Selection */
>> >+#define AT91_SMC_RBNSEL_(x) ((x) << 28)
>> >+#define AT91_SMC_NFSEL (0x01 << 31)
>> > /* Nand Flash Selection */
>> >+#define AT91_SMC_NFSEL_(x) ((x) << 31)
>> >+
>> >+#define AT91_SMC_MODE ((at91_soc_initdata.type ==
>> >AT91_SOC_SAMA5D3) ? 0x10 : 0x0c)/* Mode
>> >Register for CS n */
>>
>> Here make me thinking more, if new SoC added and MODE register's
>> offset is the same as sama5d3, then it will be:
>> (at91_soc_initdata.type == AT91_SOC_SAMA5D3) ||
>> (at91_soc_initdata.type == AT91_SOC_NEW1) || (at91_soc_initdata.type
>> == AT91_SOC_NEW2)
>>
>> Will this be acceptable?
>
> No.
>
> I think two SoC specific defines, for example
>
> #define AT91_SMC_MODE 0xc
> #define AT91_SAMA5_SMC_MODE 0x10
>
> and handling the differences in the code will scale better. I don't like
> hiding SoC differences in defines like done in this patch. If there show
> up even more differences a SoC specific struct with
Re: atmel_nand pmecc on 8k page
Hi, I'm testing with a custom board. I have just with the applied test and it's working ! I can use 8k page nand with atmel_nand driver. Do I have to wait until Matteo's patches are applied or can I submit mine right now ? Best regards, Raphaël Poggi 2014-06-13 3:26 GMT+02:00 Bo Shen : > Hi Raphaël, > > > On 06/12/2014 08:28 PM, Raphaël Poggi wrote: >> >> Hi, >> >> I'm working on a series of patches, to support 8k nand page in >> atmel_nand driver. >> >> Currently, I can detect the nand and handle an oob size of 448. But i >> have a problem with the pmecc, when barebox tried to perform pmecc >> operation, I get the following message: >> >> PMECC: Timeout to calculate error location. >> >> Example of log: >> >> nand: NAND device: Manufacturer ID: 0x2c, Chip ID: 0x68 (Micron >> MT29F32G08ABAAAWP), 4096MiB, page size: 8192, OOB size: 448 >> atmel_nand atmel_nand0: Initialize PMECC params, cap: 8, sector: 1024 >> atmel_nand atmel_nand0: PMECC: Timeout to calculate error location. >> atmel_nand atmel_nand0: PMECC: Timeout to calculate error location. >> atmel_nand atmel_nand0: PMECC: Timeout to calculate error location. >> atmel_nand atmel_nand0: PMECC: Timeout to calculate error location. >> Bad block table not found for chip 0 >> atmel_nand atmel_nand0: PMECC: Timeout to calculate error location. >> atmel_nand atmel_nand0: PMECC: Timeout to calculate error location. >> atmel_nand atmel_nand0: PMECC: Timeout to calculate error location. >> atmel_nand atmel_nand0: PMECC: Timeout to calculate error location. >> Bad block table not found for chip 0 >> Scanning device for bad blocks >> Bad eraseblock 90 at 0x05a0 >> Bad eraseblock 91 at 0x05b0 >> atmel_nand atmel_nand0: PMECC: Timeout to get ECC value. >> nand_bbt: error while writing bad block table -110 >> >> >> I don't know/find why barebox get a timeout... >> >> Someone have an idea ? > > > Which board are you test this? > Can you try to apply two patches from matteo.fort...@gmail.com on 2014-06-06 > with name > [PATCH 1/2] sama5d3x: fix HSMC MODE register offset and add TIMINGS > [PATCH 2/2] sama5d3x: HSMC NAND initialize TIMINGS and import values > >> Best regards, >> Raphaël > > > Best Regards, > Bo Shen > ___ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox
