Re: [casper] ASIAA adc5g downsampling

[Jack Hickish]

Hi Amit,

That's correct, assuming you are operating the adc in single input mode. It
also has a dual-input mode, where the first 8 outputs are one input, and
the second 8 are the other.
Don't forget that the input clock in single input (aka interleaved) mode
should be half the total sample rate. Eg., for 5gsps you input a 2.5ghz
clock. Though I suppose if you're going to downsample anyway then you may
as well use the adc in dual input mode.

Cheers,
Jack

On Tue, 31 May 2016, 04:23 Amit Bansod,  wrote:

> Hello,
>
> We are trying to sample a signal 100 MHz to 270 MHz with fpga running at
> 250MHz.
>
> To downsample by 4, I simply take every 4th output of the 16 outputs
> available from the yellow block of asiaa adc5g. We do have an
> anti-aliasing filter for the desired 500MHz bw.
>
> Is this correct or am I missing something obvious ?
>
>
> Cheers,
> Amit
>
>

[casper] ASIAA adc5g downsampling

[Amit Bansod]

Hello,

We are trying to sample a signal 100 MHz to 270 MHz with fpga running at
250MHz.

To downsample by 4, I simply take every 4th output of the 16 outputs
available from the yellow block of asiaa adc5g. We do have an
anti-aliasing filter for the desired 500MHz bw.

Is this correct or am I missing something obvious ?


Cheers,
Amit