Re: [casper] SNAP Board clocking for a low-frequency array

[Matt Dexter]

PS
The source of HERA's 10MHz ref and 1PPS into the White Rabbit
switch is an old Trimble Thunderbolt GPS Disciplined clock
leftover from PAPER.
https://www.trimble.com/timing/thunderbolt-e.aspx


On Fri, 19 Oct 2018, Matt Dexter wrote:


Date: Fri, 19 Oct 2018 11:05:53 -0700 (Pacific Daylight Time)
From: Matt Dexter <"mdex...@berkeley.edu"@berkeley.edu>
To: casper@lists.berkeley.edu
Subject: Re: [casper] SNAP Board clocking for a low-frequency array

Skimming the Meinberg manual finds reference to outputs that
are TTL levels into 50ohms,  TTL levels without load specified, and
2.5V TTL into 75 ohms.  I didn't study it enough to understand which
exact output has which drive spec. Meinberg's technical support should be 
able

to directly answer questions about the drive circuits and the
loads they can drive.

An old and simple 16way 1PPS driver design, schematics and Gerbers
included, may be found at
https://casper.berkeley.edu/wiki/16_way_1PPS_driver

The HERA project plans to use the White Rabbit Switch and
WR-LEN Endpoint from Seven Solutions for its 1PPS and 10MHz
distribution.
http://sevensols.com/index.php/timing-products/

Matt

PS.
Our lab has a collection of random synthesizers like
https://www.valonrf.com/frequency-synthesizer-6ghz.html
https://www.dsinstruments.com/store/products/category/rf-signal-generators/ 
SG6000E

OLED display ADF4350 signal generator RF source from eBay

On Fri, 19 Oct 2018, Nitish Ragoomundun wrote:


Date: Fri, 19 Oct 2018 13:45:34 +0400
From: Nitish Ragoomundun 
Reply-To: casper@lists.berkeley.edu
To: casper@lists.berkeley.edu
Subject: Re: [casper] SNAP Board clocking for a low-frequency array


Many thanks for your replies, Bob and Prof Inggs. Now we have a better idea 
how to tackle the issue.


Cheers.

On Fri, Oct 19, 2018 at 12:37 PM Michael Inggs  wrote:
  Hi Nitish

I am sure the Meinberg TTL will battle to drive 20 mA into the  SNAP. It is 
probably rated at a

few TTL loads.

For multiple boards, you will need to buffer the output of the Meinberg 
into a clock
distribution network i.e. multiple output gate / driver leading to the 
number of boards you aim
to drive as separate TTL channels. This is a bit pedantic, but just linking 
the Meinberg in
parallel to a number of TTL inputs (check the Meinberg drive capability in 
TTL loads in the
first place) will lead to multiple reflections and some jitter on the 
leading edge.


For our NeXtRAD multistatic radar that uses GPS synchronisation between 
nodes, we have
implemented an ubiquitous Frequency Distribution Unit (FDU) that can 
swallow almost any 10 MHz
or 100 MHz clock, at all the weird logic levels around, and then providing 
10 and 100 MHz in 6
ports per voltage standard (5V, 3V3, sinewave). There is an optional 10x 
multiplier (low phase
noise) for converting from 10 MHz to 100 MHz. Block diagram attached. You 
can implement any

subset of it. Can provide board layouts etc.

We also have a home made GPS Disciplined Oscillator that is proved to 
provide less that 4 ns rms
jitter between nodes with common view satellites. It provides 1 pps, 10 and 
100 MHz outputs (at
various levels). Stephan Sandenbergh is the father of this, and has 
implemented some cunning
fast lock mechanisms. Otherwise you will be there for hours if the power 
goes off.


Stephan also built a test jig for comparing two sources and plotting the 
Allen Variance. Be
careful of low cost GPSDOs as they are designed for NTP applications in 
networks, where 15 ms is

all that is required.

We also have a great deal of experience and hardware (with results) of 
using White Rabbit to

synchronise receivers.

Regards

On Fri, 19 Oct 2018 at 09:04, Nitish Ragoomundun 
 wrote:


Hi all,

We are building a low-frequency array for the observation of the deuterium 
hyperfine line
at 327.4 MHz with a bandwidth of 250 kHz. We intend to use SNAPs for 
acquisition. The
boards will operate at full 12 channels input, thus the ADCs at 250 MSps. 
We will

subsequently decimate the data rate, as our working bandwidth is narrow.

Concerning the clock input for the 
SNAP,  https://casper.berkeley.edu/wiki/SNAP states the

following:

Digital 1 PPS: 50 ohm single-ended LVTTL logic levels
 *  SMATP13
 *  Vin-high 2.0 to 3.3 Volts. Low current drive sources, such as typical 
LVTTL or CMOS
gates, probably can not supply the 40mA required to supply the 2.0V 
into the 50ohm

load.
 *  Vin-low 0.0 to 0.8 Volts

Actually we considered buying the GPS-disciplined Meinberg M500 
LANTIME(https://www.meinbergglobal.com/english/products/modular-railmount-ntp-server-ieee-1588-solution.htm)
, which is advertised to output 1 PPS TTL levels. Now, our first question 
is whether the
SNAP can work with this? Also, the note about low current drive sources is 
a little

confusing, can anyone shed some light here.

Secondly, we would like suggestions from anyone who has experience with 
clocking the SNAP.
You see, we run a very tight budget and the M5

Re: [casper] SNAP Board clocking for a low-frequency array

[Matt Dexter]

Skimming the Meinberg manual finds reference to outputs that
are TTL levels into 50ohms,  TTL levels without load specified, and
2.5V TTL into 75 ohms.  I didn't study it enough to understand which
exact output has which drive spec. Meinberg's technical support should be 
able

to directly answer questions about the drive circuits and the
loads they can drive.

An old and simple 16way 1PPS driver design, schematics and Gerbers
included, may be found at
https://casper.berkeley.edu/wiki/16_way_1PPS_driver

The HERA project plans to use the White Rabbit Switch and
WR-LEN Endpoint from Seven Solutions for its 1PPS and 10MHz
distribution.
http://sevensols.com/index.php/timing-products/

Matt

PS.
Our lab has a collection of random synthesizers like
https://www.valonrf.com/frequency-synthesizer-6ghz.html
https://www.dsinstruments.com/store/products/category/rf-signal-generators/ 
SG6000E
OLED display ADF4350 signal generator RF source from eBay

On Fri, 19 Oct 2018, Nitish Ragoomundun wrote:


Date: Fri, 19 Oct 2018 13:45:34 +0400
From: Nitish Ragoomundun 
Reply-To: casper@lists.berkeley.edu
To: casper@lists.berkeley.edu
Subject: Re: [casper] SNAP Board clocking for a low-frequency array


Many thanks for your replies, Bob and Prof Inggs. Now we have a better idea how 
to tackle the issue.

Cheers.

On Fri, Oct 19, 2018 at 12:37 PM Michael Inggs  wrote:
  Hi Nitish

I am sure the Meinberg TTL will battle to drive 20 mA into the  SNAP. It is 
probably rated at a
few TTL loads.

For multiple boards, you will need to buffer the output of the Meinberg into a 
clock
distribution network i.e. multiple output gate / driver leading to the number 
of boards you aim
to drive as separate TTL channels. This is a bit pedantic, but just linking the 
Meinberg in
parallel to a number of TTL inputs (check the Meinberg drive capability in TTL 
loads in the
first place) will lead to multiple reflections and some jitter on the leading 
edge.

For our NeXtRAD multistatic radar that uses GPS synchronisation between nodes, 
we have
implemented an ubiquitous Frequency Distribution Unit (FDU) that can swallow 
almost any 10 MHz
or 100 MHz clock, at all the weird logic levels around, and then providing 10 
and 100 MHz in 6
ports per voltage standard (5V, 3V3, sinewave). There is an optional 10x 
multiplier (low phase
noise) for converting from 10 MHz to 100 MHz. Block diagram attached. You can 
implement any
subset of it. Can provide board layouts etc.

We also have a home made GPS Disciplined Oscillator that is proved to provide 
less that 4 ns rms
jitter between nodes with common view satellites. It provides 1 pps, 10 and 100 
MHz outputs (at
various levels). Stephan Sandenbergh is the father of this, and has implemented 
some cunning
fast lock mechanisms. Otherwise you will be there for hours if the power goes 
off.

Stephan also built a test jig for comparing two sources and plotting the Allen 
Variance. Be
careful of low cost GPSDOs as they are designed for NTP applications in 
networks, where 15 ms is
all that is required.

We also have a great deal of experience and hardware (with results) of using 
White Rabbit to
synchronise receivers.

Regards

On Fri, 19 Oct 2018 at 09:04, Nitish Ragoomundun  
wrote:

Hi all,

We are building a low-frequency array for the observation of the deuterium 
hyperfine line
at 327.4 MHz with a bandwidth of 250 kHz. We intend to use SNAPs for 
acquisition. The
boards will operate at full 12 channels input, thus the ADCs at 250 MSps. We 
will
subsequently decimate the data rate, as our working bandwidth is narrow.

Concerning the clock input for the SNAP,  https://casper.berkeley.edu/wiki/SNAP 
states the
following:

Digital 1 PPS: 50 ohm single-ended LVTTL logic levels
 *  SMATP13
 *  Vin-high 2.0 to 3.3 Volts. Low current drive sources, such as typical LVTTL 
or CMOS
gates, probably can not supply the 40mA required to supply the 2.0V into 
the 50ohm
load.
 *  Vin-low 0.0 to 0.8 Volts

Actually we considered buying the GPS-disciplined Meinberg M500 
LANTIME(https://www.meinbergglobal.com/english/products/modular-railmount-ntp-server-ieee-1588-solution.htm)
, which is advertised to output 1 PPS TTL levels. Now, our first question is 
whether the
SNAP can work with this? Also, the note about low current drive sources is a 
little
confusing, can anyone shed some light here.

Secondly, we would like suggestions from anyone who has experience with 
clocking the SNAP.
You see, we run a very tight budget and the M500 LANTIME clock is expensive. We 
would like
to know if there is a less costly way to clock the SNAP and synchronise several 
boards.

Thanks.

Best regards,
Nitish Ragoomundun
Department of Physics
University of Mauritius

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Re: [casper] SNAP Board clocking for a low-frequency array

[Nitish Ragoomundun]

Many thanks for your replies, Bob and Prof Inggs. Now we have a better idea
how to tackle the issue.

Cheers.

On Fri, Oct 19, 2018 at 12:37 PM Michael Inggs  wrote:

> Hi Nitish
>
> I am sure the Meinberg TTL will battle to drive 20 mA into the  SNAP. It
> is probably rated at a few TTL loads.
>
> For multiple boards, you will need to buffer the output of the Meinberg
> into a clock distribution network i.e. multiple output gate / driver
> leading to the number of boards you aim to drive as separate TTL channels.
> This is a bit pedantic, but just linking the Meinberg in parallel to a
> number of TTL inputs (check the Meinberg drive capability in TTL loads in
> the first place) will lead to multiple reflections and some jitter on the
> leading edge.
>
> For our NeXtRAD multistatic radar that uses GPS synchronisation between
> nodes, we have implemented an ubiquitous Frequency Distribution Unit (FDU)
> that can swallow almost any 10 MHz or 100 MHz clock, at all the weird logic
> levels around, and then providing 10 and 100 MHz in 6 ports per voltage
> standard (5V, 3V3, sinewave). There is an optional 10x multiplier (low
> phase noise) for converting from 10 MHz to 100 MHz. Block diagram attached.
> You can implement any subset of it. Can provide board layouts etc.
>
> We also have a home made GPS Disciplined Oscillator that is proved to
> provide less that 4 ns rms jitter between nodes with common view
> satellites. It provides 1 pps, 10 and 100 MHz outputs (at various levels).
> Stephan Sandenbergh is the father of this, and has implemented some cunning
> fast lock mechanisms. Otherwise you will be there for hours if the power
> goes off.
>
> Stephan also built a test jig for comparing two sources and plotting the
> Allen Variance. Be careful of low cost GPSDOs as they are designed for NTP
> applications in networks, where 15 ms is all that is required.
>
> We also have a great deal of experience and hardware (with results) of
> using White Rabbit to synchronise receivers.
>
> Regards
>
> On Fri, 19 Oct 2018 at 09:04, Nitish Ragoomundun <
> nitish.ragoomun...@gmail.com> wrote:
>
>>
>> Hi all,
>>
>> We are building a low-frequency array for the observation of the
>> deuterium hyperfine line at 327.4 MHz with a bandwidth of 250 kHz. We
>> intend to use SNAPs for acquisition. The boards will operate at full 12
>> channels input, thus the ADCs at 250 MSps. We will subsequently decimate
>> the data rate, as our working bandwidth is narrow.
>>
>> Concerning the clock input for the SNAP,
>> https://casper.berkeley.edu/wiki/SNAP states the following:
>>
>> *Digital 1 PPS: 50 ohm single-ended LVTTL logic levels *
>>
>>- * SMATP13 *
>>- * Vin-high 2.0 to 3.3 Volts. Low current drive sources, such as
>>typical LVTTL or CMOS gates, probably can not supply the 40mA required to
>>supply the 2.0V into the 50ohm load. *
>>- * Vin-low 0.0 to 0.8 Volts*
>>
>>
>> Actually we considered buying the GPS-disciplined Meinberg M500 LANTIME (
>> https://www.meinbergglobal.com/english/products/modular-railmount-ntp-server-ieee-1588-solution.htm),
>> which is advertised to output 1 PPS *TTL* levels. Now, our first
>> question is whether the SNAP can work with this? Also, the note about low
>> current drive sources is a little confusing, can anyone shed some light
>> here.
>>
>> Secondly, we would like suggestions from anyone who has experience with
>> clocking the SNAP. You see, we run a very tight budget and the M500 LANTIME
>> clock is expensive. We would like to know if there is a less costly way to
>> clock the SNAP and synchronise several boards.
>>
>> Thanks.
>>
>> Best regards,
>> Nitish Ragoomundun
>> Department of Physics
>> University of Mauritius
>>
>> --
>> You received this message because you are subscribed to the Google Groups
>> "casper@lists.berkeley.edu" group.
>> To unsubscribe from this group and stop receiving emails from it, send an
>> email to casper+unsubscr...@lists.berkeley.edu.
>> To post to this group, send email to casper@lists.berkeley.edu.
>>
>
>
> --
> Michael Inggs
> 10 Devon Street, Simon's Town, South Africa. Tel: +27 21 786 1723 Fax: +27
> 21 786 1151  Skype: mikings Cell: +27 83 776 7304
> "Ex Africa semper aliquid novi"
>
> --
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Re: [casper] SNAP Board clocking for a low-frequency array

[Bob Stricklin]

For the time reference this one was suggested on an earlier discussion….

http://www.leobodnar.com/shop/index.php?main_page=index=107=468ab2632bba5b5ffe4d2fe7d8bb19e2

If you need to reduce cost even more you can find GPS based 1PPS sources on 
ebay.
https://www.ebay.com/itm/UBLOX-LEA-5T-high-precision-timing-GPS-module-dev-board-1PPS-USB-RS232-ntp-ser/263546760982?hash=item3d5c9c6f16:g:hbgAAOSwbsBXopDl:rk:19:pf:0

If you have a failure you should have a good plan for how you can obtain 
another time reference for the project before or after the failure. Also their 
can be some phase noise in a 1PPS signal. This phase noise can contribute to 
error in your system just like noise degrades RF reception.

I have not looked at the SNAP spec but it is stated here as 2.0V into a 50 ohm 
load or resistor. A LVTTL CMOS output would be the wrong voltage level and 
could not supply 40 mA. In this case you will need a buffer circuit to match 
the output conditions of the 1PPS reference selected and the input of SNAP. You 
could build this yourself. Typically there will be the need for many time 
reference lines. You must be sure not to create any phase delay as you fan out 
N time reference lines. So each circuit path and connecting cable will be the 
same type and length. You can see examples of this in other systems posted to 
this list.

Your circuit would interface the output and input with the proper voltage level 
and currents. Take a look at this link for some ideas of buffer interfaces…

http://www.ti.com/lit/an/scea035a/scea035a.pdf

I am a retired engineer that follows this list and offer these suggestions to 
hopefully help you in your efforts.


Bob Stricklin


On Oct 19, 2018, at 2:04 AM, Nitish Ragoomundun 
mailto:nitish.ragoomun...@gmail.com>> wrote:


Hi all,

We are building a low-frequency array for the observation of the deuterium 
hyperfine line at 327.4 MHz with a bandwidth of 250 kHz. We intend to use SNAPs 
for acquisition. The boards will operate at full 12 channels input, thus the 
ADCs at 250 MSps. We will subsequently decimate the data rate, as our working 
bandwidth is narrow.

Concerning the clock input for the SNAP,  https://casper.berkeley.edu/wiki/SNAP 
states the following:

Digital 1 PPS: 50 ohm single-ended LVTTL logic levels

  *   SMATP13
  *   Vin-high 2.0 to 3.3 Volts. Low current drive sources, such as typical 
LVTTL or CMOS gates, probably can not supply the 40mA required to supply the 
2.0V into the 50ohm load.
  *   Vin-low 0.0 to 0.8 Volts

Actually we considered buying the GPS-disciplined Meinberg M500 LANTIME 
(https://www.meinbergglobal.com/english/products/modular-railmount-ntp-server-ieee-1588-solution.htm),
 which is advertised to output 1 PPS TTL levels. Now, our first question is 
whether the SNAP can work with this? Also, the note about low current drive 
sources is a little confusing, can anyone shed some light here.

Secondly, we would like suggestions from anyone who has experience with 
clocking the SNAP. You see, we run a very tight budget and the M500 LANTIME 
clock is expensive. We would like to know if there is a less costly way to 
clock the SNAP and synchronise several boards.

Thanks.

Best regards,
Nitish Ragoomundun
Department of Physics
University of Mauritius


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[casper] SNAP Board clocking for a low-frequency array

[Nitish Ragoomundun]

Hi all,

We are building a low-frequency array for the observation of the deuterium
hyperfine line at 327.4 MHz with a bandwidth of 250 kHz. We intend to use
SNAPs for acquisition. The boards will operate at full 12 channels input,
thus the ADCs at 250 MSps. We will subsequently decimate the data rate, as
our working bandwidth is narrow.

Concerning the clock input for the SNAP,
https://casper.berkeley.edu/wiki/SNAP states the following:

*Digital 1 PPS: 50 ohm single-ended LVTTL logic levels *

   - * SMATP13 *
   - * Vin-high 2.0 to 3.3 Volts. Low current drive sources, such as
   typical LVTTL or CMOS gates, probably can not supply the 40mA required to
   supply the 2.0V into the 50ohm load. *
   - * Vin-low 0.0 to 0.8 Volts*


Actually we considered buying the GPS-disciplined Meinberg M500 LANTIME (
https://www.meinbergglobal.com/english/products/modular-railmount-ntp-server-ieee-1588-solution.htm),
which is advertised to output 1 PPS *TTL* levels. Now, our first question
is whether the SNAP can work with this? Also, the note about low current
drive sources is a little confusing, can anyone shed some light here.

Secondly, we would like suggestions from anyone who has experience with
clocking the SNAP. You see, we run a very tight budget and the M500 LANTIME
clock is expensive. We would like to know if there is a less costly way to
clock the SNAP and synchronise several boards.

Thanks.

Best regards,
Nitish Ragoomundun
Department of Physics
University of Mauritius

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