Hi Laura, For FPGA utilization, I look at the file: sysgen/synth_model/modelfilename_cw.syr
Mark On Wed, Nov 18, 2009 at 2:26 PM, Laura Spitler <laura.spit...@gmail.com>wrote: > Hi everyone, > > I have a general question about over mapping a design. What's the > easiest way to determine by how much I've over utilized the chip? > The log files don't seem to give a resource summary when mapping fails > with an error. > > Thanks! > Laura > >
