[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

Thanks, I'll take another look. Rereading my previous comment I just wanted to 
clarify one part so it's not misunderstood. I said " I think it's unfortunate 
that this need for the ABI hasn't translated into effort to finalise the ABI 
definition in the psABI doc and to at least get it to match what GCC actually 
implements" - I wanted to be __very__ clear this isn't a criticism of those 
trying to maintain the ABI doc, it's about companies who want to ship RVE 
hardware and software not contributing to that process.


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[PATCH] D70401: [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

First of all, thank you to everyone who has been trying to nudge this forward 
and apologies it must have been a frustrating experience.

I appreciate there are users who want to see this and I don't like that LLVM 
doesn't serve them right now - I think it's unfortunate that this need for the 
ABI hasn't translated into effort to finalise the ABI definition in the psABI 
doc and to at least get it to match what GCC actually implements (spec. That 
said, I've not really vocalised that concern clearly up to now - so that's my 
bad.

Matching what GCC does by setting stack alignment to 4 bytes for 2xlen types 
seems fine - except this doesn't seem to be documented explicitly in the 
current ABI doc (it notes the stack if 4 byte aligned, but you could have that 
be the case and still require it to be realigned when storing objects with a 
greater alignment requirement, surely?).

Having different alignment requirements _only_ on the stack does seem ugly, but 
I can't think of something off hand that would realistically break with this.

@wangpc do you want to update this with the suggested documentation in the 
release notes and RISCVUsage on the support being "experimental"?


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[PATCH] D152279: [Driver] Default -msmall-data-limit= to 0

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

In D152279#4612099 , @craig.topper 
wrote:

> In D152279#4612087 , @MaskRay wrote:
>
>> I am still interested in moving this forward. What should be done here? If 
>> the decision is to keep the current odd default 8 for 
>> `toolchains::RISCVToolChain`, I guess I'll have to take the compromise as 
>> making a step forward is better than nothing.
>
> On 1 RV64 CPU I tried in our RTL simulator, changing from 8 to 0 reduced 
> dhrystone score by 2.7%. Using 16, or 32 gave the same score as 8. Reducing 8 
> to 4 improved the score by 0.5%.

Thanks for testing - do you have a view one way or another on this default? I'm 
somewhat torn personally.


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[PATCH] D157663: [Driver] Default riscv*- triples to -fdebug-default-version=4

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.

LGTM, this seems like a good workaround.


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[PATCH] D157497: feat: Migrate isArch16Bit

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

Is there some separate discussion thread or proposal about this refactoring and 
its motivations?


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[PATCH] D157580: [RISCV][NFC] Use named arguments in newly added changes

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.

I just wanted to say thank you for your work on the named arguments tablegen 
feature. This and D154067  are good showcases 
of the readability improvement.


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[PATCH] D151547: [RISCV] Remove experimental for zihintntl

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM - just see the very minor corrections inline. Thanks!




Comment at: clang/test/Preprocessor/riscv-target-features.c:146
 
 // RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions \
+// RUN: -march=rv32izihintntl1p0 -x c -E -dM %s \

Drop `-menable-experimental-extensions`



Comment at: clang/test/Preprocessor/riscv-target-features.c:149
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTNTL %s
 // RUN: %clang -target riscv64-unknown-linux-gnu 
-menable-experimental-extensions \
+// RUN: -march=rv64izihintntl1p0 -x c -E -dM %s \

Drop `Drop `-menable-experimental-extensions`



Comment at: llvm/docs/RISCVUsage.rst:123
  ``Zifencei`` (`See Note <#riscv-i2p1-note>`__)
+ ``zihintntl``Supported
  ``Zihintpause``  Assembly Support

zihintntl -> Zihintntl


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[PATCH] D154576: [RISCV] RISCV vector calling convention (1/2)

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

Putting this behind an attribute for now makes sense given that we don't seem 
to have consensus on 
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389 let alone how to 
manage any migration. I'm slightly wary of merging this with a generic 
attribute (currently 'riscv_vector_cc') and the proposed ABI changing, causing 
further confusion.


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[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

@jacquesguan: I think this is good to go if you rebase now D156221 
 landed and add a release note.


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[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

[Alex Bradbury via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGe3c57fdd8439: [clang][RISCV] Fix bug in ABI handling of 
empty structs with hard FP calling… (authored by asb).

Changed prior to commit:
  https://reviews.llvm.org/D142327?vs=546012=547684#toc

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Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/CodeGen/ABIInfoImpl.cpp
  clang/lib/CodeGen/ABIInfoImpl.h
  clang/lib/CodeGen/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/abi-empty-structs.c

Index: clang/test/CodeGen/RISCV/abi-empty-structs.c
===
--- clang/test/CodeGen/RISCV/abi-empty-structs.c
+++ clang/test/CodeGen/RISCV/abi-empty-structs.c
@@ -1,4 +1,4 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --full-function-signature --filter "^define |^entry:"
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --filter "^define |^entry:" --version 2
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f -emit-llvm %s -o - \
 // RUN:   | FileCheck -check-prefixes=CHECK-C,CHECK32-C %s
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-abi ilp32d -emit-llvm %s -o - \
@@ -19,8 +19,9 @@
 #include 
 
 // Fields containing empty structs or unions are ignored when flattening
-// structs for the hard FP ABIs, even in C++.
-// FIXME: This isn't currently respected.
+// structs for the hard FP ABIs, even in C++. The rules for arrays of empty
+// structs or unions are subtle and documented in
+// .
 
 struct empty { struct { struct { } e; }; };
 struct s1 { struct empty e; float f; };
@@ -29,13 +30,9 @@
 // CHECK-C-SAME: (float [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local [2 x i32] @_Z7test_s12s1
-// CHECK32-CXX-SAME: ([2 x i32] [[A_COERCE:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local i64 @_Z7test_s12s1
-// CHECK64-CXX-SAME: (i64 [[A_COERCE:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local float @_Z7test_s12s1
+// CHECK-CXX-SAME: (float [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-CXX:  entry:
 //
 struct s1 test_s1(struct s1 a) {
   return a;
@@ -47,13 +44,9 @@
 // CHECK-C-SAME: (i32 [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local void @_Z7test_s22s2
-// CHECK32-CXX-SAME: (ptr noalias sret([[STRUCT_S2:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local [2 x i64] @_Z7test_s22s2
-// CHECK64-CXX-SAME: ([2 x i64] [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local { i32, float } @_Z7test_s22s2
+// CHECK-CXX-SAME: (i32 [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
+// CHECK-CXX:  entry:
 //
 struct s2 test_s2(struct s2 a) {
   return a;
@@ -65,13 +58,9 @@
 // CHECK-C-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local void @_Z7test_s32s3
-// CHECK32-CXX-SAME: (ptr noalias sret([[STRUCT_S3:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local [2 x i64] @_Z7test_s32s3
-// CHECK64-CXX-SAME: ([2 x i64] [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local { float, float } @_Z7test_s32s3
+// CHECK-CXX-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
+// CHECK-CXX:  entry:
 //
 struct s3 test_s3(struct s3 a) {
   return a;
@@ -83,13 +72,9 @@
 // CHECK-C-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local void @_Z7test_s42s4
-// CHECK32-CXX-SAME: (ptr noalias sret([[STRUCT_S4:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local [2 x i64] @_Z7test_s42s4
-// CHECK64-CXX-SAME: ([2 x i64] [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local { float, float } @_Z7test_s42s4
+// CHECK-CXX-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
+// CHECK-CXX:  entry:
 //
 struct s4 test_s4(struct s4 a) {
   return a;
@@ -142,7 +127,7 @@
 // CHECK-C:  entry:
 //
 // CHECK-CXX-LABEL: define dso_local float @_Z7test_s72s7
-// CHECK-CXX-SAME: (float [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-CXX-SAME: (float [[TMP0:%.*]]) #[[ATTR0]] {
 // CHECK-CXX:  entry:
 //
 struct s7 test_s7(struct s7 a) {
@@ -156,17 +141,31 @@
 // CHECK-C-SAME: (float 

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 546012.
asb added a comment.

This update includes test coverage for the bug that was fixed in the reverted 
version of the patch.

Thanks @rogfer01 for the smaller test case. To my surprise, cvise stripped out 
almost everything and test_s9 in abi-empty-structs.c reliably caused the assert 
for me.

Re-review appreciated in order to get this landed and ideally cherry-picked for 
the 17.x.


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Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/CodeGen/ABIInfoImpl.cpp
  clang/lib/CodeGen/ABIInfoImpl.h
  clang/lib/CodeGen/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/abi-empty-structs.c

Index: clang/test/CodeGen/RISCV/abi-empty-structs.c
===
--- clang/test/CodeGen/RISCV/abi-empty-structs.c
+++ clang/test/CodeGen/RISCV/abi-empty-structs.c
@@ -1,4 +1,4 @@
-// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --full-function-signature --filter "^define |^entry:"
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --filter "^define |^entry:" --version 2
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-abi ilp32f -emit-llvm %s -o - \
 // RUN:   | FileCheck -check-prefixes=CHECK-C,CHECK32-C %s
 // RUN: %clang_cc1 -triple riscv32 -target-feature +f -target-feature +d -target-abi ilp32d -emit-llvm %s -o - \
@@ -19,8 +19,9 @@
 #include 
 
 // Fields containing empty structs or unions are ignored when flattening
-// structs for the hard FP ABIs, even in C++.
-// FIXME: This isn't currently respected.
+// structs for the hard FP ABIs, even in C++. The rules for arrays of empty
+// structs or unions are subtle and documented in
+// .
 
 struct empty { struct { struct { } e; }; };
 struct s1 { struct empty e; float f; };
@@ -29,13 +30,9 @@
 // CHECK-C-SAME: (float [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local [2 x i32] @_Z7test_s12s1
-// CHECK32-CXX-SAME: ([2 x i32] [[A_COERCE:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local i64 @_Z7test_s12s1
-// CHECK64-CXX-SAME: (i64 [[A_COERCE:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local float @_Z7test_s12s1
+// CHECK-CXX-SAME: (float [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-CXX:  entry:
 //
 struct s1 test_s1(struct s1 a) {
   return a;
@@ -47,13 +44,9 @@
 // CHECK-C-SAME: (i32 [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local void @_Z7test_s22s2
-// CHECK32-CXX-SAME: (ptr noalias sret([[STRUCT_S2:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local [2 x i64] @_Z7test_s22s2
-// CHECK64-CXX-SAME: ([2 x i64] [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local { i32, float } @_Z7test_s22s2
+// CHECK-CXX-SAME: (i32 [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
+// CHECK-CXX:  entry:
 //
 struct s2 test_s2(struct s2 a) {
   return a;
@@ -65,13 +58,9 @@
 // CHECK-C-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local void @_Z7test_s32s3
-// CHECK32-CXX-SAME: (ptr noalias sret([[STRUCT_S3:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local [2 x i64] @_Z7test_s32s3
-// CHECK64-CXX-SAME: ([2 x i64] [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local { float, float } @_Z7test_s32s3
+// CHECK-CXX-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
+// CHECK-CXX:  entry:
 //
 struct s3 test_s3(struct s3 a) {
   return a;
@@ -83,13 +72,9 @@
 // CHECK-C-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local void @_Z7test_s42s4
-// CHECK32-CXX-SAME: (ptr noalias sret([[STRUCT_S4:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local [2 x i64] @_Z7test_s42s4
-// CHECK64-CXX-SAME: ([2 x i64] [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local { float, float } @_Z7test_s42s4
+// CHECK-CXX-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
+// CHECK-CXX:  entry:
 //
 struct s4 test_s4(struct s4 a) {
   return a;
@@ -142,7 +127,7 @@
 // CHECK-C:  entry:
 //
 // CHECK-CXX-LABEL: define dso_local float @_Z7test_s72s7
-// CHECK-CXX-SAME: (float [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-CXX-SAME: (float [[TMP0:%.*]]) #[[ATTR0]] {
 // CHECK-CXX:  

[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 544349.
asb added a comment.

I've updated the patch to fix the reported issue (adding an additional check to 
detectFPCCEligibleStruct). What I haven't been able to do so far is to extract 
a test case that shows the issue indicated by @SixWeining without relying on 
libcxx headers. I may well be missing something obvious here.


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Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/CodeGen/ABIInfoImpl.cpp
  clang/lib/CodeGen/ABIInfoImpl.h
  clang/lib/CodeGen/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/abi-empty-structs.c

Index: clang/test/CodeGen/RISCV/abi-empty-structs.c
===
--- clang/test/CodeGen/RISCV/abi-empty-structs.c
+++ clang/test/CodeGen/RISCV/abi-empty-structs.c
@@ -19,8 +19,9 @@
 #include 
 
 // Fields containing empty structs or unions are ignored when flattening
-// structs for the hard FP ABIs, even in C++.
-// FIXME: This isn't currently respected.
+// structs for the hard FP ABIs, even in C++. The rules for arrays of empty
+// structs or unions are subtle and documented in
+// .
 
 struct empty { struct { struct { } e; }; };
 struct s1 { struct empty e; float f; };
@@ -29,13 +30,9 @@
 // CHECK-C-SAME: (float [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local [2 x i32] @_Z7test_s12s1
-// CHECK32-CXX-SAME: ([2 x i32] [[A_COERCE:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local i64 @_Z7test_s12s1
-// CHECK64-CXX-SAME: (i64 [[A_COERCE:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local float @_Z7test_s12s1
+// CHECK-CXX-SAME: (float [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-CXX:  entry:
 //
 struct s1 test_s1(struct s1 a) {
   return a;
@@ -47,13 +44,9 @@
 // CHECK-C-SAME: (i32 [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local void @_Z7test_s22s2
-// CHECK32-CXX-SAME: (ptr noalias sret([[STRUCT_S2:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local [2 x i64] @_Z7test_s22s2
-// CHECK64-CXX-SAME: ([2 x i64] [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local { i32, float } @_Z7test_s22s2
+// CHECK-CXX-SAME: (i32 [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
+// CHECK-CXX:  entry:
 //
 struct s2 test_s2(struct s2 a) {
   return a;
@@ -65,13 +58,9 @@
 // CHECK-C-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local void @_Z7test_s32s3
-// CHECK32-CXX-SAME: (ptr noalias sret([[STRUCT_S3:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local [2 x i64] @_Z7test_s32s3
-// CHECK64-CXX-SAME: ([2 x i64] [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local { float, float } @_Z7test_s32s3
+// CHECK-CXX-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
+// CHECK-CXX:  entry:
 //
 struct s3 test_s3(struct s3 a) {
   return a;
@@ -83,13 +72,9 @@
 // CHECK-C-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local void @_Z7test_s42s4
-// CHECK32-CXX-SAME: (ptr noalias sret([[STRUCT_S4:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local [2 x i64] @_Z7test_s42s4
-// CHECK64-CXX-SAME: ([2 x i64] [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local { float, float } @_Z7test_s42s4
+// CHECK-CXX-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
+// CHECK-CXX:  entry:
 //
 struct s4 test_s4(struct s4 a) {
   return a;
@@ -142,7 +127,7 @@
 // CHECK-C:  entry:
 //
 // CHECK-CXX-LABEL: define dso_local float @_Z7test_s72s7
-// CHECK-CXX-SAME: (float [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-CXX-SAME: (float [[TMP0:%.*]]) #[[ATTR0]] {
 // CHECK-CXX:  entry:
 //
 struct s7 test_s7(struct s7 a) {
@@ -156,13 +141,9 @@
 // CHECK-C-SAME: (float [[TMP0:%.*]]) #[[ATTR0]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local i32 @_Z7test_s82s8
-// CHECK32-CXX-SAME: (i32 [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local i64 @_Z7test_s82s8
-// CHECK64-CXX-SAME: (i64 [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local float @_Z7test_s82s8
+// CHECK-CXX-SAME: (float [[TMP0:%.*]]) #[[ATTR0]] {
+// CHECK-CXX:  entry:
 //
 struct s8 test_s8(struct s8 a) {
   return a;
Index: 

[PATCH] D156221: [RISCV] Support overloaded version ntlh intrinsic function

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

This seems functionally correct to me, but I'd welcome opinions from others who 
work more with the C intrinsics on if this is the best way to implement the 
overloading.


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[PATCH] D156214: [LLVM][RISCV] Check more extension dependencies

[Alex Bradbury via Phabricator via cfe-commits]

asb added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:948
-  // TODO: The 'q' extension requires rv64.
-  // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
 

imkiva wrote:
> wangpc wrote:
> > I think the comment is outdated here. `E` can be combined with all other 
> > extensions according to spec:
> > > Unless otherwise stated, standard extensions compatible with RV32I and 
> > > RV64I are also compatible with RV32E and RV64E, respectively.
> > And, please see also D70401 for more context.
> I downloaded the specification from 
> [here](https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf),
>  and in page 34 the footnote says:
> 
> > RV32E can be combined with all current standard extensions. Defining the F, 
> > D, and Q extensions as having a 16-entry floating point register file when 
> > combined with RV32E was considered but **decided against**. To support 
> > systems with reduced floating-point register state, we intend to define a 
> > “Zfinx” extension...
> 
> It seems in the spec version 20191213, they rejected the combination of `E` 
> with standard floating-point extensions, instead, a separate extension 
> `Zfinx` is chosen for the original purpose.
> I am not sure if there's any newer specification that decides to allow this 
> combination.
> 
> 
There's a link to the ratified version on 
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions - see 
https://drive.google.com/file/d/1GjHmphVKvJlOBJydAt36g0Oc8yCOPtKw/view

As @wangpc says, the restriction was removed and so the comment is out of date.


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[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

In D151547#4531062 , @jacquesguan 
wrote:

> https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47 is already merged, 
> any more advice about this patch?

Just that it needs a release note, and we need the newly defined overloaded 
form of the intrinsics to be supported.


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[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

[Alex Bradbury via Phabricator via cfe-commits]

asb reopened this revision.
asb added a comment.
This revision is now accepted and ready to land.

Reopening as I've reverted following Roger's bug report.




Comment at: clang/lib/CodeGen/Targets/RISCV.cpp:178
   return false;
-if (isEmptyRecord(getContext(), Ty, true))
+if (isEmptyRecord(getContext(), Ty, true, true))
   return true;

rogfer01 wrote:
> I've observed (based on manually added tracing) that we may return true here 
> with `Field1Ty == nullptr` and `Field2Ty == nullptr`.
> 
> Then `RISCVABIInfo::coerceAndExpandFPCCEligibleStruct` receives these two 
> types and appends `Field1Ty` it into `UnpaddedCoerceElts` and then if 
> `Field2Ty == nullptr` it calls `ABIArgInfo::getCoerceAndExpand` (around line 
> 280 of `clang/lib/CodeGen/Targets/RISCV.cpp`) which then tries to do a 
> `dyn_cast` on a null value and then an assertion fires (around line 256 of 
> `clang/include/clang/CodeGen/CGFunctionInfo.h`)
> 
> I can reproduce this with the llvm-testsuite. Apologies that I have not 
> managed to create a small reproducer yet.
Thank you, I've reverted until this can be investigated and fixed.


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[PATCH] D142327: [clang][RISCV] Fix ABI handling of empty structs with hard FP calling conventions in C++

[Alex Bradbury via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG17a58b3ca7ec: [clang][RISCV] Fix ABI handling of empty 
structs with hard FP calling… (authored by asb).
Herald added a subscriber: wangpc.

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Files:
  clang/docs/ReleaseNotes.rst
  clang/lib/CodeGen/ABIInfoImpl.cpp
  clang/lib/CodeGen/ABIInfoImpl.h
  clang/lib/CodeGen/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/abi-empty-structs.c

Index: clang/test/CodeGen/RISCV/abi-empty-structs.c
===
--- clang/test/CodeGen/RISCV/abi-empty-structs.c
+++ clang/test/CodeGen/RISCV/abi-empty-structs.c
@@ -19,8 +19,9 @@
 #include 
 
 // Fields containing empty structs or unions are ignored when flattening
-// structs for the hard FP ABIs, even in C++.
-// FIXME: This isn't currently respected.
+// structs for the hard FP ABIs, even in C++. The rules for arrays of empty
+// structs or unions are subtle and documented in
+// .
 
 struct empty { struct { struct { } e; }; };
 struct s1 { struct empty e; float f; };
@@ -29,13 +30,9 @@
 // CHECK-C-SAME: (float [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local [2 x i32] @_Z7test_s12s1
-// CHECK32-CXX-SAME: ([2 x i32] [[A_COERCE:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local i64 @_Z7test_s12s1
-// CHECK64-CXX-SAME: (i64 [[A_COERCE:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local float @_Z7test_s12s1
+// CHECK-CXX-SAME: (float [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-CXX:  entry:
 //
 struct s1 test_s1(struct s1 a) {
   return a;
@@ -47,13 +44,9 @@
 // CHECK-C-SAME: (i32 [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local void @_Z7test_s22s2
-// CHECK32-CXX-SAME: (ptr noalias sret([[STRUCT_S2:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local [2 x i64] @_Z7test_s22s2
-// CHECK64-CXX-SAME: ([2 x i64] [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local { i32, float } @_Z7test_s22s2
+// CHECK-CXX-SAME: (i32 [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
+// CHECK-CXX:  entry:
 //
 struct s2 test_s2(struct s2 a) {
   return a;
@@ -65,13 +58,9 @@
 // CHECK-C-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local void @_Z7test_s32s3
-// CHECK32-CXX-SAME: (ptr noalias sret([[STRUCT_S3:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local [2 x i64] @_Z7test_s32s3
-// CHECK64-CXX-SAME: ([2 x i64] [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local { float, float } @_Z7test_s32s3
+// CHECK-CXX-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
+// CHECK-CXX:  entry:
 //
 struct s3 test_s3(struct s3 a) {
   return a;
@@ -83,13 +72,9 @@
 // CHECK-C-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local void @_Z7test_s42s4
-// CHECK32-CXX-SAME: (ptr noalias sret([[STRUCT_S4:%.*]]) align 4 [[AGG_RESULT:%.*]], ptr noundef [[A:%.*]]) #[[ATTR0]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local [2 x i64] @_Z7test_s42s4
-// CHECK64-CXX-SAME: ([2 x i64] [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local { float, float } @_Z7test_s42s4
+// CHECK-CXX-SAME: (float [[TMP0:%.*]], float [[TMP1:%.*]]) #[[ATTR0]] {
+// CHECK-CXX:  entry:
 //
 struct s4 test_s4(struct s4 a) {
   return a;
@@ -142,7 +127,7 @@
 // CHECK-C:  entry:
 //
 // CHECK-CXX-LABEL: define dso_local float @_Z7test_s72s7
-// CHECK-CXX-SAME: (float [[TMP0:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-CXX-SAME: (float [[TMP0:%.*]]) #[[ATTR0]] {
 // CHECK-CXX:  entry:
 //
 struct s7 test_s7(struct s7 a) {
@@ -156,13 +141,9 @@
 // CHECK-C-SAME: (float [[TMP0:%.*]]) #[[ATTR0]] {
 // CHECK-C:  entry:
 //
-// CHECK32-CXX-LABEL: define dso_local i32 @_Z7test_s82s8
-// CHECK32-CXX-SAME: (i32 [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK32-CXX:  entry:
-//
-// CHECK64-CXX-LABEL: define dso_local i64 @_Z7test_s82s8
-// CHECK64-CXX-SAME: (i64 [[A_COERCE:%.*]]) #[[ATTR0]] {
-// CHECK64-CXX:  entry:
+// CHECK-CXX-LABEL: define dso_local float @_Z7test_s82s8
+// CHECK-CXX-SAME: (float [[TMP0:%.*]]) #[[ATTR0]] {
+// CHECK-CXX:  entry:
 //
 struct s8 

[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

@jacquesguan yes I agree, let's hold off on merging this until that PR is 
merged as it looks like it's quite close.


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[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

I remain concerned about exposing the intrinsics if they're not yet agreed as 
finalised. I see there is now a PR to add them to riscv-c-api doc 
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/47

I'd be OK with merging this now if the intrinsics were temporarily removed, or 
logic were added to gate them in some way (though we don't have precedent on 
the best way to do this I don't think). Otherwise, I'd rather wait until the 
intrinsics are agreed.


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[PATCH] D155668: [RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

Should add a release note as well, but otherwise LGTM. My understanding is that 
all of the intrinsics this exposes have the same level of stability / 
finalisation as the other vector intrinsics, but please let me know if I 
understand incorrectly.


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[PATCH] D155339: Enable zba and zbs for RISCV64 Android

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.

LGTM.


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[PATCH] D125765: [RISCV] Add type aliases float16_t, float32_t and float64_t

[Alex Bradbury via Phabricator via cfe-commits]

asb added a reviewer: eopXD.
asb added a comment.

Adding eop as a reviewer.


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[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

[Alex Bradbury via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG29f630a1ddcb: [RISCV][MC] MC layer support for the 
experimental zacas extension (authored by asb).

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Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoA.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zacas-invalid.s
  llvm/test/MC/RISCV/rv32zacas-valid.s
  llvm/test/MC/RISCV/rv64zacas-invalid.s
  llvm/test/MC/RISCV/rv64zacas-valid.s

Index: llvm/test/MC/RISCV/rv64zacas-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zacas-valid.s
@@ -0,0 +1,51 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zacas -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zacas < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zacas -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+a -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+# Odd register numbers for rd and rs2 are allowed for amocas.d on RV64.
+
+# CHECK-ASM-AND-OBJ: amocas.d a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d a1, a3, (a5)
+# CHECK-ASM-AND-OBJ: amocas.d.aq a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d.aq a1, a3, (a5)
+# CHECK-ASM-AND-OBJ: amocas.d.rl a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d.rl a1, a3, (a5)
+# CHECK-ASM-AND-OBJ: amocas.d.aqrl a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d.aqrl a1, a3, (a5)
+
+# CHECK-ASM-AND-OBJ: amocas.q a0, a2, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc5,0xc5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q a0, a2, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q a0, a2, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc5,0xc5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q a0, a2, 0(a1)
+# CHECK-ASM-AND-OBJ: amocas.q zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q zero, zero, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q.aq zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q.aq zero, zero, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q.rl zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q.rl zero, zero, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q.aqrl zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q.aqrl zero, zero, (a1)
Index: llvm/test/MC/RISCV/rv64zacas-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zacas-invalid.s
@@ -0,0 +1,16 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zacas < %s 2>&1 | FileCheck %s
+
+# Non-zero offsets not supported for the third operand (rs1).
+amocas.w a1, a3, 1(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+amocas.d a1, a3, 2(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+amocas.q a1, a3, 3(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+
+# First and second operands (rd and rs2) of amocas.q must be even.
+amocas.q a1, a2, (a1) # CHECK: :[[@LINE]]:10: error: The destination register must be even.
+amocas.q a0, a1, (a1) # CHECK: :[[@LINE]]:14: error: The source register must be even.
+amocas.q.aq a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: The destination register must be even.
+amocas.q.aq a0, a1, 

[PATCH] D154683: [RISCV] Split __builtin_riscv_brev8 into _32 and _64 builtin.

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D154681: [RISCV] Split __builtin_riscv_xperm4/8 into separate _32 and _64 builtins.

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D154577: [RISCV] Use 'long' in sha512 builtin tests. NFC

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D154567: [RISCV] Use ClangBuiltin in IntrinsicsRISCV.td to map some scalar crypto builtins to IR intrinsic.

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 535372.
asb edited the summary of this revision.
asb added a comment.
Herald added a subscriber: wangpc.

Update to 1.0-rc1 (no code changes needed).


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Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoA.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zacas-invalid.s
  llvm/test/MC/RISCV/rv32zacas-valid.s
  llvm/test/MC/RISCV/rv64zacas-invalid.s
  llvm/test/MC/RISCV/rv64zacas-valid.s

Index: llvm/test/MC/RISCV/rv64zacas-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zacas-valid.s
@@ -0,0 +1,51 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zacas -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zacas < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zacas -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+a -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+# Odd register numbers for rd and rs2 are allowed for amocas.d on RV64.
+
+# CHECK-ASM-AND-OBJ: amocas.d a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d a1, a3, (a5)
+# CHECK-ASM-AND-OBJ: amocas.d.aq a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d.aq a1, a3, (a5)
+# CHECK-ASM-AND-OBJ: amocas.d.rl a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d.rl a1, a3, (a5)
+# CHECK-ASM-AND-OBJ: amocas.d.aqrl a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d.aqrl a1, a3, (a5)
+
+# CHECK-ASM-AND-OBJ: amocas.q a0, a2, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc5,0xc5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q a0, a2, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q a0, a2, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc5,0xc5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q a0, a2, 0(a1)
+# CHECK-ASM-AND-OBJ: amocas.q zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q zero, zero, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q.aq zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q.aq zero, zero, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q.rl zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q.rl zero, zero, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q.aqrl zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q.aqrl zero, zero, (a1)
Index: llvm/test/MC/RISCV/rv64zacas-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zacas-invalid.s
@@ -0,0 +1,16 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zacas < %s 2>&1 | FileCheck %s
+
+# Non-zero offsets not supported for the third operand (rs1).
+amocas.w a1, a3, 1(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+amocas.d a1, a3, 2(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+amocas.q a1, a3, 3(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+
+# First and second operands (rd and rs2) of amocas.q must be even.
+amocas.q a1, a2, (a1) # CHECK: :[[@LINE]]:10: error: The destination register must be even.
+amocas.q a0, a1, (a1) # CHECK: :[[@LINE]]:14: error: The source register must be even.
+amocas.q.aq a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: The destination register must be even.
+amocas.q.aq a0, a1, (a1) # CHECK: :[[@LINE]]:17: error: The source register must be even.
+amocas.q.rl a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: The destination register must be even.
+amocas.q.rl a0, 

[PATCH] D153836: [RISCV] Bump vector crypto to v1.0.0-rc1

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

Agreed that looking at 
https://github.com/riscv/riscv-crypto/compare/v20230531...v20230620 there are 
no changes that need to be reflected on the LLVM side beyond the version bump 
here. LGTM


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[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

[Alex Bradbury via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG6101d720cb49: [RISCV] Relax rules for ordering s/z/x 
prefixed extensions in ISA naming strings (authored by asb).

Changed prior to commit:
  https://reviews.llvm.org/D149246?vs=517106=534930#toc

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Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/riscv-arch.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/unittests/Support/RISCVISAInfoTest.cpp

Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -192,7 +192,7 @@
   EXPECT_EQ(InfoRV64G.getFLen(), 64U);
 }
 
-TEST(ParseArchString, RequiresCanonicalOrderForExtensions) {
+TEST(ParseArchString, RequiresCanonicalOrderForSingleLetterExtensions) {
   EXPECT_EQ(
   toString(RISCVISAInfo::parseArchString("rv64idf", true).takeError()),
   "standard user-level extension not given in canonical order 'f'");
@@ -203,12 +203,10 @@
   toString(
   RISCVISAInfo::parseArchString("rv32i_zfinx_a", true).takeError()),
   "invalid extension prefix 'a'");
-  EXPECT_EQ(
-  toString(RISCVISAInfo::parseArchString("rv64i_svnapot_zicsr", true)
-   .takeError()),
-  "standard user-level extension not given in canonical order 'zicsr'");
+  // Canonical ordering not required for z*, s*, and x* extensions.
   EXPECT_THAT_EXPECTED(
-  RISCVISAInfo::parseArchString("rv64imafdc_zicsr_svnapot", true),
+  RISCVISAInfo::parseArchString(
+  "rv64imafdc_xsfvcp_zicsr_xtheadba_svnapot_zawrs", true),
   Succeeded());
 }
 
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -811,9 +811,9 @@
   // Parse the ISA string containing non-standard user-level
   // extensions, standard supervisor-level extensions and
   // non-standard supervisor-level extensions.
-  // These extensions start with 'z', 's', 'x' prefixes, follow a
-  // canonical order, might have a version number (major, minor)
-  // and are separated by a single underscore '_'.
+  // These extensions start with 'z', 's', 'x' prefixes, might have a version
+  // number (major, minor) and are separated by a single underscore '_'. We do
+  // not enforce a canonical order for them.
   // Set the hardware features for the extensions that are supported.
 
   // Multi-letter extensions are seperated by a single underscore
@@ -822,9 +822,6 @@
   OtherExts.split(Split, '_');
 
   SmallVector AllExts;
-  std::array Prefix{"z", "s", "x"};
-  auto I = Prefix.begin();
-  auto E = Prefix.end();
   if (Split.size() > 1 || Split[0] != "") {
 for (StringRef Ext : Split) {
   if (Ext.empty())
@@ -844,18 +841,6 @@
  "invalid extension prefix '" + Ext + "'");
   }
 
-  // Check ISA extensions are specified in the canonical order.
-  while (I != E && *I != Type)
-++I;
-
-  if (I == E) {
-if (IgnoreUnknown)
-  continue;
-return createStringError(errc::invalid_argument,
- "%s not given in canonical order '%s'",
- Desc.str().c_str(), Ext.str().c_str());
-  }
-
   if (!IgnoreUnknown && Name.size() == Type.size()) {
 return createStringError(errc::invalid_argument,
  "%s name missing after '%s'",
Index: llvm/docs/RISCVUsage.rst
===
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -40,6 +40,8 @@
   users migrate build systems so as not to rely on this.
 * Allowing CSRs to be named without gating on specific extensions.  This
   applies to all CSR names, not just those in zicsr, zicntr, and zihpm.
+* The ordering of ``z*``, ``s*``, and ``x*`` prefixed extension names is not
+  enforced in user-specified ISA naming strings (e.g. ``-march``).
 
 We are actively deciding not to support multiple specification revisions
 at this time. We acknowledge a likely future need, but actively defer the
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -323,8 +323,7 @@
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
 // RV32-X-ORDER: error: invalid arch name 'rv32ixdef_sabc',
-// RV32-X-ORDER: standard supervisor-level extension not given
-// RV32-X-ORDER: in canonical order 'sabc'
+// RV32-X-ORDER  

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.
Herald added a subscriber: wangpc.

All feedback so far has been positive and this has two LGTMs, but I also 
recognise this patch has been left for a while. Heads up that I intend to 
commit this towards the end of the working day Monday UK time unless anyone has 
any objections / concerns.


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[PATCH] D153170: [RISCV] Sort the extensions in SupportedExtensions and SupportedExperimentalExtensions.

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

OK, if this patch is going to verify the table is sorted then 
SupportedExtensions and SupportedExperimentalExtensions probably deserve a 
comment to explicitly note they must be kept in sort order. Otherwise, still 
LGTM.


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[PATCH] D153170: [RISCV] Sort the extensions in SupportedExtensions and SupportedExperimentalExtensions.

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 531244.
asb added a comment.

Rebase and ping.


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Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoA.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zacas-invalid.s
  llvm/test/MC/RISCV/rv32zacas-valid.s
  llvm/test/MC/RISCV/rv64zacas-invalid.s
  llvm/test/MC/RISCV/rv64zacas-valid.s

Index: llvm/test/MC/RISCV/rv64zacas-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zacas-valid.s
@@ -0,0 +1,51 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zacas -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zacas < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zacas -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+a -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+# Odd register numbers for rd and rs2 are allowed for amocas.d on RV64.
+
+# CHECK-ASM-AND-OBJ: amocas.d a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d a1, a3, (a5)
+# CHECK-ASM-AND-OBJ: amocas.d.aq a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d.aq a1, a3, (a5)
+# CHECK-ASM-AND-OBJ: amocas.d.rl a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d.rl a1, a3, (a5)
+# CHECK-ASM-AND-OBJ: amocas.d.aqrl a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d.aqrl a1, a3, (a5)
+
+# CHECK-ASM-AND-OBJ: amocas.q a0, a2, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc5,0xc5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q a0, a2, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q a0, a2, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc5,0xc5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q a0, a2, 0(a1)
+# CHECK-ASM-AND-OBJ: amocas.q zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q zero, zero, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q.aq zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q.aq zero, zero, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q.rl zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q.rl zero, zero, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q.aqrl zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q.aqrl zero, zero, (a1)
Index: llvm/test/MC/RISCV/rv64zacas-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zacas-invalid.s
@@ -0,0 +1,16 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zacas < %s 2>&1 | FileCheck %s
+
+# Non-zero offsets not supported for the third operand (rs1).
+amocas.w a1, a3, 1(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+amocas.d a1, a3, 2(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+amocas.q a1, a3, 3(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+
+# First and second operands (rd and rs2) of amocas.q must be even.
+amocas.q a1, a2, (a1) # CHECK: :[[@LINE]]:10: error: The destination register must be even.
+amocas.q a0, a1, (a1) # CHECK: :[[@LINE]]:14: error: The source register must be even.
+amocas.q.aq a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: The destination register must be even.
+amocas.q.aq a0, a1, (a1) # CHECK: :[[@LINE]]:17: error: The source register must be even.
+amocas.q.rl a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: The destination register must be even.
+amocas.q.rl a0, a1, (a1) # CHECK: :[[@LINE]]:17: error: The source register must be even.
+amocas.q.aqrl a1, a2, (a1) # 

[PATCH] D152279: [Driver] Default -msmall-data-limit= to 0

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

In D152279#4415974 , @MaskRay wrote:

> However, RISC-V `-msmall-data-limit=` is probably a case warranting a 
> difference.
> The global pointer relaxation has a very limited value (benchmarked by 
> multiple parties, including a party which implemented this feature in the GNU 
> toolchain: even they can only say the optimization only applies to very 
> specific projects).
> The default value is confusing: as explained by the summary.
>
> I suspect that `-msmall-data-limit=8` is too conservative, maybe 16 would be 
> better, I don't know. I think global pointer relaxation users should toggle 
> this by themselves, not relying on `0` or `8` default decided by a bunch of 
> strange conditions.

I don't disagree that the small data limit being 8 rather than something else 
doesn't seem to be particularly well motivated, but I understand that the case 
where the option does make a difference is on embedded targets (I think the 
data that was shared before was for SPEC, but could be wrong?). I think we can 
generally expect more willingness for people targeting embedded systems to 
explore different compiler flags, but just matching gcc does feel like a better 
default. What do you think about keeping the default for bare metal targets?


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[PATCH] D152627: [RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM. llvm/test/Bitcode is the other place the autoupgrade tests could go, but 
it looks like it's not used any more frequently for such tests than 
llvm/test/CodeGen/$tgt/.


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[PATCH] D152628: [RISCV] Add __builtin_riscv_zip/unzip for Zbkb to match gcc.

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

I'm not super familiar with these builtins so this might be a silly question 
why are the new builtins added in this patch LiLi (long int) rather than ZiZi 
(int32_t) like the old `_32` suffixed builtins?


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[PATCH] D152627: [RISCV] Change the immediate argument to Zvk intrinsics/builtins to i8.

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

The patch title should indicate "from i8 to i32" or similar?


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[PATCH] D152279: [Driver] Default -msmall-data-limit= to 0

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

One of the key things we've been discussing on this at the LLVM call is that we 
probably want to keep the small data limit for embedded targets.


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[PATCH] D152279: [Driver] Default -msmall-data-limit= to 0

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

In D152279#4403940 , @phosek wrote:

> We're planning to default to `-msmall-data-limit=0` for Android and Fuchsia 
> so I'm supportive of this change because it means less complexity and fewer 
> differences between platforms.
>
> I think it would be worth bringing up this topic at the RISC-V LLVM sync-up 
> call tomorrow.

Sounds good, I'll put it on the agenda.


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[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

@jacquesguan I'm not sure on the standardisation process or status for these 
intrinsics. Perhaps @kito-cheng has an idea?


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[PATCH] D151867: [Clang][RISCV] Make generic clz/ctz builtins defined for zero on RISCV targets.

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

Could you please post a separate patch that has a test that will show the 
codegen change (and demonstrate how it is unchanged when zbb or xtheadbb)?


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[PATCH] D151547: [RISCV] Remove experimental for zihintntl.

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

Is the __riscv_ntl_* interface finalised and agreed? I'm wary of repeating the 
mistake we made with the V extension where we exposed intrinsics that weren't 
yet finalised.


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[PATCH] D150926: [RISCV] Support LMUL!=1 for __attribute__((riscv_rvv_vector_bits(N)))

[Alex Bradbury via Phabricator via cfe-commits]

asb added inline comments.



Comment at: clang/include/clang/Basic/AttrDocs.td:2347
 
-Only ``*m1_t`` (LMUL=1) types are supported at this time.
+For types where LMUL!=1, ``__riscv_v_fixed_vlen`` needs to be scaled by the 
LMULo
+of the type before passing to the attribute.

LMULo -> LMUL


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[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

[Alex Bradbury via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa1455de74d95: [RISCV][MC] Add support for experimental 
Zvfbfwma extension (authored by asb).

Changed prior to commit:
  https://reviews.llvm.org/D147612?vs=523018=523771#toc

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Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rvv/zvfbfwma-invalid.s
  llvm/test/MC/RISCV/rvv/zvfbfwma.s

Index: llvm/test/MC/RISCV/rvv/zvfbfwma.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvfbfwma.s
@@ -0,0 +1,68 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfwma - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfwma - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: vfwmaccbf16.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 14 4a 8c 
+vfwmaccbf16.vv v8, v20, v4, v0.t
+
+# CHECK-INST: vfwmaccbf16.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 14 4a 8e 
+vfwmaccbf16.vv v8, v20, v4
+
+# CHECK-INST: vfwmaccbf16.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 54 45 8c 
+vfwmaccbf16.vf v8, fa0, v4, v0.t
+
+# CHECK-INST: vfwmaccbf16.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 54 45 8e 
+vfwmaccbf16.vf v8, fa0, v4
+
+# Check scalar half FP load/store/move included in this extension.
+
+# CHECK-INST: flh ft0, 12(a0)
+# CHECK-ENCODING: [0x07,0x10,0xc5,0x00]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 07 10 c5 00 
+flh f0, 12(a0)
+
+# CHECK-INST: fsh ft6, 2047(s4)
+# CHECK-ENCODING: [0xa7,0x1f,0x6a,0x7e]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: a7 1f 6a 7e 
+fsh f6, 2047(s4)
+
+# CHECK-INST: fmv.x.h a2, fs7
+# CHECK-ENCODING: [0x53,0x86,0x0b,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 53 86 0b e4 
+fmv.x.h a2, fs7
+
+# CHECK-INST: fmv.h.x ft1, a6
+# CHECK-ENCODING: [0xd3,0x00,0x08,0xf4]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: d3 00 08 f4 
+fmv.h.x ft1, a6
Index: llvm/test/MC/RISCV/rvv/zvfbfwma-invalid.s

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

[Alex Bradbury via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGb18a81966499: [RISCV][MC] Add support for experimental 
Zvfbfmin extension (authored by asb).

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Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvfbfmin.s

Index: llvm/test/MC/RISCV/rvv/zvfbfmin.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvfbfmin.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfmin - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfmin - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: vfncvtbf16.f.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x4e,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 4e 48 
+vfncvtbf16.f.f.w v8, v4, v0.t
+
+# CHECK-INST: vfncvtbf16.f.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x4e,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 4e 4a 
+vfncvtbf16.f.f.w v8, v4
+
+# CHECK-INST: vfwcvtbf16.f.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x46,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 46 48 
+vfwcvtbf16.f.f.v v8, v4, v0.t
+
+# CHECK-INST: vfwcvtbf16.f.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x46,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 46 4a 
+vfwcvtbf16.f.f.v v8, v4
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -266,3 +266,6 @@
 
 .attribute arch, "rv32if_zfbfmin0p6"
 # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p6"
+
+.attribute arch, "rv32if_zvfbfmin0p6"
+# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -75,6 +75,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -157,6 +158,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+f,+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
 
 ; CHECK: .attribute 4, 16
 
@@ -234,6 +236,7 @@
 ; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
 ; RV32SSAIA: 

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

[Alex Bradbury via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG35ff5eba1646: [RISCV][MC] Add support for experimental 
Zfbfmin extension (authored by asb).

Repository:
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Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zfbfmin-invalid.s
  llvm/test/MC/RISCV/rv32zfbfmin-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s

Index: llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
===
--- llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
+++ llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
@@ -1,7 +1,7 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zhinxmin %s 2>&1 | FileCheck %s
 
 # Not support float registers
-flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
+flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
 
 # Invalid instructions
 fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv64zhinx-invalid.s
===
--- llvm/test/MC/RISCV/rv64zhinx-invalid.s
+++ llvm/test/MC/RISCV/rv64zhinx-invalid.s
@@ -1,7 +1,7 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s
 
 # Not support float registers
-flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
+flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
 
 # Invalid instructions
 fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv32zfbfmin-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfbfmin-valid.s
@@ -0,0 +1,56 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfbfmin,+f -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfbfmin,+f -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfbfmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfbfmin,+f -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfbfmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfbfmin,+f -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: flh ft0, 12(a0)
+# CHECK-ASM: encoding: [0x07,0x10,0xc5,0x00]
+flh f0, 12(a0)
+# CHECK-ASM-AND-OBJ: flh ft1, 4(ra)
+# CHECK-ASM: encoding: [0x87,0x90,0x40,0x00]
+flh f1, +4(ra)
+# CHECK-ASM-AND-OBJ: flh ft2, -2048(a3)
+# CHECK-ASM: encoding: [0x07,0x91,0x06,0x80]
+flh f2, -2048(x13)
+# CHECK-ASM-AND-OBJ: flh ft3, -2048(s1)
+# CHECK-ASM: encoding: [0x87,0x91,0x04,0x80]
+flh f3, %lo(2048)(s1)
+# CHECK-ASM-AND-OBJ: flh ft4, 2047(s2)
+# CHECK-ASM: encoding: [0x07,0x12,0xf9,0x7f]
+flh f4, 2047(s2)
+# CHECK-ASM-AND-OBJ: flh ft5, 0(s3)
+# CHECK-ASM: encoding: [0x87,0x92,0x09,0x00]
+flh f5, 0(s3)
+
+# CHECK-ASM-AND-OBJ: fsh ft6, 2047(s4)
+# CHECK-ASM: encoding: [0xa7,0x1f,0x6a,0x7e]
+fsh f6, 2047(s4)
+# CHECK-ASM-AND-OBJ: fsh ft7, -2048(s5)
+# CHECK-ASM: encoding: [0x27,0x90,0x7a,0x80]
+fsh f7, -2048(s5)
+# CHECK-ASM-AND-OBJ: fsh fs0, -2048(s6)
+# CHECK-ASM: encoding: [0x27,0x10,0x8b,0x80]
+fsh f8, %lo(2048)(s6)
+# CHECK-ASM-AND-OBJ: fsh fs1, 999(s7)
+# CHECK-ASM: encoding: [0xa7,0x93,0x9b,0x3e]
+fsh f9, 999(s7)
+
+# CHECK-ASM-AND-OBJ: fmv.x.h a2, fs7
+# CHECK-ASM: encoding: [0x53,0x86,0x0b,0xe4]
+fmv.x.h a2, fs7
+# CHECK-ASM-AND-OBJ: fmv.h.x ft1, a6
+# CHECK-ASM: encoding: [0xd3,0x00,0x08,0xf4]
+fmv.h.x ft1, a6
+
+# CHECK-ASM-AND-OBJ: fcvt.s.bf16 fa0, ft0
+# CHECK-ASM: encoding: [0x53,0x75,0x60,0x40]
+fcvt.s.bf16 fa0, ft0
+# CHECK-ASM-AND-OBJ: fcvt.bf16.s ft2, fa2
+# 

[PATCH] D150777: [clang][RISCV] Set HasLegalHalfType to true if zhinx is enabled

[Alex Bradbury via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG8e8237686346: [clang][RISCV] Set HasLegalHalfType to true if 
zhinx is enabled (authored by asb).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150777/new/

https://reviews.llvm.org/D150777

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/Float16-arith.c


Index: clang/test/CodeGen/RISCV/Float16-arith.c
===
--- clang/test/CodeGen/RISCV/Float16-arith.c
+++ clang/test/CodeGen/RISCV/Float16-arith.c
@@ -42,12 +42,9 @@
 // ZHINX-SAME: () #[[ATTR0:[0-9]+]] {
 // ZHINX-NEXT:  entry:
 // ZHINX-NEXT:[[TMP0:%.*]] = load half, ptr @y, align 2
-// ZHINX-NEXT:[[EXT:%.*]] = fpext half [[TMP0]] to float
 // ZHINX-NEXT:[[TMP1:%.*]] = load half, ptr @z, align 2
-// ZHINX-NEXT:[[EXT1:%.*]] = fpext half [[TMP1]] to float
-// ZHINX-NEXT:[[ADD:%.*]] = fadd float [[EXT]], [[EXT1]]
-// ZHINX-NEXT:[[UNPROMOTION:%.*]] = fptrunc float [[ADD]] to half
-// ZHINX-NEXT:store half [[UNPROMOTION]], ptr @x, align 2
+// ZHINX-NEXT:[[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// ZHINX-NEXT:store half [[ADD]], ptr @x, align 2
 // ZHINX-NEXT:ret void
 //
 void f16_add() {
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -320,7 +320,7 @@
   if (ABI.empty())
 ABI = ISAInfo->computeDefaultABI().str();
 
-  if (ISAInfo->hasExtension("zfh"))
+  if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
 HasLegalHalfType = true;
 
   return true;


Index: clang/test/CodeGen/RISCV/Float16-arith.c
===
--- clang/test/CodeGen/RISCV/Float16-arith.c
+++ clang/test/CodeGen/RISCV/Float16-arith.c
@@ -42,12 +42,9 @@
 // ZHINX-SAME: () #[[ATTR0:[0-9]+]] {
 // ZHINX-NEXT:  entry:
 // ZHINX-NEXT:[[TMP0:%.*]] = load half, ptr @y, align 2
-// ZHINX-NEXT:[[EXT:%.*]] = fpext half [[TMP0]] to float
 // ZHINX-NEXT:[[TMP1:%.*]] = load half, ptr @z, align 2
-// ZHINX-NEXT:[[EXT1:%.*]] = fpext half [[TMP1]] to float
-// ZHINX-NEXT:[[ADD:%.*]] = fadd float [[EXT]], [[EXT1]]
-// ZHINX-NEXT:[[UNPROMOTION:%.*]] = fptrunc float [[ADD]] to half
-// ZHINX-NEXT:store half [[UNPROMOTION]], ptr @x, align 2
+// ZHINX-NEXT:[[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// ZHINX-NEXT:store half [[ADD]], ptr @x, align 2
 // ZHINX-NEXT:ret void
 //
 void f16_add() {
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -320,7 +320,7 @@
   if (ABI.empty())
 ABI = ISAInfo->computeDefaultABI().str();
 
-  if (ISAInfo->hasExtension("zfh"))
+  if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
 HasLegalHalfType = true;
 
   return true;
___
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cfe-commits@lists.llvm.org
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[PATCH] D150777: [clang][RISCV] Set HasLegalHalfType to true if zhinx is enabled

[Alex Bradbury via Phabricator via cfe-commits]

asb created this revision.
asb added reviewers: craig.topper, kito-cheng, realqhc.
Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, 
frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, 
psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, 
johnrusso, rbar, arichardson.
Herald added a project: All.
asb requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: clang.

Now that codegen support for zhinx in landed (D149811 
), we should set HasLegalHalfType=true for 
zhinx (see D145071  for the patch doing this 
for zfh).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D150777

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/Float16-arith.c


Index: clang/test/CodeGen/RISCV/Float16-arith.c
===
--- clang/test/CodeGen/RISCV/Float16-arith.c
+++ clang/test/CodeGen/RISCV/Float16-arith.c
@@ -42,12 +42,9 @@
 // ZHINX-SAME: () #[[ATTR0:[0-9]+]] {
 // ZHINX-NEXT:  entry:
 // ZHINX-NEXT:[[TMP0:%.*]] = load half, ptr @y, align 2
-// ZHINX-NEXT:[[EXT:%.*]] = fpext half [[TMP0]] to float
 // ZHINX-NEXT:[[TMP1:%.*]] = load half, ptr @z, align 2
-// ZHINX-NEXT:[[EXT1:%.*]] = fpext half [[TMP1]] to float
-// ZHINX-NEXT:[[ADD:%.*]] = fadd float [[EXT]], [[EXT1]]
-// ZHINX-NEXT:[[UNPROMOTION:%.*]] = fptrunc float [[ADD]] to half
-// ZHINX-NEXT:store half [[UNPROMOTION]], ptr @x, align 2
+// ZHINX-NEXT:[[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// ZHINX-NEXT:store half [[ADD]], ptr @x, align 2
 // ZHINX-NEXT:ret void
 //
 void f16_add() {
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -320,7 +320,7 @@
   if (ABI.empty())
 ABI = ISAInfo->computeDefaultABI().str();
 
-  if (ISAInfo->hasExtension("zfh"))
+  if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
 HasLegalHalfType = true;
 
   return true;


Index: clang/test/CodeGen/RISCV/Float16-arith.c
===
--- clang/test/CodeGen/RISCV/Float16-arith.c
+++ clang/test/CodeGen/RISCV/Float16-arith.c
@@ -42,12 +42,9 @@
 // ZHINX-SAME: () #[[ATTR0:[0-9]+]] {
 // ZHINX-NEXT:  entry:
 // ZHINX-NEXT:[[TMP0:%.*]] = load half, ptr @y, align 2
-// ZHINX-NEXT:[[EXT:%.*]] = fpext half [[TMP0]] to float
 // ZHINX-NEXT:[[TMP1:%.*]] = load half, ptr @z, align 2
-// ZHINX-NEXT:[[EXT1:%.*]] = fpext half [[TMP1]] to float
-// ZHINX-NEXT:[[ADD:%.*]] = fadd float [[EXT]], [[EXT1]]
-// ZHINX-NEXT:[[UNPROMOTION:%.*]] = fptrunc float [[ADD]] to half
-// ZHINX-NEXT:store half [[UNPROMOTION]], ptr @x, align 2
+// ZHINX-NEXT:[[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// ZHINX-NEXT:store half [[ADD]], ptr @x, align 2
 // ZHINX-NEXT:ret void
 //
 void f16_add() {
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -320,7 +320,7 @@
   if (ABI.empty())
 ABI = ISAInfo->computeDefaultABI().str();
 
-  if (ISAInfo->hasExtension("zfh"))
+  if (ISAInfo->hasExtension("zfh") || ISAInfo->hasExtension("zhinx"))
 HasLegalHalfType = true;
 
   return true;
___
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cfe-commits@lists.llvm.org
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[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 523026.
asb added a comment.

Rebase and ping (also checked there have been no relevant spec changes since 
this patch was posted).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D149248/new/

https://reviews.llvm.org/D149248

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoA.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zacas-invalid.s
  llvm/test/MC/RISCV/rv32zacas-valid.s
  llvm/test/MC/RISCV/rv64zacas-invalid.s
  llvm/test/MC/RISCV/rv64zacas-valid.s

Index: llvm/test/MC/RISCV/rv64zacas-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zacas-valid.s
@@ -0,0 +1,51 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zacas -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zacas < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zacas -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+a -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+# Odd register numbers for rd and rs2 are allowed for amocas.d on RV64.
+
+# CHECK-ASM-AND-OBJ: amocas.d a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d a1, a3, (a5)
+# CHECK-ASM-AND-OBJ: amocas.d.aq a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d.aq a1, a3, (a5)
+# CHECK-ASM-AND-OBJ: amocas.d.rl a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d.rl a1, a3, (a5)
+# CHECK-ASM-AND-OBJ: amocas.d.aqrl a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d.aqrl a1, a3, (a5)
+
+# CHECK-ASM-AND-OBJ: amocas.q a0, a2, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc5,0xc5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q a0, a2, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q a0, a2, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc5,0xc5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q a0, a2, 0(a1)
+# CHECK-ASM-AND-OBJ: amocas.q zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q zero, zero, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q.aq zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q.aq zero, zero, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q.rl zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q.rl zero, zero, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q.aqrl zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q.aqrl zero, zero, (a1)
Index: llvm/test/MC/RISCV/rv64zacas-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zacas-invalid.s
@@ -0,0 +1,16 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zacas < %s 2>&1 | FileCheck %s
+
+# Non-zero offsets not supported for the third operand (rs1).
+amocas.w a1, a3, 1(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+amocas.d a1, a3, 2(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+amocas.q a1, a3, 3(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+
+# First and second operands (rd and rs2) of amocas.q must be even.
+amocas.q a1, a2, (a1) # CHECK: :[[@LINE]]:10: error: The destination register must be even.
+amocas.q a0, a1, (a1) # CHECK: :[[@LINE]]:14: error: The source register must be even.
+amocas.q.aq a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: The destination register must be even.
+amocas.q.aq a0, a1, (a1) # CHECK: :[[@LINE]]:17: error: The source register must be even.
+amocas.q.rl a1, a2, (a1) # CHECK: :[[@LINE]]:13: error: The destination register must be even.
+amocas.q.rl a0, a1, (a1) # CHECK: 

[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 523018.
asb edited the summary of this revision.
asb added a comment.

Now updated to version 0.6 of the spec (was previously blocked on a new PDF 
being tagged and uploaded).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147612/new/

https://reviews.llvm.org/D147612

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rvv/zvfbfwma-invalid.s
  llvm/test/MC/RISCV/rvv/zvfbfwma.s

Index: llvm/test/MC/RISCV/rvv/zvfbfwma.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvfbfwma.s
@@ -0,0 +1,68 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfwma - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfwma - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: vfwmaccbf16.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 14 4a 8c 
+vfwmaccbf16.vv v8, v20, v4, v0.t
+
+# CHECK-INST: vfwmaccbf16.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 14 4a 8e 
+vfwmaccbf16.vv v8, v20, v4
+
+# CHECK-INST: vfwmaccbf16.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 54 45 8c 
+vfwmaccbf16.vf v8, fa0, v4, v0.t
+
+# CHECK-INST: vfwmaccbf16.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 54 45 8e 
+vfwmaccbf16.vf v8, fa0, v4
+
+# Check scalar half FP load/store/move included in this extension.
+
+# CHECK-INST: flh ft0, 12(a0)
+# CHECK-ENCODING: [0x07,0x10,0xc5,0x00]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 07 10 c5 00 
+flh f0, 12(a0)
+
+# CHECK-INST: fsh ft6, 2047(s4)
+# CHECK-ENCODING: [0xa7,0x1f,0x6a,0x7e]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: a7 1f 6a 7e 
+fsh f6, 2047(s4)
+
+# CHECK-INST: fmv.x.h a2, fs7
+# CHECK-ENCODING: [0x53,0x86,0x0b,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 53 86 0b e4 
+fmv.x.h a2, fs7
+
+# CHECK-INST: fmv.h.x ft1, a6
+# CHECK-ENCODING: [0xd3,0x00,0x08,0xf4]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: d3 00 08 f4 
+fmv.h.x ft1, a6
Index: llvm/test/MC/RISCV/rvv/zvfbfwma-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvfbfwma-invalid.s
@@ -0,0 +1,11 @@
+# RUN: not llvm-mc -triple riscv32 

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 523017.
asb edited the summary of this revision.
asb added a comment.

Now updated to version 0.6 of the specification (was previously blocked on a 
new PDF being tagged).


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147611/new/

https://reviews.llvm.org/D147611

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvfbfmin.s

Index: llvm/test/MC/RISCV/rvv/zvfbfmin.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvfbfmin.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfmin - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfmin - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: vfncvtbf16.f.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x4e,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 4e 48 
+vfncvtbf16.f.f.w v8, v4, v0.t
+
+# CHECK-INST: vfncvtbf16.f.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x4e,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 4e 4a 
+vfncvtbf16.f.f.w v8, v4
+
+# CHECK-INST: vfwcvtbf16.f.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x46,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 46 48 
+vfwcvtbf16.f.f.v v8, v4, v0.t
+
+# CHECK-INST: vfwcvtbf16.f.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x46,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 46 4a 
+vfwcvtbf16.f.f.v v8, v4
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -266,3 +266,6 @@
 
 .attribute arch, "rv32if_zfbfmin0p6"
 # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p6"
+
+.attribute arch, "rv32if_zvfbfmin0p6"
+# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -75,6 +75,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SMAIA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV32SSAIA %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -157,6 +158,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SMAIA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssaia %s -o - | FileCheck --check-prefixes=CHECK,RV64SSAIA %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+f,+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
 
 ; CHECK: .attribute 4, 16
 
@@ -234,6 +236,7 @@
 ; RV32SMAIA: .attribute 5, "rv32i2p1_smaia1p0"
 ; RV32SSAIA: .attribute 5, 

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 523016.
asb edited the summary of this revision.
asb added a comment.

Now updated to reflect v0.6 of the spec and should be ready for final review 
and merge https://github.com/riscv/riscv-bfloat16/releases/tag/main


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147610/new/

https://reviews.llvm.org/D147610

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zfbfmin-invalid.s
  llvm/test/MC/RISCV/rv32zfbfmin-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s

Index: llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
===
--- llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
+++ llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
@@ -1,7 +1,7 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zhinxmin %s 2>&1 | FileCheck %s
 
 # Not support float registers
-flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
+flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
 
 # Invalid instructions
 fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv64zhinx-invalid.s
===
--- llvm/test/MC/RISCV/rv64zhinx-invalid.s
+++ llvm/test/MC/RISCV/rv64zhinx-invalid.s
@@ -1,7 +1,7 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s
 
 # Not support float registers
-flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
+flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
 
 # Invalid instructions
 fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv32zfbfmin-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfbfmin-valid.s
@@ -0,0 +1,56 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfbfmin,+f -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfbfmin,+f -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfbfmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfbfmin,+f -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfbfmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfbfmin,+f -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: flh ft0, 12(a0)
+# CHECK-ASM: encoding: [0x07,0x10,0xc5,0x00]
+flh f0, 12(a0)
+# CHECK-ASM-AND-OBJ: flh ft1, 4(ra)
+# CHECK-ASM: encoding: [0x87,0x90,0x40,0x00]
+flh f1, +4(ra)
+# CHECK-ASM-AND-OBJ: flh ft2, -2048(a3)
+# CHECK-ASM: encoding: [0x07,0x91,0x06,0x80]
+flh f2, -2048(x13)
+# CHECK-ASM-AND-OBJ: flh ft3, -2048(s1)
+# CHECK-ASM: encoding: [0x87,0x91,0x04,0x80]
+flh f3, %lo(2048)(s1)
+# CHECK-ASM-AND-OBJ: flh ft4, 2047(s2)
+# CHECK-ASM: encoding: [0x07,0x12,0xf9,0x7f]
+flh f4, 2047(s2)
+# CHECK-ASM-AND-OBJ: flh ft5, 0(s3)
+# CHECK-ASM: encoding: [0x87,0x92,0x09,0x00]
+flh f5, 0(s3)
+
+# CHECK-ASM-AND-OBJ: fsh ft6, 2047(s4)
+# CHECK-ASM: encoding: [0xa7,0x1f,0x6a,0x7e]
+fsh f6, 2047(s4)
+# CHECK-ASM-AND-OBJ: fsh ft7, -2048(s5)
+# CHECK-ASM: encoding: [0x27,0x90,0x7a,0x80]
+fsh f7, -2048(s5)
+# CHECK-ASM-AND-OBJ: fsh fs0, -2048(s6)
+# CHECK-ASM: encoding: [0x27,0x10,0x8b,0x80]
+fsh f8, %lo(2048)(s6)
+# CHECK-ASM-AND-OBJ: fsh fs1, 999(s7)
+# CHECK-ASM: encoding: [0xa7,0x93,0x9b,0x3e]
+fsh f9, 999(s7)
+
+# CHECK-ASM-AND-OBJ: fmv.x.h a2, fs7
+# CHECK-ASM: encoding: [0x53,0x86,0x0b,0xe4]
+fmv.x.h a2, fs7
+# CHECK-ASM-AND-OBJ: fmv.h.x ft1, a6
+# CHECK-ASM: encoding: [0xd3,0x00,0x08,0xf4]
+fmv.h.x ft1, a6
+
+# CHECK-ASM-AND-OBJ: fcvt.s.bf16 fa0, ft0
+# CHECK-ASM: encoding: [0x53,0x75,0x60,0x40]
+fcvt.s.bf16 fa0, ft0
+# CHECK-ASM-AND-OBJ: 

[PATCH] D128612: RISC-V big-endian support implementation

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

In D128612#4349259 , @djtodoro wrote:

> In D128612#4345912 , @asb wrote:
>
>> In D128612#4337037 , @djtodoro 
>> wrote:
>>
>>> Hi! I am wondering if someone knows what is the status of this.
>>
>> I've not seen any further progress. I think it needs at a minimum a PR 
>> against the psABI doc for big endian that we can review against.
>
> OK. Can you please share with me the GCC PR, so I can take a look how it 
> should be done :)

Based on comments here it sounds like GCC merged some level of support without 
submitting corresponding changes to the psABI. I don't have those patches to 
hand, but you can probably find them on the GCC patches list. I think we've had 
enough unexpected compatibility issues by now that it's not really justifiable 
to merge something that's meant to be a standard ABI without having the 
corresponding psABI patch (even if it appears simple). I don't think anyone has 
posted such a psABI patch but there is/was a tracking issue for it on the psABI 
repo.

@kito-cheng is the bigendian RISC-V work in GCC still active at all? I'm 
wondering if there's a connection you could help make for Djordje.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D128612: RISC-V big-endian support implementation

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

Thanks for this patch Guy. As just discussed in the RISC-V sync-up call, it 
would be helpful from a review perspective to write down at least a simple 
plain-text description of the changes to the psABI doc needed to reflect the BE 
ABI implemented by GCC (and soon LLVM), perhaps in an issue.

I think this patch is lacking some test coverage around things like fixup 
handling (e.g. the logic to swap fixups).

In D128612#4337037 , @djtodoro wrote:

> Hi! I am wondering if someone knows what is the status of this.

I've not seen any further progress. I think it needs at a minimum a PR against 
the psABI doc for big endian that we can review against.


Repository:
  rG LLVM Github Monorepo

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[PATCH] D145071: [clang][RISCV] Set HasLegalHalfType to true if zfh is enabled

[Alex Bradbury via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG560065b6ecd5: [clang][RISCV] Set HasLegalHalfType to true if 
zfh is enabled (authored by asb).
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Changed prior to commit:
  https://reviews.llvm.org/D145071?vs=501507=519825#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D145071/new/

https://reviews.llvm.org/D145071

Files:
  clang/lib/Basic/Targets/RISCV.cpp
  clang/test/CodeGen/RISCV/Float16-arith.c


Index: clang/test/CodeGen/RISCV/Float16-arith.c
===
--- clang/test/CodeGen/RISCV/Float16-arith.c
+++ clang/test/CodeGen/RISCV/Float16-arith.c
@@ -11,8 +11,7 @@
 _Float16 x, y, z;
 
 // With no native half type support (no zfh), f16 will be promoted to f32.
-// With zfh, it shouldn't be (FIXME: set HasLegalHalfType = true in order to
-// get this behaviour for zfh).
+// With zfh, it shouldn't be.
 
 // NOZFH-LABEL: define dso_local void @f16_add
 // NOZFH-SAME: () #[[ATTR0:[0-9]+]] {
@@ -30,12 +29,9 @@
 // ZFH-SAME: () #[[ATTR0:[0-9]+]] {
 // ZFH-NEXT:  entry:
 // ZFH-NEXT:[[TMP0:%.*]] = load half, ptr @y, align 2
-// ZFH-NEXT:[[EXT:%.*]] = fpext half [[TMP0]] to float
 // ZFH-NEXT:[[TMP1:%.*]] = load half, ptr @z, align 2
-// ZFH-NEXT:[[EXT1:%.*]] = fpext half [[TMP1]] to float
-// ZFH-NEXT:[[ADD:%.*]] = fadd float [[EXT]], [[EXT1]]
-// ZFH-NEXT:[[UNPROMOTION:%.*]] = fptrunc float [[ADD]] to half
-// ZFH-NEXT:store half [[UNPROMOTION]], ptr @x, align 2
+// ZFH-NEXT:[[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// ZFH-NEXT:store half [[ADD]], ptr @x, align 2
 // ZFH-NEXT:ret void
 //
 void f16_add() {
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -320,6 +320,9 @@
   if (ABI.empty())
 ABI = ISAInfo->computeDefaultABI().str();
 
+  if (ISAInfo->hasExtension("zfh"))
+HasLegalHalfType = true;
+
   return true;
 }
 


Index: clang/test/CodeGen/RISCV/Float16-arith.c
===
--- clang/test/CodeGen/RISCV/Float16-arith.c
+++ clang/test/CodeGen/RISCV/Float16-arith.c
@@ -11,8 +11,7 @@
 _Float16 x, y, z;
 
 // With no native half type support (no zfh), f16 will be promoted to f32.
-// With zfh, it shouldn't be (FIXME: set HasLegalHalfType = true in order to
-// get this behaviour for zfh).
+// With zfh, it shouldn't be.
 
 // NOZFH-LABEL: define dso_local void @f16_add
 // NOZFH-SAME: () #[[ATTR0:[0-9]+]] {
@@ -30,12 +29,9 @@
 // ZFH-SAME: () #[[ATTR0:[0-9]+]] {
 // ZFH-NEXT:  entry:
 // ZFH-NEXT:[[TMP0:%.*]] = load half, ptr @y, align 2
-// ZFH-NEXT:[[EXT:%.*]] = fpext half [[TMP0]] to float
 // ZFH-NEXT:[[TMP1:%.*]] = load half, ptr @z, align 2
-// ZFH-NEXT:[[EXT1:%.*]] = fpext half [[TMP1]] to float
-// ZFH-NEXT:[[ADD:%.*]] = fadd float [[EXT]], [[EXT1]]
-// ZFH-NEXT:[[UNPROMOTION:%.*]] = fptrunc float [[ADD]] to half
-// ZFH-NEXT:store half [[UNPROMOTION]], ptr @x, align 2
+// ZFH-NEXT:[[ADD:%.*]] = fadd half [[TMP0]], [[TMP1]]
+// ZFH-NEXT:store half [[ADD]], ptr @x, align 2
 // ZFH-NEXT:ret void
 //
 void f16_add() {
Index: clang/lib/Basic/Targets/RISCV.cpp
===
--- clang/lib/Basic/Targets/RISCV.cpp
+++ clang/lib/Basic/Targets/RISCV.cpp
@@ -320,6 +320,9 @@
   if (ABI.empty())
 ABI = ISAInfo->computeDefaultABI().str();
 
+  if (ISAInfo->hasExtension("zfh"))
+HasLegalHalfType = true;
+
   return true;
 }
 
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[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

Just noting for posterity that we discussed this at last week's RISC-V sync-up 
call and I think the tentative conclusion (there weren't particularly strong 
views) was that experiments CSRs should really be gated by 
-menable-experimental-extensions, with the CSR names gated so as to avoid the 
issues mentioned here.


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[PATCH] D149314: [RISCV] Remove support for attribute interrupt("user").

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

In D149314#4302312 , @reames wrote:

> In D149314#4302300 , @aaron.ballman 
> wrote:
>
>> In D149314#4302266 , @asb wrote:
>>
>>> In D149314#4302203 , 
>>> @aaron.ballman wrote:
>>>
 Is this a potentially breaking change that we need to call out for users 
 to be aware of?
>>>
>>> We should mention this in the Clang release notes I think.
>>
>> Beyond that, we've got a process for what to do when considering potentially 
>> breaking changes, we should be following that: 
>> https://llvm.org/docs/DeveloperPolicy.html#making-potentially-breaking-changes
>>  Also, if we're all agreed this is potentially breaking, it really should 
>> have more review time and buy-in from the code owner.
>
> I don't think this change should count as "potentially breaking" in the sense 
> of that document.  We're talking about an experimental feature for an 
> experimental ISA extension which never got to ratification.  There's no 
> hardware in the wild which implements this (to my knowledge).  Given the 
> churn on the RISCV extension side, we've adopted a policy for experimental 
> extensions (https://llvm.org/docs/RISCVUsage.html#experimental-extensions) 
> which offers much less in the way of support.  I think we should release note 
> it just to be friendly, but the process described in your link is significant 
> overkill.

+1 on this. The upstream (RISC-V side) process for the ISA extension lifecycle 
and their ratification is now properly established, and we gate 
not-yet-ratified things behind `-menable-experimental-extensions` going 
forward. This review perhaps could have been held open a bit longer to check 
there's no concerns, and thanks to Aaron for raising the question. But I think 
a release note only is the appropriate option here.


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[PATCH] D149314: [RISCV] Remove support for attribute interrupt("user").

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

In D149314#4302203 , @aaron.ballman 
wrote:

> Is this a potentially breaking change that we need to call out for users to 
> be aware of?

We should mention this in the Clang release notes I think.


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[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

FWIW, I've reviewed the CSR numbers vs the spec so LGTM from that perspective.


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[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

In D148066#4294924 , @kito-cheng 
wrote:

>> My concern would be that as we don't gate CSR names on enabling the relevant 
>> extension, people could start using CSR names and encodings that could 
>> change, without opting in via -menable-experimental-extensions, perhaps not 
>> realising that they're using the unratified version. OTOH, you could argue 
>> it was user error from the start by not trying to specify all the needed 
>> extensions in the ISA naming string.
>
> We decide don't gate CSR before, but I am wondering maybe we should gate 
> those CSR if they are defined by a unratified/experimental ext., and remove 
> the checking once it ratified, since it might change the name or CSR number 
> before ratified.

That's definitely a risk, but at least when people try to do the "right" thing 
and specify the extension name in the ISA string, they'll quickly find out that 
the version supported in the compiler is experimental. Given the cost of 
marking such CSR extensions as experimental is near-zero, I think we might as 
well. I agree gating the CSR names might also make sense, but then we're back 
to the effort of testing this. I think our conclusions before were that nobody 
is particularly opposed to doing finer grained control of CSRs for new 
extensions at least (it's more problematic for the older CSRs given spec 
changes to move CSRs to separate extensions), so I think it would be find if 
someone wanted to implement that. I don't think we need that as a pre-requisite 
for this patch though, IMHO.


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[PATCH] D138810: [RISCV] Support vector crypto extension C intrinsics

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

I just wanted to check on whether this is ready to review? Also, to what degree 
are these intrinsics standardised and where is the relevant specification for 
them? Thanks!


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[PATCH] D148094: [DRAFT][clang][CodeGen] Break up TargetInfo.cpp [6/6]

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

+1 on this refactoring being a good idea. The RISC-V changes seem fine to me 
(haven't done a detailed line by line review).


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[PATCH] D149248: [RISCV][MC] MC layer support for the experimental zacas extension

[Alex Bradbury via Phabricator via cfe-commits]

asb created this revision.
asb added reviewers: reames, craig.topper, kito-cheng.
Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, 
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rogfer01, edward-jones, zzheng, jrtc27, shiva0217, niosHD, sabuasal, simoncook, 
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This implements the v0.1 draft extension.

amocas.d on RV32 and amocas.q have the restriction that rd and rs2 must be even 
registers. I've opted to implement this restriction in 
RISCVAsmParser::validateInstruction even though for codegen we'll need a new 
register class and can then remove this validation. My reasoning is that this 
validation is easy to implement and review, while ensuring the register class 
is correct as described isn't so easy without testing that is only added when 
codegen is implemented. Admittedly, the need to check for the aq/rl/aqrl opcode 
variants makes the validateInstruction
logic a bit uglier. Happy to switch approach if preferred by reviewers.

It's not a pre-requisite for this patch, but we likely want to have an asm 
constraint for even registers. I've filed an issue here 
https://github.com/riscv-non-isa/riscv-c-api-doc/issues/37


Repository:
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https://reviews.llvm.org/D149248

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoA.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zacas-invalid.s
  llvm/test/MC/RISCV/rv32zacas-valid.s
  llvm/test/MC/RISCV/rv64zacas-invalid.s
  llvm/test/MC/RISCV/rv64zacas-valid.s

Index: llvm/test/MC/RISCV/rv64zacas-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv64zacas-valid.s
@@ -0,0 +1,51 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zacas -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zacas < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zacas -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+a -show-encoding %s 2>&1 \
+# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
+
+# Odd register numbers for rd and rs2 are allowed for amocas.d on RV64.
+
+# CHECK-ASM-AND-OBJ: amocas.d a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d a1, a3, (a5)
+# CHECK-ASM-AND-OBJ: amocas.d.aq a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d.aq a1, a3, (a5)
+# CHECK-ASM-AND-OBJ: amocas.d.rl a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d.rl a1, a3, (a5)
+# CHECK-ASM-AND-OBJ: amocas.d.aqrl a1, a3, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xd7,0x2e]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.d.aqrl a1, a3, (a5)
+
+# CHECK-ASM-AND-OBJ: amocas.q a0, a2, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc5,0xc5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q a0, a2, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q a0, a2, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc5,0xc5,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q a0, a2, 0(a1)
+# CHECK-ASM-AND-OBJ: amocas.q zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x28]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q zero, zero, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q.aq zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x2c]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q.aq zero, zero, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q.rl zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x2a]
+# CHECK-ERROR: instruction requires the following: 'Zacas' (Atomic Compare-And-Swap Instructions){{$}}
+amocas.q.rl zero, zero, (a1)
+# CHECK-ASM-AND-OBJ: amocas.q.aqrl zero, zero, (a1)
+# CHECK-ASM: encoding: [0x2f,0xc0,0x05,0x2e]
+# CHECK-ERROR: 

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 517106.
asb added a comment.

Add missing doc comment update.


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Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/unittests/Support/RISCVISAInfoTest.cpp

Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -192,7 +192,7 @@
   EXPECT_EQ(InfoRV64G.getFLen(), 64U);
 }
 
-TEST(ParseArchString, RequiresCanonicalOrderForExtensions) {
+TEST(ParseArchString, RequiresCanonicalOrderForSingleLetterExtensions) {
   EXPECT_EQ(
   toString(RISCVISAInfo::parseArchString("rv64idf", true).takeError()),
   "standard user-level extension not given in canonical order 'f'");
@@ -203,12 +203,10 @@
   toString(
   RISCVISAInfo::parseArchString("rv32i_zfinx_a", true).takeError()),
   "invalid extension prefix 'a'");
-  EXPECT_EQ(
-  toString(RISCVISAInfo::parseArchString("rv64i_svnapot_zicsr", true)
-   .takeError()),
-  "standard user-level extension not given in canonical order 'zicsr'");
+  // Canonical ordering not required for z*, s*, and x* extensions.
   EXPECT_THAT_EXPECTED(
-  RISCVISAInfo::parseArchString("rv64imafdc_zicsr_svnapot", true),
+  RISCVISAInfo::parseArchString(
+  "rv64imafdc_xsfvcp_zicsr_xtheadba_svnapot_zawrs", true),
   Succeeded());
 }
 
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -756,9 +756,9 @@
   // Parse the ISA string containing non-standard user-level
   // extensions, standard supervisor-level extensions and
   // non-standard supervisor-level extensions.
-  // These extensions start with 'z', 's', 'x' prefixes, follow a
-  // canonical order, might have a version number (major, minor)
-  // and are separated by a single underscore '_'.
+  // These extensions start with 'z', 's', 'x' prefixes, might have a version
+  // number (major, minor) and are separated by a single underscore '_'. We do
+  // not enforce a canonical order for them.
   // Set the hardware features for the extensions that are supported.
 
   // Multi-letter extensions are seperated by a single underscore
@@ -767,9 +767,6 @@
   OtherExts.split(Split, '_');
 
   SmallVector AllExts;
-  std::array Prefix{"z", "s", "x"};
-  auto I = Prefix.begin();
-  auto E = Prefix.end();
   if (Split.size() > 1 || Split[0] != "") {
 for (StringRef Ext : Split) {
   if (Ext.empty())
@@ -789,18 +786,6 @@
  "invalid extension prefix '" + Ext + "'");
   }
 
-  // Check ISA extensions are specified in the canonical order.
-  while (I != E && *I != Type)
-++I;
-
-  if (I == E) {
-if (IgnoreUnknown)
-  continue;
-return createStringError(errc::invalid_argument,
- "%s not given in canonical order '%s'",
- Desc.str().c_str(), Ext.str().c_str());
-  }
-
   if (!IgnoreUnknown && Name.size() == Type.size()) {
 return createStringError(errc::invalid_argument,
  "%s name missing after '%s'",
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -333,8 +333,7 @@
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
 // RV32-X-ORDER: error: invalid arch name 'rv32ixdef_sabc',
-// RV32-X-ORDER: standard supervisor-level extension not given
-// RV32-X-ORDER: in canonical order 'sabc'
+// RV32-X-ORDER  unsupported non-standard user-level extension 'xdef'
 
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32ixabc_xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XDUP %s
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -422,6 +422,9 @@
 - Fixed incorrect ABI lowering of ``_Float16`` in the case of structs
   containing ``_Float16`` that are eligible for passing via GPR+FPR or
   FPR+FPR.
+- The rules for ordering of extensions in ``-march`` strings were relaxed. A
+  canonical ordering is no longer enforced on ``z*``, ``s*``, and ``x*``
+  prefixed extensions.
 
 CUDA/HIP Language Changes
 ^
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[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 517105.

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Files:
  clang/docs/ReleaseNotes.rst
  clang/test/Driver/riscv-arch.c
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/unittests/Support/RISCVISAInfoTest.cpp


Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -192,7 +192,7 @@
   EXPECT_EQ(InfoRV64G.getFLen(), 64U);
 }
 
-TEST(ParseArchString, RequiresCanonicalOrderForExtensions) {
+TEST(ParseArchString, RequiresCanonicalOrderForSingleLetterExtensions) {
   EXPECT_EQ(
   toString(RISCVISAInfo::parseArchString("rv64idf", true).takeError()),
   "standard user-level extension not given in canonical order 'f'");
@@ -203,12 +203,10 @@
   toString(
   RISCVISAInfo::parseArchString("rv32i_zfinx_a", true).takeError()),
   "invalid extension prefix 'a'");
-  EXPECT_EQ(
-  toString(RISCVISAInfo::parseArchString("rv64i_svnapot_zicsr", true)
-   .takeError()),
-  "standard user-level extension not given in canonical order 'zicsr'");
+  // Canonical ordering not required for z*, s*, and x* extensions.
   EXPECT_THAT_EXPECTED(
-  RISCVISAInfo::parseArchString("rv64imafdc_zicsr_svnapot", true),
+  RISCVISAInfo::parseArchString(
+  "rv64imafdc_xsfvcp_zicsr_xtheadba_svnapot_zawrs", true),
   Succeeded());
 }
 
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -767,9 +767,6 @@
   OtherExts.split(Split, '_');
 
   SmallVector AllExts;
-  std::array Prefix{"z", "s", "x"};
-  auto I = Prefix.begin();
-  auto E = Prefix.end();
   if (Split.size() > 1 || Split[0] != "") {
 for (StringRef Ext : Split) {
   if (Ext.empty())
@@ -789,18 +786,6 @@
  "invalid extension prefix '" + Ext + "'");
   }
 
-  // Check ISA extensions are specified in the canonical order.
-  while (I != E && *I != Type)
-++I;
-
-  if (I == E) {
-if (IgnoreUnknown)
-  continue;
-return createStringError(errc::invalid_argument,
- "%s not given in canonical order '%s'",
- Desc.str().c_str(), Ext.str().c_str());
-  }
-
   if (!IgnoreUnknown && Name.size() == Type.size()) {
 return createStringError(errc::invalid_argument,
  "%s name missing after '%s'",
Index: clang/test/Driver/riscv-arch.c
===
--- clang/test/Driver/riscv-arch.c
+++ clang/test/Driver/riscv-arch.c
@@ -333,8 +333,7 @@
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32ixdef_sabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-X-ORDER %s
 // RV32-X-ORDER: error: invalid arch name 'rv32ixdef_sabc',
-// RV32-X-ORDER: standard supervisor-level extension not given
-// RV32-X-ORDER: in canonical order 'sabc'
+// RV32-X-ORDER  unsupported non-standard user-level extension 'xdef'
 
 // RUN: %clang --target=riscv32-unknown-elf -march=rv32ixabc_xabc -### %s \
 // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-XDUP %s
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -422,6 +422,9 @@
 - Fixed incorrect ABI lowering of ``_Float16`` in the case of structs
   containing ``_Float16`` that are eligible for passing via GPR+FPR or
   FPR+FPR.
+- The rules for ordering of extensions in ``-march`` strings were relaxed. A
+  canonical ordering is no longer enforced on ``z*``, ``s*``, and ``x*``
+  prefixed extensions.
 
 CUDA/HIP Language Changes
 ^


Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -192,7 +192,7 @@
   EXPECT_EQ(InfoRV64G.getFLen(), 64U);
 }
 
-TEST(ParseArchString, RequiresCanonicalOrderForExtensions) {
+TEST(ParseArchString, RequiresCanonicalOrderForSingleLetterExtensions) {
   EXPECT_EQ(
   toString(RISCVISAInfo::parseArchString("rv64idf", true).takeError()),
   "standard user-level extension not given in canonical order 'f'");
@@ -203,12 +203,10 @@
   toString(
   RISCVISAInfo::parseArchString("rv32i_zfinx_a", true).takeError()),
   "invalid extension prefix 'a'");
-  EXPECT_EQ(
-  toString(RISCVISAInfo::parseArchString("rv64i_svnapot_zicsr", true)
-   .takeError()),
-  "standard user-level extension not given in canonical order 'zicsr'");
+  // Canonical ordering not required for z*, s*, and x* 

[PATCH] D149246: [RISCV] Relax rules for ordering s/z/x prefixed extensions in ISA naming strings

[Alex Bradbury via Phabricator via cfe-commits]

asb created this revision.
asb added reviewers: reames, kito-cheng, craig.topper, jrtc27, joshua-arch1.
Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, 
frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, 
benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, shiva0217, niosHD, sabuasal, simoncook, johnrusso, rbar, 
hiraditya, arichardson.
Herald added a project: All.
asb requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added projects: clang, LLVM.

This was discussed somewhat in D148315 . As 
it stands, we require in RISCVISAInfo::parseArchString (used for e.g. `-march` 
parsing in Clang) that extensions are given in the order of z, then s, then x 
prefixed extensions (after the standard single-letter extensions). However, we 
recently (in D148315 ) moved to that order 
from z/x/s as the canonical ordering was changed in the spec. In addition, 
recent GCC seems to require z* extensions before s*.

My recollection of the history here is that we thought keeping `-march` as 
close to the rules for ISA naming strings as possible would simplify things, as 
there's an existing spec to point to. My feeling is that now we've had 
incompatible changes, and an incompatibility with GCC there's no real benefit 
to sticking to this restriction, and it risks making it much more painful than 
it needs to be to copy a `-march=` string between GCC and Clang.

This patch actually removes all ordering restrictions so you can freely mix 
x/s/z extensions. Arguably this is more freedom than we want to allow, on the 
other hand it might be less hassle for build systems assembling their arch 
strings.

To be very explicit, this doesn't change our behaviour when emitting a 
canonically ordered extension string (e.g. in build attributes). We of course 
sort according to the canonical order (as we understand it) in that case.


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https://reviews.llvm.org/D149246

Files:
  clang/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/unittests/Support/RISCVISAInfoTest.cpp


Index: llvm/unittests/Support/RISCVISAInfoTest.cpp
===
--- llvm/unittests/Support/RISCVISAInfoTest.cpp
+++ llvm/unittests/Support/RISCVISAInfoTest.cpp
@@ -192,7 +192,7 @@
   EXPECT_EQ(InfoRV64G.getFLen(), 64U);
 }
 
-TEST(ParseArchString, RequiresCanonicalOrderForExtensions) {
+TEST(ParseArchString, RequiresCanonicalOrderForSingleLetterExtensions) {
   EXPECT_EQ(
   toString(RISCVISAInfo::parseArchString("rv64idf", true).takeError()),
   "standard user-level extension not given in canonical order 'f'");
@@ -203,12 +203,10 @@
   toString(
   RISCVISAInfo::parseArchString("rv32i_zfinx_a", true).takeError()),
   "invalid extension prefix 'a'");
-  EXPECT_EQ(
-  toString(RISCVISAInfo::parseArchString("rv64i_svnapot_zicsr", true)
-   .takeError()),
-  "standard user-level extension not given in canonical order 'zicsr'");
+  // Canonical ordering not required for z*, s*, and x* extensions.
   EXPECT_THAT_EXPECTED(
-  RISCVISAInfo::parseArchString("rv64imafdc_zicsr_svnapot", true),
+  RISCVISAInfo::parseArchString(
+  "rv64imafdc_xsfvcp_zicsr_xtheadba_svnapot_zawrs", true),
   Succeeded());
 }
 
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -767,9 +767,6 @@
   OtherExts.split(Split, '_');
 
   SmallVector AllExts;
-  std::array Prefix{"z", "s", "x"};
-  auto I = Prefix.begin();
-  auto E = Prefix.end();
   if (Split.size() > 1 || Split[0] != "") {
 for (StringRef Ext : Split) {
   if (Ext.empty())
@@ -789,18 +786,6 @@
  "invalid extension prefix '" + Ext + "'");
   }
 
-  // Check ISA extensions are specified in the canonical order.
-  while (I != E && *I != Type)
-++I;
-
-  if (I == E) {
-if (IgnoreUnknown)
-  continue;
-return createStringError(errc::invalid_argument,
- "%s not given in canonical order '%s'",
- Desc.str().c_str(), Ext.str().c_str());
-  }
-
   if (!IgnoreUnknown && Name.size() == Type.size()) {
 return createStringError(errc::invalid_argument,
  "%s name missing after '%s'",
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -422,6 +422,9 @@
 - Fixed incorrect ABI lowering of ``_Float16`` in the case of structs
   containing ``_Float16`` that are eligible for passing via GPR+FPR or
   FPR+FPR.
+- The 

[PATCH] D148962: [RISCV] Make Zicntr and Zihpm imply Zicsr.

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.

LGTM.


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[PATCH] D148817: [RISCV] Add Tag_RISCV_arch attribute by default when using clang as an assembler.

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

I'd appreciate some riscv32 RUN lines for completeness, but otherwise LGTM.


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[PATCH] D148483: [RISCV] Zvk (vector crypto) specification update to 0.5.1 (Zvbb/Zvbc/Zvkt/Zvkng/Zvksg)

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

In D148483#4283898 , @ego wrote:

> Thanks for the clarification. I went with the additional alignment. I used to 
> overdo vertical alignment but it was beaten out of me by the Google C++ style 
> guide and automatic formatters.

Yes, once there's a decent .td auto-formatting solution I'll probably miss some 
of the niceties of manually aligned instruction definitions, but it will also 
be nice to spend less review time going back and forth on whitespace :)

Thanks for the rapid iteration on this - I've now landed the patch.


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[PATCH] D148483: [RISCV] Zvk (vector crypto) specification update to 0.5.1 (Zvbb/Zvbc/Zvkt/Zvkng/Zvksg)

[Alex Bradbury via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGcb7dffdc9a83: [RISCV] Zvk (vector crypto) specification 
update to 0.5.1… (authored by ego, committed by asb).
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Changed prior to commit:
  https://reviews.llvm.org/D148483?vs=515356=515384#toc

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Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvbb.s
  llvm/test/MC/RISCV/rvv/zvbc.s
  llvm/test/MC/RISCV/rvv/zvkb.s
  llvm/test/MC/RISCV/rvv/zvkg.s

Index: llvm/test/MC/RISCV/rvv/zvkg.s
===
--- llvm/test/MC/RISCV/rvv/zvkg.s
+++ llvm/test/MC/RISCV/rvv/zvkg.s
@@ -13,3 +13,9 @@
 # CHECK-ENCODING: [0x77,0x25,0x94,0xb2]
 # CHECK-ERROR: instruction requires the following: 'Zvkg' (Vector GCM instructions for Cryptography.){{$}}
 # CHECK-UNKNOWN: 77 25 94 b2   
+
+vgmul.vv v10, v9
+# CHECK-INST: vgmul.vv v10, v9
+# CHECK-ENCODING: [0x77,0xa5,0x98,0xa2]
+# CHECK-ERROR: instruction requires the following: 'Zvkg' (Vector GCM instructions for Cryptography.){{$}}
+# CHECK-UNKNOWN: 77 a5 98 a2   
Index: llvm/test/MC/RISCV/rvv/zvkb.s
===
--- llvm/test/MC/RISCV/rvv/zvkb.s
+++ /dev/null
@@ -1,87 +0,0 @@
-# RUN: llvm-mc -triple=riscv32 -show-encoding --mattr=+zve32x --mattr=+experimental-zvkb %s \
-# RUN:| FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
-# RUN: not llvm-mc -triple=riscv32 -show-encoding %s 2>&1 \
-# RUN:| FileCheck %s --check-prefix=CHECK-ERROR
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
-# RUN:| llvm-objdump -d --mattr=+zve32x --mattr=+experimental-zvkb  - \
-# RUN:| FileCheck %s --check-prefix=CHECK-INST
-# RUN: llvm-mc -triple=riscv32 -filetype=obj --mattr=+zve32x --mattr=+experimental-zvkb %s \
-# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
-
-vandn.vv v10, v9, v8, v0.t
-# CHECK-INST: vandn.vv v10, v9, v8, v0.t
-# CHECK-ENCODING: [0x57,0x05,0x94,0x04]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 05 94 04   
-
-vandn.vx v10, v9, a0, v0.t
-# CHECK-INST: vandn.vx v10, v9, a0, v0.t
-# CHECK-ENCODING: [0x57,0x45,0x95,0x04]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 45 95 04   
-
-vbrev8.v v10, v9, v0.t
-# CHECK-INST: vbrev8.v v10, v9, v0.t
-# CHECK-ENCODING: [0x57,0x25,0x94,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 25 94 48   
-
-vclmul.vv v10, v9, v8
-# CHECK-INST: vclmul.vv v10, v9, v8
-# CHECK-ENCODING: [0x57,0x25,0x94,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 25 94 32   
-   
-vclmul.vx v10, v9, a0
-# CHECK-INST: vclmul.vx v10, v9, a0
-# CHECK-ENCODING: [0x57,0x65,0x95,0x32]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 65 95 32   
-
-vclmulh.vv v10, v9, v8
-# CHECK-INST: vclmulh.vv v10, v9, v8
-# CHECK-ENCODING: [0x57,0x25,0x94,0x36]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 25 94 36   
-
-vclmulh.vx v10, v9, a0
-# CHECK-INST: vclmulh.vx v10, v9, a0
-# CHECK-ENCODING: [0x57,0x65,0x95,0x36]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 65 95 36   
-   
-vrev8.v v10, v9, v0.t
-# CHECK-INST: vrev8.v v10, v9, v0.t
-# CHECK-ENCODING: [0x57,0xa5,0x94,0x48]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 a5 94 48   
-
-vrol.vv v10, v9, v8, v0.t
-# CHECK-INST: vrol.vv v10, v9, v8, v0.t
-# CHECK-ENCODING: [0x57,0x05,0x94,0x54]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 57 05 94 54   
-
-vrol.vx v10, v9, a0, v0.t
-# CHECK-INST: vrol.vx v10, v9, a0, v0.t
-# CHECK-ENCODING: [0x57,0x45,0x95,0x54]
-# CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bitmanip instructions for Cryptography.){{$}}
-# CHECK-UNKNOWN: 

[PATCH] D148315: [RISCV] Modify arch string parsing order according to latest riscv spec

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

I'm starting to think we should just remove the ordering rules for z/s/x 
altogether when parsing arch strings I see that gcc 12.2.0 actually requires s 
and then z:

  [asb@purge ~]$ riscv64-linux-gnu-gcc -march=rv64imafdc_svinval_zicbom t.c -c
  [asb@purge ~]$ riscv64-linux-gnu-gcc -march=rv64imafdc_zicbom_svinval t.c -c
  riscv64-linux-gnu-gcc: error: '-march=rv64imafdc_zicbom_svinval': unexpected 
ISA string at end: 'svinval'

So ISA naming strings aren't easily portable between clang and GCC right now, 
even if the same extension names are recognised.


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[PATCH] D148634: [RISCV] Bump Zfa version to 0.2 and correct RISCVUsage description

[Alex Bradbury via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2a5661c84158: [RISCV] Bump Zfa version to 0.2 and correct 
RISCVUsage description (authored by asb).
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Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s


Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -234,8 +234,8 @@
 .attribute arch, "rv32izifencei2p0"
 # CHECK: attribute  5, "rv32i2p1_zifencei2p0"
 
-.attribute arch, "rv32izfa0p1"
-# CHECK: attribute  5, "rv32i2p1_f2p2_zicsr2p0_zfa0p1"
+.attribute arch, "rv32izfa0p2"
+# CHECK: attribute  5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2"
 
 .attribute arch, "rv32izicond1p0"
 # CHECK: attribute  5, "rv32i2p1_zicond1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -193,7 +193,7 @@
 ; RV32ZCF: .attribute 5, "rv32i2p1_zcf1p0"
 ; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0"
 ; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0"
-; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p1"
+; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2"
 ; RV32ZVKB: .attribute 5, 
"rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0"
 ; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
 ; RV32ZVKN: .attribute 5, 
"rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
@@ -264,7 +264,7 @@
 ; RV64ZCD: .attribute 5, "rv64i2p1_zcd1p0"
 ; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0"
 ; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0"
-; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p1"
+; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2"
 ; RV64ZVKB: .attribute 5, 
"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvl32b1p0_zvl64b1p0"
 ; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg0p3_zvl32b1p0"
 ; RV64ZVKN: .attribute 5, 
"rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb0p3_zvkn0p3_zvkned0p3_zvknha0p3_zvknhb0p3_zvl32b1p0_zvl64b1p0"
Index: llvm/lib/Support/RISCVISAInfo.cpp
===
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -139,7 +139,7 @@
 {"zcb", RISCVExtensionVersion{1, 0}},
 {"zcd", RISCVExtensionVersion{1, 0}},
 {"zcf", RISCVExtensionVersion{1, 0}},
-{"zfa", RISCVExtensionVersion{0, 1}},
+{"zfa", RISCVExtensionVersion{0, 2}},
 {"zicond", RISCVExtensionVersion{1, 0}},
 {"zvfh", RISCVExtensionVersion{0, 1}},
 {"ztso", RISCVExtensionVersion{0, 1}},
Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -166,6 +166,7 @@
   on RISC-V, but conforms with the new "platform register" defined in the
   RISC-V psABI (for more details see the 
   `psABI discussion 
`_).
+* Added support for Zfa extension version 0.2.
 
 Changes to the WebAssembly Backend
 --
Index: llvm/docs/RISCVUsage.rst
===
--- llvm/docs/RISCVUsage.rst
+++ llvm/docs/RISCVUsage.rst
@@ -188,7 +188,7 @@
   LLVM implements the `1.0.1 draft specification 
`_.
 
 ``experimental-zfa``
-  LLVM implements a subset of `0.1 draft specification 
`_
 (see Chapter 25).
+  LLVM implements the `0.2 draft specification 
`_.
 
 ``experimental-zicond``
   LLVM implements the `1.0-rc1 draft specification 
_.
Index: clang/test/Preprocessor/riscv-target-features.c
===
--- clang/test/Preprocessor/riscv-target-features.c
+++ clang/test/Preprocessor/riscv-target-features.c
@@ -518,12 +518,12 @@
 // CHECK-ZIFENCEI-EXT: __riscv_zifencei 200{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu 
-menable-experimental-extensions \
-// RUN: -march=rv32izfa0p1 -x c -E -dM %s \
+// RUN: -march=rv32izfa0p2 -x c -E -dM %s \
 // RUN: 

[PATCH] D148315: [RISCV] Modify arch string parsing order according to latest riscv spec

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

@joshua-arch1: I've posted D146815  to fix 
the canonical ordering and directly committed 
rGa35e67fc5be654a7efdfa6125343b90f8960a487 
 to add 
some test coverage.


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[PATCH] D148124: [RISCV][Driver] Allow the use of CPUs with a different XLEN than the triple.

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.

LGTM.


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[PATCH] D147935: [RISCV] Add SiFive extension support

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.

LGTM


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[PATCH] D148034: [clang][driver] Disable GP relaxation with RISC-V ShadowCallStack

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

In D148034#4262991 , @MaskRay wrote:

> In D148034#4260376 , @asb wrote:
>
>> Will `--[no-]relax-gp` make its way into a minor gcc point release or do we 
>> need to wait for the next major release?
>>
>> In terms of this breaking GNU users - isn't it the case that without this 
>> option, they may get silently broken code when using the shadow call stack? 
>> Breaking loudly and early seems preferable, though of course it would be 
>> best if it's easily fixable by e.g. updating to a newer released binutils.
>
> Yes, `-fsanitize=shadow-call-stack` using gp users will get silently broken 
> code if linked with GNU ld, unless GNU ld is specified, or `-Wl,--no-relax` 
> or `-Wl,--no-relax-gp` is specified.
> This is an instance of the guideline proposed in 
> https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/371/commits/bb0df41a4f2626fa039173c2a975039905dce99c
>
>> For such platforms, care must be taken to ensure all code (compiler 
>> generated or otherwise) avoids using gp in a way incompatible with the 
>> platform specific purpose, and that global pointer relaxation is disabled in 
>> the toolchain.
>
> Personally I think most `-fsanitize=shadow-call-stack`  users do not use GNU 
> ld, so this incompatibility is actually minor.
>
> `-fsanitize=shadow-call-stack` is already a quite specific configuration. For 
> GNU ld users, I think placing the burden more on user education is fine 
> (sorry, just that we don't have better options).

I just wanted to make sure I'm following your suggestion here. Have you come 
round to the idea of adding `--no-relax-gp` when shadow call stack is enabled 
and letting it error for users of old GNU tools on the basis that there aren't 
better options?


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[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

In D148066#4262379 , @reames wrote:

> I would be fine landing this as experimental before ratification.  I see no 
> real downside to doing that

My concern would be that as we don't gate CSR names on enabling the relevant 
extension, people could start using CSR names and encodings that could change, 
without opting in via `-menable-experimental-extensions`, perhaps not realising 
that they're using the unratified version. OTOH, you could argue it was user 
error from the start by not trying to specify all the needed extensions in the 
ISA naming string.


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[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 512745.
asb added a comment.

Rebase


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  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rvv/zvfbfwma-invalid.s
  llvm/test/MC/RISCV/rvv/zvfbfwma.s

Index: llvm/test/MC/RISCV/rvv/zvfbfwma.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvfbfwma.s
@@ -0,0 +1,68 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfwma - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfwma - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: vfwmaccbf16.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 14 4a 8c 
+vfwmaccbf16.vv v8, v20, v4, v0.t
+
+# CHECK-INST: vfwmaccbf16.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 14 4a 8e 
+vfwmaccbf16.vv v8, v20, v4
+
+# CHECK-INST: vfwmaccbf16.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 54 45 8c 
+vfwmaccbf16.vf v8, fa0, v4, v0.t
+
+# CHECK-INST: vfwmaccbf16.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 54 45 8e 
+vfwmaccbf16.vf v8, fa0, v4
+
+# Check scalar half FP load/store/move included in this extension.
+
+# CHECK-INST: flh ft0, 12(a0)
+# CHECK-ENCODING: [0x07,0x10,0xc5,0x00]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 07 10 c5 00 
+flh f0, 12(a0)
+
+# CHECK-INST: fsh ft6, 2047(s4)
+# CHECK-ENCODING: [0xa7,0x1f,0x6a,0x7e]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: a7 1f 6a 7e 
+fsh f6, 2047(s4)
+
+# CHECK-INST: fmv.x.h a2, fs7
+# CHECK-ENCODING: [0x53,0x86,0x0b,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 53 86 0b e4 
+fmv.x.h a2, fs7
+
+# CHECK-INST: fmv.h.x ft1, a6
+# CHECK-ENCODING: [0xd3,0x00,0x08,0xf4]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: d3 00 08 f4 
+fmv.h.x ft1, a6
Index: llvm/test/MC/RISCV/rvv/zvfbfwma-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvfbfwma-invalid.s
@@ -0,0 +1,11 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zvfbfwma,+d < %s 2>&1 | \
+# RUN:   FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zvfbfwma,+d < %s 

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 512744.
asb added a comment.

Rebase.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147611/new/

https://reviews.llvm.org/D147611

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvfbfmin.s

Index: llvm/test/MC/RISCV/rvv/zvfbfmin.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvfbfmin.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfmin - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfmin - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: vfncvtbf16.f.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x4e,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 4e 48 
+vfncvtbf16.f.f.w v8, v4, v0.t
+
+# CHECK-INST: vfncvtbf16.f.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x4e,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 4e 4a 
+vfncvtbf16.f.f.w v8, v4
+
+# CHECK-INST: vfwcvtbf16.f.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x46,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 46 48 
+vfwcvtbf16.f.f.v v8, v4, v0.t
+
+# CHECK-INST: vfwcvtbf16.f.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x46,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 46 4a 
+vfwcvtbf16.f.f.v v8, v4
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -242,3 +242,6 @@
 
 .attribute arch, "rv32if_zfbfmin0p2"
 # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p2"
+
+.attribute arch, "rv32if_zvfbfmin0p2"
+# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p2_zvl32b1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -66,6 +66,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -139,6 +140,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+f,+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
 
 ; CHECK: .attribute 4, 16
 
@@ -207,6 +209,7 @@
 ; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
 ; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
 ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p2"
+; RV32ZVFBFMIN: .attribute 

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 512743.
asb edited the summary of this revision.
asb added a comment.

Rebase and use the new encoding suggested in 
https://github.com/riscv/riscv-bfloat16/issues/33 - hoping for the commits that 
alter the encoding to be pushed to the spec repo and a new PDF (with new 
version) to be generated ahead of landing this.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147610/new/

https://reviews.llvm.org/D147610

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zfbfmin-invalid.s
  llvm/test/MC/RISCV/rv32zfbfmin-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s

Index: llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
===
--- llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
+++ llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
@@ -1,7 +1,7 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zhinxmin %s 2>&1 | FileCheck %s
 
 # Not support float registers
-flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
+flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
 
 # Invalid instructions
 fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv64zhinx-invalid.s
===
--- llvm/test/MC/RISCV/rv64zhinx-invalid.s
+++ llvm/test/MC/RISCV/rv64zhinx-invalid.s
@@ -1,7 +1,7 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s
 
 # Not support float registers
-flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
+flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
 
 # Invalid instructions
 fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv32zfbfmin-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfbfmin-valid.s
@@ -0,0 +1,56 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfbfmin,+f -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfbfmin,+f -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfbfmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfbfmin,+f -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfbfmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfbfmin,+f -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: flh ft0, 12(a0)
+# CHECK-ASM: encoding: [0x07,0x10,0xc5,0x00]
+flh f0, 12(a0)
+# CHECK-ASM-AND-OBJ: flh ft1, 4(ra)
+# CHECK-ASM: encoding: [0x87,0x90,0x40,0x00]
+flh f1, +4(ra)
+# CHECK-ASM-AND-OBJ: flh ft2, -2048(a3)
+# CHECK-ASM: encoding: [0x07,0x91,0x06,0x80]
+flh f2, -2048(x13)
+# CHECK-ASM-AND-OBJ: flh ft3, -2048(s1)
+# CHECK-ASM: encoding: [0x87,0x91,0x04,0x80]
+flh f3, %lo(2048)(s1)
+# CHECK-ASM-AND-OBJ: flh ft4, 2047(s2)
+# CHECK-ASM: encoding: [0x07,0x12,0xf9,0x7f]
+flh f4, 2047(s2)
+# CHECK-ASM-AND-OBJ: flh ft5, 0(s3)
+# CHECK-ASM: encoding: [0x87,0x92,0x09,0x00]
+flh f5, 0(s3)
+
+# CHECK-ASM-AND-OBJ: fsh ft6, 2047(s4)
+# CHECK-ASM: encoding: [0xa7,0x1f,0x6a,0x7e]
+fsh f6, 2047(s4)
+# CHECK-ASM-AND-OBJ: fsh ft7, -2048(s5)
+# CHECK-ASM: encoding: [0x27,0x90,0x7a,0x80]
+fsh f7, -2048(s5)
+# CHECK-ASM-AND-OBJ: fsh fs0, -2048(s6)
+# CHECK-ASM: encoding: [0x27,0x10,0x8b,0x80]
+fsh f8, %lo(2048)(s6)
+# CHECK-ASM-AND-OBJ: fsh fs1, 999(s7)
+# CHECK-ASM: encoding: [0xa7,0x93,0x9b,0x3e]
+fsh f9, 999(s7)
+
+# CHECK-ASM-AND-OBJ: fmv.x.h a2, fs7
+# CHECK-ASM: encoding: [0x53,0x86,0x0b,0xe4]
+fmv.x.h a2, fs7
+# CHECK-ASM-AND-OBJ: fmv.h.x ft1, a6
+# CHECK-ASM: encoding: [0xd3,0x00,0x08,0xf4]
+fmv.h.x ft1, a6
+
+# CHECK-ASM-AND-OBJ: fcvt.s.bf16 

[PATCH] D148066: [RISCV] Add Smaia and Ssaia extensions support

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

This extension doesn't appear to be ratified but you've listed it in the table 
of ratified extensions and treated it as a ratified extension in 
RISCVISAInfo.cpp. I know that given we don't do checking for CSR names the 
distinction feels a bit academic, but I don't think this is the best approach. 
For CSR only extensions like this my feeling is we should review a patch like 
this ahead of ratification, but not land until it's actually ratified. One of 
the main goals (from my perspective at least) for allowing not-yet-ratified 
extensions upstream was to allow collaboration on the implementation, but given 
the simplicity of CSR-only extensions I'm not sure the cost/benefit makes sense 
vs just waiting for ratification when we can be sure the assigned numbers won't 
change. I'd be open to counter arguments though.


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[PATCH] D148034: [clang][driver] Disable GP relaxation with RISC-V ShadowCallStack

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

Will `--[no-]relax-gp` make its way into a minor gcc point release or do we 
need to wait for the next major release?

In terms of this breaking GNU users - isn't it the case that without this 
option, they may get silently broken code when using the shadow call stack? 
Breaking loudly and early seems preferable, though of course it would be best 
if it's easily fixable by e.g. updating to a newer released binutils.

One slight tweak might be to avoid adding `--no-relax-gp` if linker relaxation 
is already disabled, though it's not going to matter once binutils gets support 
for --no-relax-gp.


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[PATCH] D132819: [RISCV] Add MC support of RISCV zcmp Extension

[Alex Bradbury via Phabricator via cfe-commits]

asb added inline comments.



Comment at: clang/test/Preprocessor/riscv-target-features.c:51
 // CHECK-NOT: __riscv_zcf {{.*$}}
+// CHECK-NOT: __riscv_zcmp
 // CHECK-NOT: __riscv_h {{.*$}}

jrtc27 wrote:
> Does this really belong in an MC patch?
We typically do include this test change in the initial MC layer patch on the 
basis that the change becomes testable as soon as MC layer support is 
introduced (and indeed might be used for e.g. ifdefing inline assembler, so 
isn't really only useful in the presence of codegen/intrinsics support).


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[PATCH] D147935: [RISCV] Add SiFive extension support

[Alex Bradbury via Phabricator via cfe-commits]

asb added inline comments.



Comment at: clang/include/clang/Support/RISCVVIntrinsicUtils.h:465
   RVV_REQ_FullMultiply = 1 << 1,
+  RVV_REQ_xsfvcp = 1 << 2,
 

Nit: It would better match the surrounding capitalisation to call this 
RVV_REQ_Xsfvcp


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[PATCH] D147978: [RISCV] Remove getCPUFeaturesExceptStdExt.

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D147986: [RISCV] Print a better error message when a rv32 CPU is used on rv64 and vice versa.

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to X3

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.

In D146463#4255927 , @paulkirth wrote:

> @asb  Are we happy with the state of consensus w.r.t. using `x3`? I think the 
> lingering concerns from the psABI discussion have been resolved.

Yes, all LGTM now.




Comment at: clang/lib/Driver/ToolChains/Clang.cpp:2062
   const llvm::Triple  = TC.getTriple();
-  // Default small data limitation is eight.
-  const char *SmallDataLimit = "8";
+  // Default small data limitation on some platforms(Android and Fuchsia) is
+  // zero, otherwise its eight.

Nit: Missing space after platforms


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[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to X3

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

Ok, looks like the consensus I thought we had isn't quite there on the psABI 
thread - Andrew Waterman has some concerns. We should let that discussion play 
out some more.


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[PATCH] D146463: [CodeGen][RISCV] Change Shadow Call Stack Register to X3

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

In D146463#4247050 , @paulkirth wrote:

> @asb, @craig.topper, @jrtc27  Are there any remaining considerations for us 
> here? From the discussions in psABI and sig-toolchain, I think we have a 
> consensus that this is the approach we'll be taking for RISC-V. We'd prefer 
> to correct this ASAP, so as to prevent future incompatibility/continuing to 
> use a non-standard register.

It looks like we have strong consensus here. Could you update the patch to add 
a release note about this change please? (I guess it might merit inclusion in 
both the LLVM and the Clang release notes).

The RFC to check nobody downstream is concerned about changing the SCS register 
has been up for a week and a half with no concerns. You might consider leaving 
merging this until Monday to give it a full 2 week period, but I'm not opposed 
to going ahead before that. With the level of agreement we have it's hard to 
imagine changing direction and we want to change this default anyway - if 
there's a downstream user who needs to continue supporting the old SCS register 
then the logical path of action would be to add a new compiler option to enable 
that.


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[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 511082.

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Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rvv/zvfbfwma-invalid.s
  llvm/test/MC/RISCV/rvv/zvfbfwma.s

Index: llvm/test/MC/RISCV/rvv/zvfbfwma.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvfbfwma.s
@@ -0,0 +1,68 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfwma - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfwma - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: vfwmaccbf16.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 14 4a 8c 
+vfwmaccbf16.vv v8, v20, v4, v0.t
+
+# CHECK-INST: vfwmaccbf16.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 14 4a 8e 
+vfwmaccbf16.vv v8, v20, v4
+
+# CHECK-INST: vfwmaccbf16.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 54 45 8c 
+vfwmaccbf16.vf v8, fa0, v4, v0.t
+
+# CHECK-INST: vfwmaccbf16.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 54 45 8e 
+vfwmaccbf16.vf v8, fa0, v4
+
+# Check scalar half FP load/store/move included in this extension.
+
+# CHECK-INST: flh ft0, 12(a0)
+# CHECK-ENCODING: [0x07,0x10,0xc5,0x00]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 07 10 c5 00 
+flh f0, 12(a0)
+
+# CHECK-INST: fsh ft6, 2047(s4)
+# CHECK-ENCODING: [0xa7,0x1f,0x6a,0x7e]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: a7 1f 6a 7e 
+fsh f6, 2047(s4)
+
+# CHECK-INST: fmv.x.h a2, fs7
+# CHECK-ENCODING: [0x53,0x86,0x0b,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 53 86 0b e4 
+fmv.x.h a2, fs7
+
+# CHECK-INST: fmv.h.x ft1, a6
+# CHECK-ENCODING: [0xd3,0x00,0x08,0xf4]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: d3 00 08 f4 
+fmv.h.x ft1, a6
Index: llvm/test/MC/RISCV/rvv/zvfbfwma-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvfbfwma-invalid.s
@@ -0,0 +1,11 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zvfbfwma,+d < %s 2>&1 | \
+# RUN:   FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zvfbfwma,+d < %s 2>&1 | \
+# RUN:   FileCheck 

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 511081.

CHANGES SINCE LAST ACTION
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https://reviews.llvm.org/D147611

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvfbfmin.s

Index: llvm/test/MC/RISCV/rvv/zvfbfmin.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvfbfmin.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfmin - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfmin - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: vfncvtbf16.f.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x4e,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 4e 48 
+vfncvtbf16.f.f.w v8, v4, v0.t
+
+# CHECK-INST: vfncvtbf16.f.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x4e,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 4e 4a 
+vfncvtbf16.f.f.w v8, v4
+
+# CHECK-INST: vfwcvtbf16.f.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x46,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 46 48 
+vfwcvtbf16.f.f.v v8, v4, v0.t
+
+# CHECK-INST: vfwcvtbf16.f.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x46,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 46 4a 
+vfwcvtbf16.f.f.v v8, v4
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -239,3 +239,6 @@
 
 .attribute arch, "rv32if_zfbfmin0p2"
 # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p2"
+
+.attribute arch, "rv32if_zvfbfmin0p2"
+# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p2_zvl32b1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -66,6 +66,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -139,6 +140,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZFBFMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+f,+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s
 
 ; CHECK: .attribute 4, 16
 
@@ -207,6 +209,7 @@
 ; RV32ZVKSH: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
 ; RV32ZICOND: .attribute 5, "rv32i2p1_zicond1p0"
 ; RV32ZFBFMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p2"
+; RV32ZVFBFMIN: .attribute 5, 

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

[Alex Bradbury via Phabricator via cfe-commits]

asb updated this revision to Diff 511080.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147610/new/

https://reviews.llvm.org/D147610

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zfbfmin-invalid.s
  llvm/test/MC/RISCV/rv32zfbfmin-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s

Index: llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
===
--- llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
+++ llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
@@ -1,7 +1,7 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zhinxmin %s 2>&1 | FileCheck %s
 
 # Not support float registers
-flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
+flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
 
 # Invalid instructions
 fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv64zhinx-invalid.s
===
--- llvm/test/MC/RISCV/rv64zhinx-invalid.s
+++ llvm/test/MC/RISCV/rv64zhinx-invalid.s
@@ -1,7 +1,7 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s
 
 # Not support float registers
-flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
+flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
 
 # Invalid instructions
 fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv32zfbfmin-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfbfmin-valid.s
@@ -0,0 +1,56 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfbfmin,+f -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfbfmin,+f -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfbfmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfbfmin,+f -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfbfmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfbfmin,+f -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: flh ft0, 12(a0)
+# CHECK-ASM: encoding: [0x07,0x10,0xc5,0x00]
+flh f0, 12(a0)
+# CHECK-ASM-AND-OBJ: flh ft1, 4(ra)
+# CHECK-ASM: encoding: [0x87,0x90,0x40,0x00]
+flh f1, +4(ra)
+# CHECK-ASM-AND-OBJ: flh ft2, -2048(a3)
+# CHECK-ASM: encoding: [0x07,0x91,0x06,0x80]
+flh f2, -2048(x13)
+# CHECK-ASM-AND-OBJ: flh ft3, -2048(s1)
+# CHECK-ASM: encoding: [0x87,0x91,0x04,0x80]
+flh f3, %lo(2048)(s1)
+# CHECK-ASM-AND-OBJ: flh ft4, 2047(s2)
+# CHECK-ASM: encoding: [0x07,0x12,0xf9,0x7f]
+flh f4, 2047(s2)
+# CHECK-ASM-AND-OBJ: flh ft5, 0(s3)
+# CHECK-ASM: encoding: [0x87,0x92,0x09,0x00]
+flh f5, 0(s3)
+
+# CHECK-ASM-AND-OBJ: fsh ft6, 2047(s4)
+# CHECK-ASM: encoding: [0xa7,0x1f,0x6a,0x7e]
+fsh f6, 2047(s4)
+# CHECK-ASM-AND-OBJ: fsh ft7, -2048(s5)
+# CHECK-ASM: encoding: [0x27,0x90,0x7a,0x80]
+fsh f7, -2048(s5)
+# CHECK-ASM-AND-OBJ: fsh fs0, -2048(s6)
+# CHECK-ASM: encoding: [0x27,0x10,0x8b,0x80]
+fsh f8, %lo(2048)(s6)
+# CHECK-ASM-AND-OBJ: fsh fs1, 999(s7)
+# CHECK-ASM: encoding: [0xa7,0x93,0x9b,0x3e]
+fsh f9, 999(s7)
+
+# CHECK-ASM-AND-OBJ: fmv.x.h a2, fs7
+# CHECK-ASM: encoding: [0x53,0x86,0x0b,0xe4]
+fmv.x.h a2, fs7
+# CHECK-ASM-AND-OBJ: fmv.h.x ft1, a6
+# CHECK-ASM: encoding: [0xd3,0x00,0x08,0xf4]
+fmv.h.x ft1, a6
+
+# CHECK-ASM-AND-OBJ: fcvt.s.bf16 fa0, ft0
+# CHECK-ASM: encoding: [0x53,0x75,0x60,0x10]
+fcvt.s.bf16 fa0, ft0
+# CHECK-ASM-AND-OBJ: fcvt.bf16.s ft2, fa2
+# CHECK-ASM: encoding: [0x53,0x71,0x46,0x44]
+fcvt.bf16.s ft2, fa2
Index: llvm/test/MC/RISCV/rv32zfbfmin-invalid.s
===
--- 

[PATCH] D147612: [RISCV][MC] Add support for experimental Zvfbfwma extension

[Alex Bradbury via Phabricator via cfe-commits]

asb created this revision.
asb added reviewers: reames, craig.topper.
Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, 
frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, 
s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, 
sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
Herald added a project: All.
asb requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added projects: clang, LLVM.

The current specification version doesn't explicitly mark Zvfbfwma as dependent 
on Zve32f, but this is believed to be an oversight. See 
https://github.com/riscv/riscv-bfloat16/pull/34.

As currently specified, Zvfbfwma does not appear to have a dependency on 
Zvfbfmin or Zfbfmin.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D147612

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
  llvm/test/MC/RISCV/rvv/zvfbfwma-invalid.s
  llvm/test/MC/RISCV/rvv/zvfbfwma.s

Index: llvm/test/MC/RISCV/rvv/zvfbfwma.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvfbfwma.s
@@ -0,0 +1,68 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfwma - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfwma - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfwma %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: vfwmaccbf16.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 14 4a 8c 
+vfwmaccbf16.vv v8, v20, v4, v0.t
+
+# CHECK-INST: vfwmaccbf16.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 14 4a 8e 
+vfwmaccbf16.vv v8, v20, v4
+
+# CHECK-INST: vfwmaccbf16.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 54 45 8c 
+vfwmaccbf16.vf v8, fa0, v4, v0.t
+
+# CHECK-INST: vfwmaccbf16.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 57 54 45 8e 
+vfwmaccbf16.vf v8, fa0, v4
+
+# Check scalar half FP load/store/move included in this extension.
+
+# CHECK-INST: flh ft0, 12(a0)
+# CHECK-ENCODING: [0x07,0x10,0xc5,0x00]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: 07 10 c5 00 
+flh f0, 12(a0)
+
+# CHECK-INST: fsh ft6, 2047(s4)
+# CHECK-ENCODING: [0xa7,0x1f,0x6a,0x7e]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 widening mul-add){{$}}
+# CHECK-UNKNOWN: a7 1f 6a 7e 
+fsh f6, 2047(s4)
+
+# CHECK-INST: fmv.x.h a2, fs7
+# CHECK-ENCODING: [0x53,0x86,0x0b,0xe4]
+# CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts) or 'Zvfbfwma' (Vector BF16 

[PATCH] D147611: [RISCV][MC] Add support for experimental Zvfbfmin extension

[Alex Bradbury via Phabricator via cfe-commits]

asb created this revision.
asb added reviewers: reames, craig.topper.
Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, 
frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, 
s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, 
sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
Herald added a project: All.
asb requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added projects: clang, LLVM.

The current specification version doesn't explicitly mark Zvfbfmin as dependent 
on Zve32f, but this is believed to be an oversight. See 
https://github.com/riscv/riscv-bfloat16/pull/34.

Zvfbfmin does not appear to have a dependency on Zfbfmin as currently specified.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D147611

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvfbf.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rvv/zvfbfmin.s

Index: llvm/test/MC/RISCV/rvv/zvfbfmin.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rvv/zvfbfmin.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc -triple=riscv32 -show-encoding -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv32 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfmin - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv32 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+# RUN: llvm-mc -triple=riscv64 -show-encoding -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:   | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding -mattr=+v,+f %s 2>&1 \
+# RUN:   | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d --mattr=+f,+experimental-zvfbfmin - \
+# RUN:| FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj -mattr=+f,+experimental-zvfbfmin %s \
+# RUN:| llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+# CHECK-INST: vfncvtbf16.f.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x4e,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 4e 48 
+vfncvtbf16.f.f.w v8, v4, v0.t
+
+# CHECK-INST: vfncvtbf16.f.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x4e,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 4e 4a 
+vfncvtbf16.f.f.w v8, v4
+
+# CHECK-INST: vfwcvtbf16.f.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x46,0x48]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 46 48 
+vfwcvtbf16.f.f.v v8, v4, v0.t
+
+# CHECK-INST: vfwcvtbf16.f.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x46,0x4a]
+# CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}}
+# CHECK-UNKNOWN: 57 94 46 4a 
+vfwcvtbf16.f.f.v v8, v4
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -239,3 +239,6 @@
 
 .attribute arch, "rv32if_zfbfmin0p2"
 # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p2"
+
+.attribute arch, "rv32if_zvfbfmin0p2"
+# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p2_zvl32b1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -66,6 +66,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
 ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZFBFMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+f,+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck 

[PATCH] D147610: [RISCV][MC] Add support for experimental Zfbfmin extension

[Alex Bradbury via Phabricator via cfe-commits]

asb created this revision.
asb added reviewers: reames, craig.topper.
Herald added subscribers: jobnoorman, luke, wingo, pmatos, VincentWu, vkmr, 
frasercrmck, jdoerfert, evandro, luismarques, apazos, sameer.abuasal, 
s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, 
rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, 
sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
Herald added a project: All.
asb requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD, MaskRay.
Herald added projects: clang, LLVM.

As documented, this extension includes FLH, FSH, FMV.H.X, and FMH.X.H as 
defined in Zfh/Zfhmin, but doesn't require either extension.

No Zfbfinxmin has been defined (though you would expect one in the future, for 
symmetry with Zfhinxmin). See issue 
https://github.com/riscv/riscv-bfloat16/issues/27.

This patch is not ready for merging because the fcvt.bf16.s encoding collides 
with fround.h from zfa. See issue 
https://github.com/riscv/riscv-bfloat16/issues/33. Applying this patch causes 
tests failures due to this. Posting in order to allow early review, though I 
intended to wait for the encoding clash to be resolved before pushing to get 
this committed.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D147610

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zfbfmin-invalid.s
  llvm/test/MC/RISCV/rv32zfbfmin-valid.s
  llvm/test/MC/RISCV/rv64zhinx-invalid.s
  llvm/test/MC/RISCV/rv64zhinxmin-invalid.s

Index: llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
===
--- llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
+++ llvm/test/MC/RISCV/rv64zhinxmin-invalid.s
@@ -1,7 +1,7 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zhinxmin %s 2>&1 | FileCheck %s
 
 # Not support float registers
-flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
+flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
 
 # Invalid instructions
 fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv64zhinx-invalid.s
===
--- llvm/test/MC/RISCV/rv64zhinx-invalid.s
+++ llvm/test/MC/RISCV/rv64zhinx-invalid.s
@@ -1,7 +1,7 @@
 # RUN: not llvm-mc -triple riscv64 -mattr=+zhinx %s 2>&1 | FileCheck %s
 
 # Not support float registers
-flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal){{$}}
+flh fa4, 12(sp) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}}
 
 # Invalid instructions
 fsh a5, 12(sp) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
Index: llvm/test/MC/RISCV/rv32zfbfmin-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zfbfmin-valid.s
@@ -0,0 +1,56 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zfbfmin,+f -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zfbfmin,+f -riscv-no-aliases -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zfbfmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfbfmin,+f -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zfbfmin,+d < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zfbfmin,+f -M no-aliases -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: flh ft0, 12(a0)
+# CHECK-ASM: encoding: [0x07,0x10,0xc5,0x00]
+flh f0, 12(a0)
+# CHECK-ASM-AND-OBJ: flh ft1, 4(ra)
+# CHECK-ASM: encoding: [0x87,0x90,0x40,0x00]
+flh f1, +4(ra)
+# CHECK-ASM-AND-OBJ: flh ft2, -2048(a3)
+# CHECK-ASM: encoding: [0x07,0x91,0x06,0x80]
+flh f2, -2048(x13)
+# CHECK-ASM-AND-OBJ: flh ft3, -2048(s1)
+# CHECK-ASM: encoding: 

[PATCH] D147261: [RISCV] Add Zicsr and Zifencei to CPUs in RISCVProcessors.td.

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM. I also understand that Rocket and SCR-1 support zicsr and zifencei in all 
standard configurations (and their respective repos seem to confirm this).


Repository:
  rG LLVM Github Monorepo

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[PATCH] D147179: [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version

[Alex Bradbury via Phabricator via cfe-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM, thanks (though see minor note about tweaking commit message to clarify 
the change).


Repository:
  rG LLVM Github Monorepo

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[PATCH] D147179: [RISCV] Bump I, F, D, and A extension versions to 20191214 spec version

[Alex Bradbury via Phabricator via cfe-commits]

asb added a comment.

I've added a couple of inline comments, but otherwise this seems fine to me. 
I'd suggest updating the patch description to reference Philip's documentation 
patch (which was posted soon after this), and also to explain why there are no 
codegen changes (I think "Either changes to the specification required no 
codegen changes, or LLVM was written against a newer version of the 
specification than it claimed" is vague but accurate).




Comment at: llvm/lib/Support/RISCVISAInfo.cpp:625
   case 'g':
 // g = imafd
 if (Arch.size() > 5 && isdigit(Arch[5]))

Perhaps update to `// g expands to extensions in RISCVGImplications.` or delete 
altogether.



Comment at: llvm/unittests/Support/RISCVISAInfoTest.cpp:253
 TEST(ParseArchString, AcceptsVersionInLongOrShortForm) {
-  for (StringRef Input : {"rv64i2", "rv64i2p0"}) {
-auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true);

Why is this test dropped? It's not redundant as there's a slightly separate 
path for parsing the version on the base ISA vs other extensions (this could 
perhaps be refactored).


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[PATCH] D146946: [RISCV][MC] Add support for experimental zicond extension

[Alex Bradbury via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGd3291c692c0a: [RISCV][MC] Add support for the experimental 
zicond extension (authored by asb).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D146946/new/

https://reviews.llvm.org/D146946

Files:
  clang/test/Preprocessor/riscv-target-features.c
  llvm/docs/RISCVUsage.rst
  llvm/docs/ReleaseNotes.rst
  llvm/lib/Support/RISCVISAInfo.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
  llvm/test/CodeGen/RISCV/attributes.ll
  llvm/test/MC/RISCV/attribute-arch.s
  llvm/test/MC/RISCV/rv32zicond-invalid.s
  llvm/test/MC/RISCV/rv32zicond-valid.s

Index: llvm/test/MC/RISCV/rv32zicond-valid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zicond-valid.s
@@ -0,0 +1,18 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zicond -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zicond -show-encoding \
+# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zicond < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zicond < %s \
+# RUN: | llvm-objdump --mattr=+experimental-zicond -d -r - \
+# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: czero.eqz t0, a3, ra
+# CHECK-ASM: encoding: [0xb3,0xd2,0x16,0x0e]
+czero.eqz t0, a3, ra
+
+# CHECK-ASM-AND-OBJ: czero.nez a1, gp, t6
+# CHECK-ASM: encoding: [0xb3,0xf5,0xf1,0x0f]
+czero.nez a1, gp, t6
Index: llvm/test/MC/RISCV/rv32zicond-invalid.s
===
--- /dev/null
+++ llvm/test/MC/RISCV/rv32zicond-invalid.s
@@ -0,0 +1,18 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zicond < %s 2>&1 | FileCheck %s
+
+# Use of operand modifier on register name
+czero.eqz t1, %lo(t2), t3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+
+# Invalid register name
+czero.nez a4, a3, foo # CHECK: :[[@LINE]]:19: error: invalid operand for instruction
+
+# Invalid operand type
+czero.eqz t1, 2, t3 # CHECK: :[[@LINE]]:15: error: invalid operand for instruction
+
+# Too many operands
+czero.eqz t1, t2, t3, t4 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+czero.nez t1, t2, t3, 4 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+
+# Too few operands
+czero.eqz t1, t2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
Index: llvm/test/MC/RISCV/attribute-arch.s
===
--- llvm/test/MC/RISCV/attribute-arch.s
+++ llvm/test/MC/RISCV/attribute-arch.s
@@ -236,3 +236,6 @@
 
 .attribute arch, "rv32izfa0p1"
 # CHECK: attribute  5, "rv32i2p0_f2p0_zfa0p1"
+
+.attribute arch, "rv32izicond1p0"
+# CHECK: attribute  5, "rv32i2p0_zicond1p0"
Index: llvm/test/CodeGen/RISCV/attributes.ll
===
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -64,6 +64,7 @@
 ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV32ZVKS %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV32ZVKSED %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV32ZVKSH %s
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV32ZICOND %s
 
 ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -135,6 +136,7 @@
 ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvks %s -o - | FileCheck --check-prefix=RV64ZVKS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksed %s -o - | FileCheck --check-prefix=RV64ZVKSED %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvksh %s -o - | FileCheck --check-prefix=RV64ZVKSH %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicond %s -o - | FileCheck --check-prefix=RV64ZICOND %s
 
 ; CHECK: .attribute 4, 16
 
@@ -201,6 +203,7 @@
 ; RV32ZVKS: .attribute 5, "rv32i2p0_zve32x1p0_zvkb0p3_zvks0p3_zvksed0p3_zvksh0p3_zvl32b1p0"
 ; RV32ZVKSED: .attribute 5, "rv32i2p0_zve32x1p0_zvksed0p3_zvl32b1p0"
 ; RV32ZVKSH: .attribute 5, "rv32i2p0_zve32x1p0_zvksh0p3_zvl32b1p0"
+; RV32ZICOND: .attribute 5,