from:"Amilendra Kodithuwakku via Phabricator via cfe\-commits"

[PATCH] D143587: [Docs] Multilib design

2023-02-09 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra added inline comments.



Comment at: clang/docs/Multilib.rst:89
+   the *last* matching multilib variant, or may use all matching variants,
+   thereby layering them.
+#. Generate ``-isystem`` and ``-L`` arguments. Iterate in reverse order over

What would be the effect of layering? Does this mean multiple choices for 
`--sysroot``, ``-isystem`` and ``-L`` will be used?


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[PATCH] D143587: [Docs] Multilib design

2023-02-09 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra added a comment.

Thanks for the design docs. At a high-level this gives a good summary on what 
you intend the multilib feature to do. Couple of suggestions.




Comment at: clang/docs/Multilib.rst:86-89
+   a match.
+   If more than one variant matches then a toolchain may opt to either use only
+   the *last* matching multilib variant, or may use all matching variants,
+   thereby layering them.

Would it be possible to give more details on how the toolchain makes this 
choice?



Comment at: clang/docs/Multilib.rst:97
+
+Multilib via configuration file shall be considered an experimental feature
+until LLVM 18, at which point ``-print-multi-selection-flags-experimental``

Would it be worth to also add a flag to activate/deactivate the multilib 
feature for the duration that it is experimental?
IIUC, a similar mechanism was used before switching to a new pass manager.


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[PATCH] D143590: [NFC] Simplify test from change D73904

2023-02-08 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra accepted this revision.
amilendra added a comment.
This revision is now accepted and ready to land.

LGTM.


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[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77

2022-03-14 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra added a comment.

LGTM.


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[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77

2022-03-14 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra added inline comments.



Comment at: llvm/lib/Target/AArch64/AArch64.td:978
  FeatureNEON, FeatureRCPC, FeaturePerfMon,
  FeatureSPE, FeatureFullFP16, FeatureDotProd];
   list X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,

stuij wrote:
> amilendra wrote:
> > stuij wrote:
> > > dmgreen wrote:
> > > > X1 and A77 missing SSBS too. Should they be added at the same time?
> > > Yes they should. Thanks!
> > Maybe add unit tests for X1 and A77 too?
> I did. See the top file.
> 
> In general it'd be good to have better testing for individual cores. This 
> will happen more structurally in future changes.
Ah yes, I was expecting tests similar to that for `R82` in 
aarch64-target-features.c. Anyway what you have already is good for `ssbs`


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[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77

2022-03-14 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra accepted this revision.
amilendra added inline comments.
This revision is now accepted and ready to land.



Comment at: llvm/lib/Target/AArch64/AArch64.td:978
  FeatureNEON, FeatureRCPC, FeaturePerfMon,
  FeatureSPE, FeatureFullFP16, FeatureDotProd];
   list X1C  = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,

stuij wrote:
> dmgreen wrote:
> > X1 and A77 missing SSBS too. Should they be added at the same time?
> Yes they should. Thanks!
Maybe add unit tests for X1 and A77 too?


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[PATCH] D119166: [clang][ARM] Re-word PACBTI warning.

2022-02-08 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

This revision was automatically updated to reflect the committed changes.
Closed by commit rG424e850f1ebc: [clang][ARM] Re-word PACBTI warning. (authored 
by amilendra).

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Files:
  clang/include/clang/Basic/DiagnosticCommonKinds.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/arm-security-options.c


Index: clang/test/Driver/arm-security-options.c
===
--- clang/test/Driver/arm-security-options.c
+++ clang/test/Driver/arm-security-options.c
@@ -90,4 +90,4 @@
 // BAD-B-KEY-COMBINATION: invalid branch protection option 'b-key' in 
'-mbranch-protection={{.*}}'
 // BAD-LEAF-COMBINATION: invalid branch protection option 'leaf' in 
'-mbranch-protection={{.*}}'
 
-// INCOMPATIBLE-ARCH: ignoring '-mbranch-protection=' option because the 
'{{.*}}' architecture does not support it
+// INCOMPATIBLE-ARCH: '-mbranch-protection=' option is incompatible with the 
'{{.*}}' architecture
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -1639,7 +1639,7 @@
   const Driver  = TC.getDriver();
   const llvm::Triple  = TC.getEffectiveTriple();
   if (!(isAArch64 || (Triple.isArmT32() && Triple.isArmMClass(
-D.Diag(diag::warn_target_unsupported_branch_protection_option)
+D.Diag(diag::warn_incompatible_branch_protection_option)
 << Triple.getArchName();
 
   StringRef Scope, Key;
Index: clang/include/clang/Basic/DiagnosticCommonKinds.td
===
--- clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -145,8 +145,8 @@
 def err_nullability_conflicting : Error<
   "nullability specifier %0 conflicts with existing specifier %1">;
 
-def warn_target_unsupported_branch_protection_option: Warning <
-  "ignoring '-mbranch-protection=' option because the '%0' architecture does 
not support it">,
+def warn_incompatible_branch_protection_option: Warning <
+  "'-mbranch-protection=' option is incompatible with the '%0' architecture">,
   InGroup;
 
 def warn_target_unsupported_branch_protection_attribute: Warning <


Index: clang/test/Driver/arm-security-options.c
===
--- clang/test/Driver/arm-security-options.c
+++ clang/test/Driver/arm-security-options.c
@@ -90,4 +90,4 @@
 // BAD-B-KEY-COMBINATION: invalid branch protection option 'b-key' in '-mbranch-protection={{.*}}'
 // BAD-LEAF-COMBINATION: invalid branch protection option 'leaf' in '-mbranch-protection={{.*}}'
 
-// INCOMPATIBLE-ARCH: ignoring '-mbranch-protection=' option because the '{{.*}}' architecture does not support it
+// INCOMPATIBLE-ARCH: '-mbranch-protection=' option is incompatible with the '{{.*}}' architecture
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -1639,7 +1639,7 @@
   const Driver  = TC.getDriver();
   const llvm::Triple  = TC.getEffectiveTriple();
   if (!(isAArch64 || (Triple.isArmT32() && Triple.isArmMClass(
-D.Diag(diag::warn_target_unsupported_branch_protection_option)
+D.Diag(diag::warn_incompatible_branch_protection_option)
 << Triple.getArchName();
 
   StringRef Scope, Key;
Index: clang/include/clang/Basic/DiagnosticCommonKinds.td
===
--- clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -145,8 +145,8 @@
 def err_nullability_conflicting : Error<
   "nullability specifier %0 conflicts with existing specifier %1">;
 
-def warn_target_unsupported_branch_protection_option: Warning <
-  "ignoring '-mbranch-protection=' option because the '%0' architecture does not support it">,
+def warn_incompatible_branch_protection_option: Warning <
+  "'-mbranch-protection=' option is incompatible with the '%0' architecture">,
   InGroup;
 
 def warn_target_unsupported_branch_protection_attribute: Warning <
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[PATCH] D119166: [clang][ARM] Re-word PACBTI warning.

2022-02-08 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra updated this revision to Diff 406780.
amilendra added a comment.

[clang][ARM] Re-word PACBTI warning.

Fix grammar error.


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Files:
  clang/include/clang/Basic/DiagnosticCommonKinds.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/arm-security-options.c


Index: clang/test/Driver/arm-security-options.c
===
--- clang/test/Driver/arm-security-options.c
+++ clang/test/Driver/arm-security-options.c
@@ -90,4 +90,4 @@
 // BAD-B-KEY-COMBINATION: invalid branch protection option 'b-key' in 
'-mbranch-protection={{.*}}'
 // BAD-LEAF-COMBINATION: invalid branch protection option 'leaf' in 
'-mbranch-protection={{.*}}'
 
-// INCOMPATIBLE-ARCH: ignoring '-mbranch-protection=' option because the 
'{{.*}}' architecture does not support it
+// INCOMPATIBLE-ARCH: '-mbranch-protection=' option is incompatible with the 
'{{.*}}' architecture
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -1639,7 +1639,7 @@
   const Driver  = TC.getDriver();
   const llvm::Triple  = TC.getEffectiveTriple();
   if (!(isAArch64 || (Triple.isArmT32() && Triple.isArmMClass(
-D.Diag(diag::warn_target_unsupported_branch_protection_option)
+D.Diag(diag::warn_incompatible_branch_protection_option)
 << Triple.getArchName();
 
   StringRef Scope, Key;
Index: clang/include/clang/Basic/DiagnosticCommonKinds.td
===
--- clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -145,8 +145,8 @@
 def err_nullability_conflicting : Error<
   "nullability specifier %0 conflicts with existing specifier %1">;
 
-def warn_target_unsupported_branch_protection_option: Warning <
-  "ignoring '-mbranch-protection=' option because the '%0' architecture does 
not support it">,
+def warn_incompatible_branch_protection_option: Warning <
+  "'-mbranch-protection=' option is incompatible with the '%0' architecture">,
   InGroup;
 
 def warn_target_unsupported_branch_protection_attribute: Warning <


Index: clang/test/Driver/arm-security-options.c
===
--- clang/test/Driver/arm-security-options.c
+++ clang/test/Driver/arm-security-options.c
@@ -90,4 +90,4 @@
 // BAD-B-KEY-COMBINATION: invalid branch protection option 'b-key' in '-mbranch-protection={{.*}}'
 // BAD-LEAF-COMBINATION: invalid branch protection option 'leaf' in '-mbranch-protection={{.*}}'
 
-// INCOMPATIBLE-ARCH: ignoring '-mbranch-protection=' option because the '{{.*}}' architecture does not support it
+// INCOMPATIBLE-ARCH: '-mbranch-protection=' option is incompatible with the '{{.*}}' architecture
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -1639,7 +1639,7 @@
   const Driver  = TC.getDriver();
   const llvm::Triple  = TC.getEffectiveTriple();
   if (!(isAArch64 || (Triple.isArmT32() && Triple.isArmMClass(
-D.Diag(diag::warn_target_unsupported_branch_protection_option)
+D.Diag(diag::warn_incompatible_branch_protection_option)
 << Triple.getArchName();
 
   StringRef Scope, Key;
Index: clang/include/clang/Basic/DiagnosticCommonKinds.td
===
--- clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -145,8 +145,8 @@
 def err_nullability_conflicting : Error<
   "nullability specifier %0 conflicts with existing specifier %1">;
 
-def warn_target_unsupported_branch_protection_option: Warning <
-  "ignoring '-mbranch-protection=' option because the '%0' architecture does not support it">,
+def warn_incompatible_branch_protection_option: Warning <
+  "'-mbranch-protection=' option is incompatible with the '%0' architecture">,
   InGroup;
 
 def warn_target_unsupported_branch_protection_attribute: Warning <
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[PATCH] D119166: [clang][ARM] Re-word PACBTI warning.

2022-02-07 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra created this revision.
amilendra added reviewers: chill, stuij.
Herald added a subscriber: kristof.beyls.
amilendra requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

The original warning added in D115501  when 
pacbti is used with an
incompatible architecture was not exactly correct because it was
not really ignored and can affect codegen.

Therefore reword to say that the pacbti option is incompatible with
the given architecture.


Repository:
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Files:
  clang/include/clang/Basic/DiagnosticCommonKinds.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/arm-security-options.c


Index: clang/test/Driver/arm-security-options.c
===
--- clang/test/Driver/arm-security-options.c
+++ clang/test/Driver/arm-security-options.c
@@ -90,4 +90,4 @@
 // BAD-B-KEY-COMBINATION: invalid branch protection option 'b-key' in 
'-mbranch-protection={{.*}}'
 // BAD-LEAF-COMBINATION: invalid branch protection option 'leaf' in 
'-mbranch-protection={{.*}}'
 
-// INCOMPATIBLE-ARCH: ignoring '-mbranch-protection=' option because the 
'{{.*}}' architecture does not support it
+// INCOMPATIBLE-ARCH: '-mbranch-protection=' option incompatible with the 
'{{.*}}' architecture
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -1639,7 +1639,7 @@
   const Driver  = TC.getDriver();
   const llvm::Triple  = TC.getEffectiveTriple();
   if (!(isAArch64 || (Triple.isArmT32() && Triple.isArmMClass(
-D.Diag(diag::warn_target_unsupported_branch_protection_option)
+D.Diag(diag::warn_incompatible_branch_protection_option)
 << Triple.getArchName();
 
   StringRef Scope, Key;
Index: clang/include/clang/Basic/DiagnosticCommonKinds.td
===
--- clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -145,8 +145,8 @@
 def err_nullability_conflicting : Error<
   "nullability specifier %0 conflicts with existing specifier %1">;
 
-def warn_target_unsupported_branch_protection_option: Warning <
-  "ignoring '-mbranch-protection=' option because the '%0' architecture does 
not support it">,
+def warn_incompatible_branch_protection_option: Warning <
+  "'-mbranch-protection=' option incompatible with the '%0' architecture">,
   InGroup;
 
 def warn_target_unsupported_branch_protection_attribute: Warning <


Index: clang/test/Driver/arm-security-options.c
===
--- clang/test/Driver/arm-security-options.c
+++ clang/test/Driver/arm-security-options.c
@@ -90,4 +90,4 @@
 // BAD-B-KEY-COMBINATION: invalid branch protection option 'b-key' in '-mbranch-protection={{.*}}'
 // BAD-LEAF-COMBINATION: invalid branch protection option 'leaf' in '-mbranch-protection={{.*}}'
 
-// INCOMPATIBLE-ARCH: ignoring '-mbranch-protection=' option because the '{{.*}}' architecture does not support it
+// INCOMPATIBLE-ARCH: '-mbranch-protection=' option incompatible with the '{{.*}}' architecture
Index: clang/lib/Driver/ToolChains/Clang.cpp
===
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -1639,7 +1639,7 @@
   const Driver  = TC.getDriver();
   const llvm::Triple  = TC.getEffectiveTriple();
   if (!(isAArch64 || (Triple.isArmT32() && Triple.isArmMClass(
-D.Diag(diag::warn_target_unsupported_branch_protection_option)
+D.Diag(diag::warn_incompatible_branch_protection_option)
 << Triple.getArchName();
 
   StringRef Scope, Key;
Index: clang/include/clang/Basic/DiagnosticCommonKinds.td
===
--- clang/include/clang/Basic/DiagnosticCommonKinds.td
+++ clang/include/clang/Basic/DiagnosticCommonKinds.td
@@ -145,8 +145,8 @@
 def err_nullability_conflicting : Error<
   "nullability specifier %0 conflicts with existing specifier %1">;
 
-def warn_target_unsupported_branch_protection_option: Warning <
-  "ignoring '-mbranch-protection=' option because the '%0' architecture does not support it">,
+def warn_incompatible_branch_protection_option: Warning <
+  "'-mbranch-protection=' option incompatible with the '%0' architecture">,
   InGroup;
 
 def warn_target_unsupported_branch_protection_attribute: Warning <
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[PATCH] D119008: Add Cortex-X1C to Clang LLVM 14 release notes

2022-02-07 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra added a comment.

LGTM.


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[PATCH] D118380: Add info on PACBTI-M to the Clang release notes

2022-01-31 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra added a comment.

LGTM.


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[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

2022-01-28 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG1f08b0867412: [clang][ARM] Emit warnings when PACBTI-M is 
used with unsupported architectures (authored by amilendra).

Repository:
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CHANGES SINCE LAST ACTION
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Files:
  clang/include/clang/Basic/DiagnosticCommonKinds.td
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/arm-branch-protection-attr-2.c
  clang/test/CodeGen/arm_acle.c
  clang/test/Driver/aarch64-security-options.c
  clang/test/Driver/arm-security-options.c
  clang/test/Frontend/arm-branch-protection-default-arch.c
  clang/test/Frontend/arm-ignore-branch-protection-option.c
  clang/test/Frontend/arm-invalid-branch-protection.c
  clang/test/Sema/arm-branch-protection-attr-warn.c
  clang/test/Sema/arm-branch-protection.c
  llvm/include/llvm/ADT/Triple.h
  llvm/unittests/ADT/TripleTest.cpp

Index: llvm/unittests/ADT/TripleTest.cpp
===
--- llvm/unittests/ADT/TripleTest.cpp
+++ llvm/unittests/ADT/TripleTest.cpp
@@ -1702,4 +1702,148 @@
 EXPECT_EQ(Triple::AArch64SubArch_arm64e, T.getSubArch());
   }
 }
+
+TEST(TripleTest, isArmT32) {
+  // Not isArmT32
+  {
+Triple T = Triple("thumbv6m");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv8m.base");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7s");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7k");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7ve");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6m");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6k");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6t2");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv5");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv5te");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv4t");
+EXPECT_FALSE(T.isArmT32());
+  }
+
+  // isArmT32
+  {
+Triple T = Triple("arm");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7m");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7em");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv8m.main");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv8.1m.main");
+EXPECT_TRUE(T.isArmT32());
+  }
+}
+
+TEST(TripleTest, isArmMClass) {
+  // not M-class
+  {
+Triple T = Triple("armv7s");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7k");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7ve");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv6");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv6k");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv6t2");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv5");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv5te");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv4t");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("arm");
+EXPECT_FALSE(T.isArmMClass());
+  }
+
+  // is M-class
+  {
+Triple T = Triple("armv6m");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7m");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7em");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv8m.base");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv8m.main");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv8.1m.main");
+EXPECT_TRUE(T.isArmMClass());
+  }
+}
 } // end anonymous namespace
Index: llvm/include/llvm/ADT/Triple.h
===
--- llvm/include/llvm/ADT/Triple.h
+++ llvm/include/llvm/ADT/Triple.h
@@ -721,6 +721,41 @@
isOSBinFormatELF();
   }
 
+  /// Tests whether the target is T32.
+  bool isArmT32() const {
+switch (auto SubArch = getSubArch()) {
+case Triple::ARMSubArch_v8m_baseline:
+case Triple::ARMSubArch_v7s:
+case Triple::ARMSubArch_v7k:
+case Triple::ARMSubArch_v7ve:
+case Triple::ARMSubArch_v6:
+case Triple::ARMSubArch_v6m:
+case Triple::ARMSubArch_v6k:
+case

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

2022-01-28 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra added a comment.

The CI errors seem unrelated.

  Failed Tests (9):
libarcher :: races/critical-unrelated.c
libarcher :: races/lock-nested-unrelated.c
libarcher :: races/lock-unrelated.c
libarcher :: races/parallel-simple.c
libarcher :: races/task-dependency.c
libarcher :: races/task-taskgroup-unrelated.c
libarcher :: races/task-taskwait-nested.c
libarcher :: races/task-two.c
libarcher :: task/task_late_fulfill.c

So pushing these changes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115501/new/

https://reviews.llvm.org/D115501

___
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[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

2022-01-27 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra updated this revision to Diff 403801.
amilendra added a comment.

Fix clang-format errors.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115501/new/

https://reviews.llvm.org/D115501

Files:
  clang/include/clang/Basic/DiagnosticCommonKinds.td
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/arm-branch-protection-attr-2.c
  clang/test/CodeGen/arm_acle.c
  clang/test/Driver/aarch64-security-options.c
  clang/test/Driver/arm-security-options.c
  clang/test/Frontend/arm-branch-protection-default-arch.c
  clang/test/Frontend/arm-ignore-branch-protection-option.c
  clang/test/Frontend/arm-invalid-branch-protection.c
  clang/test/Sema/arm-branch-protection-attr-warn.c
  clang/test/Sema/arm-branch-protection.c
  llvm/include/llvm/ADT/Triple.h
  llvm/unittests/ADT/TripleTest.cpp

Index: llvm/unittests/ADT/TripleTest.cpp
===
--- llvm/unittests/ADT/TripleTest.cpp
+++ llvm/unittests/ADT/TripleTest.cpp
@@ -1702,4 +1702,148 @@
 EXPECT_EQ(Triple::AArch64SubArch_arm64e, T.getSubArch());
   }
 }
+
+TEST(TripleTest, isArmT32) {
+  // Not isArmT32
+  {
+Triple T = Triple("thumbv6m");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv8m.base");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7s");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7k");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7ve");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6m");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6k");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6t2");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv5");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv5te");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv4t");
+EXPECT_FALSE(T.isArmT32());
+  }
+
+  // isArmT32
+  {
+Triple T = Triple("arm");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7m");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7em");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv8m.main");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv8.1m.main");
+EXPECT_TRUE(T.isArmT32());
+  }
+}
+
+TEST(TripleTest, isArmMClass) {
+  // not M-class
+  {
+Triple T = Triple("armv7s");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7k");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7ve");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv6");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv6k");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv6t2");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv5");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv5te");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv4t");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("arm");
+EXPECT_FALSE(T.isArmMClass());
+  }
+
+  // is M-class
+  {
+Triple T = Triple("armv6m");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7m");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7em");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv8m.base");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv8m.main");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv8.1m.main");
+EXPECT_TRUE(T.isArmMClass());
+  }
+}
 } // end anonymous namespace
Index: llvm/include/llvm/ADT/Triple.h
===
--- llvm/include/llvm/ADT/Triple.h
+++ llvm/include/llvm/ADT/Triple.h
@@ -721,6 +721,41 @@
isOSBinFormatELF();
   }
 
+  /// Tests whether the target is T32.
+  bool isArmT32() const {
+switch (auto SubArch = getSubArch()) {
+case Triple::ARMSubArch_v8m_baseline:
+case Triple::ARMSubArch_v7s:
+case Triple::ARMSubArch_v7k:
+case Triple::ARMSubArch_v7ve:
+case Triple::ARMSubArch_v6:
+case Triple::ARMSubArch_v6m:
+case Triple::ARMSubArch_v6k:
+case Triple::ARMSubArch_v6t2:
+case Triple::ARMSubArch_v5:
+case Triple::ARMSubArch_v5te:
+case Triple::ARMSubArch_v4t:
+  return false;
+default:
+  return true;
+

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

2022-01-24 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra updated this revision to Diff 402661.
amilendra added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115501/new/

https://reviews.llvm.org/D115501

Files:
  clang/include/clang/Basic/DiagnosticCommonKinds.td
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/arm-branch-protection-attr-2.c
  clang/test/CodeGen/arm_acle.c
  clang/test/Driver/aarch64-security-options.c
  clang/test/Driver/arm-security-options.c
  clang/test/Frontend/arm-branch-protection-default-arch.c
  clang/test/Frontend/arm-ignore-branch-protection-option.c
  clang/test/Frontend/arm-invalid-branch-protection.c
  clang/test/Sema/arm-branch-protection-attr-warn.c
  clang/test/Sema/arm-branch-protection.c
  llvm/include/llvm/ADT/Triple.h
  llvm/unittests/ADT/TripleTest.cpp

Index: llvm/unittests/ADT/TripleTest.cpp
===
--- llvm/unittests/ADT/TripleTest.cpp
+++ llvm/unittests/ADT/TripleTest.cpp
@@ -1702,4 +1702,148 @@
 EXPECT_EQ(Triple::AArch64SubArch_arm64e, T.getSubArch());
   }
 }
+
+TEST(TripleTest, isArmT32) {
+  // Not isArmT32
+  {
+Triple T = Triple("thumbv6m");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv8m.base");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7s");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7k");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7ve");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6m");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6k");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6t2");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv5");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv5te");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv4t");
+EXPECT_FALSE(T.isArmT32());
+  }
+
+  // isArmT32
+  {
+Triple T = Triple("arm");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7m");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7em");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv8m.main");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv8.1m.main");
+EXPECT_TRUE(T.isArmT32());
+  }
+}
+
+TEST(TripleTest, isArmMClass) {
+  // not M-class
+  {
+Triple T = Triple("armv7s");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7k");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7ve");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv6");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv6k");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv6t2");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv5");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv5te");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv4t");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("arm");
+EXPECT_FALSE(T.isArmMClass());
+  }
+
+  // is M-class
+  {
+Triple T = Triple("armv6m");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7m");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7em");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv8m.base");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv8m.main");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv8.1m.main");
+EXPECT_TRUE(T.isArmMClass());
+  }
+}
 } // end anonymous namespace
Index: llvm/include/llvm/ADT/Triple.h
===
--- llvm/include/llvm/ADT/Triple.h
+++ llvm/include/llvm/ADT/Triple.h
@@ -721,6 +721,41 @@
isOSBinFormatELF();
   }
 
+  /// Tests whether the target is T32.
+  bool isArmT32() const {
+switch (auto SubArch = getSubArch()) {
+case Triple::ARMSubArch_v8m_baseline:
+case Triple::ARMSubArch_v7s:
+case Triple::ARMSubArch_v7k:
+case Triple::ARMSubArch_v7ve:
+case Triple::ARMSubArch_v6:
+case Triple::ARMSubArch_v6m:
+case Triple::ARMSubArch_v6k:
+case Triple::ARMSubArch_v6t2:
+case Triple::ARMSubArch_v5:
+case Triple::ARMSubArch_v5te:
+case Triple::ARMSubArch_v4t:
+  return false;
+default:
+  return true;
+}
+  }
+
+

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

2022-01-24 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra updated this revision to Diff 402659.
amilendra added a comment.

Add new interface isArmMClass() to the Triple class.
Use isArmT32() and isArmMClass() to emit PACBTI warnings for ARM.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115501/new/

https://reviews.llvm.org/D115501

Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/aarch64-security-options.c
  clang/test/Driver/arm-security-options.c
  clang/test/Sema/arm-branch-protection-attr-warn.c
  llvm/include/llvm/ADT/Triple.h
  llvm/unittests/ADT/TripleTest.cpp

Index: llvm/unittests/ADT/TripleTest.cpp
===
--- llvm/unittests/ADT/TripleTest.cpp
+++ llvm/unittests/ADT/TripleTest.cpp
@@ -1702,4 +1702,148 @@
 EXPECT_EQ(Triple::AArch64SubArch_arm64e, T.getSubArch());
   }
 }
+
+TEST(TripleTest, isArmT32) {
+  // Not isArmT32
+  {
+Triple T = Triple("thumbv6m");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv8m.base");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7s");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7k");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7ve");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6m");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6k");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv6t2");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv5");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv5te");
+EXPECT_FALSE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv4t");
+EXPECT_FALSE(T.isArmT32());
+  }
+
+  // isArmT32
+  {
+Triple T = Triple("arm");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7m");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv7em");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv8m.main");
+EXPECT_TRUE(T.isArmT32());
+  }
+  {
+Triple T = Triple("armv8.1m.main");
+EXPECT_TRUE(T.isArmT32());
+  }
+}
+
+TEST(TripleTest, isArmMClass) {
+  // not M-class
+  {
+Triple T = Triple("armv7s");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7k");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7ve");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv6");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv6k");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv6t2");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv5");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv5te");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv4t");
+EXPECT_FALSE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("arm");
+EXPECT_FALSE(T.isArmMClass());
+  }
+
+  // is M-class
+  {
+Triple T = Triple("armv6m");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7m");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv7em");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv8m.base");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv8m.main");
+EXPECT_TRUE(T.isArmMClass());
+  }
+  {
+Triple T = Triple("armv8.1m.main");
+EXPECT_TRUE(T.isArmMClass());
+  }
+}
 } // end anonymous namespace
Index: llvm/include/llvm/ADT/Triple.h
===
--- llvm/include/llvm/ADT/Triple.h
+++ llvm/include/llvm/ADT/Triple.h
@@ -723,20 +723,39 @@
 
   /// Tests whether the target is T32.
   bool isArmT32() const {
-if (!isARM())
+switch (auto SubArch = getSubArch()) {
+case Triple::ARMSubArch_v8m_baseline:
+case Triple::ARMSubArch_v7s:
+case Triple::ARMSubArch_v7k:
+case Triple::ARMSubArch_v7ve:
+case Triple::ARMSubArch_v6:
+case Triple::ARMSubArch_v6m:
+case Triple::ARMSubArch_v6k:
+case Triple::ARMSubArch_v6t2:
+case Triple::ARMSubArch_v5:
+case Triple::ARMSubArch_v5te:
+case Triple::ARMSubArch_v4t:
   return false;
-
-if (getArch() == Triple::aarch64)
+default:
   return true;
+}
+  }
 
-if (isThumb())
+  /// Tests whether the target is an M-class.
+  bool isArmMClass() const {
+switch (auto SubArch = getSubArch()) {
+case Triple::ARMSubArch_v6m:
+case Triple::ARMSubArch_v7m:
+case Triple::ARMSubArch_v7em:
+case Triple::ARMSubArch_v8m_mainline:
+case Triple::ARMSubArch_v8m_baseline:
+case Triple::ARMSubArch_v8_1m_mainline:
   return true;
-
-return (getSubArch() ==

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

2022-01-11 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra updated this revision to Diff 398901.
amilendra added a comment.
Herald added subscribers: llvm-commits, dexonsmith.
Herald added a project: LLVM.

Refactor the check conditions to a single function (isArmT32)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115501/new/

https://reviews.llvm.org/D115501

Files:
  clang/include/clang/Basic/DiagnosticCommonKinds.td
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/arm-branch-protection-attr-2.c
  clang/test/CodeGen/arm_acle.c
  clang/test/Driver/arm-security-options.c
  clang/test/Frontend/arm-branch-protection-default-arch.c
  clang/test/Frontend/arm-ignore-branch-protection-option.c
  clang/test/Frontend/arm-invalid-branch-protection.c
  clang/test/Sema/arm-branch-protection-attr-warn.c
  clang/test/Sema/arm-branch-protection.c
  llvm/include/llvm/ADT/Triple.h

Index: llvm/include/llvm/ADT/Triple.h
===
--- llvm/include/llvm/ADT/Triple.h
+++ llvm/include/llvm/ADT/Triple.h
@@ -721,6 +721,22 @@
isOSBinFormatELF();
   }
 
+  /// Tests whether the target is T32.
+  bool isArmT32() const {
+if (!isARM())
+  return false;
+
+if (getArch() == Triple::aarch64)
+  return true;
+
+if (isThumb())
+  return true;
+
+return (getSubArch() == Triple::ARMSubArch_v8_1m_mainline) ||
+   (getSubArch() == Triple::ARMSubArch_v8m_mainline) ||
+   (getSubArch() == Triple::ARMSubArch_v7m) ||
+   (getSubArch() == Triple::ARMSubArch_v7em);
+  }
   /// Tests whether the target is AArch64 (little and big endian).
   bool isAArch64() const {
 return getArch() == Triple::aarch64 || getArch() == Triple::aarch64_be ||
Index: clang/test/Sema/arm-branch-protection.c
===
--- /dev/null
+++ clang/test/Sema/arm-branch-protection.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple thumbv6m -verify -fsyntax-only %s
+
+// expected-no-diagnostics
+// Armv8.1-M.Main
+__attribute__((target("arch=cortex-m55,branch-protection=bti"))) void f1() {}
+__attribute__((target("arch=cortex-m55,branch-protection=pac-ret"))) void f2() {}
+__attribute__((target("arch=cortex-m55,branch-protection=bti+pac-ret"))) void f3() {}
+__attribute__((target("arch=cortex-m55,branch-protection=bti+pac-ret+leaf"))) void f4() {}
+// Armv8-M.Main
+__attribute__((target("arch=cortex-m33,branch-protection=bti"))) void f5() {}
+__attribute__((target("arch=cortex-m33,branch-protection=pac-ret"))) void f6() {}
+__attribute__((target("arch=cortex-m33,branch-protection=bti+pac-ret"))) void f7() {}
+__attribute__((target("arch=cortex-m33,branch-protection=bti+pac-ret+leaf"))) void f8() {}
+// Armv7-M
+__attribute__((target("arch=cortex-m3,branch-protection=bti"))) void f9() {}
+__attribute__((target("arch=cortex-m3,branch-protection=pac-ret"))) void f10() {}
+__attribute__((target("arch=cortex-m3,branch-protection=bti+pac-ret"))) void f11() {}
+__attribute__((target("arch=cortex-m3,branch-protection=bti+pac-ret+leaf"))) void f12() {}
+// Armv7E-M
+__attribute__((target("arch=cortex-m4,branch-protection=bti"))) void f13() {}
+__attribute__((target("arch=cortex-m4,branch-protection=pac-ret"))) void f14() {}
+__attribute__((target("arch=cortex-m4,branch-protection=bti+pac-ret"))) void f15() {}
+__attribute__((target("arch=cortex-m4,branch-protection=bti+pac-ret+leaf"))) void f16() {}
Index: clang/test/Sema/arm-branch-protection-attr-warn.c
===
--- /dev/null
+++ clang/test/Sema/arm-branch-protection-attr-warn.c
@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 -triple thumbv6m -verify -fsyntax-only %s
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=bti"))) void f1() {}
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=pac-ret"))) void f2() {}
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=bti+pac-ret"))) void f3() {}
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=bti+pac-ret+leaf"))) void f4() {}
Index: clang/test/Frontend/arm-invalid-branch-protection.c
===
---

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

2021-12-30 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra updated this revision to Diff 396695.
amilendra added a comment.

Fix clang-format errors.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115501/new/

https://reviews.llvm.org/D115501

Files:
  clang/include/clang/Basic/DiagnosticCommonKinds.td
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/arm-branch-protection-attr-2.c
  clang/test/CodeGen/arm_acle.c
  clang/test/Driver/arm-security-options.c
  clang/test/Frontend/arm-branch-protection-default-arch.c
  clang/test/Frontend/arm-ignore-branch-protection-option.c
  clang/test/Frontend/arm-invalid-branch-protection.c
  clang/test/Sema/arm-branch-protection-attr-warn.c
  clang/test/Sema/arm-branch-protection.c

Index: clang/test/Sema/arm-branch-protection.c
===
--- /dev/null
+++ clang/test/Sema/arm-branch-protection.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple thumbv6m -verify -fsyntax-only %s
+
+// expected-no-diagnostics
+// Armv8.1-M.Main
+__attribute__((target("arch=cortex-m55,branch-protection=bti"))) void f1() {}
+__attribute__((target("arch=cortex-m55,branch-protection=pac-ret"))) void f2() {}
+__attribute__((target("arch=cortex-m55,branch-protection=bti+pac-ret"))) void f3() {}
+__attribute__((target("arch=cortex-m55,branch-protection=bti+pac-ret+leaf"))) void f4() {}
+// Armv8-M.Main
+__attribute__((target("arch=cortex-m33,branch-protection=bti"))) void f5() {}
+__attribute__((target("arch=cortex-m33,branch-protection=pac-ret"))) void f6() {}
+__attribute__((target("arch=cortex-m33,branch-protection=bti+pac-ret"))) void f7() {}
+__attribute__((target("arch=cortex-m33,branch-protection=bti+pac-ret+leaf"))) void f8() {}
+// Armv7-M
+__attribute__((target("arch=cortex-m3,branch-protection=bti"))) void f9() {}
+__attribute__((target("arch=cortex-m3,branch-protection=pac-ret"))) void f10() {}
+__attribute__((target("arch=cortex-m3,branch-protection=bti+pac-ret"))) void f11() {}
+__attribute__((target("arch=cortex-m3,branch-protection=bti+pac-ret+leaf"))) void f12() {}
+// Armv7E-M
+__attribute__((target("arch=cortex-m4,branch-protection=bti"))) void f13() {}
+__attribute__((target("arch=cortex-m4,branch-protection=pac-ret"))) void f14() {}
+__attribute__((target("arch=cortex-m4,branch-protection=bti+pac-ret"))) void f15() {}
+__attribute__((target("arch=cortex-m4,branch-protection=bti+pac-ret+leaf"))) void f16() {}
Index: clang/test/Sema/arm-branch-protection-attr-warn.c
===
--- /dev/null
+++ clang/test/Sema/arm-branch-protection-attr-warn.c
@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 -triple thumbv6m -verify -fsyntax-only %s
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=bti"))) void f1() {}
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=pac-ret"))) void f2() {}
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=bti+pac-ret"))) void f3() {}
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=bti+pac-ret+leaf"))) void f4() {}
Index: clang/test/Frontend/arm-invalid-branch-protection.c
===
--- clang/test/Frontend/arm-invalid-branch-protection.c
+++ clang/test/Frontend/arm-invalid-branch-protection.c
@@ -1,7 +1,7 @@
 // REQUIRES: arm-registered-target
-// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=pac-ret+b-key -c %s -o /dev/null 2>&1 | FileCheck %s
-// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
-// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=bti+pac-ret+b-key -c %s -o /dev/null 2>&1 | FileCheck %s
-// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=bti+pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=pac-ret+b-key -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=bti+pac-ret+b-key -c %s -o

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

2021-12-30 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra updated this revision to Diff 396671.
amilendra added a comment.

Address review comments.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115501/new/

https://reviews.llvm.org/D115501

Files:
  clang/include/clang/Basic/DiagnosticCommonKinds.td
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/arm-branch-protection-attr-2.c
  clang/test/CodeGen/arm_acle.c
  clang/test/Driver/arm-security-options.c
  clang/test/Frontend/arm-branch-protection-default-arch.c
  clang/test/Frontend/arm-ignore-branch-protection-option.c
  clang/test/Frontend/arm-invalid-branch-protection.c
  clang/test/Sema/arm-branch-protection-attr-warn.c
  clang/test/Sema/arm-branch-protection.c

Index: clang/test/Sema/arm-branch-protection.c
===
--- /dev/null
+++ clang/test/Sema/arm-branch-protection.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple thumbv6m -verify -fsyntax-only %s
+
+// expected-no-diagnostics
+// Armv8.1-M.Main
+__attribute__((target("arch=cortex-m55,branch-protection=bti"))) void f1() {}
+__attribute__((target("arch=cortex-m55,branch-protection=pac-ret"))) void f2() {}
+__attribute__((target("arch=cortex-m55,branch-protection=bti+pac-ret"))) void f3() {}
+__attribute__((target("arch=cortex-m55,branch-protection=bti+pac-ret+leaf"))) void f4() {}
+// Armv8-M.Main
+__attribute__((target("arch=cortex-m33,branch-protection=bti"))) void f5() {}
+__attribute__((target("arch=cortex-m33,branch-protection=pac-ret"))) void f6() {}
+__attribute__((target("arch=cortex-m33,branch-protection=bti+pac-ret"))) void f7() {}
+__attribute__((target("arch=cortex-m33,branch-protection=bti+pac-ret+leaf"))) void f8() {}
+// Armv7-M
+__attribute__((target("arch=cortex-m3,branch-protection=bti"))) void f9() {}
+__attribute__((target("arch=cortex-m3,branch-protection=pac-ret"))) void f10() {}
+__attribute__((target("arch=cortex-m3,branch-protection=bti+pac-ret"))) void f11() {}
+__attribute__((target("arch=cortex-m3,branch-protection=bti+pac-ret+leaf"))) void f12() {}
+// Armv7E-M
+__attribute__((target("arch=cortex-m4,branch-protection=bti"))) void f13() {}
+__attribute__((target("arch=cortex-m4,branch-protection=pac-ret"))) void f14() {}
+__attribute__((target("arch=cortex-m4,branch-protection=bti+pac-ret"))) void f15() {}
+__attribute__((target("arch=cortex-m4,branch-protection=bti+pac-ret+leaf"))) void f16() {}
Index: clang/test/Sema/arm-branch-protection-attr-warn.c
===
--- /dev/null
+++ clang/test/Sema/arm-branch-protection-attr-warn.c
@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 -triple thumbv6m -verify -fsyntax-only %s
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=bti"))) void f1() {}
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=pac-ret"))) void f2() {}
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=bti+pac-ret"))) void f3() {}
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=bti+pac-ret+leaf"))) void f4() {}
Index: clang/test/Frontend/arm-invalid-branch-protection.c
===
--- clang/test/Frontend/arm-invalid-branch-protection.c
+++ clang/test/Frontend/arm-invalid-branch-protection.c
@@ -1,7 +1,7 @@
 // REQUIRES: arm-registered-target
-// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=pac-ret+b-key -c %s -o /dev/null 2>&1 | FileCheck %s
-// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
-// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=bti+pac-ret+b-key -c %s -o /dev/null 2>&1 | FileCheck %s
-// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=bti+pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=pac-ret+b-key -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=bti+pac-ret+b-key -c %s -o

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

2021-12-15 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra added inline comments.



Comment at: clang/lib/Basic/Targets/ARM.cpp:391-392
 
+  if (!Arch.empty() && !isBranchProtectionSupportedArch(Arch))
+return false;
+

chill wrote:
> On empty `Arch` it'd continue down the function, but we'd like to return 
> failure.
I am having trouble getting the test `arm-branch-protection-attr-1.c` to work 
after these changes. `validateBranchProtection()` checks the combination of two 
parameters, the branch protection attribute and architecture.
If the architecture is empty, like below, shouldn't the function to continue 
checking further than simply returning false? 
```
__attribute__((target("branch-protection=bti"))) void btionly() {}
```
Or should I be using something else other than 
`CGM.getTarget().getTargetOpts().CPU` to get the architecture in 
`ARMTargetCodeGenInfo::setTargetAttributes`?



Repository:
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[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

2021-12-13 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra updated this revision to Diff 393918.
amilendra added a comment.

Rebase


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D115501/new/

https://reviews.llvm.org/D115501

Files:
  clang/include/clang/Basic/DiagnosticCommonKinds.td
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/arm-branch-protection-attr-2.c
  clang/test/CodeGen/arm_acle.c
  clang/test/Driver/arm-security-options.c
  clang/test/Frontend/arm-branch-protection-default-arch.c
  clang/test/Frontend/arm-ignore-branch-protection-option.c
  clang/test/Frontend/arm-invalid-branch-protection.c
  clang/test/Sema/arm-branch-protection-attr-warn.c
  clang/test/Sema/arm-branch-protection.c

Index: clang/test/Sema/arm-branch-protection.c
===
--- /dev/null
+++ clang/test/Sema/arm-branch-protection.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple thumbv6m -verify -fsyntax-only %s
+
+// expected-no-diagnostics
+// Armv8.1-M.Main
+__attribute__((target("arch=cortex-m55,branch-protection=bti"))) void f1() {}
+__attribute__((target("arch=cortex-m55,branch-protection=pac-ret"))) void f2() {}
+__attribute__((target("arch=cortex-m55,branch-protection=bti+pac-ret"))) void f3() {}
+__attribute__((target("arch=cortex-m55,branch-protection=bti+pac-ret+leaf"))) void f4() {}
+// Armv8-M.Main
+__attribute__((target("arch=cortex-m33,branch-protection=bti"))) void f5() {}
+__attribute__((target("arch=cortex-m33,branch-protection=pac-ret"))) void f6() {}
+__attribute__((target("arch=cortex-m33,branch-protection=bti+pac-ret"))) void f7() {}
+__attribute__((target("arch=cortex-m33,branch-protection=bti+pac-ret+leaf"))) void f8() {}
+// Armv7-M
+__attribute__((target("arch=cortex-m3,branch-protection=bti"))) void f9() {}
+__attribute__((target("arch=cortex-m3,branch-protection=pac-ret"))) void f10() {}
+__attribute__((target("arch=cortex-m3,branch-protection=bti+pac-ret"))) void f11() {}
+__attribute__((target("arch=cortex-m3,branch-protection=bti+pac-ret+leaf"))) void f12() {}
+// Armv7E-M
+__attribute__((target("arch=cortex-m4,branch-protection=bti"))) void f13() {}
+__attribute__((target("arch=cortex-m4,branch-protection=pac-ret"))) void f14() {}
+__attribute__((target("arch=cortex-m4,branch-protection=bti+pac-ret"))) void f15() {}
+__attribute__((target("arch=cortex-m4,branch-protection=bti+pac-ret+leaf"))) void f16() {}
Index: clang/test/Sema/arm-branch-protection-attr-warn.c
===
--- /dev/null
+++ clang/test/Sema/arm-branch-protection-attr-warn.c
@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 -triple thumbv6m -verify -fsyntax-only %s
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=bti"))) void f1() {}
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=pac-ret"))) void f2() {}
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=bti+pac-ret"))) void f3() {}
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=bti+pac-ret+leaf"))) void f4() {}
Index: clang/test/Frontend/arm-invalid-branch-protection.c
===
--- clang/test/Frontend/arm-invalid-branch-protection.c
+++ clang/test/Frontend/arm-invalid-branch-protection.c
@@ -1,7 +1,7 @@
 // REQUIRES: arm-registered-target
-// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=pac-ret+b-key -c %s -o /dev/null 2>&1 | FileCheck %s
-// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
-// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=bti+pac-ret+b-key -c %s -o /dev/null 2>&1 | FileCheck %s
-// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=bti+pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=pac-ret+b-key -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=pac-ret+b-key+leaf -c %s -o /dev/null 2>&1 | FileCheck %s
+// RUN: %clang -target arm-arm-none-eabi -march=armv8.1-m.main -mbranch-protection=bti+pac-ret+b-key -c %s -o /dev/null 2>&1 |

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

2021-12-13 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra updated this revision to Diff 393917.
amilendra added a comment.

Address review comment.


Repository:
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Files:
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/CodeGen/TargetInfo.cpp


Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -6403,7 +6403,8 @@
 // If the Branch Protection attribute is missing, validate the target
 // Architecture attribute against Branch Protection command line
 // settings.
-if 
(!CGM.getTarget().isBranchProtectionSupportedArch(Attr.Architecture))
+if (!Attr.Architecture.empty() &&
+
!CGM.getTarget().isBranchProtectionSupportedArch(Attr.Architecture))
   CGM.getDiags().Report(
   D->getLocation(),
   diag::warn_target_unsupported_branch_protection_attribute)
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -369,7 +369,7 @@
 
 bool ARMTargetInfo::isBranchProtectionSupportedArch(StringRef Arch) const {
   if (Arch.empty())
-return true;
+return false;
 
   llvm::ARM::ArchKind ArchKind = llvm::ARM::parseCPUArch(Arch);
   if (ArchKind != llvm::ARM::ArchKind::ARMV8_1MMainline &&
@@ -388,7 +388,7 @@
   if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err))
 return false;
 
-  if (!isBranchProtectionSupportedArch(Arch))
+  if (!Arch.empty() && !isBranchProtectionSupportedArch(Arch))
 return false;
 
   BPI.SignReturnAddr =


Index: clang/lib/CodeGen/TargetInfo.cpp
===
--- clang/lib/CodeGen/TargetInfo.cpp
+++ clang/lib/CodeGen/TargetInfo.cpp
@@ -6403,7 +6403,8 @@
 // If the Branch Protection attribute is missing, validate the target
 // Architecture attribute against Branch Protection command line
 // settings.
-if (!CGM.getTarget().isBranchProtectionSupportedArch(Attr.Architecture))
+if (!Attr.Architecture.empty() &&
+!CGM.getTarget().isBranchProtectionSupportedArch(Attr.Architecture))
   CGM.getDiags().Report(
   D->getLocation(),
   diag::warn_target_unsupported_branch_protection_attribute)
Index: clang/lib/Basic/Targets/ARM.cpp
===
--- clang/lib/Basic/Targets/ARM.cpp
+++ clang/lib/Basic/Targets/ARM.cpp
@@ -369,7 +369,7 @@
 
 bool ARMTargetInfo::isBranchProtectionSupportedArch(StringRef Arch) const {
   if (Arch.empty())
-return true;
+return false;
 
   llvm::ARM::ArchKind ArchKind = llvm::ARM::parseCPUArch(Arch);
   if (ArchKind != llvm::ARM::ArchKind::ARMV8_1MMainline &&
@@ -388,7 +388,7 @@
   if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err))
 return false;
 
-  if (!isBranchProtectionSupportedArch(Arch))
+  if (!Arch.empty() && !isBranchProtectionSupportedArch(Arch))
 return false;
 
   BPI.SignReturnAddr =
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[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

2021-12-10 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra created this revision.
amilendra added reviewers: chill, vhscampos.
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Branch protection in M-class is supported by

- Armv8.1-M.Main
- Armv8-M.Main
- Armv7-M

Attempting to enable this for other architectures, either by
command-line (e.g -mbranch-protection=bti) or by target attribute
in source code (e.g.  __attribute__((target("branch-protection=..."))) )
will generate a warning.

In both cases function attributes related to branch protection will not
be emitted. Regardless of the warning, module level attributes related to
branch protection will be emitted when it is enabled via the command-line.

The following people also contributed to this patch:

- Victor Campos


Repository:
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https://reviews.llvm.org/D115501

Files:
  clang/include/clang/Basic/DiagnosticCommonKinds.td
  clang/include/clang/Basic/TargetInfo.h
  clang/lib/Basic/Targets/AArch64.cpp
  clang/lib/Basic/Targets/AArch64.h
  clang/lib/Basic/Targets/ARM.cpp
  clang/lib/Basic/Targets/ARM.h
  clang/lib/CodeGen/CodeGenModule.cpp
  clang/lib/CodeGen/TargetInfo.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Sema/SemaDeclAttr.cpp
  clang/test/CodeGen/arm-branch-protection-attr-2.c
  clang/test/CodeGen/arm_acle.c
  clang/test/Driver/arm-security-options.c
  clang/test/Frontend/arm-branch-protection-default-arch.c
  clang/test/Frontend/arm-ignore-branch-protection-option.c
  clang/test/Frontend/arm-invalid-branch-protection.c
  clang/test/Sema/arm-branch-protection-attr-warn.c
  clang/test/Sema/arm-branch-protection.c

Index: clang/test/Sema/arm-branch-protection.c
===
--- /dev/null
+++ clang/test/Sema/arm-branch-protection.c
@@ -0,0 +1,23 @@
+// RUN: %clang_cc1 -triple thumbv6m -verify -fsyntax-only %s
+
+// expected-no-diagnostics
+// Armv8.1-M.Main
+__attribute__((target("arch=cortex-m55,branch-protection=bti"))) void f1() {}
+__attribute__((target("arch=cortex-m55,branch-protection=pac-ret"))) void f2() {}
+__attribute__((target("arch=cortex-m55,branch-protection=bti+pac-ret"))) void f3() {}
+__attribute__((target("arch=cortex-m55,branch-protection=bti+pac-ret+leaf"))) void f4() {}
+// Armv8-M.Main
+__attribute__((target("arch=cortex-m33,branch-protection=bti"))) void f5() {}
+__attribute__((target("arch=cortex-m33,branch-protection=pac-ret"))) void f6() {}
+__attribute__((target("arch=cortex-m33,branch-protection=bti+pac-ret"))) void f7() {}
+__attribute__((target("arch=cortex-m33,branch-protection=bti+pac-ret+leaf"))) void f8() {}
+// Armv7-M
+__attribute__((target("arch=cortex-m3,branch-protection=bti"))) void f9() {}
+__attribute__((target("arch=cortex-m3,branch-protection=pac-ret"))) void f10() {}
+__attribute__((target("arch=cortex-m3,branch-protection=bti+pac-ret"))) void f11() {}
+__attribute__((target("arch=cortex-m3,branch-protection=bti+pac-ret+leaf"))) void f12() {}
+// Armv7E-M
+__attribute__((target("arch=cortex-m4,branch-protection=bti"))) void f13() {}
+__attribute__((target("arch=cortex-m4,branch-protection=pac-ret"))) void f14() {}
+__attribute__((target("arch=cortex-m4,branch-protection=bti+pac-ret"))) void f15() {}
+__attribute__((target("arch=cortex-m4,branch-protection=bti+pac-ret+leaf"))) void f16() {}
Index: clang/test/Sema/arm-branch-protection-attr-warn.c
===
--- /dev/null
+++ clang/test/Sema/arm-branch-protection-attr-warn.c
@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 -triple thumbv6m -verify -fsyntax-only %s
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=bti"))) void f1() {}
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=pac-ret"))) void f2() {}
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=bti+pac-ret"))) void f3() {}
+
+// expected-warning@+1 {{unsupported 'branch-protection' in the 'target' attribute string; 'target' attribute ignored}}
+__attribute__((target("arch=cortex-m0,branch-protection=bti+pac-ret+leaf"))) void f4() {}
Index: clang/test/Frontend/arm-invalid-branch-protection.c
===
--- clang/test/Frontend/arm-invalid-branch-protection.c
+++ clang/test/Frontend/arm-invalid-branch-protection.c
@@ -1,7 +1,7 @@
 // REQUIRES: arm-registered-target
-// RUN: %clang -target arm-arm-none-eabi -mbranch-protection=pac-ret+b-key -c %s -o /dev/null 2>&1 | FileCheck %s
-// RUN: %clang -target arm-arm-none-eabi

[PATCH] D98277: [release][docs] List all cores Arm has added support for in LLVM 12.

2021-03-12 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra closed this revision.
amilendra added a comment.

Commited the fix to LLVM Release 12.x branch. Rendering looks okay this time.


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[PATCH] D98277: [release][docs] List all cores Arm has added support for in LLVM 12.

2021-03-12 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra requested review of this revision.
amilendra added a comment.

Sorry for the back-and-forth. Requesting re-review.


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[PATCH] D98277: [release][docs] List all cores Arm has added support for in LLVM 12.

2021-03-12 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra updated this revision to Diff 330345.
amilendra added a comment.

Add a newline before the sub-list to fix a rendering issue.


Repository:
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Files:
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Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -132,6 +132,7 @@
   (`D92054 `_)
 - Support has been added for the following processors (command-line identifiers
   in parentheses):
+
   - Arm Cortex-A78C (cortex-a78c).
   - Arm Cortex-R82 (cortex-r82).
   - Arm Neoverse V1 (neoverse-v1).


Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -132,6 +132,7 @@
   (`D92054 `_)
 - Support has been added for the following processors (command-line identifiers
   in parentheses):
+
   - Arm Cortex-A78C (cortex-a78c).
   - Arm Cortex-R82 (cortex-r82).
   - Arm Neoverse V1 (neoverse-v1).
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[PATCH] D98277: [release][docs] List all cores Arm has added support for in LLVM 12.

2021-03-12 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra reopened this revision.
amilendra added a comment.
This revision is now accepted and ready to land.

Reopening to add a missing empty line before starting the level-2 list.


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[PATCH] D98277: [release][docs] List all cores Arm has added support for in LLVM 12.

2021-03-12 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra closed this revision.
amilendra added a comment.

Commited to LLVM Release 12.x branch


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[PATCH] D98277: [release][docs] List all cores Arm has added support for in LLVM 12.

2021-03-09 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra created this revision.
amilendra added reviewers: willlovett, kristof.beyls, jgreenhalgh.
amilendra requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Repository:
  rG LLVM Github Monorepo

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Files:
  clang/docs/ReleaseNotes.rst


Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -130,6 +130,15 @@
   This behavior matches newer GCC.
   (`D91760 `_)
   (`D92054 `_)
+- Support has been added for the following processors (command-line identifiers
+  in parentheses):
+  - Arm Cortex-A78C (cortex-a78c).
+  - Arm Cortex-R82 (cortex-r82).
+  - Arm Neoverse V1 (neoverse-v1).
+  - Arm Neoverse N2 (neoverse-n2).
+  - Fujitsu A64FX (a64fx).
+  For example, to select architecture support and tuning for Neoverse-V1 based
+  systems, use ``-mcpu=neoverse-v1``.
 
 Removed Compiler Flags
 -


Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -130,6 +130,15 @@
   This behavior matches newer GCC.
   (`D91760 `_)
   (`D92054 `_)
+- Support has been added for the following processors (command-line identifiers
+  in parentheses):
+  - Arm Cortex-A78C (cortex-a78c).
+  - Arm Cortex-R82 (cortex-r82).
+  - Arm Neoverse V1 (neoverse-v1).
+  - Arm Neoverse N2 (neoverse-n2).
+  - Fujitsu A64FX (a64fx).
+  For example, to select architecture support and tuning for Neoverse-V1 based
+  systems, use ``-mcpu=neoverse-v1``.
 
 Removed Compiler Flags
 -
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[PATCH] D98255: [release][docs] List all cores Arm has added support for in LLVM 12.

2021-03-09 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra abandoned this revision.
amilendra added a comment.
Herald added a subscriber: JDevlieghere.

Abandoning this revision because I think I messed up something when using 
arcanist to fix pre-merge errors. 
https://buildkite.com/llvm-project/diff-checks/builds/32719
I'll submit a new review.


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[PATCH] D98255: [release][docs] List all cores Arm has added support for in LLVM 12.

2021-03-09 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra updated this revision to Diff 329380.
amilendra added a comment.
Herald added subscribers: llvm-commits, libcxx-commits, openmp-commits, 
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- Fix test failures after a92ceea91116e7b95d23eff634507fa2cff86ef2 

- [libc++] Fix extern template test failing on Windows
- [libc++] Fix extern-templates.sh.cpp test on Linux
- [release][docs] List all cores Arm has added support for in LLVM 12.


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  .github/workflows/libclang-abi-tests.yml
  .github/workflows/libclc-tests.yml
  .github/workflows/lld-tests.yml
  .github/workflows/lldb-tests.yml
  .github/workflows/llvm-tests.yml
  .github/workflows/main-branch-sync.yml
  clang-tools-extra/clang-tidy/cppcoreguidelines/CMakeLists.txt
  clang-tools-extra/clang-tidy/cppcoreguidelines/CppCoreGuidelinesTidyModule.cpp
  
clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.cpp
  clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.h
  clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
  clang-tools-extra/clangd/ClangdLSPServer.cpp
  clang-tools-extra/clangd/Config.h
  clang-tools-extra/clangd/ConfigCompile.cpp
  clang-tools-extra/clangd/ConfigFragment.h
  clang-tools-extra/clangd/ConfigYAML.cpp
  clang-tools-extra/clangd/GlobalCompilationDatabase.cpp
  clang-tools-extra/clangd/ParsedAST.cpp
  clang-tools-extra/clangd/Protocol.cpp
  clang-tools-extra/clangd/TidyProvider.cpp
  clang-tools-extra/clangd/refactor/Rename.cpp
  clang-tools-extra/clangd/support/CMakeLists.txt
  clang-tools-extra/clangd/support/Function.h
  clang-tools-extra/clangd/support/Path.cpp
  clang-tools-extra/clangd/support/Path.h
  clang-tools-extra/clangd/unittests/CMakeLists.txt
  clang-tools-extra/clangd/unittests/ConfigCompileTests.cpp
  clang-tools-extra/clangd/unittests/ConfigYAMLTests.cpp
  clang-tools-extra/clangd/unittests/RenameTests.cpp
  clang-tools-extra/clangd/unittests/TidyProviderTests.cpp
  clang-tools-extra/clangd/unittests/support/PathTests.cpp
  clang-tools-extra/docs/ReleaseNotes.rst
  
clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines-prefer-member-initializer.rst
  
clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-prefer-member-initializer-modernize-use-default-member-init-assignment.cpp
  
clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-prefer-member-initializer-modernize-use-default-member-init.cpp
  
clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines-prefer-member-initializer.cpp
  clang-tools-extra/unittests/clang-tidy/CMakeLists.txt
  clang/docs/ReleaseNotes.rst
  clang/include/clang/AST/ASTContext.h
  clang/include/clang/AST/DeclCXX.h
  clang/include/clang/AST/Mangle.h
  clang/include/clang/AST/MangleNumberingContext.h
  clang/include/clang/AST/RecursiveASTVisitor.h
  clang/include/clang/ASTMatchers/ASTMatchers.h
  clang/include/clang/Basic/CodeGenOptions.def
  clang/include/clang/Basic/CodeGenOptions.h
  clang/include/clang/Driver/Options.td
  clang/include/clang/Lex/VariadicMacroSupport.h
  clang/include/clang/Sema/Sema.h
  clang/lib/AST/ASTImporter.cpp
  clang/lib/AST/CXXABI.h
  clang/lib/AST/DeclCXX.cpp
  clang/lib/AST/ExprConstant.cpp
  clang/lib/AST/ItaniumCXXABI.cpp
  clang/lib/AST/ItaniumMangle.cpp
  clang/lib/AST/MicrosoftCXXABI.cpp
  clang/lib/ASTMatchers/ASTMatchFinder.cpp
  clang/lib/ASTMatchers/ASTMatchersInternal.cpp
  clang/lib/Basic/ProfileList.cpp
  clang/lib/Basic/Targets/PPC.cpp
  clang/lib/Basic/Targets/RISCV.cpp
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/lib/CodeGen/CGCUDANV.cpp
  clang/lib/CodeGen/CGCall.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/lib/Driver/ToolChains/Arch/RISCV.cpp
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/lib/Driver/ToolChains/CommonArgs.cpp
  clang/lib/Driver/ToolChains/Linux.cpp

[PATCH] D98255: [release][docs] List all cores Arm has added support for in LLVM 12.

2021-03-09 Thread Amilendra Kodithuwakku via Phabricator via cfe-commits

amilendra created this revision.
amilendra added reviewers: willlovett, kristof.beyls, jgreenhalgh.
amilendra added a project: clang.
amilendra requested review of this revision.
Herald added a subscriber: cfe-commits.

Repository:
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Files:
  clang/docs/ReleaseNotes.rst


Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -130,6 +130,15 @@
   This behavior matches newer GCC.
   (`D91760 `_)
   (`D92054 `_)
+- Support has been added for the following processors (command-line identifiers
+  in parentheses):
+  - Arm Cortex-A78C (cortex-a78c).
+  - Arm Cortex-R82 (cortex-r82).
+  - Arm Neoverse V1 (neoverse-v1).
+  - Arm Neoverse N2 (neoverse-n2).
+  - Fujitsu A64FX (a64fx).
+  For example, to select architecture support and tuning for Neoverse-V1 based
+  systems, use ``-mcpu=neoverse-v1``.
 
 Removed Compiler Flags
 -


Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -130,6 +130,15 @@
   This behavior matches newer GCC.
   (`D91760 `_)
   (`D92054 `_)
+- Support has been added for the following processors (command-line identifiers
+  in parentheses):
+  - Arm Cortex-A78C (cortex-a78c).
+  - Arm Cortex-R82 (cortex-r82).
+  - Arm Neoverse V1 (neoverse-v1).
+  - Arm Neoverse N2 (neoverse-n2).
+  - Fujitsu A64FX (a64fx).
+  For example, to select architecture support and tuning for Neoverse-V1 based
+  systems, use ``-mcpu=neoverse-v1``.
 
 Removed Compiler Flags
 -
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[PATCH] D143587: [Docs] Multilib design

[PATCH] D143587: [Docs] Multilib design

[PATCH] D143590: [NFC] Simplify test from change D73904

[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77

[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77

[PATCH] D121206: [AARCH64] ssbs should be enabled by default for cortex-x1, cortex-x1c, cortex-a77

[PATCH] D119166: [clang][ARM] Re-word PACBTI warning.

[PATCH] D119166: [clang][ARM] Re-word PACBTI warning.

[PATCH] D119166: [clang][ARM] Re-word PACBTI warning.

[PATCH] D119008: Add Cortex-X1C to Clang LLVM 14 release notes

[PATCH] D118380: Add info on PACBTI-M to the Clang release notes

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

[PATCH] D115501: [clang][ARM] Emit warnings when PACBTI-M is used with unsupported architectures

[PATCH] D98277: [release][docs] List all cores Arm has added support for in LLVM 12.

[PATCH] D98277: [release][docs] List all cores Arm has added support for in LLVM 12.

[PATCH] D98277: [release][docs] List all cores Arm has added support for in LLVM 12.

[PATCH] D98277: [release][docs] List all cores Arm has added support for in LLVM 12.

[PATCH] D98277: [release][docs] List all cores Arm has added support for in LLVM 12.

[PATCH] D98277: [release][docs] List all cores Arm has added support for in LLVM 12.

[PATCH] D98255: [release][docs] List all cores Arm has added support for in LLVM 12.

[PATCH] D98255: [release][docs] List all cores Arm has added support for in LLVM 12.

[PATCH] D98255: [release][docs] List all cores Arm has added support for in LLVM 12.

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