[PATCH] D152206: [Basic] Support 64-bit x86 target for UEFI

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

@Prabhuk This reproduces with my setup as well. Did you try building with 
`-DBUILD_SHARED_LIBS=ON`?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152206/new/

https://reviews.llvm.org/D152206

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D125604: [FileCheck] Catch missspelled directives.

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Committing this revealed some more failures, fixed in 
rG8894c05b0d351f998b1836542ba791247394bd12 
.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125604/new/

https://reviews.llvm.org/D125604

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D125604: [FileCheck] Catch missspelled directives.

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGad1d60c3befd: [FileCheck] Catch missspelled directives. 
(authored by kosarev).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125604/new/

https://reviews.llvm.org/D125604

Files:
  clang/test/CodeGenCXX/attr-mustprogress.cpp
  clang/test/CodeGenCXX/eh-aggregate-copy-destroy.cpp
  clang/test/CodeGenCXX/inheriting-constructor.cpp
  clang/test/CodeGenObjC/non-runtime-protocol.m
  clang/test/OpenMP/master_taskloop_private_codegen.cpp
  clang/test/OpenMP/master_taskloop_simd_private_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_private_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_private_codegen.cpp
  clang/test/OpenMP/task_private_codegen.cpp
  clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp
  clang/test/OpenMP/taskloop_private_codegen.cpp
  clang/test/OpenMP/taskloop_simd_private_codegen.cpp
  flang/test/Fir/convert-to-llvm.fir
  flang/test/Lower/Intrinsics/not.f90
  llvm/include/llvm/FileCheck/FileCheck.h
  llvm/lib/FileCheck/FileCheck.cpp
  llvm/test/Analysis/MemorySSA/phi-translation.ll
  llvm/test/Analysis/RegionInfo/infinite_loop_4.ll
  llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll
  llvm/test/CodeGen/AMDGPU/hoist-cond.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
  llvm/test/CodeGen/AMDGPU/mode-register.mir
  llvm/test/CodeGen/AMDGPU/smrd.ll
  llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll
  llvm/test/CodeGen/AVR/atomics/fence.ll
  llvm/test/CodeGen/BPF/CORE/offset-reloc-middle-chain.ll
  llvm/test/CodeGen/WebAssembly/libcalls.ll
  llvm/test/DebugInfo/NVPTX/debug-info.ll
  llvm/test/FileCheck/missspelled-directive.txt
  llvm/test/MC/AMDGPU/data.s
  llvm/test/MC/AsmParser/directive_file-g.s
  llvm/test/MC/PowerPC/ppc64-reloc-directive-pcrel.s
  llvm/test/MC/WebAssembly/unnamed-data.ll
  llvm/test/Transforms/Inline/inline-strictfp.ll
  llvm/test/Transforms/LoopVectorize/X86/gather-vs-interleave.ll
  llvm/test/Transforms/MergeFunc/alias.ll
  llvm/test/Transforms/PGOProfile/PR41279.ll
  llvm/test/Transforms/PGOProfile/memop_clone.ll
  llvm/test/Transforms/PGOProfile/memop_size_from_strlen.ll
  llvm/test/tools/llvm-dwp/X86/tu_units_v5.s
  llvm/test/tools/llvm-dwp/X86/type_dedup_v5.test
  llvm/test/tools/llvm-objdump/MachO/disassemble-all.test
  llvm/test/tools/llvm-readobj/COFF/unwind-arm64-windows.test
  mlir/test/Dialect/Affine/loop-coalescing.mlir
  mlir/test/Dialect/Linalg/fuse-with-reshape-by-collapsing.mlir
  mlir/test/Dialect/Linalg/tile-and-fuse-no-fuse.mlir
  mlir/test/Dialect/MemRef/canonicalize.mlir
  mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
  mlir/test/Dialect/Vector/vector-transfer-full-partial-split.mlir
  mlir/test/IR/dynamic.mlir
  mlir/test/mlir-tblgen/op-decl-and-defs.td
  polly/test/ScopDetect/dot-scops-npm.ll

Index: polly/test/ScopDetect/dot-scops-npm.ll
===
--- polly/test/ScopDetect/dot-scops-npm.ll
+++ polly/test/ScopDetect/dot-scops-npm.ll
@@ -30,35 +30,35 @@
 ; CHECK-NEXT: Node0x[[OUTER_EXIT]] -> Node0x[[RETURN_ID:.*]];
 ; CHECK-NEXT: Node0x[[RETURN_ID]] [shape=record,label="{return:
 ; CHECK-NEXT: colorscheme = "paired12"
-; CHECK_NEXT: subgraph cluster_0x[[:.*]] {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = solid;
-; CHECK_NEXT: color = 1
-; CHECK_NEXT: subgraph cluster_0x[[:.*]] {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = filled;
-; CHECK_NEXT: color = 3subgraph cluster_0x7152c40 {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = solid;
-; CHECK_NEXT: color = 5
-; CHECK_NEXT: subgraph cluster_0x[[:.*]] {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = solid;
-; CHECK_NEXT: color = 7
-; CHECK_NEXT: Node0x[[INNER_FOR_ID]];
-; CHECK_NEXT: Node0x[[BABY1_ID]];
-; CHECK_NEXT: Node0x[[INNER_INC_ID]];
-; CHECK_NEXT: }
-; CHECK_NEXT: Node0x[[OUTER_FOR_ID]];
-; CHECK_NEXT: Node0x[[INNER_EXIT_ID]];
-; CHECK_NEXT: Node0x[[OUTER_INC_ID]];
-; CHECK_NEXT: }
-; CHECK_NEXT: Node0x[[OUTER_EXIT]];
-; CHECK_NEXT: }
-; CHECK_NEXT: Node0x[[EntryID]];
-; CHECK_NEXT: Node0x[[RETURN_ID]];
-; CHECK_NEXT: }
-; CHECK_NEXT: }
+; CHECK-NEXT: subgraph cluster_0x{{.*}} {
+; CHECK-NEXT: label = "";
+; CHECK-NEXT: style = solid;
+; CHECK-NEXT: color = 1
+; CHECK-NEXT: subgraph cluster_0x{{.*}} {
+; CHECK-NEXT: label = "";
+; CHECK-NEXT: style = filled;
+; CHECK-NEXT: color = 3subgraph cluster_0x{{.*}} {
+; CHECK-NEXT: label = "";
+; CHECK-NEXT: style = solid;
+; CHECK-NEXT: color = 5
+; CHECK-NEXT: subgraph cluster_0x{{.*}} {
+; CHECK-NEXT: label = "";
+; CHECK-NEXT: style = solid;
+; CHECK-NEXT: color = 7
+; CHECK-NEXT: Node0x[[INNER_FOR_ID]];
+; CHECK-NEXT: Node0x[[BABY1_ID]];
+; CHECK-NEXT: Node0x[[INNER_INC_ID]];
+; CHECK-NEXT: }
+; CHECK-NEXT: Node0x[[OUTER_FOR_ID]];
+; CHECK-NEXT: Node0x[[INNER_EXIT_ID]];
+; CHECK-NEXT: Node0x[[OUTER_INC_ID]];
+; CHECK-NEXT: }
+; 

[PATCH] D125604: [FileCheck] Catch missspelled directives.

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 431979.
kosarev added a comment.

Rebased on top of fixes for non-trivial cases. Going to submit this
tomorrow, if no objections.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125604/new/

https://reviews.llvm.org/D125604

Files:
  clang/test/CodeGenCXX/attr-mustprogress.cpp
  clang/test/CodeGenCXX/eh-aggregate-copy-destroy.cpp
  clang/test/CodeGenCXX/inheriting-constructor.cpp
  clang/test/CodeGenObjC/non-runtime-protocol.m
  clang/test/OpenMP/master_taskloop_private_codegen.cpp
  clang/test/OpenMP/master_taskloop_simd_private_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_private_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_private_codegen.cpp
  clang/test/OpenMP/task_private_codegen.cpp
  clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp
  clang/test/OpenMP/taskloop_private_codegen.cpp
  clang/test/OpenMP/taskloop_simd_private_codegen.cpp
  flang/test/Fir/convert-to-llvm.fir
  flang/test/Lower/Intrinsics/not.f90
  llvm/include/llvm/FileCheck/FileCheck.h
  llvm/lib/FileCheck/FileCheck.cpp
  llvm/test/Analysis/MemorySSA/phi-translation.ll
  llvm/test/Analysis/RegionInfo/infinite_loop_4.ll
  llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll
  llvm/test/CodeGen/AMDGPU/hoist-cond.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
  llvm/test/CodeGen/AMDGPU/mode-register.mir
  llvm/test/CodeGen/AMDGPU/smrd.ll
  llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll
  llvm/test/CodeGen/AVR/atomics/fence.ll
  llvm/test/CodeGen/BPF/CORE/offset-reloc-middle-chain.ll
  llvm/test/CodeGen/WebAssembly/libcalls.ll
  llvm/test/DebugInfo/NVPTX/debug-info.ll
  llvm/test/FileCheck/missspelled-directive.txt
  llvm/test/MC/AMDGPU/data.s
  llvm/test/MC/AsmParser/directive_file-g.s
  llvm/test/MC/PowerPC/ppc64-reloc-directive-pcrel.s
  llvm/test/MC/WebAssembly/unnamed-data.ll
  llvm/test/Transforms/Inline/inline-strictfp.ll
  llvm/test/Transforms/LoopVectorize/X86/gather-vs-interleave.ll
  llvm/test/Transforms/MergeFunc/alias.ll
  llvm/test/Transforms/PGOProfile/PR41279.ll
  llvm/test/Transforms/PGOProfile/memop_clone.ll
  llvm/test/Transforms/PGOProfile/memop_size_from_strlen.ll
  llvm/test/tools/llvm-dwp/X86/tu_units_v5.s
  llvm/test/tools/llvm-dwp/X86/type_dedup_v5.test
  llvm/test/tools/llvm-objdump/MachO/disassemble-all.test
  llvm/test/tools/llvm-readobj/COFF/unwind-arm64-windows.test
  mlir/test/Dialect/Affine/loop-coalescing.mlir
  mlir/test/Dialect/Linalg/fuse-with-reshape-by-collapsing.mlir
  mlir/test/Dialect/Linalg/tile-and-fuse-no-fuse.mlir
  mlir/test/Dialect/MemRef/canonicalize.mlir
  mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
  mlir/test/Dialect/Vector/vector-transfer-full-partial-split.mlir
  mlir/test/IR/dynamic.mlir
  mlir/test/mlir-tblgen/op-decl-and-defs.td
  polly/test/ScopDetect/dot-scops-npm.ll

Index: polly/test/ScopDetect/dot-scops-npm.ll
===
--- polly/test/ScopDetect/dot-scops-npm.ll
+++ polly/test/ScopDetect/dot-scops-npm.ll
@@ -30,35 +30,35 @@
 ; CHECK-NEXT: Node0x[[OUTER_EXIT]] -> Node0x[[RETURN_ID:.*]];
 ; CHECK-NEXT: Node0x[[RETURN_ID]] [shape=record,label="{return:
 ; CHECK-NEXT: colorscheme = "paired12"
-; CHECK_NEXT: subgraph cluster_0x[[:.*]] {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = solid;
-; CHECK_NEXT: color = 1
-; CHECK_NEXT: subgraph cluster_0x[[:.*]] {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = filled;
-; CHECK_NEXT: color = 3subgraph cluster_0x7152c40 {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = solid;
-; CHECK_NEXT: color = 5
-; CHECK_NEXT: subgraph cluster_0x[[:.*]] {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = solid;
-; CHECK_NEXT: color = 7
-; CHECK_NEXT: Node0x[[INNER_FOR_ID]];
-; CHECK_NEXT: Node0x[[BABY1_ID]];
-; CHECK_NEXT: Node0x[[INNER_INC_ID]];
-; CHECK_NEXT: }
-; CHECK_NEXT: Node0x[[OUTER_FOR_ID]];
-; CHECK_NEXT: Node0x[[INNER_EXIT_ID]];
-; CHECK_NEXT: Node0x[[OUTER_INC_ID]];
-; CHECK_NEXT: }
-; CHECK_NEXT: Node0x[[OUTER_EXIT]];
-; CHECK_NEXT: }
-; CHECK_NEXT: Node0x[[EntryID]];
-; CHECK_NEXT: Node0x[[RETURN_ID]];
-; CHECK_NEXT: }
-; CHECK_NEXT: }
+; CHECK-NEXT: subgraph cluster_0x{{.*}} {
+; CHECK-NEXT: label = "";
+; CHECK-NEXT: style = solid;
+; CHECK-NEXT: color = 1
+; CHECK-NEXT: subgraph cluster_0x{{.*}} {
+; CHECK-NEXT: label = "";
+; CHECK-NEXT: style = filled;
+; CHECK-NEXT: color = 3subgraph cluster_0x{{.*}} {
+; CHECK-NEXT: label = "";
+; CHECK-NEXT: style = solid;
+; CHECK-NEXT: color = 5
+; CHECK-NEXT: subgraph cluster_0x{{.*}} {
+; CHECK-NEXT: label = "";
+; CHECK-NEXT: style = solid;
+; CHECK-NEXT: color = 7
+; CHECK-NEXT: Node0x[[INNER_FOR_ID]];
+; CHECK-NEXT: Node0x[[BABY1_ID]];
+; CHECK-NEXT: Node0x[[INNER_INC_ID]];
+; CHECK-NEXT: }
+; CHECK-NEXT: Node0x[[OUTER_FOR_ID]];
+; CHECK-NEXT: Node0x[[INNER_EXIT_ID]];
+; CHECK-NEXT: Node0x[[OUTER_INC_ID]];
+; CHECK-NEXT: }
+; CHECK-NEXT: Node0x[[OUTER_EXIT]];
+; CHECK-NEXT: }
+; 

[PATCH] D126191: [Clang][CodeGen] Fix the cmse-clear-return.c test.

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGbe4eaf10eef7: [Clang][CodeGen] Fix the cmse-clear-return.c 
test. (authored by kosarev).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D126191/new/

https://reviews.llvm.org/D126191

Files:
  clang/test/CodeGen/cmse-clear-return.c


Index: clang/test/CodeGen/cmse-clear-return.c
===
--- clang/test/CodeGen/cmse-clear-return.c
+++ clang/test/CodeGen/cmse-clear-return.c
@@ -228,11 +228,12 @@
 
 T14 t14;
 __attribute__((cmse_nonsecure_entry)) T14 f14(void) { return t14; }
-// CHECK: define {{.*}} @f14()
-// CHECK: [[R:%.*]] = load
-// CHECK-LE-NOPT-NEXT: [[AND:%.+]] = and i32 [[R]], -1
-// CHECK-BE-NOPT-NEXT: [[AND:%.+]] = and i32 [[R]], -1
-// CHECK_NEXT: ret i32 [[AND]]
+// CHECK: define {{.*}} @f14()
+// CHECK: [[R:%.*]] = load
+// CHECK-LE-OPT:  ret i32 [[R]]
+// CHECK-LE-NOPT: [[AND:%.+]] = and i32 [[R]], -1
+// CHECK-LE-NOPT: ret i32 [[AND]]
+// CHECK-BE-OPT:  ret i32 [[R]]
 
 // LE: ..11 ..11   0xf3f3/-3085
 // BE: 11.. 11..   0xcfcf/-808452097


Index: clang/test/CodeGen/cmse-clear-return.c
===
--- clang/test/CodeGen/cmse-clear-return.c
+++ clang/test/CodeGen/cmse-clear-return.c
@@ -228,11 +228,12 @@
 
 T14 t14;
 __attribute__((cmse_nonsecure_entry)) T14 f14(void) { return t14; }
-// CHECK: define {{.*}} @f14()
-// CHECK: [[R:%.*]] = load
-// CHECK-LE-NOPT-NEXT: [[AND:%.+]] = and i32 [[R]], -1
-// CHECK-BE-NOPT-NEXT: [[AND:%.+]] = and i32 [[R]], -1
-// CHECK_NEXT: ret i32 [[AND]]
+// CHECK: define {{.*}} @f14()
+// CHECK: [[R:%.*]] = load
+// CHECK-LE-OPT:  ret i32 [[R]]
+// CHECK-LE-NOPT: [[AND:%.+]] = and i32 [[R]], -1
+// CHECK-LE-NOPT: ret i32 [[AND]]
+// CHECK-BE-OPT:  ret i32 [[R]]
 
 // LE: ..11 ..11   0xf3f3/-3085
 // BE: 11.. 11..   0xcfcf/-808452097
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D126191: [Clang][CodeGen] Fix the cmse-clear-return.c test.

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
Herald added a project: All.
kosarev requested review of this revision.
Herald added a project: clang.
Herald added a subscriber: cfe-commits.

Caught with D125604 .


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D126191

Files:
  clang/test/CodeGen/cmse-clear-return.c


Index: clang/test/CodeGen/cmse-clear-return.c
===
--- clang/test/CodeGen/cmse-clear-return.c
+++ clang/test/CodeGen/cmse-clear-return.c
@@ -228,11 +228,12 @@
 
 T14 t14;
 __attribute__((cmse_nonsecure_entry)) T14 f14(void) { return t14; }
-// CHECK: define {{.*}} @f14()
-// CHECK: [[R:%.*]] = load
-// CHECK-LE-NOPT-NEXT: [[AND:%.+]] = and i32 [[R]], -1
-// CHECK-BE-NOPT-NEXT: [[AND:%.+]] = and i32 [[R]], -1
-// CHECK_NEXT: ret i32 [[AND]]
+// CHECK: define {{.*}} @f14()
+// CHECK: [[R:%.*]] = load
+// CHECK-LE-OPT:  ret i32 [[R]]
+// CHECK-LE-NOPT: [[AND:%.+]] = and i32 [[R]], -1
+// CHECK-LE-NOPT: ret i32 [[AND]]
+// CHECK-BE-OPT:  ret i32 [[R]]
 
 // LE: ..11 ..11   0xf3f3/-3085
 // BE: 11.. 11..   0xcfcf/-808452097


Index: clang/test/CodeGen/cmse-clear-return.c
===
--- clang/test/CodeGen/cmse-clear-return.c
+++ clang/test/CodeGen/cmse-clear-return.c
@@ -228,11 +228,12 @@
 
 T14 t14;
 __attribute__((cmse_nonsecure_entry)) T14 f14(void) { return t14; }
-// CHECK: define {{.*}} @f14()
-// CHECK: [[R:%.*]] = load
-// CHECK-LE-NOPT-NEXT: [[AND:%.+]] = and i32 [[R]], -1
-// CHECK-BE-NOPT-NEXT: [[AND:%.+]] = and i32 [[R]], -1
-// CHECK_NEXT: ret i32 [[AND]]
+// CHECK: define {{.*}} @f14()
+// CHECK: [[R:%.*]] = load
+// CHECK-LE-OPT:  ret i32 [[R]]
+// CHECK-LE-NOPT: [[AND:%.+]] = and i32 [[R]], -1
+// CHECK-LE-NOPT: ret i32 [[AND]]
+// CHECK-BE-OPT:  ret i32 [[R]]
 
 // LE: ..11 ..11   0xf3f3/-3085
 // BE: 11.. 11..   0xcfcf/-808452097
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D125604: [FileCheck] Catch missspelled directives.

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 430392.
kosarev added a comment.
Herald added a project: Flang.

Added Flang fixes and rebased.

Thanks Simon for the quick turnaround!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125604/new/

https://reviews.llvm.org/D125604

Files:
  clang/test/CodeGen/cmse-clear-return.c
  clang/test/CodeGenCXX/attr-mustprogress.cpp
  clang/test/CodeGenCXX/eh-aggregate-copy-destroy.cpp
  clang/test/CodeGenCXX/inheriting-constructor.cpp
  clang/test/CodeGenObjC/non-runtime-protocol.m
  clang/test/OpenMP/master_taskloop_private_codegen.cpp
  clang/test/OpenMP/master_taskloop_simd_private_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_private_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_private_codegen.cpp
  clang/test/OpenMP/task_private_codegen.cpp
  clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp
  clang/test/OpenMP/taskloop_private_codegen.cpp
  clang/test/OpenMP/taskloop_simd_private_codegen.cpp
  flang/test/Fir/convert-to-llvm.fir
  flang/test/Lower/Intrinsics/not.f90
  llvm/include/llvm/FileCheck/FileCheck.h
  llvm/lib/FileCheck/FileCheck.cpp
  llvm/test/Analysis/MemorySSA/phi-translation.ll
  llvm/test/Analysis/RegionInfo/infinite_loop_4.ll
  llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll
  llvm/test/CodeGen/AMDGPU/hoist-cond.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
  llvm/test/CodeGen/AMDGPU/mode-register.mir
  llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
  llvm/test/CodeGen/AMDGPU/smrd.ll
  llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll
  llvm/test/CodeGen/AVR/atomics/fence.ll
  llvm/test/CodeGen/BPF/CORE/offset-reloc-middle-chain.ll
  llvm/test/CodeGen/MIR/AMDGPU/extra-imm-operand.mir
  llvm/test/CodeGen/MIR/AMDGPU/extra-reg-operand.mir
  llvm/test/CodeGen/WebAssembly/libcalls.ll
  llvm/test/DebugInfo/NVPTX/debug-info.ll
  llvm/test/FileCheck/missspelled-directive.txt
  llvm/test/MC/AMDGPU/data.s
  llvm/test/MC/AsmParser/directive_file-g.s
  llvm/test/MC/PowerPC/ppc64-reloc-directive-pcrel.s
  llvm/test/MC/WebAssembly/unnamed-data.ll
  llvm/test/Transforms/Inline/inline-strictfp.ll
  llvm/test/Transforms/LoopVectorize/X86/gather-vs-interleave.ll
  llvm/test/Transforms/MergeFunc/alias.ll
  llvm/test/Transforms/PGOProfile/PR41279.ll
  llvm/test/Transforms/PGOProfile/memop_clone.ll
  llvm/test/Transforms/PGOProfile/memop_size_from_strlen.ll
  llvm/test/tools/llvm-dwp/X86/tu_units_v5.s
  llvm/test/tools/llvm-dwp/X86/type_dedup_v5.test
  llvm/test/tools/llvm-objdump/MachO/disassemble-all.test
  llvm/test/tools/llvm-readobj/COFF/unwind-arm64-windows.test
  mlir/test/Conversion/MemRefToSPIRV/alloc.mlir
  mlir/test/Dialect/Affine/loop-coalescing.mlir
  mlir/test/Dialect/Linalg/fuse-with-reshape-by-collapsing.mlir
  mlir/test/Dialect/Linalg/tile-and-fuse-no-fuse.mlir
  mlir/test/Dialect/MemRef/canonicalize.mlir
  mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
  mlir/test/Dialect/Vector/vector-transfer-full-partial-split.mlir
  mlir/test/IR/dynamic.mlir
  mlir/test/mlir-tblgen/op-decl-and-defs.td
  polly/test/ScopDetect/dot-scops-npm.ll

Index: polly/test/ScopDetect/dot-scops-npm.ll
===
--- polly/test/ScopDetect/dot-scops-npm.ll
+++ polly/test/ScopDetect/dot-scops-npm.ll
@@ -30,35 +30,35 @@
 ; CHECK-NEXT: Node0x[[OUTER_EXIT]] -> Node0x[[RETURN_ID:.*]];
 ; CHECK-NEXT: Node0x[[RETURN_ID]] [shape=record,label="{return:
 ; CHECK-NEXT: colorscheme = "paired12"
-; CHECK_NEXT: subgraph cluster_0x[[:.*]] {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = solid;
-; CHECK_NEXT: color = 1
-; CHECK_NEXT: subgraph cluster_0x[[:.*]] {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = filled;
-; CHECK_NEXT: color = 3subgraph cluster_0x7152c40 {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = solid;
-; CHECK_NEXT: color = 5
-; CHECK_NEXT: subgraph cluster_0x[[:.*]] {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = solid;
-; CHECK_NEXT: color = 7
-; CHECK_NEXT: Node0x[[INNER_FOR_ID]];
-; CHECK_NEXT: Node0x[[BABY1_ID]];
-; CHECK_NEXT: Node0x[[INNER_INC_ID]];
-; CHECK_NEXT: }
-; CHECK_NEXT: Node0x[[OUTER_FOR_ID]];
-; CHECK_NEXT: Node0x[[INNER_EXIT_ID]];
-; CHECK_NEXT: Node0x[[OUTER_INC_ID]];
-; CHECK_NEXT: }
-; CHECK_NEXT: Node0x[[OUTER_EXIT]];
-; CHECK_NEXT: }
-; CHECK_NEXT: Node0x[[EntryID]];
-; CHECK_NEXT: Node0x[[RETURN_ID]];
-; CHECK_NEXT: }
-; CHECK_NEXT: }
+; CHECK-NEXT: subgraph cluster_0x{{.*}} {
+; CHECK-NEXT: label = "";
+; CHECK-NEXT: style = solid;
+; CHECK-NEXT: color = 1
+; CHECK-NEXT: subgraph cluster_0x{{.*}} {
+; CHECK-NEXT: label = "";
+; CHECK-NEXT: style = filled;
+; CHECK-NEXT: color = 3subgraph cluster_0x{{.*}} {
+; CHECK-NEXT: label = "";
+; CHECK-NEXT: style = solid;
+; CHECK-NEXT: color = 5
+; CHECK-NEXT: subgraph cluster_0x{{.*}} {
+; CHECK-NEXT: label = "";
+; CHECK-NEXT: style = solid;
+; CHECK-NEXT: color = 7
+; CHECK-NEXT: Node0x[[INNER_FOR_ID]];
+; CHECK-NEXT: Node0x[[BABY1_ID]];

[PATCH] D125604: [FileCheck] Catch missspelled directives.

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added subscribers: chill, momchil.velikov, az, alex-t, 
keith.walker.arm, plotfi, aivchenk, zer0, awanpand, levivic, zlei.
kosarev added a comment.

Tagging more people in hope to add visibility.




Comment at: clang/test/CodeGen/cmse-clear-return.c:235
 // CHECK-BE-NOPT-NEXT: [[AND:%.+]] = and i32 [[R]], -1
-// CHECK_NEXT: ret i32 [[AND]]
+// TODO-NEXT: ret i32 [[AND]]
 

@momchil.velikov @chill 



Comment at: llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll:682-688
+; TODO-CVT-DAG:   fcvtl   [[LO:v[0-9]+\.4s]], v0.4h
+; TODO-CVT-DAG:   fcvtl2  [[HI:v[0-9]+\.4s]], v0.8h
+; TODO-CVT-DAG:   fcvtzs  [[LOF32:v[0-9]+\.4s]], [[LO]]
+; TODO-CVT-DAG:   xtn [[I16:v[0-9]+]].4h, [[LOF32]]
+; TODO-CVT-DAG:   fcvtzs  [[HIF32:v[0-9]+\.4s]], [[HI]]
+; TODO-CVT-DAG:   xtn2[[I16]].8h, [[HIF32]]
+; TODO-NEXT:  ret

@az 



Comment at: llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir:3-5
+# GCN-LABEL: phi_moveimm_input
 # GCN-NOT: %{{[0-9]+}}:vgpr_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1
+# TODO: %{{[0-9]+}}:sreg_32 = PHI %{{[0-9]+}}, %bb.3, %{{[0-9]+}}, %bb.1

@alex-t 



Comment at: llvm/test/CodeGen/Thumb2/thumb2-execute-only-prologue.ll:13
 ; CHECK: .LCPI0_0:
-; CHECK_NEXT:long   4294963196
+; TODO-NEXT: long   4294963196
+

@keith.walker.arm 



Comment at: llvm/test/CodeGen/WebAssembly/libcalls.ll:52-53
   ; Basic ops should be expanded
-  ; CHECK_NOT: call
+  ; CHECK: .local
+  ; CHECK-NOT: call
   %a = add i128 %x, %y

@dschuff 



Comment at: llvm/test/CodeGen/X86/GlobalISel/select-ext.mir:69-72
+# ALL-NEXT: %1:gr8 = COPY %0.sub_8bit
+# ALL-NEXT: %2:gr8 = AND8ri %1, 1, implicit-def $eflags
+# ALL-NEXT: $al = COPY %2
+# ALL-NEXT: RET 0, implicit $al

@aivchenk @plotfi @zer0 



Comment at: llvm/test/DebugInfo/X86/debug-info-template-parameter.ll:33-36
+; TODO-NEXT: DW_AT_default_value {{.*}} true
 ; CHECK: DW_AT_type {{.*}} "int"
 ; CHECK-NEXT: DW_AT_name {{.*}} "i"
+; TODO-NEXT: DW_AT_default_value {{.*}} true

@awanpand 



Comment at: mlir/test/Conversion/MemRefToSPIRV/alloc.mlir:44
 //  CHECK-SAME:   !spv.ptr)>, Workgroup>
-// CHECK_LABEL: spv.func @alloc_dealloc_workgroup_mem
+//  TODO-LABEL: spv.func @alloc_dealloc_workgroup_mem
 //   CHECK:   %[[VAR:.+]] = spv.mlir.addressof @__workgroup_mem__0

@antiagainst @levivic @zlei 


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125604/new/

https://reviews.llvm.org/D125604

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D125604: [FileCheck] Catch missspelled directives.

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 430322.
kosarev added a comment.
Herald added a reviewer: bollu.

Add Polly fixes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125604/new/

https://reviews.llvm.org/D125604

Files:
  clang/test/CodeGen/cmse-clear-return.c
  clang/test/CodeGenCXX/attr-mustprogress.cpp
  clang/test/CodeGenCXX/eh-aggregate-copy-destroy.cpp
  clang/test/CodeGenCXX/inheriting-constructor.cpp
  clang/test/CodeGenObjC/non-runtime-protocol.m
  clang/test/OpenMP/master_taskloop_private_codegen.cpp
  clang/test/OpenMP/master_taskloop_simd_private_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_private_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_private_codegen.cpp
  clang/test/OpenMP/task_private_codegen.cpp
  clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp
  clang/test/OpenMP/taskloop_private_codegen.cpp
  clang/test/OpenMP/taskloop_simd_private_codegen.cpp
  llvm/include/llvm/FileCheck/FileCheck.h
  llvm/lib/FileCheck/FileCheck.cpp
  llvm/test/Analysis/MemorySSA/phi-translation.ll
  llvm/test/Analysis/RegionInfo/infinite_loop_4.ll
  llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
  llvm/test/CodeGen/AArch64/neon-vmull-high-p64.ll
  llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll
  llvm/test/CodeGen/AMDGPU/hoist-cond.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
  llvm/test/CodeGen/AMDGPU/mode-register.mir
  llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
  llvm/test/CodeGen/AMDGPU/smrd.ll
  llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll
  llvm/test/CodeGen/AVR/atomics/fence.ll
  llvm/test/CodeGen/BPF/CORE/offset-reloc-middle-chain.ll
  llvm/test/CodeGen/MIR/AMDGPU/extra-imm-operand.mir
  llvm/test/CodeGen/MIR/AMDGPU/extra-reg-operand.mir
  llvm/test/CodeGen/Thumb2/thumb2-execute-only-prologue.ll
  llvm/test/CodeGen/WebAssembly/libcalls.ll
  llvm/test/CodeGen/X86/GlobalISel/select-ext.mir
  llvm/test/CodeGen/X86/coalesce-dead-lanes.mir
  llvm/test/CodeGen/X86/copy-propagation.ll
  llvm/test/CodeGen/X86/lvi-hardening-indirectbr.ll
  llvm/test/CodeGen/X86/statepoint-vreg-details.ll
  llvm/test/DebugInfo/NVPTX/debug-info.ll
  llvm/test/DebugInfo/X86/debug-info-template-parameter.ll
  llvm/test/FileCheck/missspelled-directive.txt
  llvm/test/MC/AMDGPU/data.s
  llvm/test/MC/AsmParser/directive_file-g.s
  llvm/test/MC/PowerPC/ppc64-reloc-directive-pcrel.s
  llvm/test/MC/WebAssembly/unnamed-data.ll
  llvm/test/Transforms/Inline/inline-strictfp.ll
  llvm/test/Transforms/LoopVectorize/X86/gather-vs-interleave.ll
  llvm/test/Transforms/MergeFunc/alias.ll
  llvm/test/Transforms/PGOProfile/PR41279.ll
  llvm/test/Transforms/PGOProfile/memop_clone.ll
  llvm/test/Transforms/PGOProfile/memop_size_from_strlen.ll
  llvm/test/tools/llvm-dwp/X86/tu_units_v5.s
  llvm/test/tools/llvm-dwp/X86/type_dedup_v5.test
  llvm/test/tools/llvm-objdump/MachO/disassemble-all.test
  llvm/test/tools/llvm-readobj/COFF/unwind-arm64-windows.test
  mlir/test/Conversion/MemRefToSPIRV/alloc.mlir
  mlir/test/Dialect/Affine/loop-coalescing.mlir
  mlir/test/Dialect/Linalg/fuse-with-reshape-by-collapsing.mlir
  mlir/test/Dialect/Linalg/tile-and-fuse-no-fuse.mlir
  mlir/test/Dialect/MemRef/canonicalize.mlir
  mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
  mlir/test/Dialect/Vector/vector-transfer-full-partial-split.mlir
  mlir/test/IR/dynamic.mlir
  mlir/test/mlir-tblgen/op-decl-and-defs.td
  polly/test/ScopDetect/dot-scops-npm.ll

Index: polly/test/ScopDetect/dot-scops-npm.ll
===
--- polly/test/ScopDetect/dot-scops-npm.ll
+++ polly/test/ScopDetect/dot-scops-npm.ll
@@ -30,35 +30,35 @@
 ; CHECK-NEXT: Node0x[[OUTER_EXIT]] -> Node0x[[RETURN_ID:.*]];
 ; CHECK-NEXT: Node0x[[RETURN_ID]] [shape=record,label="{return:
 ; CHECK-NEXT: colorscheme = "paired12"
-; CHECK_NEXT: subgraph cluster_0x[[:.*]] {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = solid;
-; CHECK_NEXT: color = 1
-; CHECK_NEXT: subgraph cluster_0x[[:.*]] {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = filled;
-; CHECK_NEXT: color = 3subgraph cluster_0x7152c40 {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = solid;
-; CHECK_NEXT: color = 5
-; CHECK_NEXT: subgraph cluster_0x[[:.*]] {
-; CHECK_NEXT: label = "";
-; CHECK_NEXT: style = solid;
-; CHECK_NEXT: color = 7
-; CHECK_NEXT: Node0x[[INNER_FOR_ID]];
-; CHECK_NEXT: Node0x[[BABY1_ID]];
-; CHECK_NEXT: Node0x[[INNER_INC_ID]];
-; CHECK_NEXT: }
-; CHECK_NEXT: Node0x[[OUTER_FOR_ID]];
-; CHECK_NEXT: Node0x[[INNER_EXIT_ID]];
-; CHECK_NEXT: Node0x[[OUTER_INC_ID]];
-; CHECK_NEXT: }
-; CHECK_NEXT: Node0x[[OUTER_EXIT]];
-; CHECK_NEXT: }
-; CHECK_NEXT: Node0x[[EntryID]];
-; CHECK_NEXT: Node0x[[RETURN_ID]];
-; CHECK_NEXT: }
-; CHECK_NEXT: }
+; CHECK-NEXT: subgraph cluster_0x{{.*}} {
+; CHECK-NEXT: label = "";
+; CHECK-NEXT: style = solid;
+; CHECK-NEXT: color = 1
+; CHECK-NEXT: subgraph cluster_0x{{.*}} {
+; CHECK-NEXT: label = "";
+; CHECK-NEXT: style = filled;
+; 

[PATCH] D125604: [FileCheck] Catch missspelled directives.

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added inline comments.



Comment at: llvm/lib/FileCheck/FileCheck.cpp:1774-1781
+static std::pair
+FindCheckType(const FileCheckRequest , StringRef Buffer, StringRef Prefix) 
{
+  bool Misspelled = false;
+  auto Res = FindCheckType(Req, Buffer, Prefix, Misspelled);
+  if (Res.first != Check::CheckNone && Misspelled)
+return {Check::CheckMisspelled, Res.second};
+  return Res;

thopre wrote:
> kosarev wrote:
> > thopre wrote:
> > > kosarev wrote:
> > > > thopre wrote:
> > > > > Instead of introducing a new wrapper, why don't you change all the 
> > > > > return to call a constructor method (e.g. `make_check_type()`) that 
> > > > > does what this wrapper do? Then there would not be any FindCheckType 
> > > > > that take a Misspelled parameter.
> > > > > 
> > > > > I'm also not sure about Misspelled being a check kind. It feels 
> > > > > conceptually wrong but on the other hand I guess it makes the 
> > > > > implementation simpler.
> > > > Tried that. Replacing the returned pair with a new `CheckLine` kind of 
> > > > object implementing the misspelled-related logic seems to add a lot of 
> > > > extra clutter such as the definition of the new structure itself, but 
> > > > especially all the repetitive mentions of `Misspelled` on every 
> > > > `return`. Feels like having it as a reference parameter works better, 
> > > > as we only need to alter the flag occasionally.
> > > > 
> > > > Regarding `CheckMisspelled`, now that we have `CheckBadNot` and 
> > > > `CheckBadCount`, this looks the usual way of propagating the 
> > > > information about our spelling-related concerns. Might be not the best 
> > > > design and may be worth looking into at some point, but at least doesn' 
> > > > seem to be specific to this patch?
> > > I was thinking something along the line of:
> > > 
> > > return getRealCheckType(CHECK::CheckBadCount, Rest, Misspelled); with:
> > > 
> > > ```static std::pair
> > > getRealCheckType(Check::FileCheckType CheckType, StringRef Rest, bool 
> > > Misspelled) {
> > >   if (CheckType != Check::CheckNone && Misspelled)
> > > return {Check::CheckMisspelled, Rest};
> > >   return {CheckType, Rest};
> > > }```
> > > 
> > > Fair enough for CheckMisspelled, there is indeeed precedent.
> > That unfortunately wouldn't eliminate the repetitive `return 
> > getRealCheckType(..., Misspelled)` bits, thus adding a significant amount 
> > of clutter -- all for the sake of a single assignment where we raise the 
> > flag, while also making the code more fragile as the compiler wouldn't then 
> > be able to catch `return`s without calling `getRealCheckType()`. And if 
> > that's not enough, then the name of the function sounds like we introduce 
> > one of the most irritating kinds of concepts -- the 'real' ones. :-)
> Fair enough. LGTM for the FileCheck part then. Have you sent a message to 
> discourse to ask test authors for help on the TODO?
https://discourse.llvm.org/t/help-wanted-with-fixing-misspelled-filecheck-directives/62593

Thanks for the idea!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125604/new/

https://reviews.llvm.org/D125604

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D125604: [FileCheck] Catch missspelled directives.

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added inline comments.



Comment at: llvm/lib/FileCheck/FileCheck.cpp:1774-1781
+static std::pair
+FindCheckType(const FileCheckRequest , StringRef Buffer, StringRef Prefix) 
{
+  bool Misspelled = false;
+  auto Res = FindCheckType(Req, Buffer, Prefix, Misspelled);
+  if (Res.first != Check::CheckNone && Misspelled)
+return {Check::CheckMisspelled, Res.second};
+  return Res;

thopre wrote:
> kosarev wrote:
> > thopre wrote:
> > > Instead of introducing a new wrapper, why don't you change all the return 
> > > to call a constructor method (e.g. `make_check_type()`) that does what 
> > > this wrapper do? Then there would not be any FindCheckType that take a 
> > > Misspelled parameter.
> > > 
> > > I'm also not sure about Misspelled being a check kind. It feels 
> > > conceptually wrong but on the other hand I guess it makes the 
> > > implementation simpler.
> > Tried that. Replacing the returned pair with a new `CheckLine` kind of 
> > object implementing the misspelled-related logic seems to add a lot of 
> > extra clutter such as the definition of the new structure itself, but 
> > especially all the repetitive mentions of `Misspelled` on every `return`. 
> > Feels like having it as a reference parameter works better, as we only need 
> > to alter the flag occasionally.
> > 
> > Regarding `CheckMisspelled`, now that we have `CheckBadNot` and 
> > `CheckBadCount`, this looks the usual way of propagating the information 
> > about our spelling-related concerns. Might be not the best design and may 
> > be worth looking into at some point, but at least doesn' seem to be 
> > specific to this patch?
> I was thinking something along the line of:
> 
> return getRealCheckType(CHECK::CheckBadCount, Rest, Misspelled); with:
> 
> ```static std::pair
> getRealCheckType(Check::FileCheckType CheckType, StringRef Rest, bool 
> Misspelled) {
>   if (CheckType != Check::CheckNone && Misspelled)
> return {Check::CheckMisspelled, Rest};
>   return {CheckType, Rest};
> }```
> 
> Fair enough for CheckMisspelled, there is indeeed precedent.
That unfortunately wouldn't eliminate the repetitive `return 
getRealCheckType(..., Misspelled)` bits, thus adding a significant amount of 
clutter -- all for the sake of a single assignment where we raise the flag, 
while also making the code more fragile as the compiler wouldn't then be able 
to catch `return`s without calling `getRealCheckType()`. And if that's not 
enough, then the name of the function sounds like we introduce one of the most 
irritating kinds of concepts -- the 'real' ones. :-)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125604/new/

https://reviews.llvm.org/D125604

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D125604: [FileCheck] Catch missspelled directives.

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 429997.
kosarev added a comment.
Herald added subscribers: ThomasRaoux, sdasgup3, wenzhicui, wrengr, 
Chia-hungDuan, dcaballe, cota, mravishankar, teijeong, rdzhabarov, tatianashp, 
msifontes, jurahul, Kayjukh, grosul1, Joonsoo, stephenneuendorffer, liufengdb, 
aartbik, mgester, arpith-jacob, csigg, nicolasvasilache, antiagainst, shauheen, 
rriddle, mehdi_amini.
Herald added a reviewer: antiagainst.
Herald added a reviewer: nicolasvasilache.
Herald added a reviewer: aartbik.
Herald added a project: MLIR.

Added MLIR fixes.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125604/new/

https://reviews.llvm.org/D125604

Files:
  clang/test/CodeGen/cmse-clear-return.c
  clang/test/CodeGenCXX/attr-mustprogress.cpp
  clang/test/CodeGenCXX/eh-aggregate-copy-destroy.cpp
  clang/test/CodeGenCXX/inheriting-constructor.cpp
  clang/test/CodeGenObjC/non-runtime-protocol.m
  clang/test/OpenMP/master_taskloop_private_codegen.cpp
  clang/test/OpenMP/master_taskloop_simd_private_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_private_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_private_codegen.cpp
  clang/test/OpenMP/task_private_codegen.cpp
  clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp
  clang/test/OpenMP/taskloop_private_codegen.cpp
  clang/test/OpenMP/taskloop_simd_private_codegen.cpp
  llvm/include/llvm/FileCheck/FileCheck.h
  llvm/lib/FileCheck/FileCheck.cpp
  llvm/test/Analysis/MemorySSA/phi-translation.ll
  llvm/test/Analysis/RegionInfo/infinite_loop_4.ll
  llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
  llvm/test/CodeGen/AArch64/neon-vmull-high-p64.ll
  llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll
  llvm/test/CodeGen/AMDGPU/hoist-cond.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
  llvm/test/CodeGen/AMDGPU/mode-register.mir
  llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
  llvm/test/CodeGen/AMDGPU/smrd.ll
  llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll
  llvm/test/CodeGen/AVR/atomics/fence.ll
  llvm/test/CodeGen/BPF/CORE/offset-reloc-middle-chain.ll
  llvm/test/CodeGen/MIR/AMDGPU/extra-imm-operand.mir
  llvm/test/CodeGen/MIR/AMDGPU/extra-reg-operand.mir
  llvm/test/CodeGen/Thumb2/thumb2-execute-only-prologue.ll
  llvm/test/CodeGen/WebAssembly/libcalls.ll
  llvm/test/CodeGen/X86/GlobalISel/select-ext.mir
  llvm/test/CodeGen/X86/coalesce-dead-lanes.mir
  llvm/test/CodeGen/X86/copy-propagation.ll
  llvm/test/CodeGen/X86/lvi-hardening-indirectbr.ll
  llvm/test/CodeGen/X86/statepoint-vreg-details.ll
  llvm/test/DebugInfo/NVPTX/debug-info.ll
  llvm/test/DebugInfo/X86/debug-info-template-parameter.ll
  llvm/test/FileCheck/missspelled-directive.txt
  llvm/test/MC/AMDGPU/data.s
  llvm/test/MC/AsmParser/directive_file-g.s
  llvm/test/MC/PowerPC/ppc64-reloc-directive-pcrel.s
  llvm/test/MC/WebAssembly/unnamed-data.ll
  llvm/test/Transforms/Inline/inline-strictfp.ll
  llvm/test/Transforms/LoopVectorize/X86/gather-vs-interleave.ll
  llvm/test/Transforms/MergeFunc/alias.ll
  llvm/test/Transforms/PGOProfile/PR41279.ll
  llvm/test/Transforms/PGOProfile/memop_clone.ll
  llvm/test/Transforms/PGOProfile/memop_size_from_strlen.ll
  llvm/test/tools/llvm-dwp/X86/tu_units_v5.s
  llvm/test/tools/llvm-dwp/X86/type_dedup_v5.test
  llvm/test/tools/llvm-objdump/MachO/disassemble-all.test
  llvm/test/tools/llvm-readobj/COFF/unwind-arm64-windows.test
  mlir/test/Conversion/MemRefToSPIRV/alloc.mlir
  mlir/test/Dialect/Affine/loop-coalescing.mlir
  mlir/test/Dialect/Linalg/fuse-with-reshape-by-collapsing.mlir
  mlir/test/Dialect/Linalg/tile-and-fuse-no-fuse.mlir
  mlir/test/Dialect/MemRef/canonicalize.mlir
  mlir/test/Dialect/SPIRV/IR/memory-ops.mlir
  mlir/test/Dialect/Vector/vector-transfer-full-partial-split.mlir
  mlir/test/IR/dynamic.mlir
  mlir/test/mlir-tblgen/op-decl-and-defs.td

Index: mlir/test/mlir-tblgen/op-decl-and-defs.td
===
--- mlir/test/mlir-tblgen/op-decl-and-defs.td
+++ mlir/test/mlir-tblgen/op-decl-and-defs.td
@@ -199,7 +199,7 @@
   let results = (outs AnyType:$b);
 }
 
-// CHECK_LABEL: class HCollectiveParamsOp :
+// CHECK-LABEL: class HCollectiveParamsOp :
 // CHECK: static void build(::mlir::OpBuilder , ::mlir::OperationState , ::mlir::Type b, ::mlir::Value a);
 // CHECK: static void build(::mlir::OpBuilder , ::mlir::OperationState , ::mlir::TypeRange resultTypes, ::mlir::Value a);
 // CHECK: static void build(::mlir::OpBuilder &, ::mlir::OperationState , ::mlir::TypeRange resultTypes, ::mlir::ValueRange operands, ::llvm::ArrayRef<::mlir::NamedAttribute> attributes = {})
@@ -212,7 +212,7 @@
   let results = (outs Variadic:$b);
 }
 
-// CHECK_LABEL: class HCollectiveParamsSuppress0Op :
+// CHECK-LABEL: class HCollectiveParamsSuppress0Op :
 // CHECK-NOT: static void build(::mlir::OpBuilder , ::mlir::OperationState , ::mlir::TypeRange b, ::mlir::ValueRange a);
 // CHECK: static void build(::mlir::OpBuilder &, 

[PATCH] D125604: [FileCheck] Catch missspelled directives.

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added inline comments.



Comment at: llvm/lib/FileCheck/FileCheck.cpp:1774-1781
+static std::pair
+FindCheckType(const FileCheckRequest , StringRef Buffer, StringRef Prefix) 
{
+  bool Misspelled = false;
+  auto Res = FindCheckType(Req, Buffer, Prefix, Misspelled);
+  if (Res.first != Check::CheckNone && Misspelled)
+return {Check::CheckMisspelled, Res.second};
+  return Res;

thopre wrote:
> Instead of introducing a new wrapper, why don't you change all the return to 
> call a constructor method (e.g. `make_check_type()`) that does what this 
> wrapper do? Then there would not be any FindCheckType that take a Misspelled 
> parameter.
> 
> I'm also not sure about Misspelled being a check kind. It feels conceptually 
> wrong but on the other hand I guess it makes the implementation simpler.
Tried that. Replacing the returned pair with a new `CheckLine` kind of object 
implementing the misspelled-related logic seems to add a lot of extra clutter 
such as the definition of the new structure itself, but especially all the 
repetitive mentions of `Misspelled` on every `return`. Feels like having it as 
a reference parameter works better, as we only need to alter the flag 
occasionally.

Regarding `CheckMisspelled`, now that we have `CheckBadNot` and 
`CheckBadCount`, this looks the usual way of propagating the information about 
our spelling-related concerns. Might be not the best design and may be worth 
looking into at some point, but at least doesn' seem to be specific to this 
patch?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125604/new/

https://reviews.llvm.org/D125604

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D125604: [FileCheck] Catch missspelled directives.

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

In D125604#3514983 , @jhenderson 
wrote:

> Are the TODO cases where the test fails if changing them?

Yes, this and where the fix is not perfectly obvious.




Comment at: llvm/test/FileCheck/missspelled-directive.txt:18
+
+P4_COUNT-2: foo
+CHECK4: error: misspelled directive 'P4_COUNT-2:'

jhenderson wrote:
> What about `P4-COUNT_2`? Is that case not really related?
Yeah, that's intentionally left for later. At the moment I don't even know how 
severe the problem with `COUNT_*` is, need to try and see.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125604/new/

https://reviews.llvm.org/D125604

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D125604: [FileCheck] Catch missspelled directives.

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

A work in progress. Contains changes that we likely want to see addressed 
separately.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D125604/new/

https://reviews.llvm.org/D125604

___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D125604: [FileCheck] Catch missspelled directives.

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
Herald added subscribers: mattd, gchakrabarti, pmatos, asb, asavonic, wenlei, 
kerbowa, pengfei, Jim, asbirlea, thopre, rupprecht, george.burgess.iv, kbarton, 
hiraditya, jgravelle-google, sbc100, jvesely, nemanjai, dylanmckay, dschuff, 
jholewinski.
Herald added a reviewer: jhenderson.
Herald added a reviewer: MaskRay.
Herald added a project: All.
kosarev requested review of this revision.
Herald added subscribers: llvm-commits, cfe-commits, StephenFan, aheejin.
Herald added projects: clang, LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D125604

Files:
  clang/test/CodeGen/cmse-clear-return.c
  clang/test/CodeGenCXX/attr-mustprogress.cpp
  clang/test/CodeGenCXX/eh-aggregate-copy-destroy.cpp
  clang/test/CodeGenCXX/inheriting-constructor.cpp
  clang/test/CodeGenObjC/non-runtime-protocol.m
  clang/test/OpenMP/master_taskloop_private_codegen.cpp
  clang/test/OpenMP/master_taskloop_simd_private_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_private_codegen.cpp
  clang/test/OpenMP/parallel_master_taskloop_simd_private_codegen.cpp
  clang/test/OpenMP/task_private_codegen.cpp
  clang/test/OpenMP/taskgroup_task_reduction_codegen.cpp
  clang/test/OpenMP/taskloop_private_codegen.cpp
  clang/test/OpenMP/taskloop_simd_private_codegen.cpp
  llvm/include/llvm/FileCheck/FileCheck.h
  llvm/lib/FileCheck/FileCheck.cpp
  llvm/test/Analysis/MemorySSA/phi-translation.ll
  llvm/test/Analysis/RegionInfo/infinite_loop_4.ll
  llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll
  llvm/test/CodeGen/AArch64/neon-vmull-high-p64.ll
  llvm/test/CodeGen/AMDGPU/divergence-driven-bfe-isel.ll
  llvm/test/CodeGen/AMDGPU/hoist-cond.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ps.live.ll
  llvm/test/CodeGen/AMDGPU/mode-register.mir
  llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir
  llvm/test/CodeGen/AMDGPU/smrd.ll
  llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll
  llvm/test/CodeGen/AVR/atomics/fence.ll
  llvm/test/CodeGen/BPF/CORE/offset-reloc-middle-chain.ll
  llvm/test/CodeGen/MIR/AMDGPU/extra-imm-operand.mir
  llvm/test/CodeGen/MIR/AMDGPU/extra-reg-operand.mir
  llvm/test/CodeGen/Thumb2/thumb2-execute-only-prologue.ll
  llvm/test/CodeGen/WebAssembly/libcalls.ll
  llvm/test/CodeGen/X86/GlobalISel/select-ext.mir
  llvm/test/CodeGen/X86/coalesce-dead-lanes.mir
  llvm/test/CodeGen/X86/copy-propagation.ll
  llvm/test/CodeGen/X86/lvi-hardening-indirectbr.ll
  llvm/test/CodeGen/X86/statepoint-vreg-details.ll
  llvm/test/DebugInfo/NVPTX/debug-info.ll
  llvm/test/DebugInfo/X86/debug-info-template-parameter.ll
  llvm/test/FileCheck/missspelled-directive.txt
  llvm/test/MC/AMDGPU/data.s
  llvm/test/MC/AsmParser/directive_file-g.s
  llvm/test/MC/PowerPC/ppc64-reloc-directive-pcrel.s
  llvm/test/MC/WebAssembly/unnamed-data.ll
  llvm/test/Transforms/Inline/inline-strictfp.ll
  llvm/test/Transforms/LoopVectorize/X86/gather-vs-interleave.ll
  llvm/test/Transforms/MergeFunc/alias.ll
  llvm/test/Transforms/PGOProfile/PR41279.ll
  llvm/test/Transforms/PGOProfile/memop_clone.ll
  llvm/test/Transforms/PGOProfile/memop_size_from_strlen.ll
  llvm/test/tools/llvm-dwp/X86/tu_units_v5.s
  llvm/test/tools/llvm-dwp/X86/type_dedup_v5.test
  llvm/test/tools/llvm-objdump/MachO/disassemble-all.test
  llvm/test/tools/llvm-readobj/COFF/unwind-arm64-windows.test

Index: llvm/test/tools/llvm-readobj/COFF/unwind-arm64-windows.test
===
--- llvm/test/tools/llvm-readobj/COFF/unwind-arm64-windows.test
+++ llvm/test/tools/llvm-readobj/COFF/unwind-arm64-windows.test
@@ -27,7 +27,7 @@
 UNWIND1-NEXT:0x28; ldp x19, x20, [sp], #64
 UNWIND1-NEXT:0xe4; end
 UNWIND1-NEXT:  ]
-UNWIND1_NEXT:}
+UNWIND1-NEXT:}
 
 
 UNWIND2: ExceptionData {
Index: llvm/test/tools/llvm-objdump/MachO/disassemble-all.test
===
--- llvm/test/tools/llvm-objdump/MachO/disassemble-all.test
+++ llvm/test/tools/llvm-objdump/MachO/disassemble-all.test
@@ -1,39 +1,39 @@
 // RUN: llvm-objdump --macho -d --full-leading-addr --print-imm-hex --no-show-raw-insn %p/Inputs/macho-multiple-text | FileCheck %s --check-prefix=TEXT
 
 TEXT:  (__TEXT,__text) section
-TEXT_NEXT: _main:
-TEXT_NEXT: 00010f60	pushq	%rbp
-TEXT_NEXT: 00010f61	movq	%rsp, %rbp
-TEXT_NEXT: 00010f64	subq	$0x10, %rsp
-TEXT_NEXT: 00010f68	movl	$0x0, -0x4(%rbp)
-TEXT_NEXT: 00010f6f	callq	_hello
-TEXT_NEXT: 00010f74	xorl	%eax, %eax
-TEXT_NEXT: 00010f76	addq	$0x10, %rsp
-TEXT_NEXT: 00010f7a	popq	%rbp
-TEXT_NEXT: 00010f7b	retq
+TEXT-NEXT: _main:
+TEXT-NEXT: 00010f60	pushq	%rbp
+TEXT-NEXT: 00010f61	movq	%rsp, %rbp
+TEXT-NEXT: 00010f64	subq	$0x10, %rsp
+TEXT-NEXT: 00010f68	movl	$0x0, -0x4(%rbp)
+TEXT-NEXT: 00010f6f	callq	_hello
+TEXT-NEXT: 00010f74	xorl	%eax, %eax
+TEXT-NEXT: 00010f76	

[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC340140: [NEON] Define fp16 vld and vst intrinsics 
conditionally (authored by kosarev, committed by ).

Repository:
  rC Clang

https://reviews.llvm.org/D49075

Files:
  include/clang/Basic/arm_neon.td
  test/CodeGen/arm-neon-vld.c
  test/CodeGen/arm-neon-vst.c
  test/Sema/arm-no-fp16.c

Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -337,48 +337,78 @@
 
 // E.3.14 Loads and stores of a single vector
 def VLD1  : WInst<"vld1", "dc",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VLD1_X2   : WInst<"vld1_x2", "2c",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VLD1_X3   : WInst<"vld1_x3", "3c",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VLD1_X4   : WInst<"vld1_x4", "4c",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VLD1_LANE : WInst<"vld1_lane", "dcdi",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VLD1_DUP  : WInst<"vld1_dup", "dc",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VST1  : WInst<"vst1", "vpd",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VST1_X2   : WInst<"vst1_x2", "vp2",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VST1_X3   : WInst<"vst1_x3", "vp3",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VST1_X4   : WInst<"vst1_x4", "vp4",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VST1_LANE : WInst<"vst1_lane", "vpdi",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
+let ArchGuard = "(__ARM_FP & 2)" in {
+def VLD1_F16  : WInst<"vld1", "dc", "hQh">;
+def VLD1_X2_F16   : WInst<"vld1_x2", "2c", "hQh">;
+def VLD1_X3_F16   : WInst<"vld1_x3", "3c", "hQh">;
+def VLD1_X4_F16   : WInst<"vld1_x4", "4c", "hQh">;
+def VLD1_LANE_F16 : WInst<"vld1_lane", "dcdi", "hQh">;
+def VLD1_DUP_F16  : WInst<"vld1_dup", "dc", "hQh">;
+def VST1_F16  : WInst<"vst1", "vpd", "hQh">;
+def VST1_X2_F16   : WInst<"vst1_x2", "vp2", "hQh">;
+def VST1_X3_F16   : WInst<"vst1_x3", "vp3", "hQh">;
+def VST1_X4_F16   : WInst<"vst1_x4", "vp4", "hQh">;
+def VST1_LANE_F16 : WInst<"vst1_lane", "vpdi", "hQh">;
+}
 
 
 // E.3.15 Loads and stores of an N-element structure
-def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+def VLD2 : WInst<"vld2", "2c", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
+def VLD3 : WInst<"vld3", "3c", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
+def VLD4 : WInst<"vld4", "4c", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VLD2_DUP  : WInst<"vld2_dup", "2c",
-  "UcUsUiUlcsilhfPcPsQcQfQhQiQlQsQPcQPsQUcQUiQUlQUs">;
+  "UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUs">;
 def VLD3_DUP  : WInst<"vld3_dup", "3c",
-  "UcUsUiUlcsilhfPcPsQcQfQhQiQlQsQPcQPsQUcQUiQUlQUs">;
+  "UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUs">;
 def VLD4_DUP  : WInst<"vld4_dup", "4c",
-  "UcUsUiUlcsilhfPcPsQcQfQhQiQlQsQPcQPsQUcQUiQUlQUs">;
-def VLD2_LANE : WInst<"vld2_lane", "2c2i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
-def VLD3_LANE : WInst<"vld3_lane", "3c3i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
-def VLD4_LANE : WInst<"vld4_lane", "4c4i", "QUsQUiQsQiQhQfQPsUcUsUicsihfPcPs">;
-def VST2 : WInst<"vst2", "vp2", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VST3 : WInst<"vst3", "vp3", "QUcQUsQUiQcQsQiQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
-def VST4 : WInst<"vst4", "vp4", 

[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL340140: [NEON] Define fp16 vld and vst intrinsics 
conditionally (authored by kosarev, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D49075?vs=157960=161400#toc

Repository:
  rC Clang

https://reviews.llvm.org/D49075

Files:
  cfe/trunk/include/clang/Basic/arm_neon.td
  cfe/trunk/test/CodeGen/arm-neon-vld.c
  cfe/trunk/test/CodeGen/arm-neon-vst.c
  cfe/trunk/test/Sema/arm-no-fp16.c

Index: cfe/trunk/test/CodeGen/arm-neon-vst.c
===
--- cfe/trunk/test/CodeGen/arm-neon-vst.c
+++ cfe/trunk/test/CodeGen/arm-neon-vst.c
@@ -2,8 +2,8 @@
 // RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
 // RUN: FileCheck -check-prefixes=CHECK,CHECK-A64 %s
 // RUN: %clang_cc1 -triple armv8-none-linux-gnueabi -target-feature +neon \
-// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
-// RUN: FileCheck -check-prefixes=CHECK,CHECK-A32 %s
+// RUN: -target-feature +fp16 -S -disable-O0-optnone -emit-llvm -o - %s | \
+// RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A32 %s
 
 #include 
 
Index: cfe/trunk/test/CodeGen/arm-neon-vld.c
===
--- cfe/trunk/test/CodeGen/arm-neon-vld.c
+++ cfe/trunk/test/CodeGen/arm-neon-vld.c
@@ -2,8 +2,8 @@
 // RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
 // RUN: FileCheck -check-prefixes=CHECK,CHECK-A64 %s
 // RUN: %clang_cc1 -triple armv8-none-linux-gnueabi -target-feature +neon \
-// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
-// RUN: FileCheck -check-prefixes=CHECK,CHECK-A32 %s
+// RUN: -target-feature +fp16 -S -disable-O0-optnone -emit-llvm -o - %s | \
+// RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A32 %s
 
 #include 
 
Index: cfe/trunk/test/Sema/arm-no-fp16.c
===
--- cfe/trunk/test/Sema/arm-no-fp16.c
+++ cfe/trunk/test/Sema/arm-no-fp16.c
@@ -83,3 +83,213 @@
 float16x8_t test_vminnmq_f16(float16x8_t a, float16x8_t b) {
   return vminnmq_f16(a, b); // expected-warning{{implicit declaration of function 'vminnmq_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
 }
+
+float16x4_t test_vld1_f16(const float16_t *a) {
+  return vld1_f16(a); // expected-warning{{implicit declaration of function 'vld1_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vld1q_f16(const float16_t *a) {
+  return vld1q_f16(a); // expected-warning{{implicit declaration of function 'vld1q_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vld1_dup_f16(const float16_t *a) {
+  return vld1_dup_f16(a); // expected-warning{{implicit declaration of function 'vld1_dup_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vld1q_dup_f16(const float16_t *a) {
+  return vld1q_dup_f16(a); // expected-warning{{implicit declaration of function 'vld1q_dup_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vld1_lane_f16(const float16_t *a, float16x4_t b) {
+  return vld1_lane_f16(a, b, 3); // expected-warning{{implicit declaration of function 'vld1_lane_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vld1q_lane_f16(const float16_t *a, float16x8_t b) {
+  return vld1q_lane_f16(a, b, 7); // expected-warning{{implicit declaration of function 'vld1q_lane_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
+
+float16x4x2_t test_vld1_f16_x2(const float16_t *a) {
+  return vld1_f16_x2(a); // expected-warning{{implicit declaration of function 'vld1_f16_x2'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4x2_t'}}
+}
+
+float16x8x2_t test_vld1q_f16_x2(const float16_t *a) {
+  return vld1q_f16_x2(a); // expected-warning{{implicit declaration of function 'vld1q_f16_x2'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8x2_t'}}
+}
+
+float16x4x3_t test_vld1_f16_x3(const float16_t *a) {
+  return vld1_f16_x3(a); // expected-warning{{implicit declaration of function 'vld1_f16_x3'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4x3_t'}}
+}
+
+float16x8x3_t test_vld1q_f16_x3(const float16_t *a) {
+  return vld1q_f16_x3(a); // expected-warning{{implicit declaration of function 'vld1q_f16_x3'}} expected-error{{returning 'int' from a function with incompatible result type 

[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Ping.


https://reviews.llvm.org/D49075



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 157960.
kosarev added a comment.

Test that the affected intrinsics are not defined in no-fp16 mode.


https://reviews.llvm.org/D49075

Files:
  include/clang/Basic/arm_neon.td
  test/CodeGen/arm-neon-vld.c
  test/CodeGen/arm-neon-vst.c
  test/Sema/arm-no-fp16.c

Index: test/Sema/arm-no-fp16.c
===
--- test/Sema/arm-no-fp16.c
+++ test/Sema/arm-no-fp16.c
@@ -83,3 +83,213 @@
 float16x8_t test_vminnmq_f16(float16x8_t a, float16x8_t b) {
   return vminnmq_f16(a, b); // expected-warning{{implicit declaration of function 'vminnmq_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
 }
+
+float16x4_t test_vld1_f16(const float16_t *a) {
+  return vld1_f16(a); // expected-warning{{implicit declaration of function 'vld1_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vld1q_f16(const float16_t *a) {
+  return vld1q_f16(a); // expected-warning{{implicit declaration of function 'vld1q_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vld1_dup_f16(const float16_t *a) {
+  return vld1_dup_f16(a); // expected-warning{{implicit declaration of function 'vld1_dup_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vld1q_dup_f16(const float16_t *a) {
+  return vld1q_dup_f16(a); // expected-warning{{implicit declaration of function 'vld1q_dup_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vld1_lane_f16(const float16_t *a, float16x4_t b) {
+  return vld1_lane_f16(a, b, 3); // expected-warning{{implicit declaration of function 'vld1_lane_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vld1q_lane_f16(const float16_t *a, float16x8_t b) {
+  return vld1q_lane_f16(a, b, 7); // expected-warning{{implicit declaration of function 'vld1q_lane_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
+
+float16x4x2_t test_vld1_f16_x2(const float16_t *a) {
+  return vld1_f16_x2(a); // expected-warning{{implicit declaration of function 'vld1_f16_x2'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4x2_t'}}
+}
+
+float16x8x2_t test_vld1q_f16_x2(const float16_t *a) {
+  return vld1q_f16_x2(a); // expected-warning{{implicit declaration of function 'vld1q_f16_x2'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8x2_t'}}
+}
+
+float16x4x3_t test_vld1_f16_x3(const float16_t *a) {
+  return vld1_f16_x3(a); // expected-warning{{implicit declaration of function 'vld1_f16_x3'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4x3_t'}}
+}
+
+float16x8x3_t test_vld1q_f16_x3(const float16_t *a) {
+  return vld1q_f16_x3(a); // expected-warning{{implicit declaration of function 'vld1q_f16_x3'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8x3_t'}}
+}
+
+float16x4x4_t test_vld1_f16_x4(const float16_t *a) {
+  return vld1_f16_x4(a); // expected-warning{{implicit declaration of function 'vld1_f16_x4'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4x4_t'}}
+}
+
+float16x8x4_t test_vld1q_f16_x4(const float16_t *a) {
+  return vld1q_f16_x4(a); // expected-warning{{implicit declaration of function 'vld1q_f16_x4'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8x4_t'}}
+}
+
+float16x4x2_t test_vld2_f16(const float16_t *a) {
+  return vld2_f16(a); // expected-warning{{implicit declaration of function 'vld2_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4x2_t'}}
+}
+
+float16x8x2_t test_vld2q_f16(const float16_t *a) {
+  return vld2q_f16(a); // expected-warning{{implicit declaration of function 'vld2q_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8x2_t'}}
+}
+
+float16x4x2_t test_vld2_lane_f16(const float16_t *a, float16x4x2_t b) {
+  return vld2_lane_f16(a, b, 3); // expected-warning{{implicit declaration of function 'vld2_lane_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4x2_t'}}
+}
+
+float16x8x2_t test_vld2q_lane_f16(const float16_t *a, float16x8x2_t b) {
+  return vld2q_lane_f16(a, b, 7); // expected-warning{{implicit declaration of function 'vld2q_lane_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8x2_t'}}
+}
+
+float16x4x2_t test_vld2_dup_f16(const float16_t *src) {
+  return vld2_dup_f16(src); // expected-warning{{implicit declaration of function 'vld2_dup_f16'}} 

[PATCH] D49375: [NEON] Define half-precision vmaxnm intrinsics only when available

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC337704: [NEON] Define half-precision vmaxnm intrinsics only 
when available (authored by kosarev, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D49375?vs=155675=156802#toc

Repository:
  rC Clang

https://reviews.llvm.org/D49375

Files:
  include/clang/Basic/arm_neon.td
  test/Sema/arm-no-fp16.c


Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -1466,8 +1466,10 @@
   // Max/Min
   def VMAXH : SInst<"vmax", "ddd", "hQh">;
   def VMINH : SInst<"vmin", "ddd", "hQh">;
-  def FMAXNMH   : SInst<"vmaxnm", "ddd", "hQh">;
-  def FMINNMH   : SInst<"vminnm", "ddd", "hQh">;
+  let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN) && 
defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
+def FMAXNMH   : SInst<"vmaxnm", "ddd", "hQh">;
+def FMINNMH   : SInst<"vminnm", "ddd", "hQh">;
+  }
 
   // Multiplication/Division
   def VMULH : SOpInst<"vmul", "ddd", "hQh", OP_MUL>;
Index: test/Sema/arm-no-fp16.c
===
--- test/Sema/arm-no-fp16.c
+++ test/Sema/arm-no-fp16.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -triple thumbv7-none-eabi %s -target-feature +neon 
-target-feature -fp16 -fsyntax-only -verify
+// RUN: %clang_cc1 -triple thumbv7-none-eabi %s -target-feature +neon \
+// RUN:   -fallow-half-arguments-and-returns -target-feature -fp16 \
+// RUN:   -fsyntax-only -verify
 
 #include 
 
@@ -65,3 +67,19 @@
 float16x8_t test_vrndxq_f16(float16x8_t a) {
   return vrndxq_f16(a); // expected-warning{{implicit declaration of function 
'vrndxq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
 }
+
+float16x4_t test_vmaxnm_f16(float16x4_t a, float16x4_t b) {
+  return vmaxnm_f16(a, b); // expected-warning{{implicit declaration of 
function 'vmaxnm_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vmaxnmq_f16(float16x8_t a, float16x8_t b) {
+  return vmaxnmq_f16(a, b); // expected-warning{{implicit declaration of 
function 'vmaxnmq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vminnm_f16(float16x4_t a, float16x4_t b) {
+  return vminnm_f16(a, b); // expected-warning{{implicit declaration of 
function 'vminnm_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vminnmq_f16(float16x8_t a, float16x8_t b) {
+  return vminnmq_f16(a, b); // expected-warning{{implicit declaration of 
function 'vminnmq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
+}


Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -1466,8 +1466,10 @@
   // Max/Min
   def VMAXH : SInst<"vmax", "ddd", "hQh">;
   def VMINH : SInst<"vmin", "ddd", "hQh">;
-  def FMAXNMH   : SInst<"vmaxnm", "ddd", "hQh">;
-  def FMINNMH   : SInst<"vminnm", "ddd", "hQh">;
+  let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
+def FMAXNMH   : SInst<"vmaxnm", "ddd", "hQh">;
+def FMINNMH   : SInst<"vminnm", "ddd", "hQh">;
+  }
 
   // Multiplication/Division
   def VMULH : SOpInst<"vmul", "ddd", "hQh", OP_MUL>;
Index: test/Sema/arm-no-fp16.c
===
--- test/Sema/arm-no-fp16.c
+++ test/Sema/arm-no-fp16.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -triple thumbv7-none-eabi %s -target-feature +neon -target-feature -fp16 -fsyntax-only -verify
+// RUN: %clang_cc1 -triple thumbv7-none-eabi %s -target-feature +neon \
+// RUN:   -fallow-half-arguments-and-returns -target-feature -fp16 \
+// RUN:   -fsyntax-only -verify
 
 #include 
 
@@ -65,3 +67,19 @@
 float16x8_t test_vrndxq_f16(float16x8_t a) {
   return vrndxq_f16(a); // expected-warning{{implicit declaration of function 'vrndxq_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
 }
+
+float16x4_t test_vmaxnm_f16(float16x4_t a, float16x4_t b) {
+  return vmaxnm_f16(a, b); // expected-warning{{implicit declaration of function 'vmaxnm_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vmaxnmq_f16(float16x8_t a, float16x8_t b) {
+  return vmaxnmq_f16(a, b); // expected-warning{{implicit declaration of function 'vmaxnmq_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
+

[PATCH] D49376: [NEON] Define half-precision vrnd intrinsics only when available

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC337699: [NEON] Define half-precision vrnd intrinsics only 
when available (authored by kosarev, committed by ).

Repository:
  rC Clang

https://reviews.llvm.org/D49376

Files:
  include/clang/Basic/arm_neon.td
  test/Sema/arm-no-fp16.c


Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -1417,12 +1417,14 @@
   def VCVTP_U16: SInst<"vcvtp_u16", "ud", "hQh">;
 
   // Vector rounding
-  def FRINTZH  : SInst<"vrnd",  "dd", "hQh">;
-  def FRINTNH  : SInst<"vrndn", "dd", "hQh">;
-  def FRINTAH  : SInst<"vrnda", "dd", "hQh">;
-  def FRINTPH  : SInst<"vrndp", "dd", "hQh">;
-  def FRINTMH  : SInst<"vrndm", "dd", "hQh">;
-  def FRINTXH  : SInst<"vrndx", "dd", "hQh">;
+  let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING) 
&& defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
+def FRINTZH  : SInst<"vrnd",  "dd", "hQh">;
+def FRINTNH  : SInst<"vrndn", "dd", "hQh">;
+def FRINTAH  : SInst<"vrnda", "dd", "hQh">;
+def FRINTPH  : SInst<"vrndp", "dd", "hQh">;
+def FRINTMH  : SInst<"vrndm", "dd", "hQh">;
+def FRINTXH  : SInst<"vrndx", "dd", "hQh">;
+  }
 
   // Misc.
   def VABSH: SInst<"vabs", "dd", "hQh">;
Index: test/Sema/arm-no-fp16.c
===
--- test/Sema/arm-no-fp16.c
+++ test/Sema/arm-no-fp16.c
@@ -9,3 +9,59 @@
 float32x4_t test_vcvt_f32_f16(float16x4_t a) {
   return vcvt_f32_f16(a); // expected-warning{{implicit declaration of 
function 'vcvt_f32_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float32x4_t'}}
 }
+
+float16x4_t test_vrnda_f16(float16x4_t a) {
+  return vrnda_f16(a); // expected-warning{{implicit declaration of function 
'vrnda_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x4_t'}}
+}
+
+float16x8_t test_vrndaq_f16(float16x8_t a) {
+  return vrndaq_f16(a); // expected-warning{{implicit declaration of function 
'vrndaq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vrnd_f16(float16x4_t a) {
+  return vrnd_f16(a); // expected-warning{{implicit declaration of function 
'vrnd_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x4_t'}}
+}
+
+float16x8_t test_vrndq_f16(float16x8_t a) {
+  return vrndq_f16(a); // expected-warning{{implicit declaration of function 
'vrndq_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x8_t'}}
+}
+
+float16x4_t test_vrndi_f16(float16x4_t a) {
+  return vrndi_f16(a); // expected-warning{{implicit declaration of function 
'vrndi_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x4_t'}}
+}
+
+float16x8_t test_vrndiq_f16(float16x8_t a) {
+  return vrndiq_f16(a); // expected-warning{{implicit declaration of function 
'vrndiq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vrndm_f16(float16x4_t a) {
+  return vrndm_f16(a); // expected-warning{{implicit declaration of function 
'vrndm_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x4_t'}}
+}
+
+float16x8_t test_vrndmq_f16(float16x8_t a) {
+  return vrndmq_f16(a); // expected-warning{{implicit declaration of function 
'vrndmq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vrndn_f16(float16x4_t a) {
+  return vrndn_f16(a); // expected-warning{{implicit declaration of function 
'vrndn_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x4_t'}}
+}
+
+float16x8_t test_vrndnq_f16(float16x8_t a) {
+  return vrndnq_f16(a); // expected-warning{{implicit declaration of function 
'vrndnq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vrndp_f16(float16x4_t a) {
+  return vrndp_f16(a); // expected-warning{{implicit declaration of function 
'vrndp_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x4_t'}}
+}
+
+float16x8_t test_vrndpq_f16(float16x8_t a) {
+  return vrndpq_f16(a); // expected-warning{{implicit declaration of function 
'vrndpq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vrndx_f16(float16x4_t a) {
+  return vrndx_f16(a); // expected-warning{{implicit declaration of function 
'vrndx_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x4_t'}}
+}
+
+float16x8_t 

[PATCH] D49376: [NEON] Define half-precision vrnd intrinsics only when available

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added inline comments.



Comment at: include/clang/Basic/arm_neon.td:1419
   // Vector rounding
-  def FRINTZH  : SInst<"vrnd",  "dd", "hQh">;
-  def FRINTNH  : SInst<"vrndn", "dd", "hQh">;
-  def FRINTAH  : SInst<"vrnda", "dd", "hQh">;
-  def FRINTPH  : SInst<"vrndp", "dd", "hQh">;
-  def FRINTMH  : SInst<"vrndm", "dd", "hQh">;
-  def FRINTXH  : SInst<"vrndx", "dd", "hQh">;
+  let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING) 
&& defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
+def FRINTZH  : SInst<"vrnd",  "dd", "hQh">;

SjoerdMeijer wrote:
> nit: is the indentation a bit off here?
It's a nested `let ArchGuard`, so I guess we do want the indentation here?


https://reviews.llvm.org/D49376



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D49375: [NEON] Define half-precision vmaxnm intrinsics only when available

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Thanks for reviewing!




Comment at: include/clang/Basic/arm_neon.td:1466
   def VMINH : SInst<"vmin", "ddd", "hQh">;
-  def FMAXNMH   : SInst<"vmaxnm", "ddd", "hQh">;
-  def FMINNMH   : SInst<"vminnm", "ddd", "hQh">;
+  let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN) && 
defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
+def FMAXNMH   : SInst<"vmaxnm", "ddd", "hQh">;

SjoerdMeijer wrote:
> nit: indentation?
Do we want some special indentation here?


https://reviews.llvm.org/D49375



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D48829: [NEON] Fix support for vrndi_f32(), vrndiq_f32() and vrndns_f32() intrinsics

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC337690: [NEON] Fix support for vrndi_f32(), vrndiq_f32() and 
vrndns_f32() intrinsics (authored by kosarev, committed by ).

Repository:
  rC Clang

https://reviews.llvm.org/D48829

Files:
  include/clang/Basic/arm_neon.td
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGen/aarch64-neon-misc.c
  test/CodeGen/arm-neon-directed-rounding.c
  test/CodeGen/arm64-vrnd.c

Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -988,6 +988,7 @@
 def FRINTM_S32 : SInst<"vrndm", "dd", "fQf">;
 def FRINTX_S32 : SInst<"vrndx", "dd", "fQf">;
 def FRINTZ_S32 : SInst<"vrnd", "dd", "fQf">;
+def FRINTI_S32 : SInst<"vrndi", "dd", "fQf">;
 }
 
 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__) && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in {
@@ -997,7 +998,7 @@
 def FRINTM_S64 : SInst<"vrndm", "dd", "dQd">;
 def FRINTX_S64 : SInst<"vrndx", "dd", "dQd">;
 def FRINTZ_S64 : SInst<"vrnd", "dd", "dQd">;
-def FRINTI_S64 : SInst<"vrndi", "dd", "fdQfQd">;
+def FRINTI_S64 : SInst<"vrndi", "dd", "dQd">;
 }
 
 
Index: test/CodeGen/arm-neon-directed-rounding.c
===
--- test/CodeGen/arm-neon-directed-rounding.c
+++ test/CodeGen/arm-neon-directed-rounding.c
@@ -1,96 +1,128 @@
 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 \
 // RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
-// RUN: opt -S -mem2reg | FileCheck %s
+// RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A32 %s
+// RUN: %clang_cc1 -triple arm64-linux-gnueabihf -target-feature +neon \
+// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
+// RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A64 %s
 
 #include 
 
-// CHECK-LABEL: define <2 x float> @test_vrnda_f32(<2 x float> %a) #0 {
-// CHECK:   [[VRNDA_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrinta.v2f32(<2 x float> %a) #2
-// CHECK:   ret <2 x float> [[VRNDA_V1_I]]
+// CHECK-LABEL: define <2 x float> @test_vrnda_f32(<2 x float> %a)
+// CHECK-A32: [[VRNDA_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrinta.v2f32(<2 x float> %a)
+// CHECK-A64: [[VRNDA_V1_I:%.*]] = call <2 x float> @llvm.round.v2f32(<2 x float> %a)
+// CHECK: ret <2 x float> [[VRNDA_V1_I]]
 float32x2_t test_vrnda_f32(float32x2_t a) {
   return vrnda_f32(a);
 }
 
-// CHECK-LABEL: define <4 x float> @test_vrndaq_f32(<4 x float> %a) #0 {
-// CHECK:   [[VRNDAQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrinta.v4f32(<4 x float> %a) #2
-// CHECK:   ret <4 x float> [[VRNDAQ_V1_I]]
+// CHECK-LABEL: define <4 x float> @test_vrndaq_f32(<4 x float> %a)
+// CHECK-A32: [[VRNDAQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrinta.v4f32(<4 x float> %a)
+// CHECK-A64: [[VRNDAQ_V1_I:%.*]] = call <4 x float> @llvm.round.v4f32(<4 x float> %a)
+// CHECK: ret <4 x float> [[VRNDAQ_V1_I]]
 float32x4_t test_vrndaq_f32(float32x4_t a) {
   return vrndaq_f32(a);
 }
 
-// CHECK-LABEL: define <2 x float> @test_vrndm_f32(<2 x float> %a) #0 {
-// CHECK:   [[VRNDM_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintm.v2f32(<2 x float> %a) #2
-// CHECK:   ret <2 x float> [[VRNDM_V1_I]]
+// CHECK-LABEL: define <2 x float> @test_vrndm_f32(<2 x float> %a)
+// CHECK-A32: [[VRNDM_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintm.v2f32(<2 x float> %a)
+// CHECK-A64: [[VRNDM_V1_I:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> %a)
+// CHECK: ret <2 x float> [[VRNDM_V1_I]]
 float32x2_t test_vrndm_f32(float32x2_t a) {
   return vrndm_f32(a);
 }
 
-// CHECK-LABEL: define <4 x float> @test_vrndmq_f32(<4 x float> %a) #0 {
-// CHECK:   [[VRNDMQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintm.v4f32(<4 x float> %a) #2
-// CHECK:   ret <4 x float> [[VRNDMQ_V1_I]]
+// CHECK-LABEL: define <4 x float> @test_vrndmq_f32(<4 x float> %a)
+// CHECK-A32: [[VRNDMQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrintm.v4f32(<4 x float> %a)
+// CHECK-A64: [[VRNDMQ_V1_I:%.*]] = call <4 x float> @llvm.floor.v4f32(<4 x float> %a)
+// CHECK: ret <4 x float> [[VRNDMQ_V1_I]]
 float32x4_t test_vrndmq_f32(float32x4_t a) {
   return vrndmq_f32(a);
 }
 
-// CHECK-LABEL: define <2 x float> @test_vrndn_f32(<2 x float> %a) #0 {
-// CHECK:   [[VRNDN_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintn.v2f32(<2 x float> %a) #2
-// CHECK:   ret <2 x float> [[VRNDN_V1_I]]
+// CHECK-LABEL: define <2 x float> @test_vrndn_f32(<2 x float> %a)
+// CHECK-A32: [[VRNDN_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrintn.v2f32(<2 x float> %a)
+// CHECK-A64: [[VRNDN_V1_I:%.*]] = call <2 x float> @llvm.aarch64.neon.frintn.v2f32(<2 x float> %a)
+// CHECK: ret <2 x float> [[VRNDN_V1_I]]
 float32x2_t test_vrndn_f32(float32x2_t a) {
   return vrndn_f32(a);
 }
 
-// CHECK-LABEL: define 

[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Ping.


https://reviews.llvm.org/D49075



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D48829: [NEON] Fix support for vrndi_f32(), vrndiq_f32() and vrndns_f32() intrinsics

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Ping.


https://reviews.llvm.org/D48829



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D49375: [NEON] Define half-precision vmaxnm intrinsics only when available

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Ping.


https://reviews.llvm.org/D49375



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D49376: [NEON] Define half-precision vrnd intrinsics only when available

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Ping.


https://reviews.llvm.org/D49376



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Ping.


https://reviews.llvm.org/D49075



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D48829: [NEON] Fix support for vrndi_f32(), vrndiq_f32() and vrndns_f32() intrinsics

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Ping.


https://reviews.llvm.org/D48829



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D49376: [NEON] Define half-precision vrnd intrinsics only when available

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added reviewers: SjoerdMeijer, jgreenhalgh, rengolin.
kosarev added a project: clang.
Herald added a reviewer: javed.absar.

https://reviews.llvm.org/D49376

Files:
  include/clang/Basic/arm_neon.td
  test/Sema/arm-no-fp16.c


Index: test/Sema/arm-no-fp16.c
===
--- test/Sema/arm-no-fp16.c
+++ test/Sema/arm-no-fp16.c
@@ -9,3 +9,59 @@
 float32x4_t test_vcvt_f32_f16(float16x4_t a) {
   return vcvt_f32_f16(a); // expected-warning{{implicit declaration of 
function 'vcvt_f32_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float32x4_t'}}
 }
+
+float16x4_t test_vrnda_f16(float16x4_t a) {
+  return vrnda_f16(a); // expected-warning{{implicit declaration of function 
'vrnda_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x4_t'}}
+}
+
+float16x8_t test_vrndaq_f16(float16x8_t a) {
+  return vrndaq_f16(a); // expected-warning{{implicit declaration of function 
'vrndaq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vrnd_f16(float16x4_t a) {
+  return vrnd_f16(a); // expected-warning{{implicit declaration of function 
'vrnd_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x4_t'}}
+}
+
+float16x8_t test_vrndq_f16(float16x8_t a) {
+  return vrndq_f16(a); // expected-warning{{implicit declaration of function 
'vrndq_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x8_t'}}
+}
+
+float16x4_t test_vrndi_f16(float16x4_t a) {
+  return vrndi_f16(a); // expected-warning{{implicit declaration of function 
'vrndi_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x4_t'}}
+}
+
+float16x8_t test_vrndiq_f16(float16x8_t a) {
+  return vrndiq_f16(a); // expected-warning{{implicit declaration of function 
'vrndiq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vrndm_f16(float16x4_t a) {
+  return vrndm_f16(a); // expected-warning{{implicit declaration of function 
'vrndm_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x4_t'}}
+}
+
+float16x8_t test_vrndmq_f16(float16x8_t a) {
+  return vrndmq_f16(a); // expected-warning{{implicit declaration of function 
'vrndmq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vrndn_f16(float16x4_t a) {
+  return vrndn_f16(a); // expected-warning{{implicit declaration of function 
'vrndn_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x4_t'}}
+}
+
+float16x8_t test_vrndnq_f16(float16x8_t a) {
+  return vrndnq_f16(a); // expected-warning{{implicit declaration of function 
'vrndnq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vrndp_f16(float16x4_t a) {
+  return vrndp_f16(a); // expected-warning{{implicit declaration of function 
'vrndp_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x4_t'}}
+}
+
+float16x8_t test_vrndpq_f16(float16x8_t a) {
+  return vrndpq_f16(a); // expected-warning{{implicit declaration of function 
'vrndpq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vrndx_f16(float16x4_t a) {
+  return vrndx_f16(a); // expected-warning{{implicit declaration of function 
'vrndx_f16'}} expected-error{{returning 'int' from a function with incompatible 
result type 'float16x4_t'}}
+}
+
+float16x8_t test_vrndxq_f16(float16x8_t a) {
+  return vrndxq_f16(a); // expected-warning{{implicit declaration of function 
'vrndxq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
+}
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -1416,12 +1416,14 @@
   def VCVTP_U16: SInst<"vcvtp_u16", "ud", "hQh">;
 
   // Vector rounding
-  def FRINTZH  : SInst<"vrnd",  "dd", "hQh">;
-  def FRINTNH  : SInst<"vrndn", "dd", "hQh">;
-  def FRINTAH  : SInst<"vrnda", "dd", "hQh">;
-  def FRINTPH  : SInst<"vrndp", "dd", "hQh">;
-  def FRINTMH  : SInst<"vrndm", "dd", "hQh">;
-  def FRINTXH  : SInst<"vrndx", "dd", "hQh">;
+  let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING) 
&& defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
+def FRINTZH  : SInst<"vrnd",  "dd", "hQh">;
+def FRINTNH  : SInst<"vrndn", "dd", "hQh">;
+def FRINTAH  : SInst<"vrnda", "dd", "hQh">;
+def FRINTPH  : SInst<"vrndp", "dd", "hQh">;
+def FRINTMH  : 

[PATCH] D49375: [NEON] Define half-precision vmaxnm intrinsics only when available

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added reviewers: SjoerdMeijer, jgreenhalgh, rengolin.
kosarev added a project: clang.
Herald added a reviewer: javed.absar.

https://reviews.llvm.org/D49375

Files:
  include/clang/Basic/arm_neon.td
  test/Sema/arm-no-fp16.c


Index: test/Sema/arm-no-fp16.c
===
--- test/Sema/arm-no-fp16.c
+++ test/Sema/arm-no-fp16.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -triple thumbv7-none-eabi %s -target-feature +neon 
-target-feature -fp16 -fsyntax-only -verify
+// RUN: %clang_cc1 -triple thumbv7-none-eabi %s -target-feature +neon \
+// RUN:   -fallow-half-arguments-and-returns -target-feature -fp16 \
+// RUN:   -fsyntax-only -verify
 
 #include 
 
@@ -9,3 +11,19 @@
 float32x4_t test_vcvt_f32_f16(float16x4_t a) {
   return vcvt_f32_f16(a); // expected-warning{{implicit declaration of 
function 'vcvt_f32_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float32x4_t'}}
 }
+
+float16x4_t test_vmaxnm_f16(float16x4_t a, float16x4_t b) {
+  return vmaxnm_f16(a, b); // expected-warning{{implicit declaration of 
function 'vmaxnm_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vmaxnmq_f16(float16x8_t a, float16x8_t b) {
+  return vmaxnmq_f16(a, b); // expected-warning{{implicit declaration of 
function 'vmaxnmq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vminnm_f16(float16x4_t a, float16x4_t b) {
+  return vminnm_f16(a, b); // expected-warning{{implicit declaration of 
function 'vminnm_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vminnmq_f16(float16x8_t a, float16x8_t b) {
+  return vminnmq_f16(a, b); // expected-warning{{implicit declaration of 
function 'vminnmq_f16'}} expected-error{{returning 'int' from a function with 
incompatible result type 'float16x8_t'}}
+}
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -1463,8 +1463,10 @@
   // Max/Min
   def VMAXH : SInst<"vmax", "ddd", "hQh">;
   def VMINH : SInst<"vmin", "ddd", "hQh">;
-  def FMAXNMH   : SInst<"vmaxnm", "ddd", "hQh">;
-  def FMINNMH   : SInst<"vminnm", "ddd", "hQh">;
+  let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN) && 
defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in {
+def FMAXNMH   : SInst<"vmaxnm", "ddd", "hQh">;
+def FMINNMH   : SInst<"vminnm", "ddd", "hQh">;
+  }
 
   // Multiplication/Division
   def VMULH : SOpInst<"vmul", "ddd", "hQh", OP_MUL>;


Index: test/Sema/arm-no-fp16.c
===
--- test/Sema/arm-no-fp16.c
+++ test/Sema/arm-no-fp16.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -triple thumbv7-none-eabi %s -target-feature +neon -target-feature -fp16 -fsyntax-only -verify
+// RUN: %clang_cc1 -triple thumbv7-none-eabi %s -target-feature +neon \
+// RUN:   -fallow-half-arguments-and-returns -target-feature -fp16 \
+// RUN:   -fsyntax-only -verify
 
 #include 
 
@@ -9,3 +11,19 @@
 float32x4_t test_vcvt_f32_f16(float16x4_t a) {
   return vcvt_f32_f16(a); // expected-warning{{implicit declaration of function 'vcvt_f32_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float32x4_t'}}
 }
+
+float16x4_t test_vmaxnm_f16(float16x4_t a, float16x4_t b) {
+  return vmaxnm_f16(a, b); // expected-warning{{implicit declaration of function 'vmaxnm_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vmaxnmq_f16(float16x8_t a, float16x8_t b) {
+  return vmaxnmq_f16(a, b); // expected-warning{{implicit declaration of function 'vmaxnmq_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
+
+float16x4_t test_vminnm_f16(float16x4_t a, float16x4_t b) {
+  return vminnm_f16(a, b); // expected-warning{{implicit declaration of function 'vminnm_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x4_t'}}
+}
+
+float16x8_t test_vminnmq_f16(float16x8_t a, float16x8_t b) {
+  return vminnmq_f16(a, b); // expected-warning{{implicit declaration of function 'vminnmq_f16'}} expected-error{{returning 'int' from a function with incompatible result type 'float16x8_t'}}
+}
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -1463,8 +1463,10 @@
   // Max/Min
   def VMAXH : SInst<"vmax", "ddd", "hQh">;
   def VMINH : SInst<"vmin", "ddd", "hQh">;
-  def FMAXNMH   : SInst<"vmaxnm", "ddd", "hQh">;
-  def FMINNMH   : 

[PATCH] D48829: [NEON] Fix support for vrndi_f32(), vrndiq_f32() and vrndns_f32() intrinsics

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Ping.


https://reviews.llvm.org/D48829



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D49075: [NEON] Define fp16 vld and vst intrinsics conditionally

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added reviewers: SjoerdMeijer, jgreenhalgh, rengolin.
kosarev added a project: clang.
Herald added a reviewer: javed.absar.

This patch fixes definitions of vld and vst NEON intrinsics so that we only 
define them if half-precision arithmetic is supported on the target platform, 
as prescribed in ACLE 2.0.


https://reviews.llvm.org/D49075

Files:
  include/clang/Basic/arm_neon.td
  test/CodeGen/arm-neon-vld.c
  test/CodeGen/arm-neon-vst.c

Index: test/CodeGen/arm-neon-vst.c
===
--- test/CodeGen/arm-neon-vst.c
+++ test/CodeGen/arm-neon-vst.c
@@ -2,8 +2,8 @@
 // RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
 // RUN: FileCheck -check-prefixes=CHECK,CHECK-A64 %s
 // RUN: %clang_cc1 -triple armv8-none-linux-gnueabi -target-feature +neon \
-// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
-// RUN: FileCheck -check-prefixes=CHECK,CHECK-A32 %s
+// RUN: -target-feature +fp16 -S -disable-O0-optnone -emit-llvm -o - %s | \
+// RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A32 %s
 
 #include 
 
Index: test/CodeGen/arm-neon-vld.c
===
--- test/CodeGen/arm-neon-vld.c
+++ test/CodeGen/arm-neon-vld.c
@@ -2,8 +2,8 @@
 // RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
 // RUN: FileCheck -check-prefixes=CHECK,CHECK-A64 %s
 // RUN: %clang_cc1 -triple armv8-none-linux-gnueabi -target-feature +neon \
-// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \
-// RUN: FileCheck -check-prefixes=CHECK,CHECK-A32 %s
+// RUN: -target-feature +fp16 -S -disable-O0-optnone -emit-llvm -o - %s | \
+// RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A32 %s
 
 #include 
 
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -337,48 +337,78 @@
 
 // E.3.14 Loads and stores of a single vector
 def VLD1  : WInst<"vld1", "dc",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VLD1_X2   : WInst<"vld1_x2", "2c",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VLD1_X3   : WInst<"vld1_x3", "3c",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VLD1_X4   : WInst<"vld1_x4", "4c",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VLD1_LANE : WInst<"vld1_lane", "dcdi",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VLD1_DUP  : WInst<"vld1_dup", "dc",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VST1  : WInst<"vst1", "vpd",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
 def VST1_X2   : WInst<"vst1_x2", "vp2",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VST1_X3   : WInst<"vst1_x3", "vp3",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VST1_X4   : WInst<"vst1_x4", "vp4",
-  "cfhilsUcUiUlUsQcQfQhQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
+  "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">;
 def VST1_LANE : WInst<"vst1_lane", "vpdi",
-  "QUcQUsQUiQUlQcQsQiQlQhQfQPcQPsUcUsUiUlcsilhfPcPs">;
+  "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">;
+let ArchGuard = "(__ARM_FP & 2)" in {
+def VLD1_F16  : WInst<"vld1", "dc", "hQh">;
+def VLD1_X2_F16   : WInst<"vld1_x2", "2c", "hQh">;
+def VLD1_X3_F16   : WInst<"vld1_x3", "3c", "hQh">;
+def VLD1_X4_F16   : WInst<"vld1_x4", "4c", "hQh">;
+def VLD1_LANE_F16 : WInst<"vld1_lane", "dcdi", "hQh">;
+def VLD1_DUP_F16  : WInst<"vld1_dup", "dc", "hQh">;
+def VST1_F16  : WInst<"vst1", "vpd", "hQh">;
+def VST1_X2_F16   : WInst<"vst1_x2", "vp2", "hQh">;
+def VST1_X3_F16   : WInst<"vst1_x3", "vp3", "hQh">;
+def VST1_X4_F16   : WInst<"vst1_x4", "vp4", "hQh">;
+def VST1_LANE_F16 : WInst<"vst1_lane", "vpdi", "hQh">;
+}
 
 

[PATCH] D48829: [NEON] Fix support for vrndi_f32(), vrndiq_f32() and vrndns_f32() intrinsics

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added reviewers: SjoerdMeijer, jgreenhalgh, rengolin.
kosarev added a project: clang.
Herald added a reviewer: javed.absar.
Herald added a subscriber: kristof.beyls.

This patch adds support for vrndi_f32() and vrndiq_f32() intrinsics in AArch32 
mode and for vrndns_f32() intrinsic in AArch64 mode.


https://reviews.llvm.org/D48829

Files:
  include/clang/Basic/arm_neon.td
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGen/aarch64-neon-misc.c
  test/CodeGen/arm-neon-directed-rounding.c
  test/CodeGen/arm64-vrnd.c

Index: test/CodeGen/arm64-vrnd.c
===
--- test/CodeGen/arm64-vrnd.c
+++ test/CodeGen/arm64-vrnd.c
@@ -2,50 +2,21 @@
 
 #include 
 
-int32x2_t rnd1(float32x2_t a) { return vrnd_f32(a); }
-// CHECK: call <2 x float> @llvm.trunc.v2f32(<2 x float>
-int32x4_t rnd3(float32x4_t a) { return vrndq_f32(a); }
-// CHECK: call <4 x float> @llvm.trunc.v4f32(<4 x float>
 int64x2_t rnd5(float64x2_t a) { return vrndq_f64(a); }
 // CHECK: call <2 x double> @llvm.trunc.v2f64(<2 x double>
 
-
-int32x2_t rnd7(float32x2_t a) { return vrndn_f32(a); }
-// CHECK: call <2 x float> @llvm.aarch64.neon.frintn.v2f32(<2 x float>
-int32x4_t rnd8(float32x4_t a) { return vrndnq_f32(a); }
-// CHECK: call <4 x float> @llvm.aarch64.neon.frintn.v4f32(<4 x float>
-int64x2_t rnd9(float64x2_t a) { return vrndnq_f64(a); }
-// CHECK: call <2 x double> @llvm.aarch64.neon.frintn.v2f64(<2 x double>
-int64x2_t rnd10(float64x2_t a) { return vrndnq_f64(a); }
+int64x2_t rnd9(float64x2_t a) { return vrndnq_f64(a); }
 // CHECK: call <2 x double> @llvm.aarch64.neon.frintn.v2f64(<2 x double>
 
-int32x2_t rnd11(float32x2_t a) { return vrndm_f32(a); }
-// CHECK: call <2 x float> @llvm.floor.v2f32(<2 x float>
-int32x4_t rnd12(float32x4_t a) { return vrndmq_f32(a); }
-// CHECK: call <4 x float> @llvm.floor.v4f32(<4 x float>
 int64x2_t rnd13(float64x2_t a) { return vrndmq_f64(a); }
 // CHECK: call <2 x double> @llvm.floor.v2f64(<2 x double>
-int64x2_t rnd14(float64x2_t a) { return vrndmq_f64(a); }
-// CHECK: call <2 x double> @llvm.floor.v2f64(<2 x double>
 
-int32x2_t rnd15(float32x2_t a) { return vrndp_f32(a); }
-// CHECK: call <2 x float> @llvm.ceil.v2f32(<2 x float>
-int32x4_t rnd16(float32x4_t a) { return vrndpq_f32(a); }
-// CHECK: call <4 x float> @llvm.ceil.v4f32(<4 x float>
 int64x2_t rnd18(float64x2_t a) { return vrndpq_f64(a); }
 // CHECK: call <2 x double> @llvm.ceil.v2f64(<2 x double>
 
-int32x2_t rnd19(float32x2_t a) { return vrnda_f32(a); }
-// CHECK: call <2 x float> @llvm.round.v2f32(<2 x float>
-int32x4_t rnd20(float32x4_t a) { return vrndaq_f32(a); }
-// CHECK: call <4 x float> @llvm.round.v4f32(<4 x float>
 int64x2_t rnd22(float64x2_t a) { return vrndaq_f64(a); }
 // CHECK: call <2 x double> @llvm.round.v2f64(<2 x double>
 
-int32x2_t rnd23(float32x2_t a) { return vrndx_f32(a); }
-// CHECK: call <2 x float> @llvm.rint.v2f32(<2 x float>
-int32x4_t rnd24(float32x4_t a) { return vrndxq_f32(a); }
-// CHECK: call <4 x float> @llvm.rint.v4f32(<4 x float>
 int64x2_t rnd25(float64x2_t a) { return vrndxq_f64(a); }
 // CHECK: call <2 x double> @llvm.rint.v2f64(<2 x double>
 
Index: test/CodeGen/arm-neon-directed-rounding.c
===
--- test/CodeGen/arm-neon-directed-rounding.c
+++ test/CodeGen/arm-neon-directed-rounding.c
@@ -1,96 +1,128 @@
 // RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 \
 // RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
-// RUN: opt -S -mem2reg | FileCheck %s
+// RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A32 %s
+// RUN: %clang_cc1 -triple arm64-linux-gnueabihf -target-feature +neon \
+// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
+// RUN: opt -S -mem2reg | FileCheck -check-prefixes=CHECK,CHECK-A64 %s
 
 #include 
 
-// CHECK-LABEL: define <2 x float> @test_vrnda_f32(<2 x float> %a) #0 {
-// CHECK:   [[VRNDA_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrinta.v2f32(<2 x float> %a) #2
-// CHECK:   ret <2 x float> [[VRNDA_V1_I]]
+// CHECK-LABEL: define <2 x float> @test_vrnda_f32(<2 x float> %a)
+// CHECK-A32: [[VRNDA_V1_I:%.*]] = call <2 x float> @llvm.arm.neon.vrinta.v2f32(<2 x float> %a)
+// CHECK-A64: [[VRNDA_V1_I:%.*]] = call <2 x float> @llvm.round.v2f32(<2 x float> %a)
+// CHECK: ret <2 x float> [[VRNDA_V1_I]]
 float32x2_t test_vrnda_f32(float32x2_t a) {
   return vrnda_f32(a);
 }
 
-// CHECK-LABEL: define <4 x float> @test_vrndaq_f32(<4 x float> %a) #0 {
-// CHECK:   [[VRNDAQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrinta.v4f32(<4 x float> %a) #2
-// CHECK:   ret <4 x float> [[VRNDAQ_V1_I]]
+// CHECK-LABEL: define <4 x float> @test_vrndaq_f32(<4 x float> %a)
+// CHECK-A32: [[VRNDAQ_V1_I:%.*]] = call <4 x float> @llvm.arm.neon.vrinta.v4f32(<4 x float> %a)
+// CHECK-A64: [[VRNDAQ_V1_I:%.*]] = call <4 x float> @llvm.round.v4f32(<4 x float> %a)
+// CHECK: ret <4 x 

[PATCH] D48440: [NEON] Support vldNq intrinsics in AArch32 (Clang part)

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Yep, this patch removes `vld_dup.c` as it duplicates part of what we have in 
`arm-neon-vld.c`. Clicking 'Show File Contents' below the file displays its 
contents. Thanks for reviewing!


https://reviews.llvm.org/D48440



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D48440: [NEON] Support vldNq intrinsics in AArch32 (Clang part)

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Ping.


https://reviews.llvm.org/D48440



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D47446: [NEON] Support VST1xN intrinsics in AArch32 mode (Clang part)

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Ping.


https://reviews.llvm.org/D47446



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D47121: [NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL333819: [NEON] Support VLD1xN intrinsics in AArch32 mode 
(Clang part) (authored by kosarev, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D47121?vs=147718=149612#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D47121

Files:
  llvm/trunk/include/llvm/IR/IntrinsicsARM.td
  llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
  llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
  llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
  llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
  llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
  llvm/trunk/test/CodeGen/ARM/arm-vld1.ll

Index: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
===
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -1761,9 +1761,7 @@
   case MVT::v4f32:
   case MVT::v4i32: OpcodeIndex = 2; break;
   case MVT::v2f64:
-  case MVT::v2i64: OpcodeIndex = 3;
-assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
-break;
+  case MVT::v2i64: OpcodeIndex = 3; break;
   }
 
   EVT ResTy;
@@ -3441,6 +3439,51 @@
   return;
 }
 
+case Intrinsic::arm_neon_vld1x2: {
+  static const uint16_t DOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
+   ARM::VLD1q32, ARM::VLD1q64 };
+  static const uint16_t QOpcodes[] = { ARM::VLD1d8QPseudo,
+   ARM::VLD1d16QPseudo,
+   ARM::VLD1d32QPseudo,
+   ARM::VLD1d64QPseudo };
+  SelectVLD(N, false, 2, DOpcodes, QOpcodes, nullptr);
+  return;
+}
+
+case Intrinsic::arm_neon_vld1x3: {
+  static const uint16_t DOpcodes[] = { ARM::VLD1d8TPseudo,
+   ARM::VLD1d16TPseudo,
+   ARM::VLD1d32TPseudo,
+   ARM::VLD1d64TPseudo };
+  static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowTPseudo_UPD,
+ARM::VLD1q16LowTPseudo_UPD,
+ARM::VLD1q32LowTPseudo_UPD,
+ARM::VLD1q64LowTPseudo_UPD };
+  static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighTPseudo,
+ARM::VLD1q16HighTPseudo,
+ARM::VLD1q32HighTPseudo,
+ARM::VLD1q64HighTPseudo };
+  SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
+  return;
+}
+
+case Intrinsic::arm_neon_vld1x4: {
+  static const uint16_t DOpcodes[] = { ARM::VLD1d8QPseudo,
+   ARM::VLD1d16QPseudo,
+   ARM::VLD1d32QPseudo,
+   ARM::VLD1d64QPseudo };
+  static const uint16_t QOpcodes0[] = { ARM::VLD1q8LowQPseudo_UPD,
+ARM::VLD1q16LowQPseudo_UPD,
+ARM::VLD1q32LowQPseudo_UPD,
+ARM::VLD1q64LowQPseudo_UPD };
+  static const uint16_t QOpcodes1[] = { ARM::VLD1q8HighQPseudo,
+ARM::VLD1q16HighQPseudo,
+ARM::VLD1q32HighQPseudo,
+ARM::VLD1q64HighQPseudo };
+  SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
+  return;
+}
+
 case Intrinsic::arm_neon_vld2: {
   static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
ARM::VLD2d32, ARM::VLD1q64 };
Index: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
===
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
@@ -12763,6 +12763,9 @@
   case ISD::INTRINSIC_W_CHAIN:
 switch (cast(N->getOperand(1))->getZExtValue()) {
 case Intrinsic::arm_neon_vld1:
+case Intrinsic::arm_neon_vld1x2:
+case Intrinsic::arm_neon_vld1x3:
+case Intrinsic::arm_neon_vld1x4:
 case Intrinsic::arm_neon_vld2:
 case Intrinsic::arm_neon_vld3:
 case Intrinsic::arm_neon_vld4:
@@ -14074,6 +14077,21 @@
 Info.flags = MachineMemOperand::MOLoad;
 return true;
   }
+  case Intrinsic::arm_neon_vld1x2:
+  case Intrinsic::arm_neon_vld1x3:
+  case Intrinsic::arm_neon_vld1x4: {
+Info.opc = ISD::INTRINSIC_W_CHAIN;
+// Conservatively set memVT to the entire set of vectors loaded.
+auto  = I.getCalledFunction()->getParent()->getDataLayout();
+uint64_t NumElts = DL.getTypeSizeInBits(I.getType()) / 64;
+Info.memVT = 

[PATCH] D47121: [NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Thanks for reviewing.




Comment at: lib/CodeGen/CGBuiltin.cpp:7865
   }
 // FIXME: Sharing loads & stores with 32-bit is complicated by the absence
 // of an Align parameter here.

SjoerdMeijer wrote:
> How about this FIXME? Is it still relevant? And does it need to be moved up? 
> Or perhaps better: move the code back here to minimise the diff?
Yes, it's still true for the vst builtins handled below. None of the vld/vst 
patches removes this comment, but it should go away with whatever is the one to 
be committed last.

Umm, it seems leaving the vld code here wouldn't make the diff smaller?



Comment at: test/CodeGen/arm-neon-vld.c:4
+// RUN: FileCheck -check-prefixes=CHECK,CHECK-A64 %s
+// RUN: %clang_cc1 -triple armv8-none-linux-gnueabi -target-feature +neon \
+// RUN: -S -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | \

SjoerdMeijer wrote:
> Should this be armv7?
There are more ARMv8 vld intrinsics that we currently support only in A64 so I 
was going to add tests for them here. I'm not sure if we want to test 
availability of NEON intrinsics for various architectures with codegen tests 
like this one or have some separate tests in sema.


https://reviews.llvm.org/D47121



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D47121: [NEON] Support VLD1xN intrinsics in AArch32 mode (Clang part)

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Ping.


https://reviews.llvm.org/D47121



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Thanks Sjoerd and James. Just added a comment referring to this revision in 
https://reviews.llvm.org/rL330420.


Repository:
  rL LLVM

https://reviews.llvm.org/D45668



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D45670: [NEON] Define vfma_n_f32() and vfmaq_n_f32() intrinsics in AArch32 mode

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL330336: [NEON] Define vfma_n_f32() and vfmaq_n_f32() 
intrinsics in AArch32 mode (authored by kosarev, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D45670?vs=142784=143099#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D45670

Files:
  cfe/trunk/include/clang/Basic/arm_neon.td
  cfe/trunk/test/CodeGen/arm-neon-fma.c


Index: cfe/trunk/include/clang/Basic/arm_neon.td
===
--- cfe/trunk/include/clang/Basic/arm_neon.td
+++ cfe/trunk/include/clang/Basic/arm_neon.td
@@ -531,6 +531,7 @@
 let ArchGuard = "defined(__ARM_FEATURE_FMA)" in {
   def VFMA : SInst<"vfma", "", "fQf">;
   def VFMS : SOpInst<"vfms", "", "fQf", OP_FMLS>;
+  def FMLA_N_F32 : SOpInst<"vfma_n", "ddds", "fQf", OP_FMLA_N>;
 }
 
 

@@ -621,7 +622,7 @@
 // MUL, MLA, MLS, FMA, FMS definitions with scalar argument
 def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>;
 
-def FMLA_N : SOpInst<"vfma_n", "ddds", "fdQfQd", OP_FMLA_N>;
+def FMLA_N : SOpInst<"vfma_n", "ddds", "dQd", OP_FMLA_N>;
 def FMLS_N : SOpInst<"vfms_n", "ddds", "fdQfQd", OP_FMLS_N>;
 
 def MLA_N : SOpInst<"vmla_n", "ddds", "Qd", OP_MLA_N>;
Index: cfe/trunk/test/CodeGen/arm-neon-fma.c
===
--- cfe/trunk/test/CodeGen/arm-neon-fma.c
+++ cfe/trunk/test/CodeGen/arm-neon-fma.c
@@ -20,3 +20,27 @@
 float32x4_t test_fmaq_order(float32x4_t accum, float32x4_t lhs, float32x4_t 
rhs) {
   return vfmaq_f32(accum, lhs, rhs);
 }
+
+// CHECK-LABEL: define <2 x float> @test_vfma_n_f32(<2 x float> %a, <2 x 
float> %b, float %n) #0 {
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %n, i32 0
+// CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], 
float %n, i32 1
+// CHECK:   [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <2 x float> [[VECINIT1_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> %b, <2 
x float> [[VECINIT1_I]], <2 x float> %a)
+// CHECK:   ret <2 x float> [[TMP3]]
+float32x2_t test_vfma_n_f32(float32x2_t a, float32x2_t b, float32_t n) {
+  return vfma_n_f32(a, b, n);
+}
+
+// CHECK-LABEL: define <4 x float> @test_vfmaq_n_f32(<4 x float> %a, <4 x 
float> %b, float %n) #0 {
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
+// CHECK:   [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], 
float %n, i32 1
+// CHECK:   [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], 
float %n, i32 2
+// CHECK:   [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], 
float %n, i32 3
+// CHECK:   [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <4 x float> [[VECINIT3_I]] to <16 x i8>
+// CHECK:   [[TMP3:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 
x float> [[VECINIT3_I]], <4 x float> %a)
+// CHECK:   ret <4 x float> [[TMP3]]
+float32x4_t test_vfmaq_n_f32(float32x4_t a, float32x4_t b, float32_t n) {
+  return vfmaq_n_f32(a, b, n);
+}


Index: cfe/trunk/include/clang/Basic/arm_neon.td
===
--- cfe/trunk/include/clang/Basic/arm_neon.td
+++ cfe/trunk/include/clang/Basic/arm_neon.td
@@ -531,6 +531,7 @@
 let ArchGuard = "defined(__ARM_FEATURE_FMA)" in {
   def VFMA : SInst<"vfma", "", "fQf">;
   def VFMS : SOpInst<"vfms", "", "fQf", OP_FMLS>;
+  def FMLA_N_F32 : SOpInst<"vfma_n", "ddds", "fQf", OP_FMLA_N>;
 }
 
 
@@ -621,7 +622,7 @@
 // MUL, MLA, MLS, FMA, FMS definitions with scalar argument
 def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>;
 
-def FMLA_N : SOpInst<"vfma_n", "ddds", "fdQfQd", OP_FMLA_N>;
+def FMLA_N : SOpInst<"vfma_n", "ddds", "dQd", OP_FMLA_N>;
 def FMLS_N : SOpInst<"vfms_n", "ddds", "fdQfQd", OP_FMLS_N>;
 
 def MLA_N : SOpInst<"vmla_n", "ddds", "Qd", OP_MLA_N>;
Index: cfe/trunk/test/CodeGen/arm-neon-fma.c
===
--- cfe/trunk/test/CodeGen/arm-neon-fma.c
+++ cfe/trunk/test/CodeGen/arm-neon-fma.c
@@ -20,3 +20,27 @@
 float32x4_t test_fmaq_order(float32x4_t accum, float32x4_t lhs, float32x4_t rhs) {
   return vfmaq_f32(accum, lhs, rhs);
 }
+
+// CHECK-LABEL: define <2 x float> @test_vfma_n_f32(<2 x float> %a, <2 x float> %b, float %n) #0 {
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %n, i32 0
+// CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %n, i32 1
+// CHECK:   [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <2 x float> [[VECINIT1_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = 

[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Sure, will do. Should we treat these intrinsics as ARMv8 or ARMv7/v8? Also, 
would you mind if I commit a comment under this differential revision 
explaining the situation?


Repository:
  rL LLVM

https://reviews.llvm.org/D45668



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL330195: [NEON] Define vget_high_f16() and vget_low_f16() 
intrinsics in AArch64 mode only (authored by kosarev, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D45668?vs=142558=142789#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D45668

Files:
  cfe/trunk/include/clang/Basic/arm_neon.td
  cfe/trunk/test/CodeGen/arm_neon_intrinsics.c


Index: cfe/trunk/include/clang/Basic/arm_neon.td
===
--- cfe/trunk/include/clang/Basic/arm_neon.td
+++ cfe/trunk/include/clang/Basic/arm_neon.td
@@ -398,8 +398,14 @@
 

 // E.3.21 Splitting vectors
 let InstName = "vmov" in {
-def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>;
-def VGET_LOW  : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>;
+def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilfUcUsUiUlPcPs", OP_HI>;
+def VGET_LOW  : NoTestOpInst<"vget_low", "dk", "csilfUcUsUiUlPcPs", OP_LO>;
+}
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)" in {
+  let InstName = "vmov" in {
+  def VGET_HIGH_F16 : NoTestOpInst<"vget_high", "dk", "h", OP_HI>;
+  def VGET_LOW_F16  : NoTestOpInst<"vget_low", "dk", "h", OP_LO>;
+  }
 }
 
 

Index: cfe/trunk/test/CodeGen/arm_neon_intrinsics.c
===
--- cfe/trunk/test/CodeGen/arm_neon_intrinsics.c
+++ cfe/trunk/test/CodeGen/arm_neon_intrinsics.c
@@ -3254,13 +3254,6 @@
   return vget_high_s64(a);
 }
 
-// CHECK-LABEL: @test_vget_high_f16(
-// CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 
x i32> 
-// CHECK:   ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_high_f16(float16x8_t a) {
-  return vget_high_f16(a);
-}
-
 // CHECK-LABEL: @test_vget_high_f32(
 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, 
<2 x i32> 
 // CHECK:   ret <2 x float> [[SHUFFLE_I]]
@@ -3560,13 +3553,6 @@
   return vget_low_s64(a);
 }
 
-// CHECK-LABEL: @test_vget_low_f16(
-// CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 
x i32> 
-// CHECK:   ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_low_f16(float16x8_t a) {
-  return vget_low_f16(a);
-}
-
 // CHECK-LABEL: @test_vget_low_f32(
 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, 
<2 x i32> 
 // CHECK:   ret <2 x float> [[SHUFFLE_I]]


Index: cfe/trunk/include/clang/Basic/arm_neon.td
===
--- cfe/trunk/include/clang/Basic/arm_neon.td
+++ cfe/trunk/include/clang/Basic/arm_neon.td
@@ -398,8 +398,14 @@
 
 // E.3.21 Splitting vectors
 let InstName = "vmov" in {
-def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>;
-def VGET_LOW  : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>;
+def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilfUcUsUiUlPcPs", OP_HI>;
+def VGET_LOW  : NoTestOpInst<"vget_low", "dk", "csilfUcUsUiUlPcPs", OP_LO>;
+}
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)" in {
+  let InstName = "vmov" in {
+  def VGET_HIGH_F16 : NoTestOpInst<"vget_high", "dk", "h", OP_HI>;
+  def VGET_LOW_F16  : NoTestOpInst<"vget_low", "dk", "h", OP_LO>;
+  }
 }
 
 
Index: cfe/trunk/test/CodeGen/arm_neon_intrinsics.c
===
--- cfe/trunk/test/CodeGen/arm_neon_intrinsics.c
+++ cfe/trunk/test/CodeGen/arm_neon_intrinsics.c
@@ -3254,13 +3254,6 @@
   return vget_high_s64(a);
 }
 
-// CHECK-LABEL: @test_vget_high_f16(
-// CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 x i32> 
-// CHECK:   ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_high_f16(float16x8_t a) {
-  return vget_high_f16(a);
-}
-
 // CHECK-LABEL: @test_vget_high_f32(
 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> 
 // CHECK:   ret <2 x float> [[SHUFFLE_I]]
@@ -3560,13 +3553,6 @@
   return vget_low_s64(a);
 }
 
-// CHECK-LABEL: @test_vget_low_f16(
-// CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 x i32> 
-// CHECK:   ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_low_f16(float16x8_t a) {
-  return vget_low_f16(a);
-}
-
 // CHECK-LABEL: @test_vget_low_f32(
 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> 
 // CHECK:   ret <2 x float> [[SHUFFLE_I]]
___
cfe-commits mailing list
cfe-commits@lists.llvm.org

[PATCH] D45670: [NEON} Define vfma_n_f32() and vfmaq_n_f32() intrinsics in AArch32 mode

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 142784.
kosarev added a comment.

Removed checks for unused bitcasts. Thanks for catching!


https://reviews.llvm.org/D45670

Files:
  include/clang/Basic/arm_neon.td
  test/CodeGen/arm-neon-fma.c


Index: test/CodeGen/arm-neon-fma.c
===
--- test/CodeGen/arm-neon-fma.c
+++ test/CodeGen/arm-neon-fma.c
@@ -20,3 +20,27 @@
 float32x4_t test_fmaq_order(float32x4_t accum, float32x4_t lhs, float32x4_t 
rhs) {
   return vfmaq_f32(accum, lhs, rhs);
 }
+
+// CHECK-LABEL: define <2 x float> @test_vfma_n_f32(<2 x float> %a, <2 x 
float> %b, float %n) #0 {
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %n, i32 0
+// CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], 
float %n, i32 1
+// CHECK:   [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <2 x float> [[VECINIT1_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> %b, <2 
x float> [[VECINIT1_I]], <2 x float> %a)
+// CHECK:   ret <2 x float> [[TMP3]]
+float32x2_t test_vfma_n_f32(float32x2_t a, float32x2_t b, float32_t n) {
+  return vfma_n_f32(a, b, n);
+}
+
+// CHECK-LABEL: define <4 x float> @test_vfmaq_n_f32(<4 x float> %a, <4 x 
float> %b, float %n) #0 {
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
+// CHECK:   [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], 
float %n, i32 1
+// CHECK:   [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], 
float %n, i32 2
+// CHECK:   [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], 
float %n, i32 3
+// CHECK:   [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <4 x float> [[VECINIT3_I]] to <16 x i8>
+// CHECK:   [[TMP3:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 
x float> [[VECINIT3_I]], <4 x float> %a)
+// CHECK:   ret <4 x float> [[TMP3]]
+float32x4_t test_vfmaq_n_f32(float32x4_t a, float32x4_t b, float32_t n) {
+  return vfmaq_n_f32(a, b, n);
+}
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -531,6 +531,7 @@
 let ArchGuard = "defined(__ARM_FEATURE_FMA)" in {
   def VFMA : SInst<"vfma", "", "fQf">;
   def VFMS : SOpInst<"vfms", "", "fQf", OP_FMLS>;
+  def FMLA_N_F32 : SOpInst<"vfma_n", "ddds", "fQf", OP_FMLA_N>;
 }
 
 

@@ -621,7 +622,7 @@
 // MUL, MLA, MLS, FMA, FMS definitions with scalar argument
 def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>;
 
-def FMLA_N : SOpInst<"vfma_n", "ddds", "fdQfQd", OP_FMLA_N>;
+def FMLA_N : SOpInst<"vfma_n", "ddds", "dQd", OP_FMLA_N>;
 def FMLS_N : SOpInst<"vfms_n", "ddds", "fdQfQd", OP_FMLS_N>;
 
 def MLA_N : SOpInst<"vmla_n", "ddds", "Qd", OP_MLA_N>;


Index: test/CodeGen/arm-neon-fma.c
===
--- test/CodeGen/arm-neon-fma.c
+++ test/CodeGen/arm-neon-fma.c
@@ -20,3 +20,27 @@
 float32x4_t test_fmaq_order(float32x4_t accum, float32x4_t lhs, float32x4_t rhs) {
   return vfmaq_f32(accum, lhs, rhs);
 }
+
+// CHECK-LABEL: define <2 x float> @test_vfma_n_f32(<2 x float> %a, <2 x float> %b, float %n) #0 {
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %n, i32 0
+// CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %n, i32 1
+// CHECK:   [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <2 x float> [[VECINIT1_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> %b, <2 x float> [[VECINIT1_I]], <2 x float> %a)
+// CHECK:   ret <2 x float> [[TMP3]]
+float32x2_t test_vfma_n_f32(float32x2_t a, float32x2_t b, float32_t n) {
+  return vfma_n_f32(a, b, n);
+}
+
+// CHECK-LABEL: define <4 x float> @test_vfmaq_n_f32(<4 x float> %a, <4 x float> %b, float %n) #0 {
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
+// CHECK:   [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %n, i32 1
+// CHECK:   [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %n, i32 2
+// CHECK:   [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float %n, i32 3
+// CHECK:   [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <4 x float> [[VECINIT3_I]] to <16 x i8>
+// CHECK:   [[TMP3:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 x float> [[VECINIT3_I]], <4 x float> %a)
+// CHECK:   ret <4 x float> [[TMP3]]
+float32x4_t test_vfmaq_n_f32(float32x4_t a, float32x4_t b, float32_t n) {
+  return vfmaq_n_f32(a, b, n);
+}
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td

[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

The NEON Intrinsics Reference 
(http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0073a/index.html)
 reads like they are AArch64-only.


https://reviews.llvm.org/D45668



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D45669: [NEON] Fix the architecture condition for the crypto intrinsics

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL330187: [NEON] Fix the architecture condition for the crypto 
intrinsics (authored by kosarev, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D45669?vs=142559=142766#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D45669

Files:
  cfe/trunk/include/clang/Basic/arm_neon.td


Index: cfe/trunk/include/clang/Basic/arm_neon.td
===
--- cfe/trunk/include/clang/Basic/arm_neon.td
+++ cfe/trunk/include/clang/Basic/arm_neon.td
@@ -913,7 +913,7 @@
 
 

 // Crypto
-let ArchGuard = "__ARM_FEATURE_CRYPTO" in {
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_CRYPTO)" in {
 def AESE : SInst<"vaese", "ddd", "QUc">;
 def AESD : SInst<"vaesd", "ddd", "QUc">;
 def AESMC : SInst<"vaesmc", "dd", "QUc">;


Index: cfe/trunk/include/clang/Basic/arm_neon.td
===
--- cfe/trunk/include/clang/Basic/arm_neon.td
+++ cfe/trunk/include/clang/Basic/arm_neon.td
@@ -913,7 +913,7 @@
 
 
 // Crypto
-let ArchGuard = "__ARM_FEATURE_CRYPTO" in {
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_CRYPTO)" in {
 def AESE : SInst<"vaese", "ddd", "QUc">;
 def AESD : SInst<"vaesd", "ddd", "QUc">;
 def AESMC : SInst<"vaesmc", "dd", "QUc">;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D45669: [NEON] Fix the architecture condition for the crypto intrinsics

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC330187: [NEON] Fix the architecture condition for the crypto 
intrinsics (authored by kosarev, committed by ).

Repository:
  rL LLVM

https://reviews.llvm.org/D45669

Files:
  include/clang/Basic/arm_neon.td


Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -913,7 +913,7 @@
 
 

 // Crypto
-let ArchGuard = "__ARM_FEATURE_CRYPTO" in {
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_CRYPTO)" in {
 def AESE : SInst<"vaese", "ddd", "QUc">;
 def AESD : SInst<"vaesd", "ddd", "QUc">;
 def AESMC : SInst<"vaesmc", "dd", "QUc">;


Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -913,7 +913,7 @@
 
 
 // Crypto
-let ArchGuard = "__ARM_FEATURE_CRYPTO" in {
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_CRYPTO)" in {
 def AESE : SInst<"vaese", "ddd", "QUc">;
 def AESD : SInst<"vaesd", "ddd", "QUc">;
 def AESMC : SInst<"vaesmc", "dd", "QUc">;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D45670: [NEON} Define vfma_n_f32() and vfmaq_n_f32() intrinsics in AArch32 mode

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added reviewers: t.p.northover, rengolin, SjoerdMeijer.
kosarev added a project: clang.
Herald added subscribers: kristof.beyls, javed.absar.

Currently we only support them in AArch64 mode. The AArch64 test cases are in 
tools/clang/test/CodeGen/aarch64-neon-2velem.c.


https://reviews.llvm.org/D45670

Files:
  include/clang/Basic/arm_neon.td
  test/CodeGen/arm-neon-fma.c


Index: test/CodeGen/arm-neon-fma.c
===
--- test/CodeGen/arm-neon-fma.c
+++ test/CodeGen/arm-neon-fma.c
@@ -20,3 +20,29 @@
 float32x4_t test_fmaq_order(float32x4_t accum, float32x4_t lhs, float32x4_t 
rhs) {
   return vfmaq_f32(accum, lhs, rhs);
 }
+
+// CHECK-LABEL: define <2 x float> @test_vfma_n_f32(<2 x float> %a, <2 x 
float> %b, float %n) #0 {
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %n, i32 0
+// CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], 
float %n, i32 1
+// CHECK:   [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
+// CHECK:   [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <2 x float> [[VECINIT1_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> %b, <2 
x float> [[VECINIT1_I]], <2 x float> %a)
+// CHECK:   ret <2 x float> [[TMP3]]
+float32x2_t test_vfma_n_f32(float32x2_t a, float32x2_t b, float32_t n) {
+  return vfma_n_f32(a, b, n);
+}
+
+// CHECK-LABEL: define <4 x float> @test_vfmaq_n_f32(<4 x float> %a, <4 x 
float> %b, float %n) #0 {
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
+// CHECK:   [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], 
float %n, i32 1
+// CHECK:   [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], 
float %n, i32 2
+// CHECK:   [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], 
float %n, i32 3
+// CHECK:   [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
+// CHECK:   [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <4 x float> [[VECINIT3_I]] to <16 x i8>
+// CHECK:   [[TMP3:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> %b, <4 
x float> [[VECINIT3_I]], <4 x float> %a)
+// CHECK:   ret <4 x float> [[TMP3]]
+float32x4_t test_vfmaq_n_f32(float32x4_t a, float32x4_t b, float32_t n) {
+  return vfmaq_n_f32(a, b, n);
+}
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -531,6 +531,7 @@
 let ArchGuard = "defined(__ARM_FEATURE_FMA)" in {
   def VFMA : SInst<"vfma", "", "fQf">;
   def VFMS : SOpInst<"vfms", "", "fQf", OP_FMLS>;
+  def FMLA_N_F32 : SOpInst<"vfma_n", "ddds", "fQf", OP_FMLA_N>;
 }
 
 

@@ -621,7 +622,7 @@
 // MUL, MLA, MLS, FMA, FMS definitions with scalar argument
 def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>;
 
-def FMLA_N : SOpInst<"vfma_n", "ddds", "fdQfQd", OP_FMLA_N>;
+def FMLA_N : SOpInst<"vfma_n", "ddds", "dQd", OP_FMLA_N>;
 def FMLS_N : SOpInst<"vfms_n", "ddds", "fdQfQd", OP_FMLS_N>;
 
 def MLA_N : SOpInst<"vmla_n", "ddds", "Qd", OP_MLA_N>;


Index: test/CodeGen/arm-neon-fma.c
===
--- test/CodeGen/arm-neon-fma.c
+++ test/CodeGen/arm-neon-fma.c
@@ -20,3 +20,29 @@
 float32x4_t test_fmaq_order(float32x4_t accum, float32x4_t lhs, float32x4_t rhs) {
   return vfmaq_f32(accum, lhs, rhs);
 }
+
+// CHECK-LABEL: define <2 x float> @test_vfma_n_f32(<2 x float> %a, <2 x float> %b, float %n) #0 {
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %n, i32 0
+// CHECK:   [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %n, i32 1
+// CHECK:   [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
+// CHECK:   [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <2 x float> [[VECINIT1_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> %b, <2 x float> [[VECINIT1_I]], <2 x float> %a)
+// CHECK:   ret <2 x float> [[TMP3]]
+float32x2_t test_vfma_n_f32(float32x2_t a, float32x2_t b, float32_t n) {
+  return vfma_n_f32(a, b, n);
+}
+
+// CHECK-LABEL: define <4 x float> @test_vfmaq_n_f32(<4 x float> %a, <4 x float> %b, float %n) #0 {
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
+// CHECK:   [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %n, i32 1
+// CHECK:   [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %n, i32 2
+// CHECK:   [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float %n, i32 3
+// CHECK:   [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
+// CHECK:   [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <4 x float> 

[PATCH] D45669: [NEON] Fix the architecture condition for the crypto intrinsics

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added reviewers: t.p.northover, rengolin, SjoerdMeijer.
kosarev added a project: clang.
Herald added subscribers: kristof.beyls, javed.absar.

This is rather a cosmetic change as on ARMv7 targets we do not define 
__ARM_FEATURE_CRYPTO, even if it was explicitly requested with -target-feature. 
The crypto intrinsics test cases are in tools/clang/test/CodeGen/neon-crypto.c 
. No changes are necessary for them.


https://reviews.llvm.org/D45669

Files:
  include/clang/Basic/arm_neon.td


Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -913,7 +913,7 @@
 
 

 // Crypto
-let ArchGuard = "__ARM_FEATURE_CRYPTO" in {
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_CRYPTO)" in {
 def AESE : SInst<"vaese", "ddd", "QUc">;
 def AESD : SInst<"vaesd", "ddd", "QUc">;
 def AESMC : SInst<"vaesmc", "dd", "QUc">;


Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -913,7 +913,7 @@
 
 
 // Crypto
-let ArchGuard = "__ARM_FEATURE_CRYPTO" in {
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_CRYPTO)" in {
 def AESE : SInst<"vaese", "ddd", "QUc">;
 def AESD : SInst<"vaesd", "ddd", "QUc">;
 def AESMC : SInst<"vaesmc", "dd", "QUc">;
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D45668: [NEON] Define vget_high_f16() and vget_low_f16() intrinsics in AArch64 mode only

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added reviewers: t.p.northover, rengolin, SjoerdMeijer.
kosarev added a project: clang.
Herald added subscribers: kristof.beyls, javed.absar.

These are AArch64-specific intrinsics. The patch removes AArch32-mode test 
cases and maintains AArch64 ones in 
tools/clang/test/CodeGen/aarch64-neon-vget-hilo.c.


https://reviews.llvm.org/D45668

Files:
  include/clang/Basic/arm_neon.td
  test/CodeGen/arm_neon_intrinsics.c


Index: test/CodeGen/arm_neon_intrinsics.c
===
--- test/CodeGen/arm_neon_intrinsics.c
+++ test/CodeGen/arm_neon_intrinsics.c
@@ -3254,13 +3254,6 @@
   return vget_high_s64(a);
 }
 
-// CHECK-LABEL: @test_vget_high_f16(
-// CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 
x i32> 
-// CHECK:   ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_high_f16(float16x8_t a) {
-  return vget_high_f16(a);
-}
-
 // CHECK-LABEL: @test_vget_high_f32(
 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, 
<2 x i32> 
 // CHECK:   ret <2 x float> [[SHUFFLE_I]]
@@ -3560,13 +3553,6 @@
   return vget_low_s64(a);
 }
 
-// CHECK-LABEL: @test_vget_low_f16(
-// CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 
x i32> 
-// CHECK:   ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_low_f16(float16x8_t a) {
-  return vget_low_f16(a);
-}
-
 // CHECK-LABEL: @test_vget_low_f32(
 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, 
<2 x i32> 
 // CHECK:   ret <2 x float> [[SHUFFLE_I]]
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -398,8 +398,14 @@
 

 // E.3.21 Splitting vectors
 let InstName = "vmov" in {
-def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>;
-def VGET_LOW  : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>;
+def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilfUcUsUiUlPcPs", OP_HI>;
+def VGET_LOW  : NoTestOpInst<"vget_low", "dk", "csilfUcUsUiUlPcPs", OP_LO>;
+}
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)" in {
+  let InstName = "vmov" in {
+  def VGET_HIGH_F16 : NoTestOpInst<"vget_high", "dk", "h", OP_HI>;
+  def VGET_LOW_F16  : NoTestOpInst<"vget_low", "dk", "h", OP_LO>;
+  }
 }
 
 



Index: test/CodeGen/arm_neon_intrinsics.c
===
--- test/CodeGen/arm_neon_intrinsics.c
+++ test/CodeGen/arm_neon_intrinsics.c
@@ -3254,13 +3254,6 @@
   return vget_high_s64(a);
 }
 
-// CHECK-LABEL: @test_vget_high_f16(
-// CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 x i32> 
-// CHECK:   ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_high_f16(float16x8_t a) {
-  return vget_high_f16(a);
-}
-
 // CHECK-LABEL: @test_vget_high_f32(
 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> 
 // CHECK:   ret <2 x float> [[SHUFFLE_I]]
@@ -3560,13 +3553,6 @@
   return vget_low_s64(a);
 }
 
-// CHECK-LABEL: @test_vget_low_f16(
-// CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <8 x half> %a, <8 x half> %a, <4 x i32> 
-// CHECK:   ret <4 x half> [[SHUFFLE_I]]
-float16x4_t test_vget_low_f16(float16x8_t a) {
-  return vget_low_f16(a);
-}
-
 // CHECK-LABEL: @test_vget_low_f32(
 // CHECK:   [[SHUFFLE_I:%.*]] = shufflevector <4 x float> %a, <4 x float> %a, <2 x i32> 
 // CHECK:   ret <2 x float> [[SHUFFLE_I]]
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -398,8 +398,14 @@
 
 // E.3.21 Splitting vectors
 let InstName = "vmov" in {
-def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilhfUcUsUiUlPcPs", OP_HI>;
-def VGET_LOW  : NoTestOpInst<"vget_low", "dk", "csilhfUcUsUiUlPcPs", OP_LO>;
+def VGET_HIGH : NoTestOpInst<"vget_high", "dk", "csilfUcUsUiUlPcPs", OP_HI>;
+def VGET_LOW  : NoTestOpInst<"vget_low", "dk", "csilfUcUsUiUlPcPs", OP_LO>;
+}
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)" in {
+  let InstName = "vmov" in {
+  def VGET_HIGH_F16 : NoTestOpInst<"vget_high", "dk", "h", OP_HI>;
+  def VGET_LOW_F16  : NoTestOpInst<"vget_low", "dk", "h", OP_LO>;
+  }
 }
 
 
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D45515: [NEON] Support vrndns_f32 intrinsic

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC330012: [NEON] Support vrndns_f32 intrinsic (authored by 
kosarev, committed by ).

Repository:
  rC Clang

https://reviews.llvm.org/D45515

Files:
  include/clang/Basic/arm_neon.td
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGen/arm-neon-directed-rounding.c


Index: test/CodeGen/arm-neon-directed-rounding.c
===
--- test/CodeGen/arm-neon-directed-rounding.c
+++ test/CodeGen/arm-neon-directed-rounding.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 
-ffreestanding -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | 
FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 \
+// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
+// RUN: opt -S -mem2reg | FileCheck %s
 
 #include 
 
@@ -85,3 +87,10 @@
 float32x4_t test_vrndq_f32(float32x4_t a) {
   return vrndq_f32(a);
 }
+
+// CHECK-LABEL: define float @test_vrndns_f32(float %a) #0 {
+// CHECK:   [[VRNDN_I:%.*]] = call float @llvm.arm.neon.vrintn.f32(float %a) #2
+// CHECK:   ret float [[VRNDN_I]]
+float32_t test_vrndns_f32(float32_t a) {
+  return vrndns_f32(a);
+}
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -5590,6 +5590,12 @@
   case NEON::BI__builtin_neon_vgetq_lane_f32:
 return Builder.CreateExtractElement(Ops[0], Ops[1], "vget_lane");
 
+  case NEON::BI__builtin_neon_vrndns_f32: {
+Value *Arg = EmitScalarExpr(E->getArg(0));
+llvm::Type *Tys[] = {Arg->getType()};
+Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vrintn, Tys);
+return Builder.CreateCall(F, {Arg}, "vrndn"); }
+
   case NEON::BI__builtin_neon_vset_lane_i8:
   case NEON::BI__builtin_neon_vset_lane_i16:
   case NEON::BI__builtin_neon_vset_lane_i32:
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -1116,6 +1116,12 @@
 }
 
 

+// Scalar Floating-point Round to Integral
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" 
in {
+def SCALAR_FRINTN_S32 : SInst<"vrndn", "ss", "Sf">;
+}
+
+
 // Scalar Reduce Pairwise Addition (Scalar and Floating Point)
 def SCALAR_ADDP  : SInst<"vpadd", "sd", "SfSHlSHdSHUl">;
 


Index: test/CodeGen/arm-neon-directed-rounding.c
===
--- test/CodeGen/arm-neon-directed-rounding.c
+++ test/CodeGen/arm-neon-directed-rounding.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 \
+// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
+// RUN: opt -S -mem2reg | FileCheck %s
 
 #include 
 
@@ -85,3 +87,10 @@
 float32x4_t test_vrndq_f32(float32x4_t a) {
   return vrndq_f32(a);
 }
+
+// CHECK-LABEL: define float @test_vrndns_f32(float %a) #0 {
+// CHECK:   [[VRNDN_I:%.*]] = call float @llvm.arm.neon.vrintn.f32(float %a) #2
+// CHECK:   ret float [[VRNDN_I]]
+float32_t test_vrndns_f32(float32_t a) {
+  return vrndns_f32(a);
+}
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -5590,6 +5590,12 @@
   case NEON::BI__builtin_neon_vgetq_lane_f32:
 return Builder.CreateExtractElement(Ops[0], Ops[1], "vget_lane");
 
+  case NEON::BI__builtin_neon_vrndns_f32: {
+Value *Arg = EmitScalarExpr(E->getArg(0));
+llvm::Type *Tys[] = {Arg->getType()};
+Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vrintn, Tys);
+return Builder.CreateCall(F, {Arg}, "vrndn"); }
+
   case NEON::BI__builtin_neon_vset_lane_i8:
   case NEON::BI__builtin_neon_vset_lane_i16:
   case NEON::BI__builtin_neon_vset_lane_i32:
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -1116,6 +1116,12 @@
 }
 
 
+// Scalar Floating-point Round to Integral
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in {
+def SCALAR_FRINTN_S32 : SInst<"vrndn", "ss", "Sf">;
+}
+
+
 // Scalar Reduce Pairwise Addition (Scalar and Floating Point)
 def SCALAR_ADDP  : SInst<"vpadd", "sd", "SfSHlSHdSHUl">;
 

[PATCH] D45483: [NEON] Support vfma_n and vfms_n intrinsics

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL329814: [NEON] Support vfma_n and vfms_n intrinsics 
(authored by kosarev, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D45483?vs=141828=142008#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D45483

Files:
  cfe/trunk/include/clang/Basic/arm_neon.td
  cfe/trunk/test/CodeGen/aarch64-neon-2velem.c


Index: cfe/trunk/test/CodeGen/aarch64-neon-2velem.c
===
--- cfe/trunk/test/CodeGen/aarch64-neon-2velem.c
+++ cfe/trunk/test/CodeGen/aarch64-neon-2velem.c
@@ -3083,6 +3083,17 @@
   return vfma_n_f32(a, b, n);
 }
 
+// CHECK-LABEL: @test_vfma_n_f64(
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x double> undef, double %n, 
i32 0
+// CHECK:   [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
+// CHECK:   [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <1 x double> [[VECINIT_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <1 x double> @llvm.fma.v1f64(<1 x double> %b, 
<1 x double> [[VECINIT_I]], <1 x double> %a)
+// CHECK:   ret <1 x double> [[TMP3]]
+float64x1_t test_vfma_n_f64(float64x1_t a, float64x1_t b, float64_t n) {
+  return vfma_n_f64(a, b, n);
+}
+
 // CHECK-LABEL: @test_vfmaq_n_f32(
 // CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
 // CHECK:   [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], 
float %n, i32 1
@@ -3110,6 +3121,18 @@
   return vfms_n_f32(a, b, n);
 }
 
+// CHECK-LABEL: @test_vfms_n_f64(
+// CHECK:   [[SUB_I:%.*]] = fsub <1 x double> , %b
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x double> undef, double %n, 
i32 0
+// CHECK:   [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
+// CHECK:   [[TMP1:%.*]] = bitcast <1 x double> [[SUB_I]] to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <1 x double> [[VECINIT_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <1 x double> @llvm.fma.v1f64(<1 x double> 
[[SUB_I]], <1 x double> [[VECINIT_I]], <1 x double> %a)
+// CHECK:   ret <1 x double> [[TMP3]]
+float64x1_t test_vfms_n_f64(float64x1_t a, float64x1_t b, float64_t n) {
+  return vfms_n_f64(a, b, n);
+}
+
 // CHECK-LABEL: @test_vfmsq_n_f32(
 // CHECK:   [[SUB_I:%.*]] = fsub <4 x float> , %b
 // CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
Index: cfe/trunk/include/clang/Basic/arm_neon.td
===
--- cfe/trunk/include/clang/Basic/arm_neon.td
+++ cfe/trunk/include/clang/Basic/arm_neon.td
@@ -621,8 +621,8 @@
 // MUL, MLA, MLS, FMA, FMS definitions with scalar argument
 def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>;
 
-def FMLA_N : SOpInst<"vfma_n", "ddds", "fQfQd", OP_FMLA_N>;
-def FMLS_N : SOpInst<"vfms_n", "ddds", "fQfQd", OP_FMLS_N>;
+def FMLA_N : SOpInst<"vfma_n", "ddds", "fdQfQd", OP_FMLA_N>;
+def FMLS_N : SOpInst<"vfms_n", "ddds", "fdQfQd", OP_FMLS_N>;
 
 def MLA_N : SOpInst<"vmla_n", "ddds", "Qd", OP_MLA_N>;
 def MLS_N : SOpInst<"vmls_n", "ddds", "Qd", OP_MLS_N>;


Index: cfe/trunk/test/CodeGen/aarch64-neon-2velem.c
===
--- cfe/trunk/test/CodeGen/aarch64-neon-2velem.c
+++ cfe/trunk/test/CodeGen/aarch64-neon-2velem.c
@@ -3083,6 +3083,17 @@
   return vfma_n_f32(a, b, n);
 }
 
+// CHECK-LABEL: @test_vfma_n_f64(
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x double> undef, double %n, i32 0
+// CHECK:   [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
+// CHECK:   [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <1 x double> [[VECINIT_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <1 x double> @llvm.fma.v1f64(<1 x double> %b, <1 x double> [[VECINIT_I]], <1 x double> %a)
+// CHECK:   ret <1 x double> [[TMP3]]
+float64x1_t test_vfma_n_f64(float64x1_t a, float64x1_t b, float64_t n) {
+  return vfma_n_f64(a, b, n);
+}
+
 // CHECK-LABEL: @test_vfmaq_n_f32(
 // CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
 // CHECK:   [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %n, i32 1
@@ -3110,6 +3121,18 @@
   return vfms_n_f32(a, b, n);
 }
 
+// CHECK-LABEL: @test_vfms_n_f64(
+// CHECK:   [[SUB_I:%.*]] = fsub <1 x double> , %b
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x double> undef, double %n, i32 0
+// CHECK:   [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
+// CHECK:   [[TMP1:%.*]] = bitcast <1 x double> [[SUB_I]] to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <1 x double> [[VECINIT_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <1 x double> @llvm.fma.v1f64(<1 x double> [[SUB_I]], <1 x double> [[VECINIT_I]], <1 x double> %a)
+// CHECK:   ret <1 x double> [[TMP3]]
+float64x1_t test_vfms_n_f64(float64x1_t a, float64x1_t b, float64_t n) {
+  return vfms_n_f64(a, b, n);
+}
+
 // CHECK-LABEL: @test_vfmsq_n_f32(
 // 

[PATCH] D45483: [NEON] Support vfma_n and vfms_n intrinsics

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC329814: [NEON] Support vfma_n and vfms_n intrinsics 
(authored by kosarev, committed by ).

Repository:
  rL LLVM

https://reviews.llvm.org/D45483

Files:
  include/clang/Basic/arm_neon.td
  test/CodeGen/aarch64-neon-2velem.c


Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -621,8 +621,8 @@
 // MUL, MLA, MLS, FMA, FMS definitions with scalar argument
 def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>;
 
-def FMLA_N : SOpInst<"vfma_n", "ddds", "fQfQd", OP_FMLA_N>;
-def FMLS_N : SOpInst<"vfms_n", "ddds", "fQfQd", OP_FMLS_N>;
+def FMLA_N : SOpInst<"vfma_n", "ddds", "fdQfQd", OP_FMLA_N>;
+def FMLS_N : SOpInst<"vfms_n", "ddds", "fdQfQd", OP_FMLS_N>;
 
 def MLA_N : SOpInst<"vmla_n", "ddds", "Qd", OP_MLA_N>;
 def MLS_N : SOpInst<"vmls_n", "ddds", "Qd", OP_MLS_N>;
Index: test/CodeGen/aarch64-neon-2velem.c
===
--- test/CodeGen/aarch64-neon-2velem.c
+++ test/CodeGen/aarch64-neon-2velem.c
@@ -3083,6 +3083,17 @@
   return vfma_n_f32(a, b, n);
 }
 
+// CHECK-LABEL: @test_vfma_n_f64(
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x double> undef, double %n, 
i32 0
+// CHECK:   [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
+// CHECK:   [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <1 x double> [[VECINIT_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <1 x double> @llvm.fma.v1f64(<1 x double> %b, 
<1 x double> [[VECINIT_I]], <1 x double> %a)
+// CHECK:   ret <1 x double> [[TMP3]]
+float64x1_t test_vfma_n_f64(float64x1_t a, float64x1_t b, float64_t n) {
+  return vfma_n_f64(a, b, n);
+}
+
 // CHECK-LABEL: @test_vfmaq_n_f32(
 // CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
 // CHECK:   [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], 
float %n, i32 1
@@ -3110,6 +3121,18 @@
   return vfms_n_f32(a, b, n);
 }
 
+// CHECK-LABEL: @test_vfms_n_f64(
+// CHECK:   [[SUB_I:%.*]] = fsub <1 x double> , %b
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x double> undef, double %n, 
i32 0
+// CHECK:   [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
+// CHECK:   [[TMP1:%.*]] = bitcast <1 x double> [[SUB_I]] to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <1 x double> [[VECINIT_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <1 x double> @llvm.fma.v1f64(<1 x double> 
[[SUB_I]], <1 x double> [[VECINIT_I]], <1 x double> %a)
+// CHECK:   ret <1 x double> [[TMP3]]
+float64x1_t test_vfms_n_f64(float64x1_t a, float64x1_t b, float64_t n) {
+  return vfms_n_f64(a, b, n);
+}
+
 // CHECK-LABEL: @test_vfmsq_n_f32(
 // CHECK:   [[SUB_I:%.*]] = fsub <4 x float> , %b
 // CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0


Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -621,8 +621,8 @@
 // MUL, MLA, MLS, FMA, FMS definitions with scalar argument
 def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>;
 
-def FMLA_N : SOpInst<"vfma_n", "ddds", "fQfQd", OP_FMLA_N>;
-def FMLS_N : SOpInst<"vfms_n", "ddds", "fQfQd", OP_FMLS_N>;
+def FMLA_N : SOpInst<"vfma_n", "ddds", "fdQfQd", OP_FMLA_N>;
+def FMLS_N : SOpInst<"vfms_n", "ddds", "fdQfQd", OP_FMLS_N>;
 
 def MLA_N : SOpInst<"vmla_n", "ddds", "Qd", OP_MLA_N>;
 def MLS_N : SOpInst<"vmls_n", "ddds", "Qd", OP_MLS_N>;
Index: test/CodeGen/aarch64-neon-2velem.c
===
--- test/CodeGen/aarch64-neon-2velem.c
+++ test/CodeGen/aarch64-neon-2velem.c
@@ -3083,6 +3083,17 @@
   return vfma_n_f32(a, b, n);
 }
 
+// CHECK-LABEL: @test_vfma_n_f64(
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x double> undef, double %n, i32 0
+// CHECK:   [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
+// CHECK:   [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <1 x double> [[VECINIT_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <1 x double> @llvm.fma.v1f64(<1 x double> %b, <1 x double> [[VECINIT_I]], <1 x double> %a)
+// CHECK:   ret <1 x double> [[TMP3]]
+float64x1_t test_vfma_n_f64(float64x1_t a, float64x1_t b, float64_t n) {
+  return vfma_n_f64(a, b, n);
+}
+
 // CHECK-LABEL: @test_vfmaq_n_f32(
 // CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
 // CHECK:   [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %n, i32 1
@@ -3110,6 +3121,18 @@
   return vfms_n_f32(a, b, n);
 }
 
+// CHECK-LABEL: @test_vfms_n_f64(
+// CHECK:   [[SUB_I:%.*]] = fsub <1 x double> , %b
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x double> undef, double %n, i32 0
+// CHECK:   [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
+// CHECK:   

[PATCH] D45515: [NEON] Support vrndns_f32 intrinsic

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added reviewers: t.p.northover, rengolin, SjoerdMeijer.
kosarev added a project: clang.
Herald added a subscriber: javed.absar.

https://reviews.llvm.org/D45515

Files:
  include/clang/Basic/arm_neon.td
  lib/CodeGen/CGBuiltin.cpp
  test/CodeGen/arm-neon-directed-rounding.c


Index: test/CodeGen/arm-neon-directed-rounding.c
===
--- test/CodeGen/arm-neon-directed-rounding.c
+++ test/CodeGen/arm-neon-directed-rounding.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 
-ffreestanding -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | 
FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 \
+// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
+// RUN: opt -S -mem2reg | FileCheck %s
 
 #include 
 
@@ -85,3 +87,10 @@
 float32x4_t test_vrndq_f32(float32x4_t a) {
   return vrndq_f32(a);
 }
+
+// CHECK-LABEL: define float @test_vrndns_f32(float %a) #0 {
+// CHECK:   [[VRNDN_I:%.*]] = call float @llvm.arm.neon.vrintn.f32(float %a) #2
+// CHECK:   ret float [[VRNDN_I]]
+float32_t test_vrndns_f32(float32_t a) {
+  return vrndns_f32(a);
+}
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -5485,6 +5485,12 @@
   case NEON::BI__builtin_neon_vgetq_lane_f32:
 return Builder.CreateExtractElement(Ops[0], Ops[1], "vget_lane");
 
+  case NEON::BI__builtin_neon_vrndns_f32: {
+Value *Arg = EmitScalarExpr(E->getArg(0));
+llvm::Type *Tys[] = {Arg->getType()};
+Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vrintn, Tys);
+return Builder.CreateCall(F, {Arg}, "vrndn"); }
+
   case NEON::BI__builtin_neon_vset_lane_i8:
   case NEON::BI__builtin_neon_vset_lane_i16:
   case NEON::BI__builtin_neon_vset_lane_i32:
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -1116,6 +1116,12 @@
 }
 
 

+// Scalar Floating-point Round to Integral
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" 
in {
+def SCALAR_FRINTN_S32 : SInst<"vrndn", "ss", "Sf">;
+}
+
+
 // Scalar Reduce Pairwise Addition (Scalar and Floating Point)
 def SCALAR_ADDP  : SInst<"vpadd", "sd", "SfSHlSHdSHUl">;
 


Index: test/CodeGen/arm-neon-directed-rounding.c
===
--- test/CodeGen/arm-neon-directed-rounding.c
+++ test/CodeGen/arm-neon-directed-rounding.c
@@ -1,4 +1,6 @@
-// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck %s
+// RUN: %clang_cc1 -triple thumbv8-linux-gnueabihf -target-cpu cortex-a57 \
+// RUN: -ffreestanding -disable-O0-optnone -emit-llvm %s -o - | \
+// RUN: opt -S -mem2reg | FileCheck %s
 
 #include 
 
@@ -85,3 +87,10 @@
 float32x4_t test_vrndq_f32(float32x4_t a) {
   return vrndq_f32(a);
 }
+
+// CHECK-LABEL: define float @test_vrndns_f32(float %a) #0 {
+// CHECK:   [[VRNDN_I:%.*]] = call float @llvm.arm.neon.vrintn.f32(float %a) #2
+// CHECK:   ret float [[VRNDN_I]]
+float32_t test_vrndns_f32(float32_t a) {
+  return vrndns_f32(a);
+}
Index: lib/CodeGen/CGBuiltin.cpp
===
--- lib/CodeGen/CGBuiltin.cpp
+++ lib/CodeGen/CGBuiltin.cpp
@@ -5485,6 +5485,12 @@
   case NEON::BI__builtin_neon_vgetq_lane_f32:
 return Builder.CreateExtractElement(Ops[0], Ops[1], "vget_lane");
 
+  case NEON::BI__builtin_neon_vrndns_f32: {
+Value *Arg = EmitScalarExpr(E->getArg(0));
+llvm::Type *Tys[] = {Arg->getType()};
+Function *F = CGM.getIntrinsic(Intrinsic::arm_neon_vrintn, Tys);
+return Builder.CreateCall(F, {Arg}, "vrndn"); }
+
   case NEON::BI__builtin_neon_vset_lane_i8:
   case NEON::BI__builtin_neon_vset_lane_i16:
   case NEON::BI__builtin_neon_vset_lane_i32:
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -1116,6 +1116,12 @@
 }
 
 
+// Scalar Floating-point Round to Integral
+let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in {
+def SCALAR_FRINTN_S32 : SInst<"vrndn", "ss", "Sf">;
+}
+
+
 // Scalar Reduce Pairwise Addition (Scalar and Floating Point)
 def SCALAR_ADDP  : SInst<"vpadd", "sd", "SfSHlSHdSHUl">;
 

[PATCH] D45483: [NEON] Support vfma_n and vfms_n intrinsics

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added reviewers: az, sbaranga, t.p.northover.
kosarev added a project: clang.
Herald added subscribers: javed.absar, rengolin.

https://reviews.llvm.org/D45483

Files:
  include/clang/Basic/arm_neon.td
  test/CodeGen/aarch64-neon-2velem.c


Index: test/CodeGen/aarch64-neon-2velem.c
===
--- test/CodeGen/aarch64-neon-2velem.c
+++ test/CodeGen/aarch64-neon-2velem.c
@@ -3083,6 +3083,17 @@
   return vfma_n_f32(a, b, n);
 }
 
+// CHECK-LABEL: @test_vfma_n_f64(
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x double> undef, double %n, 
i32 0
+// CHECK:   [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
+// CHECK:   [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <1 x double> [[VECINIT_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <1 x double> @llvm.fma.v1f64(<1 x double> %b, 
<1 x double> [[VECINIT_I]], <1 x double> %a)
+// CHECK:   ret <1 x double> [[TMP3]]
+float64x1_t test_vfma_n_f64(float64x1_t a, float64x1_t b, float64_t n) {
+  return vfma_n_f64(a, b, n);
+}
+
 // CHECK-LABEL: @test_vfmaq_n_f32(
 // CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
 // CHECK:   [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], 
float %n, i32 1
@@ -3110,6 +3121,18 @@
   return vfms_n_f32(a, b, n);
 }
 
+// CHECK-LABEL: @test_vfms_n_f64(
+// CHECK:   [[SUB_I:%.*]] = fsub <1 x double> , %b
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x double> undef, double %n, 
i32 0
+// CHECK:   [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
+// CHECK:   [[TMP1:%.*]] = bitcast <1 x double> [[SUB_I]] to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <1 x double> [[VECINIT_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <1 x double> @llvm.fma.v1f64(<1 x double> 
[[SUB_I]], <1 x double> [[VECINIT_I]], <1 x double> %a)
+// CHECK:   ret <1 x double> [[TMP3]]
+float64x1_t test_vfms_n_f64(float64x1_t a, float64x1_t b, float64_t n) {
+  return vfms_n_f64(a, b, n);
+}
+
 // CHECK-LABEL: @test_vfmsq_n_f32(
 // CHECK:   [[SUB_I:%.*]] = fsub <4 x float> , %b
 // CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ include/clang/Basic/arm_neon.td
@@ -621,8 +621,8 @@
 // MUL, MLA, MLS, FMA, FMS definitions with scalar argument
 def VMUL_N_A64 : IOpInst<"vmul_n", "dds", "Qd", OP_MUL_N>;
 
-def FMLA_N : SOpInst<"vfma_n", "ddds", "fQfQd", OP_FMLA_N>;
-def FMLS_N : SOpInst<"vfms_n", "ddds", "fQfQd", OP_FMLS_N>;
+def FMLA_N : SOpInst<"vfma_n", "ddds", "fdQfQd", OP_FMLA_N>;
+def FMLS_N : SOpInst<"vfms_n", "ddds", "fdQfQd", OP_FMLS_N>;
 
 def MLA_N : SOpInst<"vmla_n", "ddds", "Qd", OP_MLA_N>;
 def MLS_N : SOpInst<"vmls_n", "ddds", "Qd", OP_MLS_N>;


Index: test/CodeGen/aarch64-neon-2velem.c
===
--- test/CodeGen/aarch64-neon-2velem.c
+++ test/CodeGen/aarch64-neon-2velem.c
@@ -3083,6 +3083,17 @@
   return vfma_n_f32(a, b, n);
 }
 
+// CHECK-LABEL: @test_vfma_n_f64(
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x double> undef, double %n, i32 0
+// CHECK:   [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
+// CHECK:   [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <1 x double> [[VECINIT_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <1 x double> @llvm.fma.v1f64(<1 x double> %b, <1 x double> [[VECINIT_I]], <1 x double> %a)
+// CHECK:   ret <1 x double> [[TMP3]]
+float64x1_t test_vfma_n_f64(float64x1_t a, float64x1_t b, float64_t n) {
+  return vfma_n_f64(a, b, n);
+}
+
 // CHECK-LABEL: @test_vfmaq_n_f32(
 // CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
 // CHECK:   [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %n, i32 1
@@ -3110,6 +3121,18 @@
   return vfms_n_f32(a, b, n);
 }
 
+// CHECK-LABEL: @test_vfms_n_f64(
+// CHECK:   [[SUB_I:%.*]] = fsub <1 x double> , %b
+// CHECK:   [[VECINIT_I:%.*]] = insertelement <1 x double> undef, double %n, i32 0
+// CHECK:   [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
+// CHECK:   [[TMP1:%.*]] = bitcast <1 x double> [[SUB_I]] to <8 x i8>
+// CHECK:   [[TMP2:%.*]] = bitcast <1 x double> [[VECINIT_I]] to <8 x i8>
+// CHECK:   [[TMP3:%.*]] = call <1 x double> @llvm.fma.v1f64(<1 x double> [[SUB_I]], <1 x double> [[VECINIT_I]], <1 x double> %a)
+// CHECK:   ret <1 x double> [[TMP3]]
+float64x1_t test_vfms_n_f64(float64x1_t a, float64x1_t b, float64_t n) {
+  return vfms_n_f64(a, b, n);
+}
+
 // CHECK-LABEL: @test_vfmsq_n_f32(
 // CHECK:   [[SUB_I:%.*]] = fsub <4 x float> , %b
 // CHECK:   [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %n, i32 0
Index: include/clang/Basic/arm_neon.td
===
--- include/clang/Basic/arm_neon.td
+++ 

[PATCH] D44616: Update existed CodeGen TBAA tests

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Looks fine to me.


Repository:
  rC Clang

https://reviews.llvm.org/D44616



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D42366: [CodeGen] Fix generation of TBAA tags for may-alias accesses

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

I think zero would serve better as the unknown-size value. People who are not 
aware of TBAA internals would guess that since zero-sized accesses make no 
sense, they are likely to have some special meaning. Similarly, for code that 
is supposed to process the size fields of access descriptors zero would be an 
obvious "illegal size value". In contrast, UINT64_MAX is just a very large 
number that doesn't hint anything on its special purpose.

Either way, we should reflect the convention in the documentation, 
https://reviews.llvm.org/D40975.


Repository:
  rC Clang

https://reviews.llvm.org/D42366



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D42366: [CodeGen] Fix generation of TBAA tags for may-alias accesses

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC325575: [CodeGen] Fix generation of TBAA tags for may-alias 
accesses (authored by kosarev, committed by ).

Repository:
  rC Clang

https://reviews.llvm.org/D42366

Files:
  lib/CodeGen/CodeGenModule.cpp
  lib/CodeGen/CodeGenTBAA.cpp
  lib/CodeGen/CodeGenTBAA.h
  test/CodeGen/may-alias.c

Index: test/CodeGen/may-alias.c
===
--- test/CodeGen/may-alias.c
+++ test/CodeGen/may-alias.c
@@ -1,42 +1,61 @@
-// RUN: %clang_cc1 -Werror -triple i386-unknown-unknown -emit-llvm -O1 -no-struct-path-tbaa -disable-llvm-passes -o - %s | FileCheck %s
-// RUN: %clang_cc1 -Werror -triple i386-unknown-unknown -emit-llvm -O1 -disable-llvm-passes -o - %s | FileCheck %s -check-prefix=PATH
+// RUN: %clang_cc1 -Werror -triple i386-unknown-unknown -emit-llvm -O1 \
+// RUN: -no-struct-path-tbaa -disable-llvm-passes -o - %s | \
+// RUN: FileCheck %s -check-prefixes=CHECK,SCALAR
+// RUN: %clang_cc1 -Werror -triple i386-unknown-unknown -emit-llvm -O1 \
+// RUN: -disable-llvm-passes -o - %s | \
+// RUN: FileCheck %s -check-prefixes=CHECK,OLD-PATH
+// RUN: %clang_cc1 -Werror -triple i386-unknown-unknown -emit-llvm -O1 \
+// RUN: -new-struct-path-tbaa -disable-llvm-passes -o - %s | \
+// RUN: FileCheck %s -check-prefixes=CHECK,NEW-PATH
 
 // Types with the may_alias attribute should be considered equivalent
 // to char for aliasing.
 
 typedef int __attribute__((may_alias)) aliasing_int;
 
-void test0(aliasing_int *ai, int *i)
-{
-// CHECK: store i32 0, i32* %{{.*}}, !tbaa [[TAG_CHAR:!.*]]
-// PATH: store i32 0, i32* %{{.*}}, !tbaa [[TAG_CHAR:!.*]]
+void test0(aliasing_int *ai, int *i) {
+// CHECK-LABEL: test0
+// CHECK: store i32 0, {{.*}}, !tbaa [[TAG_alias_int:!.*]]
   *ai = 0;
-// CHECK: store i32 1, i32* %{{.*}}, !tbaa [[TAG_INT:!.*]]
-// PATH: store i32 1, i32* %{{.*}}, !tbaa [[TAG_INT:!.*]]
+
+// CHECK: store i32 1, {{.*}}, !tbaa [[TAG_int:!.*]]
   *i = 1;
 }
 
 // PR9307
 struct Test1 { int x; };
 struct Test1MA { int x; } __attribute__((may_alias));
 void test1(struct Test1MA *p1, struct Test1 *p2) {
-  // CHECK: store i32 2, i32* {{%.*}}, !tbaa [[TAG_CHAR]]
-  // PATH: store i32 2, i32* {{%.*}}, !tbaa [[TAG_CHAR]]
+// CHECK-LABEL: test1
+// CHECK: store i32 2, {{.*}}, !tbaa [[TAG_alias_test1_x:!.*]]
   p1->x = 2;
-  // CHECK: store i32 3, i32* {{%.*}}, !tbaa [[TAG_INT]]
-  // PATH: store i32 3, i32* {{%.*}}, !tbaa [[TAG_test1_x:!.*]]
+
+// CHECK: store i32 3, {{.*}}, !tbaa [[TAG_test1_x:!.*]]
   p2->x = 3;
 }
-// CHECK:  !"any pointer", [[TYPE_CHAR:!.*]],
-// CHECK: [[TYPE_CHAR]] = !{!"omnipotent char", [[TAG_CXX_TBAA:!.*]],
-// CHECK: [[TAG_CXX_TBAA]] = !{!"Simple C/C++ TBAA"}
-// CHECK: [[TAG_CHAR]] = !{[[TYPE_CHAR]], [[TYPE_CHAR]], i64 0}
-// CHECK: [[TAG_INT]] = !{[[TYPE_INT:!.*]], [[TYPE_INT]], i64 0}
-// CHECK: [[TYPE_INT]] = !{!"int", [[TYPE_CHAR]]
-
-// PATH: [[TYPE_CHAR:!.*]] = !{!"omnipotent char", !{{.*}}
-// PATH: [[TAG_CHAR]] = !{[[TYPE_CHAR]], [[TYPE_CHAR]], i64 0}
-// PATH: [[TAG_INT]] = !{[[TYPE_INT:!.*]], [[TYPE_INT]], i64 0}
-// PATH: [[TYPE_INT]] = !{!"int", [[TYPE_CHAR]]
-// PATH: [[TAG_test1_x]] = !{[[TYPE_test1:!.*]], [[TYPE_INT]], i64 0}
-// PATH: [[TYPE_test1]] = !{!"Test1", [[TYPE_INT]], i64 0}
+
+// SCALAR-DAG: [[ROOT:!.*]] = !{!"Simple C/C++ TBAA"}
+// SCALAR-DAG: [[TYPE_char:!.*]] = !{!"omnipotent char", [[ROOT]], i64 0}
+// SCALAR-DAG: [[TAG_alias_int]] = !{[[TYPE_char]], [[TYPE_char]], i64 0}
+// SCALAR-DAG: [[TAG_alias_test1_x]] = !{[[TYPE_char]], [[TYPE_char]], i64 0}
+// SCALAR-DAG: [[TYPE_int:!.*]] = !{!"int", [[TYPE_char]], i64 0}
+// SCALAR-DAG: [[TAG_int]] = !{[[TYPE_int]], [[TYPE_int]], i64 0}
+// SCALAR-DAG: [[TAG_test1_x]] = !{[[TYPE_int]], [[TYPE_int]], i64 0}
+
+// OLD-PATH-DAG: [[ROOT:!.*]] = !{!"Simple C/C++ TBAA"}
+// OLD-PATH-DAG: [[TYPE_char:!.*]] = !{!"omnipotent char", [[ROOT]], i64 0}
+// OLD-PATH-DAG: [[TAG_alias_int]] = !{[[TYPE_char]], [[TYPE_char]], i64 0}
+// OLD-PATH-DAG: [[TAG_alias_test1_x]] = !{[[TYPE_char]], [[TYPE_char]], i64 0}
+// OLD-PATH-DAG: [[TYPE_int:!.*]] = !{!"int", [[TYPE_char]], i64 0}
+// OLD-PATH-DAG: [[TAG_int]] = !{[[TYPE_int]], [[TYPE_int]], i64 0}
+// OLD-PATH-DAG: [[TYPE_test1:!.*]] = !{!"Test1", [[TYPE_int]], i64 0}
+// OLD-PATH-DAG: [[TAG_test1_x]] = !{[[TYPE_test1]], [[TYPE_int]], i64 0}
+
+// NEW-PATH-DAG: [[ROOT:!.*]] = !{!"Simple C/C++ TBAA"}
+// NEW-PATH-DAG: [[TYPE_char:!.*]] = !{[[ROOT]], i64 1, !"omnipotent char"}
+// NEW-PATH-DAG: [[TAG_alias_int]] = !{[[TYPE_char]], [[TYPE_char]], i64 0, i64 0}
+// NEW-PATH-DAG: [[TAG_alias_test1_x]] = !{[[TYPE_char]], [[TYPE_char]], i64 0, i64 0}
+// NEW-PATH-DAG: [[TYPE_int:!.*]] = !{[[TYPE_char]], i64 4, !"int"}
+// NEW-PATH-DAG: [[TAG_int]] = !{[[TYPE_int]], [[TYPE_int]], i64 0, i64 4}
+// NEW-PATH-DAG: [[TYPE_test1:!.*]] = !{[[TYPE_char]], i64 4, !"Test1", [[TYPE_int]], i64 0, i64 4}
+// NEW-PATH-DAG: [[TAG_test1_x]] = 

[PATCH] D42366: [CodeGen] Fix generation of TBAA tags for may-alias accesses

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 134877.
kosarev edited the summary of this revision.
kosarev added a comment.

Do not change the size field of may-alias TBAA descriptors for now.


https://reviews.llvm.org/D42366

Files:
  lib/CodeGen/CodeGenModule.cpp
  lib/CodeGen/CodeGenTBAA.cpp
  lib/CodeGen/CodeGenTBAA.h
  test/CodeGen/may-alias.c

Index: test/CodeGen/may-alias.c
===
--- test/CodeGen/may-alias.c
+++ test/CodeGen/may-alias.c
@@ -1,42 +1,61 @@
-// RUN: %clang_cc1 -Werror -triple i386-unknown-unknown -emit-llvm -O1 -no-struct-path-tbaa -disable-llvm-passes -o - %s | FileCheck %s
-// RUN: %clang_cc1 -Werror -triple i386-unknown-unknown -emit-llvm -O1 -disable-llvm-passes -o - %s | FileCheck %s -check-prefix=PATH
+// RUN: %clang_cc1 -Werror -triple i386-unknown-unknown -emit-llvm -O1 \
+// RUN: -no-struct-path-tbaa -disable-llvm-passes -o - %s | \
+// RUN: FileCheck %s -check-prefixes=CHECK,SCALAR
+// RUN: %clang_cc1 -Werror -triple i386-unknown-unknown -emit-llvm -O1 \
+// RUN: -disable-llvm-passes -o - %s | \
+// RUN: FileCheck %s -check-prefixes=CHECK,OLD-PATH
+// RUN: %clang_cc1 -Werror -triple i386-unknown-unknown -emit-llvm -O1 \
+// RUN: -new-struct-path-tbaa -disable-llvm-passes -o - %s | \
+// RUN: FileCheck %s -check-prefixes=CHECK,NEW-PATH
 
 // Types with the may_alias attribute should be considered equivalent
 // to char for aliasing.
 
 typedef int __attribute__((may_alias)) aliasing_int;
 
-void test0(aliasing_int *ai, int *i)
-{
-// CHECK: store i32 0, i32* %{{.*}}, !tbaa [[TAG_CHAR:!.*]]
-// PATH: store i32 0, i32* %{{.*}}, !tbaa [[TAG_CHAR:!.*]]
+void test0(aliasing_int *ai, int *i) {
+// CHECK-LABEL: test0
+// CHECK: store i32 0, {{.*}}, !tbaa [[TAG_alias_int:!.*]]
   *ai = 0;
-// CHECK: store i32 1, i32* %{{.*}}, !tbaa [[TAG_INT:!.*]]
-// PATH: store i32 1, i32* %{{.*}}, !tbaa [[TAG_INT:!.*]]
+
+// CHECK: store i32 1, {{.*}}, !tbaa [[TAG_int:!.*]]
   *i = 1;
 }
 
 // PR9307
 struct Test1 { int x; };
 struct Test1MA { int x; } __attribute__((may_alias));
 void test1(struct Test1MA *p1, struct Test1 *p2) {
-  // CHECK: store i32 2, i32* {{%.*}}, !tbaa [[TAG_CHAR]]
-  // PATH: store i32 2, i32* {{%.*}}, !tbaa [[TAG_CHAR]]
+// CHECK-LABEL: test1
+// CHECK: store i32 2, {{.*}}, !tbaa [[TAG_alias_test1_x:!.*]]
   p1->x = 2;
-  // CHECK: store i32 3, i32* {{%.*}}, !tbaa [[TAG_INT]]
-  // PATH: store i32 3, i32* {{%.*}}, !tbaa [[TAG_test1_x:!.*]]
+
+// CHECK: store i32 3, {{.*}}, !tbaa [[TAG_test1_x:!.*]]
   p2->x = 3;
 }
-// CHECK:  !"any pointer", [[TYPE_CHAR:!.*]],
-// CHECK: [[TYPE_CHAR]] = !{!"omnipotent char", [[TAG_CXX_TBAA:!.*]],
-// CHECK: [[TAG_CXX_TBAA]] = !{!"Simple C/C++ TBAA"}
-// CHECK: [[TAG_CHAR]] = !{[[TYPE_CHAR]], [[TYPE_CHAR]], i64 0}
-// CHECK: [[TAG_INT]] = !{[[TYPE_INT:!.*]], [[TYPE_INT]], i64 0}
-// CHECK: [[TYPE_INT]] = !{!"int", [[TYPE_CHAR]]
-
-// PATH: [[TYPE_CHAR:!.*]] = !{!"omnipotent char", !{{.*}}
-// PATH: [[TAG_CHAR]] = !{[[TYPE_CHAR]], [[TYPE_CHAR]], i64 0}
-// PATH: [[TAG_INT]] = !{[[TYPE_INT:!.*]], [[TYPE_INT]], i64 0}
-// PATH: [[TYPE_INT]] = !{!"int", [[TYPE_CHAR]]
-// PATH: [[TAG_test1_x]] = !{[[TYPE_test1:!.*]], [[TYPE_INT]], i64 0}
-// PATH: [[TYPE_test1]] = !{!"Test1", [[TYPE_INT]], i64 0}
+
+// SCALAR-DAG: [[ROOT:!.*]] = !{!"Simple C/C++ TBAA"}
+// SCALAR-DAG: [[TYPE_char:!.*]] = !{!"omnipotent char", [[ROOT]], i64 0}
+// SCALAR-DAG: [[TAG_alias_int]] = !{[[TYPE_char]], [[TYPE_char]], i64 0}
+// SCALAR-DAG: [[TAG_alias_test1_x]] = !{[[TYPE_char]], [[TYPE_char]], i64 0}
+// SCALAR-DAG: [[TYPE_int:!.*]] = !{!"int", [[TYPE_char]], i64 0}
+// SCALAR-DAG: [[TAG_int]] = !{[[TYPE_int]], [[TYPE_int]], i64 0}
+// SCALAR-DAG: [[TAG_test1_x]] = !{[[TYPE_int]], [[TYPE_int]], i64 0}
+
+// OLD-PATH-DAG: [[ROOT:!.*]] = !{!"Simple C/C++ TBAA"}
+// OLD-PATH-DAG: [[TYPE_char:!.*]] = !{!"omnipotent char", [[ROOT]], i64 0}
+// OLD-PATH-DAG: [[TAG_alias_int]] = !{[[TYPE_char]], [[TYPE_char]], i64 0}
+// OLD-PATH-DAG: [[TAG_alias_test1_x]] = !{[[TYPE_char]], [[TYPE_char]], i64 0}
+// OLD-PATH-DAG: [[TYPE_int:!.*]] = !{!"int", [[TYPE_char]], i64 0}
+// OLD-PATH-DAG: [[TAG_int]] = !{[[TYPE_int]], [[TYPE_int]], i64 0}
+// OLD-PATH-DAG: [[TYPE_test1:!.*]] = !{!"Test1", [[TYPE_int]], i64 0}
+// OLD-PATH-DAG: [[TAG_test1_x]] = !{[[TYPE_test1]], [[TYPE_int]], i64 0}
+
+// NEW-PATH-DAG: [[ROOT:!.*]] = !{!"Simple C/C++ TBAA"}
+// NEW-PATH-DAG: [[TYPE_char:!.*]] = !{[[ROOT]], i64 1, !"omnipotent char"}
+// NEW-PATH-DAG: [[TAG_alias_int]] = !{[[TYPE_char]], [[TYPE_char]], i64 0, i64 0}
+// NEW-PATH-DAG: [[TAG_alias_test1_x]] = !{[[TYPE_char]], [[TYPE_char]], i64 0, i64 0}
+// NEW-PATH-DAG: [[TYPE_int:!.*]] = !{[[TYPE_char]], i64 4, !"int"}
+// NEW-PATH-DAG: [[TAG_int]] = !{[[TYPE_int]], [[TYPE_int]], i64 0, i64 4}
+// NEW-PATH-DAG: [[TYPE_test1:!.*]] = !{[[TYPE_char]], i64 4, !"Test1", [[TYPE_int]], i64 0, i64 4}
+// NEW-PATH-DAG: [[TAG_test1_x]] = !{[[TYPE_test1]], [[TYPE_int]], i64 0, i64 

[PATCH] D43181: [CodeGen] Initialize large arrays by copying from a global

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL325478: [CodeGen] Initialize large arrays by copying from a 
global (authored by kosarev, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D43181?vs=134590=134865#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D43181

Files:
  cfe/trunk/lib/CodeGen/CGExprAgg.cpp
  cfe/trunk/test/CodeGen/init.c

Index: cfe/trunk/test/CodeGen/init.c
===
--- cfe/trunk/test/CodeGen/init.c
+++ cfe/trunk/test/CodeGen/init.c
@@ -8,8 +8,9 @@
 // CHECK-DAG: %struct.M = type { [2 x %struct.I] }
 // CHECK-DAG: %struct.I = type { [3 x i32] }
 
-// CHECK: [1 x %struct.M] [%struct.M { [2 x %struct.I] [%struct.I { [3 x i32] [i32 4, i32 4, i32 0] }, %struct.I { [3 x i32] [i32 4, i32 4, i32 5] }] }],
-// CHECK: [2 x [3 x i32]] {{[[][[]}}3 x i32] [i32 , i32 , i32 0], [3 x i32] [i32 , i32 , i32 ]],
+// CHECK-DAG: [1 x %struct.M] [%struct.M { [2 x %struct.I] [%struct.I { [3 x i32] [i32 4, i32 4, i32 0] }, %struct.I { [3 x i32] [i32 4, i32 4, i32 5] }] }],
+// CHECK-DAG: [2 x [3 x i32]] {{[[][[]}}3 x i32] [i32 , i32 , i32 0], [3 x i32] [i32 , i32 , i32 ]],
+// CHECK-DAG: [[INIT14:.*]] = private global [16 x i32] [i32 0, i32 0, i32 0, i32 0, i32 0, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 0, i32 0, i32 0, i32 0], align 4
 
 void f1() {
   // Scalars in braces.
@@ -33,8 +34,8 @@
 }
 
 // Constants
-// CHECK: @g3 = constant i32 10
-// CHECK: @f4.g4 = internal constant i32 12
+// CHECK-DAG: @g3 = constant i32 10
+// CHECK-DAG: @f4.g4 = internal constant i32 12
 const int g3 = 10;
 int f4() {
   static const int g4 = 12;
@@ -61,7 +62,7 @@
 
 
 
-// CHECK: @test7 = global{{.*}}{ i32 0, [4 x i8] c"bar\00" }
+// CHECK-DAG: @test7 = global{{.*}}{ i32 0, [4 x i8] c"bar\00" }
 // PR8217
 struct a7 {
   int  b;
@@ -151,3 +152,15 @@
   // CHECK: memcpy{{.*}}getelementptr inbounds ([3 x i8], [3 x i8]* @
   bar((char[3]) {""});
 }
+
+// Test that we initialize large member arrays by copying from a global and not
+// with a series of stores.
+struct S14 { int a[16]; };
+
+void test14(struct S14 *s14) {
+// CHECK-LABEL: @test14
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 {{.*}}, i8* align 4 {{.*}} [[INIT14]] {{.*}}, i32 64, i1 false)
+// CHECK-NOT: store
+// CHECK: ret void
+  *s14 = (struct S14) { { [5 ... 11] = 17 } };
+}
Index: cfe/trunk/lib/CodeGen/CGExprAgg.cpp
===
--- cfe/trunk/lib/CodeGen/CGExprAgg.cpp
+++ cfe/trunk/lib/CodeGen/CGExprAgg.cpp
@@ -14,6 +14,7 @@
 #include "CodeGenFunction.h"
 #include "CGObjCRuntime.h"
 #include "CodeGenModule.h"
+#include "ConstantEmitter.h"
 #include "clang/AST/ASTContext.h"
 #include "clang/AST/DeclCXX.h"
 #include "clang/AST/DeclTemplate.h"
@@ -85,7 +86,7 @@
   void EmitMoveFromReturnSlot(const Expr *E, RValue Src);
 
   void EmitArrayInit(Address DestPtr, llvm::ArrayType *AType,
- QualType elementType, InitListExpr *E);
+ QualType ArrayQTy, InitListExpr *E);
 
   AggValueSlot::NeedsGCBarriers_t needsGC(QualType T) {
 if (CGF.getLangOpts().getGC() && TypeRequiresGCollection(T))
@@ -394,12 +395,15 @@
 
 /// \brief Emit initialization of an array from an initializer list.
 void AggExprEmitter::EmitArrayInit(Address DestPtr, llvm::ArrayType *AType,
-   QualType elementType, InitListExpr *E) {
+   QualType ArrayQTy, InitListExpr *E) {
   uint64_t NumInitElements = E->getNumInits();
 
   uint64_t NumArrayElements = AType->getNumElements();
   assert(NumInitElements <= NumArrayElements);
 
+  QualType elementType =
+  CGF.getContext().getAsArrayType(ArrayQTy)->getElementType();
+
   // DestPtr is an array*.  Construct an elementType* by drilling
   // down a level.
   llvm::Value *zero = llvm::ConstantInt::get(CGF.SizeTy, 0);
@@ -411,6 +415,29 @@
   CharUnits elementAlign =
 DestPtr.getAlignment().alignmentOfArrayElement(elementSize);
 
+  // Consider initializing the array by copying from a global. For this to be
+  // more efficient than per-element initialization, the size of the elements
+  // with explicit initializers should be large enough.
+  if (NumInitElements * elementSize.getQuantity() > 16 &&
+  elementType.isTriviallyCopyableType(CGF.getContext())) {
+CodeGen::CodeGenModule  = CGF.CGM;
+ConstantEmitter Emitter(CGM);
+LangAS AS = ArrayQTy.getAddressSpace();
+if (llvm::Constant *C = Emitter.tryEmitForInitializer(E, AS, ArrayQTy)) {
+  auto GV = new llvm::GlobalVariable(
+  CGM.getModule(), C->getType(),
+  CGM.isTypeConstant(ArrayQTy, /* ExcludeCtorDtor= */ true),
+  llvm::GlobalValue::PrivateLinkage, C, "constinit",
+  /* InsertBefore= */ nullptr, llvm::GlobalVariable::NotThreadLocal,
+  

[PATCH] D42366: [CodeGen] Fix generation of TBAA tags for may-alias accesses

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

John, the patch hangs for about a month now and Hal still seems to be extremely 
busy. Can we commit this with the constant to be whatever you think is most 
correct and the fix it as needed and if needed later? At this very moment we 
don't analyze the size fields of tags anyway, so the point of this patch is 
mostly to handle may-alias-marked types correctly.


Repository:
  rL LLVM

https://reviews.llvm.org/D42366



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D43181: [CodeGen] Initialize large arrays by copying from a global

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 134590.
kosarev added a comment.

Updated to consider the total size of the explicit initializers instead of 
their number. The threshold value is adjusted respectively.


https://reviews.llvm.org/D43181

Files:
  lib/CodeGen/CGExprAgg.cpp
  test/CodeGen/init.c

Index: test/CodeGen/init.c
===
--- test/CodeGen/init.c
+++ test/CodeGen/init.c
@@ -8,8 +8,9 @@
 // CHECK-DAG: %struct.M = type { [2 x %struct.I] }
 // CHECK-DAG: %struct.I = type { [3 x i32] }
 
-// CHECK: [1 x %struct.M] [%struct.M { [2 x %struct.I] [%struct.I { [3 x i32] [i32 4, i32 4, i32 0] }, %struct.I { [3 x i32] [i32 4, i32 4, i32 5] }] }],
-// CHECK: [2 x [3 x i32]] {{[[][[]}}3 x i32] [i32 , i32 , i32 0], [3 x i32] [i32 , i32 , i32 ]],
+// CHECK-DAG: [1 x %struct.M] [%struct.M { [2 x %struct.I] [%struct.I { [3 x i32] [i32 4, i32 4, i32 0] }, %struct.I { [3 x i32] [i32 4, i32 4, i32 5] }] }],
+// CHECK-DAG: [2 x [3 x i32]] {{[[][[]}}3 x i32] [i32 , i32 , i32 0], [3 x i32] [i32 , i32 , i32 ]],
+// CHECK-DAG: [[INIT14:.*]] = private global [16 x i32] [i32 0, i32 0, i32 0, i32 0, i32 0, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 0, i32 0, i32 0, i32 0], align 4
 
 void f1() {
   // Scalars in braces.
@@ -33,8 +34,8 @@
 }
 
 // Constants
-// CHECK: @g3 = constant i32 10
-// CHECK: @f4.g4 = internal constant i32 12
+// CHECK-DAG: @g3 = constant i32 10
+// CHECK-DAG: @f4.g4 = internal constant i32 12
 const int g3 = 10;
 int f4() {
   static const int g4 = 12;
@@ -61,7 +62,7 @@
 
 
 
-// CHECK: @test7 = global{{.*}}{ i32 0, [4 x i8] c"bar\00" }
+// CHECK-DAG: @test7 = global{{.*}}{ i32 0, [4 x i8] c"bar\00" }
 // PR8217
 struct a7 {
   int  b;
@@ -151,3 +152,15 @@
   // CHECK: memcpy{{.*}}getelementptr inbounds ([3 x i8], [3 x i8]* @
   bar((char[3]) {""});
 }
+
+// Test that we initialize large member arrays by copying from a global and not
+// with a series of stores.
+struct S14 { int a[16]; };
+
+void test14(struct S14 *s14) {
+// CHECK-LABEL: @test14
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 {{.*}}, i8* align 4 {{.*}} [[INIT14]] {{.*}}, i32 64, i1 false)
+// CHECK-NOT: store
+// CHECK: ret void
+  *s14 = (struct S14) { { [5 ... 11] = 17 } };
+}
Index: lib/CodeGen/CGExprAgg.cpp
===
--- lib/CodeGen/CGExprAgg.cpp
+++ lib/CodeGen/CGExprAgg.cpp
@@ -14,6 +14,7 @@
 #include "CodeGenFunction.h"
 #include "CGObjCRuntime.h"
 #include "CodeGenModule.h"
+#include "ConstantEmitter.h"
 #include "clang/AST/ASTContext.h"
 #include "clang/AST/DeclCXX.h"
 #include "clang/AST/DeclTemplate.h"
@@ -85,7 +86,7 @@
   void EmitMoveFromReturnSlot(const Expr *E, RValue Src);
 
   void EmitArrayInit(Address DestPtr, llvm::ArrayType *AType,
- QualType elementType, InitListExpr *E);
+ QualType ArrayQTy, InitListExpr *E);
 
   AggValueSlot::NeedsGCBarriers_t needsGC(QualType T) {
 if (CGF.getLangOpts().getGC() && TypeRequiresGCollection(T))
@@ -394,12 +395,15 @@
 
 /// \brief Emit initialization of an array from an initializer list.
 void AggExprEmitter::EmitArrayInit(Address DestPtr, llvm::ArrayType *AType,
-   QualType elementType, InitListExpr *E) {
+   QualType ArrayQTy, InitListExpr *E) {
   uint64_t NumInitElements = E->getNumInits();
 
   uint64_t NumArrayElements = AType->getNumElements();
   assert(NumInitElements <= NumArrayElements);
 
+  QualType elementType =
+  CGF.getContext().getAsArrayType(ArrayQTy)->getElementType();
+
   // DestPtr is an array*.  Construct an elementType* by drilling
   // down a level.
   llvm::Value *zero = llvm::ConstantInt::get(CGF.SizeTy, 0);
@@ -411,6 +415,29 @@
   CharUnits elementAlign =
 DestPtr.getAlignment().alignmentOfArrayElement(elementSize);
 
+  // Consider initializing the array by copying from a global. For this to be
+  // more efficient than per-element initialization, the number of the elements
+  // with explicit initializers should be large enough.
+  if (NumInitElements * elementSize.getQuantity() > 16 &&
+  elementType.isTriviallyCopyableType(CGF.getContext())) {
+CodeGen::CodeGenModule  = CGF.CGM;
+ConstantEmitter Emitter(CGM);
+LangAS AS = ArrayQTy.getAddressSpace();
+if (llvm::Constant *C = Emitter.tryEmitForInitializer(E, AS, ArrayQTy)) {
+  auto GV = new llvm::GlobalVariable(
+  CGM.getModule(), C->getType(),
+  CGM.isTypeConstant(ArrayQTy, /* ExcludeCtorDtor= */ true),
+  llvm::GlobalValue::PrivateLinkage, C, "constinit",
+  /* InsertBefore= */ nullptr, llvm::GlobalVariable::NotThreadLocal,
+  CGM.getContext().getTargetAddressSpace(AS));
+  Emitter.finalize(GV);
+  CharUnits Align = CGM.getContext().getTypeAlignInChars(ArrayQTy);
+  GV->setAlignment(Align.getQuantity());
+  

[PATCH] D43187: [AST] Refine the condition for element-dependent array fillers

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL325120: [AST] Refine the condition for element-dependent 
array fillers (authored by kosarev, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D43187?vs=133846=134200#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D43187

Files:
  cfe/trunk/lib/AST/ExprConstant.cpp
  cfe/trunk/test/SemaCXX/large-array-init.cpp


Index: cfe/trunk/test/SemaCXX/large-array-init.cpp
===
--- cfe/trunk/test/SemaCXX/large-array-init.cpp
+++ cfe/trunk/test/SemaCXX/large-array-init.cpp
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -S -o %t.ll -mllvm -debug-only=exprconstant %s 2>&1 | \
+// RUN: FileCheck %s
+
+struct S { int i; };
+
+static struct S arr[1] = {{ 0 }};
+// CHECK: The number of elements to initialize: 1.
+
+struct S *foo() { return arr; }
Index: cfe/trunk/lib/AST/ExprConstant.cpp
===
--- cfe/trunk/lib/AST/ExprConstant.cpp
+++ cfe/trunk/lib/AST/ExprConstant.cpp
@@ -48,6 +48,8 @@
 #include 
 #include 
 
+#define DEBUG_TYPE "exprconstant"
+
 using namespace clang;
 using llvm::APSInt;
 using llvm::APFloat;
@@ -6780,6 +6782,22 @@
   return ArrayExprEvaluator(Info, This, Result).Visit(E);
 }
 
+// Return true iff the given array filler may depend on the element index.
+static bool MaybeElementDependentArrayFiller(const Expr *FillerExpr) {
+  // For now, just whitelist non-class value-initialization and initialization
+  // lists comprised of them.
+  if (isa(FillerExpr))
+return false;
+  if (const InitListExpr *ILE = dyn_cast(FillerExpr)) {
+for (unsigned I = 0, E = ILE->getNumInits(); I != E; ++I) {
+  if (MaybeElementDependentArrayFiller(ILE->getInit(I)))
+return true;
+}
+return false;
+  }
+  return true;
+}
+
 bool ArrayExprEvaluator::VisitInitListExpr(const InitListExpr *E) {
   const ConstantArrayType *CAT = Info.Ctx.getAsConstantArrayType(E->getType());
   if (!CAT)
@@ -6809,10 +6827,13 @@
   const Expr *FillerExpr = E->hasArrayFiller() ? E->getArrayFiller() : nullptr;
 
   // If the initializer might depend on the array index, run it for each
-  // array element. For now, just whitelist non-class value-initialization.
-  if (NumEltsToInit != NumElts && !isa(FillerExpr))
+  // array element.
+  if (NumEltsToInit != NumElts && MaybeElementDependentArrayFiller(FillerExpr))
 NumEltsToInit = NumElts;
 
+  DEBUG(llvm::dbgs() << "The number of elements to initialize: " <<
+NumEltsToInit << ".\n");
+
   Result = APValue(APValue::UninitArray(), NumEltsToInit, NumElts);
 
   // If the array was previously zero-initialized, preserve the


Index: cfe/trunk/test/SemaCXX/large-array-init.cpp
===
--- cfe/trunk/test/SemaCXX/large-array-init.cpp
+++ cfe/trunk/test/SemaCXX/large-array-init.cpp
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -S -o %t.ll -mllvm -debug-only=exprconstant %s 2>&1 | \
+// RUN: FileCheck %s
+
+struct S { int i; };
+
+static struct S arr[1] = {{ 0 }};
+// CHECK: The number of elements to initialize: 1.
+
+struct S *foo() { return arr; }
Index: cfe/trunk/lib/AST/ExprConstant.cpp
===
--- cfe/trunk/lib/AST/ExprConstant.cpp
+++ cfe/trunk/lib/AST/ExprConstant.cpp
@@ -48,6 +48,8 @@
 #include 
 #include 
 
+#define DEBUG_TYPE "exprconstant"
+
 using namespace clang;
 using llvm::APSInt;
 using llvm::APFloat;
@@ -6780,6 +6782,22 @@
   return ArrayExprEvaluator(Info, This, Result).Visit(E);
 }
 
+// Return true iff the given array filler may depend on the element index.
+static bool MaybeElementDependentArrayFiller(const Expr *FillerExpr) {
+  // For now, just whitelist non-class value-initialization and initialization
+  // lists comprised of them.
+  if (isa(FillerExpr))
+return false;
+  if (const InitListExpr *ILE = dyn_cast(FillerExpr)) {
+for (unsigned I = 0, E = ILE->getNumInits(); I != E; ++I) {
+  if (MaybeElementDependentArrayFiller(ILE->getInit(I)))
+return true;
+}
+return false;
+  }
+  return true;
+}
+
 bool ArrayExprEvaluator::VisitInitListExpr(const InitListExpr *E) {
   const ConstantArrayType *CAT = Info.Ctx.getAsConstantArrayType(E->getType());
   if (!CAT)
@@ -6809,10 +6827,13 @@
   const Expr *FillerExpr = E->hasArrayFiller() ? E->getArrayFiller() : nullptr;
 
   // If the initializer might depend on the array index, run it for each
-  // array element. For now, just whitelist non-class value-initialization.
-  if (NumEltsToInit != NumElts && !isa(FillerExpr))
+  // array element.
+  if (NumEltsToInit != NumElts && MaybeElementDependentArrayFiller(FillerExpr))
 NumEltsToInit = NumElts;
 
+  DEBUG(llvm::dbgs() << "The number of elements to initialize: " <<
+NumEltsToInit << ".\n");
+
   Result = APValue(APValue::UninitArray(), NumEltsToInit, 

[PATCH] D43181: [CodeGen] Initialize large arrays by copying from a global

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 134042.
kosarev added a comment.

Improved as suggested to cover all trivially-copyable types.


https://reviews.llvm.org/D43181

Files:
  lib/CodeGen/CGExprAgg.cpp
  test/CodeGen/init.c

Index: test/CodeGen/init.c
===
--- test/CodeGen/init.c
+++ test/CodeGen/init.c
@@ -8,8 +8,9 @@
 // CHECK-DAG: %struct.M = type { [2 x %struct.I] }
 // CHECK-DAG: %struct.I = type { [3 x i32] }
 
-// CHECK: [1 x %struct.M] [%struct.M { [2 x %struct.I] [%struct.I { [3 x i32] [i32 4, i32 4, i32 0] }, %struct.I { [3 x i32] [i32 4, i32 4, i32 5] }] }],
-// CHECK: [2 x [3 x i32]] {{[[][[]}}3 x i32] [i32 , i32 , i32 0], [3 x i32] [i32 , i32 , i32 ]],
+// CHECK-DAG: [1 x %struct.M] [%struct.M { [2 x %struct.I] [%struct.I { [3 x i32] [i32 4, i32 4, i32 0] }, %struct.I { [3 x i32] [i32 4, i32 4, i32 5] }] }],
+// CHECK-DAG: [2 x [3 x i32]] {{[[][[]}}3 x i32] [i32 , i32 , i32 0], [3 x i32] [i32 , i32 , i32 ]],
+// CHECK-DAG: [[INIT14:.*]] = private global [16 x i32] [i32 0, i32 0, i32 0, i32 0, i32 0, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 0, i32 0, i32 0, i32 0], align 4
 
 void f1() {
   // Scalars in braces.
@@ -33,8 +34,8 @@
 }
 
 // Constants
-// CHECK: @g3 = constant i32 10
-// CHECK: @f4.g4 = internal constant i32 12
+// CHECK-DAG: @g3 = constant i32 10
+// CHECK-DAG: @f4.g4 = internal constant i32 12
 const int g3 = 10;
 int f4() {
   static const int g4 = 12;
@@ -61,7 +62,7 @@
 
 
 
-// CHECK: @test7 = global{{.*}}{ i32 0, [4 x i8] c"bar\00" }
+// CHECK-DAG: @test7 = global{{.*}}{ i32 0, [4 x i8] c"bar\00" }
 // PR8217
 struct a7 {
   int  b;
@@ -151,3 +152,15 @@
   // CHECK: memcpy{{.*}}getelementptr inbounds ([3 x i8], [3 x i8]* @
   bar((char[3]) {""});
 }
+
+// Test that we initialize large member arrays by copying from a global and not
+// with a series of stores.
+struct S14 { int a[16]; };
+
+void test14(struct S14 *s14) {
+// CHECK-LABEL: @test14
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 {{.*}}, i8* align 4 {{.*}} [[INIT14]] {{.*}}, i32 64, i1 false)
+// CHECK-NOT: store
+// CHECK: ret void
+  *s14 = (struct S14) { { [5 ... 11] = 17 } };
+}
Index: lib/CodeGen/CGExprAgg.cpp
===
--- lib/CodeGen/CGExprAgg.cpp
+++ lib/CodeGen/CGExprAgg.cpp
@@ -14,6 +14,7 @@
 #include "CodeGenFunction.h"
 #include "CGObjCRuntime.h"
 #include "CodeGenModule.h"
+#include "ConstantEmitter.h"
 #include "clang/AST/ASTContext.h"
 #include "clang/AST/DeclCXX.h"
 #include "clang/AST/DeclTemplate.h"
@@ -85,7 +86,7 @@
   void EmitMoveFromReturnSlot(const Expr *E, RValue Src);
 
   void EmitArrayInit(Address DestPtr, llvm::ArrayType *AType,
- QualType elementType, InitListExpr *E);
+ QualType ArrayQTy, InitListExpr *E);
 
   AggValueSlot::NeedsGCBarriers_t needsGC(QualType T) {
 if (CGF.getLangOpts().getGC() && TypeRequiresGCollection(T))
@@ -394,12 +395,15 @@
 
 /// \brief Emit initialization of an array from an initializer list.
 void AggExprEmitter::EmitArrayInit(Address DestPtr, llvm::ArrayType *AType,
-   QualType elementType, InitListExpr *E) {
+   QualType ArrayQTy, InitListExpr *E) {
   uint64_t NumInitElements = E->getNumInits();
 
   uint64_t NumArrayElements = AType->getNumElements();
   assert(NumInitElements <= NumArrayElements);
 
+  QualType elementType =
+  CGF.getContext().getAsArrayType(ArrayQTy)->getElementType();
+
   // DestPtr is an array*.  Construct an elementType* by drilling
   // down a level.
   llvm::Value *zero = llvm::ConstantInt::get(CGF.SizeTy, 0);
@@ -411,6 +415,29 @@
   CharUnits elementAlign =
 DestPtr.getAlignment().alignmentOfArrayElement(elementSize);
 
+  // Consider initializing the array by copying from a global. For this to be
+  // more efficient than per-element initialization, the number of the elements
+  // with explicit initializers should be large enough.
+  if (NumInitElements > 8 &&
+  elementType.isTriviallyCopyableType(CGF.getContext())) {
+CodeGen::CodeGenModule  = CGF.CGM;
+ConstantEmitter Emitter(CGM);
+LangAS AS = ArrayQTy.getAddressSpace();
+if (llvm::Constant *C = Emitter.tryEmitForInitializer(E, AS, ArrayQTy)) {
+  auto GV = new llvm::GlobalVariable(
+  CGM.getModule(), C->getType(),
+  CGM.isTypeConstant(ArrayQTy, /* ExcludeCtorDtor= */ true),
+  llvm::GlobalValue::PrivateLinkage, C, "constinit",
+  /* InsertBefore= */ nullptr, llvm::GlobalVariable::NotThreadLocal,
+  CGM.getContext().getTargetAddressSpace(AS));
+  Emitter.finalize(GV);
+  CharUnits Align = CGM.getContext().getTypeAlignInChars(ArrayQTy);
+  GV->setAlignment(Align.getQuantity());
+  EmitFinalDestCopy(ArrayQTy, CGF.MakeAddrLValue(GV, ArrayQTy, Align));
+  return;
+}
+  }
+
   // 

[PATCH] D43187: [AST] Refine the condition for element-dependent array fillers

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

John, maybe you can review this or suggest some other reviewers? Thanks.


Repository:
  rL LLVM

https://reviews.llvm.org/D43187



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D43181: [CodeGen] Initialize large arrays by copying from a global

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added inline comments.



Comment at: lib/CodeGen/CGExprAgg.cpp:421
+  // with explicit initializers should be large enough.
+  if (NumInitElements > 8 && elementType->isBuiltinType()) {
+CodeGen::CodeGenModule  = CGF.CGM;

rjmccall wrote:
> Is there a good reason to use an element-count heuristic instead of a 
> total-size heuristic here?
> 
> Why only builtin types?  That seems to pointlessly rule out nested arrays, 
> complex types, vectors, C structs, and so on.  I think the predicate you 
> probably want here is isTriviallyCopyableType.
> Is there a good reason to use an element-count heuristic instead of a 
> total-size heuristic here?

Yes, the code below generates per-element initialization only for explicitly 
specified initializers. The rest, if any, is initialized with a filler, so it 
doesn't affect the size of the resulting code much.


Repository:
  rL LLVM

https://reviews.llvm.org/D43181



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D43187: [AST] Refine the condition for element-dependent array fillers

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added a reviewer: rsmith.
kosarev added a project: clang.
Herald added a subscriber: llvm-commits.

This patch fixes clang to not consider braced initializers for aggregate 
elements of arrays to be potentially dependent on the indices of the 
initialized elements. Resolves bug 18978:
initialize a large static array = clang oom?
https://bugs.llvm.org/show_bug.cgi?id=18978


Repository:
  rL LLVM

https://reviews.llvm.org/D43187

Files:
  lib/AST/ExprConstant.cpp
  test/SemaCXX/large-array-init.cpp


Index: test/SemaCXX/large-array-init.cpp
===
--- test/SemaCXX/large-array-init.cpp
+++ test/SemaCXX/large-array-init.cpp
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -S -o %t.ll -mllvm -debug-only=exprconstant %s 2>&1 | \
+// RUN: FileCheck %s
+
+struct S { int i; };
+
+static struct S arr[1] = {{ 0 }};
+// CHECK: The number of elements to initialize: 1.
+
+struct S *foo() { return arr; }
Index: lib/AST/ExprConstant.cpp
===
--- lib/AST/ExprConstant.cpp
+++ lib/AST/ExprConstant.cpp
@@ -48,6 +48,8 @@
 #include 
 #include 
 
+#define DEBUG_TYPE "exprconstant"
+
 using namespace clang;
 using llvm::APSInt;
 using llvm::APFloat;
@@ -6780,6 +6782,23 @@
   return ArrayExprEvaluator(Info, This, Result).Visit(E);
 }
 
+// Return true iff the given array filler may depend on element on the element
+// index.
+static bool MaybeElementDependentArrayFiller(const Expr *FillerExpr) {
+  // For now, just whitelist non-class value-initialization and initialization
+  // lists comprised of them.
+  if (isa(FillerExpr))
+return false;
+  if (const InitListExpr *ILE = dyn_cast(FillerExpr)) {
+for (unsigned I = 0, E = ILE->getNumInits(); I != E; ++I) {
+  if (MaybeElementDependentArrayFiller(ILE->getInit(I)))
+return true;
+}
+return false;
+  }
+  return true;
+}
+
 bool ArrayExprEvaluator::VisitInitListExpr(const InitListExpr *E) {
   const ConstantArrayType *CAT = Info.Ctx.getAsConstantArrayType(E->getType());
   if (!CAT)
@@ -6809,10 +6828,13 @@
   const Expr *FillerExpr = E->hasArrayFiller() ? E->getArrayFiller() : nullptr;
 
   // If the initializer might depend on the array index, run it for each
-  // array element. For now, just whitelist non-class value-initialization.
-  if (NumEltsToInit != NumElts && !isa(FillerExpr))
+  // array element.
+  if (NumEltsToInit != NumElts && MaybeElementDependentArrayFiller(FillerExpr))
 NumEltsToInit = NumElts;
 
+  DEBUG(llvm::dbgs() << "The number of elements to initialize: " <<
+NumEltsToInit << ".\n");
+
   Result = APValue(APValue::UninitArray(), NumEltsToInit, NumElts);
 
   // If the array was previously zero-initialized, preserve the


Index: test/SemaCXX/large-array-init.cpp
===
--- test/SemaCXX/large-array-init.cpp
+++ test/SemaCXX/large-array-init.cpp
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -S -o %t.ll -mllvm -debug-only=exprconstant %s 2>&1 | \
+// RUN: FileCheck %s
+
+struct S { int i; };
+
+static struct S arr[1] = {{ 0 }};
+// CHECK: The number of elements to initialize: 1.
+
+struct S *foo() { return arr; }
Index: lib/AST/ExprConstant.cpp
===
--- lib/AST/ExprConstant.cpp
+++ lib/AST/ExprConstant.cpp
@@ -48,6 +48,8 @@
 #include 
 #include 
 
+#define DEBUG_TYPE "exprconstant"
+
 using namespace clang;
 using llvm::APSInt;
 using llvm::APFloat;
@@ -6780,6 +6782,23 @@
   return ArrayExprEvaluator(Info, This, Result).Visit(E);
 }
 
+// Return true iff the given array filler may depend on element on the element
+// index.
+static bool MaybeElementDependentArrayFiller(const Expr *FillerExpr) {
+  // For now, just whitelist non-class value-initialization and initialization
+  // lists comprised of them.
+  if (isa(FillerExpr))
+return false;
+  if (const InitListExpr *ILE = dyn_cast(FillerExpr)) {
+for (unsigned I = 0, E = ILE->getNumInits(); I != E; ++I) {
+  if (MaybeElementDependentArrayFiller(ILE->getInit(I)))
+return true;
+}
+return false;
+  }
+  return true;
+}
+
 bool ArrayExprEvaluator::VisitInitListExpr(const InitListExpr *E) {
   const ConstantArrayType *CAT = Info.Ctx.getAsConstantArrayType(E->getType());
   if (!CAT)
@@ -6809,10 +6828,13 @@
   const Expr *FillerExpr = E->hasArrayFiller() ? E->getArrayFiller() : nullptr;
 
   // If the initializer might depend on the array index, run it for each
-  // array element. For now, just whitelist non-class value-initialization.
-  if (NumEltsToInit != NumElts && !isa(FillerExpr))
+  // array element.
+  if (NumEltsToInit != NumElts && MaybeElementDependentArrayFiller(FillerExpr))
 NumEltsToInit = NumElts;
 
+  DEBUG(llvm::dbgs() << "The number of elements to initialize: " <<
+NumEltsToInit << ".\n");
+
   Result = 

[PATCH] D43181: [CodeGen] Initialize large arrays by copying from a global

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added a reviewer: rjmccall.
kosarev added a project: clang.
Herald added a subscriber: llvm-commits.

Currently, clang compiles explicit initializers for array elements into series 
of store instructions. For large arrays of built-in types this results in 
bloated output code and significant amount of time spent on the instruction 
selection phase. This patch fixes the issue by initializing such arrays with 
global constants that store the binary image of the initializer.


Repository:
  rL LLVM

https://reviews.llvm.org/D43181

Files:
  lib/CodeGen/CGExprAgg.cpp
  test/CodeGen/init.c

Index: test/CodeGen/init.c
===
--- test/CodeGen/init.c
+++ test/CodeGen/init.c
@@ -8,8 +8,9 @@
 // CHECK-DAG: %struct.M = type { [2 x %struct.I] }
 // CHECK-DAG: %struct.I = type { [3 x i32] }
 
-// CHECK: [1 x %struct.M] [%struct.M { [2 x %struct.I] [%struct.I { [3 x i32] [i32 4, i32 4, i32 0] }, %struct.I { [3 x i32] [i32 4, i32 4, i32 5] }] }],
-// CHECK: [2 x [3 x i32]] {{[[][[]}}3 x i32] [i32 , i32 , i32 0], [3 x i32] [i32 , i32 , i32 ]],
+// CHECK-DAG: [1 x %struct.M] [%struct.M { [2 x %struct.I] [%struct.I { [3 x i32] [i32 4, i32 4, i32 0] }, %struct.I { [3 x i32] [i32 4, i32 4, i32 5] }] }],
+// CHECK-DAG: [2 x [3 x i32]] {{[[][[]}}3 x i32] [i32 , i32 , i32 0], [3 x i32] [i32 , i32 , i32 ]],
+// CHECK-DAG: [[INIT14:.*]] = private global [16 x i32] [i32 0, i32 0, i32 0, i32 0, i32 0, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 17, i32 0, i32 0, i32 0, i32 0], align 4
 
 void f1() {
   // Scalars in braces.
@@ -33,8 +34,8 @@
 }
 
 // Constants
-// CHECK: @g3 = constant i32 10
-// CHECK: @f4.g4 = internal constant i32 12
+// CHECK-DAG: @g3 = constant i32 10
+// CHECK-DAG: @f4.g4 = internal constant i32 12
 const int g3 = 10;
 int f4() {
   static const int g4 = 12;
@@ -61,7 +62,7 @@
 
 
 
-// CHECK: @test7 = global{{.*}}{ i32 0, [4 x i8] c"bar\00" }
+// CHECK-DAG: @test7 = global{{.*}}{ i32 0, [4 x i8] c"bar\00" }
 // PR8217
 struct a7 {
   int  b;
@@ -151,3 +152,15 @@
   // CHECK: memcpy{{.*}}getelementptr inbounds ([3 x i8], [3 x i8]* @
   bar((char[3]) {""});
 }
+
+// Test that we initialize large member arrays by copying from a global and not
+// with a series of stores.
+struct S14 { int a[16]; };
+
+void test14(struct S14 *s14) {
+// CHECK-LABEL: @test14
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 {{.*}}, i8* align 4 {{.*}} [[INIT14]] {{.*}}, i32 64, i1 false)
+// CHECK-NOT: store
+// CHECK: ret void
+  *s14 = (struct S14) { { [5 ... 11] = 17 } };
+}
Index: lib/CodeGen/CGExprAgg.cpp
===
--- lib/CodeGen/CGExprAgg.cpp
+++ lib/CodeGen/CGExprAgg.cpp
@@ -14,6 +14,7 @@
 #include "CodeGenFunction.h"
 #include "CGObjCRuntime.h"
 #include "CodeGenModule.h"
+#include "ConstantEmitter.h"
 #include "clang/AST/ASTContext.h"
 #include "clang/AST/DeclCXX.h"
 #include "clang/AST/DeclTemplate.h"
@@ -85,7 +86,7 @@
   void EmitMoveFromReturnSlot(const Expr *E, RValue Src);
 
   void EmitArrayInit(Address DestPtr, llvm::ArrayType *AType,
- QualType elementType, InitListExpr *E);
+ QualType ArrayQTy, InitListExpr *E);
 
   AggValueSlot::NeedsGCBarriers_t needsGC(QualType T) {
 if (CGF.getLangOpts().getGC() && TypeRequiresGCollection(T))
@@ -394,12 +395,15 @@
 
 /// \brief Emit initialization of an array from an initializer list.
 void AggExprEmitter::EmitArrayInit(Address DestPtr, llvm::ArrayType *AType,
-   QualType elementType, InitListExpr *E) {
+   QualType ArrayQTy, InitListExpr *E) {
   uint64_t NumInitElements = E->getNumInits();
 
   uint64_t NumArrayElements = AType->getNumElements();
   assert(NumInitElements <= NumArrayElements);
 
+  QualType elementType =
+  CGF.getContext().getAsArrayType(ArrayQTy)->getElementType();
+
   // DestPtr is an array*.  Construct an elementType* by drilling
   // down a level.
   llvm::Value *zero = llvm::ConstantInt::get(CGF.SizeTy, 0);
@@ -411,6 +415,28 @@
   CharUnits elementAlign =
 DestPtr.getAlignment().alignmentOfArrayElement(elementSize);
 
+  // Consider initializing the array by copying from a global. For this to be
+  // more efficient than per-element initialization, the number of the elements
+  // with explicit initializers should be large enough.
+  if (NumInitElements > 8 && elementType->isBuiltinType()) {
+CodeGen::CodeGenModule  = CGF.CGM;
+ConstantEmitter Emitter(CGM);
+LangAS AS = ArrayQTy.getAddressSpace();
+if (llvm::Constant *C = Emitter.tryEmitForInitializer(E, AS, ArrayQTy)) {
+  auto GV = new llvm::GlobalVariable(
+  CGM.getModule(), C->getType(),
+  CGM.isTypeConstant(ArrayQTy, /* ExcludeCtorDtor= */ true),
+  llvm::GlobalValue::PrivateLinkage, C, "constinit",
+  /* 

[PATCH] D42366: [CodeGen] Fix generation of TBAA tags for may-alias accesses

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Hal, a friendly ping.


Repository:
  rL LLVM

https://reviews.llvm.org/D42366



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D42366: [CodeGen] Fix generation of TBAA tags for may-alias accesses

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Hal, will you please take a look?


Repository:
  rL LLVM

https://reviews.llvm.org/D42366



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D42366: [CodeGen] Fix generation of TBAA tags for may-alias accesses

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added inline comments.



Comment at: lib/CodeGen/CodeGenTBAA.h:67
   /* BaseType= */ nullptr, /* AccessType= */ nullptr,
-  /* Offset= */ 0, /* Size= */ 0);
+  /* Offset= */ 0, /* Size= */ UINT64_MAX);
   }

rjmccall wrote:
> Hmm.  I think you should talk this part over with Hal.  If the size should be 
> ignored then I think it's better to just leave this as 0; it's certainly 
> easier to recognize 0 as a "size unknown" value.
Hal, in D41501 we use UINT64_MAX as the "unknown" size value. Should we do the 
same here?


Repository:
  rL LLVM

https://reviews.llvm.org/D42366



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D41539: [CodeGen] Decorate aggregate accesses with TBAA tags

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC323421: [CodeGen] Decorate aggregate accesses with TBAA tags 
(authored by kosarev, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D41539?vs=131257=131434#toc

Repository:
  rC Clang

https://reviews.llvm.org/D41539

Files:
  lib/CodeGen/CGAtomic.cpp
  lib/CodeGen/CGCall.cpp
  lib/CodeGen/CGClass.cpp
  lib/CodeGen/CGExprAgg.cpp
  lib/CodeGen/CGExprCXX.cpp
  lib/CodeGen/CGObjC.cpp
  lib/CodeGen/CGOpenMPRuntime.cpp
  lib/CodeGen/CGStmt.cpp
  lib/CodeGen/CGStmtOpenMP.cpp
  lib/CodeGen/CodeGenFunction.h
  lib/CodeGen/CodeGenModule.cpp
  lib/CodeGen/CodeGenModule.h
  lib/CodeGen/CodeGenTBAA.cpp
  lib/CodeGen/CodeGenTBAA.h
  lib/CodeGen/ItaniumCXXABI.cpp
  test/CodeGen/tbaa-struct.cpp

Index: test/CodeGen/tbaa-struct.cpp
===
--- test/CodeGen/tbaa-struct.cpp
+++ test/CodeGen/tbaa-struct.cpp
@@ -1,75 +1,129 @@
-// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - -O1 %s | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - -O1 %s | \
+// RUN: FileCheck -check-prefixes=CHECK,CHECK-OLD %s
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -new-struct-path-tbaa \
+// RUN: -emit-llvm -o - -O1 %s | \
+// RUN: FileCheck -check-prefixes=CHECK,CHECK-NEW %s
 //
-// Check that we generate !tbaa.struct metadata for struct copies.
+// Check that we generate TBAA metadata for struct copies correctly.
+
 struct A {
   short s;
   int i;
   char c;
   int j;
 };
 
-void copy(struct A *a, struct A *b) {
-  *a = *b;
-}
+typedef A __attribute__((may_alias)) AA;
 
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 16, i1 false), !tbaa.struct [[TS:!.*]]
+void copy(A *a1, A *a2) {
+// CHECK-LABEL: _Z4copyP1AS0_
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 16, i1 false)
+// CHECK-OLD-SAME: !tbaa.struct [[TS:!.*]]
+// CHECK-NEW-SAME: !tbaa [[TAG_A:![0-9]*]]
+  *a1 = *a2;
+}
 
 struct B {
-  char c1;
-  struct A a;
-  int ii;
+  char c;
+  A a;
+  int i;
 };
 
-void copy2(struct B *a, struct B *b) {
-  *a = *b;
+void copy2(B *b1, B *b2) {
+// CHECK-LABEL: _Z5copy2P1BS0_
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 24, i1 false)
+// CHECK-OLD-SAME: !tbaa.struct [[TS2:!.*]]
+// CHECK-NEW-SAME: !tbaa [[TAG_B:![0-9]*]]
+  *b1 = *b2;
 }
 
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 24, i1 false), !tbaa.struct [[TS2:!.*]]
+struct S {
+  _Complex char cc;
+  _Complex int ci;
+};
 
-typedef _Complex int T2;
-typedef _Complex char T5;
-typedef _Complex int T7;
-typedef struct T4 { T5 field0; T7 field1; } T4;
-typedef union T1 { T2 field0; T4 field1; } T1;
+union U {
+  _Complex int ci;
+  S s;
+};
 
-void copy3 (T1 *a, T1 *b) {
-  *a = *b;
+void copy3(U *u1, U *u2) {
+// CHECK-LABEL: _Z5copy3P1US0_
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 12, i1 false)
+// CHECK-OLD-SAME: !tbaa.struct [[TS3:!.*]]
+// CHECK-NEW-SAME: !tbaa [[TAG_U:![0-9]*]]
+  *u1 = *u2;
 }
 
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 12, i1 false), !tbaa.struct [[TS3:!.*]]
-
 // Make sure that zero-length bitfield works.
-#define ATTR __attribute__ ((ms_struct))
-struct five {
+struct C {
   char a;
-  int :0;/* ignored; prior field is not a bitfield. */
+  int : 0;  // Shall not be ignored; see r185018.
   char b;
   char c;
-} ATTR;
-void copy4(struct five *a, struct five *b) {
-  *a = *b;
+} __attribute__((ms_struct));
+
+void copy4(C *c1, C *c2) {
+// CHECK-LABEL: _Z5copy4P1CS0_
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* {{.*}}, i64 3, i1 false)
+// CHECK-OLD-SAME: !tbaa.struct [[TS4:!.*]]
+// CHECK-NEW-SAME: !tbaa [[TAG_C:![0-9]*]]
+  *c1 = *c2;
 }
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* {{.*}}, i64 3, i1 false), !tbaa.struct [[TS4:!.*]]
 
-struct six {
+struct D {
   char a;
-  int :0;
+  int : 0;
   char b;
   char c;
 };
-void copy5(struct six *a, struct six *b) {
-  *a = *b;
+
+void copy5(D *d1, D *d2) {
+// CHECK-LABEL: _Z5copy5P1DS0_
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* {{.*}}, i64 6, i1 false)
+// CHECK-OLD-SAME: !tbaa.struct [[TS5:!.*]]
+// CHECK-NEW-SAME: !tbaa [[TAG_D:![0-9]*]]
+  *d1 = *d2;
+}
+
+void copy6(AA *a1, A *a2) {
+// CHECK-LABEL: _Z5copy6P1AS0_
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 16, i1 false)
+// CHECK-OLD-SAME: !tbaa.struct [[TS]]
+// CHECK-NEW-SAME: !tbaa [[TAG_char:![0-9]*]]
+  *a1 = *a2;
+}
+
+void copy7(A *a1, AA *a2) {
+// CHECK-LABEL: _Z5copy7P1AS0_
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 16, i1 false)
+// CHECK-OLD-SAME: !tbaa.struct [[TS]]
+// 

[PATCH] D41539: [CodeGen] Decorate aggregate accesses with TBAA tags

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL323421: [CodeGen] Decorate aggregate accesses with TBAA tags 
(authored by kosarev, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D41539?vs=131257=131433#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D41539

Files:
  cfe/trunk/lib/CodeGen/CGAtomic.cpp
  cfe/trunk/lib/CodeGen/CGCall.cpp
  cfe/trunk/lib/CodeGen/CGClass.cpp
  cfe/trunk/lib/CodeGen/CGExprAgg.cpp
  cfe/trunk/lib/CodeGen/CGExprCXX.cpp
  cfe/trunk/lib/CodeGen/CGObjC.cpp
  cfe/trunk/lib/CodeGen/CGOpenMPRuntime.cpp
  cfe/trunk/lib/CodeGen/CGStmt.cpp
  cfe/trunk/lib/CodeGen/CGStmtOpenMP.cpp
  cfe/trunk/lib/CodeGen/CodeGenFunction.h
  cfe/trunk/lib/CodeGen/CodeGenModule.cpp
  cfe/trunk/lib/CodeGen/CodeGenModule.h
  cfe/trunk/lib/CodeGen/CodeGenTBAA.cpp
  cfe/trunk/lib/CodeGen/CodeGenTBAA.h
  cfe/trunk/lib/CodeGen/ItaniumCXXABI.cpp
  cfe/trunk/test/CodeGen/tbaa-struct.cpp

Index: cfe/trunk/test/CodeGen/tbaa-struct.cpp
===
--- cfe/trunk/test/CodeGen/tbaa-struct.cpp
+++ cfe/trunk/test/CodeGen/tbaa-struct.cpp
@@ -1,75 +1,129 @@
-// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - -O1 %s | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - -O1 %s | \
+// RUN: FileCheck -check-prefixes=CHECK,CHECK-OLD %s
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -new-struct-path-tbaa \
+// RUN: -emit-llvm -o - -O1 %s | \
+// RUN: FileCheck -check-prefixes=CHECK,CHECK-NEW %s
 //
-// Check that we generate !tbaa.struct metadata for struct copies.
+// Check that we generate TBAA metadata for struct copies correctly.
+
 struct A {
   short s;
   int i;
   char c;
   int j;
 };
 
-void copy(struct A *a, struct A *b) {
-  *a = *b;
-}
+typedef A __attribute__((may_alias)) AA;
 
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 16, i1 false), !tbaa.struct [[TS:!.*]]
+void copy(A *a1, A *a2) {
+// CHECK-LABEL: _Z4copyP1AS0_
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 16, i1 false)
+// CHECK-OLD-SAME: !tbaa.struct [[TS:!.*]]
+// CHECK-NEW-SAME: !tbaa [[TAG_A:![0-9]*]]
+  *a1 = *a2;
+}
 
 struct B {
-  char c1;
-  struct A a;
-  int ii;
+  char c;
+  A a;
+  int i;
 };
 
-void copy2(struct B *a, struct B *b) {
-  *a = *b;
+void copy2(B *b1, B *b2) {
+// CHECK-LABEL: _Z5copy2P1BS0_
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 24, i1 false)
+// CHECK-OLD-SAME: !tbaa.struct [[TS2:!.*]]
+// CHECK-NEW-SAME: !tbaa [[TAG_B:![0-9]*]]
+  *b1 = *b2;
 }
 
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 24, i1 false), !tbaa.struct [[TS2:!.*]]
+struct S {
+  _Complex char cc;
+  _Complex int ci;
+};
 
-typedef _Complex int T2;
-typedef _Complex char T5;
-typedef _Complex int T7;
-typedef struct T4 { T5 field0; T7 field1; } T4;
-typedef union T1 { T2 field0; T4 field1; } T1;
+union U {
+  _Complex int ci;
+  S s;
+};
 
-void copy3 (T1 *a, T1 *b) {
-  *a = *b;
+void copy3(U *u1, U *u2) {
+// CHECK-LABEL: _Z5copy3P1US0_
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 12, i1 false)
+// CHECK-OLD-SAME: !tbaa.struct [[TS3:!.*]]
+// CHECK-NEW-SAME: !tbaa [[TAG_U:![0-9]*]]
+  *u1 = *u2;
 }
 
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 12, i1 false), !tbaa.struct [[TS3:!.*]]
-
 // Make sure that zero-length bitfield works.
-#define ATTR __attribute__ ((ms_struct))
-struct five {
+struct C {
   char a;
-  int :0;/* ignored; prior field is not a bitfield. */
+  int : 0;  // Shall not be ignored; see r185018.
   char b;
   char c;
-} ATTR;
-void copy4(struct five *a, struct five *b) {
-  *a = *b;
+} __attribute__((ms_struct));
+
+void copy4(C *c1, C *c2) {
+// CHECK-LABEL: _Z5copy4P1CS0_
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* {{.*}}, i64 3, i1 false)
+// CHECK-OLD-SAME: !tbaa.struct [[TS4:!.*]]
+// CHECK-NEW-SAME: !tbaa [[TAG_C:![0-9]*]]
+  *c1 = *c2;
 }
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* {{.*}}, i64 3, i1 false), !tbaa.struct [[TS4:!.*]]
 
-struct six {
+struct D {
   char a;
-  int :0;
+  int : 0;
   char b;
   char c;
 };
-void copy5(struct six *a, struct six *b) {
-  *a = *b;
+
+void copy5(D *d1, D *d2) {
+// CHECK-LABEL: _Z5copy5P1DS0_
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* {{.*}}, i64 6, i1 false)
+// CHECK-OLD-SAME: !tbaa.struct [[TS5:!.*]]
+// CHECK-NEW-SAME: !tbaa [[TAG_D:![0-9]*]]
+  *d1 = *d2;
+}
+
+void copy6(AA *a1, A *a2) {
+// CHECK-LABEL: _Z5copy6P1AS0_
+// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 %{{.*}}, i8* align 4 %{{.*}}, i64 16, i1 false)
+// CHECK-OLD-SAME: !tbaa.struct [[TS]]
+// CHECK-NEW-SAME: !tbaa [[TAG_char:![0-9]*]]
+  

[PATCH] D41539: [CodeGen] Decorate aggregate accesses with TBAA tags

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 131257.
kosarev added a comment.

The copying functions changed to take LValues. It seems Address-taking versions 
are not very useful so we don't bother with overloading.


https://reviews.llvm.org/D41539

Files:
  lib/CodeGen/CGAtomic.cpp
  lib/CodeGen/CGCall.cpp
  lib/CodeGen/CGClass.cpp
  lib/CodeGen/CGExprAgg.cpp
  lib/CodeGen/CGExprCXX.cpp
  lib/CodeGen/CGObjC.cpp
  lib/CodeGen/CGOpenMPRuntime.cpp
  lib/CodeGen/CGStmt.cpp
  lib/CodeGen/CGStmtOpenMP.cpp
  lib/CodeGen/CodeGenFunction.h
  lib/CodeGen/CodeGenModule.cpp
  lib/CodeGen/CodeGenModule.h
  lib/CodeGen/CodeGenTBAA.cpp
  lib/CodeGen/CodeGenTBAA.h
  lib/CodeGen/ItaniumCXXABI.cpp
  test/CodeGen/tbaa-struct.cpp

Index: test/CodeGen/tbaa-struct.cpp
===
--- test/CodeGen/tbaa-struct.cpp
+++ test/CodeGen/tbaa-struct.cpp
@@ -1,75 +1,122 @@
-// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - -O1 %s | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - -O1 %s | \
+// RUN: FileCheck -check-prefixes=CHECK,CHECK-OLD %s
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -new-struct-path-tbaa \
+// RUN: -emit-llvm -o - -O1 %s | \
+// RUN: FileCheck -check-prefixes=CHECK,CHECK-NEW %s
 //
-// Check that we generate !tbaa.struct metadata for struct copies.
+// Check that we generate TBAA metadata for struct copies correctly.
+
 struct A {
   short s;
   int i;
   char c;
   int j;
 };
 
-void copy(struct A *a, struct A *b) {
-  *a = *b;
-}
+typedef A __attribute__((may_alias)) AA;
 
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 16, i32 4, i1 false), !tbaa.struct [[TS:!.*]]
+void copy(A *a1, A *a2) {
+// CHECK-LABEL: _Z4copyP1AS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_A:![0-9]*]]
+  *a1 = *a2;
+}
 
 struct B {
-  char c1;
-  struct A a;
-  int ii;
+  char c;
+  A a;
+  int i;
 };
 
-void copy2(struct B *a, struct B *b) {
-  *a = *b;
+void copy2(B *b1, B *b2) {
+// CHECK-LABEL: _Z5copy2P1BS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS2:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_B:![0-9]*]]
+  *b1 = *b2;
 }
 
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 24, i32 4, i1 false), !tbaa.struct [[TS2:!.*]]
+struct S {
+  _Complex char cc;
+  _Complex int ci;
+};
 
-typedef _Complex int T2;
-typedef _Complex char T5;
-typedef _Complex int T7;
-typedef struct T4 { T5 field0; T7 field1; } T4;
-typedef union T1 { T2 field0; T4 field1; } T1;
+union U {
+  _Complex int ci;
+  S s;
+};
 
-void copy3 (T1 *a, T1 *b) {
-  *a = *b;
+void copy3(U *u1, U *u2) {
+// CHECK-LABEL: _Z5copy3P1US0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS3:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_U:![0-9]*]]
+  *u1 = *u2;
 }
 
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 12, i32 4, i1 false), !tbaa.struct [[TS3:!.*]]
-
 // Make sure that zero-length bitfield works.
-#define ATTR __attribute__ ((ms_struct))
-struct five {
+struct C {
   char a;
-  int :0;/* ignored; prior field is not a bitfield. */
+  int : 0;  // Shall not be ignored; see r185018.
   char b;
   char c;
-} ATTR;
-void copy4(struct five *a, struct five *b) {
-  *a = *b;
+} __attribute__((ms_struct));
+
+void copy4(C *c1, C *c2) {
+// CHECK-LABEL: _Z5copy4P1CS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS4:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_C:![0-9]*]]
+  *c1 = *c2;
 }
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 3, i32 1, i1 false), !tbaa.struct [[TS4:!.*]]
 
-struct six {
+struct D {
   char a;
-  int :0;
+  int : 0;
   char b;
   char c;
 };
-void copy5(struct six *a, struct six *b) {
-  *a = *b;
+
+void copy5(D *d1, D *d2) {
+// CHECK-LABEL: _Z5copy5P1DS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS5:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_D:![0-9]*]]
+  *d1 = *d2;
+}
+
+void copy6(AA *a1, A *a2) {
+// CHECK-LABEL: _Z5copy6P1AS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_char:![0-9]*]]
+  *a1 = *a2;
+}
+
+void copy7(A *a1, AA *a2) {
+// CHECK-LABEL: _Z5copy7P1AS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_char]]
+  *a1 = *a2;
 }
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 6, i32 1, i1 false), !tbaa.struct [[TS5:!.*]]
 
-// CHECK: [[TS]] = !{i64 0, i64 2, !{{.*}}, i64 4, i64 4, !{{.*}}, i64 8, i64 1, !{{.*}}, i64 12, i64 4, !{{.*}}}
-// CHECK: [[CHAR:!.*]] = !{!"omnipotent char", !{{.*}}}
-// CHECK: [[TAG_INT:!.*]] = !{[[INT:!.*]], [[INT]], i64 0}
-// CHECK: [[INT]] = !{!"int", [[CHAR]]
-// CHECK: 

[PATCH] D41539: [CodeGen] Decorate aggregate accesses with TBAA tags

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 130599.
kosarev added a comment.

- Supported propagation of TBAA info for aggregate transfers.
- Added tests on copying of `may_alias` aggregates.


https://reviews.llvm.org/D41539

Files:
  lib/CodeGen/CGAtomic.cpp
  lib/CodeGen/CGCall.cpp
  lib/CodeGen/CGClass.cpp
  lib/CodeGen/CGExprAgg.cpp
  lib/CodeGen/CGExprCXX.cpp
  lib/CodeGen/CGObjC.cpp
  lib/CodeGen/CGOpenMPRuntime.cpp
  lib/CodeGen/CGStmt.cpp
  lib/CodeGen/CGStmtOpenMP.cpp
  lib/CodeGen/CodeGenFunction.h
  lib/CodeGen/CodeGenModule.cpp
  lib/CodeGen/CodeGenModule.h
  lib/CodeGen/CodeGenTBAA.cpp
  lib/CodeGen/CodeGenTBAA.h
  lib/CodeGen/ItaniumCXXABI.cpp
  test/CodeGen/tbaa-struct.cpp

Index: test/CodeGen/tbaa-struct.cpp
===
--- test/CodeGen/tbaa-struct.cpp
+++ test/CodeGen/tbaa-struct.cpp
@@ -1,75 +1,122 @@
-// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - -O1 %s | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - -O1 %s | \
+// RUN: FileCheck -check-prefixes=CHECK,CHECK-OLD %s
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -new-struct-path-tbaa \
+// RUN: -emit-llvm -o - -O1 %s | \
+// RUN: FileCheck -check-prefixes=CHECK,CHECK-NEW %s
 //
-// Check that we generate !tbaa.struct metadata for struct copies.
+// Check that we generate TBAA metadata for struct copies correctly.
+
 struct A {
   short s;
   int i;
   char c;
   int j;
 };
 
-void copy(struct A *a, struct A *b) {
-  *a = *b;
-}
+typedef A __attribute__((may_alias)) AA;
 
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 16, i32 4, i1 false), !tbaa.struct [[TS:!.*]]
+void copy(A *a1, A *a2) {
+// CHECK-LABEL: _Z4copyP1AS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_A:![0-9]*]]
+  *a1 = *a2;
+}
 
 struct B {
-  char c1;
-  struct A a;
-  int ii;
+  char c;
+  A a;
+  int i;
 };
 
-void copy2(struct B *a, struct B *b) {
-  *a = *b;
+void copy2(B *b1, B *b2) {
+// CHECK-LABEL: _Z5copy2P1BS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS2:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_B:![0-9]*]]
+  *b1 = *b2;
 }
 
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 24, i32 4, i1 false), !tbaa.struct [[TS2:!.*]]
+struct S {
+  _Complex char cc;
+  _Complex int ci;
+};
 
-typedef _Complex int T2;
-typedef _Complex char T5;
-typedef _Complex int T7;
-typedef struct T4 { T5 field0; T7 field1; } T4;
-typedef union T1 { T2 field0; T4 field1; } T1;
+union U {
+  _Complex int ci;
+  S s;
+};
 
-void copy3 (T1 *a, T1 *b) {
-  *a = *b;
+void copy3(U *u1, U *u2) {
+// CHECK-LABEL: _Z5copy3P1US0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS3:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_U:![0-9]*]]
+  *u1 = *u2;
 }
 
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 12, i32 4, i1 false), !tbaa.struct [[TS3:!.*]]
-
 // Make sure that zero-length bitfield works.
-#define ATTR __attribute__ ((ms_struct))
-struct five {
+struct C {
   char a;
-  int :0;/* ignored; prior field is not a bitfield. */
+  int : 0;  // Shall not be ignored; see r185018.
   char b;
   char c;
-} ATTR;
-void copy4(struct five *a, struct five *b) {
-  *a = *b;
+} __attribute__((ms_struct));
+
+void copy4(C *c1, C *c2) {
+// CHECK-LABEL: _Z5copy4P1CS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS4:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_C:![0-9]*]]
+  *c1 = *c2;
 }
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 3, i32 1, i1 false), !tbaa.struct [[TS4:!.*]]
 
-struct six {
+struct D {
   char a;
-  int :0;
+  int : 0;
   char b;
   char c;
 };
-void copy5(struct six *a, struct six *b) {
-  *a = *b;
+
+void copy5(D *d1, D *d2) {
+// CHECK-LABEL: _Z5copy5P1DS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS5:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_D:![0-9]*]]
+  *d1 = *d2;
+}
+
+void copy6(AA *a1, A *a2) {
+// CHECK-LABEL: _Z5copy6P1AS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_char:![0-9]*]]
+  *a1 = *a2;
+}
+
+void copy7(A *a1, AA *a2) {
+// CHECK-LABEL: _Z5copy7P1AS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_char]]
+  *a1 = *a2;
 }
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 6, i32 1, i1 false), !tbaa.struct [[TS5:!.*]]
 
-// CHECK: [[TS]] = !{i64 0, i64 2, !{{.*}}, i64 4, i64 4, !{{.*}}, i64 8, i64 1, !{{.*}}, i64 12, i64 4, !{{.*}}}
-// CHECK: [[CHAR:!.*]] = !{!"omnipotent char", !{{.*}}}
-// CHECK: [[TAG_INT:!.*]] = !{[[INT:!.*]], [[INT]], i64 0}
-// CHECK: [[INT]] = !{!"int", [[CHAR]]
-// CHECK: [[TAG_CHAR:!.*]] = !{[[CHAR]], 

[PATCH] D41539: [CodeGen] Decorate aggregate accesses with TBAA tags

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

OK, I'm reading your response so that this patch may significantly increase the 
number of cases where we propagate TBAA tags from memory-transfer intrinsic 
calls, which means potentially more cases where ignoring may_alias would lead 
to problems. If so, then I tend to agree. Will prepare another version. Thanks.


https://reviews.llvm.org/D41539



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D41539: [CodeGen] Decorate aggregate accesses with TBAA tags

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Sure, but since it is not a trivial change we could first replace 'tbaa.struct' 
with 'tbaa' and then decide how to attach multiple TBAA tags to an instruction. 
I didn't think enough about it, but one way to do that is to have different 
kinds of TBAA tags for read and write accesses, in which case we could 
re-purpose the 'tbaa.struct' tag slot.


https://reviews.llvm.org/D41539



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D41562: [CodeGen] Generate TBAA info on passing arguments and returning values

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added reviewers: rjmccall, hfinkel.
kosarev added a project: clang.

We only do this for the new format as the old format does not allow to 
represent accesses to aggregates. This patch significantly improves TBAA 
coverage on -O1 builds.


Repository:
  rL LLVM

https://reviews.llvm.org/D41562

Files:
  lib/CodeGen/CGCall.cpp
  test/CodeGen/tbaa-call.cpp

Index: test/CodeGen/tbaa-call.cpp
===
--- test/CodeGen/tbaa-call.cpp
+++ test/CodeGen/tbaa-call.cpp
@@ -0,0 +1,110 @@
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -disable-llvm-passes \
+// RUN: -new-struct-path-tbaa %s -emit-llvm -o - | FileCheck %s
+//
+// Check that we generate correct TBAA information for instructions that pass
+// function arguments and returning values.
+
+struct A { int : 0; };
+struct B { double d; };
+struct C { A a; B b; };
+struct D { int i; };
+struct E { double d; int i; };
+struct F { float _Complex c; int x; };
+struct G { E e; };
+
+B get_B();
+C get_C();
+D get_D();
+E get_E();
+F get_F();
+
+void set_E(E);
+
+C f1() {
+// CHECK-LABEL: _Z2f1v
+// CHECK: load double, {{.*}}, !tbaa [[TAG_C:!.*]]
+  return C();
+}
+
+D f2() {
+// CHECK-LABEL: _Z2f2v
+// CHECK: load i32, {{.*}}, !tbaa [[TAG_D:!.*]]
+  return D();
+}
+
+E f3() {
+// CHECK-LABEL: _Z2f3v
+// CHECK: load { double, i32 }, {{.*}}, !tbaa [[TAG_E:!.*]]
+  return E();
+}
+
+E f4() {
+// CHECK-LABEL: _Z2f4v
+// CHECK: call { double, i32 } @_Z5get_Ev()
+// CHECK-DAG: store double {{.*}}, !tbaa [[TAG_E]]
+// CHECK-DAG: store i32 {{.*}}, !tbaa [[TAG_E]]
+// CHECK: load { double, i32 }, {{.*}}, !tbaa [[TAG_E]]
+  return get_E();
+}
+
+B f5() {
+// CHECK-LABEL: _Z2f5v
+// CHECK: call double @_Z5get_Bv()
+// CHECK: store double {{.*}}, !tbaa [[TAG_B:!.*]]
+// CHECK: load double, {{.*}}, !tbaa [[TAG_B]]
+  return get_B();
+}
+
+C f6() {
+// CHECK-LABEL: _Z2f6v
+// CHECK: call double @_Z5get_Cv()
+// CHECK: store double {{.*}}, !tbaa [[TAG_C]]
+// CHECK: load double, {{.*}}, !tbaa [[TAG_C]]
+  return get_C();
+}
+
+D f7() {
+// CHECK-LABEL: _Z2f7v
+// CHECK: call i32 @_Z5get_Dv()
+// CHECK: store i32 {{.*}}, !tbaa [[TAG_D]]
+// CHECK: load i32, {{.*}}, !tbaa [[TAG_D]]
+  return get_D();
+}
+
+F f8() {
+// CHECK-LABEL: _Z2f8v
+// CHECK: call { <2 x float>, i32 } @_Z5get_Fv()
+// CHECK: store { <2 x float>, i32 } {{.*}}, !tbaa [[TAG_F:!.*]]
+// CHECK: load { <2 x float>, i32 }, {{.*}}, !tbaa [[TAG_F]]
+  return get_F();
+}
+
+G f9(G g) {
+// CHECK-LABEL: _Z2f91G
+// CHECK-DAG: store double {{.*}}, !tbaa [[TAG_G:!.*]]
+// CHECK-DAG: store i32 {{.*}}, !tbaa [[TAG_G]]
+// CHECK: load { double, i32 }, {{.*}}, !tbaa [[TAG_G]]
+  return g;
+}
+
+void f10() {
+// CHECK-LABEL: _Z3f10v
+// CHECK-DAG: load double, {{.*}}, !tbaa [[TAG_E]]
+// CHECK-DAG: load i32, {{.*}}, !tbaa [[TAG_E]]
+// CHECK: call void @_Z5set_E1E
+  E e;
+  set_E(e);
+}
+
+// CHECK-DAG: [[TYPE_B:!.*]] = !{{{.*}}, !"_ZTS1B", {{.*}}}
+// CHECK-DAG: [[TAG_B]] = !{[[TYPE_B]], [[TYPE_B]], {{.*}}}
+// CHECK-DAG: [[TYPE_C:!.*]] = !{{{.*}}, !"_ZTS1C", {{.*}}}
+// CHECK-DAG: [[TAG_C]] = !{[[TYPE_C]], [[TYPE_C]], {{.*}}}
+// CHECK-DAG: [[TYPE_D:!.*]] = !{{{.*}}, !"_ZTS1D", {{.*}}}
+// CHECK-DAG: [[TAG_D]] = !{[[TYPE_D]], [[TYPE_D]], {{.*}}}
+// CHECK-DAG: [[TYPE_E:!.*]] = !{{{.*}}, !"_ZTS1E", {{.*}}}
+// CHECK-DAG: [[TAG_E]] = !{[[TYPE_E]], [[TYPE_E]], {{.*}}}
+// CHECK-DAG: [[TYPE_F:!.*]] = !{{{.*}}, !"_ZTS1F", {{.*}}}
+// CHECK-DAG: [[TAG_F]] = !{[[TYPE_F]], [[TYPE_F]], {{.*}}}
+// CHECK-DAG: [[TYPE_G:!.*]] = !{{{.*}}, !"_ZTS1G", {{.*}}}
+// CHECK-DAG: [[TAG_G]] = !{[[TYPE_G]], [[TYPE_G]], {{.*}}}
Index: lib/CodeGen/CGCall.cpp
===
--- lib/CodeGen/CGCall.cpp
+++ lib/CodeGen/CGCall.cpp
@@ -1195,12 +1195,16 @@
 /// destination type; in this situation the values of bits which not
 /// present in the src are undefined.
 static llvm::Value *CreateCoercedLoad(Address Src, llvm::Type *Ty,
+  TBAAAccessInfo TBAAInfo,
   CodeGenFunction ) {
   llvm::Type *SrcTy = Src.getElementType();
 
   // If SrcTy and Ty are the same, just do a load.
-  if (SrcTy == Ty)
-return CGF.Builder.CreateLoad(Src);
+  if (SrcTy == Ty) {
+auto *Load = CGF.Builder.CreateLoad(Src);
+CGF.CGM.DecorateInstructionWithTBAA(Load, TBAAInfo);
+return Load;
+  }
 
   uint64_t DstSize = CGF.CGM.getDataLayout().getTypeAllocSize(Ty);
 
@@ -1215,7 +1219,8 @@
   // extension or truncation to the desired type.
   if ((isa(Ty) || isa(Ty)) &&
   (isa(SrcTy) || isa(SrcTy))) {
-llvm::Value *Load = CGF.Builder.CreateLoad(Src);
+auto *Load = CGF.Builder.CreateLoad(Src);
+CGF.CGM.DecorateInstructionWithTBAA(Load, TBAAInfo);
 return CoerceIntOrPtrToIntOrPtr(Load, Ty, CGF);
   }
 
@@ -1229,7 +1234,9 @@
 // to that information.
 Src = CGF.Builder.CreateBitCast(Src,
 

[PATCH] D41547: [CodeGen] Fix TBAA info for accesses to members of base classes

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added reviewers: rjmccall, hfinkel.
kosarev added a project: clang.

Resolves:
Bug 35724 - regression (r315984): fatal error: error in backend: Broken 
function found (Did not see access type in access path!)
https://bugs.llvm.org/show_bug.cgi?id=35724


Repository:
  rL LLVM

https://reviews.llvm.org/D41547

Files:
  lib/CodeGen/CGExpr.cpp
  test/CodeGen/tbaa-base.cpp


Index: test/CodeGen/tbaa-base.cpp
===
--- test/CodeGen/tbaa-base.cpp
+++ test/CodeGen/tbaa-base.cpp
@@ -0,0 +1,53 @@
+// RUN: %clang_cc1 -triple x86_64-linux-gnu -O1 %s -emit-llvm -o - | FileCheck 
%s
+//
+// Test generating of TBAA metadata for accesses to members of base classes.
+
+struct A {
+  int x, y, z;
+};
+
+struct B : A {
+  int i;
+};
+
+struct C {
+  int i;
+  B b;
+  int j;
+};
+
+int f1(B *b) {
+// CHECK-LABEL: _Z2f1P1B
+// CHECK: load i32, {{.*}}, !tbaa [[TAG_A_y:!.*]]
+  return b->y;
+}
+
+int f2(C *c) {
+// CHECK-LABEL: _Z2f2P1C
+// CHECK: load i32, {{.*}}, !tbaa [[TAG_A_y]]
+  return (&(c->b))->y;
+}
+
+struct D : virtual A
+{};
+
+struct E {
+  D d;
+};
+
+int f3(D *d) {
+// CHECK-LABEL: _Z2f3P1D
+// CHECK: load i32, {{.*}}, !tbaa [[TAG_A_y]]
+  return d->y;
+}
+
+int f4(E *e) {
+// CHECK-LABEL: _Z2f4P1E
+// CHECK: load i32, {{.*}}, !tbaa [[TAG_A_y]]
+  return (&(e->d))->y;
+}
+
+// CHECK-DAG: [[TYPE_char:!.*]] = !{!"omnipotent char", {{.*}}, i64 0}
+// CHECK-DAG: [[TYPE_int:!.*]] = !{!"int", [[TYPE_char]], i64 0}
+// CHECK-DAG: [[TYPE_A:!.*]] = !{!"_ZTS1A", [[TYPE_int]], i64 0, [[TYPE_int]], 
i64 4, [[TYPE_int]], i64 8}
+// CHECK-DAG: [[TAG_A_y]] = !{[[TYPE_A]], [[TYPE_int]], i64 4}
Index: lib/CodeGen/CGExpr.cpp
===
--- lib/CodeGen/CGExpr.cpp
+++ lib/CodeGen/CGExpr.cpp
@@ -1034,8 +1034,12 @@
 // Derived-to-base conversions.
 case CK_UncheckedDerivedToBase:
 case CK_DerivedToBase: {
-  Address Addr = EmitPointerWithAlignment(CE->getSubExpr(), BaseInfo,
-  TBAAInfo);
+  // TODO: Support accesses to members of base classes in TBAA. For now, we
+  // conservatively pretend that the complete object is of the base class
+  // type.
+  if (TBAAInfo)
+*TBAAInfo = CGM.getTBAAAccessInfo(E->getType());
+  Address Addr = EmitPointerWithAlignment(CE->getSubExpr(), BaseInfo);
   auto Derived = CE->getSubExpr()->getType()->getPointeeCXXRecordDecl();
   return GetAddressOfBaseClass(Addr, Derived,
CE->path_begin(), CE->path_end(),


Index: test/CodeGen/tbaa-base.cpp
===
--- test/CodeGen/tbaa-base.cpp
+++ test/CodeGen/tbaa-base.cpp
@@ -0,0 +1,53 @@
+// RUN: %clang_cc1 -triple x86_64-linux-gnu -O1 %s -emit-llvm -o - | FileCheck %s
+//
+// Test generating of TBAA metadata for accesses to members of base classes.
+
+struct A {
+  int x, y, z;
+};
+
+struct B : A {
+  int i;
+};
+
+struct C {
+  int i;
+  B b;
+  int j;
+};
+
+int f1(B *b) {
+// CHECK-LABEL: _Z2f1P1B
+// CHECK: load i32, {{.*}}, !tbaa [[TAG_A_y:!.*]]
+  return b->y;
+}
+
+int f2(C *c) {
+// CHECK-LABEL: _Z2f2P1C
+// CHECK: load i32, {{.*}}, !tbaa [[TAG_A_y]]
+  return (&(c->b))->y;
+}
+
+struct D : virtual A
+{};
+
+struct E {
+  D d;
+};
+
+int f3(D *d) {
+// CHECK-LABEL: _Z2f3P1D
+// CHECK: load i32, {{.*}}, !tbaa [[TAG_A_y]]
+  return d->y;
+}
+
+int f4(E *e) {
+// CHECK-LABEL: _Z2f4P1E
+// CHECK: load i32, {{.*}}, !tbaa [[TAG_A_y]]
+  return (&(e->d))->y;
+}
+
+// CHECK-DAG: [[TYPE_char:!.*]] = !{!"omnipotent char", {{.*}}, i64 0}
+// CHECK-DAG: [[TYPE_int:!.*]] = !{!"int", [[TYPE_char]], i64 0}
+// CHECK-DAG: [[TYPE_A:!.*]] = !{!"_ZTS1A", [[TYPE_int]], i64 0, [[TYPE_int]], i64 4, [[TYPE_int]], i64 8}
+// CHECK-DAG: [[TAG_A_y]] = !{[[TYPE_A]], [[TYPE_int]], i64 4}
Index: lib/CodeGen/CGExpr.cpp
===
--- lib/CodeGen/CGExpr.cpp
+++ lib/CodeGen/CGExpr.cpp
@@ -1034,8 +1034,12 @@
 // Derived-to-base conversions.
 case CK_UncheckedDerivedToBase:
 case CK_DerivedToBase: {
-  Address Addr = EmitPointerWithAlignment(CE->getSubExpr(), BaseInfo,
-  TBAAInfo);
+  // TODO: Support accesses to members of base classes in TBAA. For now, we
+  // conservatively pretend that the complete object is of the base class
+  // type.
+  if (TBAAInfo)
+*TBAAInfo = CGM.getTBAAAccessInfo(E->getType());
+  Address Addr = EmitPointerWithAlignment(CE->getSubExpr(), BaseInfo);
   auto Derived = CE->getSubExpr()->getType()->getPointeeCXXRecordDecl();
   return GetAddressOfBaseClass(Addr, Derived,
CE->path_begin(), CE->path_end(),
___
cfe-commits mailing list
cfe-commits@lists.llvm.org

[PATCH] D41539: [CodeGen] Decorate aggregate accesses with TBAA tags

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 128017.
kosarev added a comment.

Reworked to not add another test file.


https://reviews.llvm.org/D41539

Files:
  lib/CodeGen/CGExprAgg.cpp
  test/CodeGen/tbaa-struct.cpp

Index: test/CodeGen/tbaa-struct.cpp
===
--- test/CodeGen/tbaa-struct.cpp
+++ test/CodeGen/tbaa-struct.cpp
@@ -1,75 +1,105 @@
-// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - -O1 %s | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -emit-llvm -o - -O1 %s | \
+// RUN: FileCheck -check-prefixes=CHECK,CHECK-OLD %s
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -new-struct-path-tbaa \
+// RUN: -emit-llvm -o - -O1 %s | \
+// RUN: FileCheck -check-prefixes=CHECK,CHECK-NEW %s
 //
-// Check that we generate !tbaa.struct metadata for struct copies.
+// Check that we generate TBAA metadata for struct copies correctly.
+
 struct A {
   short s;
   int i;
   char c;
   int j;
 };
 
-void copy(struct A *a, struct A *b) {
-  *a = *b;
+void copy(A *a1, A *a2) {
+// CHECK-LABEL: _Z4copyP1AS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_A:![0-9]*]]
+  *a1 = *a2;
 }
 
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 16, i32 4, i1 false), !tbaa.struct [[TS:!.*]]
-
 struct B {
-  char c1;
-  struct A a;
-  int ii;
+  char c;
+  A a;
+  int i;
 };
 
-void copy2(struct B *a, struct B *b) {
-  *a = *b;
+void copy2(B *b1, B *b2) {
+// CHECK-LABEL: _Z5copy2P1BS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS2:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_B:![0-9]*]]
+  *b1 = *b2;
 }
 
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 24, i32 4, i1 false), !tbaa.struct [[TS2:!.*]]
+struct S {
+  _Complex char cc;
+  _Complex int ci;
+};
 
-typedef _Complex int T2;
-typedef _Complex char T5;
-typedef _Complex int T7;
-typedef struct T4 { T5 field0; T7 field1; } T4;
-typedef union T1 { T2 field0; T4 field1; } T1;
+union U {
+  _Complex int ci;
+  S s;
+};
 
-void copy3 (T1 *a, T1 *b) {
-  *a = *b;
+void copy3(U *u1, U *u2) {
+// CHECK-LABEL: _Z5copy3P1US0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS3:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_U:![0-9]*]]
+  *u1 = *u2;
 }
 
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 12, i32 4, i1 false), !tbaa.struct [[TS3:!.*]]
-
 // Make sure that zero-length bitfield works.
-#define ATTR __attribute__ ((ms_struct))
-struct five {
+struct C {
   char a;
-  int :0;/* ignored; prior field is not a bitfield. */
+  int : 0;  // Shall not be ignored; see r185018.
   char b;
   char c;
-} ATTR;
-void copy4(struct five *a, struct five *b) {
-  *a = *b;
+} __attribute__((ms_struct));
+
+void copy4(C *c1, C *c2) {
+// CHECK-LABEL: _Z5copy4P1CS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS4:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_C:![0-9]*]]
+  *c1 = *c2;
 }
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 3, i32 1, i1 false), !tbaa.struct [[TS4:!.*]]
 
-struct six {
+struct D {
   char a;
-  int :0;
+  int : 0;
   char b;
   char c;
 };
-void copy5(struct six *a, struct six *b) {
-  *a = *b;
+
+void copy5(D *d1, D *d2) {
+// CHECK-LABEL: _Z5copy5P1DS0_
+// CHECK-OLD: call void @llvm.memcpy{{.*}}, !tbaa.struct [[TS5:!.*]]
+// CHECK-NEW: call void @llvm.memcpy{{.*}}, !tbaa [[TAG_D:![0-9]*]]
+  *d1 = *d2;
 }
-// CHECK: call void @llvm.memcpy.p0i8.p0i8.i64(i8* %{{.*}}, i8* %{{.*}}, i64 6, i32 1, i1 false), !tbaa.struct [[TS5:!.*]]
 
-// CHECK: [[TS]] = !{i64 0, i64 2, !{{.*}}, i64 4, i64 4, !{{.*}}, i64 8, i64 1, !{{.*}}, i64 12, i64 4, !{{.*}}}
-// CHECK: [[CHAR:!.*]] = !{!"omnipotent char", !{{.*}}}
-// CHECK: [[TAG_INT:!.*]] = !{[[INT:!.*]], [[INT]], i64 0}
-// CHECK: [[INT]] = !{!"int", [[CHAR]]
-// CHECK: [[TAG_CHAR:!.*]] = !{[[CHAR]], [[CHAR]], i64 0}
+// CHECK-OLD: [[TS]] = !{i64 0, i64 2, !{{.*}}, i64 4, i64 4, !{{.*}}, i64 8, i64 1, !{{.*}}, i64 12, i64 4, !{{.*}}}
+// CHECK-OLD: [[CHAR:!.*]] = !{!"omnipotent char", !{{.*}}}
+// CHECK-OLD: [[TAG_INT:!.*]] = !{[[INT:!.*]], [[INT]], i64 0}
+// CHECK-OLD: [[INT]] = !{!"int", [[CHAR]]
+// CHECK-OLD: [[TAG_CHAR:!.*]] = !{[[CHAR]], [[CHAR]], i64 0}
 // (offset, size) = (0,1) char; (4,2) short; (8,4) int; (12,1) char; (16,4) int; (20,4) int
-// CHECK: [[TS2]] = !{i64 0, i64 1, !{{.*}}, i64 4, i64 2, !{{.*}}, i64 8, i64 4, !{{.*}}, i64 12, i64 1, !{{.*}}, i64 16, i64 4, {{.*}}, i64 20, i64 4, {{.*}}}
+// CHECK-OLD: [[TS2]] = !{i64 0, i64 1, !{{.*}}, i64 4, i64 2, !{{.*}}, i64 8, i64 4, !{{.*}}, i64 12, i64 1, !{{.*}}, i64 16, i64 4, {{.*}}, i64 20, i64 4, {{.*}}}
 // (offset, size) = (0,8) char; (0,2) char; (4,8) char
-// CHECK: [[TS3]] = !{i64 0, i64 8, !{{.*}}, i64 0, i64 2, !{{.*}}, i64 4, i64 8, !{{.*}}}
-// CHECK: [[TS4]] = 

[PATCH] D41399: [CodeGen] Represent array members in new-format TBAA type descriptors

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL321352: [CodeGen] Represent array members in new-format TBAA 
type descriptors (authored by kosarev, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D41399?vs=127742=127994#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D41399

Files:
  cfe/trunk/lib/CodeGen/CodeGenTBAA.cpp
  cfe/trunk/test/CodeGen/tbaa-array.cpp


Index: cfe/trunk/test/CodeGen/tbaa-array.cpp
===
--- cfe/trunk/test/CodeGen/tbaa-array.cpp
+++ cfe/trunk/test/CodeGen/tbaa-array.cpp
@@ -1,18 +1,52 @@
 // RUN: %clang_cc1 -triple x86_64-linux -O1 -disable-llvm-passes %s \
 // RUN: -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-linux -O1 -disable-llvm-passes %s \
+// RUN: -new-struct-path-tbaa -emit-llvm -o - | \
+// RUN: FileCheck -check-prefix=CHECK-NEW %s
 //
 // Check that we generate correct TBAA information for accesses to array
 // elements.
 
 struct A { int i; };
 struct B { A a[1]; };
+struct C { int i; int x[3]; };
 
 int foo(B *b) {
 // CHECK-LABEL: _Z3fooP1B
 // CHECK: load i32, {{.*}}, !tbaa [[TAG_A_i:!.*]]
+// CHECK-NEW-LABEL: _Z3fooP1B
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_A_i:!.*]]
   return b->a->i;
 }
 
+// Check that members of array types are represented correctly.
+int bar(C *c) {
+// CHECK-NEW-LABEL: _Z3barP1C
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_C_i:!.*]]
+  return c->i;
+}
+
+int bar2(C *c) {
+// CHECK-NEW-LABEL: _Z4bar2P1C
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_int:!.*]]
+  return c->x[2];
+}
+
+int bar3(C *c, int j) {
+// CHECK-NEW-LABEL: _Z4bar3P1Ci
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_int:!.*]]
+  return c->x[j];
+}
+
 // CHECK-DAG: [[TAG_A_i]] = !{[[TYPE_A:!.*]], [[TYPE_int:!.*]], i64 0}
 // CHECK-DAG: [[TYPE_A]] = !{!"_ZTS1A", !{{.*}}, i64 0}
 // CHECK-DAG: [[TYPE_int]] = !{!"int", !{{.*}}, i64 0}
+
+// CHECK-NEW-DAG: [[TYPE_char:!.*]] = !{{{.*}}, i64 1, !"omnipotent char"}
+// CHECK-NEW-DAG: [[TYPE_int:!.*]] = !{[[TYPE_char]], i64 4, !"int"}
+// CHECK-NEW-DAG: [[TAG_int]] = !{[[TYPE_int]], [[TYPE_int]], i64 0, i64 4}
+// CHECK-NEW-DAG: [[TYPE_pointer:!.*]] = !{[[TYPE_char]], i64 8, !"any 
pointer"}
+// CHECK-NEW-DAG: [[TYPE_A:!.*]] = !{[[TYPE_char]], i64 4, !"_ZTS1A", 
[[TYPE_int]], i64 0, i64 4}
+// CHECK-NEW-DAG: [[TAG_A_i]] = !{[[TYPE_A]], [[TYPE_int]], i64 0, i64 4}
+// CHECK-NEW-DAG: [[TYPE_C:!.*]] = !{[[TYPE_char]], i64 16, !"_ZTS1C", 
[[TYPE_int]], i64 0, i64 4, [[TYPE_int]], i64 4, i64 12}
+// CHECK-NEW-DAG: [[TAG_C_i]] = !{[[TYPE_C:!.*]], [[TYPE_int:!.*]], i64 0, i64 
4}
Index: cfe/trunk/lib/CodeGen/CodeGenTBAA.cpp
===
--- cfe/trunk/lib/CodeGen/CodeGenTBAA.cpp
+++ cfe/trunk/lib/CodeGen/CodeGenTBAA.cpp
@@ -161,6 +161,10 @@
   if (Ty->isPointerType() || Ty->isReferenceType())
 return createScalarTypeNode("any pointer", getChar(), Size);
 
+  // Accesses to arrays are accesses to objects of their element types.
+  if (CodeGenOpts.NewStructPathTBAA && Ty->isArrayType())
+return getTypeInfo(cast(Ty)->getElementType());
+
   // Enum types are distinct types. In C++ they have "underlying types",
   // however they aren't related for TBAA.
   if (const EnumType *ETy = dyn_cast(Ty)) {


Index: cfe/trunk/test/CodeGen/tbaa-array.cpp
===
--- cfe/trunk/test/CodeGen/tbaa-array.cpp
+++ cfe/trunk/test/CodeGen/tbaa-array.cpp
@@ -1,18 +1,52 @@
 // RUN: %clang_cc1 -triple x86_64-linux -O1 -disable-llvm-passes %s \
 // RUN: -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-linux -O1 -disable-llvm-passes %s \
+// RUN: -new-struct-path-tbaa -emit-llvm -o - | \
+// RUN: FileCheck -check-prefix=CHECK-NEW %s
 //
 // Check that we generate correct TBAA information for accesses to array
 // elements.
 
 struct A { int i; };
 struct B { A a[1]; };
+struct C { int i; int x[3]; };
 
 int foo(B *b) {
 // CHECK-LABEL: _Z3fooP1B
 // CHECK: load i32, {{.*}}, !tbaa [[TAG_A_i:!.*]]
+// CHECK-NEW-LABEL: _Z3fooP1B
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_A_i:!.*]]
   return b->a->i;
 }
 
+// Check that members of array types are represented correctly.
+int bar(C *c) {
+// CHECK-NEW-LABEL: _Z3barP1C
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_C_i:!.*]]
+  return c->i;
+}
+
+int bar2(C *c) {
+// CHECK-NEW-LABEL: _Z4bar2P1C
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_int:!.*]]
+  return c->x[2];
+}
+
+int bar3(C *c, int j) {
+// CHECK-NEW-LABEL: _Z4bar3P1Ci
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_int:!.*]]
+  return c->x[j];
+}
+
 // CHECK-DAG: [[TAG_A_i]] = !{[[TYPE_A:!.*]], [[TYPE_int:!.*]], i64 0}
 // CHECK-DAG: [[TYPE_A]] = !{!"_ZTS1A", !{{.*}}, i64 0}
 // CHECK-DAG: [[TYPE_int]] = !{!"int", !{{.*}}, i64 0}
+
+// CHECK-NEW-DAG: [[TYPE_char:!.*]] = !{{{.*}}, i64 1, !"omnipotent char"}
+// CHECK-NEW-DAG: [[TYPE_int:!.*]] = 

[PATCH] D41394: [CodeGen] Support generation of TBAA info in the new format

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL321351: [CodeGen] Support generation of TBAA info in the new 
format (authored by kosarev, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D41394?vs=127838=127993#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D41394

Files:
  cfe/trunk/lib/CodeGen/CodeGenTBAA.cpp
  cfe/trunk/test/CodeGen/tbaa.cpp

Index: cfe/trunk/test/CodeGen/tbaa.cpp
===
--- cfe/trunk/test/CodeGen/tbaa.cpp
+++ cfe/trunk/test/CodeGen/tbaa.cpp
@@ -1,5 +1,6 @@
 // RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -no-struct-path-tbaa -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s
-// RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s -check-prefix=PATH
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s -check-prefixes=PATH,OLD-PATH
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -new-struct-path-tbaa -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s -check-prefixes=PATH,NEW-PATH
 // RUN: %clang_cc1 -triple x86_64-apple-darwin -O0 -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s -check-prefix=NO-TBAA
 // RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -relaxed-aliasing -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s -check-prefix=NO-TBAA
 // Test TBAA metadata generated by front-end.
@@ -248,29 +249,57 @@
 // CHECK: [[TYPE_i16]] = !{!"short", [[TYPE_char]],
 // CHECK: [[TAG_char]] = !{[[TYPE_char]], [[TYPE_char]], i64 0}
 
-// PATH: [[TYPE_CHAR:!.*]] = !{!"omnipotent char", !
-// PATH: [[TAG_i32]] = !{[[TYPE_INT:!.*]], [[TYPE_INT]], i64 0}
-// PATH: [[TYPE_INT]] = !{!"int", [[TYPE_CHAR]]
-// PATH: [[TAG_A_f32]] = !{[[TYPE_A:!.*]], [[TYPE_INT]], i64 4}
-// PATH: [[TYPE_A]] = !{!"_ZTS7StructA", [[TYPE_SHORT:!.*]], i64 0, [[TYPE_INT]], i64 4, [[TYPE_SHORT]], i64 8, [[TYPE_INT]], i64 12}
-// PATH: [[TYPE_SHORT:!.*]] = !{!"short", [[TYPE_CHAR]]
-// PATH: [[TAG_A_f16]] = !{[[TYPE_A]], [[TYPE_SHORT]], i64 0}
-// PATH: [[TAG_B_a_f32]] = !{[[TYPE_B:!.*]], [[TYPE_INT]], i64 8}
-// PATH: [[TYPE_B]] = !{!"_ZTS7StructB", [[TYPE_SHORT]], i64 0, [[TYPE_A]], i64 4, [[TYPE_INT]], i64 20}
-// PATH: [[TAG_B_a_f16]] = !{[[TYPE_B]], [[TYPE_SHORT]], i64 4}
-// PATH: [[TAG_B_f32]] = !{[[TYPE_B]], [[TYPE_INT]], i64 20}
-// PATH: [[TAG_B_a_f32_2]] = !{[[TYPE_B]], [[TYPE_INT]], i64 16}
-// PATH: [[TAG_S_f32]] = !{[[TYPE_S:!.*]], [[TYPE_INT]], i64 4}
-// PATH: [[TYPE_S]] = !{!"_ZTS7StructS", [[TYPE_SHORT]], i64 0, [[TYPE_INT]], i64 4}
-// PATH: [[TAG_S_f16]] = !{[[TYPE_S]], [[TYPE_SHORT]], i64 0}
-// PATH: [[TAG_S2_f32]] = !{[[TYPE_S2:!.*]], [[TYPE_INT]], i64 4}
-// PATH: [[TYPE_S2]] = !{!"_ZTS8StructS2", [[TYPE_SHORT]], i64 0, [[TYPE_INT]], i64 4}
-// PATH: [[TAG_S2_f16]] = !{[[TYPE_S2]], [[TYPE_SHORT]], i64 0}
-// PATH: [[TAG_C_b_a_f32]] = !{[[TYPE_C:!.*]], [[TYPE_INT]], i64 12}
-// PATH: [[TYPE_C]] = !{!"_ZTS7StructC", [[TYPE_SHORT]], i64 0, [[TYPE_B]], i64 4, [[TYPE_INT]], i64 28}
-// PATH: [[TAG_D_b_a_f32]] = !{[[TYPE_D:!.*]], [[TYPE_INT]], i64 12}
-// PATH: [[TYPE_D]] = !{!"_ZTS7StructD", [[TYPE_SHORT]], i64 0, [[TYPE_B]], i64 4, [[TYPE_INT]], i64 28, [[TYPE_CHAR]], i64 32}
-// PATH: [[TAG_five_b]] = !{[[TYPE_five:!.*]], [[TYPE_CHAR]], i64 1}
-// PATH: [[TYPE_five]] = !{!"_ZTS4five", [[TYPE_CHAR]], i64 0, [[TYPE_INT]], i64 1, [[TYPE_CHAR]], i64 1, [[TYPE_CHAR]], i64 2}
-// PATH: [[TAG_six_b]] = !{[[TYPE_six:!.*]], [[TYPE_CHAR]], i64 4}
-// PATH: [[TYPE_six]] = !{!"_ZTS3six", [[TYPE_CHAR]], i64 0, [[TYPE_INT]], i64 4, [[TYPE_CHAR]], i64 4, [[TYPE_CHAR]], i64 5}
+// OLD-PATH: [[TYPE_CHAR:!.*]] = !{!"omnipotent char", !
+// OLD-PATH: [[TAG_i32]] = !{[[TYPE_INT:!.*]], [[TYPE_INT]], i64 0}
+// OLD-PATH: [[TYPE_INT]] = !{!"int", [[TYPE_CHAR]]
+// OLD-PATH: [[TAG_A_f32]] = !{[[TYPE_A:!.*]], [[TYPE_INT]], i64 4}
+// OLD-PATH: [[TYPE_A]] = !{!"_ZTS7StructA", [[TYPE_SHORT:!.*]], i64 0, [[TYPE_INT]], i64 4, [[TYPE_SHORT]], i64 8, [[TYPE_INT]], i64 12}
+// OLD-PATH: [[TYPE_SHORT:!.*]] = !{!"short", [[TYPE_CHAR]]
+// OLD-PATH: [[TAG_A_f16]] = !{[[TYPE_A]], [[TYPE_SHORT]], i64 0}
+// OLD-PATH: [[TAG_B_a_f32]] = !{[[TYPE_B:!.*]], [[TYPE_INT]], i64 8}
+// OLD-PATH: [[TYPE_B]] = !{!"_ZTS7StructB", [[TYPE_SHORT]], i64 0, [[TYPE_A]], i64 4, [[TYPE_INT]], i64 20}
+// OLD-PATH: [[TAG_B_a_f16]] = !{[[TYPE_B]], [[TYPE_SHORT]], i64 4}
+// OLD-PATH: [[TAG_B_f32]] = !{[[TYPE_B]], [[TYPE_INT]], i64 20}
+// OLD-PATH: [[TAG_B_a_f32_2]] = !{[[TYPE_B]], [[TYPE_INT]], i64 16}
+// OLD-PATH: [[TAG_S_f32]] = !{[[TYPE_S:!.*]], [[TYPE_INT]], i64 4}
+// OLD-PATH: [[TYPE_S]] = !{!"_ZTS7StructS", [[TYPE_SHORT]], i64 0, [[TYPE_INT]], i64 4}
+// OLD-PATH: [[TAG_S_f16]] = !{[[TYPE_S]], [[TYPE_SHORT]], i64 0}
+// OLD-PATH: [[TAG_S2_f32]] = !{[[TYPE_S2:!.*]], [[TYPE_INT]], i64 4}
+// OLD-PATH: [[TYPE_S2]] = !{!"_ZTS8StructS2", [[TYPE_SHORT]], i64 0, [[TYPE_INT]], i64 4}
+// OLD-PATH: 

[PATCH] D41394: [CodeGen] Support generation of TBAA info in the new format

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 127838.
kosarev added a comment.

Updated as suggested.


https://reviews.llvm.org/D41394

Files:
  lib/CodeGen/CodeGenTBAA.cpp
  test/CodeGen/tbaa.cpp

Index: test/CodeGen/tbaa.cpp
===
--- test/CodeGen/tbaa.cpp
+++ test/CodeGen/tbaa.cpp
@@ -1,5 +1,6 @@
 // RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -no-struct-path-tbaa -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s
-// RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s -check-prefix=PATH
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s -check-prefixes=PATH,OLD-PATH
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -new-struct-path-tbaa -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s -check-prefixes=PATH,NEW-PATH
 // RUN: %clang_cc1 -triple x86_64-apple-darwin -O0 -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s -check-prefix=NO-TBAA
 // RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -relaxed-aliasing -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s -check-prefix=NO-TBAA
 // Test TBAA metadata generated by front-end.
@@ -248,29 +249,57 @@
 // CHECK: [[TYPE_i16]] = !{!"short", [[TYPE_char]],
 // CHECK: [[TAG_char]] = !{[[TYPE_char]], [[TYPE_char]], i64 0}
 
-// PATH: [[TYPE_CHAR:!.*]] = !{!"omnipotent char", !
-// PATH: [[TAG_i32]] = !{[[TYPE_INT:!.*]], [[TYPE_INT]], i64 0}
-// PATH: [[TYPE_INT]] = !{!"int", [[TYPE_CHAR]]
-// PATH: [[TAG_A_f32]] = !{[[TYPE_A:!.*]], [[TYPE_INT]], i64 4}
-// PATH: [[TYPE_A]] = !{!"_ZTS7StructA", [[TYPE_SHORT:!.*]], i64 0, [[TYPE_INT]], i64 4, [[TYPE_SHORT]], i64 8, [[TYPE_INT]], i64 12}
-// PATH: [[TYPE_SHORT:!.*]] = !{!"short", [[TYPE_CHAR]]
-// PATH: [[TAG_A_f16]] = !{[[TYPE_A]], [[TYPE_SHORT]], i64 0}
-// PATH: [[TAG_B_a_f32]] = !{[[TYPE_B:!.*]], [[TYPE_INT]], i64 8}
-// PATH: [[TYPE_B]] = !{!"_ZTS7StructB", [[TYPE_SHORT]], i64 0, [[TYPE_A]], i64 4, [[TYPE_INT]], i64 20}
-// PATH: [[TAG_B_a_f16]] = !{[[TYPE_B]], [[TYPE_SHORT]], i64 4}
-// PATH: [[TAG_B_f32]] = !{[[TYPE_B]], [[TYPE_INT]], i64 20}
-// PATH: [[TAG_B_a_f32_2]] = !{[[TYPE_B]], [[TYPE_INT]], i64 16}
-// PATH: [[TAG_S_f32]] = !{[[TYPE_S:!.*]], [[TYPE_INT]], i64 4}
-// PATH: [[TYPE_S]] = !{!"_ZTS7StructS", [[TYPE_SHORT]], i64 0, [[TYPE_INT]], i64 4}
-// PATH: [[TAG_S_f16]] = !{[[TYPE_S]], [[TYPE_SHORT]], i64 0}
-// PATH: [[TAG_S2_f32]] = !{[[TYPE_S2:!.*]], [[TYPE_INT]], i64 4}
-// PATH: [[TYPE_S2]] = !{!"_ZTS8StructS2", [[TYPE_SHORT]], i64 0, [[TYPE_INT]], i64 4}
-// PATH: [[TAG_S2_f16]] = !{[[TYPE_S2]], [[TYPE_SHORT]], i64 0}
-// PATH: [[TAG_C_b_a_f32]] = !{[[TYPE_C:!.*]], [[TYPE_INT]], i64 12}
-// PATH: [[TYPE_C]] = !{!"_ZTS7StructC", [[TYPE_SHORT]], i64 0, [[TYPE_B]], i64 4, [[TYPE_INT]], i64 28}
-// PATH: [[TAG_D_b_a_f32]] = !{[[TYPE_D:!.*]], [[TYPE_INT]], i64 12}
-// PATH: [[TYPE_D]] = !{!"_ZTS7StructD", [[TYPE_SHORT]], i64 0, [[TYPE_B]], i64 4, [[TYPE_INT]], i64 28, [[TYPE_CHAR]], i64 32}
-// PATH: [[TAG_five_b]] = !{[[TYPE_five:!.*]], [[TYPE_CHAR]], i64 1}
-// PATH: [[TYPE_five]] = !{!"_ZTS4five", [[TYPE_CHAR]], i64 0, [[TYPE_INT]], i64 1, [[TYPE_CHAR]], i64 1, [[TYPE_CHAR]], i64 2}
-// PATH: [[TAG_six_b]] = !{[[TYPE_six:!.*]], [[TYPE_CHAR]], i64 4}
-// PATH: [[TYPE_six]] = !{!"_ZTS3six", [[TYPE_CHAR]], i64 0, [[TYPE_INT]], i64 4, [[TYPE_CHAR]], i64 4, [[TYPE_CHAR]], i64 5}
+// OLD-PATH: [[TYPE_CHAR:!.*]] = !{!"omnipotent char", !
+// OLD-PATH: [[TAG_i32]] = !{[[TYPE_INT:!.*]], [[TYPE_INT]], i64 0}
+// OLD-PATH: [[TYPE_INT]] = !{!"int", [[TYPE_CHAR]]
+// OLD-PATH: [[TAG_A_f32]] = !{[[TYPE_A:!.*]], [[TYPE_INT]], i64 4}
+// OLD-PATH: [[TYPE_A]] = !{!"_ZTS7StructA", [[TYPE_SHORT:!.*]], i64 0, [[TYPE_INT]], i64 4, [[TYPE_SHORT]], i64 8, [[TYPE_INT]], i64 12}
+// OLD-PATH: [[TYPE_SHORT:!.*]] = !{!"short", [[TYPE_CHAR]]
+// OLD-PATH: [[TAG_A_f16]] = !{[[TYPE_A]], [[TYPE_SHORT]], i64 0}
+// OLD-PATH: [[TAG_B_a_f32]] = !{[[TYPE_B:!.*]], [[TYPE_INT]], i64 8}
+// OLD-PATH: [[TYPE_B]] = !{!"_ZTS7StructB", [[TYPE_SHORT]], i64 0, [[TYPE_A]], i64 4, [[TYPE_INT]], i64 20}
+// OLD-PATH: [[TAG_B_a_f16]] = !{[[TYPE_B]], [[TYPE_SHORT]], i64 4}
+// OLD-PATH: [[TAG_B_f32]] = !{[[TYPE_B]], [[TYPE_INT]], i64 20}
+// OLD-PATH: [[TAG_B_a_f32_2]] = !{[[TYPE_B]], [[TYPE_INT]], i64 16}
+// OLD-PATH: [[TAG_S_f32]] = !{[[TYPE_S:!.*]], [[TYPE_INT]], i64 4}
+// OLD-PATH: [[TYPE_S]] = !{!"_ZTS7StructS", [[TYPE_SHORT]], i64 0, [[TYPE_INT]], i64 4}
+// OLD-PATH: [[TAG_S_f16]] = !{[[TYPE_S]], [[TYPE_SHORT]], i64 0}
+// OLD-PATH: [[TAG_S2_f32]] = !{[[TYPE_S2:!.*]], [[TYPE_INT]], i64 4}
+// OLD-PATH: [[TYPE_S2]] = !{!"_ZTS8StructS2", [[TYPE_SHORT]], i64 0, [[TYPE_INT]], i64 4}
+// OLD-PATH: [[TAG_S2_f16]] = !{[[TYPE_S2]], [[TYPE_SHORT]], i64 0}
+// OLD-PATH: [[TAG_C_b_a_f32]] = !{[[TYPE_C:!.*]], [[TYPE_INT]], i64 12}
+// OLD-PATH: [[TYPE_C]] = !{!"_ZTS7StructC", [[TYPE_SHORT]], i64 0, [[TYPE_B]], i64 4, [[TYPE_INT]], i64 28}
+// OLD-PATH: 

[PATCH] D41452: [CodeGen] Fix access sizes in new-format TBAA tags

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL321250: [CodeGen] Fix access sizes in new-format TBAA tags 
(authored by kosarev, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D41452?vs=127724=127834#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D41452

Files:
  cfe/trunk/lib/CodeGen/CGExpr.cpp


Index: cfe/trunk/lib/CodeGen/CGExpr.cpp
===
--- cfe/trunk/lib/CodeGen/CGExpr.cpp
+++ cfe/trunk/lib/CodeGen/CGExpr.cpp
@@ -3801,8 +3801,10 @@
   FieldTBAAInfo.Offset +=
   Layout.getFieldOffset(field->getFieldIndex()) / CharWidth;
 
-// Update the final access type.
+// Update the final access type and size.
 FieldTBAAInfo.AccessType = CGM.getTBAATypeInfo(FieldType);
+FieldTBAAInfo.Size =
+getContext().getTypeSizeInChars(FieldType).getQuantity();
   }
 
   Address addr = base.getAddress();


Index: cfe/trunk/lib/CodeGen/CGExpr.cpp
===
--- cfe/trunk/lib/CodeGen/CGExpr.cpp
+++ cfe/trunk/lib/CodeGen/CGExpr.cpp
@@ -3801,8 +3801,10 @@
   FieldTBAAInfo.Offset +=
   Layout.getFieldOffset(field->getFieldIndex()) / CharWidth;
 
-// Update the final access type.
+// Update the final access type and size.
 FieldTBAAInfo.AccessType = CGM.getTBAATypeInfo(FieldType);
+FieldTBAAInfo.Size =
+getContext().getTypeSizeInChars(FieldType).getQuantity();
   }
 
   Address addr = base.getAddress();
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D41399: [CodeGen] Represent array members in new-format TBAA type descriptors

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 127742.
kosarev added a comment.

- Fixed the access size.
- Added the suggested tests.


https://reviews.llvm.org/D41399

Files:
  lib/CodeGen/CodeGenTBAA.cpp
  test/CodeGen/tbaa-array.cpp


Index: test/CodeGen/tbaa-array.cpp
===
--- test/CodeGen/tbaa-array.cpp
+++ test/CodeGen/tbaa-array.cpp
@@ -1,18 +1,52 @@
 // RUN: %clang_cc1 -triple x86_64-linux -O1 -disable-llvm-passes %s \
 // RUN: -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-linux -O1 -disable-llvm-passes %s \
+// RUN: -new-struct-path-tbaa -emit-llvm -o - | \
+// RUN: FileCheck -check-prefix=CHECK-NEW %s
 //
 // Check that we generate correct TBAA information for accesses to array
 // elements.
 
 struct A { int i; };
 struct B { A a[1]; };
+struct C { int i; int x[3]; };
 
 int foo(B *b) {
 // CHECK-LABEL: _Z3fooP1B
 // CHECK: load i32, {{.*}}, !tbaa [[TAG_A_i:!.*]]
+// CHECK-NEW-LABEL: _Z3fooP1B
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_A_i:!.*]]
   return b->a->i;
 }
 
+// Check that members of array types are represented correctly.
+int bar(C *c) {
+// CHECK-NEW-LABEL: _Z3barP1C
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_C_i:!.*]]
+  return c->i;
+}
+
+int bar2(C *c) {
+// CHECK-NEW-LABEL: _Z4bar2P1C
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_int:!.*]]
+  return c->x[2];
+}
+
+int bar3(C *c, int j) {
+// CHECK-NEW-LABEL: _Z4bar3P1Ci
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_int:!.*]]
+  return c->x[j];
+}
+
 // CHECK-DAG: [[TAG_A_i]] = !{[[TYPE_A:!.*]], [[TYPE_int:!.*]], i64 0}
 // CHECK-DAG: [[TYPE_A]] = !{!"_ZTS1A", !{{.*}}, i64 0}
 // CHECK-DAG: [[TYPE_int]] = !{!"int", !{{.*}}, i64 0}
+
+// CHECK-NEW-DAG: [[TYPE_char:!.*]] = !{{{.*}}, i64 1, !"omnipotent char"}
+// CHECK-NEW-DAG: [[TYPE_int:!.*]] = !{[[TYPE_char]], i64 4, !"int"}
+// CHECK-NEW-DAG: [[TAG_int]] = !{[[TYPE_int]], [[TYPE_int]], i64 0, i64 4}
+// CHECK-NEW-DAG: [[TYPE_pointer:!.*]] = !{[[TYPE_char]], i64 8, !"any 
pointer"}
+// CHECK-NEW-DAG: [[TYPE_A:!.*]] = !{[[TYPE_char]], i64 4, !"_ZTS1A", 
[[TYPE_int]], i64 0, i64 4}
+// CHECK-NEW-DAG: [[TAG_A_i]] = !{[[TYPE_A]], [[TYPE_int]], i64 0, i64 4}
+// CHECK-NEW-DAG: [[TYPE_C:!.*]] = !{[[TYPE_char]], i64 16, !"_ZTS1C", 
[[TYPE_int]], i64 0, i64 4, [[TYPE_int]], i64 4, i64 12}
+// CHECK-NEW-DAG: [[TAG_C_i]] = !{[[TYPE_C:!.*]], [[TYPE_int:!.*]], i64 0, i64 
4}
Index: lib/CodeGen/CodeGenTBAA.cpp
===
--- lib/CodeGen/CodeGenTBAA.cpp
+++ lib/CodeGen/CodeGenTBAA.cpp
@@ -161,6 +161,10 @@
   if (Ty->isPointerType() || Ty->isReferenceType())
 return createScalarTypeNode("any pointer", getChar(), Size);
 
+  // Accesses to arrays are accesses to objects of their element types.
+  if (CodeGenOpts.NewStructPathTBAA && Ty->isArrayType())
+return getTypeInfo(cast(Ty)->getElementType());
+
   // Enum types are distinct types. In C++ they have "underlying types",
   // however they aren't related for TBAA.
   if (const EnumType *ETy = dyn_cast(Ty)) {


Index: test/CodeGen/tbaa-array.cpp
===
--- test/CodeGen/tbaa-array.cpp
+++ test/CodeGen/tbaa-array.cpp
@@ -1,18 +1,52 @@
 // RUN: %clang_cc1 -triple x86_64-linux -O1 -disable-llvm-passes %s \
 // RUN: -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -triple x86_64-linux -O1 -disable-llvm-passes %s \
+// RUN: -new-struct-path-tbaa -emit-llvm -o - | \
+// RUN: FileCheck -check-prefix=CHECK-NEW %s
 //
 // Check that we generate correct TBAA information for accesses to array
 // elements.
 
 struct A { int i; };
 struct B { A a[1]; };
+struct C { int i; int x[3]; };
 
 int foo(B *b) {
 // CHECK-LABEL: _Z3fooP1B
 // CHECK: load i32, {{.*}}, !tbaa [[TAG_A_i:!.*]]
+// CHECK-NEW-LABEL: _Z3fooP1B
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_A_i:!.*]]
   return b->a->i;
 }
 
+// Check that members of array types are represented correctly.
+int bar(C *c) {
+// CHECK-NEW-LABEL: _Z3barP1C
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_C_i:!.*]]
+  return c->i;
+}
+
+int bar2(C *c) {
+// CHECK-NEW-LABEL: _Z4bar2P1C
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_int:!.*]]
+  return c->x[2];
+}
+
+int bar3(C *c, int j) {
+// CHECK-NEW-LABEL: _Z4bar3P1Ci
+// CHECK-NEW: load i32, {{.*}}, !tbaa [[TAG_int:!.*]]
+  return c->x[j];
+}
+
 // CHECK-DAG: [[TAG_A_i]] = !{[[TYPE_A:!.*]], [[TYPE_int:!.*]], i64 0}
 // CHECK-DAG: [[TYPE_A]] = !{!"_ZTS1A", !{{.*}}, i64 0}
 // CHECK-DAG: [[TYPE_int]] = !{!"int", !{{.*}}, i64 0}
+
+// CHECK-NEW-DAG: [[TYPE_char:!.*]] = !{{{.*}}, i64 1, !"omnipotent char"}
+// CHECK-NEW-DAG: [[TYPE_int:!.*]] = !{[[TYPE_char]], i64 4, !"int"}
+// CHECK-NEW-DAG: [[TAG_int]] = !{[[TYPE_int]], [[TYPE_int]], i64 0, i64 4}
+// CHECK-NEW-DAG: [[TYPE_pointer:!.*]] = !{[[TYPE_char]], i64 8, !"any pointer"}
+// CHECK-NEW-DAG: [[TYPE_A:!.*]] = !{[[TYPE_char]], i64 4, !"_ZTS1A", [[TYPE_int]], i64 0, i64 4}
+// 

[PATCH] D41399: [CodeGen] Represent array members in new-format TBAA type descriptors

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added inline comments.



Comment at: test/CodeGen/tbaa-array.cpp:24
+// CHECK-DAG: [[TAG_A_i]] = !{[[TYPE_A:!.*]], [[TYPE_int:!.*]], i64 0, i64 4}
+// CHECK-DAG: [[TAG_C_i]] = !{[[TYPE_C:!.*]], [[TYPE_int:!.*]], i64 0, i64 16}
+// CHECK-DAG: [[TYPE_A]] = !{[[TYPE_char:!.*]], i64 4, !"_ZTS1A", 
[[TYPE_int]], i64 0, i64 4}

kosarev wrote:
> hfinkel wrote:
> > Shouldn't this access have a size of 4, and an access for c->x[2] have a 
> > size of 4 and a specific offset and c->x[j] have a size of 12 and an offset 
> > of zero? Why does this list a size of 16?
> > 
> > In any case, please add tests for:
> > 
> >   int *bar2(C *c) {
> > return c->x;
> >   }
> > 
> >   int bar3(C *c) {
> > return c->x[2];
> >   }
> > 
> >   int bar4(C *c, int j) {
> > return c->x[j];
> >   }
> > 
> Indeed, the access size is wrong as we mistakenly inherit it from the base 
> type. D41452 fixes this. Thanks for catching.
Hal, in bar2() we don't really access memory. What do we want to check with it?


Repository:
  rL LLVM

https://reviews.llvm.org/D41399



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D41399: [CodeGen] Represent array members in new-format TBAA type descriptors

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added inline comments.



Comment at: test/CodeGen/tbaa-array.cpp:24
+// CHECK-DAG: [[TAG_A_i]] = !{[[TYPE_A:!.*]], [[TYPE_int:!.*]], i64 0, i64 4}
+// CHECK-DAG: [[TAG_C_i]] = !{[[TYPE_C:!.*]], [[TYPE_int:!.*]], i64 0, i64 16}
+// CHECK-DAG: [[TYPE_A]] = !{[[TYPE_char:!.*]], i64 4, !"_ZTS1A", 
[[TYPE_int]], i64 0, i64 4}

hfinkel wrote:
> Shouldn't this access have a size of 4, and an access for c->x[2] have a size 
> of 4 and a specific offset and c->x[j] have a size of 12 and an offset of 
> zero? Why does this list a size of 16?
> 
> In any case, please add tests for:
> 
>   int *bar2(C *c) {
> return c->x;
>   }
> 
>   int bar3(C *c) {
> return c->x[2];
>   }
> 
>   int bar4(C *c, int j) {
> return c->x[j];
>   }
> 
Indeed, the access size is wrong as we mistakenly inherit it from the base 
type. D41452 fixes this. Thanks for catching.


Repository:
  rL LLVM

https://reviews.llvm.org/D41399



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D41452: [CodeGen] Fix access sizes in new-format TBAA tags

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added reviewers: rjmccall, hfinkel.
kosarev added a project: clang.

The new format requires to specify both the type of the access and its size. 
This patch fixes setting access sizes for TBAA tags that denote accesses to 
structure members. This fix affects all future TBAA metadata tests for the new 
format, so I guess we don't need any special tests for this fix.


Repository:
  rL LLVM

https://reviews.llvm.org/D41452

Files:
  lib/CodeGen/CGExpr.cpp


Index: lib/CodeGen/CGExpr.cpp
===
--- lib/CodeGen/CGExpr.cpp
+++ lib/CodeGen/CGExpr.cpp
@@ -3790,8 +3790,10 @@
   FieldTBAAInfo.Offset +=
   Layout.getFieldOffset(field->getFieldIndex()) / CharWidth;
 
-// Update the final access type.
+// Update the final access type and size.
 FieldTBAAInfo.AccessType = CGM.getTBAATypeInfo(FieldType);
+FieldTBAAInfo.Size =
+getContext().getTypeSizeInChars(FieldType).getQuantity();
   }
 
   Address addr = base.getAddress();


Index: lib/CodeGen/CGExpr.cpp
===
--- lib/CodeGen/CGExpr.cpp
+++ lib/CodeGen/CGExpr.cpp
@@ -3790,8 +3790,10 @@
   FieldTBAAInfo.Offset +=
   Layout.getFieldOffset(field->getFieldIndex()) / CharWidth;
 
-// Update the final access type.
+// Update the final access type and size.
 FieldTBAAInfo.AccessType = CGM.getTBAATypeInfo(FieldType);
+FieldTBAAInfo.Size =
+getContext().getTypeSizeInChars(FieldType).getQuantity();
   }
 
   Address addr = base.getAddress();
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D41394: [CodeGen] Support generation of TBAA info in the new format

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 127722.
kosarev added a comment.

Added tests.


https://reviews.llvm.org/D41394

Files:
  lib/CodeGen/CodeGenTBAA.cpp
  test/CodeGen/tbaa.cpp

Index: test/CodeGen/tbaa.cpp
===
--- test/CodeGen/tbaa.cpp
+++ test/CodeGen/tbaa.cpp
@@ -1,5 +1,6 @@
 // RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -no-struct-path-tbaa -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s
 // RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s -check-prefix=PATH
+// RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -new-struct-path-tbaa -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s -check-prefix=NEW-PATH
 // RUN: %clang_cc1 -triple x86_64-apple-darwin -O0 -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s -check-prefix=NO-TBAA
 // RUN: %clang_cc1 -triple x86_64-apple-darwin -O1 -relaxed-aliasing -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s -check-prefix=NO-TBAA
 // Test TBAA metadata generated by front-end.
@@ -55,6 +56,9 @@
 // PATH-LABEL: define i32 @_Z1g
 // PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_i32:!.*]]
 // PATH: store i32 4, i32* %{{.*}}, align 4, !tbaa [[TAG_A_f32:!.*]]
+// NEW-PATH-LABEL: define i32 @_Z1g
+// NEW-PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_i32:!.*]]
+// NEW-PATH: store i32 4, i32* %{{.*}}, align 4, !tbaa [[TAG_A_f32:!.*]]
   *s = 1;
   A->f32 = 4;
   return *s;
@@ -67,6 +71,9 @@
 // PATH-LABEL: define i32 @_Z2g2
 // PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_i32]]
 // PATH: store i16 4, i16* %{{.*}}, align 4, !tbaa [[TAG_A_f16:!.*]]
+// NEW-PATH-LABEL: define i32 @_Z2g2
+// NEW-PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_i32]]
+// NEW-PATH: store i16 4, i16* %{{.*}}, align 4, !tbaa [[TAG_A_f16:!.*]]
   *s = 1;
   A->f16 = 4;
   return *s;
@@ -79,6 +86,9 @@
 // PATH-LABEL: define i32 @_Z2g3
 // PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_A_f32]]
 // PATH: store i32 4, i32* %{{.*}}, align 4, !tbaa [[TAG_B_a_f32:!.*]]
+// NEW-PATH-LABEL: define i32 @_Z2g3
+// NEW-PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_A_f32]]
+// NEW-PATH: store i32 4, i32* %{{.*}}, align 4, !tbaa [[TAG_B_a_f32:!.*]]
   A->f32 = 1;
   B->a.f32 = 4;
   return A->f32;
@@ -91,6 +101,9 @@
 // PATH-LABEL: define i32 @_Z2g4
 // PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_A_f32]]
 // PATH: store i16 4, i16* %{{.*}}, align 4, !tbaa [[TAG_B_a_f16:!.*]]
+// NEW-PATH-LABEL: define i32 @_Z2g4
+// NEW-PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_A_f32]]
+// NEW-PATH: store i16 4, i16* %{{.*}}, align 4, !tbaa [[TAG_B_a_f16:!.*]]
   A->f32 = 1;
   B->a.f16 = 4;
   return A->f32;
@@ -103,6 +116,9 @@
 // PATH-LABEL: define i32 @_Z2g5
 // PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_A_f32]]
 // PATH: store i32 4, i32* %{{.*}}, align 4, !tbaa [[TAG_B_f32:!.*]]
+// NEW-PATH-LABEL: define i32 @_Z2g5
+// NEW-PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_A_f32]]
+// NEW-PATH: store i32 4, i32* %{{.*}}, align 4, !tbaa [[TAG_B_f32:!.*]]
   A->f32 = 1;
   B->f32 = 4;
   return A->f32;
@@ -115,6 +131,9 @@
 // PATH-LABEL: define i32 @_Z2g6
 // PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_A_f32]]
 // PATH: store i32 4, i32* %{{.*}}, align 4, !tbaa [[TAG_B_a_f32_2:!.*]]
+// NEW-PATH-LABEL: define i32 @_Z2g6
+// NEW-PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_A_f32]]
+// NEW-PATH: store i32 4, i32* %{{.*}}, align 4, !tbaa [[TAG_B_a_f32_2:!.*]]
   A->f32 = 1;
   B->a.f32_2 = 4;
   return A->f32;
@@ -127,6 +146,9 @@
 // PATH-LABEL: define i32 @_Z2g7
 // PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_A_f32]]
 // PATH: store i32 4, i32* %{{.*}}, align 4, !tbaa [[TAG_S_f32:!.*]]
+// NEW-PATH-LABEL: define i32 @_Z2g7
+// NEW-PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_A_f32]]
+// NEW-PATH: store i32 4, i32* %{{.*}}, align 4, !tbaa [[TAG_S_f32:!.*]]
   A->f32 = 1;
   S->f32 = 4;
   return A->f32;
@@ -139,6 +161,9 @@
 // PATH-LABEL: define i32 @_Z2g8
 // PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_A_f32]]
 // PATH: store i16 4, i16* %{{.*}}, align 4, !tbaa [[TAG_S_f16:!.*]]
+// NEW-PATH-LABEL: define i32 @_Z2g8
+// NEW-PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_A_f32]]
+// NEW-PATH: store i16 4, i16* %{{.*}}, align 4, !tbaa [[TAG_S_f16:!.*]]
   A->f32 = 1;
   S->f16 = 4;
   return A->f32;
@@ -151,6 +176,9 @@
 // PATH-LABEL: define i32 @_Z2g9
 // PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_S_f32]]
 // PATH: store i32 4, i32* %{{.*}}, align 4, !tbaa [[TAG_S2_f32:!.*]]
+// NEW-PATH-LABEL: define i32 @_Z2g9
+// NEW-PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_S_f32]]
+// NEW-PATH: store i32 4, i32* %{{.*}}, align 4, !tbaa [[TAG_S2_f32:!.*]]
   S->f32 = 1;
   S2->f32 = 4;
   return S->f32;
@@ -163,6 +191,9 @@
 // PATH-LABEL: define i32 @_Z3g10
 // PATH: store i32 1, i32* %{{.*}}, align 4, !tbaa [[TAG_S_f32]]
 // PATH: store i16 

[PATCH] D41394: [CodeGen] Support generation of TBAA info in the new format

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

There are more tests that we will need to rewrite during migration to the new 
format than I think we could handle with a single patch. I was going to address 
them with separate patches. Or, I can rewrite some most basic of them as part 
of this patch.


Repository:
  rL LLVM

https://reviews.llvm.org/D41394



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D41399: [CodeGen] Represent array members in new-format TBAA type descriptors

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added reviewers: rjmccall, hfinkel.
kosarev added a project: clang.

Now that in the new TBAA format we allow access types to be of any object 
types, including aggregate ones, it becomes critical to specify types of all 
sub-objects such aggregates comprise as their members. In order to meet this 
requirement, this patch enables generation of field descriptors for members of 
array types.

This patch requires https://reviews.llvm.org/D41394 to be landed first.


Repository:
  rL LLVM

https://reviews.llvm.org/D41399

Files:
  lib/CodeGen/CodeGenTBAA.cpp
  test/CodeGen/tbaa-array.cpp


Index: test/CodeGen/tbaa-array.cpp
===
--- test/CodeGen/tbaa-array.cpp
+++ test/CodeGen/tbaa-array.cpp
@@ -1,18 +1,28 @@
 // RUN: %clang_cc1 -triple x86_64-linux -O1 -disable-llvm-passes %s \
-// RUN: -emit-llvm -o - | FileCheck %s
-//
-// Check that we generate correct TBAA information for accesses to array
-// elements.
+// RUN: -new-struct-path-tbaa -emit-llvm -o - | FileCheck %s
 
 struct A { int i; };
 struct B { A a[1]; };
+struct C { int i; int x[3]; };
 
+// Check that we generate correct TBAA information for accesses to array
+// elements.
 int foo(B *b) {
 // CHECK-LABEL: _Z3fooP1B
 // CHECK: load i32, {{.*}}, !tbaa [[TAG_A_i:!.*]]
   return b->a->i;
 }
 
-// CHECK-DAG: [[TAG_A_i]] = !{[[TYPE_A:!.*]], [[TYPE_int:!.*]], i64 0}
-// CHECK-DAG: [[TYPE_A]] = !{!"_ZTS1A", !{{.*}}, i64 0}
-// CHECK-DAG: [[TYPE_int]] = !{!"int", !{{.*}}, i64 0}
+// Check that members of array types are represented correctly.
+int bar(C *c) {
+// CHECK-LABEL: _Z3barP1C
+// CHECK: load i32, {{.*}}, !tbaa [[TAG_C_i:!.*]]
+  return c->i;
+}
+
+// CHECK-DAG: [[TAG_A_i]] = !{[[TYPE_A:!.*]], [[TYPE_int:!.*]], i64 0, i64 4}
+// CHECK-DAG: [[TAG_C_i]] = !{[[TYPE_C:!.*]], [[TYPE_int:!.*]], i64 0, i64 16}
+// CHECK-DAG: [[TYPE_A]] = !{[[TYPE_char:!.*]], i64 4, !"_ZTS1A", 
[[TYPE_int]], i64 0, i64 4}
+// CHECK-DAG: [[TYPE_C]] = !{[[TYPE_char]], i64 16, !"_ZTS1C", [[TYPE_int]], 
i64 0, i64 4, [[TYPE_int]], i64 4, i64 12}
+// CHECK-DAG: [[TYPE_int]] = !{[[TYPE_char]], i64 4, !"int"}
+// CHECK-DAG: [[TYPE_char]] = !{{{!.*}}, i64 1, !"omnipotent char"}
Index: lib/CodeGen/CodeGenTBAA.cpp
===
--- lib/CodeGen/CodeGenTBAA.cpp
+++ lib/CodeGen/CodeGenTBAA.cpp
@@ -161,6 +161,10 @@
   if (Ty->isPointerType() || Ty->isReferenceType())
 return createScalarTypeNode("any pointer", getChar(), Size);
 
+  // Accesses to arrays are accesses to objects of their element types.
+  if (CodeGenOpts.NewStructPathTBAA && Ty->isArrayType())
+return getTypeInfo(cast(Ty)->getElementType());
+
   // Enum types are distinct types. In C++ they have "underlying types",
   // however they aren't related for TBAA.
   if (const EnumType *ETy = dyn_cast(Ty)) {


Index: test/CodeGen/tbaa-array.cpp
===
--- test/CodeGen/tbaa-array.cpp
+++ test/CodeGen/tbaa-array.cpp
@@ -1,18 +1,28 @@
 // RUN: %clang_cc1 -triple x86_64-linux -O1 -disable-llvm-passes %s \
-// RUN: -emit-llvm -o - | FileCheck %s
-//
-// Check that we generate correct TBAA information for accesses to array
-// elements.
+// RUN: -new-struct-path-tbaa -emit-llvm -o - | FileCheck %s
 
 struct A { int i; };
 struct B { A a[1]; };
+struct C { int i; int x[3]; };
 
+// Check that we generate correct TBAA information for accesses to array
+// elements.
 int foo(B *b) {
 // CHECK-LABEL: _Z3fooP1B
 // CHECK: load i32, {{.*}}, !tbaa [[TAG_A_i:!.*]]
   return b->a->i;
 }
 
-// CHECK-DAG: [[TAG_A_i]] = !{[[TYPE_A:!.*]], [[TYPE_int:!.*]], i64 0}
-// CHECK-DAG: [[TYPE_A]] = !{!"_ZTS1A", !{{.*}}, i64 0}
-// CHECK-DAG: [[TYPE_int]] = !{!"int", !{{.*}}, i64 0}
+// Check that members of array types are represented correctly.
+int bar(C *c) {
+// CHECK-LABEL: _Z3barP1C
+// CHECK: load i32, {{.*}}, !tbaa [[TAG_C_i:!.*]]
+  return c->i;
+}
+
+// CHECK-DAG: [[TAG_A_i]] = !{[[TYPE_A:!.*]], [[TYPE_int:!.*]], i64 0, i64 4}
+// CHECK-DAG: [[TAG_C_i]] = !{[[TYPE_C:!.*]], [[TYPE_int:!.*]], i64 0, i64 16}
+// CHECK-DAG: [[TYPE_A]] = !{[[TYPE_char:!.*]], i64 4, !"_ZTS1A", [[TYPE_int]], i64 0, i64 4}
+// CHECK-DAG: [[TYPE_C]] = !{[[TYPE_char]], i64 16, !"_ZTS1C", [[TYPE_int]], i64 0, i64 4, [[TYPE_int]], i64 4, i64 12}
+// CHECK-DAG: [[TYPE_int]] = !{[[TYPE_char]], i64 4, !"int"}
+// CHECK-DAG: [[TYPE_char]] = !{{{!.*}}, i64 1, !"omnipotent char"}
Index: lib/CodeGen/CodeGenTBAA.cpp
===
--- lib/CodeGen/CodeGenTBAA.cpp
+++ lib/CodeGen/CodeGenTBAA.cpp
@@ -161,6 +161,10 @@
   if (Ty->isPointerType() || Ty->isReferenceType())
 return createScalarTypeNode("any pointer", getChar(), Size);
 
+  // Accesses to arrays are accesses to objects of their element types.
+  if (CodeGenOpts.NewStructPathTBAA && Ty->isArrayType())
+return 

[PATCH] D41394: [CodeGen] Support generation of TBAA info in the new format

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev created this revision.
kosarev added reviewers: rjmccall, hfinkel.
kosarev added a project: clang.

Now that the MDBuilder helpers generating TBAA type and access descriptors in 
the new format are in place, we can teach clang to use them when requested.


Repository:
  rL LLVM

https://reviews.llvm.org/D41394

Files:
  lib/CodeGen/CodeGenTBAA.cpp


Index: lib/CodeGen/CodeGenTBAA.cpp
===
--- lib/CodeGen/CodeGenTBAA.cpp
+++ lib/CodeGen/CodeGenTBAA.cpp
@@ -59,7 +59,10 @@
 llvm::MDNode *CodeGenTBAA::createScalarTypeNode(StringRef Name,
 llvm::MDNode *Parent,
 uint64_t Size) {
-  (void)Size; // TODO: Support generation of size-aware type nodes.
+  if (CodeGenOpts.NewStructPathTBAA) {
+llvm::Metadata *Id = MDHelper.createString(Name);
+return MDHelper.createTBAATypeNode(Parent, Size, Id);
+  }
   return MDHelper.createTBAAScalarTypeNode(Name, Parent);
 }
 
@@ -300,8 +303,12 @@
   OutName = RD->getName();
 }
 
-// TODO: Support size-aware type nodes and create one here for the
-// given aggregate type.
+if (CodeGenOpts.NewStructPathTBAA) {
+  llvm::MDNode *Parent = getChar();
+  uint64_t Size = Context.getTypeSizeInChars(Ty).getQuantity();
+  llvm::Metadata *Id = MDHelper.createString(OutName);
+  return MDHelper.createTBAATypeNode(Parent, Size, Id, Fields);
+}
 
 // Create the struct type node with a vector of pairs (offset, type).
 SmallVector, 4> OffsetsAndTypes;
@@ -348,6 +355,10 @@
 Info.BaseType = Info.AccessType;
 assert(!Info.Offset && "Nonzero offset for an access with no base type!");
   }
+  if (CodeGenOpts.NewStructPathTBAA) {
+return N = MDHelper.createTBAAAccessTag(Info.BaseType, Info.AccessType,
+Info.Offset, Info.Size);
+  }
   return N = MDHelper.createTBAAStructTagNode(Info.BaseType, Info.AccessType,
   Info.Offset);
 }


Index: lib/CodeGen/CodeGenTBAA.cpp
===
--- lib/CodeGen/CodeGenTBAA.cpp
+++ lib/CodeGen/CodeGenTBAA.cpp
@@ -59,7 +59,10 @@
 llvm::MDNode *CodeGenTBAA::createScalarTypeNode(StringRef Name,
 llvm::MDNode *Parent,
 uint64_t Size) {
-  (void)Size; // TODO: Support generation of size-aware type nodes.
+  if (CodeGenOpts.NewStructPathTBAA) {
+llvm::Metadata *Id = MDHelper.createString(Name);
+return MDHelper.createTBAATypeNode(Parent, Size, Id);
+  }
   return MDHelper.createTBAAScalarTypeNode(Name, Parent);
 }
 
@@ -300,8 +303,12 @@
   OutName = RD->getName();
 }
 
-// TODO: Support size-aware type nodes and create one here for the
-// given aggregate type.
+if (CodeGenOpts.NewStructPathTBAA) {
+  llvm::MDNode *Parent = getChar();
+  uint64_t Size = Context.getTypeSizeInChars(Ty).getQuantity();
+  llvm::Metadata *Id = MDHelper.createString(OutName);
+  return MDHelper.createTBAATypeNode(Parent, Size, Id, Fields);
+}
 
 // Create the struct type node with a vector of pairs (offset, type).
 SmallVector, 4> OffsetsAndTypes;
@@ -348,6 +355,10 @@
 Info.BaseType = Info.AccessType;
 assert(!Info.Offset && "Nonzero offset for an access with no base type!");
   }
+  if (CodeGenOpts.NewStructPathTBAA) {
+return N = MDHelper.createTBAAAccessTag(Info.BaseType, Info.AccessType,
+Info.Offset, Info.Size);
+  }
   return N = MDHelper.createTBAAStructTagNode(Info.BaseType, Info.AccessType,
   Info.Offset);
 }
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D39455: [CodeGen] Add initial support for union members in TBAA

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev added a comment.

Responded here: https://bugs.llvm.org/show_bug.cgi?id=26603


Repository:
  rL LLVM

https://reviews.llvm.org/D39455



___
cfe-commits mailing list
cfe-commits@lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D39455: [CodeGen] Add initial support for union members in TBAA

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL319413: [CodeGen] Add initial support for union members in 
TBAA (authored by kosarev).

Changed prior to commit:
  https://reviews.llvm.org/D39455?vs=124726=124883#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D39455

Files:
  cfe/trunk/lib/CodeGen/CGExpr.cpp
  cfe/trunk/lib/CodeGen/CodeGenModule.h
  cfe/trunk/lib/CodeGen/CodeGenTBAA.cpp
  cfe/trunk/lib/CodeGen/CodeGenTBAA.h
  cfe/trunk/test/CodeGen/tbaa-union.cpp
  cfe/trunk/test/CodeGen/union-tbaa1.c

Index: cfe/trunk/test/CodeGen/tbaa-union.cpp
===
--- cfe/trunk/test/CodeGen/tbaa-union.cpp
+++ cfe/trunk/test/CodeGen/tbaa-union.cpp
@@ -0,0 +1,100 @@
+// RUN: %clang_cc1 -triple x86_64-linux -O1 -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s
+//
+// Check that we generate correct TBAA information for accesses to union
+// members.
+
+struct X {
+  int a, b;
+  int arr[3];
+  int c, d;
+};
+
+union U {
+  int i;
+  X x;
+  int j;
+};
+
+struct S {
+  U u, v;
+};
+
+union N {
+  int i;
+  S s;
+  int j;
+};
+
+struct R {
+  N n, m;
+};
+
+int f1(U *p) {
+// CHECK-LABEL: _Z2f1P1U
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_U_j:!.*]]
+  return p->j;
+}
+
+int f2(S *p) {
+// CHECK-LABEL: _Z2f2P1S
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_S_u_i:!.*]]
+  return p->u.i;
+}
+
+int f3(S *p) {
+// CHECK-LABEL: _Z2f3P1S
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_S_v_j:!.*]]
+  return p->v.j;
+}
+
+int f4(S *p) {
+// CHECK-LABEL: _Z2f4P1S
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_S_u_x_b:!.*]]
+  return p->u.x.b;
+}
+
+int f5(S *p) {
+// CHECK-LABEL: _Z2f5P1S
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_S_v_x_b:!.*]]
+  return p->v.x.b;
+}
+
+int f6(S *p) {
+// CHECK-LABEL: _Z2f6P1S
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_S_u_x_arr:!.*]]
+  return p->u.x.arr[1];
+}
+
+int f7(S *p) {
+// CHECK-LABEL: _Z2f7P1S
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_S_v_x_arr:!.*]]
+  return p->v.x.arr[1];
+}
+
+int f8(N *p) {
+// CHECK-LABEL: _Z2f8P1N
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_N_s_v_x_c:!.*]]
+  return p->s.v.x.c;
+}
+
+int f9(R *p) {
+// CHECK-LABEL: _Z2f9P1R
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_R_m_s_v_x_c:!.*]]
+  return p->m.s.v.x.c;
+}
+
+// CHECK-DAG: [[TAG_U_j]] = !{[[TYPE_U:!.*]], [[TYPE_union_member:!.*]], i64 0}
+// CHECK-DAG: [[TAG_S_u_i]] = !{[[TYPE_S:!.*]], [[TYPE_union_member]], i64 0}
+// CHECK-DAG: [[TAG_S_u_x_b]] = !{[[TYPE_S:!.*]], [[TYPE_union_member]], i64 0}
+// CHECK-DAG: [[TAG_S_u_x_arr]] = !{[[TYPE_S:!.*]], [[TYPE_union_member]], i64 0}
+// CHECK-DAG: [[TAG_S_v_j]] = !{[[TYPE_S:!.*]], [[TYPE_union_member]], i64 28}
+// CHECK-DAG: [[TAG_S_v_x_b]] = !{[[TYPE_S:!.*]], [[TYPE_union_member]], i64 28}
+// CHECK-DAG: [[TAG_S_v_x_arr]] = !{[[TYPE_S:!.*]], [[TYPE_union_member]], i64 28}
+// CHECK-DAG: [[TAG_N_s_v_x_c]] = !{[[TYPE_N:!.*]], [[TYPE_union_member]], i64 0}
+// CHECK-DAG: [[TAG_R_m_s_v_x_c]] = !{[[TYPE_R:!.*]], [[TYPE_union_member]], i64 56}
+// CHECK-DAG: [[TYPE_U]] = !{!"_ZTS1U", [[TYPE_union_member]], i64 0}
+// CHECK-DAG: [[TYPE_S]] = !{!"_ZTS1S", [[TYPE_U]], i64 0, [[TYPE_U]], i64 28}
+// CHECK-DAG: [[TYPE_N]] = !{!"_ZTS1N", [[TYPE_union_member]], i64 0}
+// CHECK-DAG: [[TYPE_R]] = !{!"_ZTS1R", [[TYPE_N]], i64 0, [[TYPE_N]], i64 56}
+// CHECK-DAG: [[TYPE_union_member]] = !{!"union member", [[TYPE_char:!.*]], i64 0}
+// CHECK-DAG: [[TYPE_char]] = !{!"omnipotent char", {{.*}}, i64 0}
Index: cfe/trunk/test/CodeGen/union-tbaa1.c
===
--- cfe/trunk/test/CodeGen/union-tbaa1.c
+++ cfe/trunk/test/CodeGen/union-tbaa1.c
@@ -15,30 +15,32 @@
 // But no tbaa for the two stores:
 // CHECK: %uw[[UW1:[0-9]*]] = getelementptr
 // CHECK: store{{.*}}%uw[[UW1]]
-// CHECK: tbaa ![[OCPATH:[0-9]+]]
+// CHECK: tbaa [[TAG_vect32_union_member:![0-9]+]]
 // There will be a load after the store, and it will use tbaa. Make sure
 // the check-not above doesn't find it:
 // CHECK: load
   Tmp[*Index][0].uw = Arr[*Index][0] * Num;
 // CHECK: %uw[[UW2:[0-9]*]] = getelementptr
 // CHECK: store{{.*}}%uw[[UW2]]
-// CHECK: tbaa ![[OCPATH]]
+// CHECK: tbaa [[TAG_vect32_union_member]]
   Tmp[*Index][1].uw = Arr[*Index][1] * Num;
 // Same here, don't generate tbaa for the loads:
 // CHECK: %uh[[UH1:[0-9]*]] = bitcast %union.vect32
 // CHECK: %arrayidx[[AX1:[0-9]*]] = getelementptr{{.*}}%uh[[UH1]]
 // CHECK: load i16, i16* %arrayidx[[AX1]]
-// CHECK: tbaa ![[OCPATH]]
+// CHECK: tbaa [[TAG_vect32_union_member]]
 // CHECK: store
   Vec[0] = Tmp[*Index][0].uh[1];
 // CHECK: %uh[[UH2:[0-9]*]] = bitcast %union.vect32
 // CHECK: %arrayidx[[AX2:[0-9]*]] = getelementptr{{.*}}%uh[[UH2]]
 // CHECK: load i16, i16* %arrayidx[[AX2]]
-// CHECK: tbaa ![[OCPATH]]
+// CHECK: tbaa [[TAG_vect32_union_member]]
 // CHECK: store
   Vec[1] = Tmp[*Index][1].uh[1];
   bar(Tmp);
 }
 
-// CHECK-DAG: ![[CHAR:[0-9]+]] = !{!"omnipotent 

[PATCH] D39455: [CodeGen] Add initial support for union members in TBAA

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 124726.
kosarev added a comment.

- Added tests with nested unions.
- Rebased.


https://reviews.llvm.org/D39455

Files:
  lib/CodeGen/CGExpr.cpp
  lib/CodeGen/CodeGenModule.h
  lib/CodeGen/CodeGenTBAA.cpp
  lib/CodeGen/CodeGenTBAA.h
  test/CodeGen/tbaa-union.cpp
  test/CodeGen/union-tbaa1.c

Index: test/CodeGen/union-tbaa1.c
===
--- test/CodeGen/union-tbaa1.c
+++ test/CodeGen/union-tbaa1.c
@@ -15,30 +15,32 @@
 // But no tbaa for the two stores:
 // CHECK: %uw[[UW1:[0-9]*]] = getelementptr
 // CHECK: store{{.*}}%uw[[UW1]]
-// CHECK: tbaa ![[OCPATH:[0-9]+]]
+// CHECK: tbaa [[TAG_vect32_union_member:![0-9]+]]
 // There will be a load after the store, and it will use tbaa. Make sure
 // the check-not above doesn't find it:
 // CHECK: load
   Tmp[*Index][0].uw = Arr[*Index][0] * Num;
 // CHECK: %uw[[UW2:[0-9]*]] = getelementptr
 // CHECK: store{{.*}}%uw[[UW2]]
-// CHECK: tbaa ![[OCPATH]]
+// CHECK: tbaa [[TAG_vect32_union_member]]
   Tmp[*Index][1].uw = Arr[*Index][1] * Num;
 // Same here, don't generate tbaa for the loads:
 // CHECK: %uh[[UH1:[0-9]*]] = bitcast %union.vect32
 // CHECK: %arrayidx[[AX1:[0-9]*]] = getelementptr{{.*}}%uh[[UH1]]
 // CHECK: load i16, i16* %arrayidx[[AX1]]
-// CHECK: tbaa ![[OCPATH]]
+// CHECK: tbaa [[TAG_vect32_union_member]]
 // CHECK: store
   Vec[0] = Tmp[*Index][0].uh[1];
 // CHECK: %uh[[UH2:[0-9]*]] = bitcast %union.vect32
 // CHECK: %arrayidx[[AX2:[0-9]*]] = getelementptr{{.*}}%uh[[UH2]]
 // CHECK: load i16, i16* %arrayidx[[AX2]]
-// CHECK: tbaa ![[OCPATH]]
+// CHECK: tbaa [[TAG_vect32_union_member]]
 // CHECK: store
   Vec[1] = Tmp[*Index][1].uh[1];
   bar(Tmp);
 }
 
-// CHECK-DAG: ![[CHAR:[0-9]+]] = !{!"omnipotent char"
-// CHECK-DAG: ![[OCPATH]] = !{![[CHAR]], ![[CHAR]], i64 0}
+// CHECK-DAG: [[TAG_vect32_union_member]] = !{[[TYPE_vect32:!.*]], [[TYPE_union_member:!.*]], i64 0}
+// CHECK-DAG: [[TYPE_vect32]] = !{!"", [[TYPE_union_member]], i64 0}
+// CHECK-DAG: [[TYPE_union_member]] = !{!"union member", [[TYPE_char:!.*]], i64 0}
+// CHECK-DAG: [[TYPE_char]] = !{!"omnipotent char", {{.*}}}
Index: test/CodeGen/tbaa-union.cpp
===
--- test/CodeGen/tbaa-union.cpp
+++ test/CodeGen/tbaa-union.cpp
@@ -0,0 +1,100 @@
+// RUN: %clang_cc1 -triple x86_64-linux -O1 -disable-llvm-passes %s -emit-llvm -o - | FileCheck %s
+//
+// Check that we generate correct TBAA information for accesses to union
+// members.
+
+struct X {
+  int a, b;
+  int arr[3];
+  int c, d;
+};
+
+union U {
+  int i;
+  X x;
+  int j;
+};
+
+struct S {
+  U u, v;
+};
+
+union N {
+  int i;
+  S s;
+  int j;
+};
+
+struct R {
+  N n, m;
+};
+
+int f1(U *p) {
+// CHECK-LABEL: _Z2f1P1U
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_U_j:!.*]]
+  return p->j;
+}
+
+int f2(S *p) {
+// CHECK-LABEL: _Z2f2P1S
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_S_u_i:!.*]]
+  return p->u.i;
+}
+
+int f3(S *p) {
+// CHECK-LABEL: _Z2f3P1S
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_S_v_j:!.*]]
+  return p->v.j;
+}
+
+int f4(S *p) {
+// CHECK-LABEL: _Z2f4P1S
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_S_u_x_b:!.*]]
+  return p->u.x.b;
+}
+
+int f5(S *p) {
+// CHECK-LABEL: _Z2f5P1S
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_S_v_x_b:!.*]]
+  return p->v.x.b;
+}
+
+int f6(S *p) {
+// CHECK-LABEL: _Z2f6P1S
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_S_u_x_arr:!.*]]
+  return p->u.x.arr[1];
+}
+
+int f7(S *p) {
+// CHECK-LABEL: _Z2f7P1S
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_S_v_x_arr:!.*]]
+  return p->v.x.arr[1];
+}
+
+int f8(N *p) {
+// CHECK-LABEL: _Z2f8P1N
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_N_s_v_x_c:!.*]]
+  return p->s.v.x.c;
+}
+
+int f9(R *p) {
+// CHECK-LABEL: _Z2f9P1R
+// CHECK: load i32, i32* {{.*}}, !tbaa [[TAG_R_m_s_v_x_c:!.*]]
+  return p->m.s.v.x.c;
+}
+
+// CHECK-DAG: [[TAG_U_j]] = !{[[TYPE_U:!.*]], [[TYPE_union_member:!.*]], i64 0}
+// CHECK-DAG: [[TAG_S_u_i]] = !{[[TYPE_S:!.*]], [[TYPE_union_member]], i64 0}
+// CHECK-DAG: [[TAG_S_u_x_b]] = !{[[TYPE_S:!.*]], [[TYPE_union_member]], i64 0}
+// CHECK-DAG: [[TAG_S_u_x_arr]] = !{[[TYPE_S:!.*]], [[TYPE_union_member]], i64 0}
+// CHECK-DAG: [[TAG_S_v_j]] = !{[[TYPE_S:!.*]], [[TYPE_union_member]], i64 28}
+// CHECK-DAG: [[TAG_S_v_x_b]] = !{[[TYPE_S:!.*]], [[TYPE_union_member]], i64 28}
+// CHECK-DAG: [[TAG_S_v_x_arr]] = !{[[TYPE_S:!.*]], [[TYPE_union_member]], i64 28}
+// CHECK-DAG: [[TAG_N_s_v_x_c]] = !{[[TYPE_N:!.*]], [[TYPE_union_member]], i64 0}
+// CHECK-DAG: [[TAG_R_m_s_v_x_c]] = !{[[TYPE_R:!.*]], [[TYPE_union_member]], i64 56}
+// CHECK-DAG: [[TYPE_U]] = !{!"_ZTS1U", [[TYPE_union_member]], i64 0}
+// CHECK-DAG: [[TYPE_S]] = !{!"_ZTS1S", [[TYPE_U]], i64 0, [[TYPE_U]], i64 28}
+// CHECK-DAG: [[TYPE_N]] = !{!"_ZTS1N", [[TYPE_union_member]], i64 0}
+// CHECK-DAG: [[TYPE_R]] = !{!"_ZTS1R", [[TYPE_N]], i64 0, [[TYPE_N]], i64 56}
+// CHECK-DAG: [[TYPE_union_member]] = !{!"union member", 

[PATCH] D40176: [CodeGen] Collect information about sizes of accesses and access types for TBAA

[Ivan Kosarev via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL319012: [CodeGen] Collect information about sizes of 
accesses and access types for TBAA (authored by kosarev).

Changed prior to commit:
  https://reviews.llvm.org/D40176?vs=124084=124332#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D40176

Files:
  cfe/trunk/lib/CodeGen/CGClass.cpp
  cfe/trunk/lib/CodeGen/CodeGenModule.cpp
  cfe/trunk/lib/CodeGen/CodeGenModule.h
  cfe/trunk/lib/CodeGen/CodeGenTBAA.cpp
  cfe/trunk/lib/CodeGen/CodeGenTBAA.h

Index: cfe/trunk/lib/CodeGen/CodeGenTBAA.h
===
--- cfe/trunk/lib/CodeGen/CodeGenTBAA.h
+++ cfe/trunk/lib/CodeGen/CodeGenTBAA.h
@@ -36,40 +36,53 @@
 enum class TBAAAccessKind : unsigned {
   Ordinary,
   MayAlias,
+  Incomplete,
 };
 
 // TBAAAccessInfo - Describes a memory access in terms of TBAA.
 struct TBAAAccessInfo {
   TBAAAccessInfo(TBAAAccessKind Kind, llvm::MDNode *BaseType,
- llvm::MDNode *AccessType, uint64_t Offset)
-: Kind(Kind), BaseType(BaseType), AccessType(AccessType), Offset(Offset)
+ llvm::MDNode *AccessType, uint64_t Offset, uint64_t Size)
+: Kind(Kind), BaseType(BaseType), AccessType(AccessType),
+  Offset(Offset), Size(Size)
   {}
 
   TBAAAccessInfo(llvm::MDNode *BaseType, llvm::MDNode *AccessType,
- uint64_t Offset)
-: TBAAAccessInfo(TBAAAccessKind::Ordinary, BaseType, AccessType, Offset)
+ uint64_t Offset, uint64_t Size)
+: TBAAAccessInfo(TBAAAccessKind::Ordinary, BaseType, AccessType,
+ Offset, Size)
   {}
 
-  explicit TBAAAccessInfo(llvm::MDNode *AccessType)
-: TBAAAccessInfo(/* BaseType= */ nullptr, AccessType, /* Offset= */ 0)
+  explicit TBAAAccessInfo(llvm::MDNode *AccessType, uint64_t Size)
+: TBAAAccessInfo(/* BaseType= */ nullptr, AccessType, /* Offset= */ 0, Size)
   {}
 
   TBAAAccessInfo()
-: TBAAAccessInfo(/* AccessType= */ nullptr)
+: TBAAAccessInfo(/* AccessType= */ nullptr, /* Size= */ 0)
   {}
 
   static TBAAAccessInfo getMayAliasInfo() {
-return TBAAAccessInfo(TBAAAccessKind::MayAlias, /* BaseType= */ nullptr,
-  /* AccessType= */ nullptr, /* Offset= */ 0);
+return TBAAAccessInfo(TBAAAccessKind::MayAlias,
+  /* BaseType= */ nullptr, /* AccessType= */ nullptr,
+  /* Offset= */ 0, /* Size= */ 0);
   }
 
   bool isMayAlias() const { return Kind == TBAAAccessKind::MayAlias; }
 
+  static TBAAAccessInfo getIncompleteInfo() {
+return TBAAAccessInfo(TBAAAccessKind::Incomplete,
+  /* BaseType= */ nullptr, /* AccessType= */ nullptr,
+  /* Offset= */ 0, /* Size= */ 0);
+  }
+
+  bool isIncomplete() const { return Kind == TBAAAccessKind::Incomplete; }
+
   bool operator==(const TBAAAccessInfo ) const {
 return Kind == Other.Kind &&
BaseType == Other.BaseType &&
AccessType == Other.AccessType &&
-   Offset == Other.Offset;
+   Offset == Other.Offset &&
+   Size == Other.Size;
   }
 
   bool operator!=(const TBAAAccessInfo ) const {
@@ -95,12 +108,16 @@
   /// Offset - The byte offset of the final access within the base one. Must be
   /// zero if the base access type is not specified.
   uint64_t Offset;
+
+  /// Size - The size of access, in bytes.
+  uint64_t Size;
 };
 
 /// CodeGenTBAA - This class organizes the cross-module state that is used
 /// while lowering AST types to LLVM types.
 class CodeGenTBAA {
   ASTContext 
+  llvm::Module 
   const CodeGenOptions 
   const LangOptions 
   MangleContext 
@@ -138,10 +155,10 @@
  SmallVectorImpl ,
  bool MayAlias);
 
-  /// A wrapper function to create a scalar type. For struct-path aware TBAA,
-  /// the scalar type has the same format as the struct type: name, offset,
-  /// pointer to another node in the type DAG.
-  llvm::MDNode *createTBAAScalarType(StringRef Name, llvm::MDNode *Parent);
+  /// createScalarTypeNode - A wrapper function to create a metadata node
+  /// describing a scalar type.
+  llvm::MDNode *createScalarTypeNode(StringRef Name, llvm::MDNode *Parent,
+ uint64_t Size);
 
   /// getTypeInfoHelper - An internal helper function to generate metadata used
   /// to describe accesses to objects of the given type.
@@ -152,19 +169,17 @@
   llvm::MDNode *getBaseTypeInfoHelper(const Type *Ty);
 
 public:
-  CodeGenTBAA(ASTContext , llvm::LLVMContext ,
-  const CodeGenOptions ,
-  const LangOptions ,
-  MangleContext );
+  CodeGenTBAA(ASTContext , llvm::Module , const CodeGenOptions ,
+  const LangOptions , MangleContext );
   ~CodeGenTBAA();
 
   /// getTypeInfo - Get metadata used to describe accesses to objects of the
   /// given type.
   llvm::MDNode *getTypeInfo(QualType QTy);
 
   /// 

[PATCH] D40176: [CodeGen] Collect information about sizes of accesses and access types for TBAA

[Ivan Kosarev via Phabricator via cfe-commits]

kosarev updated this revision to Diff 124084.
kosarev added a comment.

Rebased.


https://reviews.llvm.org/D40176

Files:
  lib/CodeGen/CGClass.cpp
  lib/CodeGen/CodeGenModule.cpp
  lib/CodeGen/CodeGenModule.h
  lib/CodeGen/CodeGenTBAA.cpp
  lib/CodeGen/CodeGenTBAA.h

Index: lib/CodeGen/CodeGenTBAA.h
===
--- lib/CodeGen/CodeGenTBAA.h
+++ lib/CodeGen/CodeGenTBAA.h
@@ -36,40 +36,53 @@
 enum class TBAAAccessKind : unsigned {
   Ordinary,
   MayAlias,
+  Incomplete,
 };
 
 // TBAAAccessInfo - Describes a memory access in terms of TBAA.
 struct TBAAAccessInfo {
   TBAAAccessInfo(TBAAAccessKind Kind, llvm::MDNode *BaseType,
- llvm::MDNode *AccessType, uint64_t Offset)
-: Kind(Kind), BaseType(BaseType), AccessType(AccessType), Offset(Offset)
+ llvm::MDNode *AccessType, uint64_t Offset, uint64_t Size)
+: Kind(Kind), BaseType(BaseType), AccessType(AccessType),
+  Offset(Offset), Size(Size)
   {}
 
   TBAAAccessInfo(llvm::MDNode *BaseType, llvm::MDNode *AccessType,
- uint64_t Offset)
-: TBAAAccessInfo(TBAAAccessKind::Ordinary, BaseType, AccessType, Offset)
+ uint64_t Offset, uint64_t Size)
+: TBAAAccessInfo(TBAAAccessKind::Ordinary, BaseType, AccessType,
+ Offset, Size)
   {}
 
-  explicit TBAAAccessInfo(llvm::MDNode *AccessType)
-: TBAAAccessInfo(/* BaseType= */ nullptr, AccessType, /* Offset= */ 0)
+  explicit TBAAAccessInfo(llvm::MDNode *AccessType, uint64_t Size)
+: TBAAAccessInfo(/* BaseType= */ nullptr, AccessType, /* Offset= */ 0, Size)
   {}
 
   TBAAAccessInfo()
-: TBAAAccessInfo(/* AccessType= */ nullptr)
+: TBAAAccessInfo(/* AccessType= */ nullptr, /* Size= */ 0)
   {}
 
   static TBAAAccessInfo getMayAliasInfo() {
-return TBAAAccessInfo(TBAAAccessKind::MayAlias, /* BaseType= */ nullptr,
-  /* AccessType= */ nullptr, /* Offset= */ 0);
+return TBAAAccessInfo(TBAAAccessKind::MayAlias,
+  /* BaseType= */ nullptr, /* AccessType= */ nullptr,
+  /* Offset= */ 0, /* Size= */ 0);
   }
 
   bool isMayAlias() const { return Kind == TBAAAccessKind::MayAlias; }
 
+  static TBAAAccessInfo getIncompleteInfo() {
+return TBAAAccessInfo(TBAAAccessKind::Incomplete,
+  /* BaseType= */ nullptr, /* AccessType= */ nullptr,
+  /* Offset= */ 0, /* Size= */ 0);
+  }
+
+  bool isIncomplete() const { return Kind == TBAAAccessKind::Incomplete; }
+
   bool operator==(const TBAAAccessInfo ) const {
 return Kind == Other.Kind &&
BaseType == Other.BaseType &&
AccessType == Other.AccessType &&
-   Offset == Other.Offset;
+   Offset == Other.Offset &&
+   Size == Other.Size;
   }
 
   bool operator!=(const TBAAAccessInfo ) const {
@@ -95,12 +108,16 @@
   /// Offset - The byte offset of the final access within the base one. Must be
   /// zero if the base access type is not specified.
   uint64_t Offset;
+
+  /// Size - The size of access, in bytes.
+  uint64_t Size;
 };
 
 /// CodeGenTBAA - This class organizes the cross-module state that is used
 /// while lowering AST types to LLVM types.
 class CodeGenTBAA {
   ASTContext 
+  llvm::Module 
   const CodeGenOptions 
   const LangOptions 
   MangleContext 
@@ -138,10 +155,10 @@
  SmallVectorImpl ,
  bool MayAlias);
 
-  /// A wrapper function to create a scalar type. For struct-path aware TBAA,
-  /// the scalar type has the same format as the struct type: name, offset,
-  /// pointer to another node in the type DAG.
-  llvm::MDNode *createTBAAScalarType(StringRef Name, llvm::MDNode *Parent);
+  /// createScalarTypeNode - A wrapper function to create a metadata node
+  /// describing a scalar type.
+  llvm::MDNode *createScalarTypeNode(StringRef Name, llvm::MDNode *Parent,
+ uint64_t Size);
 
   /// getTypeInfoHelper - An internal helper function to generate metadata used
   /// to describe accesses to objects of the given type.
@@ -152,19 +169,17 @@
   llvm::MDNode *getBaseTypeInfoHelper(const Type *Ty);
 
 public:
-  CodeGenTBAA(ASTContext , llvm::LLVMContext ,
-  const CodeGenOptions ,
-  const LangOptions ,
-  MangleContext );
+  CodeGenTBAA(ASTContext , llvm::Module , const CodeGenOptions ,
+  const LangOptions , MangleContext );
   ~CodeGenTBAA();
 
   /// getTypeInfo - Get metadata used to describe accesses to objects of the
   /// given type.
   llvm::MDNode *getTypeInfo(QualType QTy);
 
   /// getVTablePtrAccessInfo - Get the TBAA information that describes an
   /// access to a virtual table pointer.
-  TBAAAccessInfo getVTablePtrAccessInfo();
+  TBAAAccessInfo getVTablePtrAccessInfo(llvm::Type *VTablePtrType);
 
   /// getTBAAStructInfo - Get the TBAAStruct MDNode to be used for a memcpy of