[clang] [llvm] [AMDGPU][Clang] Add check of size for __builtin_amdgcn_global_load_lds (PR #93064)
https://github.com/shiltian closed https://github.com/llvm/llvm-project/pull/93064 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU][Clang] Add check of size for __builtin_amdgcn_global_load_lds (PR #93064)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/93064
>From 1f5353d9539e42cbd6e7bd70d948041001373d2a Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 23 May 2024 10:04:26 -0400
Subject: [PATCH] [AMDGPU][Clang] Add check of size for
__builtin_amdgcn_global_load_lds
---
.../clang/Basic/DiagnosticSemaKinds.td| 4
clang/lib/Sema/SemaChecking.cpp | 22 +++
.../SemaOpenCL/builtins-amdgcn-gfx940-err.cl | 14
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 2 +-
4 files changed, 41 insertions(+), 1 deletion(-)
create mode 100644 clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index cc402182687f3..50b2fb8113e44 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -12385,4 +12385,8 @@ def err_acc_reduction_composite_type
def err_acc_reduction_composite_member_type :Error<
"OpenACC 'reduction' composite variable must not have non-scalar field">;
def note_acc_reduction_composite_member_loc : Note<"invalid field is here">;
+
+// AMDGCN builtins diagnostics
+def err_amdgcn_global_load_lds_size_invalid_value : Error<"invalid size
value">;
+def note_amdgcn_global_load_lds_size_valid_value : Note<"size must be 1, 2, or
4">;
} // end of sema component.
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index dd48490e6dd42..fac9a58fa2689 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5696,6 +5696,28 @@ bool Sema::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
// position of memory order and scope arguments in the builtin
unsigned OrderIndex, ScopeIndex;
switch (BuiltinID) {
+ case AMDGPU::BI__builtin_amdgcn_global_load_lds: {
+constexpr const int SizeIdx = 2;
+llvm::APSInt Size;
+Expr *ArgExpr = TheCall->getArg(SizeIdx);
+ExprResult R = VerifyIntegerConstantExpression(ArgExpr, );
+if (R.isInvalid())
+ return true;
+switch (Size.getSExtValue()) {
+case 1:
+case 2:
+case 4:
+ return false;
+default:
+ Diag(ArgExpr->getExprLoc(),
+ diag::err_amdgcn_global_load_lds_size_invalid_value)
+ << ArgExpr->getSourceRange();
+ Diag(ArgExpr->getExprLoc(),
+ diag::note_amdgcn_global_load_lds_size_valid_value)
+ << ArgExpr->getSourceRange();
+ return true;
+}
+ }
case AMDGPU::BI__builtin_amdgcn_get_fpenv:
case AMDGPU::BI__builtin_amdgcn_set_fpenv:
return false;
diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
b/clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
new file mode 100644
index 0..487cc53e8ad8a
--- /dev/null
+++ b/clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
@@ -0,0 +1,14 @@
+// RUN: %clang_cc1 -cl-std=CL2.0 -O0 -triple amdgcn-unknown-unknown
-target-cpu gfx940 -S -verify -o - %s
+// REQUIRES: amdgpu-registered-target
+
+typedef unsigned int u32;
+
+void test_global_load_lds_unsupported_size(global u32* src, local u32 *dst,
u32 size) {
+ __builtin_amdgcn_global_load_lds(src, dst, size, /*offset=*/0, /*aux=*/0);
// expected-error{{expression is not an integer constant expression}}
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/5, /*offset=*/0,
/*aux=*/0); // expected-error{{invalid size value}} expected-note {{size must
be 1, 2, or 4}}
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/0, /*offset=*/0,
/*aux=*/0); // expected-error{{invalid size value}} expected-note {{size must
be 1, 2, or 4}}
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/3, /*offset=*/0,
/*aux=*/0); // expected-error{{invalid size value}} expected-note {{size must
be 1, 2, or 4}}
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/12, /*offset=*/0,
/*aux=*/0); // expected-error{{invalid size value}} expected-note {{size must
be 1, 2, or 4}}
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/16, /*offset=*/0,
/*aux=*/0); // expected-error{{invalid size value}} expected-note {{size must
be 1, 2, or 4}}
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/-1, /*offset=*/0,
/*aux=*/0); // expected-error{{invalid size value}} expected-note {{size must
be 1, 2, or 4}}
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 5c001a4dd6247..d4a8954a4cdac 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2472,7 +2472,7 @@ class AMDGPUGlobalLoadLDS :
[],
[LLVMQualPointerType<1>,// Base global pointer to load from
LLVMQualPointerType<3>,// LDS base pointer to store to
- llvm_i32_ty, // Data byte size: 1/2/4 (/12/16 for
gfx950)
+ llvm_i32_ty, // Data byte size: 1/2/4
llvm_i32_ty,
[clang] [llvm] [AMDGPU][Clang] Add check of size for __builtin_amdgcn_global_load_lds (PR #93064)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/93064
>From e12473d466d7b354ecff0b8ea553b64d3059e1cf Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 23 May 2024 09:07:31 -0400
Subject: [PATCH] [AMDGPU][Clang] Add check of size for
__builtin_amdgcn_global_load_lds
---
.../clang/Basic/DiagnosticSemaKinds.td| 4
clang/lib/Sema/SemaChecking.cpp | 22 +++
.../SemaOpenCL/builtins-amdgcn-gfx940-err.cl | 13 +++
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 2 +-
4 files changed, 40 insertions(+), 1 deletion(-)
create mode 100644 clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index cc402182687f3..085f3111ff422 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -12385,4 +12385,8 @@ def err_acc_reduction_composite_type
def err_acc_reduction_composite_member_type :Error<
"OpenACC 'reduction' composite variable must not have non-scalar field">;
def note_acc_reduction_composite_member_loc : Note<"invalid field is here">;
+
+// AMDGCN builtins diagnostics
+def err_amdgcn_global_load_lds_size_invalid_value : Error<"invalid size
value">;
+def note_amdgcn_global_load_lds_size_valid_value : Note<"size must be 1/2/4">;
} // end of sema component.
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index dd48490e6dd42..fac9a58fa2689 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5696,6 +5696,28 @@ bool Sema::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
// position of memory order and scope arguments in the builtin
unsigned OrderIndex, ScopeIndex;
switch (BuiltinID) {
+ case AMDGPU::BI__builtin_amdgcn_global_load_lds: {
+constexpr const int SizeIdx = 2;
+llvm::APSInt Size;
+Expr *ArgExpr = TheCall->getArg(SizeIdx);
+ExprResult R = VerifyIntegerConstantExpression(ArgExpr, );
+if (R.isInvalid())
+ return true;
+switch (Size.getSExtValue()) {
+case 1:
+case 2:
+case 4:
+ return false;
+default:
+ Diag(ArgExpr->getExprLoc(),
+ diag::err_amdgcn_global_load_lds_size_invalid_value)
+ << ArgExpr->getSourceRange();
+ Diag(ArgExpr->getExprLoc(),
+ diag::note_amdgcn_global_load_lds_size_valid_value)
+ << ArgExpr->getSourceRange();
+ return true;
+}
+ }
case AMDGPU::BI__builtin_amdgcn_get_fpenv:
case AMDGPU::BI__builtin_amdgcn_set_fpenv:
return false;
diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
b/clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
new file mode 100644
index 0..0ebe56197ed33
--- /dev/null
+++ b/clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
@@ -0,0 +1,13 @@
+// RUN: %clang_cc1 -cl-std=CL2.0 -O0 -triple amdgcn-unknown-unknown
-target-cpu gfx940 -S -verify -o - %s
+// REQUIRES: amdgpu-registered-target
+
+typedef unsigned int u32;
+
+void test_global_load_lds_unsupported_size(global u32* src, local u32 *dst,
u32 size) {
+ __builtin_amdgcn_global_load_lds(src, dst, size, /*offset=*/0, /*aux=*/0);
// expected-error{{expression is not an integer constant expression}}
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/5, /*offset=*/0,
/*aux=*/0); // expected-error{{invalid size value}} expected-note {{size must
be 1/2/4}}
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/0, /*offset=*/0,
/*aux=*/0); // expected-error{{invalid size value}} expected-note {{size must
be 1/2/4}}
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/3, /*offset=*/0,
/*aux=*/0); // expected-error{{invalid size value}} expected-note {{size must
be 1/2/4}}
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/12, /*offset=*/0,
/*aux=*/0); // expected-error{{invalid size value}} expected-note {{size must
be 1/2/4}}
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/16, /*offset=*/0,
/*aux=*/0); // expected-error{{invalid size value}} expected-note {{size must
be 1/2/4}}
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 5c001a4dd6247..d4a8954a4cdac 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2472,7 +2472,7 @@ class AMDGPUGlobalLoadLDS :
[],
[LLVMQualPointerType<1>,// Base global pointer to load from
LLVMQualPointerType<3>,// LDS base pointer to store to
- llvm_i32_ty, // Data byte size: 1/2/4 (/12/16 for
gfx950)
+ llvm_i32_ty, // Data byte size: 1/2/4
llvm_i32_ty, // imm offset (applied to both global
and LDS address)
llvm_i32_ty], // auxiliary data (imm, cachepolicy
(bit 0 = sc0,
//
[clang] [llvm] [AMDGPU][Clang] Add check of size for __builtin_amdgcn_global_load_lds (PR #93064)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/93064
>From 6096d6a7a672786807173f2cbe3c08beb1b9ad74 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 22 May 2024 16:11:04 -0400
Subject: [PATCH] [AMDGPU][Clang] Add check of size for
__builtin_amdgcn_global_load_lds
---
.../clang/Basic/DiagnosticSemaKinds.td| 4
clang/lib/Sema/SemaChecking.cpp | 22 +++
.../SemaOpenCL/builtins-amdgcn-gfx940-err.cl | 9
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 2 +-
4 files changed, 36 insertions(+), 1 deletion(-)
create mode 100644 clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 761243ed96cb7..7130324ef3810 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -12391,4 +12391,8 @@ def err_acc_reduction_composite_type
def err_acc_reduction_composite_member_type :Error<
"OpenACC 'reduction' composite variable must not have non-scalar field">;
def note_acc_reduction_composite_member_loc : Note<"invalid field is here">;
+
+// AMDGCN builtins diagnostics
+def err_amdgcn_global_load_lds_size_invalid_value : Error<"invalid size
value">;
+def note_amdgcn_global_load_lds_size_valid_value : Note<"size must be 1/2/4">;
} // end of sema component.
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 8c08bf7510c85..db7cd687c7b5d 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5695,6 +5695,28 @@ bool Sema::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
// position of memory order and scope arguments in the builtin
unsigned OrderIndex, ScopeIndex;
switch (BuiltinID) {
+ case AMDGPU::BI__builtin_amdgcn_global_load_lds: {
+constexpr const int SizeIdx = 2;
+llvm::APSInt Size;
+Expr *ArgExpr = TheCall->getArg(SizeIdx);
+ExprResult R = VerifyIntegerConstantExpression(ArgExpr, );
+if (R.isInvalid())
+ return true;
+switch (Size.getSExtValue()) {
+case 1:
+case 2:
+case 4:
+ return false;
+default:
+ Diag(ArgExpr->getExprLoc(),
+ diag::err_amdgcn_global_load_lds_size_invalid_value)
+ << ArgExpr->getSourceRange();
+ Diag(ArgExpr->getExprLoc(),
+ diag::note_amdgcn_global_load_lds_size_valid_value)
+ << ArgExpr->getSourceRange();
+ return true;
+}
+ }
case AMDGPU::BI__builtin_amdgcn_get_fpenv:
case AMDGPU::BI__builtin_amdgcn_set_fpenv:
return false;
diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
b/clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
new file mode 100644
index 0..f5b28616507f1
--- /dev/null
+++ b/clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -cl-std=CL2.0 -O0 -triple amdgcn-unknown-unknown
-target-cpu gfx940 -S -verify -o - %s
+// REQUIRES: amdgpu-registered-target
+
+typedef unsigned int u32;
+
+void test_global_load_lds_unsupported_size(global u32* src, local u32 *dst,
u32 size) {
+ __builtin_amdgcn_global_load_lds(src, dst, size, /*offset=*/0, /*aux=*/0);
// expected-error{{expression is not an integer constant expression}}
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/5, /*offset=*/0,
/*aux=*/0); // expected-error{{invalid size value}} expected-note {{size must
be 1/2/4}}
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 5c001a4dd6247..d4a8954a4cdac 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2472,7 +2472,7 @@ class AMDGPUGlobalLoadLDS :
[],
[LLVMQualPointerType<1>,// Base global pointer to load from
LLVMQualPointerType<3>,// LDS base pointer to store to
- llvm_i32_ty, // Data byte size: 1/2/4 (/12/16 for
gfx950)
+ llvm_i32_ty, // Data byte size: 1/2/4
llvm_i32_ty, // imm offset (applied to both global
and LDS address)
llvm_i32_ty], // auxiliary data (imm, cachepolicy
(bit 0 = sc0,
//
bit 1 = sc1,
___
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[clang] [llvm] [AMDGPU][Clang] Add check of size for __builtin_amdgcn_global_load_lds (PR #93064)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/93064
>From cc1b4f7ac1a4c0a827e843068547aa5c9748ca3e Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 22 May 2024 16:09:53 -0400
Subject: [PATCH] [AMDGPU][Clang] Add check of size for
__builtin_amdgcn_global_load_lds
---
.../clang/Basic/DiagnosticSemaKinds.td| 4 +++
clang/lib/Sema/SemaChecking.cpp | 22 +++
.../SemaOpenCL/builtins-amdgcn-gfx940-err.cl | 9 ++
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 28 +--
4 files changed, 49 insertions(+), 14 deletions(-)
create mode 100644 clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 761243ed96cb7..7130324ef3810 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -12391,4 +12391,8 @@ def err_acc_reduction_composite_type
def err_acc_reduction_composite_member_type :Error<
"OpenACC 'reduction' composite variable must not have non-scalar field">;
def note_acc_reduction_composite_member_loc : Note<"invalid field is here">;
+
+// AMDGCN builtins diagnostics
+def err_amdgcn_global_load_lds_size_invalid_value : Error<"invalid size
value">;
+def note_amdgcn_global_load_lds_size_valid_value : Note<"size must be 1/2/4">;
} // end of sema component.
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 8c08bf7510c85..db7cd687c7b5d 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5695,6 +5695,28 @@ bool Sema::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
// position of memory order and scope arguments in the builtin
unsigned OrderIndex, ScopeIndex;
switch (BuiltinID) {
+ case AMDGPU::BI__builtin_amdgcn_global_load_lds: {
+constexpr const int SizeIdx = 2;
+llvm::APSInt Size;
+Expr *ArgExpr = TheCall->getArg(SizeIdx);
+ExprResult R = VerifyIntegerConstantExpression(ArgExpr, );
+if (R.isInvalid())
+ return true;
+switch (Size.getSExtValue()) {
+case 1:
+case 2:
+case 4:
+ return false;
+default:
+ Diag(ArgExpr->getExprLoc(),
+ diag::err_amdgcn_global_load_lds_size_invalid_value)
+ << ArgExpr->getSourceRange();
+ Diag(ArgExpr->getExprLoc(),
+ diag::note_amdgcn_global_load_lds_size_valid_value)
+ << ArgExpr->getSourceRange();
+ return true;
+}
+ }
case AMDGPU::BI__builtin_amdgcn_get_fpenv:
case AMDGPU::BI__builtin_amdgcn_set_fpenv:
return false;
diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
b/clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
new file mode 100644
index 0..f5b28616507f1
--- /dev/null
+++ b/clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -cl-std=CL2.0 -O0 -triple amdgcn-unknown-unknown
-target-cpu gfx940 -S -verify -o - %s
+// REQUIRES: amdgpu-registered-target
+
+typedef unsigned int u32;
+
+void test_global_load_lds_unsupported_size(global u32* src, local u32 *dst,
u32 size) {
+ __builtin_amdgcn_global_load_lds(src, dst, size, /*offset=*/0, /*aux=*/0);
// expected-error{{expression is not an integer constant expression}}
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/5, /*offset=*/0,
/*aux=*/0); // expected-error{{invalid size value}} expected-note {{size must
be 1/2/4}}
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 5c001a4dd6247..90db7082152bb 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2467,20 +2467,20 @@ def int_amdgcn_perm :
//===--===//
class AMDGPUGlobalLoadLDS :
- ClangBuiltin<"__builtin_amdgcn_global_load_lds">,
- Intrinsic <
-[],
-[LLVMQualPointerType<1>,// Base global pointer to load from
- LLVMQualPointerType<3>,// LDS base pointer to store to
- llvm_i32_ty, // Data byte size: 1/2/4 (/12/16 for
gfx950)
- llvm_i32_ty, // imm offset (applied to both global
and LDS address)
- llvm_i32_ty], // auxiliary data (imm, cachepolicy
(bit 0 = sc0,
-//
bit 1 = sc1,
-//
bit 4 = scc))
-[IntrWillReturn, NoCapture>, NoCapture>,
- ImmArg>, ImmArg>, ImmArg>,
IntrNoCallback, IntrNoFree],
- "", [SDNPMemOperand]>;
-def int_amdgcn_global_load_lds : AMDGPUGlobalLoadLDS;
+ ClangBuiltin<"__builtin_amdgcn_global_load_lds">,
+ Intrinsic <
+ [],
+ [LLVMQualPointerType<1>,// Base global pointer to load from
+ LLVMQualPointerType<3>,// LDS
[clang] [llvm] [AMDGPU][Clang] Add check of size for __builtin_amdgcn_global_load_lds (PR #93064)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/93064
>From 0ac36053bada98dc0f9e5eb2f3b215acc06b07a5 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 22 May 2024 16:06:51 -0400
Subject: [PATCH] [AMDGPU][Clang] Add check of size for
__builtin_amdgcn_global_load_lds
---
.../clang/Basic/DiagnosticSemaKinds.td| 5
clang/lib/Sema/SemaChecking.cpp | 22 +++
.../SemaOpenCL/builtins-amdgcn-gfx940-err.cl | 9 ++
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 28 +--
4 files changed, 50 insertions(+), 14 deletions(-)
create mode 100644 clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td
b/clang/include/clang/Basic/DiagnosticSemaKinds.td
index 41a9745ddb570..2a8a179a75a3a 100644
--- a/clang/include/clang/Basic/DiagnosticSemaKinds.td
+++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td
@@ -12386,4 +12386,9 @@ def err_acc_reduction_composite_type
def err_acc_reduction_composite_member_type :Error<
"OpenACC 'reduction' composite variable must not have non-scalar field">;
def note_acc_reduction_composite_member_loc : Note<"invalid field is here">;
+
+// AMDGCN builtins diagnostics
+
+def err_amdgcn_global_load_lds_size_invalid_value : Error<"invalid size
value">;
+def note_amdgcn_global_load_lds_size_valid_value : Note<"size must be 1/2/4">;
} // end of sema component.
diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp
index 8c08bf7510c85..db7cd687c7b5d 100644
--- a/clang/lib/Sema/SemaChecking.cpp
+++ b/clang/lib/Sema/SemaChecking.cpp
@@ -5695,6 +5695,28 @@ bool Sema::CheckAMDGCNBuiltinFunctionCall(unsigned
BuiltinID,
// position of memory order and scope arguments in the builtin
unsigned OrderIndex, ScopeIndex;
switch (BuiltinID) {
+ case AMDGPU::BI__builtin_amdgcn_global_load_lds: {
+constexpr const int SizeIdx = 2;
+llvm::APSInt Size;
+Expr *ArgExpr = TheCall->getArg(SizeIdx);
+ExprResult R = VerifyIntegerConstantExpression(ArgExpr, );
+if (R.isInvalid())
+ return true;
+switch (Size.getSExtValue()) {
+case 1:
+case 2:
+case 4:
+ return false;
+default:
+ Diag(ArgExpr->getExprLoc(),
+ diag::err_amdgcn_global_load_lds_size_invalid_value)
+ << ArgExpr->getSourceRange();
+ Diag(ArgExpr->getExprLoc(),
+ diag::note_amdgcn_global_load_lds_size_valid_value)
+ << ArgExpr->getSourceRange();
+ return true;
+}
+ }
case AMDGPU::BI__builtin_amdgcn_get_fpenv:
case AMDGPU::BI__builtin_amdgcn_set_fpenv:
return false;
diff --git a/clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
b/clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
new file mode 100644
index 0..f5b28616507f1
--- /dev/null
+++ b/clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -cl-std=CL2.0 -O0 -triple amdgcn-unknown-unknown
-target-cpu gfx940 -S -verify -o - %s
+// REQUIRES: amdgpu-registered-target
+
+typedef unsigned int u32;
+
+void test_global_load_lds_unsupported_size(global u32* src, local u32 *dst,
u32 size) {
+ __builtin_amdgcn_global_load_lds(src, dst, size, /*offset=*/0, /*aux=*/0);
// expected-error{{expression is not an integer constant expression}}
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/5, /*offset=*/0,
/*aux=*/0); // expected-error{{invalid size value}} expected-note {{size must
be 1/2/4}}
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 0b774b724d0c0..293613f6328ac 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2467,20 +2467,20 @@ def int_amdgcn_perm :
//===--===//
class AMDGPUGlobalLoadLDS :
- ClangBuiltin<"__builtin_amdgcn_global_load_lds">,
- Intrinsic <
-[],
-[LLVMQualPointerType<1>,// Base global pointer to load from
- LLVMQualPointerType<3>,// LDS base pointer to store to
- llvm_i32_ty, // Data byte size: 1/2/4 (/12/16 for
gfx950)
- llvm_i32_ty, // imm offset (applied to both global
and LDS address)
- llvm_i32_ty], // auxiliary data (imm, cachepolicy
(bit 0 = sc0,
-//
bit 1 = sc1,
-//
bit 4 = scc))
-[IntrWillReturn, NoCapture>, NoCapture>,
- ImmArg>, ImmArg>, ImmArg>,
IntrNoCallback, IntrNoFree],
- "", [SDNPMemOperand]>;
-def int_amdgcn_global_load_lds : AMDGPUGlobalLoadLDS;
+ ClangBuiltin<"__builtin_amdgcn_global_load_lds">,
+ Intrinsic <
+ [],
+ [LLVMQualPointerType<1>,// Base global pointer to load from
+ LLVMQualPointerType<3>,// LDS
[clang] [llvm] [AMDGPU][Clang] Add check of size for __builtin_amdgcn_global_load_lds (PR #93064)
@@ -2537,6 +2537,47 @@ static RValue EmitHipStdParUnsupportedBuiltin(CodeGenFunction *CGF, return RValue::get(CGF->Builder.CreateCall(UBF, Args)); } +static void buildInstrinsicCallArgs(CodeGenFunction , const CallExpr *E, shiltian wrote: Yeah, no need of anything change in CGBuiltin. https://github.com/llvm/llvm-project/pull/93064 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU][Clang] Add check of size for __builtin_amdgcn_global_load_lds (PR #93064)
@@ -19040,6 +19040,48 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
CGM.getIntrinsic(Intrinsic::amdgcn_s_sendmsg_rtn, {ResultType});
return Builder.CreateCall(F, {Arg});
}
+ case AMDGPU::BI__builtin_amdgcn_global_load_lds: {
+SmallVector Args;
+unsigned ICEArguments = 0;
+ASTContext::GetBuiltinTypeError Error;
+getContext().GetBuiltinType(BuiltinID, Error, );
+assert(Error == ASTContext::GE_None && "Should not codegen an error");
+Function *F = CGM.getIntrinsic(Intrinsic::amdgcn_global_load_lds);
+llvm::FunctionType *FTy = F->getFunctionType();
+for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
+ Value *ArgValue = EmitScalarOrConstFoldImmArg(ICEArguments, i, E);
+ llvm::Type *PTy = FTy->getParamType(i);
+ if (PTy != ArgValue->getType()) {
+if (auto *PtrTy = dyn_cast(PTy)) {
+ if (PtrTy->getAddressSpace() !=
+ ArgValue->getType()->getPointerAddressSpace()) {
+ArgValue = Builder.CreateAddrSpaceCast(
+ArgValue, llvm::PointerType::get(getLLVMContext(),
+ PtrTy->getAddressSpace()));
+ }
+}
shiltian wrote:
Aha, good to know!
https://github.com/llvm/llvm-project/pull/93064
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[clang] [llvm] [AMDGPU][Clang] Add check of size for __builtin_amdgcn_global_load_lds (PR #93064)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/93064
>From 630adf5665f6e030f924b8da864b139382c30dea Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 22 May 2024 12:51:42 -0400
Subject: [PATCH] [AMDGPU][Clang] Add check of size for
__builtin_amdgcn_global_load_lds
---
clang/lib/CodeGen/CGBuiltin.cpp | 101 +++---
.../SemaOpenCL/builtins-amdgcn-gfx940-err.cl | 9 ++
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 22 ++--
3 files changed, 83 insertions(+), 49 deletions(-)
create mode 100644 clang/test/SemaOpenCL/builtins-amdgcn-gfx940-err.cl
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index ba94bf89e4751..b39b9d4f0ae85 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -2537,6 +2537,47 @@ static RValue
EmitHipStdParUnsupportedBuiltin(CodeGenFunction *CGF,
return RValue::get(CGF->Builder.CreateCall(UBF, Args));
}
+static void buildInstrinsicCallArgs(CodeGenFunction , const CallExpr *E,
+unsigned BuiltinID,
+Function *Callee,
+SmallVectorImpl ) {
+ // Find out if any arguments are required to be integer constant
+ // expressions.
+ unsigned ICEArguments = 0;
+ ASTContext::GetBuiltinTypeError Error;
+ CGF.getContext().GetBuiltinType(BuiltinID, Error, );
+ assert(Error == ASTContext::GE_None && "Should not codegen an error");
+
+ llvm::FunctionType *FTy = Callee->getFunctionType();
+
+ for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
+Value *ArgValue = CGF.EmitScalarOrConstFoldImmArg(ICEArguments, i, E);
+// If the intrinsic arg type is different from the builtin arg type
+// we need to do a bit cast.
+llvm::Type *PTy = FTy->getParamType(i);
+if (PTy != ArgValue->getType()) {
+ // XXX - vector of pointers?
+ if (auto *PtrTy = dyn_cast(PTy)) {
+if (PtrTy->getAddressSpace() !=
+ArgValue->getType()->getPointerAddressSpace()) {
+ ArgValue = CGF.Builder.CreateAddrSpaceCast(
+ ArgValue, llvm::PointerType::get(CGF.getLLVMContext(),
+ PtrTy->getAddressSpace()));
+}
+ }
+ // Cast vector type (e.g., v256i32) to x86_amx, this only happen
+ // in amx intrinsics.
+ if (PTy->isX86_AMXTy())
+ArgValue =
+CGF.Builder.CreateIntrinsic(Intrinsic::x86_cast_vector_to_tile,
+{ArgValue->getType()}, {ArgValue});
+ else
+ArgValue = CGF.Builder.CreateBitCast(ArgValue, PTy);
+}
+Args.push_back(ArgValue);
+ }
+}
+
RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned
BuiltinID,
const CallExpr *E,
ReturnValueSlot ReturnValue) {
@@ -6024,44 +6065,8 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
if (IntrinsicID != Intrinsic::not_intrinsic) {
SmallVector Args;
-
-// Find out if any arguments are required to be integer constant
-// expressions.
-unsigned ICEArguments = 0;
-ASTContext::GetBuiltinTypeError Error;
-getContext().GetBuiltinType(BuiltinID, Error, );
-assert(Error == ASTContext::GE_None && "Should not codegen an error");
-
Function *F = CGM.getIntrinsic(IntrinsicID);
-llvm::FunctionType *FTy = F->getFunctionType();
-
-for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
- Value *ArgValue = EmitScalarOrConstFoldImmArg(ICEArguments, i, E);
- // If the intrinsic arg type is different from the builtin arg type
- // we need to do a bit cast.
- llvm::Type *PTy = FTy->getParamType(i);
- if (PTy != ArgValue->getType()) {
-// XXX - vector of pointers?
-if (auto *PtrTy = dyn_cast(PTy)) {
- if (PtrTy->getAddressSpace() !=
- ArgValue->getType()->getPointerAddressSpace()) {
-ArgValue = Builder.CreateAddrSpaceCast(
-ArgValue, llvm::PointerType::get(getLLVMContext(),
- PtrTy->getAddressSpace()));
- }
-}
-
-// Cast vector type (e.g., v256i32) to x86_amx, this only happen
-// in amx intrinsics.
-if (PTy->isX86_AMXTy())
- ArgValue =
Builder.CreateIntrinsic(Intrinsic::x86_cast_vector_to_tile,
- {ArgValue->getType()},
{ArgValue});
-else
- ArgValue = Builder.CreateBitCast(ArgValue, PTy);
- }
-
- Args.push_back(ArgValue);
-}
+buildInstrinsicCallArgs(*this, E, BuiltinID, F, Args);
Value *V = Builder.CreateCall(F, Args);
QualType BuiltinRetType = E->getType();
@@ -19040,6 +19045,28 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
[clang] [llvm] [AMDGPU][Clang] Add check of size for __builtin_amdgcn_global_load_lds (PR #93064)
@@ -19040,6 +19040,48 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
CGM.getIntrinsic(Intrinsic::amdgcn_s_sendmsg_rtn, {ResultType});
return Builder.CreateCall(F, {Arg});
}
+ case AMDGPU::BI__builtin_amdgcn_global_load_lds: {
+SmallVector Args;
+unsigned ICEArguments = 0;
+ASTContext::GetBuiltinTypeError Error;
+getContext().GetBuiltinType(BuiltinID, Error, );
+assert(Error == ASTContext::GE_None && "Should not codegen an error");
+Function *F = CGM.getIntrinsic(Intrinsic::amdgcn_global_load_lds);
+llvm::FunctionType *FTy = F->getFunctionType();
+for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
+ Value *ArgValue = EmitScalarOrConstFoldImmArg(ICEArguments, i, E);
+ llvm::Type *PTy = FTy->getParamType(i);
+ if (PTy != ArgValue->getType()) {
+if (auto *PtrTy = dyn_cast(PTy)) {
+ if (PtrTy->getAddressSpace() !=
+ ArgValue->getType()->getPointerAddressSpace()) {
+ArgValue = Builder.CreateAddrSpaceCast(
+ArgValue, llvm::PointerType::get(getLLVMContext(),
+ PtrTy->getAddressSpace()));
+ }
+}
shiltian wrote:
@yxsamliu Do we have Sema for builtin?
https://github.com/llvm/llvm-project/pull/93064
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[clang] [llvm] [AMDGPU][Clang] Add check of size for __builtin_amdgcn_global_load_lds (PR #93064)
@@ -19040,6 +19040,48 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
CGM.getIntrinsic(Intrinsic::amdgcn_s_sendmsg_rtn, {ResultType});
return Builder.CreateCall(F, {Arg});
}
+ case AMDGPU::BI__builtin_amdgcn_global_load_lds: {
+SmallVector Args;
+unsigned ICEArguments = 0;
+ASTContext::GetBuiltinTypeError Error;
+getContext().GetBuiltinType(BuiltinID, Error, );
+assert(Error == ASTContext::GE_None && "Should not codegen an error");
+Function *F = CGM.getIntrinsic(Intrinsic::amdgcn_global_load_lds);
+llvm::FunctionType *FTy = F->getFunctionType();
+for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
+ Value *ArgValue = EmitScalarOrConstFoldImmArg(ICEArguments, i, E);
+ llvm::Type *PTy = FTy->getParamType(i);
+ if (PTy != ArgValue->getType()) {
+if (auto *PtrTy = dyn_cast(PTy)) {
+ if (PtrTy->getAddressSpace() !=
+ ArgValue->getType()->getPointerAddressSpace()) {
+ArgValue = Builder.CreateAddrSpaceCast(
+ArgValue, llvm::PointerType::get(getLLVMContext(),
+ PtrTy->getAddressSpace()));
+ }
+}
+ArgValue = Builder.CreateBitCast(ArgValue, PTy);
shiltian wrote:
That is copied from existing code. I have outlined that part.
https://github.com/llvm/llvm-project/pull/93064
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[clang] [llvm] [AMDGPU][Clang] Add check of size for __builtin_amdgcn_global_load_lds (PR #93064)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/93064
>From cf074221241e4d5c83426c58f70438fb592ca7ad Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 22 May 2024 12:36:33 -0400
Subject: [PATCH] [AMDGPU][Clang] Add check of size for
__builtin_amdgcn_global_load_lds
---
clang/lib/CodeGen/CGBuiltin.cpp | 101 +++---
.../builtins-amdgcn-gfx940-err.cl | 9 ++
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 22 ++--
3 files changed, 83 insertions(+), 49 deletions(-)
create mode 100644 clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940-err.cl
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index ba94bf89e4751..b39b9d4f0ae85 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -2537,6 +2537,47 @@ static RValue
EmitHipStdParUnsupportedBuiltin(CodeGenFunction *CGF,
return RValue::get(CGF->Builder.CreateCall(UBF, Args));
}
+static void buildInstrinsicCallArgs(CodeGenFunction , const CallExpr *E,
+unsigned BuiltinID,
+Function *Callee,
+SmallVectorImpl ) {
+ // Find out if any arguments are required to be integer constant
+ // expressions.
+ unsigned ICEArguments = 0;
+ ASTContext::GetBuiltinTypeError Error;
+ CGF.getContext().GetBuiltinType(BuiltinID, Error, );
+ assert(Error == ASTContext::GE_None && "Should not codegen an error");
+
+ llvm::FunctionType *FTy = Callee->getFunctionType();
+
+ for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
+Value *ArgValue = CGF.EmitScalarOrConstFoldImmArg(ICEArguments, i, E);
+// If the intrinsic arg type is different from the builtin arg type
+// we need to do a bit cast.
+llvm::Type *PTy = FTy->getParamType(i);
+if (PTy != ArgValue->getType()) {
+ // XXX - vector of pointers?
+ if (auto *PtrTy = dyn_cast(PTy)) {
+if (PtrTy->getAddressSpace() !=
+ArgValue->getType()->getPointerAddressSpace()) {
+ ArgValue = CGF.Builder.CreateAddrSpaceCast(
+ ArgValue, llvm::PointerType::get(CGF.getLLVMContext(),
+ PtrTy->getAddressSpace()));
+}
+ }
+ // Cast vector type (e.g., v256i32) to x86_amx, this only happen
+ // in amx intrinsics.
+ if (PTy->isX86_AMXTy())
+ArgValue =
+CGF.Builder.CreateIntrinsic(Intrinsic::x86_cast_vector_to_tile,
+{ArgValue->getType()}, {ArgValue});
+ else
+ArgValue = CGF.Builder.CreateBitCast(ArgValue, PTy);
+}
+Args.push_back(ArgValue);
+ }
+}
+
RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned
BuiltinID,
const CallExpr *E,
ReturnValueSlot ReturnValue) {
@@ -6024,44 +6065,8 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
if (IntrinsicID != Intrinsic::not_intrinsic) {
SmallVector Args;
-
-// Find out if any arguments are required to be integer constant
-// expressions.
-unsigned ICEArguments = 0;
-ASTContext::GetBuiltinTypeError Error;
-getContext().GetBuiltinType(BuiltinID, Error, );
-assert(Error == ASTContext::GE_None && "Should not codegen an error");
-
Function *F = CGM.getIntrinsic(IntrinsicID);
-llvm::FunctionType *FTy = F->getFunctionType();
-
-for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
- Value *ArgValue = EmitScalarOrConstFoldImmArg(ICEArguments, i, E);
- // If the intrinsic arg type is different from the builtin arg type
- // we need to do a bit cast.
- llvm::Type *PTy = FTy->getParamType(i);
- if (PTy != ArgValue->getType()) {
-// XXX - vector of pointers?
-if (auto *PtrTy = dyn_cast(PTy)) {
- if (PtrTy->getAddressSpace() !=
- ArgValue->getType()->getPointerAddressSpace()) {
-ArgValue = Builder.CreateAddrSpaceCast(
-ArgValue, llvm::PointerType::get(getLLVMContext(),
- PtrTy->getAddressSpace()));
- }
-}
-
-// Cast vector type (e.g., v256i32) to x86_amx, this only happen
-// in amx intrinsics.
-if (PTy->isX86_AMXTy())
- ArgValue =
Builder.CreateIntrinsic(Intrinsic::x86_cast_vector_to_tile,
- {ArgValue->getType()},
{ArgValue});
-else
- ArgValue = Builder.CreateBitCast(ArgValue, PTy);
- }
-
- Args.push_back(ArgValue);
-}
+buildInstrinsicCallArgs(*this, E, BuiltinID, F, Args);
Value *V = Builder.CreateCall(F, Args);
QualType BuiltinRetType = E->getType();
@@ -19040,6 +19045,28 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
[clang] [llvm] [AMDGPU][Clang] Add check of size for __builtin_amdgcn_global_load_lds (PR #93064)
@@ -19040,6 +19040,48 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
CGM.getIntrinsic(Intrinsic::amdgcn_s_sendmsg_rtn, {ResultType});
return Builder.CreateCall(F, {Arg});
}
+ case AMDGPU::BI__builtin_amdgcn_global_load_lds: {
+SmallVector Args;
+unsigned ICEArguments = 0;
+ASTContext::GetBuiltinTypeError Error;
+getContext().GetBuiltinType(BuiltinID, Error, );
+assert(Error == ASTContext::GE_None && "Should not codegen an error");
+Function *F = CGM.getIntrinsic(Intrinsic::amdgcn_global_load_lds);
+llvm::FunctionType *FTy = F->getFunctionType();
+for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
+ Value *ArgValue = EmitScalarOrConstFoldImmArg(ICEArguments, i, E);
+ llvm::Type *PTy = FTy->getParamType(i);
+ if (PTy != ArgValue->getType()) {
+if (auto *PtrTy = dyn_cast(PTy)) {
+ if (PtrTy->getAddressSpace() !=
+ ArgValue->getType()->getPointerAddressSpace()) {
+ArgValue = Builder.CreateAddrSpaceCast(
+ArgValue, llvm::PointerType::get(getLLVMContext(),
+ PtrTy->getAddressSpace()));
+ }
+}
shiltian wrote:
Because the builtin can be used not only in OpenCL, I don't think it would be
good to put it in SemaOpenCL.
https://github.com/llvm/llvm-project/pull/93064
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[clang] [llvm] [AMDGPU][Clang] Add check of size for __builtin_amdgcn_global_load_lds (PR #93064)
@@ -19040,6 +19040,48 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
CGM.getIntrinsic(Intrinsic::amdgcn_s_sendmsg_rtn, {ResultType});
return Builder.CreateCall(F, {Arg});
}
+ case AMDGPU::BI__builtin_amdgcn_global_load_lds: {
+SmallVector Args;
+unsigned ICEArguments = 0;
+ASTContext::GetBuiltinTypeError Error;
+getContext().GetBuiltinType(BuiltinID, Error, );
+assert(Error == ASTContext::GE_None && "Should not codegen an error");
+Function *F = CGM.getIntrinsic(Intrinsic::amdgcn_global_load_lds);
+llvm::FunctionType *FTy = F->getFunctionType();
+for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
+ Value *ArgValue = EmitScalarOrConstFoldImmArg(ICEArguments, i, E);
+ llvm::Type *PTy = FTy->getParamType(i);
+ if (PTy != ArgValue->getType()) {
+if (auto *PtrTy = dyn_cast(PTy)) {
+ if (PtrTy->getAddressSpace() !=
+ ArgValue->getType()->getPointerAddressSpace()) {
+ArgValue = Builder.CreateAddrSpaceCast(
+ArgValue, llvm::PointerType::get(getLLVMContext(),
+ PtrTy->getAddressSpace()));
+ }
+}
shiltian wrote:
I think the check needs to be done in Sema, but do we have Sema for builtin?
https://github.com/llvm/llvm-project/pull/93064
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[clang] [llvm] [AMDGPU][Clang] Add check of size for __builtin_amdgcn_global_load_lds (PR #93064)
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/93064
None
>From 0ed9d89d65277d5af2bad72ba7834fc0bebb7236 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 22 May 2024 12:19:49 -0400
Subject: [PATCH] [AMDGPU][Clang] Add check of size for
__builtin_amdgcn_global_load_lds
---
clang/lib/CodeGen/CGBuiltin.cpp | 42 +++
.../builtins-amdgcn-gfx940-err.cl | 9
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 22 +-
3 files changed, 61 insertions(+), 12 deletions(-)
create mode 100644 clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940-err.cl
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index ba94bf89e4751..50c553daf74a0 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -19040,6 +19040,48 @@ Value *CodeGenFunction::EmitAMDGPUBuiltinExpr(unsigned
BuiltinID,
CGM.getIntrinsic(Intrinsic::amdgcn_s_sendmsg_rtn, {ResultType});
return Builder.CreateCall(F, {Arg});
}
+ case AMDGPU::BI__builtin_amdgcn_global_load_lds: {
+SmallVector Args;
+unsigned ICEArguments = 0;
+ASTContext::GetBuiltinTypeError Error;
+getContext().GetBuiltinType(BuiltinID, Error, );
+assert(Error == ASTContext::GE_None && "Should not codegen an error");
+Function *F = CGM.getIntrinsic(Intrinsic::amdgcn_global_load_lds);
+llvm::FunctionType *FTy = F->getFunctionType();
+for (unsigned i = 0, e = E->getNumArgs(); i != e; ++i) {
+ Value *ArgValue = EmitScalarOrConstFoldImmArg(ICEArguments, i, E);
+ llvm::Type *PTy = FTy->getParamType(i);
+ if (PTy != ArgValue->getType()) {
+if (auto *PtrTy = dyn_cast(PTy)) {
+ if (PtrTy->getAddressSpace() !=
+ ArgValue->getType()->getPointerAddressSpace()) {
+ArgValue = Builder.CreateAddrSpaceCast(
+ArgValue, llvm::PointerType::get(getLLVMContext(),
+ PtrTy->getAddressSpace()));
+ }
+}
+ArgValue = Builder.CreateBitCast(ArgValue, PTy);
+ }
+ Args.push_back(ArgValue);
+}
+constexpr const int SizeIdx = 2;
+ConstantInt *SizeVal = dyn_cast(Args[SizeIdx]);
+if (!SizeVal) {
+ CGM.Error(E->getExprLoc(), "size must be a constant");
+ return nullptr;
+}
+uint64_t Size = SizeVal->getZExtValue();
+switch (Size) {
+default:
+ CGM.Error(E->getExprLoc(), "size must be a 1/2/4");
+ return nullptr;
+case 1:
+case 2:
+case 4:
+ break;
+}
+return Builder.CreateCall(F, Args);
+ }
default:
return nullptr;
}
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940-err.cl
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940-err.cl
new file mode 100644
index 0..96df07ebf96b6
--- /dev/null
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940-err.cl
@@ -0,0 +1,9 @@
+// RUN: %clang_cc1 -cl-std=CL2.0 -O0 -triple amdgcn-unknown-unknown
-target-cpu gfx940 -S -verify -o - %s
+// REQUIRES: amdgpu-registered-target
+
+typedef unsigned int u32;
+
+void test_global_load_lds_unsupported_size(global u32* src, local u32 *dst,
u32 size) {
+ __builtin_amdgcn_global_load_lds(src, dst, size, /*offset=*/0, /*aux=*/0);
// expected-error{{size must be a constant}} expected-error{{cannot compile
this builtin function yet}}
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/5, /*offset=*/0,
/*aux=*/0); // expected-error {{size must be a 1/2/4}} expected-error{{cannot
compile this builtin function yet}}
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 0b774b724d0c0..82e3ecd268190 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2466,20 +2466,18 @@ def int_amdgcn_perm :
// GFX9 Intrinsics
//===--===//
-class AMDGPUGlobalLoadLDS :
- ClangBuiltin<"__builtin_amdgcn_global_load_lds">,
- Intrinsic <
-[],
-[LLVMQualPointerType<1>,// Base global pointer to load from
- LLVMQualPointerType<3>,// LDS base pointer to store to
- llvm_i32_ty, // Data byte size: 1/2/4 (/12/16 for
gfx950)
- llvm_i32_ty, // imm offset (applied to both global
and LDS address)
- llvm_i32_ty], // auxiliary data (imm, cachepolicy
(bit 0 = sc0,
+class AMDGPUGlobalLoadLDS : Intrinsic <
+ [],
+ [LLVMQualPointerType<1>, // Base global pointer to load from
+LLVMQualPointerType<3>, // LDS base pointer to store to
+llvm_i32_ty,// Data byte size: 1/2/4
+llvm_i32_ty,// imm offset (applied to both global
and LDS address)
+llvm_i32_ty], // auxiliary data (imm, cachepolicy
(bit 0 = sc0,
[clang] [llvm] [AMDGPU][Clang] Builtin for GLOBAL_LOAD_LDS on GFX940 (PR #92962)
https://github.com/shiltian closed https://github.com/llvm/llvm-project/pull/92962 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU][Clang] Builtin for GLOBAL_LOAD_LDS on GFX940 (PR #92962)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/92962 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU] Clang builtin for GLOBAL_LOAD_LDS on GFX940 (PR #92962)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/92962
>From 539c48a5a44392821547335bdfc3942cc03e1540 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 21 May 2024 18:26:25 -0400
Subject: [PATCH] [AMDGPU] Clang builtin for GLOBAL_LOAD_LDS on MI3XX
Fixes: SWDEV-459212
---
clang/include/clang/Basic/BuiltinsAMDGPU.def | 1 +
.../CodeGenOpenCL/builtins-amdgcn-gfx940.cl | 52 +++
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 31 +--
3 files changed, 67 insertions(+), 17 deletions(-)
create mode 100644 clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def
b/clang/include/clang/Basic/BuiltinsAMDGPU.def
index 3e21a2fe2ac6b..efa652eee9901 100644
--- a/clang/include/clang/Basic/BuiltinsAMDGPU.def
+++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def
@@ -240,6 +240,7 @@ TARGET_BUILTIN(__builtin_amdgcn_flat_atomic_fadd_v2bf16,
"V2sV2s*0V2s", "t", "at
TARGET_BUILTIN(__builtin_amdgcn_global_atomic_fadd_v2bf16, "V2sV2s*1V2s", "t",
"atomic-global-pk-add-bf16-inst")
TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_v2bf16, "V2sV2s*3V2s", "t",
"atomic-ds-pk-add-16-insts")
TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_v2f16, "V2hV2h*3V2h", "t",
"atomic-ds-pk-add-16-insts")
+TARGET_BUILTIN(__builtin_amdgcn_global_load_lds, "vv*1v*3UiiUi", "t",
"gfx940-insts")
//===--===//
// Deep learning builtins.
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
new file mode 100644
index 0..fc5649d8a41f7
--- /dev/null
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
@@ -0,0 +1,52 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -cl-std=CL2.0 -O0 -triple amdgcn-unknown-unknown
-target-cpu gfx940 -emit-llvm -o - %s | FileCheck %s
+// REQUIRES: amdgpu-registered-target
+
+typedef unsigned int u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+// CHECK-LABEL: @test_global_load_lds_u32(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[SRC_ADDR:%.*]] = alloca ptr addrspace(1), align 8,
addrspace(5)
+// CHECK-NEXT:[[DST_ADDR:%.*]] = alloca ptr addrspace(3), align 4,
addrspace(5)
+// CHECK-NEXT:store ptr addrspace(1) [[SRC:%.*]], ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:store ptr addrspace(3) [[DST:%.*]], ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr addrspace(1), ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load ptr addrspace(3), ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:call void @llvm.amdgcn.global.load.lds(ptr addrspace(1)
[[TMP0]], ptr addrspace(3) [[TMP1]], i32 4, i32 0, i32 0)
+// CHECK-NEXT:ret void
+//
+void test_global_load_lds_u32(global u32* src, local u32 *dst) {
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/4, /*offset=*/0,
/*aux=*/0);
+}
+
+// CHECK-LABEL: @test_global_load_lds_u16(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[SRC_ADDR:%.*]] = alloca ptr addrspace(1), align 8,
addrspace(5)
+// CHECK-NEXT:[[DST_ADDR:%.*]] = alloca ptr addrspace(3), align 4,
addrspace(5)
+// CHECK-NEXT:store ptr addrspace(1) [[SRC:%.*]], ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:store ptr addrspace(3) [[DST:%.*]], ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr addrspace(1), ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load ptr addrspace(3), ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:call void @llvm.amdgcn.global.load.lds(ptr addrspace(1)
[[TMP0]], ptr addrspace(3) [[TMP1]], i32 2, i32 0, i32 0)
+// CHECK-NEXT:ret void
+//
+void test_global_load_lds_u16(global u16* src, local u16 *dst) {
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/2, /*offset=*/0,
/*aux=*/0);
+}
+
+// CHECK-LABEL: @test_global_load_lds_u8(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[SRC_ADDR:%.*]] = alloca ptr addrspace(1), align 8,
addrspace(5)
+// CHECK-NEXT:[[DST_ADDR:%.*]] = alloca ptr addrspace(3), align 4,
addrspace(5)
+// CHECK-NEXT:store ptr addrspace(1) [[SRC:%.*]], ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:store ptr addrspace(3) [[DST:%.*]], ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr addrspace(1), ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load ptr addrspace(3), ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:call void @llvm.amdgcn.global.load.lds(ptr addrspace(1)
[[TMP0]], ptr addrspace(3) [[TMP1]], i32 1, i32 0, i32 0)
+// CHECK-NEXT:ret void
+//
+void test_global_load_lds_u8(global u8* src, local u8 *dst) {
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/1, /*offset=*/0,
/*aux=*/0);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
[clang] [llvm] [AMDGPU] Clang builtin for GLOBAL_LOAD_LDS on GFX940 (PR #92962)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/92962
>From a9e9fa27022738b6f7b8c5c2cbba0fb9900cd993 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 21 May 2024 18:25:38 -0400
Subject: [PATCH] [AMDGPU] Clang builtin for GLOBAL_LOAD_LDS on MI3XX
Fixes: SWDEV-459212
---
clang/include/clang/Basic/BuiltinsAMDGPU.def | 1 +
.../CodeGenOpenCL/builtins-amdgcn-gfx940.cl | 52 +++
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 31 +--
3 files changed, 67 insertions(+), 17 deletions(-)
create mode 100644 clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def
b/clang/include/clang/Basic/BuiltinsAMDGPU.def
index 3e21a2fe2ac6b..efa652eee9901 100644
--- a/clang/include/clang/Basic/BuiltinsAMDGPU.def
+++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def
@@ -240,6 +240,7 @@ TARGET_BUILTIN(__builtin_amdgcn_flat_atomic_fadd_v2bf16,
"V2sV2s*0V2s", "t", "at
TARGET_BUILTIN(__builtin_amdgcn_global_atomic_fadd_v2bf16, "V2sV2s*1V2s", "t",
"atomic-global-pk-add-bf16-inst")
TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_v2bf16, "V2sV2s*3V2s", "t",
"atomic-ds-pk-add-16-insts")
TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_v2f16, "V2hV2h*3V2h", "t",
"atomic-ds-pk-add-16-insts")
+TARGET_BUILTIN(__builtin_amdgcn_global_load_lds, "vv*1v*3UiiUi", "t",
"gfx940-insts")
//===--===//
// Deep learning builtins.
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
new file mode 100644
index 0..fc5649d8a41f7
--- /dev/null
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
@@ -0,0 +1,52 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -cl-std=CL2.0 -O0 -triple amdgcn-unknown-unknown
-target-cpu gfx940 -emit-llvm -o - %s | FileCheck %s
+// REQUIRES: amdgpu-registered-target
+
+typedef unsigned int u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+// CHECK-LABEL: @test_global_load_lds_u32(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[SRC_ADDR:%.*]] = alloca ptr addrspace(1), align 8,
addrspace(5)
+// CHECK-NEXT:[[DST_ADDR:%.*]] = alloca ptr addrspace(3), align 4,
addrspace(5)
+// CHECK-NEXT:store ptr addrspace(1) [[SRC:%.*]], ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:store ptr addrspace(3) [[DST:%.*]], ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr addrspace(1), ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load ptr addrspace(3), ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:call void @llvm.amdgcn.global.load.lds(ptr addrspace(1)
[[TMP0]], ptr addrspace(3) [[TMP1]], i32 4, i32 0, i32 0)
+// CHECK-NEXT:ret void
+//
+void test_global_load_lds_u32(global u32* src, local u32 *dst) {
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/4, /*offset=*/0,
/*aux=*/0);
+}
+
+// CHECK-LABEL: @test_global_load_lds_u16(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[SRC_ADDR:%.*]] = alloca ptr addrspace(1), align 8,
addrspace(5)
+// CHECK-NEXT:[[DST_ADDR:%.*]] = alloca ptr addrspace(3), align 4,
addrspace(5)
+// CHECK-NEXT:store ptr addrspace(1) [[SRC:%.*]], ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:store ptr addrspace(3) [[DST:%.*]], ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr addrspace(1), ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load ptr addrspace(3), ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:call void @llvm.amdgcn.global.load.lds(ptr addrspace(1)
[[TMP0]], ptr addrspace(3) [[TMP1]], i32 2, i32 0, i32 0)
+// CHECK-NEXT:ret void
+//
+void test_global_load_lds_u16(global u16* src, local u16 *dst) {
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/2, /*offset=*/0,
/*aux=*/0);
+}
+
+// CHECK-LABEL: @test_global_load_lds_u8(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[SRC_ADDR:%.*]] = alloca ptr addrspace(1), align 8,
addrspace(5)
+// CHECK-NEXT:[[DST_ADDR:%.*]] = alloca ptr addrspace(3), align 4,
addrspace(5)
+// CHECK-NEXT:store ptr addrspace(1) [[SRC:%.*]], ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:store ptr addrspace(3) [[DST:%.*]], ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr addrspace(1), ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load ptr addrspace(3), ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:call void @llvm.amdgcn.global.load.lds(ptr addrspace(1)
[[TMP0]], ptr addrspace(3) [[TMP1]], i32 1, i32 0, i32 0)
+// CHECK-NEXT:ret void
+//
+void test_global_load_lds_u8(global u8* src, local u8 *dst) {
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/1, /*offset=*/0,
/*aux=*/0);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
[clang] [llvm] [AMDGPU] Clang builtin for GLOBAL_LOAD_LDS on GFX940 (PR #92962)
@@ -2466,23 +2466,24 @@ def int_amdgcn_perm : // GFX9 Intrinsics //===--===// -class AMDGPUGlobalLoadLDS : Intrinsic < - [], - [LLVMQualPointerType<1>, // Base global pointer to load from - LLVMQualPointerType<3>, // LDS base pointer to store to - llvm_i32_ty,// Data byte size: 1/2/4 - llvm_i32_ty,// imm offset (applied to both global and LDS address) - llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc/sc0, - // bit 1 = slc/sc1, - // bit 2 = dlc on gfx10/gfx11)) - // bit 4 = scc/nt on gfx90a+)) - // gfx12+: - // cachepolicy (bits [0-2] = th, - // bits [3-4] = scope) - // swizzled buffer (bit 6 = swz), - [IntrWillReturn, NoCapture>, NoCapture>, - ImmArg>, ImmArg>, ImmArg>, IntrNoCallback, IntrNoFree], - "", [SDNPMemOperand]>; +class AMDGPUGlobalLoadLDS : + ClangBuiltin<"__builtin_amdgcn_global_load_lds">, + Intrinsic < +[], +[LLVMQualPointerType<1>,// Base global pointer to load from + LLVMQualPointerType<3>,// LDS base pointer to store to + llvm_i32_ty, // Data byte size: 1/2/4 (/12/16 for gfx950) + llvm_i32_ty, // imm offset (applied to both global and LDS address) + llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc/sc0, shiltian wrote: My bad. Forgot to remove all of them. https://github.com/llvm/llvm-project/pull/92962 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU] Clang builtin for GLOBAL_LOAD_LDS on GFX940 (PR #92962)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/92962
>From 741d71e456825c156d4a34020c6f7d8f28e11a1d Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 21 May 2024 16:57:22 -0400
Subject: [PATCH] [AMDGPU] Clang builtin for GLOBAL_LOAD_LDS on MI3XX
Fixes: SWDEV-459212
---
clang/include/clang/Basic/BuiltinsAMDGPU.def | 1 +
.../CodeGenOpenCL/builtins-amdgcn-gfx940.cl | 52 +++
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 31 +--
3 files changed, 67 insertions(+), 17 deletions(-)
create mode 100644 clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def
b/clang/include/clang/Basic/BuiltinsAMDGPU.def
index 3e21a2fe2ac6b..efa652eee9901 100644
--- a/clang/include/clang/Basic/BuiltinsAMDGPU.def
+++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def
@@ -240,6 +240,7 @@ TARGET_BUILTIN(__builtin_amdgcn_flat_atomic_fadd_v2bf16,
"V2sV2s*0V2s", "t", "at
TARGET_BUILTIN(__builtin_amdgcn_global_atomic_fadd_v2bf16, "V2sV2s*1V2s", "t",
"atomic-global-pk-add-bf16-inst")
TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_v2bf16, "V2sV2s*3V2s", "t",
"atomic-ds-pk-add-16-insts")
TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_v2f16, "V2hV2h*3V2h", "t",
"atomic-ds-pk-add-16-insts")
+TARGET_BUILTIN(__builtin_amdgcn_global_load_lds, "vv*1v*3UiiUi", "t",
"gfx940-insts")
//===--===//
// Deep learning builtins.
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
new file mode 100644
index 0..fc5649d8a41f7
--- /dev/null
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
@@ -0,0 +1,52 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -cl-std=CL2.0 -O0 -triple amdgcn-unknown-unknown
-target-cpu gfx940 -emit-llvm -o - %s | FileCheck %s
+// REQUIRES: amdgpu-registered-target
+
+typedef unsigned int u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+// CHECK-LABEL: @test_global_load_lds_u32(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[SRC_ADDR:%.*]] = alloca ptr addrspace(1), align 8,
addrspace(5)
+// CHECK-NEXT:[[DST_ADDR:%.*]] = alloca ptr addrspace(3), align 4,
addrspace(5)
+// CHECK-NEXT:store ptr addrspace(1) [[SRC:%.*]], ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:store ptr addrspace(3) [[DST:%.*]], ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr addrspace(1), ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load ptr addrspace(3), ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:call void @llvm.amdgcn.global.load.lds(ptr addrspace(1)
[[TMP0]], ptr addrspace(3) [[TMP1]], i32 4, i32 0, i32 0)
+// CHECK-NEXT:ret void
+//
+void test_global_load_lds_u32(global u32* src, local u32 *dst) {
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/4, /*offset=*/0,
/*aux=*/0);
+}
+
+// CHECK-LABEL: @test_global_load_lds_u16(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[SRC_ADDR:%.*]] = alloca ptr addrspace(1), align 8,
addrspace(5)
+// CHECK-NEXT:[[DST_ADDR:%.*]] = alloca ptr addrspace(3), align 4,
addrspace(5)
+// CHECK-NEXT:store ptr addrspace(1) [[SRC:%.*]], ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:store ptr addrspace(3) [[DST:%.*]], ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr addrspace(1), ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load ptr addrspace(3), ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:call void @llvm.amdgcn.global.load.lds(ptr addrspace(1)
[[TMP0]], ptr addrspace(3) [[TMP1]], i32 2, i32 0, i32 0)
+// CHECK-NEXT:ret void
+//
+void test_global_load_lds_u16(global u16* src, local u16 *dst) {
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/2, /*offset=*/0,
/*aux=*/0);
+}
+
+// CHECK-LABEL: @test_global_load_lds_u8(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[SRC_ADDR:%.*]] = alloca ptr addrspace(1), align 8,
addrspace(5)
+// CHECK-NEXT:[[DST_ADDR:%.*]] = alloca ptr addrspace(3), align 4,
addrspace(5)
+// CHECK-NEXT:store ptr addrspace(1) [[SRC:%.*]], ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:store ptr addrspace(3) [[DST:%.*]], ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr addrspace(1), ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load ptr addrspace(3), ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:call void @llvm.amdgcn.global.load.lds(ptr addrspace(1)
[[TMP0]], ptr addrspace(3) [[TMP1]], i32 1, i32 0, i32 0)
+// CHECK-NEXT:ret void
+//
+void test_global_load_lds_u8(global u8* src, local u8 *dst) {
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/1, /*offset=*/0,
/*aux=*/0);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
[clang] [llvm] [AMDGPU] Clang builtin for GLOBAL_LOAD_LDS on GFX940 (PR #92962)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/92962 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU] Clang builtin for GLOBAL_LOAD_LDS on MI3XX (PR #92962)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/92962
>From 05044c94265e51f81967fd0ed783b4ed163bc003 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 21 May 2024 16:41:23 -0400
Subject: [PATCH] [AMDGPU] Clang builtin for GLOBAL_LOAD_LDS on MI3XX
Fixes: SWDEV-459212
---
clang/include/clang/Basic/BuiltinsAMDGPU.def | 1 +
.../CodeGenOpenCL/builtins-amdgcn-gfx940.cl | 52 +++
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 35 +++--
3 files changed, 71 insertions(+), 17 deletions(-)
create mode 100644 clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def
b/clang/include/clang/Basic/BuiltinsAMDGPU.def
index 3e21a2fe2ac6b..efa652eee9901 100644
--- a/clang/include/clang/Basic/BuiltinsAMDGPU.def
+++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def
@@ -240,6 +240,7 @@ TARGET_BUILTIN(__builtin_amdgcn_flat_atomic_fadd_v2bf16,
"V2sV2s*0V2s", "t", "at
TARGET_BUILTIN(__builtin_amdgcn_global_atomic_fadd_v2bf16, "V2sV2s*1V2s", "t",
"atomic-global-pk-add-bf16-inst")
TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_v2bf16, "V2sV2s*3V2s", "t",
"atomic-ds-pk-add-16-insts")
TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_v2f16, "V2hV2h*3V2h", "t",
"atomic-ds-pk-add-16-insts")
+TARGET_BUILTIN(__builtin_amdgcn_global_load_lds, "vv*1v*3UiiUi", "t",
"gfx940-insts")
//===--===//
// Deep learning builtins.
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
new file mode 100644
index 0..fc5649d8a41f7
--- /dev/null
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-gfx940.cl
@@ -0,0 +1,52 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -cl-std=CL2.0 -O0 -triple amdgcn-unknown-unknown
-target-cpu gfx940 -emit-llvm -o - %s | FileCheck %s
+// REQUIRES: amdgpu-registered-target
+
+typedef unsigned int u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+// CHECK-LABEL: @test_global_load_lds_u32(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[SRC_ADDR:%.*]] = alloca ptr addrspace(1), align 8,
addrspace(5)
+// CHECK-NEXT:[[DST_ADDR:%.*]] = alloca ptr addrspace(3), align 4,
addrspace(5)
+// CHECK-NEXT:store ptr addrspace(1) [[SRC:%.*]], ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:store ptr addrspace(3) [[DST:%.*]], ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr addrspace(1), ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load ptr addrspace(3), ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:call void @llvm.amdgcn.global.load.lds(ptr addrspace(1)
[[TMP0]], ptr addrspace(3) [[TMP1]], i32 4, i32 0, i32 0)
+// CHECK-NEXT:ret void
+//
+void test_global_load_lds_u32(global u32* src, local u32 *dst) {
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/4, /*offset=*/0,
/*aux=*/0);
+}
+
+// CHECK-LABEL: @test_global_load_lds_u16(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[SRC_ADDR:%.*]] = alloca ptr addrspace(1), align 8,
addrspace(5)
+// CHECK-NEXT:[[DST_ADDR:%.*]] = alloca ptr addrspace(3), align 4,
addrspace(5)
+// CHECK-NEXT:store ptr addrspace(1) [[SRC:%.*]], ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:store ptr addrspace(3) [[DST:%.*]], ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr addrspace(1), ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load ptr addrspace(3), ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:call void @llvm.amdgcn.global.load.lds(ptr addrspace(1)
[[TMP0]], ptr addrspace(3) [[TMP1]], i32 2, i32 0, i32 0)
+// CHECK-NEXT:ret void
+//
+void test_global_load_lds_u16(global u16* src, local u16 *dst) {
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/2, /*offset=*/0,
/*aux=*/0);
+}
+
+// CHECK-LABEL: @test_global_load_lds_u8(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[SRC_ADDR:%.*]] = alloca ptr addrspace(1), align 8,
addrspace(5)
+// CHECK-NEXT:[[DST_ADDR:%.*]] = alloca ptr addrspace(3), align 4,
addrspace(5)
+// CHECK-NEXT:store ptr addrspace(1) [[SRC:%.*]], ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:store ptr addrspace(3) [[DST:%.*]], ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:[[TMP0:%.*]] = load ptr addrspace(1), ptr addrspace(5)
[[SRC_ADDR]], align 8
+// CHECK-NEXT:[[TMP1:%.*]] = load ptr addrspace(3), ptr addrspace(5)
[[DST_ADDR]], align 4
+// CHECK-NEXT:call void @llvm.amdgcn.global.load.lds(ptr addrspace(1)
[[TMP0]], ptr addrspace(3) [[TMP1]], i32 1, i32 0, i32 0)
+// CHECK-NEXT:ret void
+//
+void test_global_load_lds_u8(global u8* src, local u8 *dst) {
+ __builtin_amdgcn_global_load_lds(src, dst, /*size=*/1, /*offset=*/0,
/*aux=*/0);
+}
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
[clang] [llvm] [AMDGPU] Clang builtin for GLOBAL_LOAD_LDS on MI3XX (PR #92962)
https://github.com/shiltian created https://github.com/llvm/llvm-project/pull/92962 Fixes: SWDEV-459212 >From 5c342cbb389d32468695a925a6db3b42b09b15c4 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Tue, 21 May 2024 16:40:41 -0400 Subject: [PATCH] [AMDGPU] Clang builtin for GLOBAL_LOAD_LDS on MI3XX Fixes: SWDEV-459212 --- clang/include/clang/Basic/BuiltinsAMDGPU.def | 1 + llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 35 ++-- 2 files changed, 19 insertions(+), 17 deletions(-) diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def b/clang/include/clang/Basic/BuiltinsAMDGPU.def index 3e21a2fe2ac6b..efa652eee9901 100644 --- a/clang/include/clang/Basic/BuiltinsAMDGPU.def +++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def @@ -240,6 +240,7 @@ TARGET_BUILTIN(__builtin_amdgcn_flat_atomic_fadd_v2bf16, "V2sV2s*0V2s", "t", "at TARGET_BUILTIN(__builtin_amdgcn_global_atomic_fadd_v2bf16, "V2sV2s*1V2s", "t", "atomic-global-pk-add-bf16-inst") TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_v2bf16, "V2sV2s*3V2s", "t", "atomic-ds-pk-add-16-insts") TARGET_BUILTIN(__builtin_amdgcn_ds_atomic_fadd_v2f16, "V2hV2h*3V2h", "t", "atomic-ds-pk-add-16-insts") +TARGET_BUILTIN(__builtin_amdgcn_global_load_lds, "vv*1v*3UiiUi", "t", "gfx940-insts") //===--===// // Deep learning builtins. diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index be8048ca2459c..c6912196de5d7 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -2466,23 +2466,24 @@ def int_amdgcn_perm : // GFX9 Intrinsics //===--===// -class AMDGPUGlobalLoadLDS : Intrinsic < - [], - [LLVMQualPointerType<1>, // Base global pointer to load from - LLVMQualPointerType<3>, // LDS base pointer to store to - llvm_i32_ty,// Data byte size: 1/2/4 - llvm_i32_ty,// imm offset (applied to both global and LDS address) - llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc/sc0, - // bit 1 = slc/sc1, - // bit 2 = dlc on gfx10/gfx11)) - // bit 4 = scc/nt on gfx90a+)) - // gfx12+: - // cachepolicy (bits [0-2] = th, - // bits [3-4] = scope) - // swizzled buffer (bit 6 = swz), - [IntrWillReturn, NoCapture>, NoCapture>, - ImmArg>, ImmArg>, ImmArg>, IntrNoCallback, IntrNoFree], - "", [SDNPMemOperand]>; +class AMDGPUGlobalLoadLDS : + ClangBuiltin<"__builtin_amdgcn_global_load_lds">, + Intrinsic < +[], +[LLVMQualPointerType<1>,// Base global pointer to load from + LLVMQualPointerType<3>,// LDS base pointer to store to + llvm_i32_ty, // Data byte size: 1/2/4 (/12/16 for gfx950) + llvm_i32_ty, // imm offset (applied to both global and LDS address) + llvm_i32_ty], // auxiliary data (imm, cachepolicy (bit 0 = glc/sc0, +// bit 1 = slc/sc1, +// bit 4 = scc/nt on gfx90a+)) +// gfx12+: +// cachepolicy (bits [0-2] = th, +// bits [3-4] = scope) +// swizzled buffer (bit 6 = swz), +[IntrWillReturn, NoCapture>, NoCapture>, +ImmArg>, ImmArg>, ImmArg>, IntrNoCallback, IntrNoFree], +"", [SDNPMemOperand]>; def int_amdgcn_global_load_lds : AMDGPUGlobalLoadLDS; //===--===// ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][OpenMP] Fix multi arch compilation for -march option (PR #92290)
shiltian wrote: > > > > If `-march` is the wrong option then let's start deprecating it and > > > > remove it altogether in the next llvm release. But, as long as it is > > > > here, it should be equivalent to `--offload-arch`. > > > > > > > > > Honestly not a bad idea. I could make a patch warning users to use > > > `--offload-arch` instead for now. > > > > > > Sure, let's do that. But, let this land as long as this option is supported. > > That doesn't track, LLVM has never supported `-march` to support multiple > options and there's no reason to add it now when we're talking about > deprecating it. +1 https://github.com/llvm/llvm-project/pull/92290 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [Clang][OpenMP] Fix runtime problem when explicit map both pointer and pointee (PR #92210)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/92210 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang] Fix a crash introduced in PR#88666 (PR #89567)
https://github.com/shiltian closed https://github.com/llvm/llvm-project/pull/89567 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang] Fix a crash introduced in PR#88666 (PR #89567)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/89567
>From 041574d22c2debb5299926b58aed529919905902 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Mon, 22 Apr 2024 01:09:47 -0400
Subject: [PATCH] [Clang] Fix a crash introduced in PR#88666
The unroll value can be a template variable such that we need to check it before
we verify if it is constant value.
---
clang/lib/Sema/SemaStmtAttr.cpp | 2 +-
clang/test/Sema/unroll-template-value-crash.cpp | 10 ++
2 files changed, 11 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Sema/unroll-template-value-crash.cpp
diff --git a/clang/lib/Sema/SemaStmtAttr.cpp b/clang/lib/Sema/SemaStmtAttr.cpp
index 7cd494b42250d4..9d44c22c8ddcc3 100644
--- a/clang/lib/Sema/SemaStmtAttr.cpp
+++ b/clang/lib/Sema/SemaStmtAttr.cpp
@@ -109,7 +109,7 @@ static Attr *handleLoopHintAttr(Sema , Stmt *St, const
ParsedAttr ,
SetHints(LoopHintAttr::Unroll, LoopHintAttr::Disable);
} else if (PragmaName == "unroll") {
// #pragma unroll N
-if (ValueExpr) {
+if (ValueExpr && !ValueExpr->isValueDependent()) {
llvm::APSInt ValueAPS;
ExprResult R = S.VerifyIntegerConstantExpression(ValueExpr, );
assert(!R.isInvalid() && "unroll count value must be a valid value, it's
"
diff --git a/clang/test/Sema/unroll-template-value-crash.cpp
b/clang/test/Sema/unroll-template-value-crash.cpp
new file mode 100644
index 00..d8953c4845c265
--- /dev/null
+++ b/clang/test/Sema/unroll-template-value-crash.cpp
@@ -0,0 +1,10 @@
+// RUN: %clang_cc1 -x c++ -verify %s
+// expected-no-diagnostics
+
+template void foo() {
+ #pragma unroll Unroll
+ for (int i = 0; i < Unroll; ++i);
+
+ #pragma GCC unroll Unroll
+ for (int i = 0; i < Unroll; ++i);
+}
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[clang] [Clang] Fix a crash introduced in PR#88666 (PR #89567)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/89567
>From 3503f2bfd28af5be8e87835c47207d770659db3c Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Mon, 22 Apr 2024 00:06:31 -0400
Subject: [PATCH] [Clang] Fix a crash introduced in PR#88666
The unroll value can be a template variable such that we need to check it before
we verify if it is constant value.
---
clang/lib/Sema/SemaStmtAttr.cpp | 2 +-
clang/test/Sema/unroll-template-value-crash.cpp | 7 +++
2 files changed, 8 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Sema/unroll-template-value-crash.cpp
diff --git a/clang/lib/Sema/SemaStmtAttr.cpp b/clang/lib/Sema/SemaStmtAttr.cpp
index 7cd494b42250d4..9d44c22c8ddcc3 100644
--- a/clang/lib/Sema/SemaStmtAttr.cpp
+++ b/clang/lib/Sema/SemaStmtAttr.cpp
@@ -109,7 +109,7 @@ static Attr *handleLoopHintAttr(Sema , Stmt *St, const
ParsedAttr ,
SetHints(LoopHintAttr::Unroll, LoopHintAttr::Disable);
} else if (PragmaName == "unroll") {
// #pragma unroll N
-if (ValueExpr) {
+if (ValueExpr && !ValueExpr->isValueDependent()) {
llvm::APSInt ValueAPS;
ExprResult R = S.VerifyIntegerConstantExpression(ValueExpr, );
assert(!R.isInvalid() && "unroll count value must be a valid value, it's
"
diff --git a/clang/test/Sema/unroll-template-value-crash.cpp
b/clang/test/Sema/unroll-template-value-crash.cpp
new file mode 100644
index 00..4aea46ca727a8d
--- /dev/null
+++ b/clang/test/Sema/unroll-template-value-crash.cpp
@@ -0,0 +1,7 @@
+// RUN: %clang_cc1 -x c++ -verify %s
+// expected-no-diagnostics
+
+template void foo() {
+ #pragma unroll Unroll
+ for (int i = 0; i < Unroll; ++i);
+}
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[clang] [Clang] Allow the value of unroll count to be zero in `#pragma GCC unroll` and `#pragma unroll` (PR #88666)
shiltian wrote: @alexfh @ronlieb @Endilll fix in https://github.com/llvm/llvm-project/pull/89567. https://github.com/llvm/llvm-project/pull/88666 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang] Fix a crash introduced in PR#88666 (PR #89567)
https://github.com/shiltian created
https://github.com/llvm/llvm-project/pull/89567
The unroll value can be a template variable such that we need to check it before
we verify if it is constant value.
>From 8f14bcc2ea3d4badb63b953dc23b27b49b0a6521 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Sun, 21 Apr 2024 23:41:35 -0400
Subject: [PATCH] [Clang] Fix a crash introduced in PR#88666
The unroll value can be a template variable such that we need to check it before
we verify if it is constant value.
---
clang/lib/Sema/SemaStmtAttr.cpp | 2 +-
clang/test/Sema/unroll-template-value-crash.cpp | 7 +++
2 files changed, 8 insertions(+), 1 deletion(-)
create mode 100644 clang/test/Sema/unroll-template-value-crash.cpp
diff --git a/clang/lib/Sema/SemaStmtAttr.cpp b/clang/lib/Sema/SemaStmtAttr.cpp
index 7cd494b42250d4..9d44c22c8ddcc3 100644
--- a/clang/lib/Sema/SemaStmtAttr.cpp
+++ b/clang/lib/Sema/SemaStmtAttr.cpp
@@ -109,7 +109,7 @@ static Attr *handleLoopHintAttr(Sema , Stmt *St, const
ParsedAttr ,
SetHints(LoopHintAttr::Unroll, LoopHintAttr::Disable);
} else if (PragmaName == "unroll") {
// #pragma unroll N
-if (ValueExpr) {
+if (ValueExpr && !ValueExpr->isValueDependent()) {
llvm::APSInt ValueAPS;
ExprResult R = S.VerifyIntegerConstantExpression(ValueExpr, );
assert(!R.isInvalid() && "unroll count value must be a valid value, it's
"
diff --git a/clang/test/Sema/unroll-template-value-crash.cpp
b/clang/test/Sema/unroll-template-value-crash.cpp
new file mode 100644
index 00..bb200fc3667c8f
--- /dev/null
+++ b/clang/test/Sema/unroll-template-value-crash.cpp
@@ -0,0 +1,7 @@
+// RUN: %clang_cc1 -x c++ -emit-llvm -S -verify %s
+// expected-no-diagnostics
+
+template void foo() {
+ #pragma unroll Unroll
+ for (int i = 0; i < Unroll; ++i);
+}
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[clang] [llvm] [Offload][NFC] Remove `omp_` prefix from offloading entries (PR #88071)
shiltian wrote: How about `llvm.offload`? This might need broader discussion but I'm fine either way. https://github.com/llvm/llvm-project/pull/88071 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [openmp] [Libomp] Place generated OpenMP headers into build resource directory (PR #88007)
https://github.com/shiltian approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/88007 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [openmp] [Libomp] Place generated OpenMP headers into build resource directory (PR #88007)
@@ -16,4 +16,12 @@ typedef unsigned __INTPTR_TYPE__ uintptr_t; #error Every target should have __INTPTR_TYPE__ #endif +#ifdef __INTPTR_MAX__ +#define INTPTR_MAX__INTPTR_MAX__ +#endif + +#ifdef __UINTPTR_MAX__ +#define UINTPTR_MAX __UINTPTR_MAX__ +#endif + shiltian wrote: This header is useful when invoking front end directly such that we don't need to pass things like `-internal-isystem` which usually are added by compiler driver. https://github.com/llvm/llvm-project/pull/88007 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [openmp] [Libomp] Place generated OpenMP headers into build resource directory (PR #88007)
@@ -10,12 +10,19 @@
include(ExtendPath)
+# The generated headers will be placed in clang's resource directory if
present.
+if(${OPENMP_STANDALONE_BUILD})
+ set(LIBOMP_HEADERS_INTDIR ${CMAKE_CURRENT_BINARY_DIR})
+else()
+ set(LIBOMP_HEADERS_INTDIR ${LLVM_BINARY_DIR}/${LIBOMP_HEADERS_INSTALL_PATH})
shiltian wrote:
oh "intermediate"
https://github.com/llvm/llvm-project/pull/88007
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[clang] [openmp] [Libomp] Place generated OpenMP headers into build resource directory (PR #88007)
@@ -10,12 +10,19 @@
include(ExtendPath)
+# The generated headers will be placed in clang's resource directory if
present.
+if(${OPENMP_STANDALONE_BUILD})
+ set(LIBOMP_HEADERS_INTDIR ${CMAKE_CURRENT_BINARY_DIR})
+else()
+ set(LIBOMP_HEADERS_INTDIR ${LLVM_BINARY_DIR}/${LIBOMP_HEADERS_INSTALL_PATH})
shiltian wrote:
Is it `INSTDIR` or `INTDIR`? What does `INTDIR` mean?
https://github.com/llvm/llvm-project/pull/88007
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[clang] [llvm] [OpenMP] Add amdgpu-num-work-groups attribute to OpenMP kernels (PR #87695)
https://github.com/shiltian approved this pull request. LG https://github.com/llvm/llvm-project/pull/87695 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [OpenMP] Add amdgpu-num-work-groups attribute to OpenMP kernels (PR #87695)
@@ -4791,6 +4791,9 @@ void OpenMPIRBuilder::writeTeamsForKernel(const Triple
, Function ,
updateNVPTXMetadata(Kernel, "maxclusterrank", UB, true);
updateNVPTXMetadata(Kernel, "minctasm", LB, false);
}
+ if (T.isAMDGPU()) {
shiltian wrote:
```suggestion
if (T.isAMDGPU())
Kernel.addFnAttr("amdgpu-max-num-workgroups", llvm::utostr(LB) + ",1,1");
```
https://github.com/llvm/llvm-project/pull/87695
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[clang] [OpenMP] Allow dynamic `condition` selector in Metadirective (PR #86457)
shiltian wrote: I'm not familiar with that section of code. Maybe @jdoerfert could give you more insights. https://github.com/llvm/llvm-project/pull/86457 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] AMDGPU: Rename and add bf16 support for global_load_tr builtins (PR #86202)
shiltian wrote: > > > > Do you want to rename intrinsics as well? Because now intrinsic names > > > > do not match builtin names. > > > > > > > > > Do we have to match builtins with intrinsics? Renaming intrinsics here > > > means we will have to duplicate the intrinsics. > > > > > > Is that because of the mangling? > > Right. It was originally suggested to use a single instrinsic "load_lr". > > But eventually we use global_load_tr to indicate this is in global address > > space. If we want to rename intrinsics here, it should be > > global_load_tr_b64 and global_load_tr_b128. > > We should rename intrinsic if users can use intrinsics directly. I think > use-friendly is more important. I don't think intrinsics are meant for users. Builtins are the user-facing front. :-) https://github.com/llvm/llvm-project/pull/86202 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] AMDGPU: Rename and add bf16 support for global_load_tr builtins (PR #86202)
@@ -432,13 +432,15 @@ TARGET_BUILTIN(__builtin_amdgcn_s_wakeup_barrier, "vi", "n", "gfx12-insts") TARGET_BUILTIN(__builtin_amdgcn_s_barrier_leave, "b", "n", "gfx12-insts") TARGET_BUILTIN(__builtin_amdgcn_s_get_barrier_state, "Uii", "n", "gfx12-insts") -TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_v2i32, "V2iV2i*1", "nc", "gfx12-insts,wavefrontsize32") -TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_v8i16, "V8sV8s*1", "nc", "gfx12-insts,wavefrontsize32") -TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_v8f16, "V8hV8h*1", "nc", "gfx12-insts,wavefrontsize32") - -TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_i32, "ii*1", "nc", "gfx12-insts,wavefrontsize64") -TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_v4i16, "V4sV4s*1", "nc", "gfx12-insts,wavefrontsize64") -TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_v4f16, "V4hV4h*1", "nc", "gfx12-insts,wavefrontsize64") +TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b64_v2i32, "V2iV2i*1", "nc", "gfx12-insts,wavefrontsize32") +TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v8i16, "V8sV8s*1", "nc", "gfx12-insts,wavefrontsize32") +TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v8f16, "V8hV8h*1", "nc", "gfx12-insts,wavefrontsize32") +TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v8bf16, "V8yV8y*1", "nc", "gfx12-insts,wavefrontsize32") + +TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b64_i32, "ii*1", "nc", "gfx12-insts,wavefrontsize64") +TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4i16, "V4sV4s*1", "nc", "gfx12-insts,wavefrontsize64") +TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4f16, "V4hV4h*1", "nc", "gfx12-insts,wavefrontsize64") +TARGET_BUILTIN(__builtin_amdgcn_global_load_tr_b128_v4bf16, "V4yV4y*1", "nc", "gfx12-insts,wavefrontsize64") shiltian wrote: Do we still want to keep the old builtins to maintain compatibility, though I doubt there is any legacy code using them? https://github.com/llvm/llvm-project/pull/86202 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][OpenMP] throw compilation error instead of crash in Stmt::OMPScopeDirectiveClass case (#77535) (PR #84135)
@@ -0,0 +1,8 @@ +// RUN: %clang_cc1 -emit-obj -verify -fopenmp %s shiltian wrote: You can use `-emit-llvm` instead. https://github.com/llvm/llvm-project/pull/84135 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][OpenMP] throw compilation error instead of crash in Stmt::OMPScopeDirectiveClass case (#77535) (PR #84135)
@@ -0,0 +1,8 @@ +// RUN: %clang_cc1 -emit-obj -verify -fopenmp %s shiltian wrote: `emit-obj` is not needed https://github.com/llvm/llvm-project/pull/84135 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][OpenMP] throw compilation error instead of crash in Stmt::OMPScopeDirectiveClass case (#77535) (PR #84135)
https://github.com/shiltian approved this pull request. LG with one nit https://github.com/llvm/llvm-project/pull/84135 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][OpenMP] throw compilation error instead of crash in Stmt::OMPScopeDirectiveClass case (#77535) (PR #84135)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/84135 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU] Fix operand types for `V_DOT2_F32_BF16` (PR #82044)
https://github.com/shiltian closed https://github.com/llvm/llvm-project/pull/82044 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU] Fix operand types for `V_DOT2_F32_BF16` (PR #82044)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/82044
>From a769826f1ff424dab5377fff249bfdd1465633bb Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Mon, 19 Feb 2024 23:06:14 -0500
Subject: [PATCH] [AMDGPU] Fix operand types for `V_DOT2_F32_BF16`
---
.../builtins-amdgcn-dl-insts-gfx11.cl | 4 +-
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 4 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 2 +-
llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 2 +-
.../AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll | 14 ++---
llvm/test/MC/AMDGPU/bf16_imm.s| 63 +++
llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt | 63 +++
7 files changed, 139 insertions(+), 13 deletions(-)
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
index 7688dfa55a78e3..1ada16610d0b3a 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
@@ -15,8 +15,8 @@ typedef unsigned short __attribute__((ext_vector_type(2)))
ushort2;
// CHECK-NEXT: [[s2:%[0-9]+]] = bitcast <2 x i16> %v2ssB to <2 x bfloat>
// CHECK-NEXT: [[s3:%[0-9]+]] = bitcast i16 %sC to bfloat
// CHECK-NEXT: [[d:%[0-9]+]] = tail call bfloat
@llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> [[s1]], <2 x bfloat> [[s2]], bfloat
[[s3]])
-// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, float %fC, i1 false)
-// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, float %fC, i1 true)
+// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> [[s1]], <2 x
bfloat> [[s2]], float %fC, i1 false)
+// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> [[s1]], <2 x
bfloat> [[s2]], float %fC, i1 true)
// CHECK: call i32 @llvm.amdgcn.udot4(i32 %uiA, i32 %uiB, i32 %uiC, i1 false)
// CHECK: call i32 @llvm.amdgcn.udot4(i32 %uiA, i32 %uiB, i32 %uiC, i1 true)
// CHECK: call i32 @llvm.amdgcn.sudot4(i1 true, i32 %A, i1 false, i32 %B, i32
%C, i1 false)
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 6795fb7aa0edb8..0f29653f1f5bec 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2835,8 +2835,8 @@ def int_amdgcn_fdot2_f32_bf16 :
DefaultAttrsIntrinsic<
[llvm_float_ty], // %r
[
- llvm_v2i16_ty, // %a
- llvm_v2i16_ty, // %b
+ llvm_v2bf16_ty, // %a
+ llvm_v2bf16_ty, // %b
llvm_float_ty, // %c
llvm_i1_ty // %clamp
],
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 140c99ff304143..cd14c12a8a80c6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -2494,7 +2494,7 @@ def VOP_V2I16_I32_I32 : VOPProfile <[v2i16, i32, i32,
untyped]>;
def VOP_F16_V2F16_V2F16_F16 : VOPProfile <[f16, v2f16, v2f16, f16]>;
def VOP_BF16_V2BF16_V2BF16_BF16: VOPProfile <[bf16, v2bf16, v2bf16, bf16]>;
-def VOP_F32_V2I16_V2I16_F32 : VOPProfile <[f32, v2i16, v2i16, f32]>;
+def VOP_F32_V2BF16_V2BF16_F32 : VOPProfile <[f32, v2bf16, v2bf16, f32]>;
def VOP_F32_V2F16_V2F16_V2F16 : VOPProfile <[f32, v2f16, v2f16, v2f16]>;
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index 886858b5ab1ad3..74f451b6d4f7fe 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -396,7 +396,7 @@ defm V_DOT8_I32_I4 : VOP3PInst<"v_dot8_i32_i4",
} // End OtherPredicates = [HasDot1Insts]
def DOT2_BF16_Profile
- : VOP3P_Profile {
+ : VOP3P_Profile {
let HasSrc1Mods = 1;
}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
index 367ff57bae2fd6..e51b1d2da2e414 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s |
FileCheck %s --check-prefixes=GFX11
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs <
%s | FileCheck %s --check-prefixes=GFX11
-declare float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %a, <2 x i16> %b, float
%c, i1 %clamp)
+declare float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b,
float %c, i1 %clamp)
define amdgpu_kernel void @test_llvm_amdgcn_fdot2_f32_bf16_clamp(
; GFX11-LABEL: test_llvm_amdgcn_fdot2_f32_bf16_clamp:
@@ -25,10 +25,10 @@ define amdgpu_kernel void
@test_llvm_amdgcn_fdot2_f32_bf16_clamp(
ptr addrspace(1) %b,
ptr addrspace(1) %c) {
entry:
- %a.val = load <2 x i16>, ptr addrspace(1) %a
- %b.val = load <2 x i16>, ptr addrspace(1) %b
+ %a.val = load <2 x bfloat>, ptr addrspace(1) %a
+ %b.val = load <2 x bfloat>, ptr addrspace(1) %b
[clang] [llvm] [AMDGPU] Fix operand types for `V_DOT2_F32_BF16` (PR #82044)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/82044
>From c78fe7c5e3de222539d6ac324fedf55e0d01d321 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Mon, 19 Feb 2024 22:52:26 -0500
Subject: [PATCH] [AMDGPU] Fix operand types for `V_DOT2_F32_BF16`
---
.../builtins-amdgcn-dl-insts-gfx11.cl | 4 ++--
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 4 ++--
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 2 +-
llvm/lib/Target/AMDGPU/VOP3PInstructions.td| 2 +-
.../CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll | 14 +++---
llvm/test/MC/AMDGPU/bf16_imm.s | 9 +
llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt | 6 ++
7 files changed, 28 insertions(+), 13 deletions(-)
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
index 7688dfa55a78e3..1ada16610d0b3a 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
@@ -15,8 +15,8 @@ typedef unsigned short __attribute__((ext_vector_type(2)))
ushort2;
// CHECK-NEXT: [[s2:%[0-9]+]] = bitcast <2 x i16> %v2ssB to <2 x bfloat>
// CHECK-NEXT: [[s3:%[0-9]+]] = bitcast i16 %sC to bfloat
// CHECK-NEXT: [[d:%[0-9]+]] = tail call bfloat
@llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> [[s1]], <2 x bfloat> [[s2]], bfloat
[[s3]])
-// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, float %fC, i1 false)
-// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, float %fC, i1 true)
+// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> [[s1]], <2 x
bfloat> [[s2]], float %fC, i1 false)
+// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> [[s1]], <2 x
bfloat> [[s2]], float %fC, i1 true)
// CHECK: call i32 @llvm.amdgcn.udot4(i32 %uiA, i32 %uiB, i32 %uiC, i1 false)
// CHECK: call i32 @llvm.amdgcn.udot4(i32 %uiA, i32 %uiB, i32 %uiC, i1 true)
// CHECK: call i32 @llvm.amdgcn.sudot4(i1 true, i32 %A, i1 false, i32 %B, i32
%C, i1 false)
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 6795fb7aa0edb8..0f29653f1f5bec 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2835,8 +2835,8 @@ def int_amdgcn_fdot2_f32_bf16 :
DefaultAttrsIntrinsic<
[llvm_float_ty], // %r
[
- llvm_v2i16_ty, // %a
- llvm_v2i16_ty, // %b
+ llvm_v2bf16_ty, // %a
+ llvm_v2bf16_ty, // %b
llvm_float_ty, // %c
llvm_i1_ty // %clamp
],
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 140c99ff304143..cd14c12a8a80c6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -2494,7 +2494,7 @@ def VOP_V2I16_I32_I32 : VOPProfile <[v2i16, i32, i32,
untyped]>;
def VOP_F16_V2F16_V2F16_F16 : VOPProfile <[f16, v2f16, v2f16, f16]>;
def VOP_BF16_V2BF16_V2BF16_BF16: VOPProfile <[bf16, v2bf16, v2bf16, bf16]>;
-def VOP_F32_V2I16_V2I16_F32 : VOPProfile <[f32, v2i16, v2i16, f32]>;
+def VOP_F32_V2BF16_V2BF16_F32 : VOPProfile <[f32, v2bf16, v2bf16, f32]>;
def VOP_F32_V2F16_V2F16_V2F16 : VOPProfile <[f32, v2f16, v2f16, v2f16]>;
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index 886858b5ab1ad3..74f451b6d4f7fe 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -396,7 +396,7 @@ defm V_DOT8_I32_I4 : VOP3PInst<"v_dot8_i32_i4",
} // End OtherPredicates = [HasDot1Insts]
def DOT2_BF16_Profile
- : VOP3P_Profile {
+ : VOP3P_Profile {
let HasSrc1Mods = 1;
}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
index 367ff57bae2fd6..e51b1d2da2e414 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s |
FileCheck %s --check-prefixes=GFX11
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs <
%s | FileCheck %s --check-prefixes=GFX11
-declare float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %a, <2 x i16> %b, float
%c, i1 %clamp)
+declare float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b,
float %c, i1 %clamp)
define amdgpu_kernel void @test_llvm_amdgcn_fdot2_f32_bf16_clamp(
; GFX11-LABEL: test_llvm_amdgcn_fdot2_f32_bf16_clamp:
@@ -25,10 +25,10 @@ define amdgpu_kernel void
@test_llvm_amdgcn_fdot2_f32_bf16_clamp(
ptr addrspace(1) %b,
ptr addrspace(1) %c) {
entry:
- %a.val = load <2 x i16>, ptr addrspace(1) %a
- %b.val = load <2 x i16>, ptr addrspace(1) %b
+ %a.val = load <2 x bfloat>, ptr addrspace(1) %a
+ %b.val = load <2 x bfloat>,
[clang] [llvm] [AMDGPU] Fix operand types for `V_DOT2_F32_BF16` (PR #82044)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/82044
>From b964fee8219e655d3c7df34cd01e5650ae357f6b Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 16 Feb 2024 17:49:23 -0500
Subject: [PATCH] [AMDGPU] Fix operand types for `V_DOT2_F32_BF16`
---
.../builtins-amdgcn-dl-insts-gfx11.cl | 4 ++--
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 4 ++--
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 2 +-
llvm/lib/Target/AMDGPU/VOP3PInstructions.td| 2 +-
.../CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll | 14 +++---
llvm/test/MC/AMDGPU/bf16_imm.s | 9 +
llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt | 11 ++-
7 files changed, 32 insertions(+), 14 deletions(-)
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
index 7688dfa55a78e3..1ada16610d0b3a 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
@@ -15,8 +15,8 @@ typedef unsigned short __attribute__((ext_vector_type(2)))
ushort2;
// CHECK-NEXT: [[s2:%[0-9]+]] = bitcast <2 x i16> %v2ssB to <2 x bfloat>
// CHECK-NEXT: [[s3:%[0-9]+]] = bitcast i16 %sC to bfloat
// CHECK-NEXT: [[d:%[0-9]+]] = tail call bfloat
@llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> [[s1]], <2 x bfloat> [[s2]], bfloat
[[s3]])
-// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, float %fC, i1 false)
-// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, float %fC, i1 true)
+// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> [[s1]], <2 x
bfloat> [[s2]], float %fC, i1 false)
+// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> [[s1]], <2 x
bfloat> [[s2]], float %fC, i1 true)
// CHECK: call i32 @llvm.amdgcn.udot4(i32 %uiA, i32 %uiB, i32 %uiC, i1 false)
// CHECK: call i32 @llvm.amdgcn.udot4(i32 %uiA, i32 %uiB, i32 %uiC, i1 true)
// CHECK: call i32 @llvm.amdgcn.sudot4(i1 true, i32 %A, i1 false, i32 %B, i32
%C, i1 false)
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 6795fb7aa0edb8..0f29653f1f5bec 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2835,8 +2835,8 @@ def int_amdgcn_fdot2_f32_bf16 :
DefaultAttrsIntrinsic<
[llvm_float_ty], // %r
[
- llvm_v2i16_ty, // %a
- llvm_v2i16_ty, // %b
+ llvm_v2bf16_ty, // %a
+ llvm_v2bf16_ty, // %b
llvm_float_ty, // %c
llvm_i1_ty // %clamp
],
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
index 140c99ff304143..cd14c12a8a80c6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -2494,7 +2494,7 @@ def VOP_V2I16_I32_I32 : VOPProfile <[v2i16, i32, i32,
untyped]>;
def VOP_F16_V2F16_V2F16_F16 : VOPProfile <[f16, v2f16, v2f16, f16]>;
def VOP_BF16_V2BF16_V2BF16_BF16: VOPProfile <[bf16, v2bf16, v2bf16, bf16]>;
-def VOP_F32_V2I16_V2I16_F32 : VOPProfile <[f32, v2i16, v2i16, f32]>;
+def VOP_F32_V2BF16_V2BF16_F32 : VOPProfile <[f32, v2bf16, v2bf16, f32]>;
def VOP_F32_V2F16_V2F16_V2F16 : VOPProfile <[f32, v2f16, v2f16, v2f16]>;
diff --git a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
index 886858b5ab1ad3..74f451b6d4f7fe 100644
--- a/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3PInstructions.td
@@ -396,7 +396,7 @@ defm V_DOT8_I32_I4 : VOP3PInst<"v_dot8_i32_i4",
} // End OtherPredicates = [HasDot1Insts]
def DOT2_BF16_Profile
- : VOP3P_Profile {
+ : VOP3P_Profile {
let HasSrc1Mods = 1;
}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
index 367ff57bae2fd6..e51b1d2da2e414 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.f32.bf16.ll
@@ -2,7 +2,7 @@
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s |
FileCheck %s --check-prefixes=GFX11
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs <
%s | FileCheck %s --check-prefixes=GFX11
-declare float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %a, <2 x i16> %b, float
%c, i1 %clamp)
+declare float @llvm.amdgcn.fdot2.f32.bf16(<2 x bfloat> %a, <2 x bfloat> %b,
float %c, i1 %clamp)
define amdgpu_kernel void @test_llvm_amdgcn_fdot2_f32_bf16_clamp(
; GFX11-LABEL: test_llvm_amdgcn_fdot2_f32_bf16_clamp:
@@ -25,10 +25,10 @@ define amdgpu_kernel void
@test_llvm_amdgcn_fdot2_f32_bf16_clamp(
ptr addrspace(1) %b,
ptr addrspace(1) %c) {
entry:
- %a.val = load <2 x i16>, ptr addrspace(1) %a
- %b.val = load <2 x i16>, ptr addrspace(1) %b
+ %a.val = load <2 x bfloat>, ptr addrspace(1) %a
+ %b.val = load <2 x
[clang] [llvm] [AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian closed https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/80908
>From 5b66bb22a91690078a955cea6c02b6b746b6502b Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 16 Feb 2024 15:08:35 -0500
Subject: [PATCH] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat
Currently it looks like we generally use `i16` to represent `bf16` in those
tablegen
files. I'm not sure of the reason behind it. My wild guess is the type `bf16`
was
not available when we enabled the support. This patch is trying to use `bf16`
directly in those tablegen files, aiming at fixing #79369. Of course for #79369
a workaround can be to treat all `INT16` variants as `BFloat` in
`getOpFltSemantics`,
but it doesn't look good IMHO.
Since I'm fairly new to AMDGPU backend, I'd appreciate it if you can point out
where I don't understand correctly.
---
.../builtins-amdgcn-dl-insts-gfx11.cl | 5 +-
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 8 +-
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 92 +++
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 57
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 2 +
.../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 39
llvm/lib/Target/AMDGPU/SIDefines.h| 7 ++
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp| 15 +++
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 16 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 21 -
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp| 54 +++
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 16
llvm/lib/Target/AMDGPU/VOP3Instructions.td| 2 +-
.../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 39
llvm/test/MC/AMDGPU/bf16_imm.s| 14 +++
llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt | 16
16 files changed, 369 insertions(+), 34 deletions(-)
create mode 100644 llvm/test/MC/AMDGPU/bf16_imm.s
create mode 100644 llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
index dc7069decaaa61..7688dfa55a78e3 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
@@ -11,7 +11,10 @@ typedef unsigned short __attribute__((ext_vector_type(2)))
ushort2;
// CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB,
float %fC, i1 false)
// CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB,
float %fC, i1 true)
// CHECK: call half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %v2hA, <2 x half>
%v2hB, half %hC)
-// CHECK: call i16 @llvm.amdgcn.fdot2.bf16.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, i16 %sC)
+// CHECK: [[s1:%[0-9]+]] = bitcast <2 x i16> %v2ssA to <2 x bfloat>
+// CHECK-NEXT: [[s2:%[0-9]+]] = bitcast <2 x i16> %v2ssB to <2 x bfloat>
+// CHECK-NEXT: [[s3:%[0-9]+]] = bitcast i16 %sC to bfloat
+// CHECK-NEXT: [[d:%[0-9]+]] = tail call bfloat
@llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> [[s1]], <2 x bfloat> [[s2]], bfloat
[[s3]])
// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, float %fC, i1 false)
// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, float %fC, i1 true)
// CHECK: call i32 @llvm.amdgcn.udot4(i32 %uiA, i32 %uiB, i32 %uiC, i1 false)
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 202fa4e8f4ea81..6795fb7aa0edb8 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 :
def int_amdgcn_fdot2_bf16_bf16 :
ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">,
DefaultAttrsIntrinsic<
-[llvm_i16_ty], // %r
+[llvm_bfloat_ty], // %r
[
- llvm_v2i16_ty, // %a
- llvm_v2i16_ty, // %b
- llvm_i16_ty// %c
+ llvm_v2bf16_ty, // %a
+ llvm_v2bf16_ty, // %b
+ llvm_bfloat_ty// %c
],
[IntrNoMem, IntrSpeculatable]
>;
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 79ad6ddf7861fc..883b30562e911b 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -475,6 +475,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isSSrcF64() const { return isSCSrc_b64() || isLiteralImm(MVT::f64); }
+ bool isSSrc_bf16() const { return isSCSrcB16() || isLiteralImm(MVT::bf16); }
+
bool isSSrc_f16() const { return isSCSrcB16() || isLiteralImm(MVT::f16); }
bool isSSrcV2F16() const {
@@ -541,22 +543,40 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64);
}
+ bool isVCSrcTBF16() const {
+return isRegOrInlineNoMods(AMDGPU::VS_16RegClassID, MVT::bf16);
+ }
+
bool isVCSrcTF16() const {
return
[clang] [llvm] [AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
@@ -0,0 +1,8 @@ +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck %s + +v_dot2_bf16_bf16 v5, v1, v2, 100.0 +// CHECK: v_dot2_bf16_bf16 v5, v1, v2, 0x42c8 ; encoding: [0x05,0x00,0x67,0xd6,0x01,0x05,0xfe,0x03,0xc8,0x42,0x00,0x00] + +v_dot2_bf16_bf16 v5, v1, v2, 1.0 +// CHECK: v_dot2_bf16_bf16 v5, v1, v2, 1.0 ; encoding: [0x05,0x00,0x67,0xd6,0x01,0x05,0xca,0x03] shiltian wrote: It looks like our assembler doesn't like the case such as `v_dot2_bf16_bf16 v5, v1, 0x42c842c8, 0x42c8`, even w/o this patch. Even the asm (`v_dot2_bf16_bf16 v2, s0, 0x3f803f80, v2`) generated in another file above (`llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll`) can't be recognized by our assembler.  https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
@@ -157,6 +157,27 @@ static uint32_t getLit16Encoding(uint16_t Val, const
MCSubtargetInfo ) {
return 255;
}
+static uint32_t getLitBF16Encoding(uint16_t Val) {
+ uint16_t IntImm = getIntInlineImmEncoding(static_cast(Val));
+ if (IntImm != 0)
+return IntImm;
+
+ // clang-format off
+ switch (Val) {
shiltian wrote:
In theory, yes, but for now we can't because `getInlineEncodingV2BF16` can't
handle some cases (that I didn't dig yet). It looks like in the conversion
between `uint16_t` and `uint32_t` that makes some test cases fail. IMO we need
to unify them (not only for 16-bit) in one place instead of having almost the
same logic at least in three places.
https://github.com/llvm/llvm-project/pull/80908
___
cfe-commits mailing list
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[clang] [llvm] [AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/80908
>From d95e99ebcefa76ba2e8068f663be86340c14ab5b Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Fri, 16 Feb 2024 11:29:47 -0500
Subject: [PATCH] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat
Currently it looks like we generally use `i16` to represent `bf16` in those
tablegen
files. I'm not sure of the reason behind it. My wild guess is the type `bf16`
was
not available when we enabled the support. This patch is trying to use `bf16`
directly in those tablegen files, aiming at fixing #79369. Of course for #79369
a workaround can be to treat all `INT16` variants as `BFloat` in
`getOpFltSemantics`,
but it doesn't look good IMHO.
Since I'm fairly new to AMDGPU backend, I'd appreciate it if you can point out
where I don't understand correctly.
---
.../builtins-amdgcn-dl-insts-gfx11.cl | 5 +-
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 8 +-
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 92 +++
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 57
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 2 +
.../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 39
llvm/lib/Target/AMDGPU/SIDefines.h| 7 ++
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp| 15 +++
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 16 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 21 -
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp| 54 +++
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 16
llvm/lib/Target/AMDGPU/VOP3Instructions.td| 2 +-
.../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 39
llvm/test/MC/AMDGPU/bf16_imm.s| 8 ++
llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt | 9 ++
16 files changed, 356 insertions(+), 34 deletions(-)
create mode 100644 llvm/test/MC/AMDGPU/bf16_imm.s
create mode 100644 llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
index dc7069decaaa61..7688dfa55a78e3 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
@@ -11,7 +11,10 @@ typedef unsigned short __attribute__((ext_vector_type(2)))
ushort2;
// CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB,
float %fC, i1 false)
// CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB,
float %fC, i1 true)
// CHECK: call half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %v2hA, <2 x half>
%v2hB, half %hC)
-// CHECK: call i16 @llvm.amdgcn.fdot2.bf16.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, i16 %sC)
+// CHECK: [[s1:%[0-9]+]] = bitcast <2 x i16> %v2ssA to <2 x bfloat>
+// CHECK-NEXT: [[s2:%[0-9]+]] = bitcast <2 x i16> %v2ssB to <2 x bfloat>
+// CHECK-NEXT: [[s3:%[0-9]+]] = bitcast i16 %sC to bfloat
+// CHECK-NEXT: [[d:%[0-9]+]] = tail call bfloat
@llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> [[s1]], <2 x bfloat> [[s2]], bfloat
[[s3]])
// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, float %fC, i1 false)
// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, float %fC, i1 true)
// CHECK: call i32 @llvm.amdgcn.udot4(i32 %uiA, i32 %uiB, i32 %uiC, i1 false)
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 202fa4e8f4ea81..6795fb7aa0edb8 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 :
def int_amdgcn_fdot2_bf16_bf16 :
ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">,
DefaultAttrsIntrinsic<
-[llvm_i16_ty], // %r
+[llvm_bfloat_ty], // %r
[
- llvm_v2i16_ty, // %a
- llvm_v2i16_ty, // %b
- llvm_i16_ty// %c
+ llvm_v2bf16_ty, // %a
+ llvm_v2bf16_ty, // %b
+ llvm_bfloat_ty// %c
],
[IntrNoMem, IntrSpeculatable]
>;
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 79ad6ddf7861fc..883b30562e911b 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -475,6 +475,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isSSrcF64() const { return isSCSrc_b64() || isLiteralImm(MVT::f64); }
+ bool isSSrc_bf16() const { return isSCSrcB16() || isLiteralImm(MVT::bf16); }
+
bool isSSrc_f16() const { return isSCSrcB16() || isLiteralImm(MVT::f16); }
bool isSSrcV2F16() const {
@@ -541,22 +543,40 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64);
}
+ bool isVCSrcTBF16() const {
+return isRegOrInlineNoMods(AMDGPU::VS_16RegClassID, MVT::bf16);
+ }
+
bool isVCSrcTF16() const {
return
[clang] [llvm] [AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang] Add 'CLANG_ALLOW_IMPLICIT_RPATH' to enable toolchain use of -rpath (PR #82004)
shiltian wrote: IMHO I prefer to ask/request users to do the right thing. Vendors are totally free to do whatever to be convenient for their customers via their compiler wrappers/drivers, but for the community version, following the convention would be good. https://github.com/llvm/llvm-project/pull/82004 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
shiltian wrote: I'll create a ticket about the decoder. https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/80908
>From 9fbb1e610b0de65ae51bb90bd35146b5f927a46a Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Thu, 15 Feb 2024 19:13:44 -0500
Subject: [PATCH] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat
Currently it looks like we generally use `i16` to represent `bf16` in those
tablegen
files. I'm not sure of the reason behind it. My wild guess is the type `bf16`
was
not available when we enabled the support. This patch is trying to use `bf16`
directly in those tablegen files, aiming at fixing #79369. Of course for #79369
a workaround can be to treat all `INT16` variants as `BFloat` in
`getOpFltSemantics`,
but it doesn't look good IMHO.
Since I'm fairly new to AMDGPU backend, I'd appreciate it if you can point out
where I don't understand correctly.
---
.../builtins-amdgcn-dl-insts-gfx11.cl | 5 +-
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 8 +-
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 92 +++
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 57
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 2 +
.../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 39
llvm/lib/Target/AMDGPU/SIDefines.h| 7 ++
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp| 15 +++
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 33 +++
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 21 -
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp| 54 +++
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 16
llvm/lib/Target/AMDGPU/VOP3Instructions.td| 2 +-
.../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 39
llvm/test/MC/AMDGPU/bf16_imm.s| 8 ++
llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt | 9 ++
16 files changed, 363 insertions(+), 44 deletions(-)
create mode 100644 llvm/test/MC/AMDGPU/bf16_imm.s
create mode 100644 llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
index dc7069decaaa61..7688dfa55a78e3 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
@@ -11,7 +11,10 @@ typedef unsigned short __attribute__((ext_vector_type(2)))
ushort2;
// CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB,
float %fC, i1 false)
// CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB,
float %fC, i1 true)
// CHECK: call half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %v2hA, <2 x half>
%v2hB, half %hC)
-// CHECK: call i16 @llvm.amdgcn.fdot2.bf16.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, i16 %sC)
+// CHECK: [[s1:%[0-9]+]] = bitcast <2 x i16> %v2ssA to <2 x bfloat>
+// CHECK-NEXT: [[s2:%[0-9]+]] = bitcast <2 x i16> %v2ssB to <2 x bfloat>
+// CHECK-NEXT: [[s3:%[0-9]+]] = bitcast i16 %sC to bfloat
+// CHECK-NEXT: [[d:%[0-9]+]] = tail call bfloat
@llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> [[s1]], <2 x bfloat> [[s2]], bfloat
[[s3]])
// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, float %fC, i1 false)
// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, float %fC, i1 true)
// CHECK: call i32 @llvm.amdgcn.udot4(i32 %uiA, i32 %uiB, i32 %uiC, i1 false)
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 202fa4e8f4ea81..6795fb7aa0edb8 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 :
def int_amdgcn_fdot2_bf16_bf16 :
ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">,
DefaultAttrsIntrinsic<
-[llvm_i16_ty], // %r
+[llvm_bfloat_ty], // %r
[
- llvm_v2i16_ty, // %a
- llvm_v2i16_ty, // %b
- llvm_i16_ty// %c
+ llvm_v2bf16_ty, // %a
+ llvm_v2bf16_ty, // %b
+ llvm_bfloat_ty// %c
],
[IntrNoMem, IntrSpeculatable]
>;
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 79ad6ddf7861fc..883b30562e911b 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -475,6 +475,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isSSrcF64() const { return isSCSrc_b64() || isLiteralImm(MVT::f64); }
+ bool isSSrc_bf16() const { return isSCSrcB16() || isLiteralImm(MVT::bf16); }
+
bool isSSrc_f16() const { return isSCSrcB16() || isLiteralImm(MVT::f16); }
bool isSSrcV2F16() const {
@@ -541,22 +543,40 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64);
}
+ bool isVCSrcTBF16() const {
+return isRegOrInlineNoMods(AMDGPU::VS_16RegClassID, MVT::bf16);
+ }
+
bool isVCSrcTF16() const {
return
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/80908
>From 784670dd98c3727d8d8aa25f865b7b299f114bf4 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Wed, 14 Feb 2024 13:11:01 -0500
Subject: [PATCH] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat
Currently it looks like we generally use `i16` to represent `bf16` in those
tablegen
files. I'm not sure of the reason behind it. My wild guess is the type `bf16`
was
not available when we enabled the support. This patch is trying to use `bf16`
directly in those tablegen files, aiming at fixing #79369. Of course for #79369
a workaround can be to treat all `INT16` variants as `BFloat` in
`getOpFltSemantics`,
but it doesn't look good IMHO.
Since I'm fairly new to AMDGPU backend, I'd appreciate it if you can point out
where I don't understand correctly.
---
.../builtins-amdgcn-dl-insts-gfx11.cl | 5 +-
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 8 +-
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 92 +++
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 57
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 2 +
.../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 39
llvm/lib/Target/AMDGPU/SIDefines.h| 7 ++
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp| 15 +++
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 58 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 21 -
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp| 54 +++
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 16
llvm/lib/Target/AMDGPU/VOP3Instructions.td| 2 +-
.../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 39
llvm/test/MC/AMDGPU/bf16_imm.s| 8 ++
llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt | 8 ++
16 files changed, 379 insertions(+), 52 deletions(-)
create mode 100644 llvm/test/MC/AMDGPU/bf16_imm.s
create mode 100644 llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt
diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
index dc7069decaaa61..7688dfa55a78e3 100644
--- a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
+++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl
@@ -11,7 +11,10 @@ typedef unsigned short __attribute__((ext_vector_type(2)))
ushort2;
// CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB,
float %fC, i1 false)
// CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB,
float %fC, i1 true)
// CHECK: call half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %v2hA, <2 x half>
%v2hB, half %hC)
-// CHECK: call i16 @llvm.amdgcn.fdot2.bf16.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, i16 %sC)
+// CHECK: [[s1:%[0-9]+]] = bitcast <2 x i16> %v2ssA to <2 x bfloat>
+// CHECK-NEXT: [[s2:%[0-9]+]] = bitcast <2 x i16> %v2ssB to <2 x bfloat>
+// CHECK-NEXT: [[s3:%[0-9]+]] = bitcast i16 %sC to bfloat
+// CHECK-NEXT: [[d:%[0-9]+]] = tail call bfloat
@llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> [[s1]], <2 x bfloat> [[s2]], bfloat
[[s3]])
// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, float %fC, i1 false)
// CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16>
%v2ssB, float %fC, i1 true)
// CHECK: call i32 @llvm.amdgcn.udot4(i32 %uiA, i32 %uiB, i32 %uiC, i1 false)
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 202fa4e8f4ea81..6795fb7aa0edb8 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 :
def int_amdgcn_fdot2_bf16_bf16 :
ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">,
DefaultAttrsIntrinsic<
-[llvm_i16_ty], // %r
+[llvm_bfloat_ty], // %r
[
- llvm_v2i16_ty, // %a
- llvm_v2i16_ty, // %b
- llvm_i16_ty// %c
+ llvm_v2bf16_ty, // %a
+ llvm_v2bf16_ty, // %b
+ llvm_bfloat_ty// %c
],
[IntrNoMem, IntrSpeculatable]
>;
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 79ad6ddf7861fc..883b30562e911b 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -475,6 +475,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isSSrcF64() const { return isSCSrc_b64() || isLiteralImm(MVT::f64); }
+ bool isSSrc_bf16() const { return isSCSrcB16() || isLiteralImm(MVT::bf16); }
+
bool isSSrc_f16() const { return isSCSrcB16() || isLiteralImm(MVT::f16); }
bool isSSrcV2F16() const {
@@ -541,22 +543,40 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64);
}
+ bool isVCSrcTBF16() const {
+return isRegOrInlineNoMods(AMDGPU::VS_16RegClassID, MVT::bf16);
+ }
+
bool isVCSrcTF16() const {
[clang] [Clang][CodeGen] Loose the cast check when emitting builtins (PR #81669)
https://github.com/shiltian closed https://github.com/llvm/llvm-project/pull/81669 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/80908 >From 1488b4e54982be4d3f5bc7f35617effcab52be48 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Wed, 14 Feb 2024 09:41:00 -0500 Subject: [PATCH] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat Currently it looks like we generally use `i16` to represent `bf16` in those tablegen files. I'm not sure of the reason behind it. My wild guess is the type `bf16` was not available when we enabled the support. This patch is trying to use `bf16` directly in those tablegen files, aiming at fixing #79369. Of course for #79369 a workaround can be to treat all `INT16` variants as `BFloat` in `getOpFltSemantics`, but it doesn't look good IMHO. Since I'm fairly new to AMDGPU backend, I'd appreciate it if you can point out where I don't understand correctly. --- clang/lib/CodeGen/CGBuiltin.cpp | 4 - .../builtins-amdgcn-dl-insts-gfx11.cl | 5 +- llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 8 +- .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 92 +++ .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 57 .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 2 + .../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 39 llvm/lib/Target/AMDGPU/SIDefines.h| 7 ++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp| 15 +++ llvm/lib/Target/AMDGPU/SIInstrInfo.td | 58 ++-- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 21 - .../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp| 54 +++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 16 llvm/lib/Target/AMDGPU/VOP3Instructions.td| 2 +- .../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 39 llvm/test/MC/AMDGPU/bf16_imm.s| 8 ++ llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt | 8 ++ 17 files changed, 379 insertions(+), 56 deletions(-) create mode 100644 llvm/test/MC/AMDGPU/bf16_imm.s create mode 100644 llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index ee0b7504769622..9bc60466d09be6 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -5912,8 +5912,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } } -assert(ArgValue->getType()->canLosslesslyBitCastTo(PTy) && - "Must be able to losslessly bit cast to param"); // Cast vector type (e.g., v256i32) to x86_amx, this only happen // in amx intrinsics. if (PTy->isX86_AMXTy()) @@ -5943,8 +5941,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } } - assert(V->getType()->canLosslesslyBitCastTo(RetTy) && - "Must be able to losslessly bit cast result type"); // Cast x86_amx to vector type (e.g., v256i32), this only happen // in amx intrinsics. if (V->getType()->isX86_AMXTy()) diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl index dc7069decaaa61..7688dfa55a78e3 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl @@ -11,7 +11,10 @@ typedef unsigned short __attribute__((ext_vector_type(2))) ushort2; // CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB, float %fC, i1 false) // CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB, float %fC, i1 true) // CHECK: call half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %v2hA, <2 x half> %v2hB, half %hC) -// CHECK: call i16 @llvm.amdgcn.fdot2.bf16.bf16(<2 x i16> %v2ssA, <2 x i16> %v2ssB, i16 %sC) +// CHECK: [[s1:%[0-9]+]] = bitcast <2 x i16> %v2ssA to <2 x bfloat> +// CHECK-NEXT: [[s2:%[0-9]+]] = bitcast <2 x i16> %v2ssB to <2 x bfloat> +// CHECK-NEXT: [[s3:%[0-9]+]] = bitcast i16 %sC to bfloat +// CHECK-NEXT: [[d:%[0-9]+]] = tail call bfloat @llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> [[s1]], <2 x bfloat> [[s2]], bfloat [[s3]]) // CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16> %v2ssB, float %fC, i1 false) // CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16> %v2ssB, float %fC, i1 true) // CHECK: call i32 @llvm.amdgcn.udot4(i32 %uiA, i32 %uiB, i32 %uiC, i1 false) diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index 202fa4e8f4ea81..6795fb7aa0edb8 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 : def int_amdgcn_fdot2_bf16_bf16 : ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">, DefaultAttrsIntrinsic< -[llvm_i16_ty], // %r +[llvm_bfloat_ty], // %r [ - llvm_v2i16_ty, // %a - llvm_v2i16_ty, // %b - llvm_i16_ty// %c +
[clang] [Clang][CodeGen] Loose the cast check when emitting builtins (PR #81669)
shiltian wrote: > Don't see how that could be related; you can losslessly bitconvert between > i16 and bfloat Yes, `canLosslesslyBitCastTo` doesn't allow cast between `i16` and `bfloat`, but it does between two vectors, as long as their sizes are the same. > A cast between float and int sounds like "re-interpretation of the bits" to > me. Though the function already allows it if it's a vector of int/float. Yeah. I was reluctant to allow it in `canLosslesslyBitCastTo` also because of that. Since it allows vector conversion, it already breaks the purpose. https://github.com/llvm/llvm-project/pull/81669 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Loose the cast check when emitting builtins (PR #81669)
shiltian wrote: > I can't tell what you're trying to fix here. Is this fixing a crash? Or is > the check redundant? Or is it necessary for some followup change you want to > make? Sorry, I should have clearly mentioned that. Yes, it is for my followup change #80908. In #80908, we changed the type of LLVM builtin but kept the corresponding clang builtin unchanged to avoid breaking existing uses. Specifically, the original builtin accepts some `bfloat` arguments (either `bfloat` or `<2 x bfloat>`) and returns a `bfloat` value. Because of some historic reasons, the builtin uses `i16` to represent `bfloat` values, and the backend just treats the 16 bits as `bfloat`. Now we encountered some issues that motivated us to use the right type here, but we still want to maintain sort of backward compatibility, at least on user-facing level. Keeping the corresponding clang builtin unchanged is the path we chose. Given that, it requires the front end to emit corresponding bitcast because the type `i16` and `bfloat` (and the vec type) are not matched. `EmitBuiltinExpr` is capable of doing that, but the bitcast check here prevents it from doing it. `canLosslesslyBitCastTo` doesn't think bitcast from `i16` to `bf16` and vice versa are lossless. I was thinking of just allowing this specific cast in `canLosslesslyBitCastTo` but I figured that doesn't look very good. On a second thought, it looks like the check here is too conservative. https://github.com/llvm/llvm-project/pull/81669 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
@@ -0,0 +1,8 @@ +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1100 -disassemble -show-encoding < %s | FileCheck %s +# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1200 -disassemble -show-encoding < %s | FileCheck %s + +# CHECK: v_dot2_bf16_bf16 v5, v1, v2, 0x42c8 +0x05,0x00,0x67,0xd6,0x01,0x05,0xfe,0x03,0xc8,0x42,0x00,0x00 + +# CHECK: v_dot2_bf16_bf16 v5, v1, v2, 0x3c00 shiltian wrote: The disassembler doesn't work properly because when it sees `242` with bitwidth 16, it doesn't know whether it is bf16 or fp16. https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/80908 >From 7a517eeab81b45616dd7a1511380f4696304375a Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Tue, 13 Feb 2024 21:59:52 -0500 Subject: [PATCH] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat Currently it looks like we generally use `i16` to represent `bf16` in those tablegen files. I'm not sure of the reason behind it. My wild guess is the type `bf16` was not available when we enabled the support. This patch is trying to use `bf16` directly in those tablegen files, aiming at fixing #79369. Of course for #79369 a workaround can be to treat all `INT16` variants as `BFloat` in `getOpFltSemantics`, but it doesn't look good IMHO. Since I'm fairly new to AMDGPU backend, I'd appreciate it if you can point out where I don't understand correctly. --- clang/lib/CodeGen/CGBuiltin.cpp | 4 - .../builtins-amdgcn-dl-insts-gfx11.cl | 5 +- llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 8 +- .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 92 +++ .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 57 .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 2 + .../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 39 llvm/lib/Target/AMDGPU/SIDefines.h| 7 ++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp| 15 +++ llvm/lib/Target/AMDGPU/SIInstrInfo.td | 58 ++-- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 21 - .../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp| 54 +++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 16 llvm/lib/Target/AMDGPU/VOP3Instructions.td| 2 +- .../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 51 -- llvm/test/MC/AMDGPU/bf16_imm.s| 8 ++ llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt | 8 ++ 17 files changed, 379 insertions(+), 68 deletions(-) create mode 100644 llvm/test/MC/AMDGPU/bf16_imm.s create mode 100644 llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index ee0b7504769622..9bc60466d09be6 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -5912,8 +5912,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } } -assert(ArgValue->getType()->canLosslesslyBitCastTo(PTy) && - "Must be able to losslessly bit cast to param"); // Cast vector type (e.g., v256i32) to x86_amx, this only happen // in amx intrinsics. if (PTy->isX86_AMXTy()) @@ -5943,8 +5941,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } } - assert(V->getType()->canLosslesslyBitCastTo(RetTy) && - "Must be able to losslessly bit cast result type"); // Cast x86_amx to vector type (e.g., v256i32), this only happen // in amx intrinsics. if (V->getType()->isX86_AMXTy()) diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl index dc7069decaaa61..7688dfa55a78e3 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl @@ -11,7 +11,10 @@ typedef unsigned short __attribute__((ext_vector_type(2))) ushort2; // CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB, float %fC, i1 false) // CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB, float %fC, i1 true) // CHECK: call half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %v2hA, <2 x half> %v2hB, half %hC) -// CHECK: call i16 @llvm.amdgcn.fdot2.bf16.bf16(<2 x i16> %v2ssA, <2 x i16> %v2ssB, i16 %sC) +// CHECK: [[s1:%[0-9]+]] = bitcast <2 x i16> %v2ssA to <2 x bfloat> +// CHECK-NEXT: [[s2:%[0-9]+]] = bitcast <2 x i16> %v2ssB to <2 x bfloat> +// CHECK-NEXT: [[s3:%[0-9]+]] = bitcast i16 %sC to bfloat +// CHECK-NEXT: [[d:%[0-9]+]] = tail call bfloat @llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> [[s1]], <2 x bfloat> [[s2]], bfloat [[s3]]) // CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16> %v2ssB, float %fC, i1 false) // CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16> %v2ssB, float %fC, i1 true) // CHECK: call i32 @llvm.amdgcn.udot4(i32 %uiA, i32 %uiB, i32 %uiC, i1 false) diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index 202fa4e8f4ea81..6795fb7aa0edb8 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 : def int_amdgcn_fdot2_bf16_bf16 : ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">, DefaultAttrsIntrinsic< -[llvm_i16_ty], // %r +[llvm_bfloat_ty], // %r [ - llvm_v2i16_ty, // %a - llvm_v2i16_ty, // %b - llvm_i16_ty// %c +
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/80908 >From 47b96d282d5416f9dd4c41013d44f8865a1a0d31 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Tue, 13 Feb 2024 21:34:44 -0500 Subject: [PATCH] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat Currently it looks like we generally use `i16` to represent `bf16` in those tablegen files. I'm not sure of the reason behind it. My wild guess is the type `bf16` was not available when we enabled the support. This patch is trying to use `bf16` directly in those tablegen files, aiming at fixing #79369. Of course for #79369 a workaround can be to treat all `INT16` variants as `BFloat` in `getOpFltSemantics`, but it doesn't look good IMHO. Since I'm fairly new to AMDGPU backend, I'd appreciate it if you can point out where I don't understand correctly. --- clang/lib/CodeGen/CGBuiltin.cpp | 4 -- .../builtins-amdgcn-dl-insts-gfx11.cl | 5 +- llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 8 +-- .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 71 +++ .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 57 +++ .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 2 + .../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 7 ++ llvm/lib/Target/AMDGPU/SIDefines.h| 7 ++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp| 15 llvm/lib/Target/AMDGPU/SIInstrInfo.td | 58 --- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 21 +- .../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp| 54 ++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 16 + llvm/lib/Target/AMDGPU/VOP3Instructions.td| 2 +- .../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 51 ++--- llvm/test/MC/AMDGPU/bf16_imm.s| 8 +++ llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt | 8 +++ 17 files changed, 326 insertions(+), 68 deletions(-) create mode 100644 llvm/test/MC/AMDGPU/bf16_imm.s create mode 100644 llvm/test/MC/Disassembler/AMDGPU/bf16_imm.txt diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index ee0b7504769622..9bc60466d09be6 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -5912,8 +5912,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } } -assert(ArgValue->getType()->canLosslesslyBitCastTo(PTy) && - "Must be able to losslessly bit cast to param"); // Cast vector type (e.g., v256i32) to x86_amx, this only happen // in amx intrinsics. if (PTy->isX86_AMXTy()) @@ -5943,8 +5941,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } } - assert(V->getType()->canLosslesslyBitCastTo(RetTy) && - "Must be able to losslessly bit cast result type"); // Cast x86_amx to vector type (e.g., v256i32), this only happen // in amx intrinsics. if (V->getType()->isX86_AMXTy()) diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl index dc7069decaaa61..7688dfa55a78e3 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl @@ -11,7 +11,10 @@ typedef unsigned short __attribute__((ext_vector_type(2))) ushort2; // CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB, float %fC, i1 false) // CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB, float %fC, i1 true) // CHECK: call half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %v2hA, <2 x half> %v2hB, half %hC) -// CHECK: call i16 @llvm.amdgcn.fdot2.bf16.bf16(<2 x i16> %v2ssA, <2 x i16> %v2ssB, i16 %sC) +// CHECK: [[s1:%[0-9]+]] = bitcast <2 x i16> %v2ssA to <2 x bfloat> +// CHECK-NEXT: [[s2:%[0-9]+]] = bitcast <2 x i16> %v2ssB to <2 x bfloat> +// CHECK-NEXT: [[s3:%[0-9]+]] = bitcast i16 %sC to bfloat +// CHECK-NEXT: [[d:%[0-9]+]] = tail call bfloat @llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> [[s1]], <2 x bfloat> [[s2]], bfloat [[s3]]) // CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16> %v2ssB, float %fC, i1 false) // CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16> %v2ssB, float %fC, i1 true) // CHECK: call i32 @llvm.amdgcn.udot4(i32 %uiA, i32 %uiB, i32 %uiC, i1 false) diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index 202fa4e8f4ea81..6795fb7aa0edb8 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 : def int_amdgcn_fdot2_bf16_bf16 : ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">, DefaultAttrsIntrinsic< -[llvm_i16_ty], // %r +[llvm_bfloat_ty], // %r [ - llvm_v2i16_ty, // %a - llvm_v2i16_ty, // %b - llvm_i16_ty
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
@@ -4185,9 +4185,17 @@ bool SIInstrInfo::isInlineConstant(const MachineOperand , case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: return AMDGPU::isInlinableLiteralV2F16(Imm); + case AMDGPU::OPERAND_REG_IMM_V2BF16: + case AMDGPU::OPERAND_REG_INLINE_C_V2BF16: + case AMDGPU::OPERAND_REG_INLINE_AC_V2BF16: +return AMDGPU::isInlinableLiteralV2BF16(Imm); + case AMDGPU::OPERAND_REG_IMM_BF16: case AMDGPU::OPERAND_REG_IMM_FP16: + case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED: case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: + case AMDGPU::OPERAND_REG_INLINE_C_BF16: case AMDGPU::OPERAND_REG_INLINE_C_FP16: + case AMDGPU::OPERAND_REG_INLINE_AC_BF16: shiltian wrote: Okay, I copied `isInlinableLiteralBF16` from https://github.com/llvm/llvm-project/pull/81345. Initially I thought https://github.com/llvm/llvm-project/pull/81345 would be landed before this one, but I went down that rabbit hole and still didn't make it fully work. https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/80908 >From 22fd628687652e7f9d8795c48e9f794fdd684c45 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Tue, 13 Feb 2024 21:27:17 -0500 Subject: [PATCH] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat Currently it looks like we generally use `i16` to represent `bf16` in those tablegen files. I'm not sure of the reason behind it. My wild guess is the type `bf16` was not available when we enabled the support. This patch is trying to use `bf16` directly in those tablegen files, aiming at fixing #79369. Of course for #79369 a workaround can be to treat all `INT16` variants as `BFloat` in `getOpFltSemantics`, but it doesn't look good IMHO. Since I'm fairly new to AMDGPU backend, I'd appreciate it if you can point out where I don't understand correctly. --- clang/lib/CodeGen/CGBuiltin.cpp | 4 -- .../builtins-amdgcn-dl-insts-gfx11.cl | 5 +- llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 8 +-- .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 71 +++ .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 57 +++ .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 2 + .../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 7 ++ llvm/lib/Target/AMDGPU/SIDefines.h| 7 ++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp| 15 llvm/lib/Target/AMDGPU/SIInstrInfo.td | 58 --- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 21 +- .../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp| 54 ++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 16 + llvm/lib/Target/AMDGPU/VOP3Instructions.td| 2 +- .../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 51 ++--- llvm/test/MC/AMDGPU/bf16_imm.s| 8 +++ 16 files changed, 318 insertions(+), 68 deletions(-) create mode 100644 llvm/test/MC/AMDGPU/bf16_imm.s diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index ee0b7504769622..9bc60466d09be6 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -5912,8 +5912,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } } -assert(ArgValue->getType()->canLosslesslyBitCastTo(PTy) && - "Must be able to losslessly bit cast to param"); // Cast vector type (e.g., v256i32) to x86_amx, this only happen // in amx intrinsics. if (PTy->isX86_AMXTy()) @@ -5943,8 +5941,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } } - assert(V->getType()->canLosslesslyBitCastTo(RetTy) && - "Must be able to losslessly bit cast result type"); // Cast x86_amx to vector type (e.g., v256i32), this only happen // in amx intrinsics. if (V->getType()->isX86_AMXTy()) diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl index dc7069decaaa61..7688dfa55a78e3 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl @@ -11,7 +11,10 @@ typedef unsigned short __attribute__((ext_vector_type(2))) ushort2; // CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB, float %fC, i1 false) // CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB, float %fC, i1 true) // CHECK: call half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %v2hA, <2 x half> %v2hB, half %hC) -// CHECK: call i16 @llvm.amdgcn.fdot2.bf16.bf16(<2 x i16> %v2ssA, <2 x i16> %v2ssB, i16 %sC) +// CHECK: [[s1:%[0-9]+]] = bitcast <2 x i16> %v2ssA to <2 x bfloat> +// CHECK-NEXT: [[s2:%[0-9]+]] = bitcast <2 x i16> %v2ssB to <2 x bfloat> +// CHECK-NEXT: [[s3:%[0-9]+]] = bitcast i16 %sC to bfloat +// CHECK-NEXT: [[d:%[0-9]+]] = tail call bfloat @llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> [[s1]], <2 x bfloat> [[s2]], bfloat [[s3]]) // CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16> %v2ssB, float %fC, i1 false) // CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16> %v2ssB, float %fC, i1 true) // CHECK: call i32 @llvm.amdgcn.udot4(i32 %uiA, i32 %uiB, i32 %uiC, i1 false) diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index 202fa4e8f4ea81..6795fb7aa0edb8 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 : def int_amdgcn_fdot2_bf16_bf16 : ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">, DefaultAttrsIntrinsic< -[llvm_i16_ty], // %r +[llvm_bfloat_ty], // %r [ - llvm_v2i16_ty, // %a - llvm_v2i16_ty, // %b - llvm_i16_ty// %c + llvm_v2bf16_ty, // %a + llvm_v2bf16_ty, // %b + llvm_bfloat_ty// %c ], [IntrNoMem,
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/80908 >From d72bf8bb9d1091ba76e17bf09b0aad9073e18caa Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Tue, 13 Feb 2024 19:02:41 -0500 Subject: [PATCH] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat Currently it looks like we generally use `i16` to represent `bf16` in those tablegen files. I'm not sure of the reason behind it. My wild guess is the type `bf16` was not available when we enabled the support. This patch is trying to use `bf16` directly in those tablegen files, aiming at fixing #79369. Of course for #79369 a workaround can be to treat all `INT16` variants as `BFloat` in `getOpFltSemantics`, but it doesn't look good IMHO. Since I'm fairly new to AMDGPU backend, I'd appreciate it if you can point out where I don't understand correctly. --- clang/lib/CodeGen/CGBuiltin.cpp | 4 -- .../builtins-amdgcn-dl-insts-gfx11.cl | 5 +- llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 8 +-- .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 71 +++ .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 57 +++ .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 2 + .../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 7 ++ llvm/lib/Target/AMDGPU/SIDefines.h| 7 ++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp| 8 +++ llvm/lib/Target/AMDGPU/SIInstrInfo.td | 58 --- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 21 +- .../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp| 37 ++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 15 llvm/lib/Target/AMDGPU/VOP3Instructions.td| 2 +- .../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 51 ++--- llvm/test/MC/AMDGPU/bf16_imm.s| 8 +++ 16 files changed, 293 insertions(+), 68 deletions(-) create mode 100644 llvm/test/MC/AMDGPU/bf16_imm.s diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index ee0b7504769622..9bc60466d09be6 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -5912,8 +5912,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } } -assert(ArgValue->getType()->canLosslesslyBitCastTo(PTy) && - "Must be able to losslessly bit cast to param"); // Cast vector type (e.g., v256i32) to x86_amx, this only happen // in amx intrinsics. if (PTy->isX86_AMXTy()) @@ -5943,8 +5941,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } } - assert(V->getType()->canLosslesslyBitCastTo(RetTy) && - "Must be able to losslessly bit cast result type"); // Cast x86_amx to vector type (e.g., v256i32), this only happen // in amx intrinsics. if (V->getType()->isX86_AMXTy()) diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl index dc7069decaaa61..7688dfa55a78e3 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx11.cl @@ -11,7 +11,10 @@ typedef unsigned short __attribute__((ext_vector_type(2))) ushort2; // CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB, float %fC, i1 false) // CHECK: call float @llvm.amdgcn.fdot2(<2 x half> %v2hA, <2 x half> %v2hB, float %fC, i1 true) // CHECK: call half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %v2hA, <2 x half> %v2hB, half %hC) -// CHECK: call i16 @llvm.amdgcn.fdot2.bf16.bf16(<2 x i16> %v2ssA, <2 x i16> %v2ssB, i16 %sC) +// CHECK: [[s1:%[0-9]+]] = bitcast <2 x i16> %v2ssA to <2 x bfloat> +// CHECK-NEXT: [[s2:%[0-9]+]] = bitcast <2 x i16> %v2ssB to <2 x bfloat> +// CHECK-NEXT: [[s3:%[0-9]+]] = bitcast i16 %sC to bfloat +// CHECK-NEXT: [[d:%[0-9]+]] = tail call bfloat @llvm.amdgcn.fdot2.bf16.bf16(<2 x bfloat> [[s1]], <2 x bfloat> [[s2]], bfloat [[s3]]) // CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16> %v2ssB, float %fC, i1 false) // CHECK: call float @llvm.amdgcn.fdot2.f32.bf16(<2 x i16> %v2ssA, <2 x i16> %v2ssB, float %fC, i1 true) // CHECK: call i32 @llvm.amdgcn.udot4(i32 %uiA, i32 %uiB, i32 %uiC, i1 false) diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td index 202fa4e8f4ea81..6795fb7aa0edb8 100644 --- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td @@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 : def int_amdgcn_fdot2_bf16_bf16 : ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">, DefaultAttrsIntrinsic< -[llvm_i16_ty], // %r +[llvm_bfloat_ty], // %r [ - llvm_v2i16_ty, // %a - llvm_v2i16_ty, // %b - llvm_i16_ty// %c + llvm_v2bf16_ty, // %a + llvm_v2bf16_ty, // %b + llvm_bfloat_ty// %c ], [IntrNoMem,
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
@@ -4185,9 +4185,17 @@ bool SIInstrInfo::isInlineConstant(const MachineOperand , case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: return AMDGPU::isInlinableLiteralV2F16(Imm); + case AMDGPU::OPERAND_REG_IMM_V2BF16: + case AMDGPU::OPERAND_REG_INLINE_C_V2BF16: + case AMDGPU::OPERAND_REG_INLINE_AC_V2BF16: +return AMDGPU::isInlinableLiteralV2BF16(Imm); + case AMDGPU::OPERAND_REG_IMM_BF16: case AMDGPU::OPERAND_REG_IMM_FP16: + case AMDGPU::OPERAND_REG_IMM_BF16_DEFERRED: case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED: + case AMDGPU::OPERAND_REG_INLINE_C_BF16: case AMDGPU::OPERAND_REG_INLINE_C_FP16: + case AMDGPU::OPERAND_REG_INLINE_AC_BF16: shiltian wrote: Yes, `isInlinableLiteral16` can't because it can't tell `fp16` and `bf16` apart by just looking at the value. That's the reason I tried really hard to get rid of `isInlinableLiteral16` in #81345 and favors the explicit version. https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
@@ -488,6 +488,49 @@ static bool printImmediateFloat16(uint32_t Imm, const
MCSubtargetInfo ,
return true;
}
+static bool printImmediateBFloat16(uint32_t Imm, const MCSubtargetInfo ,
+ raw_ostream ) {
+ if (Imm == 0x3F80)
+O << "1.0";
+ else if (Imm == 0xBF80)
+O << "-1.0";
+ else if (Imm == 0x3F00)
+O << "0.5";
+ else if (Imm == 0xBF00)
+O << "-0.5";
+ else if (Imm == 0x4000)
+O << "2.0";
+ else if (Imm == 0xC000)
+O << "-2.0";
+ else if (Imm == 0x4080)
+O << "4.0";
+ else if (Imm == 0xC080)
+O << "-4.0";
+ else if (Imm == 0x3E22 && STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
+O << "0.15915494";
+ else
+return false;
+
+ return true;
+}
+
+void AMDGPUInstPrinter::printImmediateBF16(uint32_t Imm,
+ const MCSubtargetInfo ,
+ raw_ostream ) {
+ int16_t SImm = static_cast(Imm);
+ if (isInlinableIntLiteral(SImm)) {
+O << SImm;
+return;
+ }
+
+ uint16_t HImm = static_cast(Imm);
+ if (printImmediateBFloat16(HImm, STI, O))
+return;
+
+ uint64_t Imm16 = static_cast(Imm);
shiltian wrote:
Yeah, but it is to make the type promoted to `uint64_t` w/o any ambiguity.
https://github.com/llvm/llvm-project/pull/80908
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[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
@@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 : def int_amdgcn_fdot2_bf16_bf16 : ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">, DefaultAttrsIntrinsic< -[llvm_i16_ty], // %r +[llvm_bfloat_ty], // %r shiltian wrote: The cast will be inserted automatically in `clang/lib/CodeGen/CGBuiltin.cpp` after removing the two assertions. I reverted my change to the test case by accident. Lol https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
@@ -1,8 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11 -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11 shiltian wrote: This change is because of the discussion here (https://github.com/llvm/llvm-project/pull/80908/files#r1483394728). https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/80908
>From bfd3170dc5e4d6e53fb98b46b37f2bf3c3ebf86d Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 13 Feb 2024 17:39:23 -0500
Subject: [PATCH] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat
Currently it looks like we generally use `i16` to represent `bf16` in those
tablegen
files. I'm not sure of the reason behind it. My wild guess is the type `bf16`
was
not available when we enabled the support. This patch is trying to use `bf16`
directly in those tablegen files, aiming at fixing #79369. Of course for #79369
a workaround can be to treat all `INT16` variants as `BFloat` in
`getOpFltSemantics`,
but it doesn't look good IMHO.
Since I'm fairly new to AMDGPU backend, I'd appreciate it if you can point out
where I don't understand correctly.
---
clang/lib/CodeGen/CGBuiltin.cpp | 4 --
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 8 +--
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 71 +++
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 59 +++
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 2 +
.../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 7 ++
llvm/lib/Target/AMDGPU/SIDefines.h| 7 ++
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp| 8 +++
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 58 ---
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 21 +-
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp| 37 ++
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 15
llvm/lib/Target/AMDGPU/VOP3Instructions.td| 2 +-
.../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 49 +
llvm/test/MC/AMDGPU/bf16_imm.s| 8 +++
15 files changed, 289 insertions(+), 67 deletions(-)
create mode 100644 llvm/test/MC/AMDGPU/bf16_imm.s
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index ee0b7504769622..9bc60466d09be6 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -5912,8 +5912,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
}
}
-assert(ArgValue->getType()->canLosslesslyBitCastTo(PTy) &&
- "Must be able to losslessly bit cast to param");
// Cast vector type (e.g., v256i32) to x86_amx, this only happen
// in amx intrinsics.
if (PTy->isX86_AMXTy())
@@ -5943,8 +5941,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
}
}
- assert(V->getType()->canLosslesslyBitCastTo(RetTy) &&
- "Must be able to losslessly bit cast result type");
// Cast x86_amx to vector type (e.g., v256i32), this only happen
// in amx intrinsics.
if (V->getType()->isX86_AMXTy())
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 202fa4e8f4ea81..6795fb7aa0edb8 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 :
def int_amdgcn_fdot2_bf16_bf16 :
ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">,
DefaultAttrsIntrinsic<
-[llvm_i16_ty], // %r
+[llvm_bfloat_ty], // %r
[
- llvm_v2i16_ty, // %a
- llvm_v2i16_ty, // %b
- llvm_i16_ty// %c
+ llvm_v2bf16_ty, // %a
+ llvm_v2bf16_ty, // %b
+ llvm_bfloat_ty// %c
],
[IntrNoMem, IntrSpeculatable]
>;
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 79ad6ddf7861fc..09f25215beb9e5 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -475,6 +475,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isSSrcF64() const { return isSCSrc_b64() || isLiteralImm(MVT::f64); }
+ bool isSSrc_bf16() const { return isSCSrcB16() || isLiteralImm(MVT::bf16); }
+
bool isSSrc_f16() const { return isSCSrcB16() || isLiteralImm(MVT::f16); }
bool isSSrcV2F16() const {
@@ -541,22 +543,40 @@ class AMDGPUOperand : public MCParsedAsmOperand {
return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64);
}
+ bool isVCSrcTBF16() const {
+return isRegOrInlineNoMods(AMDGPU::VS_16RegClassID, MVT::bf16);
+ }
+
bool isVCSrcTF16() const {
return isRegOrInlineNoMods(AMDGPU::VS_16RegClassID, MVT::f16);
}
+ bool isVCSrcTBF16_Lo128() const {
+return isRegOrInlineNoMods(AMDGPU::VS_16_Lo128RegClassID, MVT::bf16);
+ }
+
bool isVCSrcTF16_Lo128() const {
return isRegOrInlineNoMods(AMDGPU::VS_16_Lo128RegClassID, MVT::f16);
}
+ bool isVCSrcFake16BF16_Lo128() const {
+return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID, MVT::bf16);
+ }
+
bool isVCSrcFake16F16_Lo128() const {
return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID,
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
@@ -79,17 +79,17 @@ define amdgpu_ps void @test_llvm_amdgcn_fdot2_bf16_bf16_sis( ; GFX11: ; %bb.0: ; %entry ; GFX11-NEXT:v_mov_b32_e32 v2, s1 ; GFX11-NEXT:s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT:v_dot2_bf16_bf16 v2, s0, 0x10001, v2 +; GFX11-NEXT:v_dot2_bf16_bf16 v2, s0, 0x3f803f80, v2 shiltian wrote: FWIW, #81345 can solve the issue but I'm struggling with getting two test cases passed. https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
shiltian wrote: The patch is in a good shape now. I have made two other prime patches (#81674 and #81669). I'll rebase this one once they are landed. This patch only changes one bf16 instruction with the necessary infrastructure for others. I'll update all of them once this patch is landed. However, I don't think `isInlinableLiteral16` works correctly because the encoding of the floating point inline literals are different for fp16 and bf16, but apparently for now it can only recognize fp16 encoding. This patch at least makes the asm printer work properly. #81345 is trying to fix it correctly, but that is unrelated to this patch. https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [Clang][CodeGen] Loose the cast check when emitting builtins (PR #81669)
https://github.com/shiltian created https://github.com/llvm/llvm-project/pull/81669 This patch looses the cast check (`canLosslesslyBitCastTo`) and leaves it to the one inside `CreateBitCast`. It seems too conservative for the use case here. >From 813441fd3106a0069346aabd0dd828d8feb8ea53 Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Tue, 13 Feb 2024 16:39:25 -0500 Subject: [PATCH] [Clang][CodeGen] Loose the cast check when emitting builtins This patch looses the cast check (`canLosslesslyBitCastTo`) and leaves it to the one inside `CreateBitCast`. It seems too conservative for the use case here. --- clang/lib/CodeGen/CGBuiltin.cpp | 4 1 file changed, 4 deletions(-) diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index ee0b7504769622..9bc60466d09be6 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -5912,8 +5912,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } } -assert(ArgValue->getType()->canLosslesslyBitCastTo(PTy) && - "Must be able to losslessly bit cast to param"); // Cast vector type (e.g., v256i32) to x86_amx, this only happen // in amx intrinsics. if (PTy->isX86_AMXTy()) @@ -5943,8 +5941,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } } - assert(V->getType()->canLosslesslyBitCastTo(RetTy) && - "Must be able to losslessly bit cast result type"); // Cast x86_amx to vector type (e.g., v256i32), this only happen // in amx intrinsics. if (V->getType()->isX86_AMXTy()) ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/80908
>From c556e40c13adb9d253ef7c5ebb2b46cb12969d46 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Tue, 13 Feb 2024 15:30:51 -0500
Subject: [PATCH] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat
Currently it looks like we generally use `i16` to represent `bf16` in those
tablegen
files. I'm not sure of the reason behind it. My wild guess is the type `bf16`
was
not available when we enabled the support. This patch is trying to use `bf16`
directly in those tablegen files, aiming at fixing #79369. Of course for #79369
a workaround can be to treat all `INT16` variants as `BFloat` in
`getOpFltSemantics`,
but it doesn't look good IMHO.
Since I'm fairly new to AMDGPU backend, I'd appreciate it if you can point out
where I don't understand correctly.
---
clang/lib/CodeGen/CGBuiltin.cpp | 4 --
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 8 +--
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 5 +-
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 71 +++
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 59 +++
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 2 +
.../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 7 ++
llvm/lib/Target/AMDGPU/SIDefines.h| 7 ++
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp| 8 +++
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 58 ---
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 21 +-
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp| 37 ++
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 15
llvm/lib/Target/AMDGPU/VOP3Instructions.td| 2 +-
.../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 36 +-
llvm/test/MC/AMDGPU/bf16_imm.s| 8 +++
16 files changed, 292 insertions(+), 56 deletions(-)
create mode 100644 llvm/test/MC/AMDGPU/bf16_imm.s
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index ee0b7504769622..9bc60466d09be6 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -5912,8 +5912,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
}
}
-assert(ArgValue->getType()->canLosslesslyBitCastTo(PTy) &&
- "Must be able to losslessly bit cast to param");
// Cast vector type (e.g., v256i32) to x86_amx, this only happen
// in amx intrinsics.
if (PTy->isX86_AMXTy())
@@ -5943,8 +5941,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
}
}
- assert(V->getType()->canLosslesslyBitCastTo(RetTy) &&
- "Must be able to losslessly bit cast result type");
// Cast x86_amx to vector type (e.g., v256i32), this only happen
// in amx intrinsics.
if (V->getType()->isX86_AMXTy())
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 202fa4e8f4ea81..6795fb7aa0edb8 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 :
def int_amdgcn_fdot2_bf16_bf16 :
ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">,
DefaultAttrsIntrinsic<
-[llvm_i16_ty], // %r
+[llvm_bfloat_ty], // %r
[
- llvm_v2i16_ty, // %a
- llvm_v2i16_ty, // %b
- llvm_i16_ty// %c
+ llvm_v2bf16_ty, // %a
+ llvm_v2bf16_ty, // %b
+ llvm_bfloat_ty// %c
],
[IntrNoMem, IntrSpeculatable]
>;
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 311dd9d9739a6d..3290262816ef0a 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1562,8 +1562,9 @@ bool IRTranslator::translateBitCast(const User ,
bool IRTranslator::translateCast(unsigned Opcode, const User ,
MachineIRBuilder ) {
- if (U.getType()->getScalarType()->isBFloatTy() ||
- U.getOperand(0)->getType()->getScalarType()->isBFloatTy())
+ if (Opcode != TargetOpcode::G_BITCAST &&
+ (U.getType()->getScalarType()->isBFloatTy() ||
+ U.getOperand(0)->getType()->getScalarType()->isBFloatTy()))
return false;
Register Op = getOrCreateVReg(*U.getOperand(0));
Register Res = getOrCreateVReg(U);
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 79ad6ddf7861fc..09f25215beb9e5 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -475,6 +475,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isSSrcF64() const { return isSCSrc_b64() || isLiteralImm(MVT::f64); }
+ bool isSSrc_bf16() const { return isSCSrcB16() || isLiteralImm(MVT::bf16); }
+
bool isSSrc_f16() const { return
[clang] [llvm] [LLVM] Add `__builtin_readsteadycounter` intrinsic and builtin for realtime clocks (PR #81331)
https://github.com/shiltian approved this pull request. LG https://github.com/llvm/llvm-project/pull/81331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/80908
>From df3dbb6b9c257157c4afb407e40447a25c27a2a8 Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Mon, 12 Feb 2024 18:03:57 -0500
Subject: [PATCH] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat
Currently it looks like we generally use `i16` to represent `bf16` in those
tablegen
files. I'm not sure of the reason behind it. My wild guess is the type `bf16`
was
not available when we enabled the support. This patch is trying to use `bf16`
directly in those tablegen files, aiming at fixing #79369. Of course for #79369
a workaround can be to treat all `INT16` variants as `BFloat` in
`getOpFltSemantics`,
but it doesn't look good IMHO.
Since I'm fairly new to AMDGPU backend, I'd appreciate it if you can point out
where I don't understand correctly.
---
clang/lib/CodeGen/CGBuiltin.cpp | 4 -
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 8 +-
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 5 +-
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 71 ++
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 59 +++
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 2 +
.../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 7 ++
llvm/lib/Target/AMDGPU/SIDefines.h| 7 ++
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp| 8 ++
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 58 ---
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 22 +-
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp| 74 ---
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 15
llvm/lib/Target/AMDGPU/VOP3Instructions.td| 2 +-
.../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 36 -
llvm/test/MC/AMDGPU/bf16_imm.s| 10 +++
16 files changed, 323 insertions(+), 65 deletions(-)
create mode 100644 llvm/test/MC/AMDGPU/bf16_imm.s
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index a7a410dab1a018..daf651917f2a96 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -5908,8 +5908,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
}
}
-assert(ArgValue->getType()->canLosslesslyBitCastTo(PTy) &&
- "Must be able to losslessly bit cast to param");
// Cast vector type (e.g., v256i32) to x86_amx, this only happen
// in amx intrinsics.
if (PTy->isX86_AMXTy())
@@ -5939,8 +5937,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
}
}
- assert(V->getType()->canLosslesslyBitCastTo(RetTy) &&
- "Must be able to losslessly bit cast result type");
// Cast x86_amx to vector type (e.g., v256i32), this only happen
// in amx intrinsics.
if (V->getType()->isX86_AMXTy())
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 202fa4e8f4ea81..6795fb7aa0edb8 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 :
def int_amdgcn_fdot2_bf16_bf16 :
ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">,
DefaultAttrsIntrinsic<
-[llvm_i16_ty], // %r
+[llvm_bfloat_ty], // %r
[
- llvm_v2i16_ty, // %a
- llvm_v2i16_ty, // %b
- llvm_i16_ty// %c
+ llvm_v2bf16_ty, // %a
+ llvm_v2bf16_ty, // %b
+ llvm_bfloat_ty// %c
],
[IntrNoMem, IntrSpeculatable]
>;
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index c1d8e890a66edb..828229f3e569e3 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1562,8 +1562,9 @@ bool IRTranslator::translateBitCast(const User ,
bool IRTranslator::translateCast(unsigned Opcode, const User ,
MachineIRBuilder ) {
- if (U.getType()->getScalarType()->isBFloatTy() ||
- U.getOperand(0)->getType()->getScalarType()->isBFloatTy())
+ if (Opcode != TargetOpcode::G_BITCAST &&
+ (U.getType()->getScalarType()->isBFloatTy() ||
+ U.getOperand(0)->getType()->getScalarType()->isBFloatTy()))
return false;
Register Op = getOrCreateVReg(*U.getOperand(0));
Register Res = getOrCreateVReg(U);
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 79ad6ddf7861fc..09f25215beb9e5 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -475,6 +475,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isSSrcF64() const { return isSCSrc_b64() || isLiteralImm(MVT::f64); }
+ bool isSSrc_bf16() const { return isSCSrcB16() || isLiteralImm(MVT::bf16); }
+
bool isSSrc_f16() const { return
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
@@ -2660,15 +2660,34 @@ bool isInlinableLiteral16(int16_t Literal, bool
HasInv2Pi) {
return true;
uint16_t Val = static_cast(Literal);
- return Val == 0x3C00 || // 1.0
- Val == 0xBC00 || // -1.0
- Val == 0x3800 || // 0.5
- Val == 0xB800 || // -0.5
- Val == 0x4000 || // 2.0
- Val == 0xC000 || // -2.0
- Val == 0x4400 || // 4.0
- Val == 0xC400 || // -4.0
- Val == 0x3118; // 1/2pi
+
+ // FP16
+ if (Val == 0x3C00 || // 1.0
shiltian wrote:
This function might be removed eventually in
https://github.com/llvm/llvm-project/pull/81345.
https://github.com/llvm/llvm-project/pull/80908
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[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
@@ -2730,6 +2749,12 @@ std::optional getInlineEncodingV2I16(uint32_t
Literal) {
return getInlineEncodingV216(false, Literal);
}
+// Encoding of the literal as an inline constant for a V_PK_*_BF16 instruction
+// or nullopt.
+std::optional getInlineEncodingV2BF16(uint32_t Literal) {
+ return getInlineEncodingV216(true, Literal);
shiltian wrote:
This part is still WIP along with
https://github.com/llvm/llvm-project/pull/81345.
https://github.com/llvm/llvm-project/pull/80908
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[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian updated
https://github.com/llvm/llvm-project/pull/80908
>From 4196e998349d663a9a9922937cc4bedbec95fe5f Mon Sep 17 00:00:00 2001
From: Shilei Tian
Date: Mon, 12 Feb 2024 13:48:39 -0500
Subject: [PATCH] [RFC][WIP][AMDGPU] Use `bf16` instead of `i16` for bfloat
Currently it looks like we generally use `i16` to represent `bf16` in those
tablegen
files. I'm not sure of the reason behind it. My wild guess is the type `bf16`
was
not available when we enabled the support. This patch is trying to use `bf16`
directly in those tablegen files, aiming at fixing #79369. Of course for #79369
a workaround can be to treat all `INT16` variants as `BFloat` in
`getOpFltSemantics`,
but it doesn't look good IMHO.
Since I'm fairly new to AMDGPU backend, I'd appreciate it if you can point out
where I don't understand correctly.
---
clang/lib/CodeGen/CGBuiltin.cpp | 4 --
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 8 +--
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 5 +-
.../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 71 +++
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 59 +++
.../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 2 +
.../MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 7 ++
llvm/lib/Target/AMDGPU/SIDefines.h| 7 ++
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp| 8 +++
llvm/lib/Target/AMDGPU/SIInstrInfo.td | 58 ---
llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 22 +-
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp| 48 ++---
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 15
llvm/lib/Target/AMDGPU/VOP3Instructions.td| 2 +-
.../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 36 +-
llvm/test/MC/AMDGPU/bf16_imm.s| 8 +++
16 files changed, 295 insertions(+), 65 deletions(-)
create mode 100644 llvm/test/MC/AMDGPU/bf16_imm.s
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index a7a410dab1a018..daf651917f2a96 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -5908,8 +5908,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
}
}
-assert(ArgValue->getType()->canLosslesslyBitCastTo(PTy) &&
- "Must be able to losslessly bit cast to param");
// Cast vector type (e.g., v256i32) to x86_amx, this only happen
// in amx intrinsics.
if (PTy->isX86_AMXTy())
@@ -5939,8 +5937,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
}
}
- assert(V->getType()->canLosslesslyBitCastTo(RetTy) &&
- "Must be able to losslessly bit cast result type");
// Cast x86_amx to vector type (e.g., v256i32), this only happen
// in amx intrinsics.
if (V->getType()->isX86_AMXTy())
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index 202fa4e8f4ea81..6795fb7aa0edb8 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -2819,11 +2819,11 @@ def int_amdgcn_fdot2_f16_f16 :
def int_amdgcn_fdot2_bf16_bf16 :
ClangBuiltin<"__builtin_amdgcn_fdot2_bf16_bf16">,
DefaultAttrsIntrinsic<
-[llvm_i16_ty], // %r
+[llvm_bfloat_ty], // %r
[
- llvm_v2i16_ty, // %a
- llvm_v2i16_ty, // %b
- llvm_i16_ty// %c
+ llvm_v2bf16_ty, // %a
+ llvm_v2bf16_ty, // %b
+ llvm_bfloat_ty// %c
],
[IntrNoMem, IntrSpeculatable]
>;
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index c1d8e890a66edb..828229f3e569e3 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -1562,8 +1562,9 @@ bool IRTranslator::translateBitCast(const User ,
bool IRTranslator::translateCast(unsigned Opcode, const User ,
MachineIRBuilder ) {
- if (U.getType()->getScalarType()->isBFloatTy() ||
- U.getOperand(0)->getType()->getScalarType()->isBFloatTy())
+ if (Opcode != TargetOpcode::G_BITCAST &&
+ (U.getType()->getScalarType()->isBFloatTy() ||
+ U.getOperand(0)->getType()->getScalarType()->isBFloatTy()))
return false;
Register Op = getOrCreateVReg(*U.getOperand(0));
Register Res = getOrCreateVReg(U);
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index a94da992b33859..65d6fb587c19ca 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -475,6 +475,8 @@ class AMDGPUOperand : public MCParsedAsmOperand {
bool isSSrcF64() const { return isSCSrc_b64() || isLiteralImm(MVT::f64); }
+ bool isSSrc_bf16() const { return isSCSrcB16() || isLiteralImm(MVT::bf16); }
+
bool isSSrc_f16() const { return
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
@@ -79,17 +79,17 @@ define amdgpu_ps void @test_llvm_amdgcn_fdot2_bf16_bf16_sis( ; GFX11: ; %bb.0: ; %entry ; GFX11-NEXT:v_mov_b32_e32 v2, s1 ; GFX11-NEXT:s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT:v_dot2_bf16_bf16 v2, s0, 0x10001, v2 +; GFX11-NEXT:v_dot2_bf16_bf16 v2, s0, 0x3f803f80, v2 shiltian wrote: Yeah, but I tested the FP16 version `llvm.amdgcn.fdot2.f16.f16` (w/ trunk w/o my patch), it generates `v_dot2_f16_f16 v2, s0, 0x3c003c00, v2`. I think we generally have issues with showing inline literals. https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] LLVM] Add `__builtin_readfixedtimer` intrinsic and buiiltin for realtime clocks (PR #81331)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/81331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] LLVM] Add `__builtin_readfixedtimer` intrinsic and buiiltin for realtime clocks (PR #81331)
@@ -312,6 +312,12 @@ void IntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
CI->replaceAllUsesWith(ConstantInt::get(Type::getInt64Ty(Context), 0));
break;
}
+ case Intrinsic::readfixedtimer: {
+errs() << "WARNING: this target does not support the llvm.readfixedtimer"
+ << " intrinsic. It is being lowered to a constant 0\n";
+CI->replaceAllUsesWith(ConstantInt::get(Type::getInt64Ty(Context), 0));
shiltian wrote:
`Constant::getNullValue(Type::getInt64Ty(Context))`?
https://github.com/llvm/llvm-project/pull/81331
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[clang] [llvm] LLVM] Add `__builtin_readfixedtimer` intrinsic and buiiltin for realtime clocks (PR #81331)
https://github.com/shiltian commented: Generally looks good to me. Just not sure about the name. "fixed timer" sounds pretty confusing to me. probably `readfixedfreqtimer`? https://github.com/llvm/llvm-project/pull/81331 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
@@ -4181,13 +4181,20 @@ bool SIInstrInfo::isInlineConstant(const MachineOperand , case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16: return AMDGPU::isInlinableLiteralV2I16(Imm); + case AMDGPU::OPERAND_REG_IMM_V2BF16: shiltian wrote: Yeah, I made some mistakes here. Will take care of them. https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
@@ -5908,8 +5908,6 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } } -assert(ArgValue->getType()->canLosslesslyBitCastTo(PTy) && shiltian wrote: This change might need to go to a separate patch. https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
@@ -0,0 +1,8 @@ +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1100 -show-encoding %s | FileCheck %s +// RUN: llvm-mc -arch=amdgcn -mcpu=gfx1200 -show-encoding %s | FileCheck %s + +v_dot2_bf16_bf16 v5, v1, v2, 100.0 shiltian wrote: The two instructions are from #79369 https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian ready_for_review https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
[clang] [llvm] [RFC][AMDGPU] Use `bf16` instead of `i16` for bfloat (PR #80908)
https://github.com/shiltian edited https://github.com/llvm/llvm-project/pull/80908 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
