[PATCH] D120305: [Driver] Default CLANG_DEFAULT_PIE_ON_LINUX to ON

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

In D120305#3337045 , @atanasyan wrote:

> In D120305#3337019 , @MaskRay wrote:
>
>> @atanasyan A few mips test/Driver tests will fail. Wonder if you have time 
>> making them more portable... Otherwise I'll just add `UNSUPPORTED: 
>> default-pie-on-linux` to them.
>>
>>   Failed Tests (6):
>> Clang :: Driver/hip-fpie-option.hip
>> Clang :: Driver/mips-cs.cpp
>> Clang :: Driver/mips-fsf.cpp
>> Clang :: Driver/mips-img-v2.cpp
>> Clang :: Driver/mips-img.cpp
>> Clang :: Driver/mips-mti-linux.c
>
> I will take a look at the tests. Probably `hip-fpie-option.hip` is unrelated 
> to MIPS?

Fixed MIPS tests at cedc23b 



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[PATCH] D120305: [Driver] Default CLANG_DEFAULT_PIE_ON_LINUX to ON

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

In D120305#3337019 , @MaskRay wrote:

> @atanasyan A few mips test/Driver tests will fail. Wonder if you have time 
> making them more portable... Otherwise I'll just add `UNSUPPORTED: 
> default-pie-on-linux` to them.
>
>   Failed Tests (6):
> Clang :: Driver/hip-fpie-option.hip
> Clang :: Driver/mips-cs.cpp
> Clang :: Driver/mips-fsf.cpp
> Clang :: Driver/mips-img-v2.cpp
> Clang :: Driver/mips-img.cpp
> Clang :: Driver/mips-mti-linux.c

I will take a look at the tests. Probably `hip-fpie-option.hip` is unrelated to 
MIPS?


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[PATCH] D116238: [mips] Add -mfix4300 flag to enable vr4300 mulmul bugfix pass

[Simon Atanasyan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG2edcde00cb39: [MIPS] Add -mfix4300 flag to enable vr4300 
mulmul bugfix pass (authored by Random06457, committed by atanasyan).

Changed prior to commit:
  https://reviews.llvm.org/D116238?vs=396171=396774#toc

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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  llvm/lib/Target/Mips/CMakeLists.txt
  llvm/lib/Target/Mips/Mips.h
  llvm/lib/Target/Mips/MipsMulMulBugPass.cpp
  llvm/lib/Target/Mips/MipsTargetMachine.cpp
  llvm/test/CodeGen/Mips/vr4300-mulbranch.ll
  llvm/test/CodeGen/Mips/vr4300-mulmul.ll

Index: llvm/test/CodeGen/Mips/vr4300-mulmul.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Mips/vr4300-mulmul.ll
@@ -0,0 +1,24 @@
+; RUN: llc -march=mips -mfix4300 -verify-machineinstrs < %s | FileCheck %s
+
+; Function Attrs: mustprogress nofree norecurse nosync nounwind readnone willreturn
+define dso_local float @fun_s(float %x) local_unnamed_addr #0 {
+entry:
+; CHECK-LABEL: fun_s
+; CHECK: mul.s
+; CHECK-NEXT: nop
+; CHECK: mul.s
+  %mul = fmul float %x, %x
+  %mul1 = fmul float %mul, %x
+  ret float %mul1
+}
+
+define dso_local double @fun_d(double %x) local_unnamed_addr #0 {
+entry:
+; CHECK-LABEL: fun_d
+; CHECK: mul.d
+; CHECK-NEXT: nop
+; CHECK: mul.d
+  %mul = fmul double %x, %x
+  %mul1 = fmul double %mul, %x
+  ret double %mul1
+}
Index: llvm/test/CodeGen/Mips/vr4300-mulbranch.ll
===
--- /dev/null
+++ llvm/test/CodeGen/Mips/vr4300-mulbranch.ll
@@ -0,0 +1,27 @@
+; RUN: llc -march=mips -mfix4300 -verify-machineinstrs < %s | FileCheck %s
+
+; Function Attrs: nounwind
+define dso_local void @fun_s(float %a) local_unnamed_addr #0 {
+entry:
+; CHECK-LABEL: fun_s
+; CHECK: mul.s
+; CHECK-NEXT: nop
+  %mul = fmul float %a, %a
+  tail call void @foo_s(float %mul) #2
+  ret void
+}
+
+declare dso_local void @foo_s(float) local_unnamed_addr #1
+
+; Function Attrs: nounwind
+define dso_local void @fun_d(double %a) local_unnamed_addr #0 {
+entry:
+; CHECK-LABEL: fun_d
+; CHECK: mul.d
+; CHECK-NEXT: nop
+  %mul = fmul double %a, %a
+  tail call void @foo_d(double %mul) #2
+  ret void
+}
+
+declare dso_local void @foo_d(double) local_unnamed_addr #1
Index: llvm/lib/Target/Mips/MipsTargetMachine.cpp
===
--- llvm/lib/Target/Mips/MipsTargetMachine.cpp
+++ llvm/lib/Target/Mips/MipsTargetMachine.cpp
@@ -45,6 +45,10 @@
 
 #define DEBUG_TYPE "mips"
 
+static cl::opt
+EnableMulMulFix("mfix4300", cl::init(false),
+cl::desc("Enable the VR4300 mulmul bug fix."), cl::Hidden);
+
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeMipsTarget() {
   // Register the target.
   RegisterTargetMachine X(getTheMipsTarget());
@@ -58,6 +62,7 @@
   initializeMipsBranchExpansionPass(*PR);
   initializeMicroMipsSizeReducePass(*PR);
   initializeMipsPreLegalizerCombinerPass(*PR);
+  initializeMipsMulMulBugFixPass(*PR);
 }
 
 static std::string computeDataLayout(const Triple , StringRef CPU,
@@ -292,6 +297,11 @@
   // instructions which can be remapped to a 16 bit instruction.
   addPass(createMicroMipsSizeReducePass());
 
+  // This pass inserts a nop instruction between two back-to-back multiplication
+  // instructions when the "mfix4300" flag is passed.
+  if (EnableMulMulFix)
+addPass(createMipsMulMulBugPass());
+
   // The delay slot filler pass can potientially create forbidden slot hazards
   // for MIPSR6 and therefore it should go before MipsBranchExpansion pass.
   addPass(createMipsDelaySlotFillerPass());
Index: llvm/lib/Target/Mips/MipsMulMulBugPass.cpp
===
--- /dev/null
+++ llvm/lib/Target/Mips/MipsMulMulBugPass.cpp
@@ -0,0 +1,134 @@
+//===- MipsMulMulBugPass.cpp - Mips VR4300 mulmul bugfix pass -===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===--===//
+//
+// Early revisions of the VR4300 have a hardware bug where two consecutive
+// multiplications can produce an incorrect result in the second multiply.
+//
+// This pass scans for mul instructions in each basic block and inserts
+// a nop whenever the following conditions are met:
+//
+// - The current instruction is a single or double-precision floating-point
+//   mul instruction.
+// - The next instruction is either a mul instruction (any kind)
+//   or a branch instruction.

[PATCH] D116238: [mips] Add -mfix4300 flag to enable vr4300 mulmul bugfix pass

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks for the patch.


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[PATCH] D116238: [mips] Add -mfix4300 flag to enable vr4300 mulmul bugfix pass

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan requested changes to this revision.
atanasyan added a comment.
This revision now requires changes to proceed.

Thanks for the patch. Some notes are below.




Comment at: llvm/lib/Target/Mips/MipsMulMulBugPass.cpp:16
+static cl::opt
+EnableMulMulFix("mfix4300", cl::init(false),
+cl::desc("Enable the VR4300 mulmul bug fix."), cl::Hidden);

We can move this option to the `MipsTargetMachine.cpp` and just do not add the 
pass when it is not necessary.



Comment at: llvm/lib/Target/Mips/MipsMulMulBugPass.cpp:19
+
+class MipsMulMulBugFix : public MachineFunctionPass {
+public:

Put this class into an anonymous namespace to reduce work for a linker.



Comment at: llvm/lib/Target/Mips/MipsMulMulBugPass.cpp:31
+  bool runOnMachineFunction(MachineFunction ) override;
+  bool FixMulMulBB(MachineBasicBlock );
+

Let's rename the function to the `fixMulMulBB` and move it to the `private` 
section of the class.



Comment at: llvm/lib/Target/Mips/MipsMulMulBugPass.cpp:36
+private:
+  static const MipsInstrInfo *MipsII;
+  const MipsSubtarget *Subtarget;

I do not think it's a good idea to save `MipsInstrInfo` into the **static** 
field. AFAIK now passes cannot be run in parallel. But if that changes in the 
future we get a problem with the static field. As to me I would get a reference 
to the `MipsInstrInfo` in the `runOnMachineFunction` and pass this reference to 
the `FixMulMulBB` as a parameter.



Comment at: llvm/lib/Target/Mips/MipsMulMulBugPass.cpp:37
+  static const MipsInstrInfo *MipsII;
+  const MipsSubtarget *Subtarget;
+};

Do you really need to keep a pointer to the `Subtarget` in the object?



Comment at: llvm/lib/Target/Mips/MipsMulMulBugPass.cpp:48-49
+
+  Subtarget = _cast(MF.getSubtarget());
+  MipsII = static_cast(Subtarget->getInstrInfo());
+

These lines can be merged into the single one:
```
MipsII = MF.getSubtarget().getInstrInfo();
```



Comment at: llvm/lib/Target/Mips/MipsMulMulBugPass.cpp:52-55
+  MachineFunction::iterator I = MF.begin(), E = MF.end();
+
+  for (; I != E; ++I)
+Modified |= FixMulMulBB(*I);

This code can be made a bit more compact:
```
for (auto : MF)
  Modified |= FixMulMulBB(MBB);
```



Comment at: llvm/lib/Target/Mips/MipsMulMulBugPass.cpp:60
+
+static bool isFirstMul(const MachineInstr *MI) {
+  switch (MI->getOpcode()) {

This function does not work with null pointer so change the argument's type to 
a reference.



Comment at: llvm/lib/Target/Mips/MipsMulMulBugPass.cpp:73
+
+static bool isSecondMulOrBranch(const MachineInstr *MI) {
+  if (MI->isBranch() || MI->isIndirectBranch() || MI->isCall())

Ditto



Comment at: llvm/lib/Target/Mips/MipsMulMulBugPass.cpp:95-103
+  MachineBasicBlock::instr_iterator MII = MBB.instr_begin(),
+E = MBB.instr_end();
+  MachineBasicBlock::instr_iterator NextMII;
+
+  // Iterate through the instructions in the basic block
+  for (; MII != E; MII = NextMII) {
+

`std::next` call and the iterator incrementation are cheap calls. So we can 
write the loop in a more idiomatic form:
```
for (MachineBasicBlock::instr_iterator MII = MBB.instr_begin(),
   E = MBB.instr_end();
 MII != E; ++MII) {
  MachineBasicBlock::instr_iterator NextMII = std::next(MII);
...
```



Comment at: llvm/lib/Target/Mips/MipsMulMulBugPass.cpp:110
+
+  MachineBasicBlock  = *MI->getParent();
+  const MCInstrDesc  = MipsII->get(Mips::NOP);

You do not need a new `MBB` variable. Use `MBB` passed as an argument to the 
`FixMulMulBB`.


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[PATCH] D112158: mips: fix search path for multilib o32

[Simon Atanasyan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG284c2ebc5e05: [clang][MIPS] Fix search path for Debian 
multilib O32 (authored by wzssyqa, committed by atanasyan).

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Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/lib/Driver/ToolChains/Linux.cpp
  clang/test/Driver/Inputs/debian_6_mips64_tree/libo32/.keep
  
clang/test/Driver/Inputs/debian_6_mips64_tree/usr/lib/gcc/mips64-linux-gnuabi64/4.9/32/crtbegin.o
  
clang/test/Driver/Inputs/debian_6_mips64_tree/usr/lib/gcc/mips64-linux-gnuabi64/4.9/32/crtend.o
  
clang/test/Driver/Inputs/debian_6_mips64_tree/usr/lib/gcc/mips64-linux-gnuabi64/4.9/n32/crtbegin.o
  
clang/test/Driver/Inputs/debian_6_mips64_tree/usr/lib/gcc/mips64-linux-gnuabi64/4.9/n32/crtend.o
  
clang/test/Driver/Inputs/debian_6_mips64_tree/usr/lib/gcc/mips64el-linux-gnuabi64/4.9/32/crtbegin.o
  
clang/test/Driver/Inputs/debian_6_mips64_tree/usr/lib/gcc/mips64el-linux-gnuabi64/4.9/32/crtend.o
  
clang/test/Driver/Inputs/debian_6_mips64_tree/usr/lib/gcc/mips64el-linux-gnuabi64/4.9/n32/crtbegin.o
  
clang/test/Driver/Inputs/debian_6_mips64_tree/usr/lib/gcc/mips64el-linux-gnuabi64/4.9/n32/crtend.o
  clang/test/Driver/Inputs/debian_6_mips64_tree/usr/libo32/crt1.o
  clang/test/Driver/Inputs/debian_6_mips64_tree/usr/libo32/crti.o
  clang/test/Driver/Inputs/debian_6_mips64_tree/usr/libo32/crtn.o
  clang/test/Driver/linux-ld.c


Index: clang/test/Driver/linux-ld.c
===
--- clang/test/Driver/linux-ld.c
+++ clang/test/Driver/linux-ld.c
@@ -1039,7 +1039,6 @@
 // CHECK-SPARCV9: "-m" "elf64_sparc"
 // CHECK-SPARCV9: "-dynamic-linker" 
"{{(/usr/sparcv9-unknown-linux-gnu)?}}/lib{{(64)?}}/ld-linux.so.2"
 
-
 // Test linker invocation on Android.
 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
 // RUN: --target=arm-linux-androideabi -rtlib=platform 
--unwindlib=platform \
@@ -1455,6 +1454,22 @@
 // CHECK-DEBIAN-ML-MIPS64EL-N32: "-L[[SYSROOT]]/usr/lib"
 //
 // RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
+// RUN: --target=mips64el-linux-gnuabi64 -rtlib=platform -mabi=32 \
+// RUN: --gcc-toolchain="" \
+// RUN: --sysroot=%S/Inputs/debian_6_mips64_tree \
+// RUN:   | FileCheck --check-prefix=CHECK-DEBIAN-ML-MIPS64EL-O32 %s
+// CHECK-DEBIAN-ML-MIPS64EL-O32: "{{.*}}ld{{(.exe)?}}" 
"--sysroot=[[SYSROOT:[^"]+]]"
+// CHECK-DEBIAN-ML-MIPS64EL-O32: 
"{{.*}}/usr/lib/gcc/mips64el-linux-gnuabi64/4.9/../../../../libo32{{/|}}crt1.o"
+// CHECK-DEBIAN-ML-MIPS64EL-O32: 
"{{.*}}/usr/lib/gcc/mips64el-linux-gnuabi64/4.9/../../../../libo32{{/|}}crti.o"
+// CHECK-DEBIAN-ML-MIPS64EL-O32: 
"{{.*}}/usr/lib/gcc/mips64el-linux-gnuabi64/4.9/32{{/|}}crtbegin.o"
+// CHECK-DEBIAN-ML-MIPS64EL-O32: 
"-L[[SYSROOT]]/usr/lib/gcc/mips64el-linux-gnuabi64/4.9/32"
+// CHECK-DEBIAN-ML-MIPS64EL-O32: 
"-L[[SYSROOT]]/usr/lib/gcc/mips64el-linux-gnuabi64/4.9/../../../../libo32"
+// CHECK-DEBIAN-ML-MIPS64EL-O32: "-L[[SYSROOT]]/libo32"
+// CHECK-DEBIAN-ML-MIPS64EL-O32: "-L[[SYSROOT]]/usr/libo32"
+// CHECK-DEBIAN-ML-MIPS64EL-O32: "-L[[SYSROOT]]/lib"
+// CHECK-DEBIAN-ML-MIPS64EL-O32: "-L[[SYSROOT]]/usr/lib"
+//
+// RUN: %clang -no-canonical-prefixes %s -### -o %t.o 2>&1 \
 // RUN: --target=mips64-unknown-linux-gnu --rtlib=platform \
 // RUN: --gcc-toolchain="" \
 // RUN: --sysroot=%S/Inputs/debian_6_mips64_tree \
Index: clang/lib/Driver/ToolChains/Linux.cpp
===
--- clang/lib/Driver/ToolChains/Linux.cpp
+++ clang/lib/Driver/ToolChains/Linux.cpp
@@ -261,6 +261,13 @@
   const std::string OSLibDir = std::string(getOSLibDir(Triple, Args));
   const std::string MultiarchTriple = getMultiarchTriple(D, Triple, SysRoot);
 
+  // mips32: Debian multilib, we use /libo32, while in other case, /lib is
+  // used. We need add both libo32 and /lib.
+  if (Arch == llvm::Triple::mips || Arch == llvm::Triple::mipsel) {
+Generic_GCC::AddMultilibPaths(D, SysRoot, "libo32", MultiarchTriple, 
Paths);
+addPathIfExists(D, SysRoot + "/libo32", Paths);
+addPathIfExists(D, SysRoot + "/usr/libo32", Paths);
+  }
   Generic_GCC::AddMultilibPaths(D, SysRoot, OSLibDir, MultiarchTriple, Paths);
 
   addPathIfExists(D, SysRoot + "/lib/" + MultiarchTriple, Paths);
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -1081,7 +1081,8 @@
.flag("-m32")
.flag("-mabi=n32");
 
-Multilib M32 = Multilib().flag("-m64").flag("+m32").flag("-mabi=n32");
+Multilib M32 =
+
Multilib().gccSuffix("/32").flag("-m64").flag("+m32").flag("-mabi=n32");
 
 DebianMipsMultilibs =
 MultilibSet().Either(M32, M64, 

[PATCH] D112158: mips: fix search path for multilib o32

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D112158: mips: fix search path for multilib o32

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

- Does this problem exist on all versions of Debian or starting from specific 
version only?
- This fix needs test cases. Take a look at "Check linker invocation on Debian 
6 MIPS 32/64-bit" in the `clang/test/Driver/linux-ld.c` for example.


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[PATCH] D80392: [mips][mc][clang] Use pc-relative relocations in .eh_frame

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan updated this revision to Diff 367472.
atanasyan retitled this revision from "[WIP][mips] Use pc-relative relocations 
in .eh_frame" to "[mips][mc][clang] Use pc-relative relocations in .eh_frame".
atanasyan edited the summary of this revision.
atanasyan edited reviewers, added: emaste, grosbach; removed: sdardis, 
dsanders, espindola.
atanasyan added a project: clang.
atanasyan added a comment.
Herald added subscribers: cfe-commits, dang, sdardis.

For compatibility with tools unsupported 64-bit pc-relative relocations the 
patch introduces new command line options in Clang: `mmips-pc64-rel` and 
`mno-mips-pc64-rel`. These options passed to LLVM by Clang driver as 
`-mmips-pc64-rel={true|false}`. I could not find any better way to pass the 
option into `MC` layer.


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Files:
  clang/include/clang/Driver/Options.td
  clang/lib/Driver/ToolChains/Clang.cpp
  clang/test/Driver/mips-features.c
  lld/test/ELF/mips-eh_frame-pic.s
  llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
  llvm/lib/MC/MCObjectFileInfo.cpp
  llvm/test/CodeGen/Mips/ehframe-indirect.ll
  llvm/test/DebugInfo/Mips/eh_frame.ll
  llvm/test/MC/Mips/eh-frame.s

Index: llvm/test/MC/Mips/eh-frame.s
===
--- llvm/test/MC/Mips/eh-frame.s
+++ llvm/test/MC/Mips/eh-frame.s
@@ -33,14 +33,18 @@
 // RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,PIC64 %s
 // RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_PIC %s
 
-/// However using the large code model forces R_MIPS_64 since there is no R_MIPS_PC64 relocation:
 // RUN: llvm-mc -filetype=obj %s -o %t.o -triple mips64-unknown-linux-gnu --position-independent --large-code-model
-// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,ABS64 %s
-// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_ABS %s
+// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,PIC64 %s
+// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_PIC %s
 
 // RUN: llvm-mc -filetype=obj %s -o %t.o -triple mips64el-unknown-linux-gnu --position-independent  --large-code-model
-// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,ABS64 %s
-// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_ABS %s
+// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,PIC64 %s
+// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_PIC %s
+
+// RUN: llvm-mc -filetype=obj %s -o %t.o -triple mips64-unknown-linux-gnu \
+// RUN: --position-independent --large-code-model -mmips-pc64-rel=false
+// RUN: llvm-readobj -r %t.o | FileCheck --check-prefixes=RELOCS,OLD64 %s
+// RUN: llvm-dwarfdump -eh-frame %t.o | FileCheck --check-prefixes=DWARF64,DWARF64_OLD %s
 
 func:
 	.cfi_startproc
@@ -51,7 +55,8 @@
 // ABS32-NEXT:  R_MIPS_32
 // ABS64-NEXT:  R_MIPS_64/R_MIPS_NONE/R_MIPS_NONE
 // PIC32-NEXT:  R_MIPS_PC32
-// PIC64-NEXT:  R_MIPS_PC32/R_MIPS_NONE/R_MIPS_NONE
+// PIC64-NEXT:  R_MIPS_PC32/R_MIPS_64/R_MIPS_NONE
+// OLD64-NEXT:  R_MIPS_64/R_MIPS_NONE/R_MIPS_NONE
 // RELOCS-NEXT:   }
 
 // DWARF32:  0010  CIE
@@ -87,14 +92,17 @@
 // DWARF64-NEXT: Return address column: 31
 // DWARF64_ABS-NEXT: Augmentation data: 0C
 //  ^^ fde pointer encoding: DW_EH_PE_sdata8
-// DWARF64_PIC:  Augmentation data: 1B
-//  ^^ fde pointer encoding: DW_EH_PE_pcrel | DW_EH_PE_sdata4
+// DWARF64_PIC:  Augmentation data: 1C
+//  ^^ fde pointer encoding: DW_EH_PE_pcrel | DW_EH_PE_sdata8
+// DWARF64_OLD:  Augmentation data: 0C
+//  ^^ fde pointer encoding: DW_EH_PE_sdata8
 // DWARF64-EMPTY:
 // DWARF64-NEXT: DW_CFA_def_cfa_register: SP_64
 // DWARF64_PIC-NEXT: DW_CFA_nop:
 //
 // DWARF64_ABS:  0014 0018 0018 FDE cie= pc=...
-// DWARF64_PIC:  0014 0010 0018 FDE cie= pc=...
+// DWARF64_PIC:  0014 0018 0018 FDE cie= pc=001c...001c
+// DWARF64_OLD:  0014 0018 0018 FDE cie= pc=...
 // DWARF64-NEXT: Format:   DWARF32
 // DWARF64-NEXT: DW_CFA_nop:
 // DWARF64-NEXT: DW_CFA_nop:
Index: llvm/test/DebugInfo/Mips/eh_frame.ll
===
--- llvm/test/DebugInfo/Mips/eh_frame.ll
+++ llvm/test/DebugInfo/Mips/eh_frame.ll
@@ -17,9 +17,9 @@
 ; STATIC-DAG: R_MIPS_32  .gcc_except_table
 
 ; PIC-LABEL: Relocation section '.rel.eh_frame'
-; PIC-DAG: R_MIPS_32    DW.ref.__gxx_personality_v0
+; PIC-DAG: R_MIPS_PC32  DW.ref.__gxx_personality_v0
+; 

[PATCH] D99996: [Driver] Drop $DEFAULT_TRIPLE-$name as a fallback program name

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM

AFAIK the MIPS LLVM-based toolchain mentioned in D13340 
 have not been implemented.


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[PATCH] D90570: [mips] Add a -mmips3d command line option to clang

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

My bad, I missed that you implemented passing the option to backend.

Could you add some improvements to the patch?

1. As far as I know GCC does not accept `-mmips3d` option. It uses `-mips3d`. 
We need do the same.

2. Add test cases. For the reference you might take a look at the -mdspr2 
option in the following tests:

  test/Driver/mips-as.c
  test/Driver/mips-features.c
  test/Driver/mips-integrated-as.c

3. GCC defines `#define __mips3d 1` macro when the `-mips3d` option is 
provided. Take a look at the `MipsTargetInfo::getTargetDefines()` as a point 
for implementation.

4. As far as I remember MIPS 3D requires 64-bit floating-point registers. We 
need to check that 64-bit is enabled and show an error otherwise like GCC does.

3 and 4 need test cases.


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[PATCH] D90570: [mips] Add a -mmips3d command line option to clang

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

What's a goal of this change? Do you want to suppress an error message when the 
option provided to Clang? If so, is it a real-life case?


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[PATCH] D80421: [Mips] use correct ld.so for musl soft float

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a reviewer: atanasyan.
atanasyan added a comment.

1. Please include as much context as possible with your diff. This instruction 

 helps to do that.
2. Such patch needs test case(s). Maybe it's enough to update the `linux-ld.c` 
test case which is failed now. Update failed cases and check both "soft" and 
"hard" float cases in this test.


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[PATCH] D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

Looking good to me as-is.

- Current naming is okay. But what do you think about reducing name of 
//quarter// intrinsics: `__builtin_msa_ldr_w` instead of 
`__builtin_msa_ldrq_w`? Will it clash with any future intrinsics' names?
- There is almost no documentation on target specific intrinsics. Some articles 
like Using ARM NEON instructions in big endian mode 
 cover specific use cases. It's up to 
you to write an article for these new intrinsics.


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[PATCH] D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

I see, thanks. Is there the same or similar functionality in GCC?


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[PATCH] D73644: [Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Is it possible to emulate these new intrinsics using existing ones and some 
additional code? Is code generated in this case much larger/slower then the 
code generated by the new intrinsics?


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[PATCH] D73108: [docs][mips] 10.0 Release notes

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan closed this revision.
atanasyan added a comment.

Closed by commit rG27f93515 
.


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[PATCH] D73108: [docs][mips] 10.0 Release notes

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan updated this revision to Diff 239333.
atanasyan added a reviewer: mbrkusanin.
atanasyan added a comment.

- Add `llvm-exegesis` note.


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Files:
  clang/docs/ReleaseNotes.rst
  lld/docs/ReleaseNotes.rst
  llvm/docs/ReleaseNotes.rst


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -122,8 +122,22 @@
 Changes to the MIPS Target
 --
 
- During this release ...
-
+* Improved support for ``octeon`` and added support for ``octeon+``
+  MIPS-family CPU.
+* ``min``, ``max``, ``umin``, ``umax`` atomics now supported on MIPS targets.
+* Now PC-relative relocations are generated for ``.eh_frame`` sections when
+  possible. That allows to link MIPS binaries without having to pass the
+  ``-Wl,-z,notext`` option.
+* Fix evaluating J-format branch (``j``, ``jal``, ...) targets when the
+  instruction is not in the first 256 MB region.
+* Fixed ``jal``, ``sc``, ``scs``, ``ll``, ``lld``, ``la``, ``lw``, ``sw``
+  instructions expanding. Now they accept more types of expression as 
arguments,
+  correctly handle load/store for ``XGOT`` model, expand using less 
instructions
+  or registers.
+* Initial MIPS support has been added to ``llvm-exegesis``.
+* Generates ``_mcount`` calls using proper MIPS ABI.
+* Improved support of GlobalISel instruction selection framework. This feature
+  is still in experimental state for MIPS targets though.
 
 Changes to the PowerPC Target
 -
Index: lld/docs/ReleaseNotes.rst
===
--- lld/docs/ReleaseNotes.rst
+++ lld/docs/ReleaseNotes.rst
@@ -30,6 +30,14 @@
   with GNU now. (`r375051
   
`_)
 
+* New ``elf32btsmipn32_fbsd`` and ``elf32ltsmipn32_fbsd`` emulations
+  are supported.
+
+* Relax MIPS ``jalr``and ``jr`` instructions marked by the ``R_MIPS_JALR``
+  relocation.
+
+* Reduced size of linked MIPS binaries.
+
 COFF Improvements
 -
 
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -111,6 +111,9 @@
   In a future release of Clang, we intend to change the default to
   ``-fno-lax-vector-conversions``.
 
+* Improved support for ``octeon`` MIPS-family CPU. Added ``octeon+`` to
+  the list of of CPUs accepted by the driver.
+
 New Compiler Flags
 --
 


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -122,8 +122,22 @@
 Changes to the MIPS Target
 --
 
- During this release ...
-
+* Improved support for ``octeon`` and added support for ``octeon+``
+  MIPS-family CPU.
+* ``min``, ``max``, ``umin``, ``umax`` atomics now supported on MIPS targets.
+* Now PC-relative relocations are generated for ``.eh_frame`` sections when
+  possible. That allows to link MIPS binaries without having to pass the
+  ``-Wl,-z,notext`` option.
+* Fix evaluating J-format branch (``j``, ``jal``, ...) targets when the
+  instruction is not in the first 256 MB region.
+* Fixed ``jal``, ``sc``, ``scs``, ``ll``, ``lld``, ``la``, ``lw``, ``sw``
+  instructions expanding. Now they accept more types of expression as arguments,
+  correctly handle load/store for ``XGOT`` model, expand using less instructions
+  or registers.
+* Initial MIPS support has been added to ``llvm-exegesis``.
+* Generates ``_mcount`` calls using proper MIPS ABI.
+* Improved support of GlobalISel instruction selection framework. This feature
+  is still in experimental state for MIPS targets though.
 
 Changes to the PowerPC Target
 -
Index: lld/docs/ReleaseNotes.rst
===
--- lld/docs/ReleaseNotes.rst
+++ lld/docs/ReleaseNotes.rst
@@ -30,6 +30,14 @@
   with GNU now. (`r375051
   `_)
 
+* New ``elf32btsmipn32_fbsd`` and ``elf32ltsmipn32_fbsd`` emulations
+  are supported.
+
+* Relax MIPS ``jalr``and ``jr`` instructions marked by the ``R_MIPS_JALR``
+  relocation.
+
+* Reduced size of linked MIPS binaries.
+
 COFF Improvements
 -
 
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -111,6 +111,9 @@
   In a future release of Clang, we intend to change the default to
   ``-fno-lax-vector-conversions``.
 
+* Improved support for ``octeon`` MIPS-family CPU. Added ``octeon+`` to
+  the list of of CPUs 

[PATCH] D73108: [docs][mips] 10.0 Release notes

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

In D73108#1831442 , @mstojanovic wrote:

> Initial MIPS support was also added to `llvm-exegesis`.


Oh, sorry. Good point, I'll add this note.


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[PATCH] D73108: [docs][mips] 10.0 Release notes

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan created this revision.
atanasyan added reviewers: hans, ruiu, Petar.Avramovic, mstojanovic, 
arichardson.
Herald added subscribers: jfb, sdardis.
Herald added projects: clang, LLVM.

MIPS specific part of LLVM 10.0 Release notes for LLVM, Clang and LLD.


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Files:
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  lld/docs/ReleaseNotes.rst
  llvm/docs/ReleaseNotes.rst


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -122,8 +122,21 @@
 Changes to the MIPS Target
 --
 
- During this release ...
-
+* Improved support for ``octeon`` and added support for ``octeon+``
+  MIPS-family CPU.
+* ``min``, ``max``, ``umin``, ``umax`` atomics now supported on MIPS targets.
+* Now PC-relative relocations are generated for ``.eh_frame`` sections when
+  possible. That allows to link MIPS binaries without having to pass the
+  ``-Wl,-z,notext`` option.
+* Fix evaluating J-format branch (``j``, ``jal``, ...) targets when the
+  instruction is not in the first 256 MB region.
+* Fixed ``jal``, ``sc``, ``scs``, ``ll``, ``lld``, ``la``, ``lw``, ``sw``
+  instructions expanding. Now they accept more types of expression as 
arguments,
+  correctly handle load/store for ``XGOT`` model, expand using less 
instructions
+  or registers.
+* Generates ``_mcount`` calls using proper MIPS ABI.
+* Improved support of GlobalISel instruction selection framework. This feature
+  is still in experimental state for MIPS targets though.
 
 Changes to the PowerPC Target
 -
Index: lld/docs/ReleaseNotes.rst
===
--- lld/docs/ReleaseNotes.rst
+++ lld/docs/ReleaseNotes.rst
@@ -30,6 +30,14 @@
   with GNU now. (`r375051
   
`_)
 
+* New ``elf32btsmipn32_fbsd`` and ``elf32ltsmipn32_fbsd`` emulations
+  are supported.
+
+* Relax MIPS ``jalr``and ``jr`` instructions marked by the ``R_MIPS_JALR``
+  relocation.
+
+* Reduced size of linked MIPS binaries.
+
 COFF Improvements
 -
 
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -111,6 +111,9 @@
   In a future release of Clang, we intend to change the default to
   ``-fno-lax-vector-conversions``.
 
+* Improved support for ``octeon`` MIPS-family CPU. Added ``octeon+`` to
+  the list of of CPUs accepted by the driver.
+
 New Compiler Flags
 --
 


Index: llvm/docs/ReleaseNotes.rst
===
--- llvm/docs/ReleaseNotes.rst
+++ llvm/docs/ReleaseNotes.rst
@@ -122,8 +122,21 @@
 Changes to the MIPS Target
 --
 
- During this release ...
-
+* Improved support for ``octeon`` and added support for ``octeon+``
+  MIPS-family CPU.
+* ``min``, ``max``, ``umin``, ``umax`` atomics now supported on MIPS targets.
+* Now PC-relative relocations are generated for ``.eh_frame`` sections when
+  possible. That allows to link MIPS binaries without having to pass the
+  ``-Wl,-z,notext`` option.
+* Fix evaluating J-format branch (``j``, ``jal``, ...) targets when the
+  instruction is not in the first 256 MB region.
+* Fixed ``jal``, ``sc``, ``scs``, ``ll``, ``lld``, ``la``, ``lw``, ``sw``
+  instructions expanding. Now they accept more types of expression as arguments,
+  correctly handle load/store for ``XGOT`` model, expand using less instructions
+  or registers.
+* Generates ``_mcount`` calls using proper MIPS ABI.
+* Improved support of GlobalISel instruction selection framework. This feature
+  is still in experimental state for MIPS targets though.
 
 Changes to the PowerPC Target
 -
Index: lld/docs/ReleaseNotes.rst
===
--- lld/docs/ReleaseNotes.rst
+++ lld/docs/ReleaseNotes.rst
@@ -30,6 +30,14 @@
   with GNU now. (`r375051
   `_)
 
+* New ``elf32btsmipn32_fbsd`` and ``elf32ltsmipn32_fbsd`` emulations
+  are supported.
+
+* Relax MIPS ``jalr``and ``jr`` instructions marked by the ``R_MIPS_JALR``
+  relocation.
+
+* Reduced size of linked MIPS binaries.
+
 COFF Improvements
 -
 
Index: clang/docs/ReleaseNotes.rst
===
--- clang/docs/ReleaseNotes.rst
+++ clang/docs/ReleaseNotes.rst
@@ -111,6 +111,9 @@
   In a future release of Clang, we intend to change the default to
   ``-fno-lax-vector-conversions``.
 
+* Improved support for ``octeon`` MIPS-family CPU. Added ``octeon+`` to
+  the list of of CPUs accepted by the driver.
+
 New Compiler Flags
 --
 

[PATCH] D70808: [mips] Check that features required by built-ins are enabled

[Simon Atanasyan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGf4d32ae75bf5: [mips] Check that features required by 
built-ins are enabled (authored by atanasyan).

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Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/Mips.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-mips-args.c
  clang/test/CodeGen/builtins-mips.c
  clang/test/Sema/builtins-mips-features.c

Index: clang/test/Sema/builtins-mips-features.c
===
--- /dev/null
+++ clang/test/Sema/builtins-mips-features.c
@@ -0,0 +1,37 @@
+// REQUIRES: mips-registered-target
+// RUN: %clang_cc1 -triple mips64 -fsyntax-only -verify %s
+
+typedef signed char v4i8 __attribute__ ((vector_size(4)));
+typedef signed char v4q7 __attribute__ ((vector_size(4)));
+typedef signed char v16i8 __attribute__((vector_size(16), aligned(16)));
+typedef unsigned char v16u8 __attribute__((vector_size(16), aligned(16)));
+
+void dsp() {
+  v4i8 a;
+  void* p;
+
+  // expected-error@+1 {{this builtin requires 'dsp' ASE, please use -mdsp}}
+  __builtin_mips_addu_qb(a, a);
+  // expected-error@+1 {{this builtin requires 'dsp' ASE, please use -mdsp}}
+  __builtin_mips_lwx(p, 32);
+}
+
+void dspr2() {
+  v4i8 a;
+  v4q7 b;
+
+  // expected-error@+1 {{this builtin requires 'dsp r2' ASE, please use -mdspr2}}
+  __builtin_mips_absq_s_qb(b);
+  // expected-error@+1 {{this builtin requires 'dsp r2' ASE, please use -mdspr2}}
+  __builtin_mips_subuh_r_qb(a, a);
+}
+
+void msa() {
+  v16i8 a;
+  v16u8 b;
+
+  // expected-error@+1 {{this builtin requires 'msa' ASE, please use -mmsa}}
+  __builtin_msa_add_a_b(a, a);
+  // expected-error@+1 {{this builtin requires 'msa' ASE, please use -mmsa}}
+  __builtin_msa_xori_b(b, 5);
+}
Index: clang/test/CodeGen/builtins-mips.c
===
--- clang/test/CodeGen/builtins-mips.c
+++ clang/test/CodeGen/builtins-mips.c
@@ -1,5 +1,6 @@
 // REQUIRES: mips-registered-target
-// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm %s -o - \
+// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm %s \
+// RUN:-target-feature +dspr2 -o - \
 // RUN:   | FileCheck %s
 
 typedef int q31;
Index: clang/test/CodeGen/builtins-mips-args.c
===
--- clang/test/CodeGen/builtins-mips-args.c
+++ clang/test/CodeGen/builtins-mips-args.c
@@ -1,5 +1,6 @@
 // REQUIRES: mips-registered-target
-// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -target-feature +dspr2 \
+// RUN:-fsyntax-only -verify %s
 
 void foo() {
   // MIPS DSP Rev 1
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3051,8 +3051,37 @@
  CheckHexagonBuiltinArgument(BuiltinID, TheCall);
 }
 
+bool Sema::CheckMipsBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
+  return CheckMipsBuiltinCpu(BuiltinID, TheCall) ||
+ CheckMipsBuiltinArgument(BuiltinID, TheCall);
+}
+
+bool Sema::CheckMipsBuiltinCpu(unsigned BuiltinID, CallExpr *TheCall) {
+  const TargetInfo  = Context.getTargetInfo();
 
-// CheckMipsBuiltinFunctionCall - Checks the constant value passed to the
+  if (Mips::BI__builtin_mips_addu_qb <= BuiltinID &&
+  BuiltinID <= Mips::BI__builtin_mips_lwx) {
+if (!TI.hasFeature("dsp"))
+  return Diag(TheCall->getBeginLoc(), diag::err_mips_builtin_requires_dsp);
+  }
+
+  if (Mips::BI__builtin_mips_absq_s_qb <= BuiltinID &&
+  BuiltinID <= Mips::BI__builtin_mips_subuh_r_qb) {
+if (!TI.hasFeature("dspr2"))
+  return Diag(TheCall->getBeginLoc(),
+  diag::err_mips_builtin_requires_dspr2);
+  }
+
+  if (Mips::BI__builtin_msa_add_a_b <= BuiltinID &&
+  BuiltinID <= Mips::BI__builtin_msa_xori_b) {
+if (!TI.hasFeature("msa"))
+  return Diag(TheCall->getBeginLoc(), diag::err_mips_builtin_requires_msa);
+  }
+
+  return false;
+}
+
+// CheckMipsBuiltinArgument - Checks the constant value passed to the
 // intrinsic is correct. The switch statement is ordered by DSP, MSA. The
 // ordering for DSP is unspecified. MSA is ordered by the data format used
 // by the underlying instruction i.e., df/m, df/n and then by size.
@@ -3061,7 +3090,7 @@
 //definitions from include/clang/Basic/BuiltinsMips.def.
 // FIXME: GCC is strict on signedness for some of these intrinsics, we should
 //be too.
-bool Sema::CheckMipsBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
+bool Sema::CheckMipsBuiltinArgument(unsigned BuiltinID, CallExpr *TheCall) {
   unsigned i = 0, l = 

[PATCH] D70808: [mips] Check that features required by built-ins are enabled

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan created this revision.
atanasyan added a reviewer: Petar.Avramovic.
Herald added subscribers: jrtc27, arichardson, sdardis.
Herald added a project: clang.

Now Clang does not check that features required by built-in functions are 
enabled. That causes errors in the backend reported in PR44018.

This patch fixes this bug by checking that required features are enabled.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D70808

Files:
  clang/include/clang/Basic/DiagnosticSemaKinds.td
  clang/include/clang/Sema/Sema.h
  clang/lib/Basic/Targets/Mips.cpp
  clang/lib/Sema/SemaChecking.cpp
  clang/test/CodeGen/builtins-mips-args.c
  clang/test/CodeGen/builtins-mips.c
  clang/test/Sema/builtins-mips-features.c

Index: clang/test/Sema/builtins-mips-features.c
===
--- /dev/null
+++ clang/test/Sema/builtins-mips-features.c
@@ -0,0 +1,37 @@
+// REQUIRES: mips-registered-target
+// RUN: %clang_cc1 -triple mips64 -fsyntax-only -verify %s
+
+typedef signed char v4i8 __attribute__ ((vector_size(4)));
+typedef signed char v4q7 __attribute__ ((vector_size(4)));
+typedef signed char v16i8 __attribute__((vector_size(16), aligned(16)));
+typedef unsigned char v16u8 __attribute__((vector_size(16), aligned(16)));
+
+void dsp() {
+  v4i8 a;
+  void* p;
+
+  // expected-error@+1 {{this builtin requires 'dsp' ASE, please use -mdsp}}
+  __builtin_mips_addu_qb(a, a);
+  // expected-error@+1 {{this builtin requires 'dsp' ASE, please use -mdsp}}
+  __builtin_mips_lwx(p, 32);
+}
+
+void dspr2() {
+  v4i8 a;
+  v4q7 b;
+
+  // expected-error@+1 {{this builtin requires 'dsp r2' ASE, please use -mdspr2}}
+  __builtin_mips_absq_s_qb(b);
+  // expected-error@+1 {{this builtin requires 'dsp r2' ASE, please use -mdspr2}}
+  __builtin_mips_subuh_r_qb(a, a);
+}
+
+void msa() {
+  v16i8 a;
+  v16u8 b;
+
+  // expected-error@+1 {{this builtin requires 'msa' ASE, please use -mmsa}}
+  __builtin_msa_add_a_b(a, a);
+  // expected-error@+1 {{this builtin requires 'msa' ASE, please use -mmsa}}
+  __builtin_msa_xori_b(b, 5);
+}
Index: clang/test/CodeGen/builtins-mips.c
===
--- clang/test/CodeGen/builtins-mips.c
+++ clang/test/CodeGen/builtins-mips.c
@@ -1,5 +1,6 @@
 // REQUIRES: mips-registered-target
-// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm %s -o - \
+// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm %s \
+// RUN:-target-feature +dspr2 -o - \
 // RUN:   | FileCheck %s
 
 typedef int q31;
Index: clang/test/CodeGen/builtins-mips-args.c
===
--- clang/test/CodeGen/builtins-mips-args.c
+++ clang/test/CodeGen/builtins-mips-args.c
@@ -1,5 +1,6 @@
 // REQUIRES: mips-registered-target
-// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -fsyntax-only -verify %s
+// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -target-feature +dspr2 \
+// RUN:-fsyntax-only -verify %s
 
 void foo() {
   // MIPS DSP Rev 1
Index: clang/lib/Sema/SemaChecking.cpp
===
--- clang/lib/Sema/SemaChecking.cpp
+++ clang/lib/Sema/SemaChecking.cpp
@@ -3051,8 +3051,37 @@
  CheckHexagonBuiltinArgument(BuiltinID, TheCall);
 }
 
+bool Sema::CheckMipsBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
+  return CheckMipsBuiltinCpu(BuiltinID, TheCall) ||
+ CheckMipsBuiltinArgument(BuiltinID, TheCall);
+}
+
+bool Sema::CheckMipsBuiltinCpu(unsigned BuiltinID, CallExpr *TheCall) {
+  const TargetInfo  = Context.getTargetInfo();
 
-// CheckMipsBuiltinFunctionCall - Checks the constant value passed to the
+  if (Mips::BI__builtin_mips_addu_qb <= BuiltinID &&
+  BuiltinID <= Mips::BI__builtin_mips_lwx) {
+if (!TI.hasFeature("dsp"))
+  return Diag(TheCall->getBeginLoc(), diag::err_mips_builtin_requires_dsp);
+  }
+
+  if (Mips::BI__builtin_mips_absq_s_qb <= BuiltinID &&
+  BuiltinID <= Mips::BI__builtin_mips_subuh_r_qb) {
+if (!TI.hasFeature("dspr2"))
+  return Diag(TheCall->getBeginLoc(),
+  diag::err_mips_builtin_requires_dspr2);
+  }
+
+  if (Mips::BI__builtin_msa_add_a_b <= BuiltinID &&
+  BuiltinID <= Mips::BI__builtin_msa_xori_b) {
+if (!TI.hasFeature("msa"))
+  return Diag(TheCall->getBeginLoc(), diag::err_mips_builtin_requires_msa);
+  }
+
+  return false;
+}
+
+// CheckMipsBuiltinArgument - Checks the constant value passed to the
 // intrinsic is correct. The switch statement is ordered by DSP, MSA. The
 // ordering for DSP is unspecified. MSA is ordered by the data format used
 // by the underlying instruction i.e., df/m, df/n and then by size.
@@ -3061,7 +3090,7 @@
 //definitions from include/clang/Basic/BuiltinsMips.def.
 // FIXME: GCC is strict on signedness for some of these intrinsics, we should
 //be too.
-bool Sema::CheckMipsBuiltinFunctionCall(unsigned BuiltinID, 

[PATCH] D66795: [Mips] Use appropriate private label prefix based on Mips ABI

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.

LGTM. But before commit get more approvals. For example, from echristo, code 
owners of other targets, etc.

I would keep the as-is. In that case a target of such huge modifications looks 
a bit more clear.


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[PATCH] D59702: Unbreak the build of compiler-rt on Linux/mips64el

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

I hope the rL360825  fixes the problem so 
this patch can be switch to the `abandoned` state.


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[PATCH] D60967: Move setTargetAttributes after setGVProperties in SetFunctionAttributes

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

I do not see any problem from MIPS targets point of view.


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[PATCH] D59702: Unbreak the build of compiler-rt on Linux/mips64el

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

I'm sorry for delay with handling this issue.

The **160** constant in the `FIRST_32_SECOND_64(144, 104)` depends on the 
following fragment from the `cmake/modules/HandleLLVMOptions.cmake` file 
introduced by the rL301171 . If 
`_LARGEFILE_SOURCE` and `_FILE_OFFSET_BITS=64` are defined, `sizeof(struct 
stat)` equals to **160**. This constant was configured by the rL301307 
. Unfortunately, in case of building on MIPS 
64-bit `CMAKE_SIZEOF_VOID_P` equals to **8** and these definitions are not 
provided to the compiler. It's a separate problem. Probably it needs to be 
handled by supporting the `LLVM_BUILD_32_BITS` option for MIPS targets. These 
option is used to build 32-bit binaries on 64-bit host. But now it's supported 
on limited set of architectures.

  if( CMAKE_SIZEOF_VOID_P EQUAL 4 AND NOT LLVM_FORCE_SMALLFILE_FOR_ANDROID)
# FIXME: It isn't handled in LLVM_BUILD_32_BITS.
add_definitions( -D_LARGEFILE_SOURCE )
add_definitions( -D_FILE_OFFSET_BITS=64 )
  endif()

Meanwhile, could you try to workaround the issue by explicitly providing 
`-mabi=32` (for building MIPS 32-bit binaries) and `-mabi=64` (for building 
MIPS 64-bit binaries) options to the cmake? Something like that:

  -DCMAKE_C_FLAGS="-mabi=32"
  -DCMAKE_CXX_FLAGS="-mabi=32"


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[PATCH] D59702: Unbreak the build of compiler-rt on Linux/mips64el

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

How do you build compiler-rt? What OS do yo use?


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[PATCH] D59702: Unbreak the build of compiler-rt on Linux/mips64el

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added inline comments.



Comment at: lib/sanitizer_common/sanitizer_platform_limits_linux.cc:31
 #include 
-#if defined(__x86_64__) ||  defined(__mips__)
+#if defined(__x86_64__)
 #include 

Why do you need this change?



Comment at: lib/sanitizer_common/sanitizer_platform_limits_posix.h:85
+ FIRST_32_SECOND_64(144, 104);
   const unsigned struct_kernel_stat64_sz = 104;
 #elif defined(__s390__) && !defined(__s390x__)

These numbers are sizes of the `struct stat` for 32 / 64-bit cases. Due the 
rL301171 32-bit size depends on definitions of the `_LARGEFILE_SOURCE` and 
`FILE_OFFSET_BITS=64` macros.

I run the following test case on Debian 9 mipsel  64-bit:
```
$ cat test.c
#include 
#include 

int main() {
  printf("%u\n", sizeof(struct stat));
}

$ gcc -mabi=64 test.c && ./a.out
216

$ gcc -mabi=32 test.c -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 && ./a.out
160
```

Both numbers are the same as in the original version of the 
`sanitizer_platform_limits_posix.h`.

I guess that the `144` is `sizeof(struct stat)` in 32-bit case without proper 
`_LARGEFILE_SOURCE` and `_FILE_OFFSET_BITS=64` definitions. It looks like the 
code introduced by the rL301171 does not work in your case.

The `104` looks strange. It means that the size of `struct stat` in 32-bit case 
is larger than in the 64-bit one.


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[PATCH] D58165: [Headers][mips] Add `__attribute__((__mode__(__unwind_word__)))` to the _Unwind_Word / _Unwind_SWord definitions

[Simon Atanasyan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC353965: [Headers][mips] Add 
`__attribute__((__mode__(__unwind_word__)))` to the… (authored by atanasyan, 
committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D58165?vs=186585=186694#toc

Repository:
  rC Clang

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Files:
  lib/Basic/Targets/Mips.cpp
  lib/Basic/Targets/Mips.h
  lib/Headers/unwind.h
  test/Sema/attr-mode.c


Index: lib/Basic/Targets/Mips.cpp
===
--- lib/Basic/Targets/Mips.cpp
+++ lib/Basic/Targets/Mips.cpp
@@ -215,6 +215,14 @@
  Builtin::FirstTSBuiltin);
 }
 
+unsigned MipsTargetInfo::getUnwindWordWidth() const {
+  return llvm::StringSwitch(ABI)
+  .Case("o32", 32)
+  .Case("n32", 64)
+  .Case("n64", 64)
+  .Default(getPointerWidth(0));
+}
+
 bool MipsTargetInfo::validateTarget(DiagnosticsEngine ) const {
   // microMIPS64R6 backend was removed.
   if (getTriple().isMIPS64() && IsMicromips && (ABI == "n32" || ABI == "n64")) 
{
Index: lib/Basic/Targets/Mips.h
===
--- lib/Basic/Targets/Mips.h
+++ lib/Basic/Targets/Mips.h
@@ -401,6 +401,8 @@
 return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128;
   }
 
+  unsigned getUnwindWordWidth() const override;
+
   bool validateTarget(DiagnosticsEngine ) const override;
 };
 } // namespace targets
Index: lib/Headers/unwind.h
===
--- lib/Headers/unwind.h
+++ lib/Headers/unwind.h
@@ -66,8 +66,8 @@
 #pragma GCC visibility push(default)
 #endif
 
-typedef uintptr_t _Unwind_Word;
-typedef intptr_t _Unwind_Sword;
+typedef uintptr_t _Unwind_Word __attribute__((__mode__(__unwind_word__)));
+typedef intptr_t _Unwind_Sword __attribute__((__mode__(__unwind_word__)));
 typedef uintptr_t _Unwind_Ptr;
 typedef uintptr_t _Unwind_Internal_Ptr;
 typedef uint64_t _Unwind_Exception_Class;
Index: test/Sema/attr-mode.c
===
--- test/Sema/attr-mode.c
+++ test/Sema/attr-mode.c
@@ -6,6 +6,12 @@
 // RUN:   -verify %s
 // RUN: %clang_cc1 -triple x86_64-pc-linux-gnux32 -DTEST_64BIT_X86 
-fsyntax-only \
 // RUN:   -verify %s
+// RUN: %clang_cc1 -triple mips-linux-gnu -DTEST_MIPS_32 -fsyntax-only \
+// RUN:   -verify %s
+// RUN: %clang_cc1 -triple mips64-linux-gnuabin32 -DTEST_MIPS_N32 
-fsyntax-only \
+// RUN:   -verify %s
+// RUN: %clang_cc1 -triple mips64-linux-gnu -DTEST_MIPS_64 -fsyntax-only \
+// RUN:   -verify %s
 
 typedef int i16_1 __attribute((mode(HI)));
 int i16_1_test[sizeof(i16_1) == 2 ? 1 : -1];
@@ -33,7 +39,7 @@
 int c32_test[sizeof(c32) == 8 ? 1 : -1];
 typedef _Complex float c64 __attribute((mode(DC)));
 
-#ifndef TEST_64BIT_PPC64 // Note, 'XC' mode is illegal for PPC64 machines.
+#if !defined(__ppc__) && !defined(__mips__) // Note, 'XC' mode is illegal for 
PPC64 and MIPS machines.
 typedef _Complex float c80 __attribute((mode(XC)));
 #endif
 
@@ -84,6 +90,15 @@
 void f_ft128_complex_arg(_Complex long double *x);
 void test_TFtype(f128ibm *a) { f_ft128_arg (a); }
 void test_TCtype(c128ibm *a) { f_ft128_complex_arg (a); }
+#elif TEST_MIPS_32
+typedef unsigned int gcc_unwind_word __attribute__((mode(unwind_word)));
+int foo[sizeof(gcc_unwind_word) == 4 ? 1 : -1];
+#elif TEST_MIPS_N32
+typedef unsigned int gcc_unwind_word __attribute__((mode(unwind_word)));
+int foo[sizeof(gcc_unwind_word) == 8 ? 1 : -1];
+#elif TEST_MIPS_64
+typedef unsigned int gcc_unwind_word __attribute__((mode(unwind_word)));
+int foo[sizeof(gcc_unwind_word) == 8 ? 1 : -1];
 #else
 #error Unknown test architecture.
 #endif


Index: lib/Basic/Targets/Mips.cpp
===
--- lib/Basic/Targets/Mips.cpp
+++ lib/Basic/Targets/Mips.cpp
@@ -215,6 +215,14 @@
  Builtin::FirstTSBuiltin);
 }
 
+unsigned MipsTargetInfo::getUnwindWordWidth() const {
+  return llvm::StringSwitch(ABI)
+  .Case("o32", 32)
+  .Case("n32", 64)
+  .Case("n64", 64)
+  .Default(getPointerWidth(0));
+}
+
 bool MipsTargetInfo::validateTarget(DiagnosticsEngine ) const {
   // microMIPS64R6 backend was removed.
   if (getTriple().isMIPS64() && IsMicromips && (ABI == "n32" || ABI == "n64")) {
Index: lib/Basic/Targets/Mips.h
===
--- lib/Basic/Targets/Mips.h
+++ lib/Basic/Targets/Mips.h
@@ -401,6 +401,8 @@
 return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128;
   }
 
+  unsigned getUnwindWordWidth() const override;
+
   bool validateTarget(DiagnosticsEngine ) const override;
 };
 } // namespace targets
Index: lib/Headers/unwind.h
===

[PATCH] D58165: [Headers][mips] Add `__attribute__((__mode__(__unwind_word__)))` to the _Unwind_Word / _Unwind_SWord definitions

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan created this revision.
atanasyan added reviewers: rnk, thakis, craig.topper.
Herald added subscribers: jrtc27, arichardson, sdardis.
Herald added a project: clang.

The rationale of this change is to fix _Unwind_Word / _Unwind_SWord definitions 
for MIPS N32 ABI. This ABI uses 32-bit pointers, but _Unwind_Word and 
_Unwind_SWord types are eight bytes long.

1. The __attribute__((__mode__(__unwind_word__))) is added to the type 
definitions. It makes them equal to the corresponding definitions used by GCC 
and allows to override types using `getUnwindWordWidth` function.
2. The `getUnwindWordWidth` virtual function override in the `MipsTargetInfo` 
class and provides correct type size values.


Repository:
  rC Clang

https://reviews.llvm.org/D58165

Files:
  clang/lib/Basic/Targets/Mips.cpp
  clang/lib/Basic/Targets/Mips.h
  clang/lib/Headers/unwind.h
  clang/test/Sema/attr-mode.c


Index: clang/test/Sema/attr-mode.c
===
--- clang/test/Sema/attr-mode.c
+++ clang/test/Sema/attr-mode.c
@@ -6,6 +6,12 @@
 // RUN:   -verify %s
 // RUN: %clang_cc1 -triple x86_64-pc-linux-gnux32 -DTEST_64BIT_X86 
-fsyntax-only \
 // RUN:   -verify %s
+// RUN: %clang_cc1 -triple mips-linux-gnu -DTEST_MIPS_32 -fsyntax-only \
+// RUN:   -verify %s
+// RUN: %clang_cc1 -triple mips64-linux-gnuabin32 -DTEST_MIPS_N32 
-fsyntax-only \
+// RUN:   -verify %s
+// RUN: %clang_cc1 -triple mips64-linux-gnu -DTEST_MIPS_64 -fsyntax-only \
+// RUN:   -verify %s
 
 typedef int i16_1 __attribute((mode(HI)));
 int i16_1_test[sizeof(i16_1) == 2 ? 1 : -1];
@@ -33,7 +39,7 @@
 int c32_test[sizeof(c32) == 8 ? 1 : -1];
 typedef _Complex float c64 __attribute((mode(DC)));
 
-#ifndef TEST_64BIT_PPC64 // Note, 'XC' mode is illegal for PPC64 machines.
+#if !defined(__ppc__) && !defined(__mips__) // Note, 'XC' mode is illegal for 
PPC64 and MIPS machines.
 typedef _Complex float c80 __attribute((mode(XC)));
 #endif
 
@@ -84,6 +90,15 @@
 void f_ft128_complex_arg(_Complex long double *x);
 void test_TFtype(f128ibm *a) { f_ft128_arg (a); }
 void test_TCtype(c128ibm *a) { f_ft128_complex_arg (a); }
+#elif TEST_MIPS_32
+typedef unsigned int gcc_unwind_word __attribute__((mode(unwind_word)));
+int foo[sizeof(gcc_unwind_word) == 4 ? 1 : -1];
+#elif TEST_MIPS_N32
+typedef unsigned int gcc_unwind_word __attribute__((mode(unwind_word)));
+int foo[sizeof(gcc_unwind_word) == 8 ? 1 : -1];
+#elif TEST_MIPS_64
+typedef unsigned int gcc_unwind_word __attribute__((mode(unwind_word)));
+int foo[sizeof(gcc_unwind_word) == 8 ? 1 : -1];
 #else
 #error Unknown test architecture.
 #endif
Index: clang/lib/Headers/unwind.h
===
--- clang/lib/Headers/unwind.h
+++ clang/lib/Headers/unwind.h
@@ -66,8 +66,8 @@
 #pragma GCC visibility push(default)
 #endif
 
-typedef uintptr_t _Unwind_Word;
-typedef intptr_t _Unwind_Sword;
+typedef uintptr_t _Unwind_Word __attribute__((__mode__(__unwind_word__)));
+typedef intptr_t _Unwind_Sword __attribute__((__mode__(__unwind_word__)));
 typedef uintptr_t _Unwind_Ptr;
 typedef uintptr_t _Unwind_Internal_Ptr;
 typedef uint64_t _Unwind_Exception_Class;
Index: clang/lib/Basic/Targets/Mips.h
===
--- clang/lib/Basic/Targets/Mips.h
+++ clang/lib/Basic/Targets/Mips.h
@@ -401,6 +401,8 @@
 return (ABI == "n32" || ABI == "n64") || getTargetOpts().ForceEnableInt128;
   }
 
+  unsigned getUnwindWordWidth() const override;
+
   bool validateTarget(DiagnosticsEngine ) const override;
 };
 } // namespace targets
Index: clang/lib/Basic/Targets/Mips.cpp
===
--- clang/lib/Basic/Targets/Mips.cpp
+++ clang/lib/Basic/Targets/Mips.cpp
@@ -215,6 +215,14 @@
  Builtin::FirstTSBuiltin);
 }
 
+unsigned MipsTargetInfo::getUnwindWordWidth() const {
+  return llvm::StringSwitch(ABI)
+  .Case("o32", 32)
+  .Case("n32", 64)
+  .Case("n64", 64)
+  .Default(getPointerWidth(0));
+}
+
 bool MipsTargetInfo::validateTarget(DiagnosticsEngine ) const {
   // microMIPS64R6 backend was removed.
   if (getTriple().isMIPS64() && IsMicromips && (ABI == "n32" || ABI == "n64")) 
{


Index: clang/test/Sema/attr-mode.c
===
--- clang/test/Sema/attr-mode.c
+++ clang/test/Sema/attr-mode.c
@@ -6,6 +6,12 @@
 // RUN:   -verify %s
 // RUN: %clang_cc1 -triple x86_64-pc-linux-gnux32 -DTEST_64BIT_X86 -fsyntax-only \
 // RUN:   -verify %s
+// RUN: %clang_cc1 -triple mips-linux-gnu -DTEST_MIPS_32 -fsyntax-only \
+// RUN:   -verify %s
+// RUN: %clang_cc1 -triple mips64-linux-gnuabin32 -DTEST_MIPS_N32 -fsyntax-only \
+// RUN:   -verify %s
+// RUN: %clang_cc1 -triple mips64-linux-gnu -DTEST_MIPS_64 -fsyntax-only \
+// RUN:   -verify %s
 
 typedef int i16_1 __attribute((mode(HI)));
 int i16_1_test[sizeof(i16_1) == 2 ? 1 : -1];
@@ 

[PATCH] D57458: [docs][mips] Clang 8.0 Release notes

[Simon Atanasyan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL352675: [docs][mips] Clang 8.0 Release notes (authored by 
atanasyan, committed by ).
Herald added a subscriber: llvm-commits.

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Files:
  cfe/branches/release_80/docs/ReleaseNotes.rst


Index: cfe/branches/release_80/docs/ReleaseNotes.rst
===
--- cfe/branches/release_80/docs/ReleaseNotes.rst
+++ cfe/branches/release_80/docs/ReleaseNotes.rst
@@ -127,6 +127,10 @@
   manually and rely on the old behaviour you will need to add appropriate
   compiler flags for finding the corresponding libc++ include directory.
 
+- The integrated assembler is used now by default for all MIPS targets.
+
+- Improved support for MIPS N32 ABI and MIPS R6 target triples.
+
 New Compiler Flags
 --
 
@@ -139,6 +143,10 @@
 - When using a custom stack alignment, the ``stackrealign`` attribute is now
   implicitly set on the main function.
 
+- Emission of ``R_MIPS_JALR`` and ``R_MICROMIPS_JALR`` relocations can now
+  be controlled by the ``-mrelax-pic-calls`` and ``-mno-relax-pic-calls``
+  options.
+
 - ...
 
 Deprecated Compiler Flags


Index: cfe/branches/release_80/docs/ReleaseNotes.rst
===
--- cfe/branches/release_80/docs/ReleaseNotes.rst
+++ cfe/branches/release_80/docs/ReleaseNotes.rst
@@ -127,6 +127,10 @@
   manually and rely on the old behaviour you will need to add appropriate
   compiler flags for finding the corresponding libc++ include directory.
 
+- The integrated assembler is used now by default for all MIPS targets.
+
+- Improved support for MIPS N32 ABI and MIPS R6 target triples.
+
 New Compiler Flags
 --
 
@@ -139,6 +143,10 @@
 - When using a custom stack alignment, the ``stackrealign`` attribute is now
   implicitly set on the main function.
 
+- Emission of ``R_MIPS_JALR`` and ``R_MICROMIPS_JALR`` relocations can now
+  be controlled by the ``-mrelax-pic-calls`` and ``-mno-relax-pic-calls``
+  options.
+
 - ...
 
 Deprecated Compiler Flags
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[PATCH] D57458: [docs][mips] Clang 8.0 Release notes

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan created this revision.
atanasyan added reviewers: hans, petarj, abeserminji, smaksimovic.
Herald added subscribers: arichardson, sdardis.

MIPS specific part of Clang 8.0 Release notes. Feel free to add more notes if I 
miss something.


Repository:
  rC Clang

https://reviews.llvm.org/D57458

Files:
  docs/ReleaseNotes.rst


Index: docs/ReleaseNotes.rst
===
--- docs/ReleaseNotes.rst
+++ docs/ReleaseNotes.rst
@@ -127,6 +127,10 @@
   manually and rely on the old behaviour you will need to add appropriate
   compiler flags for finding the corresponding libc++ include directory.
 
+- The integrated assembler is used now by default for all MIPS targets.
+
+- Improved support for MIPS N32 ABI and MIPS R6 target triples.
+
 New Compiler Flags
 --
 
@@ -139,6 +143,10 @@
 - When using a custom stack alignment, the ``stackrealign`` attribute is now
   implicitly set on the main function.
 
+- Emission of ``R_MIPS_JALR`` and ``R_MICROMIPS_JALR`` relocations can now
+  be controlled by the ``-mrelax-pic-calls`` and ``-mno-relax-pic-calls``
+  options.
+
 - ...
 
 Deprecated Compiler Flags


Index: docs/ReleaseNotes.rst
===
--- docs/ReleaseNotes.rst
+++ docs/ReleaseNotes.rst
@@ -127,6 +127,10 @@
   manually and rely on the old behaviour you will need to add appropriate
   compiler flags for finding the corresponding libc++ include directory.
 
+- The integrated assembler is used now by default for all MIPS targets.
+
+- Improved support for MIPS N32 ABI and MIPS R6 target triples.
+
 New Compiler Flags
 --
 
@@ -139,6 +143,10 @@
 - When using a custom stack alignment, the ``stackrealign`` attribute is now
   implicitly set on the main function.
 
+- Emission of ``R_MIPS_JALR`` and ``R_MICROMIPS_JALR`` relocations can now
+  be controlled by the ``-mrelax-pic-calls`` and ``-mno-relax-pic-calls``
+  options.
+
 - ...
 
 Deprecated Compiler Flags
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[PATCH] D56836: [mips] Include whole lpthread when using both -pthread and -static

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

In D56836#1362967 , @abeserminji wrote:

> As an option, we can provide necessary flags for the test to finish 
> successfully instead of not testing it.


Agreed.


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[PATCH] D56878: [mips] Add '-mrelax-pic-calls', '-mno-relax-pic-calls'

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM with a nit.




Comment at: lib/Driver/ToolChains/Clang.cpp:1720
+  CmdArgs.push_back("-mllvm");
+  CmdArgs.push_back(Args.MakeArgString("-mips-jalr-reloc=0"));
+}

It's not necessary to call the `MakeArgString` here. You can write just 
`CmdArgs.push_back("-mips-jalr-reloc=0");`.


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[PATCH] D56836: [mips] Include whole lpthread when using both -pthread and -static

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

In D56836#1361528 , @abeserminji wrote:

> I am not sure if -static option passed as --cflag to lnt runtest enters the 
> LDFLAGS. I guess it doesn't. 
>  But if there is a way to check which options are passed as --cflags, we 
> might be able to add -Wl, -whole-archive -lpthread -Wl -no-whole-archive only 
> in case when static is used.
>  That would be my preferable option in this situation, but I couldn't find 
> any clues on how to do that.


You are right, LDFLAGS does not contain the `-static`. But if you pass linker 
options to the CMake by the `CMAKE_EXE_LINKER_FLAGS` variable, the following 
code should help.

  --- a/SingleSource/UnitTests/C++11/CMakeLists.txt
  +++ b/SingleSource/UnitTests/C++11/CMakeLists.txt
  @@ -1,3 +1,9 @@
   list(APPEND CXXFLAGS -std=c++11 -pthread)
   list(APPEND LDFLAGS -lstdc++ -pthread)
  +
  +file(GLOB Source RELATIVE ${CMAKE_CURRENT_SOURCE_DIR} *.c *.cpp)
  +if(${CMAKE_EXE_LINKER_FLAGS} MATCHES "-static")
  +  list(REMOVE_ITEM Source stdthreadbug.cpp)
  +endif()
  +
   llvm_singlesource()


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[PATCH] D56836: [mips] Include whole lpthread when using both -pthread and -static

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Now I'm not sure that we really need to make this code more complicated. As to 
the `stdthreadbug` test case, maybe we can just exclude this test if LDFLAGS 
contains the `-static` option.

As to this patch, is it possible to implement the following algorithm? Will it 
be more easy and clear?

1. if there is no `-pthread` or `-pthreads` flag, do nothing.
2. if the flag provided, iterate over `-l` options (do not introduce new 
`lpthread` first-class argument). If there is the `-lpthread` (with or without 
`whole-archive` surrounds), consider a user know what he/she wants to do.
3. if there is no `-lpthread`, pass `--whole-archive -lpthread 
--no-whole-archive` to the linker.


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[PATCH] D55878: [Driver] Use --hash-style=gnu instead of both on FreeBSD

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added inline comments.



Comment at: lib/Driver/ToolChains/FreeBSD.cpp:160
+if (ToolChain.getTriple().getOSMajorVersion() >= 9)
+  CmdArgs.push_back("--hash-style=gnu");
 CmdArgs.push_back("--enable-new-dtags");

MaskRay wrote:
> I can't find rationale behind the MIPS discrepancy in the original commit. I 
> can add the if branch back if you tell me why...
> I can't find rationale behind the MIPS discrepancy in the original commit. I 
> can add the if branch back if you tell me why...

Did you check that linker on MIPS FreeBSD really support --hash-style=gnu?

As far as I know ".gnu.hash and the MIPS ABI require .dynsym to be sorted in 
different ways.  .gnu.hash needs symbols to be grouped by hash code whereas the 
MIPS ABI requires a mapping between the GOT and the symbol table".


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[PATCH] D52418: [driver][mips] Enable integrated assembler for MIPS64 except N32 ABI selected

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan abandoned this revision.
atanasyan added a comment.

Commits rL348934  and rL348935 
 enable using of integrated assembler for 
MIPS targets in all cases.


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[PATCH] D52418: [driver][mips] Enable integrated assembler for MIPS64 except N32 ABI selected

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

In https://reviews.llvm.org/D52418#1294699, @brad wrote:

> Simon?


The testing continues. Unfortunately I do not have access to an appropriate 
hardware so cannot control the process. But the task is not abandoned.


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[PATCH] D53984: [mips] Fix broken MSA test

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D52418: [driver][mips] Enable integrated assembler for MIPS64 except N32 ABI selected

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

In https://reviews.llvm.org/D52418#1271779, @brad wrote:

> How is it going with regard to N32 fixes / testing?


I'm in the process of building/testing LLVM/Clang binaries for N32 ABI.


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[PATCH] D50850: clang: Add triples support for MIPS r6

[Simon Atanasyan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL344608: [driver][mips] Support MIPS R6 target triples 
(authored by atanasyan, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D50850?vs=169810=169824#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D50850

Files:
  cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
  cfe/trunk/lib/Driver/ToolChains/Gnu.cpp
  cfe/trunk/lib/Driver/ToolChains/Linux.cpp
  cfe/trunk/test/CodeGen/atomics-inlining.c
  cfe/trunk/test/CodeGen/mips-zero-sized-struct.c
  cfe/trunk/test/CodeGen/target-data.c
  cfe/trunk/test/CodeGen/xray-attributes-supported.cpp
  cfe/trunk/test/Driver/clang-translation.c

Index: cfe/trunk/test/CodeGen/xray-attributes-supported.cpp
===
--- cfe/trunk/test/CodeGen/xray-attributes-supported.cpp
+++ cfe/trunk/test/CodeGen/xray-attributes-supported.cpp
@@ -5,20 +5,36 @@
 // RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
 // RUN: -triple mips-unknown-linux-gnu | FileCheck %s
 // RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
+// RUN: -triple mipsisa32r6-unknown-linux-gnu | FileCheck %s
+// RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
 // RUN: -triple mipsel-unknown-linux-gnu | FileCheck %s
 // RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
+// RUN: -triple mipsisa32r6el-unknown-linux-gnu | FileCheck %s
+// RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
 // RUN: -triple mips64-unknown-linux-gnu | FileCheck %s
 // RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
+// RUN: -triple mipsisa64r6-unknown-linux-gnu | FileCheck %s
+// RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
 // RUN: -triple mips64el-unknown-linux-gnu | FileCheck %s
 // RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
+// RUN: -triple mipsisa64r6el-unknown-linux-gnu | FileCheck %s
+// RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
 // RUN: -triple mips64-unknown-linux-gnuabi64 | FileCheck %s
 // RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
+// RUN: -triple mipsisa64r6-unknown-linux-gnuabi64 | FileCheck %s
+// RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
 // RUN: -triple mips64el-unknown-linux-gnuabi64 | FileCheck %s
 // RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
+// RUN: -triple mipsisa64r6el-unknown-linux-gnuabi64 | FileCheck %s
+// RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
 // RUN: -triple mips64-unknown-linux-gnuabin32 | FileCheck %s
 // RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
+// RUN: -triple mipsisa64r6-unknown-linux-gnuabin32 | FileCheck %s
+// RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
 // RUN: -triple mips64el-unknown-linux-gnuabin32 | FileCheck %s
 // RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
+// RUN: -triple mipsisa64r6el-unknown-linux-gnuabin32 | FileCheck %s
+// RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
 // RUN: -triple powerpc64le-unknown-linux-gnu | FileCheck %s
 
 // Make sure that the LLVM attribute for XRay-annotated functions do show up.
Index: cfe/trunk/test/CodeGen/atomics-inlining.c
===
--- cfe/trunk/test/CodeGen/atomics-inlining.c
+++ cfe/trunk/test/CodeGen/atomics-inlining.c
@@ -2,8 +2,10 @@
 // RUN: %clang_cc1 -triple powerpc-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=PPC32
 // RUN: %clang_cc1 -triple powerpc64-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=PPC64
 // RUN: %clang_cc1 -triple mipsel-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS32
+// RUN: %clang_cc1 -triple mipsisa32r6el-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS32
 // RUN: %clang_cc1 -triple mips64el-linux-gnu -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64
 // RUN: %clang_cc1 -triple mips64el-linux-gnuabi64 -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64
+// RUN: %clang_cc1 -triple mipsisa64r6el-linux-gnuabi64 -emit-llvm %s -o - | FileCheck %s -check-prefix=MIPS64
 // RUN: %clang_cc1 -triple sparc-unknown-eabi -emit-llvm %s -o - | FileCheck %s -check-prefix=SPARCV8 -check-prefix=SPARC
 // RUN: %clang_cc1 -triple sparcv9-unknown-eabi -emit-llvm %s -o - | FileCheck %s -check-prefix=SPARCV9 -check-prefix=SPARC
 
Index: cfe/trunk/test/CodeGen/mips-zero-sized-struct.c
===
--- cfe/trunk/test/CodeGen/mips-zero-sized-struct.c
+++ cfe/trunk/test/CodeGen/mips-zero-sized-struct.c
@@ -1,13 +1,23 @@
 // RUN: 

[PATCH] D50850: clang: Add triples support for MIPS r6

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks for the patch.


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[PATCH] D50850: clang: Add triples support for MIPS r6

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Could you please rebase this patch against the trunk?




Comment at: lib/Driver/ToolChains/Linux.cpp:717
+  const StringRef MIPS64R6ELMultiarchIncludeDirs[] = {
+  "/usr/include/mipsisa64r6el-linux-gnu",
+  "/usr/include/mipsisa64r6el-linux-gnuabi64"};

If we drop `mipsisa64r6-linux-gnu`, `mipsisa64r6el-linux-gnu` triples in the 
`getMultiarchTriple` function, why do we need these triple here?


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[PATCH] D51464: clang: fix MIPS/N32 triple and paths

[Simon Atanasyan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rC344570: [mips] Fix handling of GNUABIN32 environment in a 
target triple (authored by atanasyan, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D51464?vs=168116=169763#toc

Repository:
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Files:
  lib/Basic/Targets/Mips.h
  lib/Driver/ToolChains/Arch/Mips.cpp
  lib/Driver/ToolChains/Gnu.cpp
  lib/Driver/ToolChains/Linux.cpp
  test/CodeGen/atomics-inlining.c
  test/CodeGen/mips-zero-sized-struct.c
  test/CodeGen/target-data.c
  test/CodeGen/xray-attributes-supported.cpp
  test/Driver/clang-translation.c
  test/Driver/linux-ld.c

Index: test/CodeGen/mips-zero-sized-struct.c
===
--- test/CodeGen/mips-zero-sized-struct.c
+++ test/CodeGen/mips-zero-sized-struct.c
@@ -2,8 +2,12 @@
 // RUN: %clang_cc1 -triple mipsel-unknown-linux-gnu -S -emit-llvm -o - %s | FileCheck -check-prefix=O32 %s
 // RUN: %clang_cc1 -triple mips64-unknown-linux-gnu -S -emit-llvm -o - %s  -target-abi n32 | FileCheck -check-prefix=N32 %s
 // RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s  -target-abi n32 | FileCheck -check-prefix=N32 %s
+// RUN: %clang_cc1 -triple mips64-unknown-linux-gnuabin32 -S -emit-llvm -o - %s  | FileCheck -check-prefix=N32 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnuabin32 -S -emit-llvm -o - %s  | FileCheck -check-prefix=N32 %s
 // RUN: %clang_cc1 -triple mips64-unknown-linux-gnu -S -emit-llvm -o - %s | FileCheck -check-prefix=N64 %s
 // RUN: %clang_cc1 -triple mips64el-unknown-linux-gnu -S -emit-llvm -o - %s | FileCheck -check-prefix=N64 %s
+// RUN: %clang_cc1 -triple mips64-unknown-linux-gnuabi64 -S -emit-llvm -o - %s | FileCheck -check-prefix=N64 %s
+// RUN: %clang_cc1 -triple mips64el-unknown-linux-gnuabi64 -S -emit-llvm -o - %s | FileCheck -check-prefix=N64 %s
 
 // O32: define void @fn28(%struct.T2* noalias sret %agg.result, i8 signext %arg0)
 // N32: define void @fn28(i8 signext %arg0)
Index: test/CodeGen/xray-attributes-supported.cpp
===
--- test/CodeGen/xray-attributes-supported.cpp
+++ test/CodeGen/xray-attributes-supported.cpp
@@ -11,6 +11,14 @@
 // RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
 // RUN: -triple mips64el-unknown-linux-gnu | FileCheck %s
 // RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
+// RUN: -triple mips64-unknown-linux-gnuabi64 | FileCheck %s
+// RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
+// RUN: -triple mips64el-unknown-linux-gnuabi64 | FileCheck %s
+// RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
+// RUN: -triple mips64-unknown-linux-gnuabin32 | FileCheck %s
+// RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
+// RUN: -triple mips64el-unknown-linux-gnuabin32 | FileCheck %s
+// RUN: %clang_cc1 %s -fxray-instrument -std=c++11 -x c++ -emit-llvm -o - \
 // RUN: -triple powerpc64le-unknown-linux-gnu | FileCheck %s
 
 // Make sure that the LLVM attribute for XRay-annotated functions do show up.
Index: test/CodeGen/target-data.c
===
--- test/CodeGen/target-data.c
+++ test/CodeGen/target-data.c
@@ -42,18 +42,30 @@
 // RUN: FileCheck %s -check-prefix=MIPS-64EL
 // MIPS-64EL: target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
 
+// RUN: %clang_cc1 -triple mips64el-linux-gnuabi64 -o - -emit-llvm %s | \
+// RUN: FileCheck %s -check-prefix=MIPS-64EL
+
 // RUN: %clang_cc1 -triple mips64el-linux-gnu -o - -emit-llvm -target-abi n32 \
 // RUN: %s | FileCheck %s -check-prefix=MIPS-64EL-N32
 // MIPS-64EL-N32: target datalayout = "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"
 
+// RUN: %clang_cc1 -triple mips64el-linux-gnuabin32 -o - -emit-llvm \
+// RUN: %s | FileCheck %s -check-prefix=MIPS-64EL-N32
+
 // RUN: %clang_cc1 -triple mips64-linux-gnu -o - -emit-llvm %s | \
 // RUN: FileCheck %s -check-prefix=MIPS-64EB
 // MIPS-64EB: target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"
 
+// RUN: %clang_cc1 -triple mips64-linux-gnuabi64 -o - -emit-llvm %s | \
+// RUN: FileCheck %s -check-prefix=MIPS-64EB
+
 // RUN: %clang_cc1 -triple mips64-linux-gnu -o - -emit-llvm %s -target-abi n32 \
 // RUN: | FileCheck %s -check-prefix=MIPS-64EB-N32
 // MIPS-64EB-N32: target datalayout = "E-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"
 
+// RUN: %clang_cc1 -triple mips64-linux-gnuabin32 -o - -emit-llvm %s \
+// RUN: | FileCheck %s -check-prefix=MIPS-64EB-N32
+
 // RUN: %clang_cc1 -triple powerpc64-lv2 -o - -emit-llvm %s | \
 // RUN: FileCheck %s -check-prefix=PS3
 // PS3: target datalayout = "E-m:e-p:32:32-i64:64-n32:64"
Index: test/CodeGen/atomics-inlining.c
===
--- 

[PATCH] D51464: clang: fix MIPS/N32 triple and paths

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks for the patch.


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[PATCH] D51464: clang: fix MIPS/N32 triple and paths

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

I'm going to test current MIPS N32 ABI implementation. Maybe we are ready to 
enable integrated assembler for it. In that case both 
`Generic_GCC::IsIntegratedAssemblerDefault()` and `MipsMCAsmInfo` ctor can be 
simplified.


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[PATCH] D52418: [driver][mips] Enable integrated assembler for MIPS64 except N32 ABI selected

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

In https://reviews.llvm.org/D52418#1256189, @brad wrote:

> Simon, and what about lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp?


Good point. In fact, integrated assembler for GNUABIN32 was enabled in the 
`MipsMCAsmInfo` ctor by me and by mistake. I have another patch which fix it. 
But anyway there is a problem - we cannot check command line options in the 
`MipsMCAsmInfo`. So I'm going to test current MIPS N32 ABI implementation. 
Maybe we are ready to enable integrated assembler for it. In that case both 
`Generic_GCC::IsIntegratedAssemblerDefault()` and `MipsMCAsmInfo` ctor can be 
simplified.


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[PATCH] D52418: [driver][mips] Enable integrated assembler for MIPS64 except N32 ABI selected

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Ping?


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[PATCH] D50850: clang: Add triples support for MIPS r6

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

In https://reviews.llvm.org/D50850#1250285, @wzssyqa wrote:

> This is really for Clang. I guess you mean that compiler-rt directory also 
> need to be patched.


If you take a look at the previous version of this patch 
https://reviews.llvm.org/D50850?id=167419, you see that it changed LLVM files. 
Probably you attached another diff.

As to `compiler-rt` - the Phabricator replace `R6` symbols by the 
`https://reviews.llvm.org/source/compiler-rt/` links. So my statement was 
"Could you attach an actual patch brings `R6` support to the Clang driver?".




Comment at: lib/Driver/ToolChains/Gnu.cpp:2093
 BiarchTripleAliases.append(begin(MIPSELTriples), end(MIPSELTriples));
-BiarchTripleAliases.append(begin(MIPSTriples), end(MIPSTriples));
+BiarchLibDirs.append(begin(MIPSN32ELLibDirs), end(MIPSN32ELLibDirs));
+BiarchTripleAliases.append(begin(MIPSN32ELTriples), end(MIPSN32ELTriples));

wzssyqa wrote:
> atanasyan wrote:
> > Ditto
> As a question: why  MIPSTriples here?
> the above mips64 lines don't include any EL Triples.
I do not remember exact answer, although I might be an author if this code. 
Maybe it handle some complicated directories tree from multi-arch toolchains. 
Are all tests passed if you remove this line?



Comment at: lib/Driver/ToolChains/Gnu.cpp:2437
 if (getTriple().getEnvironment() == llvm::Triple::GNUABI64 ||
-getTriple().isAndroid() ||
-getTriple().isOSFreeBSD() ||
+getTriple().getEnvironment() == llvm::Triple::GNUABIN32 ||
+getTriple().isAndroid() || getTriple().isOSFreeBSD() ||

wzssyqa wrote:
> atanasyan wrote:
> > Are you sure that integrated LLVM assembler is ready to support N32 code 
> > generation? Anyway this change is for  a separate patch.
> I didn't have so many test, while helloworld programs really works.
> 
> 
You created a patch that teaches the Clang driver to understand (pass arguments 
to backend, find includes and libraries etc) N32 ABI better. Now I can compile 
"hello world". And after that you decided that LLVM backend does not have any 
MIPS N32 ABI related problems. I think we can enable the integrated assembler 
when a) it's possible to recursively build Clang with N32 ABI, b) all tests 
from LLVM test suite (https://llvm.org/docs/TestSuiteGuide.html) are passed in 
N32 ABI mode, c) we check that LLVM produces correct DWARF for N32.


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[PATCH] D51464: clang: fix MIPS/N32 triple and paths

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Please run test suite before sending a patch to review. After applying this 
patch the following tests failed:

- test/CodeGen/target-data.c
- test/Driver/mips-cs.cpp


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[PATCH] D51464: clang: fix MIPS/N32 triple and paths

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added inline comments.



Comment at: lib/Driver/ToolChains/Arch/Mips.cpp:85
 
   if (ABIName.empty() &&
   (Triple.getVendor() == llvm::Triple::MipsTechnologies ||

Is possible to rewrite this piece of code (lines 85-114) as follows?
```
  if (ABIName.empty() && (Triple.getEnvironment() == llvm::Triple::GNUABIN32))
ABIName = "n32";

  if (ABIName.empty() &&
  (Triple.getVendor() == llvm::Triple::MipsTechnologies ||
   Triple.getVendor() == llvm::Triple::ImaginationTechnologies)) {
ABIName = llvm::StringSwitch(CPUName)
  .Case("mips1", "o32")
  .Case("mips2", "o32")
  .Case("mips3", "n64")
  .Case("mips4", "n64")
  .Case("mips5", "n64")
  .Case("mips32", "o32")
  .Case("mips32r2", "o32")
  .Case("mips32r3", "o32")
  .Case("mips32r5", "o32")
  .Case("mips32r6", "o32")
  .Case("mips64", "n64")
  .Case("mips64r2", "n64")
  .Case("mips64r3", "n64")
  .Case("mips64r5", "n64")
  .Case("mips64r6", "n64")
  .Case("octeon", "n64")
  .Case("p5600", "o32")
  .Default("");
  }
```



Comment at: lib/Driver/ToolChains/Gnu.cpp:2082
 BiarchTripleAliases.append(begin(MIPSELTriples), end(MIPSELTriples));
-BiarchTripleAliases.append(begin(MIPSTriples), end(MIPSTriples));
+BiarchLibDirs.append(begin(MIPSN32ELLibDirs), end(MIPSN32ELLibDirs));
+BiarchTripleAliases.append(begin(MIPSN32ELTriples), end(MIPSN32ELTriples));

Why do you remove `BiarchTripleAliases.append(begin(MIPSTriples), 
end(MIPSTriples));` in that case only? Is it intended?


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[PATCH] D50850: clang: Add triples support for MIPS r6

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Fine. Now this patch has modifications for LLVM (not Clang) and all these 
changes were applied at https://reviews.llvm.org/rL343185 already. Could you 
attach an actual patch brings https://reviews.llvm.org/source/compiler-rt/ 
support to the Clang driver?


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[PATCH] D52619: Fix greedy FileCheck expression in test/Driver/mips-abi.c

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM. Thanks!


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[PATCH] D50850: clang: Add triples support for MIPS r6

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Could you please update the patch against the current trunk?


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[PATCH] D52290: [driver][mips] Adjust target triple accordingly to provided ABI name

[Simon Atanasyan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL343169: [driver][mips] Adjust target triple accordingly to 
provided ABI name (authored by atanasyan, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D52290?vs=167091=167237#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D52290

Files:
  cfe/trunk/lib/Driver/Driver.cpp
  cfe/trunk/test/Driver/mips-abi.c


Index: cfe/trunk/test/Driver/mips-abi.c
===
--- cfe/trunk/test/Driver/mips-abi.c
+++ cfe/trunk/test/Driver/mips-abi.c
@@ -162,3 +162,28 @@
 // RUN:-march=unknown 2>&1 \
 // RUN:   | FileCheck -check-prefix=MIPS-ARCH-UNKNOWN %s
 // MIPS-ARCH-UNKNOWN: error: unknown target CPU 'unknown'
+
+// Check adjusting of target triple accordingly to `-mabi` option.
+// RUN: %clang -target mips64-linux-gnu -mabi=32 -### %s 2>&1 \
+// RUN:   | FileCheck -check-prefix=TARGET-O32 %s
+// TARGET-O32: "-triple" "mips-unknown-linux-gnu"
+// TARGET-O32: "-target-cpu" "mips32r2"
+// TARGET-O32: "-target-abi" "o32"
+// TARGET-O32: ld{{.*}}"
+// TARGET-O32: "-m" "elf32btsmip"
+
+// RUN: %clang -target mips-linux-gnu -mabi=n32 -### %s 2>&1 \
+// RUN:   | FileCheck -check-prefix=TARGET-N32 %s
+// TARGET-N32: "-triple" "mips64-unknown-linux-gnu"
+// TARGET-N32: "-target-cpu" "mips64r2"
+// TARGET-N32: "-target-abi" "n32"
+// TARGET-N32: ld{{.*}}"
+// TARGET-N32: "-m" "elf32btsmipn32"
+
+// RUN: %clang -target mips-linux-gnu -mabi=64 -### %s 2>&1 \
+// RUN:   | FileCheck -check-prefix=TARGET-N64 %s
+// TARGET-N64: "-triple" "mips64-unknown-linux-gnu"
+// TARGET-N64: "-target-cpu" "mips64r2"
+// TARGET-N64: "-target-abi" "n64"
+// TARGET-N64: ld{{.*}}"
+// TARGET-N64: "-m" "elf64btsmip"
Index: cfe/trunk/lib/Driver/Driver.cpp
===
--- cfe/trunk/lib/Driver/Driver.cpp
+++ cfe/trunk/lib/Driver/Driver.cpp
@@ -481,6 +481,16 @@
 Target.setVendorName("intel");
   }
 
+  // If target is MIPS adjust the target triple
+  // accordingly to provided ABI name.
+  A = Args.getLastArg(options::OPT_mabi_EQ);
+  if (A && Target.isMIPS())
+Target = llvm::StringSwitch(A->getValue())
+ .Case("32", Target.get32BitArchVariant())
+ .Case("n32", Target.get64BitArchVariant())
+ .Case("64", Target.get64BitArchVariant())
+ .Default(Target);
+
   return Target;
 }
 


Index: cfe/trunk/test/Driver/mips-abi.c
===
--- cfe/trunk/test/Driver/mips-abi.c
+++ cfe/trunk/test/Driver/mips-abi.c
@@ -162,3 +162,28 @@
 // RUN:-march=unknown 2>&1 \
 // RUN:   | FileCheck -check-prefix=MIPS-ARCH-UNKNOWN %s
 // MIPS-ARCH-UNKNOWN: error: unknown target CPU 'unknown'
+
+// Check adjusting of target triple accordingly to `-mabi` option.
+// RUN: %clang -target mips64-linux-gnu -mabi=32 -### %s 2>&1 \
+// RUN:   | FileCheck -check-prefix=TARGET-O32 %s
+// TARGET-O32: "-triple" "mips-unknown-linux-gnu"
+// TARGET-O32: "-target-cpu" "mips32r2"
+// TARGET-O32: "-target-abi" "o32"
+// TARGET-O32: ld{{.*}}"
+// TARGET-O32: "-m" "elf32btsmip"
+
+// RUN: %clang -target mips-linux-gnu -mabi=n32 -### %s 2>&1 \
+// RUN:   | FileCheck -check-prefix=TARGET-N32 %s
+// TARGET-N32: "-triple" "mips64-unknown-linux-gnu"
+// TARGET-N32: "-target-cpu" "mips64r2"
+// TARGET-N32: "-target-abi" "n32"
+// TARGET-N32: ld{{.*}}"
+// TARGET-N32: "-m" "elf32btsmipn32"
+
+// RUN: %clang -target mips-linux-gnu -mabi=64 -### %s 2>&1 \
+// RUN:   | FileCheck -check-prefix=TARGET-N64 %s
+// TARGET-N64: "-triple" "mips64-unknown-linux-gnu"
+// TARGET-N64: "-target-cpu" "mips64r2"
+// TARGET-N64: "-target-abi" "n64"
+// TARGET-N64: ld{{.*}}"
+// TARGET-N64: "-m" "elf64btsmip"
Index: cfe/trunk/lib/Driver/Driver.cpp
===
--- cfe/trunk/lib/Driver/Driver.cpp
+++ cfe/trunk/lib/Driver/Driver.cpp
@@ -481,6 +481,16 @@
 Target.setVendorName("intel");
   }
 
+  // If target is MIPS adjust the target triple
+  // accordingly to provided ABI name.
+  A = Args.getLastArg(options::OPT_mabi_EQ);
+  if (A && Target.isMIPS())
+Target = llvm::StringSwitch(A->getValue())
+ .Case("32", Target.get32BitArchVariant())
+ .Case("n32", Target.get64BitArchVariant())
+ .Case("64", Target.get64BitArchVariant())
+ .Default(Target);
+
   return Target;
 }
 
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[PATCH] D52290: [driver][mips] Adjust target triple accordingly to provided ABI name

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Thanks for review.


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[PATCH] D52290: [driver][mips] Adjust target triple accordingly to provided ABI name

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added inline comments.



Comment at: lib/Driver/Driver.cpp:492
+ .Case("64", Target.get64BitArchVariant())
+ .Default(Target);
+

rnk wrote:
> We should emit a diagnostic for invalid -mabi=values.
We already do that:

  $ clang -target mips-linux-gnu -c test.c -mabi=xxx
  error: unknown target ABI 'xxx'


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[PATCH] D52290: [driver][mips] Adjust target triple accordingly to provided ABI name

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan updated this revision to Diff 167091.
atanasyan edited the summary of this revision.
atanasyan added a comment.

Always adjust target triple (explicitly and implicitly provided) accordingly to 
ABI name.


Repository:
  rC Clang

https://reviews.llvm.org/D52290

Files:
  lib/Driver/Driver.cpp
  test/Driver/mips-abi.c


Index: test/Driver/mips-abi.c
===
--- test/Driver/mips-abi.c
+++ test/Driver/mips-abi.c
@@ -162,3 +162,28 @@
 // RUN:-march=unknown 2>&1 \
 // RUN:   | FileCheck -check-prefix=MIPS-ARCH-UNKNOWN %s
 // MIPS-ARCH-UNKNOWN: error: unknown target CPU 'unknown'
+
+// Check adjusting of target triple accordingly to `-mabi` option.
+// RUN: %clang -target mips64-linux-gnu -mabi=32 -### %s 2>&1 \
+// RUN:   | FileCheck -check-prefix=TARGET-O32 %s
+// TARGET-O32: "-triple" "mips-unknown-linux-gnu"
+// TARGET-O32: "-target-cpu" "mips32r2"
+// TARGET-O32: "-target-abi" "o32"
+// TARGET-O32: ld{{.*}}"
+// TARGET-O32: "-m" "elf32btsmip"
+
+// RUN: %clang -target mips-linux-gnu -mabi=n32 -### %s 2>&1 \
+// RUN:   | FileCheck -check-prefix=TARGET-N32 %s
+// TARGET-N32: "-triple" "mips64-unknown-linux-gnu"
+// TARGET-N32: "-target-cpu" "mips64r2"
+// TARGET-N32: "-target-abi" "n32"
+// TARGET-N32: ld{{.*}}"
+// TARGET-N32: "-m" "elf32btsmipn32"
+
+// RUN: %clang -target mips-linux-gnu -mabi=64 -### %s 2>&1 \
+// RUN:   | FileCheck -check-prefix=TARGET-N64 %s
+// TARGET-N64: "-triple" "mips64-unknown-linux-gnu"
+// TARGET-N64: "-target-cpu" "mips64r2"
+// TARGET-N64: "-target-abi" "n64"
+// TARGET-N64: ld{{.*}}"
+// TARGET-N64: "-m" "elf64btsmip"
Index: lib/Driver/Driver.cpp
===
--- lib/Driver/Driver.cpp
+++ lib/Driver/Driver.cpp
@@ -481,6 +481,16 @@
 Target.setVendorName("intel");
   }
 
+  // If target is MIPS adjust the target triple
+  // accordingly to provided ABI name.
+  A = Args.getLastArg(options::OPT_mabi_EQ);
+  if (A && Target.isMIPS())
+Target = llvm::StringSwitch(A->getValue())
+ .Case("32", Target.get32BitArchVariant())
+ .Case("n32", Target.get64BitArchVariant())
+ .Case("64", Target.get64BitArchVariant())
+ .Default(Target);
+
   return Target;
 }
 


Index: test/Driver/mips-abi.c
===
--- test/Driver/mips-abi.c
+++ test/Driver/mips-abi.c
@@ -162,3 +162,28 @@
 // RUN:-march=unknown 2>&1 \
 // RUN:   | FileCheck -check-prefix=MIPS-ARCH-UNKNOWN %s
 // MIPS-ARCH-UNKNOWN: error: unknown target CPU 'unknown'
+
+// Check adjusting of target triple accordingly to `-mabi` option.
+// RUN: %clang -target mips64-linux-gnu -mabi=32 -### %s 2>&1 \
+// RUN:   | FileCheck -check-prefix=TARGET-O32 %s
+// TARGET-O32: "-triple" "mips-unknown-linux-gnu"
+// TARGET-O32: "-target-cpu" "mips32r2"
+// TARGET-O32: "-target-abi" "o32"
+// TARGET-O32: ld{{.*}}"
+// TARGET-O32: "-m" "elf32btsmip"
+
+// RUN: %clang -target mips-linux-gnu -mabi=n32 -### %s 2>&1 \
+// RUN:   | FileCheck -check-prefix=TARGET-N32 %s
+// TARGET-N32: "-triple" "mips64-unknown-linux-gnu"
+// TARGET-N32: "-target-cpu" "mips64r2"
+// TARGET-N32: "-target-abi" "n32"
+// TARGET-N32: ld{{.*}}"
+// TARGET-N32: "-m" "elf32btsmipn32"
+
+// RUN: %clang -target mips-linux-gnu -mabi=64 -### %s 2>&1 \
+// RUN:   | FileCheck -check-prefix=TARGET-N64 %s
+// TARGET-N64: "-triple" "mips64-unknown-linux-gnu"
+// TARGET-N64: "-target-cpu" "mips64r2"
+// TARGET-N64: "-target-abi" "n64"
+// TARGET-N64: ld{{.*}}"
+// TARGET-N64: "-m" "elf64btsmip"
Index: lib/Driver/Driver.cpp
===
--- lib/Driver/Driver.cpp
+++ lib/Driver/Driver.cpp
@@ -481,6 +481,16 @@
 Target.setVendorName("intel");
   }
 
+  // If target is MIPS adjust the target triple
+  // accordingly to provided ABI name.
+  A = Args.getLastArg(options::OPT_mabi_EQ);
+  if (A && Target.isMIPS())
+Target = llvm::StringSwitch(A->getValue())
+ .Case("32", Target.get32BitArchVariant())
+ .Case("n32", Target.get64BitArchVariant())
+ .Case("64", Target.get64BitArchVariant())
+ .Default(Target);
+
   return Target;
 }
 
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[PATCH] D52290: [driver][mips] Adjust target triple accordingly to provided ABI name

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

In https://reviews.llvm.org/D52290#1245222, @rnk wrote:

> Should `--target=mipsZZZ -mabi=n64` be meaningful? What does `clang 
> --target=i686-linux-gnu -m64` do? If this matches that, then let's do it.


Thanks. Initially I thought that providing different target triple and `-mabi` 
option explicitly is an error. But now I see that it's better and consistent 
with other targets to adjust a target triple accordingly to `-mabi` options in 
any (implicit/explicit) case. I will update the patch soon.


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[PATCH] D52290: [driver][mips] Adjust target triple accordingly to provided ABI name

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Ping?


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[PATCH] D52418: [driver][mips] Enable integrated assembler for MIPS64 except N32 ABI selected

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan created this revision.
atanasyan added reviewers: rsmith, rnk, zturner.
Herald added subscribers: jrtc27, arichardson, sdardis, srhines.

Enable integrated assembler for MIPS64 targets except N32 ABI explicitly 
selected by the `-mabi=n32` command line option or `mips64(el)-linux-gnuabin32` 
target triple.


Repository:
  rC Clang

https://reviews.llvm.org/D52418

Files:
  include/clang/Driver/ToolChain.h
  lib/Driver/ToolChains/Gnu.cpp
  test/Driver/mips-gnu-integrated-as.c


Index: test/Driver/mips-gnu-integrated-as.c
===
--- /dev/null
+++ test/Driver/mips-gnu-integrated-as.c
@@ -0,0 +1,27 @@
+# Check cases when MIPS cannot use the integrated assembler.
+
+# RUN: %clang -target mips-unknown-gnu -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=INT %s
+# RUN: %clang -target mipsel-unknown-gnu -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=INT %s
+# RUN: %clang -target mips64-unknown-gnu -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=INT %s
+# RUN: %clang -target mips64el-unknown-gnu -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=INT %s
+# RUN: %clang -target mips64-unknown-gnu -mabi=64 -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=INT %s
+# RUN: %clang -target mips64el-unknown-gnu -mabi=64 -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=INT %s
+
+# INT-NOT: "-no-integrated-as"
+
+# RUN: %clang -target mips64-linux-gnuabin32 -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=EXT %s
+# RUN: %clang -target mips64el-linux-gnuabin32 -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=EXT %s
+# RUN: %clang -target mips64-unknown-gnu -mabi=n32 -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=EXT %s
+# RUN: %clang -target mips64el-unknown-gnu -mabi=n32 -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=EXT %s
+
+# EXT: "-no-integrated-as"
Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -2408,15 +2408,9 @@
 return true;
   case llvm::Triple::mips64:
   case llvm::Triple::mips64el:
-// Enabled for Debian, Android, FreeBSD and OpenBSD mips64/mipsel, as they
-// can precisely identify the ABI in use (Debian) or only use N64 for 
MIPS64
-// (Android). Other targets are unable to distinguish N32 from N64.
-if (getTriple().getEnvironment() == llvm::Triple::GNUABI64 ||
-getTriple().isAndroid() ||
-getTriple().isOSFreeBSD() ||
-getTriple().isOSOpenBSD())
-  return true;
-return false;
+// Do not use integrated assembler for N32 ABI only.
+return !tools::mips::hasMipsAbiArg(getArgs(), "n32") &&
+   getTriple().getEnvironment() != llvm::Triple::GNUABIN32;
   default:
 return false;
   }
Index: include/clang/Driver/ToolChain.h
===
--- include/clang/Driver/ToolChain.h
+++ include/clang/Driver/ToolChain.h
@@ -156,6 +156,8 @@
 
   void setTripleEnvironment(llvm::Triple::EnvironmentType Env);
 
+  const llvm::opt::ArgList () const { return Args; };
+
   virtual Tool *buildAssembler() const;
   virtual Tool *buildLinker() const;
   virtual Tool *getTool(Action::ActionClass AC) const;


Index: test/Driver/mips-gnu-integrated-as.c
===
--- /dev/null
+++ test/Driver/mips-gnu-integrated-as.c
@@ -0,0 +1,27 @@
+# Check cases when MIPS cannot use the integrated assembler.
+
+# RUN: %clang -target mips-unknown-gnu -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=INT %s
+# RUN: %clang -target mipsel-unknown-gnu -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=INT %s
+# RUN: %clang -target mips64-unknown-gnu -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=INT %s
+# RUN: %clang -target mips64el-unknown-gnu -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=INT %s
+# RUN: %clang -target mips64-unknown-gnu -mabi=64 -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=INT %s
+# RUN: %clang -target mips64el-unknown-gnu -mabi=64 -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=INT %s
+
+# INT-NOT: "-no-integrated-as"
+
+# RUN: %clang -target mips64-linux-gnuabin32 -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=EXT %s
+# RUN: %clang -target mips64el-linux-gnuabin32 -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=EXT %s
+# RUN: %clang -target mips64-unknown-gnu -mabi=n32 -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=EXT %s
+# RUN: %clang -target mips64el-unknown-gnu -mabi=n32 -### -c %s 2>&1 \
+# RUN:   | FileCheck -check-prefix=EXT %s
+
+# EXT: "-no-integrated-as"
Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -2408,15 +2408,9 @@
 return true;
   case llvm::Triple::mips64:
   case llvm::Triple::mips64el:
-// Enabled for 

[PATCH] D51464: clang: fix MIPS/N32 triple and paths

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan requested changes to this revision.
atanasyan added a comment.
This revision now requires changes to proceed.

This patch fails the following test cases:

- tools/clang/test/CodeGen/target-data.c
- tools/clang/test/Driver/mips-cs.cpp




Comment at: lib/Basic/Targets/Mips.h:75
+  : "n64";
+setABI(getTriple().isMIPS32() ? "o32" : Mips64Abi);
 

Let's write all cases in a uniform manner:
```
if (Triple.isMIPS32())
  setABI("o32");
else if (Triple.getEnvironment() == llvm::Triple::GNUABIN32)
  setABI("n32");
else
  setABI("n64");
```



Comment at: lib/Driver/ToolChains/Arch/Mips.cpp:109
 
+  if (ABIName.empty() && (Triple.getEnvironment() == llvm::Triple::GNUABIN32))
+ABIName = "n32";

What about the following combination of a command line arguments?

  -target mips-mti-linux-gnuabin32 -mips64

In that case, ABIName is empty, Triple.getVendor() returns MipsTechnologies, 
CPUName is "mips64". So ABIName becomes "n64". And this new `if` statement 
doesn't work.



Comment at: lib/Driver/ToolChains/Gnu.cpp:2426
 if (getTriple().getEnvironment() == llvm::Triple::GNUABI64 ||
-getTriple().isAndroid() ||
-getTriple().isOSFreeBSD() ||
+getTriple().getEnvironment() == llvm::Triple::GNUABIN32 ||
+getTriple().isAndroid() || getTriple().isOSFreeBSD() ||

Before this change we enable integrated assembler for mips64/mips64el 
architectures only when we are sure that target ABI is N64. The problem is that 
there are some bugs which do not allow the integrated assembler generates 
correct N32 code in all cases. After this change we enable integrated assembler 
for N32 ABI. I do not think it's a good idea now.

If we can pass command line arguments to this routine, it probably would be 
possible to detect N32 ABI by checking both GNUABIN32  environment and 
`-mabi=n32` option. And disable integrated assembler for MIPS targets in that 
case only. But anyway this change is for another patch.


Repository:
  rC Clang

https://reviews.llvm.org/D51464



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[PATCH] D52290: [driver][mips] Adjust target triple accordingly to provided ABI name

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan created this revision.
atanasyan added reviewers: rsmith, rnk, zturner.
Herald added subscribers: jrtc27, arichardson, sdardis.

All MIPS target architectures can be divided into four categories: 32-bit 
little-endian, 32-bit big-endian, 64-bit little-endian, and 64-bit big-endian. 
If, for example, default target triple used to build compiler is a 
little-endian one, but user wants to generate big-endian output it's enough to 
provide just `-EB` option to implicitly convert default target triple to 
big-endian variant. But it's impossible to implicitly convert 32-bit target 
triple to 64-bit variant and vice versa. In other words, if user has Clang 
built with "mips-linux-gnu" default target triple and wants to generate 64-bit 
output, he or she has to explicitly provide 64-bit target triple 
"mips64-linux-gnu".

  clang -target mips64-linux-gnu -c test.c

While gcc in the same case allows to specify just a correct ABI name.

  gcc -mabi=64 -c test.c

The patch solves this problem. If there is no explicit `-target` option, target 
triple is adjusted accordingly provided ABI name.

For testing this change we need to build Clang with mips default target triple. 
To catch this case (on MIPS buildbot) and ran a corresponding test case I have 
to add new "lit" feature `mips-default-target`.


Repository:
  rC Clang

https://reviews.llvm.org/D52290

Files:
  lib/Driver/Driver.cpp
  test/Driver/mips-target-abi.c
  test/lit.cfg.py


Index: test/lit.cfg.py
===
--- test/lit.cfg.py
+++ test/lit.cfg.py
@@ -136,6 +136,10 @@
 if os.path.exists('/dev/fd/0') and sys.platform not in ['cygwin']:
 config.available_features.add('dev-fd-fs')
 
+# Test that default target triple is mips*
+if re.match(r'^mips*', config.target_triple):
+config.available_features.add('mips-default-target')
+
 # Not set on native MS environment.
 if not re.match(r'.*-(windows-msvc)$', config.target_triple):
 config.available_features.add('non-ms-sdk')
Index: test/Driver/mips-target-abi.c
===
--- /dev/null
+++ test/Driver/mips-target-abi.c
@@ -0,0 +1,24 @@
+// Check default target triple adjusting by ABI option.
+//
+// REQUIRES: mips-default-target
+//
+// RUN: %clang -mabi=32 -### %s 2>&1 | FileCheck -check-prefix=O32 %s
+// O32: "-triple" "mips{{[^"]*}}"
+// O32: "-target-cpu" "mips32r2"
+// O32: "-target-abi" "o32"
+// O32: ld{{.*}}"
+// O32: "-m" "elf32btsmip"
+
+// RUN: %clang -mabi=n32 -### %s 2>&1 | FileCheck -check-prefix=N32 %s
+// N32: "-triple" "mips64{{[^"]*}}"
+// N32: "-target-cpu" "mips64r2"
+// N32: "-target-abi" "n32"
+// N32: ld{{.*}}"
+// N32: "-m" "elf32btsmipn32"
+
+// RUN: %clang -mabi=64 -### %s 2>&1 | FileCheck -check-prefix=N64 %s
+// N64: "-triple" "mips64{{[^"]*}}"
+// N64: "-target-cpu" "mips64r2"
+// N64: "-target-abi" "n64"
+// N64: ld{{.*}}"
+// N64: "-m" "elf64btsmip"
Index: lib/Driver/Driver.cpp
===
--- lib/Driver/Driver.cpp
+++ lib/Driver/Driver.cpp
@@ -481,6 +481,17 @@
 Target.setVendorName("intel");
   }
 
+  // If target is MIPS and there is no explicit `-target` option,
+  // adjust the target triple accordingly to provided ABI name.
+  if (Target.isMIPS() && !Args.getLastArg(options::OPT_target)) {
+if (Arg *A = Args.getLastArg(options::OPT_mabi_EQ))
+  Target = llvm::StringSwitch(A->getValue())
+   .Case("32", Target.get32BitArchVariant())
+   .Case("n32", Target.get64BitArchVariant())
+   .Case("64", Target.get64BitArchVariant())
+   .Default(Target);
+  }
+
   return Target;
 }
 


Index: test/lit.cfg.py
===
--- test/lit.cfg.py
+++ test/lit.cfg.py
@@ -136,6 +136,10 @@
 if os.path.exists('/dev/fd/0') and sys.platform not in ['cygwin']:
 config.available_features.add('dev-fd-fs')
 
+# Test that default target triple is mips*
+if re.match(r'^mips*', config.target_triple):
+config.available_features.add('mips-default-target')
+
 # Not set on native MS environment.
 if not re.match(r'.*-(windows-msvc)$', config.target_triple):
 config.available_features.add('non-ms-sdk')
Index: test/Driver/mips-target-abi.c
===
--- /dev/null
+++ test/Driver/mips-target-abi.c
@@ -0,0 +1,24 @@
+// Check default target triple adjusting by ABI option.
+//
+// REQUIRES: mips-default-target
+//
+// RUN: %clang -mabi=32 -### %s 2>&1 | FileCheck -check-prefix=O32 %s
+// O32: "-triple" "mips{{[^"]*}}"
+// O32: "-target-cpu" "mips32r2"
+// O32: "-target-abi" "o32"
+// O32: ld{{.*}}"
+// O32: "-m" "elf32btsmip"
+
+// RUN: %clang -mabi=n32 -### %s 2>&1 | FileCheck -check-prefix=N32 %s
+// N32: "-triple" "mips64{{[^"]*}}"
+// N32: "-target-cpu" "mips64r2"
+// N32: "-target-abi" "n32"
+// N32: ld{{.*}}"
+// N32: "-m" 

[PATCH] D50850: clang: Add triples support for MIPS r6

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Could you please include more context to patches sent for review?
https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface




Comment at: lib/Driver/ToolChains/Linux.cpp:46
   TargetTriple.getEnvironment();
+  llvm::Triple::SubArchType TargetSubArch = TargetTriple.getSubArch();
   bool IsAndroid = TargetTriple.isAndroid();

Maybe use `bool IsR6` to make the following expressions shorter?



Comment at: lib/Driver/ToolChains/Linux.cpp:111
+(TargetSubArch == llvm::Triple::MipsSubArch_r6) ? "mipsisa32"
+   : "mips";
+if (D.getVFS().exists(SysRoot + "/lib/" + MipsCpu + "-linux-gnu"))

clang-format these lines


Repository:
  rC Clang

https://reviews.llvm.org/D50850



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[PATCH] D51464: clang: fix MIPS/N32 triple and paths

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Could you please include more context to patches sent for review?
https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface




Comment at: lib/Driver/ToolChains/Arch/Mips.cpp:109
 
+  if (ABIName.empty() && (Triple.getEnvironment() == llvm::Triple::GNUABIN32))
+ABIName = "n32";

If target triple is mips-mti-linux-gnuabin32 the code above set (incorrectly) 
the `ABIName` to `n64` and this statement will be `false`.



Comment at: lib/Driver/ToolChains/Linux.cpp:47
   bool IsAndroid = TargetTriple.isAndroid();
+  std::string MipsCpu = "", Mips64Abi = "gnuabi64";
+  if (TargetEnvironment == llvm::Triple::GNUABIN32)

- Do you need `MipsCpu` variable?
- Is it possible to use any lightweight type like `StringRef` for the 
`Mips64Abi`?



Comment at: lib/Driver/ToolChains/Linux.cpp:118
   case llvm::Triple::mips64:
 if (D.getVFS().exists(SysRoot + "/lib/mips64-linux-gnu"))
   return "mips64-linux-gnu";

If a user has two toolchains installed into "/lib/mips64-linux-gnu" and 
"/lib/mips64-linux-gnuabin32", this code always selects mips64-linux-gnu even 
if N32 ABI is requested. Is it intended?


Repository:
  rC Clang

https://reviews.llvm.org/D51464



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[PATCH] D51356: [docs][mips] Clang 7.0 Release notes

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Thanks for review.


Repository:
  rL LLVM

https://reviews.llvm.org/D51356



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[PATCH] D51356: [docs][mips] Clang 7.0 Release notes

[Simon Atanasyan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL341201: [docs][mips] Clang 7.0 Release notes (authored by 
atanasyan, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D51356?vs=162850=163501#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D51356

Files:
  cfe/branches/release_70/docs/ReleaseNotes.rst


Index: cfe/branches/release_70/docs/ReleaseNotes.rst
===
--- cfe/branches/release_70/docs/ReleaseNotes.rst
+++ cfe/branches/release_70/docs/ReleaseNotes.rst
@@ -114,6 +114,12 @@
   relocation scanning. The ``-faddrsig`` and ``-fno-addrsig`` flags can be
   used to control whether to emit the address-significance table.
 
+- Integrated assembler is enabled by default on OpenBSD / FreeBSD
+  for MIPS 64-bit targets.
+
+- On MIPS FreeBSD default CPUs have been changed to ``mips2``
+  for 32-bit targets and ``mips3`` for 64-bit targets.
+
 - ...
 
 New Compiler Flags
@@ -133,6 +139,15 @@
modules where it isn't necessary. It causes more inline virtual functions
to be emitted.
 
+- Added the``-mcrc`` and ``-mno-crc`` flags to enable/disable using
+  of MIPS Cyclic Redundancy Check instructions.
+
+- Added the``-mvirt`` and ``-mno-virt`` flags to enable/disable using
+  of MIPS Virtualization instructions.
+
+- Added the``-mginv`` and ``-mno-ginv`` flags to enable/disable using
+  of MIPS Global INValidate instructions.
+
 - ...
 
 Deprecated Compiler Flags


Index: cfe/branches/release_70/docs/ReleaseNotes.rst
===
--- cfe/branches/release_70/docs/ReleaseNotes.rst
+++ cfe/branches/release_70/docs/ReleaseNotes.rst
@@ -114,6 +114,12 @@
   relocation scanning. The ``-faddrsig`` and ``-fno-addrsig`` flags can be
   used to control whether to emit the address-significance table.
 
+- Integrated assembler is enabled by default on OpenBSD / FreeBSD
+  for MIPS 64-bit targets.
+
+- On MIPS FreeBSD default CPUs have been changed to ``mips2``
+  for 32-bit targets and ``mips3`` for 64-bit targets.
+
 - ...
 
 New Compiler Flags
@@ -133,6 +139,15 @@
modules where it isn't necessary. It causes more inline virtual functions
to be emitted.
 
+- Added the``-mcrc`` and ``-mno-crc`` flags to enable/disable using
+  of MIPS Cyclic Redundancy Check instructions.
+
+- Added the``-mvirt`` and ``-mno-virt`` flags to enable/disable using
+  of MIPS Virtualization instructions.
+
+- Added the``-mginv`` and ``-mno-ginv`` flags to enable/disable using
+  of MIPS Global INValidate instructions.
+
 - ...
 
 Deprecated Compiler Flags
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[PATCH] D51358: [driver] Do not pass "-flavor old-gnu" option to LLD linker

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan closed this revision.
atanasyan added a comment.

Fixed by https://reviews.llvm.org/rL340845.


Repository:
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https://reviews.llvm.org/D51358



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[PATCH] D51358: [driver] Do not pass "-flavor old-gnu" option to LLD linker

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan created this revision.
atanasyan added reviewers: echristo, ruiu.

The "-flavor old-gnu" option were introduced to enable old version of LLD ELF 
linker implementation. This option has been removed from the linker since LLD 
3.9. I do not think that there is a real case when the latest version of Clang 
is used in combination with so obsoleted version of LLD linker. Now we can 
remove support of this option from the driver.


Repository:
  rC Clang

https://reviews.llvm.org/D51358

Files:
  lib/Driver/ToolChains/Gnu.cpp


Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -323,14 +323,6 @@
   // handled somewhere else.
   Args.ClaimAllArgs(options::OPT_w);
 
-  const char *Exec = Args.MakeArgString(ToolChain.GetLinkerPath());
-  if (llvm::sys::path::stem(Exec) == "lld") {
-CmdArgs.push_back("-flavor");
-CmdArgs.push_back("old-gnu");
-CmdArgs.push_back("-target");
-CmdArgs.push_back(Args.MakeArgString(getToolChain().getTripleString()));
-  }
-
   if (!D.SysRoot.empty())
 CmdArgs.push_back(Args.MakeArgString("--sysroot=" + D.SysRoot));
 
@@ -539,6 +531,7 @@
   AddHIPLinkerScript(getToolChain(), C, Output, Inputs, Args, CmdArgs, JA,
  *this);
 
+  const char *Exec = Args.MakeArgString(ToolChain.GetLinkerPath());
   C.addCommand(llvm::make_unique(JA, *this, Exec, CmdArgs, Inputs));
 }
 


Index: lib/Driver/ToolChains/Gnu.cpp
===
--- lib/Driver/ToolChains/Gnu.cpp
+++ lib/Driver/ToolChains/Gnu.cpp
@@ -323,14 +323,6 @@
   // handled somewhere else.
   Args.ClaimAllArgs(options::OPT_w);
 
-  const char *Exec = Args.MakeArgString(ToolChain.GetLinkerPath());
-  if (llvm::sys::path::stem(Exec) == "lld") {
-CmdArgs.push_back("-flavor");
-CmdArgs.push_back("old-gnu");
-CmdArgs.push_back("-target");
-CmdArgs.push_back(Args.MakeArgString(getToolChain().getTripleString()));
-  }
-
   if (!D.SysRoot.empty())
 CmdArgs.push_back(Args.MakeArgString("--sysroot=" + D.SysRoot));
 
@@ -539,6 +531,7 @@
   AddHIPLinkerScript(getToolChain(), C, Output, Inputs, Args, CmdArgs, JA,
  *this);
 
+  const char *Exec = Args.MakeArgString(ToolChain.GetLinkerPath());
   C.addCommand(llvm::make_unique(JA, *this, Exec, CmdArgs, Inputs));
 }
 
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[PATCH] D51356: [docs][mips] Clang 7.0 Release notes

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan created this revision.
atanasyan added reviewers: hans, petarj, smaksimovic, abeserminji.
Herald added subscribers: arichardson, sdardis.

MIPS specific part of Clang 7.0 Release notes. Feel free to add more notes if I 
miss something.


Repository:
  rC Clang

https://reviews.llvm.org/D51356

Files:
  ReleaseNotes.rst


Index: ReleaseNotes.rst
===
--- ReleaseNotes.rst
+++ ReleaseNotes.rst
@@ -114,6 +114,12 @@
   relocation scanning. The ``-faddrsig`` and ``-fno-addrsig`` flags can be
   used to control whether to emit the address-significance table.
 
+- Integrated assembler is enabled by default on OpenBSD / FreeBSD
+  for MIPS 64-bit targets.
+
+- On MIPS FreeBSD default CPUs have been changed to ``mips2``
+  for 32-bit targets and ``mips3`` for 32-bit targets.
+
 - ...
 
 New Compiler Flags
@@ -133,6 +139,15 @@
modules where it isn't necessary. It causes more inline virtual functions
to be emitted.
 
+- Added the``-mcrc`` and ``-mno-crc`` flags to enable/disable using
+  of MIPS Cyclic Redundancy Check instructions.
+
+- Added the``-mvirt`` and ``-mno-virt`` flags to enable/disable using
+  of MIPS Virtualization instructions.
+
+- Added the``-mginv`` and ``-mno-ginv`` flags to enable/disable using
+  of MIPS Global INValidate instructions.
+
 - ...
 
 Deprecated Compiler Flags


Index: ReleaseNotes.rst
===
--- ReleaseNotes.rst
+++ ReleaseNotes.rst
@@ -114,6 +114,12 @@
   relocation scanning. The ``-faddrsig`` and ``-fno-addrsig`` flags can be
   used to control whether to emit the address-significance table.
 
+- Integrated assembler is enabled by default on OpenBSD / FreeBSD
+  for MIPS 64-bit targets.
+
+- On MIPS FreeBSD default CPUs have been changed to ``mips2``
+  for 32-bit targets and ``mips3`` for 32-bit targets.
+
 - ...
 
 New Compiler Flags
@@ -133,6 +139,15 @@
modules where it isn't necessary. It causes more inline virtual functions
to be emitted.
 
+- Added the``-mcrc`` and ``-mno-crc`` flags to enable/disable using
+  of MIPS Cyclic Redundancy Check instructions.
+
+- Added the``-mvirt`` and ``-mno-virt`` flags to enable/disable using
+  of MIPS Virtualization instructions.
+
+- Added the``-mginv`` and ``-mno-ginv`` flags to enable/disable using
+  of MIPS Global INValidate instructions.
+
 - ...
 
 Deprecated Compiler Flags
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[PATCH] D51234: [Driver] Change MipsLinux default linker from "lld" to "ld.lld"

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

In https://reviews.llvm.org/D51234#1213813, @ruiu wrote:

> If this piece of code used to be working correctly, there is another piece of 
> code that adds `-flavor ld` to the command line. But if that's the case, this 
> change wouldn't work because it constructs something like "ld.lld -flavor ld 
> ...". ld.lld doesn't accept `-flavor` option.
>
> So my guess is this code is dead. Or, am I missing something?


The `tools::gnutools::Linker::ConstructJob` method contains code which adds 
`-flavor old-gnu` command line option if linker name is "lld". Probably this 
code can be removed now.


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[PATCH] D51234: [Driver] Change MipsLinux default linker from "lld" to "ld.lld"

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D50557: [clang][mips] Set __mips_fpr correctly for -mfpxx

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D50557: [clang][mips] Set __mips_fpr correctly for -mfpxx

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added inline comments.



Comment at: lib/Basic/Targets/Mips.cpp:141
+  Twine(32 / (FPMode == FP64 || IsSingleFloat ? 1 : 2)));
 
   if (IsMips16)

What do you think about this variant of the code? It's longer, but imho looks 
more clear.
```
switch (FPMode) {
case FPXX:
  Builder.defineMacro("__mips_fpr", Twine(0));
  break;
case FP32:
  Builder.defineMacro("__mips_fpr", Twine(32));
  break;
case FP64:
  Builder.defineMacro("__mips_fpr", Twine(64));
  break;
}

if (FPMode == FP64 || IsSingleFloat)
  Builder.defineMacro("_MIPS_FPSET", Twine(32));
else
  Builder.defineMacro("_MIPS_FPSET", Twine(16));
```


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[PATCH] D50850: clang: Add triples support for MIPS r6

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Could you add test cases to cover these changes?




Comment at: lib/Driver/ToolChains/Arch/Mips.cpp:115
+  if (ABIName.empty() && (Triple.getEnvironment() == llvm::Triple::GNUABIN32))
+ABIName = "n32";
+

It looks like this change is unrelated to introducing new target triples and 
can be made by a separate commit.



Comment at: lib/Driver/ToolChains/Gnu.cpp:2068
 BiarchTripleAliases.append(begin(MIPS64Triples), end(MIPS64Triples));
+BiarchLibDirs.append(begin(MIPSN32LibDirs), end(MIPSN32LibDirs));
+BiarchTripleAliases.append(begin(MIPSN32Triples), end(MIPSN32Triples));

Ditto



Comment at: lib/Driver/ToolChains/Gnu.cpp:2077
 BiarchTripleAliases.append(begin(MIPS64ELTriples), end(MIPS64ELTriples));
+BiarchLibDirs.append(begin(MIPSN32ELLibDirs), end(MIPSN32ELLibDirs));
+BiarchTripleAliases.append(begin(MIPSN32ELTriples), end(MIPSN32ELTriples));

Ditto



Comment at: lib/Driver/ToolChains/Gnu.cpp:2085
 BiarchTripleAliases.append(begin(MIPSTriples), end(MIPSTriples));
+BiarchLibDirs.append(begin(MIPSN32LibDirs), end(MIPSN32LibDirs));
+BiarchTripleAliases.append(begin(MIPSN32Triples), end(MIPSN32Triples));

Ditto



Comment at: lib/Driver/ToolChains/Gnu.cpp:2093
 BiarchTripleAliases.append(begin(MIPSELTriples), end(MIPSELTriples));
-BiarchTripleAliases.append(begin(MIPSTriples), end(MIPSTriples));
+BiarchLibDirs.append(begin(MIPSN32ELLibDirs), end(MIPSN32ELLibDirs));
+BiarchTripleAliases.append(begin(MIPSN32ELTriples), end(MIPSN32ELTriples));

Ditto



Comment at: lib/Driver/ToolChains/Gnu.cpp:2437
 if (getTriple().getEnvironment() == llvm::Triple::GNUABI64 ||
-getTriple().isAndroid() ||
-getTriple().isOSFreeBSD() ||
+getTriple().getEnvironment() == llvm::Triple::GNUABIN32 ||
+getTriple().isAndroid() || getTriple().isOSFreeBSD() ||

Are you sure that integrated LLVM assembler is ready to support N32 code 
generation? Anyway this change is for  a separate patch.



Comment at: lib/Driver/ToolChains/Linux.cpp:126
   return "mips64-linux-gnu";
-if (D.getVFS().exists(SysRoot + "/lib/mips64-linux-gnuabi64"))
-  return "mips64-linux-gnuabi64";
+MipsCpu = (TargetSubArch == llvm::Triple::MipsSubArch_r6) ? "mipsisa64"
+  : "mips64";

Suppose there are both "/lib/mips64-linux-gnu" and 
"/lib/mipsisa64-linux-gnuabi64" paths on a disk and provided target triple is 
mipsisa64-linux-gnuabi64. Is it good that we return "mips64-linux-gnu" from 
this function anyway?


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[PATCH] D50557: [clang][mips] Set __mips_fpr correctly for -mfpxx

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Any test cases?




Comment at: lib/Basic/Targets/Mips.cpp:62
 
+unsigned MipsTargetInfo::getISARev(const std::string& CPU) const {
+  return llvm::StringSwitch(getCPU())

The CPU argument looks unused. We can either remove it or make this routine a 
non-member static function. Probably we can change the CPU’s type to StringRef.



Comment at: lib/Basic/Targets/Mips.cpp:97
 
-  const std::string ISARev = llvm::StringSwitch(getCPU())
- .Cases("mips32", "mips64", "1")
- .Cases("mips32r2", "mips64r2", "2")
- .Cases("mips32r3", "mips64r3", "3")
- .Cases("mips32r5", "mips64r5", "5")
- .Cases("mips32r6", "mips64r6", "6")
- .Default("");
+  const std::string ISARev = std::to_string(getISARev(getCPU()));
+

Is this change required for the fix? It looks like a refactoring and maybe done 
by a separate commit.



Comment at: lib/Basic/Targets/Mips.h:61
   bool HasFP64;
+  bool HasFPXX;
   std::string ABI;

Maybe replace these two boolean flags by a single enumeration. Something like 
FPXX, FP32, FP64.


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[PATCH] D49289: [mips64][clang] Provide the signext attribute for i32 return values

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D49143: Fix a typo/regression in r335495.

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D48982: [mips] Add '-mvirt', '-mno-virt', '-mginv', '-mno-ginv' options

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D49143: Fix a typo/regression in r335495.

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

It would be nice to have a test for this regression.


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[PATCH] D48507: [mips] Explicitly specify the linker emulation for MIPS on FreeBSD.

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added inline comments.
This revision is now accepted and ready to land.



Comment at: lib/Driver/ToolChains/FreeBSD.cpp:197
+CmdArgs.push_back("-m");
+CmdArgs.push_back("elf64ltsmip_fbsd");
+break;

bsdjhb wrote:
> atanasyan wrote:
> > Does it make a sense to handle N32 ABI case here?
> For whatever reason, FreeBSD only supports N32 on big-endian.  However, 
> binutils does ship elf32ltsmipsn32_fbsd linker scripts after all, so I could 
> handle little-endian N32 here.
LGTM with handling the elf32ltsmipsn32_fbsd case.


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[PATCH] D48499: [mips] Use more conservative default CPUs for MIPS on FreeBSD.

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D48515: [mips][ias] Enable IAS by default for OpenBSD / FreeBSD mips64/mips64el.

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

LGTM, but before commit please add a test case into the freebsd.c.


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[PATCH] D48507: [mips] Explicitly specify the linker emulation for MIPS on FreeBSD.

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added inline comments.



Comment at: lib/Driver/ToolChains/FreeBSD.cpp:197
+CmdArgs.push_back("-m");
+CmdArgs.push_back("elf64ltsmip_fbsd");
+break;

Does it make a sense to handle N32 ABI case here?


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[PATCH] D48549: Use Triple::isMIPS() instead of enumerating all Triples. NFC

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM. the only minor nit




Comment at: lib/Driver/ToolChains/FreeBSD.cpp:321
   // back to '/usr/lib' if it doesn't exist.
-  if ((Triple.getArch() == llvm::Triple::x86 ||
-   Triple.getArch() == llvm::Triple::mips ||
-   Triple.getArch() == llvm::Triple::mipsel ||
-   Triple.getArch() == llvm::Triple::ppc) &&
+  if ((Triple.getArch() == llvm::Triple::x86 || Triple.isMIPS32() || 
Triple.getArch() == llvm::Triple::ppc) &&
   D.getVFS().exists(getDriver().SysRoot + "/usr/lib32/crt1.o"))

Too long line.


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[PATCH] D48169: [mips] Add '-mcrc', '-mno-crc' options to enable/disable CRC ASE

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added inline comments.
This revision is now accepted and ready to land.



Comment at: include/clang/Driver/Options.td:2214
   HelpText<"Disable SVR4-style position-independent code (Mips only)">;
+def mno_crc : Flag<["-"], "mno-crc">, Group,
+  HelpText<"Disallow use of CRC instructions (Mips only)">;

sdardis wrote:
> atanasyan wrote:
> > Does it make a sense to define this option as an alias to the `mnocrc` and 
> > allow to use both `-mno-crc` and `-mnocrc` for ARM and MIPS?
> I thought about commenting on that. The problem there is that you then 
> permitting clang to be more lax than binutils which inhibits compatibility 
> between the two tools.
> The problem there is that you then permitting clang to be more lax than 
> binutils which inhibits compatibility between the two tools.

Good point. Agreed.




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[PATCH] D48169: [mips] Add '-mcrc', '-mno-crc' options to enable/disable CRC ASE

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added inline comments.



Comment at: include/clang/Driver/Options.td:2214
   HelpText<"Disable SVR4-style position-independent code (Mips only)">;
+def mno_crc : Flag<["-"], "mno-crc">, Group,
+  HelpText<"Disallow use of CRC instructions (Mips only)">;

Does it make a sense to define this option as an alias to the `mnocrc` and 
allow to use both `-mno-crc` and `-mnocrc` for ARM and MIPS?


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[PATCH] D46450: [Driver] Add mips_Features_Group to Options to improve documentation sorting

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Committed at https://reviews.llvm.org/rL331856.

Thanks for the patch.


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[PATCH] D46450: [Driver] Add mips_Features_Group to Options to improve documentation sorting

[Simon Atanasyan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL331856: [driver] Add mips_Features_Group to Options to 
improve documentation sorting (authored by atanasyan, committed by ).
Herald added a subscriber: llvm-commits.

Changed prior to commit:
  https://reviews.llvm.org/D46450?vs=145256=145879#toc

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Files:
  cfe/trunk/include/clang/Driver/Options.td

Index: cfe/trunk/include/clang/Driver/Options.td
===
--- cfe/trunk/include/clang/Driver/Options.td
+++ cfe/trunk/include/clang/Driver/Options.td
@@ -143,14 +143,16 @@
 // These are explicitly handled.
 def m_hexagon_Features_HVX_Group : OptionGroup<"">,
Group, DocName<"Hexagon">;
+def m_mips_Features_Group : OptionGroup<"">,
+Group, DocName<"MIPS">;
 def m_ppc_Features_Group : OptionGroup<"">,
Group, DocName<"PowerPC">;
 def m_wasm_Features_Group : OptionGroup<"">,
 Group, DocName<"WebAssembly">;
 def m_x86_Features_Group : OptionGroup<"">,
Group, Flags<[CoreOption]>, DocName<"X86">;
 
-def m_libc_Group : OptionGroup<"">, Group,
+def m_libc_Group : OptionGroup<"">, Group,
Flags<[HelpHidden]>;
 
 def O_Group : OptionGroup<"">, Group,
@@ -2094,127 +2096,135 @@
 def mno_pie_copy_relocations : Flag<["-"], "mno-pie-copy-relocations">, Group;
 def mfentry : Flag<["-"], "mfentry">, HelpText<"Insert calls to fentry at function entry (x86 only)">,
   Flags<[CC1Option]>, Group;
-def mips16 : Flag<["-"], "mips16">, Group;
-def mno_mips16 : Flag<["-"], "mno-mips16">, Group;
-def mmicromips : Flag<["-"], "mmicromips">, Group;
-def mno_micromips : Flag<["-"], "mno-micromips">, Group;
-def mxgot : Flag<["-"], "mxgot">, Group;
-def mno_xgot : Flag<["-"], "mno-xgot">, Group;
-def mldc1_sdc1 : Flag<["-"], "mldc1-sdc1">, Group;
-def mno_ldc1_sdc1 : Flag<["-"], "mno-ldc1-sdc1">, Group;
-def mcheck_zero_division : Flag<["-"], "mcheck-zero-division">, Group;
+def mips16 : Flag<["-"], "mips16">, Group;
+def mno_mips16 : Flag<["-"], "mno-mips16">, Group;
+def mmicromips : Flag<["-"], "mmicromips">, Group;
+def mno_micromips : Flag<["-"], "mno-micromips">, Group;
+def mxgot : Flag<["-"], "mxgot">, Group;
+def mno_xgot : Flag<["-"], "mno-xgot">, Group;
+def mldc1_sdc1 : Flag<["-"], "mldc1-sdc1">, Group;
+def mno_ldc1_sdc1 : Flag<["-"], "mno-ldc1-sdc1">, Group;
+def mcheck_zero_division : Flag<["-"], "mcheck-zero-division">,
+   Group;
 def mno_check_zero_division : Flag<["-"], "mno-check-zero-division">,
-  Group;
-def mcompact_branches_EQ : Joined<["-"], "mcompact-branches=">, Group;
+  Group;
+def mcompact_branches_EQ : Joined<["-"], "mcompact-branches=">,
+   Group;
 def mbranch_likely : Flag<["-"], "mbranch-likely">, Group,
   IgnoredGCCCompat;
 def mno_branch_likely : Flag<["-"], "mno-branch-likely">, Group,
   IgnoredGCCCompat;
 def mindirect_jump_EQ : Joined<["-"], "mindirect-jump=">,
-  Group,
+  Group,
   HelpText<"Change indirect jump instructions to inhibit speculation">;
-def mdsp : Flag<["-"], "mdsp">, Group;
-def mno_dsp : Flag<["-"], "mno-dsp">, Group;
-def mdspr2 : Flag<["-"], "mdspr2">, Group;
-def mno_dspr2 : Flag<["-"], "mno-dspr2">, Group;
-def msingle_float : Flag<["-"], "msingle-float">, Group;
-def mdouble_float : Flag<["-"], "mdouble-float">, Group;
-def mmadd4 : Flag<["-"], "mmadd4">, Group,
+def mdsp : Flag<["-"], "mdsp">, Group;
+def mno_dsp : Flag<["-"], "mno-dsp">, Group;
+def mdspr2 : Flag<["-"], "mdspr2">, Group;
+def mno_dspr2 : Flag<["-"], "mno-dspr2">, Group;
+def msingle_float : Flag<["-"], "msingle-float">, Group;
+def mdouble_float : Flag<["-"], "mdouble-float">, Group;
+def mmadd4 : Flag<["-"], "mmadd4">, Group,
   HelpText<"Enable the generation of 4-operand madd.s, madd.d and related instructions.">;
-def mno_madd4 : Flag<["-"], "mno-madd4">, Group,
+def mno_madd4 : Flag<["-"], "mno-madd4">, Group,
   HelpText<"Disable the generation of 4-operand madd.s, madd.d and related instructions.">;
-def mmsa : Flag<["-"], "mmsa">, Group,
+def mmsa : Flag<["-"], "mmsa">, Group,
   HelpText<"Enable MSA ASE (MIPS only)">;
-def mno_msa : Flag<["-"], "mno-msa">, Group,
+def mno_msa : Flag<["-"], "mno-msa">, Group,
   HelpText<"Disable MSA ASE (MIPS only)">;
-def mmt : Flag<["-"], "mmt">, Group,
+def mmt : Flag<["-"], "mmt">, Group,
   HelpText<"Enable MT ASE (MIPS only)">;
-def mno_mt : Flag<["-"], "mno-mt">, Group,
+def mno_mt : Flag<["-"], "mno-mt">, Group,
   HelpText<"Disable MT ASE (MIPS only)">;
-def mfp64 : Flag<["-"], "mfp64">, Group,
+def mfp64 : Flag<["-"], "mfp64">, Group,
   HelpText<"Use 64-bit floating point registers (MIPS only)">;
-def mfp32 : Flag<["-"], "mfp32">, Group,
+def mfp32 : Flag<["-"], "mfp32">, Group,
   

[PATCH] D46450: [Driver] Add mips_Features_Group to Options to improve documentation sorting

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM

Do you have commit access?


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[PATCH] D44447: Treat libclang_rt.* as normal library if the user uses --sysroot=

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added a comment.

Will it work on Windows? If sysroot is provided, `Prefix` is "-l", but I'm not 
sure that link.exe accepts "-l" notation.


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[PATCH] D43487: [mips] Spectre variant two mitigation for MIPSR2

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM


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[PATCH] D42416: [Driver] Add support for mips32 and scudo

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM


Repository:
  rC Clang

https://reviews.llvm.org/D42416



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[PATCH] D38168: [mips] Accept but ignore -m(no-)branch-likely

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan accepted this revision.
atanasyan added a comment.
This revision is now accepted and ready to land.

LGTM


https://reviews.llvm.org/D38168



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[PATCH] D36551: [mips] Show warning in case of mixing -mlong-calls and -mabicalls options

[Simon Atanasyan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL310614: [mips] Show warning in case of mixing -mlong-calls 
and -mabicalls options (authored by atanasyan).

Changed prior to commit:
  https://reviews.llvm.org/D36551?vs=110562=110586#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D36551

Files:
  cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
  cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
  cfe/trunk/test/Driver/mips-features.c
  cfe/trunk/test/Driver/mips-longcalls-warning.c


Index: cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
===
--- cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
+++ cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
@@ -292,6 +292,10 @@
   "ignoring '-mgpopt' option as it cannot be used with %select{|the implicit"
   " usage of }0-mabicalls">,
   InGroup;
+def warn_drv_unsupported_longcalls : Warning<
+  "ignoring '-mlong-calls' option as it is not currently supported with "
+  "%select{|the implicit usage of }0-mabicalls">,
+  InGroup;
 def warn_drv_unsupported_abicalls : Warning<
   "ignoring '-mabicalls' option as it cannot be used with "
   "non position-independent code and the N64 ABI">,
Index: cfe/trunk/test/Driver/mips-features.c
===
--- cfe/trunk/test/Driver/mips-features.c
+++ cfe/trunk/test/Driver/mips-features.c
@@ -336,12 +336,16 @@
 // CHECK-IMG-SINGLEFLOAT-FPXX: "-target-feature" "+fpxx"
 
 // -mlong-call
-// RUN: %clang -target mips-img-linux-gnu -### -c %s -mlong-calls 2>&1 \
+// RUN: %clang -target mips-img-linux-gnu -### -c %s \
+// RUN:-mno-abicalls -mlong-calls 2>&1 \
 // RUN:   | FileCheck --check-prefix=LONG-CALLS-ON %s
-// RUN: %clang -target mips-img-linux-gnu -### -c %s -mno-long-calls 2>&1 \
+// RUN: %clang -target mips-img-linux-gnu -### -c %s \
+// RUN:-mno-abicalls -mno-long-calls 2>&1 \
 // RUN:   | FileCheck --check-prefix=LONG-CALLS-OFF %s
 // RUN: %clang -target mips-img-linux-gnu -### -c %s 2>&1 \
 // RUN:   | FileCheck --check-prefix=LONG-CALLS-DEF %s
+// RUN: %clang -target mips-img-linux-gnu -### -c %s -mlong-calls 2>&1 \
+// RUN:   | FileCheck --check-prefix=LONG-CALLS-DEF %s
 // LONG-CALLS-ON: "-target-feature" "+long-calls"
 // LONG-CALLS-OFF: "-target-feature" "-long-calls"
 // LONG-CALLS-DEF-NOT: "long-calls"
Index: cfe/trunk/test/Driver/mips-longcalls-warning.c
===
--- cfe/trunk/test/Driver/mips-longcalls-warning.c
+++ cfe/trunk/test/Driver/mips-longcalls-warning.c
@@ -0,0 +1,6 @@
+// REQUIRES: mips-registered-target
+// RUN: %clang -### -c -target mips-mti-elf -mlong-calls %s 2>&1 | FileCheck 
-check-prefix=IMPLICIT %s
+// IMPLICIT: warning: ignoring '-mlong-calls' option as it is not currently 
supported with the implicit usage of -mabicalls
+
+// RUN: %clang -### -c -target mips-mti-elf -mlong-calls -mabicalls %s 2>&1 | 
FileCheck -check-prefix=EXPLICIT %s
+// EXPLICIT: warning: ignoring '-mlong-calls' option as it is not currently 
supported with -mabicalls
Index: cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
===
--- cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
+++ cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -245,6 +245,16 @@
   else
 Features.push_back("-noabicalls");
 
+  if (Arg *A = Args.getLastArg(options::OPT_mlong_calls,
+   options::OPT_mno_long_calls)) {
+if (A->getOption().matches(options::OPT_mno_long_calls))
+  Features.push_back("-long-calls");
+else if (!UseAbiCalls)
+  Features.push_back("+long-calls");
+else
+  D.Diag(diag::warn_drv_unsupported_longcalls) << (ABICallsArg ? 0 : 1);
+  }
+
   mips::FloatABI FloatABI = mips::getMipsFloatABI(D, Args);
   if (FloatABI == mips::FloatABI::Soft) {
 // FIXME: Note, this is a hack. We need to pass the selected float
@@ -309,8 +319,6 @@
 
   AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
options::OPT_modd_spreg, "nooddspreg");
-  AddTargetFeature(Args, Features, options::OPT_mlong_calls,
-   options::OPT_mno_long_calls, "long-calls");
   AddTargetFeature(Args, Features, options::OPT_mmt, options::OPT_mno_mt, 
"mt");
 }
 


Index: cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
===
--- cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
+++ cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
@@ -292,6 +292,10 @@
   "ignoring '-mgpopt' option as it cannot be used with %select{|the implicit"
   " usage of }0-mabicalls">,
   InGroup;
+def warn_drv_unsupported_longcalls : Warning<
+  "ignoring '-mlong-calls' option as it is not currently supported with "
+  "%select{|the implicit usage of }0-mabicalls">,
+  InGroup;
 def warn_drv_unsupported_abicalls : 

[PATCH] D36550: [mips] Notify user that `-mabicalls` is ignored on non-PIC N64 ABI

[Simon Atanasyan via Phabricator via cfe-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL310613: [mips] Notify user that `-mabicalls` is ignored on 
non-PIC N64 ABI (authored by atanasyan).

Changed prior to commit:
  https://reviews.llvm.org/D36550?vs=110561=110585#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D36550

Files:
  cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
  cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
  cfe/trunk/test/Driver/mips-abicalls-warning.c
  cfe/trunk/test/Driver/mips-features.c


Index: cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
===
--- cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
+++ cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -227,11 +227,23 @@
  O.matches(options::OPT_fno_PIE) || O.matches(options::OPT_fno_pie));
   }
 
-  if (IsN64 && NonPIC)
+  bool UseAbiCalls = false;
+
+  Arg *ABICallsArg =
+  Args.getLastArg(options::OPT_mabicalls, options::OPT_mno_abicalls);
+  UseAbiCalls =
+  !ABICallsArg ||
+  (ABICallsArg && 
ABICallsArg->getOption().matches(options::OPT_mabicalls));
+
+  if (UseAbiCalls && IsN64 && NonPIC) {
+D.Diag(diag::warn_drv_unsupported_abicalls);
+UseAbiCalls = false;
+  }
+
+  if (!UseAbiCalls)
 Features.push_back("+noabicalls");
   else
-AddTargetFeature(Args, Features, options::OPT_mno_abicalls,
- options::OPT_mabicalls, "noabicalls");
+Features.push_back("-noabicalls");
 
   mips::FloatABI FloatABI = mips::getMipsFloatABI(D, Args);
   if (FloatABI == mips::FloatABI::Soft) {
Index: cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
===
--- cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
+++ cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
@@ -292,6 +292,10 @@
   "ignoring '-mgpopt' option as it cannot be used with %select{|the implicit"
   " usage of }0-mabicalls">,
   InGroup;
+def warn_drv_unsupported_abicalls : Warning<
+  "ignoring '-mabicalls' option as it cannot be used with "
+  "non position-independent code and the N64 ABI">,
+  InGroup;
 
 def warn_drv_unable_to_find_directory_expected : Warning<
   "unable to find %0 directory, expected to be in '%1'">,
Index: cfe/trunk/test/Driver/mips-features.c
===
--- cfe/trunk/test/Driver/mips-features.c
+++ cfe/trunk/test/Driver/mips-features.c
@@ -10,6 +10,11 @@
 // RUN:   | FileCheck --check-prefix=CHECK-MNOABICALLS %s
 // CHECK-MNOABICALLS: "-target-feature" "+noabicalls"
 //
+// -mno-abicalls non-PIC N64
+// RUN: %clang -target mips64-linux-gnu -### -c -fno-PIC %s 2>&1 \
+// RUN:   | FileCheck --check-prefix=CHECK-MNOABICALLS-N64NPIC %s
+// CHECK-MNOABICALLS-N64NPIC: "-target-feature" "+noabicalls"
+//
 // -mgpopt
 // RUN: %clang -target mips-linux-gnu -### -c %s -mno-gpopt -mgpopt 
-Wno-unsupported-gpopt 2>&1 \
 // RUN:   | FileCheck --check-prefix=CHECK-MGPOPT-DEF-ABICALLS %s
Index: cfe/trunk/test/Driver/mips-abicalls-warning.c
===
--- cfe/trunk/test/Driver/mips-abicalls-warning.c
+++ cfe/trunk/test/Driver/mips-abicalls-warning.c
@@ -0,0 +1,3 @@
+// REQUIRES: mips-registered-target
+// RUN: %clang -### -c -target mips64-mti-elf -fno-PIC -mabicalls %s 2>&1 | 
FileCheck %s
+// CHECK: warning: ignoring '-mabicalls' option as it cannot be used with non 
position-independent code and the N64 ABI


Index: cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
===
--- cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
+++ cfe/trunk/lib/Driver/ToolChains/Arch/Mips.cpp
@@ -227,11 +227,23 @@
  O.matches(options::OPT_fno_PIE) || O.matches(options::OPT_fno_pie));
   }
 
-  if (IsN64 && NonPIC)
+  bool UseAbiCalls = false;
+
+  Arg *ABICallsArg =
+  Args.getLastArg(options::OPT_mabicalls, options::OPT_mno_abicalls);
+  UseAbiCalls =
+  !ABICallsArg ||
+  (ABICallsArg && ABICallsArg->getOption().matches(options::OPT_mabicalls));
+
+  if (UseAbiCalls && IsN64 && NonPIC) {
+D.Diag(diag::warn_drv_unsupported_abicalls);
+UseAbiCalls = false;
+  }
+
+  if (!UseAbiCalls)
 Features.push_back("+noabicalls");
   else
-AddTargetFeature(Args, Features, options::OPT_mno_abicalls,
- options::OPT_mabicalls, "noabicalls");
+Features.push_back("-noabicalls");
 
   mips::FloatABI FloatABI = mips::getMipsFloatABI(D, Args);
   if (FloatABI == mips::FloatABI::Soft) {
Index: cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
===
--- cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
+++ cfe/trunk/include/clang/Basic/DiagnosticDriverKinds.td
@@ -292,6 +292,10 @@
   "ignoring '-mgpopt' option as it cannot be used with %select{|the implicit"
   " usage of }0-mabicalls">,
   InGroup;
+def 

[PATCH] D36551: [mips] Show warning in case of mixing -mlong-calls and -mabicalls options

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added inline comments.



Comment at: test/Driver/mips-longcalls-warning.c:1
+// REQUIRES: mips-registered-target
+// RUN: %clang -### -c -target mips-mti-elf -mlong-calls %s 2>&1 | FileCheck 
-check-prefix=IMPLICIT %s

sdardis wrote:
> atanasyan wrote:
> > sdardis wrote:
> > > Can you put this in test/Driver/mips-abicalls-warning.c from the other 
> > > patch? I'd prefer to keep all the abicalls warnings together rather than 
> > > separate tests based on the feature the conflict with.
> > > Can you put this in test/Driver/mips-abicalls-warning.c from the other 
> > > patch?
> > 
> > I can, but in that case it's probably better to join both patches because 
> > that patch loses its test.
> > 
> You can do it as an NFC change afterward both commits in that case.
OK. Thanks for review.


Repository:
  rL LLVM

https://reviews.llvm.org/D36551



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[PATCH] D36551: [mips] Show warning in case of mixing -mlong-calls and -mabicalls options

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan added inline comments.



Comment at: test/Driver/mips-longcalls-warning.c:1
+// REQUIRES: mips-registered-target
+// RUN: %clang -### -c -target mips-mti-elf -mlong-calls %s 2>&1 | FileCheck 
-check-prefix=IMPLICIT %s

sdardis wrote:
> Can you put this in test/Driver/mips-abicalls-warning.c from the other patch? 
> I'd prefer to keep all the abicalls warnings together rather than separate 
> tests based on the feature the conflict with.
> Can you put this in test/Driver/mips-abicalls-warning.c from the other patch?

I can, but in that case it's probably better to join both patches because that 
patch loses its test.



Repository:
  rL LLVM

https://reviews.llvm.org/D36551



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[PATCH] D36551: [mips] Show warning in case of mixing -mlong-calls and -mabicalls options

[Simon Atanasyan via Phabricator via cfe-commits]

atanasyan updated this revision to Diff 110562.
atanasyan added a comment.

- Addressed review comments.


Repository:
  rL LLVM

https://reviews.llvm.org/D36551

Files:
  include/clang/Basic/DiagnosticDriverKinds.td
  lib/Driver/ToolChains/Arch/Mips.cpp
  test/Driver/mips-features.c
  test/Driver/mips-longcalls-warning.c


Index: test/Driver/mips-longcalls-warning.c
===
--- /dev/null
+++ test/Driver/mips-longcalls-warning.c
@@ -0,0 +1,6 @@
+// REQUIRES: mips-registered-target
+// RUN: %clang -### -c -target mips-mti-elf -mlong-calls %s 2>&1 | FileCheck 
-check-prefix=IMPLICIT %s
+// IMPLICIT: warning: ignoring '-mlong-calls' option as it is not currently 
supported with the implicit usage of -mabicalls
+
+// RUN: %clang -### -c -target mips-mti-elf -mlong-calls -mabicalls %s 2>&1 | 
FileCheck -check-prefix=EXPLICIT %s
+// EXPLICIT: warning: ignoring '-mlong-calls' option as it is not currently 
supported with -mabicalls
Index: test/Driver/mips-features.c
===
--- test/Driver/mips-features.c
+++ test/Driver/mips-features.c
@@ -336,12 +336,16 @@
 // CHECK-IMG-SINGLEFLOAT-FPXX: "-target-feature" "+fpxx"
 
 // -mlong-call
-// RUN: %clang -target mips-img-linux-gnu -### -c %s -mlong-calls 2>&1 \
+// RUN: %clang -target mips-img-linux-gnu -### -c %s \
+// RUN:-mno-abicalls -mlong-calls 2>&1 \
 // RUN:   | FileCheck --check-prefix=LONG-CALLS-ON %s
-// RUN: %clang -target mips-img-linux-gnu -### -c %s -mno-long-calls 2>&1 \
+// RUN: %clang -target mips-img-linux-gnu -### -c %s \
+// RUN:-mno-abicalls -mno-long-calls 2>&1 \
 // RUN:   | FileCheck --check-prefix=LONG-CALLS-OFF %s
 // RUN: %clang -target mips-img-linux-gnu -### -c %s 2>&1 \
 // RUN:   | FileCheck --check-prefix=LONG-CALLS-DEF %s
+// RUN: %clang -target mips-img-linux-gnu -### -c %s -mlong-calls 2>&1 \
+// RUN:   | FileCheck --check-prefix=LONG-CALLS-DEF %s
 // LONG-CALLS-ON: "-target-feature" "+long-calls"
 // LONG-CALLS-OFF: "-target-feature" "-long-calls"
 // LONG-CALLS-DEF-NOT: "long-calls"
Index: lib/Driver/ToolChains/Arch/Mips.cpp
===
--- lib/Driver/ToolChains/Arch/Mips.cpp
+++ lib/Driver/ToolChains/Arch/Mips.cpp
@@ -245,6 +245,16 @@
   else
 Features.push_back("-noabicalls");
 
+  if (Arg *A = Args.getLastArg(options::OPT_mlong_calls,
+   options::OPT_mno_long_calls)) {
+if (A->getOption().matches(options::OPT_mno_long_calls))
+  Features.push_back("-long-calls");
+else if (!UseAbiCalls)
+  Features.push_back("+long-calls");
+else
+  D.Diag(diag::warn_drv_unsupported_longcalls) << (ABICallsArg ? 0 : 1);
+  }
+
   mips::FloatABI FloatABI = mips::getMipsFloatABI(D, Args);
   if (FloatABI == mips::FloatABI::Soft) {
 // FIXME: Note, this is a hack. We need to pass the selected float
@@ -309,8 +319,6 @@
 
   AddTargetFeature(Args, Features, options::OPT_mno_odd_spreg,
options::OPT_modd_spreg, "nooddspreg");
-  AddTargetFeature(Args, Features, options::OPT_mlong_calls,
-   options::OPT_mno_long_calls, "long-calls");
   AddTargetFeature(Args, Features, options::OPT_mmt, options::OPT_mno_mt, 
"mt");
 }
 
Index: include/clang/Basic/DiagnosticDriverKinds.td
===
--- include/clang/Basic/DiagnosticDriverKinds.td
+++ include/clang/Basic/DiagnosticDriverKinds.td
@@ -292,6 +292,10 @@
   "ignoring '-mgpopt' option as it cannot be used with %select{|the implicit"
   " usage of }0-mabicalls">,
   InGroup;
+def warn_drv_unsupported_longcalls : Warning<
+  "ignoring '-mlong-calls' option as it is not currently supported with "
+  "%select{|the implicit usage of }0-mabicalls">,
+  InGroup;
 def warn_drv_unsupported_abicalls : Warning<
   "ignoring '-mabicalls' option as it cannot be used with "
   "non position-independent code and the N64 ABI">,


Index: test/Driver/mips-longcalls-warning.c
===
--- /dev/null
+++ test/Driver/mips-longcalls-warning.c
@@ -0,0 +1,6 @@
+// REQUIRES: mips-registered-target
+// RUN: %clang -### -c -target mips-mti-elf -mlong-calls %s 2>&1 | FileCheck -check-prefix=IMPLICIT %s
+// IMPLICIT: warning: ignoring '-mlong-calls' option as it is not currently supported with the implicit usage of -mabicalls
+
+// RUN: %clang -### -c -target mips-mti-elf -mlong-calls -mabicalls %s 2>&1 | FileCheck -check-prefix=EXPLICIT %s
+// EXPLICIT: warning: ignoring '-mlong-calls' option as it is not currently supported with -mabicalls
Index: test/Driver/mips-features.c
===
--- test/Driver/mips-features.c
+++ test/Driver/mips-features.c
@@ -336,12 +336,16 @@
 // CHECK-IMG-SINGLEFLOAT-FPXX: "-target-feature" "+fpxx"
 
 // -mlong-call
-// RUN: %clang -target