[PATCH] D85324: [z/OS] Add z/OS Target and define macros
tatyana-krasnukha added a comment.
I'm not familiar with the z/OS target, so I cannot check the correctness of the
target-specific changes. The overall patch looks good.
Comment at: clang/lib/Basic/Targets/OSTargets.h:780
+public:
+ ZOSTargetInfo(const llvm::Triple , const TargetOptions )
+ : OSTargetInfo(Triple, Opts) {}
It is possible to use inheriting constructor here instead (i.e. `using
OSTargetInfo::OSTargetInfo;`).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D85324/new/
https://reviews.llvm.org/D85324
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[PATCH] D53100: clang: Add ARCTargetInfo
tatyana-krasnukha updated this revision to Diff 175290.
tatyana-krasnukha added a comment.
Minor change: remove splitting big numeric arguments on 32-bit integers.
Backend lowering code does this work.
Repository:
rC Clang
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D53100/new/
https://reviews.llvm.org/D53100
Files:
lib/Basic/CMakeLists.txt
lib/Basic/Targets.cpp
lib/Basic/Targets/ARC.cpp
lib/Basic/Targets/ARC.h
lib/CodeGen/TargetInfo.cpp
test/CodeGen/arc/arguments.c
test/CodeGen/arc/struct-align.c
test/CodeGen/target-data.c
Index: test/CodeGen/target-data.c
===
--- test/CodeGen/target-data.c
+++ test/CodeGen/target-data.c
@@ -179,6 +179,10 @@
// RUN: %s | FileCheck %s -check-prefix=ARM-GNU
// ARM-GNU: target datalayout = "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+// RUN: %clang_cc1 -triple arc-unknown-unknown -o - -emit-llvm %s | \
+// RUN: FileCheck %s -check-prefix=ARC
+// ARC: target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-f32:32:32-i64:32-f64:32-a:0:32-n32"
+
// RUN: %clang_cc1 -triple hexagon-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=HEXAGON
// HEXAGON: target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
Index: test/CodeGen/arc/struct-align.c
===
--- test/CodeGen/arc/struct-align.c
+++ test/CodeGen/arc/struct-align.c
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -triple arc-unknown-unknown %s -emit-llvm -o - \
+// RUN: | FileCheck %s
+
+// 64-bit fields need only be 32-bit aligned for arc.
+
+typedef struct {
+ int aa;
+ double bb;
+} s1;
+
+// CHECK: define i32 @f1
+// CHECK: ret i32 12
+int f1() {
+ return sizeof(s1);
+}
+
+typedef struct {
+ int aa;
+ long long bb;
+} s2;
+// CHECK: define i32 @f2
+// CHECK: ret i32 12
+int f2() {
+ return sizeof(s2);
+}
+
Index: test/CodeGen/arc/arguments.c
===
--- test/CodeGen/arc/arguments.c
+++ test/CodeGen/arc/arguments.c
@@ -0,0 +1,135 @@
+// RUN: %clang_cc1 -triple arc-unknown-unknown %s -emit-llvm -o - \
+// RUN: | FileCheck %s
+
+// Basic argument tests for ARC.
+
+// CHECK: define void @f0(i32 inreg %i, i32 inreg %j, i64 inreg %k)
+void f0(int i, long j, long long k) {}
+
+typedef struct {
+ int aa;
+ int bb;
+} s1;
+// CHECK: define void @f1(i32 inreg %i.coerce0, i32 inreg %i.coerce1)
+void f1(s1 i) {}
+
+typedef struct {
+ char aa; char bb; char cc; char dd;
+} cs1;
+// CHECK: define void @cf1(i32 inreg %i.coerce)
+void cf1(cs1 i) {}
+
+typedef struct {
+ int cc;
+} s2;
+// CHECK: define void @f2(%struct.s2* noalias sret %agg.result)
+s2 f2() {
+ s2 foo;
+ return foo;
+}
+
+typedef struct {
+ int cc;
+ int dd;
+} s3;
+// CHECK: define void @f3(%struct.s3* noalias sret %agg.result)
+s3 f3() {
+ s3 foo;
+ return foo;
+}
+
+// CHECK: define void @f4(i64 inreg %i)
+void f4(long long i) {}
+
+// CHECK: define void @f5(i8 inreg signext %a, i16 inreg signext %b)
+void f5(signed char a, short b) {}
+
+// CHECK: define void @f6(i8 inreg zeroext %a, i16 inreg zeroext %b)
+void f6(unsigned char a, unsigned short b) {}
+
+enum my_enum {
+ ENUM1,
+ ENUM2,
+ ENUM3,
+};
+// Enums should be treated as the underlying i32.
+// CHECK: define void @f7(i32 inreg %a)
+void f7(enum my_enum a) {}
+
+enum my_big_enum {
+ ENUM4 = 0x,
+};
+// Big enums should be treated as the underlying i64.
+// CHECK: define void @f8(i64 inreg %a)
+void f8(enum my_big_enum a) {}
+
+union simple_union {
+ int a;
+ char b;
+};
+// Unions should be passed inreg.
+// CHECK: define void @f9(i32 inreg %s.coerce)
+void f9(union simple_union s) {}
+
+typedef struct {
+ int b4 : 4;
+ int b3 : 3;
+ int b8 : 8;
+} bitfield1;
+// Bitfields should be passed inreg.
+// CHECK: define void @f10(i32 inreg %bf1.coerce)
+void f10(bitfield1 bf1) {}
+
+// CHECK: define inreg { float, float } @cplx1(float inreg %r)
+_Complex float cplx1(float r) {
+ return r + 2.0fi;
+}
+
+// CHECK: define inreg { double, double } @cplx2(double inreg %r)
+_Complex double cplx2(double r) {
+ return r + 2.0i;
+}
+
+// CHECK: define inreg { i32, i32 } @cplx3(i32 inreg %r)
+_Complex int cplx3(int r) {
+ return r + 2i;
+}
+
+// CHECK: define inreg { i64, i64 } @cplx4(i64 inreg %r)
+_Complex long long cplx4(long long r) {
+ return r + 2i;
+}
+
+// CHECK: define inreg { i8, i8 } @cplx6(i8 inreg signext %r)
+_Complex signed char cplx6(signed char r) {
+ return r + 2i;
+}
+
+// CHECK: define inreg { i16, i16 } @cplx7(i16 inreg signext %r)
+_Complex short cplx7(short r) {
+ return r + 2i;
+}
+
+typedef struct {
+ int aa; int bb;
+} s8;
+
+typedef struct {
+ int aa; int bb; int cc; int dd;
+} s16;
+
+// Use 16-byte struct 2 times, gets 8 registers.
+void st2(s16 a, s16 b) {}
+//
[PATCH] D53101: [ARC] Add option for enabling reduced register file mode
tatyana-krasnukha created this revision.
tatyana-krasnukha added a reviewer: petecoup.
tatyana-krasnukha added a project: clang.
Herald added subscribers: cfe-commits, mgorny.
tatyana-krasnukha added a dependency: D53100: clang: Add ARCTargetInfo.
This option affects registers count for passing arguments.
Repository:
rC Clang
https://reviews.llvm.org/D53101
Files:
include/clang/Driver/Options.td
lib/Basic/CMakeLists.txt
lib/Basic/Targets.cpp
lib/Basic/Targets/ARC.cpp
lib/Basic/Targets/ARC.h
lib/CodeGen/TargetInfo.cpp
lib/Driver/CMakeLists.txt
lib/Driver/ToolChains/Arch/ARC.cpp
lib/Driver/ToolChains/Arch/ARC.h
lib/Driver/ToolChains/Clang.cpp
test/CodeGen/arc/arguments.c
test/CodeGen/arc/struct-align.c
test/CodeGen/target-data.c
test/Driver/arc-target-features.c
Index: test/Driver/arc-target-features.c
===
--- test/Driver/arc-target-features.c
+++ test/Driver/arc-target-features.c
@@ -0,0 +1,5 @@
+// REQUIRES: arc-registered-target
+
+// RUN: %clang -target arc-unknown-unknown -### -S %s -mrf16 2>&1 | FileCheck %s -check-prefix=CHECK-RF16
+// CHECK-RF16: "-target-feature" "+rf16"
+// CHECK: #define __ARC_RF16__
Index: test/CodeGen/target-data.c
===
--- test/CodeGen/target-data.c
+++ test/CodeGen/target-data.c
@@ -151,6 +151,10 @@
// RUN: %s | FileCheck %s -check-prefix=ARM-GNU
// ARM-GNU: target datalayout = "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+// RUN: %clang_cc1 -triple arc-unknown-unknown -o - -emit-llvm %s | \
+// RUN: FileCheck %s -check-prefix=ARC
+// ARC: target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-f32:32:32-i64:32-f64:32-a:0:32-n32"
+
// RUN: %clang_cc1 -triple hexagon-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=HEXAGON
// HEXAGON: target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
Index: test/CodeGen/arc/struct-align.c
===
--- test/CodeGen/arc/struct-align.c
+++ test/CodeGen/arc/struct-align.c
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -triple arc-unknown-unknown %s -emit-llvm -o - \
+// RUN: | FileCheck %s
+
+// 64-bit fields need only be 32-bit aligned for arc.
+
+typedef struct {
+ int aa;
+ double bb;
+} s1;
+
+// CHECK: define i32 @f1
+// CHECK: ret i32 12
+int f1() {
+ return sizeof(s1);
+}
+
+typedef struct {
+ int aa;
+ long long bb;
+} s2;
+// CHECK: define i32 @f2
+// CHECK: ret i32 12
+int f2() {
+ return sizeof(s2);
+}
+
Index: test/CodeGen/arc/arguments.c
===
--- test/CodeGen/arc/arguments.c
+++ test/CodeGen/arc/arguments.c
@@ -0,0 +1,135 @@
+// RUN: %clang_cc1 -triple arc-unknown-unknown %s -emit-llvm -o - \
+// RUN: | FileCheck %s
+
+// Basic argument tests for ARC.
+
+// CHECK: define void @f0(i32 inreg %i, i32 inreg %j, i32 inreg %k.coerce0, i32 inreg %k.coerce1)
+void f0(int i, long j, long long k) {}
+
+typedef struct {
+ int aa;
+ int bb;
+} s1;
+// CHECK: define void @f1(i32 inreg %i.coerce0, i32 inreg %i.coerce1)
+void f1(s1 i) {}
+
+typedef struct {
+ char aa; char bb; char cc; char dd;
+} cs1;
+// CHECK: define void @cf1(i32 inreg %i.coerce)
+void cf1(cs1 i) {}
+
+typedef struct {
+ int cc;
+} s2;
+// CHECK: define void @f2(%struct.s2* noalias sret %agg.result)
+s2 f2() {
+ s2 foo;
+ return foo;
+}
+
+typedef struct {
+ int cc;
+ int dd;
+} s3;
+// CHECK: define void @f3(%struct.s3* noalias sret %agg.result)
+s3 f3() {
+ s3 foo;
+ return foo;
+}
+
+// CHECK: define void @f4(i32 inreg %i.coerce0, i32 inreg %i.coerce1)
+void f4(long long i) {}
+
+// CHECK: define void @f5(i8 inreg signext %a, i16 inreg signext %b)
+void f5(signed char a, short b) {}
+
+// CHECK: define void @f6(i8 inreg zeroext %a, i16 inreg zeroext %b)
+void f6(unsigned char a, unsigned short b) {}
+
+enum my_enum {
+ ENUM1,
+ ENUM2,
+ ENUM3,
+};
+// Enums should be treated as the underlying i32.
+// CHECK: define void @f7(i32 inreg %a)
+void f7(enum my_enum a) {}
+
+enum my_big_enum {
+ ENUM4 = 0x,
+};
+// Big enums should be treated as the underlying i64.
+// CHECK: define void @f8(i32 inreg %a.coerce0, i32 inreg %a.coerce1)
+void f8(enum my_big_enum a) {}
+
+union simple_union {
+ int a;
+ char b;
+};
+// Unions should be passed inreg.
+// CHECK: define void @f9(i32 inreg %s.coerce)
+void f9(union simple_union s) {}
+
+typedef struct {
+ int b4 : 4;
+ int b3 : 3;
+ int b8 : 8;
+} bitfield1;
+// Bitfields should be passed inreg.
+// CHECK: define void @f10(i32 inreg %bf1.coerce)
+void f10(bitfield1 bf1) {}
+
+// CHECK: define inreg { float, float } @cplx1(float inreg %r)
+_Complex float cplx1(float r) {
+ return r + 2.0fi;
+}
+
+// CHECK: define inreg { double, double } @cplx2(i32
[PATCH] D53100: clang: Add ARCTargetInfo
tatyana-krasnukha created this revision.
tatyana-krasnukha added reviewers: petecoup, rjmccall, rsmith.
tatyana-krasnukha added a project: clang.
Herald added subscribers: cfe-commits, mgorny.
This patch is an updated version of https://reviews.llvm.org/D43089 with
changes in arguments classifying. If a calling convention item is not specified
by ARC ABI, it follows Itanium C++ ABI.
Repository:
rC Clang
https://reviews.llvm.org/D53100
Files:
lib/Basic/CMakeLists.txt
lib/Basic/Targets.cpp
lib/Basic/Targets/ARC.cpp
lib/Basic/Targets/ARC.h
lib/CodeGen/TargetInfo.cpp
test/CodeGen/arc/arguments.c
test/CodeGen/arc/struct-align.c
test/CodeGen/target-data.c
Index: test/CodeGen/target-data.c
===
--- test/CodeGen/target-data.c
+++ test/CodeGen/target-data.c
@@ -151,6 +151,10 @@
// RUN: %s | FileCheck %s -check-prefix=ARM-GNU
// ARM-GNU: target datalayout = "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+// RUN: %clang_cc1 -triple arc-unknown-unknown -o - -emit-llvm %s | \
+// RUN: FileCheck %s -check-prefix=ARC
+// ARC: target datalayout = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-f32:32:32-i64:32-f64:32-a:0:32-n32"
+
// RUN: %clang_cc1 -triple hexagon-unknown -o - -emit-llvm %s | \
// RUN: FileCheck %s -check-prefix=HEXAGON
// HEXAGON: target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
Index: test/CodeGen/arc/struct-align.c
===
--- test/CodeGen/arc/struct-align.c
+++ test/CodeGen/arc/struct-align.c
@@ -0,0 +1,26 @@
+// RUN: %clang_cc1 -triple arc-unknown-unknown %s -emit-llvm -o - \
+// RUN: | FileCheck %s
+
+// 64-bit fields need only be 32-bit aligned for arc.
+
+typedef struct {
+ int aa;
+ double bb;
+} s1;
+
+// CHECK: define i32 @f1
+// CHECK: ret i32 12
+int f1() {
+ return sizeof(s1);
+}
+
+typedef struct {
+ int aa;
+ long long bb;
+} s2;
+// CHECK: define i32 @f2
+// CHECK: ret i32 12
+int f2() {
+ return sizeof(s2);
+}
+
Index: test/CodeGen/arc/arguments.c
===
--- test/CodeGen/arc/arguments.c
+++ test/CodeGen/arc/arguments.c
@@ -0,0 +1,135 @@
+// RUN: %clang_cc1 -triple arc-unknown-unknown %s -emit-llvm -o - \
+// RUN: | FileCheck %s
+
+// Basic argument tests for ARC.
+
+// CHECK: define void @f0(i32 inreg %i, i32 inreg %j, i32 inreg %k.coerce0, i32 inreg %k.coerce1)
+void f0(int i, long j, long long k) {}
+
+typedef struct {
+ int aa;
+ int bb;
+} s1;
+// CHECK: define void @f1(i32 inreg %i.coerce0, i32 inreg %i.coerce1)
+void f1(s1 i) {}
+
+typedef struct {
+ char aa; char bb; char cc; char dd;
+} cs1;
+// CHECK: define void @cf1(i32 inreg %i.coerce)
+void cf1(cs1 i) {}
+
+typedef struct {
+ int cc;
+} s2;
+// CHECK: define void @f2(%struct.s2* noalias sret %agg.result)
+s2 f2() {
+ s2 foo;
+ return foo;
+}
+
+typedef struct {
+ int cc;
+ int dd;
+} s3;
+// CHECK: define void @f3(%struct.s3* noalias sret %agg.result)
+s3 f3() {
+ s3 foo;
+ return foo;
+}
+
+// CHECK: define void @f4(i32 inreg %i.coerce0, i32 inreg %i.coerce1)
+void f4(long long i) {}
+
+// CHECK: define void @f5(i8 inreg signext %a, i16 inreg signext %b)
+void f5(signed char a, short b) {}
+
+// CHECK: define void @f6(i8 inreg zeroext %a, i16 inreg zeroext %b)
+void f6(unsigned char a, unsigned short b) {}
+
+enum my_enum {
+ ENUM1,
+ ENUM2,
+ ENUM3,
+};
+// Enums should be treated as the underlying i32.
+// CHECK: define void @f7(i32 inreg %a)
+void f7(enum my_enum a) {}
+
+enum my_big_enum {
+ ENUM4 = 0x,
+};
+// Big enums should be treated as the underlying i64.
+// CHECK: define void @f8(i32 inreg %a.coerce0, i32 inreg %a.coerce1)
+void f8(enum my_big_enum a) {}
+
+union simple_union {
+ int a;
+ char b;
+};
+// Unions should be passed inreg.
+// CHECK: define void @f9(i32 inreg %s.coerce)
+void f9(union simple_union s) {}
+
+typedef struct {
+ int b4 : 4;
+ int b3 : 3;
+ int b8 : 8;
+} bitfield1;
+// Bitfields should be passed inreg.
+// CHECK: define void @f10(i32 inreg %bf1.coerce)
+void f10(bitfield1 bf1) {}
+
+// CHECK: define inreg { float, float } @cplx1(float inreg %r)
+_Complex float cplx1(float r) {
+ return r + 2.0fi;
+}
+
+// CHECK: define inreg { double, double } @cplx2(i32 inreg %r.coerce0, i32 inreg %r.coerce1)
+_Complex double cplx2(double r) {
+ return r + 2.0i;
+}
+
+// CHECK: define inreg { i32, i32 } @cplx3(i32 inreg %r)
+_Complex int cplx3(int r) {
+ return r + 2i;
+}
+
+// CHECK: define inreg { i64, i64 } @cplx4(i32 inreg %r.coerce0, i32 inreg %r.coerce1)
+_Complex long long cplx4(long long r) {
+ return r + 2i;
+}
+
+// CHECK: define inreg { i8, i8 } @cplx6(i8 inreg signext %r)
+_Complex signed char cplx6(signed char r) {
+ return r + 2i;
+}
+
+// CHECK: define inreg { i16, i16 } @cplx7(i16
[PATCH] D43089: clang: Add ARCTargetInfo
tatyana-krasnukha added a comment.
Sorry, =default is not applicable in these cases, of course.
Comment at: clang/lib/CodeGen/TargetInfo.cpp:8123
+public:
+ ARCABIInfo(CodeGen::CodeGenTypes ) : DefaultABIInfo(CGT) {}
+
tatyana-krasnukha wrote:
> Better use '= default' instead of {}
> And you even may use inheriting constructor here
Here should be inheriting of base class constructor:
```
using DefaultABIInfo::DefaultABIInfo;
```
https://reviews.llvm.org/D43089
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[PATCH] D43089: clang: Add ARCTargetInfo
tatyana-krasnukha added a comment.
This is what I could note
Comment at: clang/lib/Basic/Targets/ARC.h:26
+class LLVM_LIBRARY_VISIBILITY ARCTargetInfo : public TargetInfo {
+ static const Builtin::Info BuiltinInfo[];
+
Looks like unused member, while getTargetBuiltins returns 'None'
Comment at: clang/lib/CodeGen/TargetInfo.cpp:8123
+public:
+ ARCABIInfo(CodeGen::CodeGenTypes ) : DefaultABIInfo(CGT) {}
+
Better use '= default' instead of {}
And you even may use inheriting constructor here
Comment at: clang/lib/CodeGen/TargetInfo.cpp:8165
+ ARCTargetCodeGenInfo(CodeGenTypes )
+ : TargetCodeGenInfo(new ARCABIInfo(CGT)) {}
+};
and here
https://reviews.llvm.org/D43089
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[PATCH] D43089: clang: Add ARCTargetInfo
tatyana-krasnukha added a comment. Hello Pete, Thank you for upstreaming ARC target to clang! I checked it in couple with lldb - works well. So, the revision is good to me. But it seems, I have no rights to accept revisions yet... https://reviews.llvm.org/D43089 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
