[PATCH] D70401: [RISCV] Complete RV32E/ilp32e implementation

[luxufan via Phabricator via cfe-commits]

StephenFan added a comment.

In D70401#3873874 , @pcwang-thead 
wrote:

> In D70401#3873347 , @luojia wrote:
>
>> Hello! Any further updates to this patch? It seems like all the inline 
>> comments have been resolved.
>
> We have done some works in this patch to make it compatible with GCC, it can 
> be combined with GNU toolchain now.
>
> But as what have been discussed[1, 2], we may proceed with this patch when 
> RV32E/ilp32e is ratified.
>
> 1. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/269
> 2. https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/257

RV32E/ilp32e has been 
ratified(https://github.com/riscv-non-isa/riscv-elf-psabi-doc). Do you plan to 
proceed with this patch? :)


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[PATCH] D129448: [CodeGen][Asan] Emit lifetime intrinsic for bypassed label

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StephenFan added a comment.

In D129448#3669296 , @vitalybuka 
wrote:

> I am not sure what to do with this patch. I really prefer to avoid it to 
> minimize the risk of regressions.
>
> We probably considered/prototyped to insert starts like in this solution then 
> in 2016. But at the time of the solution was a comment by @rsmith 
> https://reviews.llvm.org/D24693#559609
> Even if it works for asan, I still don't know how this patch will affect 
> miss-compiles in other places. Dropping intrinsics completely as is must not 
> miscompile.
>
> If the goal to fix asan, then it's extremely rare case, I measured it on llvm 
> codebase and entire Google code. This is not worth of effort to me.
> Also HWAsan and MTE, which can be considered asan successors, does not even 
> bother to handle allocas with multiple lifetime start.

Ok. I'm just fixing this out of interest, and it doesn't look like it's a rigid 
demand to fix it. If this patch may cause potential regression, I respect your 
decision.


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[PATCH] D129448: [CodeGen][Asan] Emit lifetime intrinsic for bypassed label

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StephenFan added inline comments.



Comment at: clang/test/CodeGen/lifetime2.c:42
+// O2: @llvm.lifetime.start.p0i8(i64 1
 bar(, 1);
+// O2: @llvm.lifetime.end.p0i8(i64 1

StephenFan wrote:
> vitalybuka wrote:
> > It assume this will break Msan 
> > Transforms/Instrumentation/MemorySanitizer.cpp:1298 as it assume variable 
> > is not initialized on start
> > 
> > ```
> > void goto_bypass(void) {
> >   {
> > char x;
> >   l1:
> > bar(, 1);
> >if (x)
> >  goto l1
> >   }
> >   goto l1;
> > }
> > ```
> Yes. I still need some time to see how to deal with it.
Candidate solution: D129991


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[PATCH] D129448: [CodeGen][Asan] Emit lifetime intrinsic for bypassed label

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StephenFan added inline comments.



Comment at: clang/test/CodeGen/lifetime2.c:78
 break;
   case 2:
 bar(, 1);

vitalybuka wrote:
> vitalybuka wrote:
> > StephenFan wrote:
> > > vitalybuka wrote:
> > > > vitalybuka wrote:
> > > > > Please check for lifetime markers, I assume case 2 will have a new one
> > > > > Please check for lifetime markers, I assume case 2 will have a new one
> > > > Please check for *all* lifetime markers
> > > > 
> > > > you can add use "FileCheck --implicit-check-not llvm.lifetime" so it 
> > > > will fail if something has no corresponding match
> > > > 
> > > I have checked for all lifetime markers in `Diff 444701`. What's the 
> > > point of adding `--implicit-check-not llvm.lifetime`?
> > Point is to have en error, if lifetime emitted, but we don't have a check 
> > for that.
> > Which is very reasonable for the test.
> actually converting the test into --implicit-check-not in a separate patch 
> could be nice, so we would be be confused by previously missed markers. 
> https://reviews.llvm.org/D129789
Thanks!


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[PATCH] D129448: [CodeGen][Asan] Emit lifetime intrinsic for bypassed label

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StephenFan updated this revision to Diff 445420.
StephenFan added a comment.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

1. Rebase.
2. Add a test case of goto_bypass.


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Files:
  clang/lib/CodeGen/CGDecl.cpp
  clang/lib/CodeGen/CGStmt.cpp
  clang/lib/CodeGen/CodeGenFunction.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/lifetime2.c
  llvm/test/Instrumentation/MemorySanitizer/alloca.ll

Index: llvm/test/Instrumentation/MemorySanitizer/alloca.ll
===
--- llvm/test/Instrumentation/MemorySanitizer/alloca.ll
+++ llvm/test/Instrumentation/MemorySanitizer/alloca.ll
@@ -209,7 +209,42 @@
 ; KMSAN-NOT: call void @__msan_poison_alloca(i8* {{.*}}, i64 4,
 ; CHECK: call void @llvm.lifetime.end
 
+define void @goto_bypass() sanitize_memory {
+entry:
+  %x = alloca i8, align 1
+  call void @llvm.lifetime.start.p0i8(i64 1, i8* %x)
+  br label %l1
+
+l1:
+  call void @llvm.lifetime.start.p0i8(i64 1, i8* %x)
+  call void @bar(i8* noundef %x, i32 noundef 1)
+  %0 = load i8, i8* %x
+  %tobool = icmp ne i8 %0, 0
+  br i1 %tobool, label %if.then, label %if.end
+
+if.then:
+  br label %l1
+
+if.end:
+  call void @llvm.lifetime.end.p0i8(i64 1, i8* %x)
+  br label %l1
+}
 
-
+; CHECK-LABEL: define void @goto_bypass(
+; CHECK-LABEL: entry:
+; CHECK: %x = alloca i8
+; INLINE: call void @llvm.memset.p0i8.i64(i8* align 1 {{.*}}, i8 -1, i64 1, i1 false)
+; CALL: call void @__msan_poison_stack(i8* {{.*}}, i64 1)
+; ORIGIN: call void @__msan_set_alloca_origin4(i8* {{.*}}, i64 1,
+; KMSAN: call void @__msan_poison_alloca(i8* {{.*}}, i64 1,
+
+; FIXME: It is invalid to instrument here Since variable x may be initialized by callee bar.
+; CHECK-LABEL: l1:
+; INLINE: call void @llvm.memset.p0i8.i64(i8* align 1 {{.*}}, i8 -1, i64 1, i1 false)
+; CALL: call void @__msan_poison_stack(i8* {{.*}}, i64 1)
+; ORIGIN: call void @__msan_set_alloca_origin4(i8* {{.*}}, i64 1,
+; KMSAN: call void @__msan_poison_alloca(i8* {{.*}}, i64 1,
+
+declare void @bar(i8* noundef, i32 noundef)
 declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture)
 declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture)
Index: clang/test/CodeGen/lifetime2.c
===
--- clang/test/CodeGen/lifetime2.c
+++ clang/test/CodeGen/lifetime2.c
@@ -35,8 +35,11 @@
 void goto_bypass(void) {
   {
 char x;
+// O2: @llvm.lifetime.start.p0i8(i64 1
   l1:
+// O2: @llvm.lifetime.start.p0i8(i64 1
 bar(, 1);
+// O2: @llvm.lifetime.end.p0i8(i64 1
   }
   goto l1;
 }
@@ -67,21 +70,30 @@
   case 1:
 n = n;
 char x;
+// O2: @llvm.lifetime.start.p0i8(i64 1
 bar(, 1);
 break;
   case 2:
+// O2: @llvm.lifetime.start.p0i8(i64 1
 bar(, 1);
 break;
+// O2: @llvm.lifetime.end.p0i8(i64 1
   }
 }
 
 // CHECK-LABEL: @indirect_jump
 void indirect_jump(int n) {
   char x;
+  // O2: @llvm.lifetime.start.p0i8(i64 1
   void *T[] = {&};
+  // O2: @llvm.lifetime.start.p0i8(i64 8
   goto *T[n];
 L:
+  // O2: @llvm.lifetime.start.p0i8(i64 1
+  // O2: @llvm.lifetime.start.p0i8(i64 8
   bar(, 1);
+  // O2: @llvm.lifetime.end.p0i8(i64 8
+  // O2: @llvm.lifetime.end.p0i8(i64 1
 }
 
 extern void foo2(int p);
Index: clang/lib/CodeGen/CodeGenFunction.h
===
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -38,6 +38,7 @@
 #include "llvm/ADT/MapVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Frontend/OpenMP/OMPIRBuilder.h"
+#include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/ValueHandle.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Transforms/Utils/SanitizerStats.h"
@@ -1926,6 +1927,14 @@
   /// The current lexical scope.
   LexicalScope *CurLexicalScope = nullptr;
 
+  /// Map from lexical socpe to vector of bypassed lifetime start markers.
+  /// NOTE: If a lifetime start marker isn't defined in any lexical scope(
+  /// defining while CurLexicalScope is nullptr), its key is nullptr;
+  std::map>
+  BypassedLifetimeStartMarkers;
+
+  void restartBypassedVariable();
+
   /// The current source location that should be used for exception
   /// handling code.
   SourceLocation CurEHLocation;
@@ -2922,7 +2931,8 @@
   void EmitSehTryScopeBegin();
   void EmitSehTryScopeEnd();
 
-  llvm::Value *EmitLifetimeStart(llvm::TypeSize Size, llvm::Value *Addr);
+  llvm::Value *EmitLifetimeStart(llvm::TypeSize Size, llvm::Value *Addr,
+ bool isBypassed = false);
   void EmitLifetimeEnd(llvm::Value *Size, llvm::Value *Addr);
 
   llvm::Value *EmitCXXNewExpr(const CXXNewExpr *E);
Index: clang/lib/CodeGen/CodeGenFunction.cpp
===
--- 

[PATCH] D129448: [CodeGen][Asan] Emit lifetime intrinsic for bypassed label

[luxufan via Phabricator via cfe-commits]

StephenFan added inline comments.



Comment at: clang/test/CodeGen/lifetime2.c:42
+// O2: @llvm.lifetime.start.p0i8(i64 1
 bar(, 1);
+// O2: @llvm.lifetime.end.p0i8(i64 1

vitalybuka wrote:
> It assume this will break Msan 
> Transforms/Instrumentation/MemorySanitizer.cpp:1298 as it assume variable is 
> not initialized on start
> 
> ```
> void goto_bypass(void) {
>   {
> char x;
>   l1:
> bar(, 1);
>if (x)
>  goto l1
>   }
>   goto l1;
> }
> ```
Yes. I still need some time to see how to deal with it.



Comment at: clang/test/CodeGen/lifetime2.c:78
 break;
   case 2:
 bar(, 1);

vitalybuka wrote:
> vitalybuka wrote:
> > Please check for lifetime markers, I assume case 2 will have a new one
> > Please check for lifetime markers, I assume case 2 will have a new one
> Please check for *all* lifetime markers
> 
> you can add use "FileCheck --implicit-check-not llvm.lifetime" so it will 
> fail if something has no corresponding match
> 
I have checked for all lifetime markers in `Diff 444701`. What's the point of 
adding `--implicit-check-not llvm.lifetime`?


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[PATCH] D129448: [CodeGen][Asan] Emit lifetime intrinsic for bypassed label

[luxufan via Phabricator via cfe-commits]

StephenFan updated this revision to Diff 444701.
StephenFan added a comment.

1. Record bypassed lifetime start markers in codegenfunction class instead of 
lexicalscope. Since bypassed variables may be defined when lexicalscope is 
nullptr. This can also fix test fail of use-after-scope-goto.cpp.
2. Check more lifetime.start or end intrinsics in lifetime2.c test file.


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Files:
  clang/lib/CodeGen/CGDecl.cpp
  clang/lib/CodeGen/CGStmt.cpp
  clang/lib/CodeGen/CodeGenFunction.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/lifetime2.c

Index: clang/test/CodeGen/lifetime2.c
===
--- clang/test/CodeGen/lifetime2.c
+++ clang/test/CodeGen/lifetime2.c
@@ -35,11 +35,12 @@
 // CHECK-LABEL: @goto_bypass
 void goto_bypass(void) {
   {
-// O2-NOT: @llvm.lifetime.start.p0i8(i64 1
-// O2-NOT: @llvm.lifetime.end.p0i8(i64 1
+// O2: @llvm.lifetime.start.p0i8(i64 1
 char x;
   l1:
+// O2: @llvm.lifetime.start.p0i8(i64 1
 bar(, 1);
+// O2: @llvm.lifetime.end.p0i8(i64 1
   }
   goto l1;
 }
@@ -69,24 +70,26 @@
   switch (n) {
   case 1:
 n = n;
-// O2-NOT: @llvm.lifetime.start.p0i8(i64 1
-// O2-NOT: @llvm.lifetime.end.p0i8(i64 1
+// O2: @llvm.lifetime.start.p0i8(i64 1
 char x;
 bar(, 1);
 break;
   case 2:
+// O2: @llvm.lifetime.start.p0i8(i64 1
 bar(, 1);
 break;
+// O2: @llvm.lifetime.end.p0i8(i64 1
   }
 }
 
 // CHECK-LABEL: @indirect_jump
 void indirect_jump(int n) {
   char x;
-  // O2-NOT: @llvm.lifetime
+  // O2: @llvm.lifetime.start
   void *T[] = {&};
   goto *T[n];
 L:
+  // O2: @llvm.lifetime.start
   bar(, 1);
 }
 
Index: clang/lib/CodeGen/CodeGenFunction.h
===
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -38,6 +38,7 @@
 #include "llvm/ADT/MapVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Frontend/OpenMP/OMPIRBuilder.h"
+#include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/ValueHandle.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Transforms/Utils/SanitizerStats.h"
@@ -1926,6 +1927,14 @@
   /// The current lexical scope.
   LexicalScope *CurLexicalScope = nullptr;
 
+  /// Map from lexical socpe to vector of bypassed lifetime start markers.
+  /// NOTE: If a lifetime start marker isn't defined in any lexical scope(
+  /// defining while CurLexicalScope is nullptr), its key is nullptr;
+  std::map>
+  BypassedLifetimeStartMarkers;
+
+  void restartBypassedVariable();
+
   /// The current source location that should be used for exception
   /// handling code.
   SourceLocation CurEHLocation;
@@ -2922,7 +2931,8 @@
   void EmitSehTryScopeBegin();
   void EmitSehTryScopeEnd();
 
-  llvm::Value *EmitLifetimeStart(llvm::TypeSize Size, llvm::Value *Addr);
+  llvm::Value *EmitLifetimeStart(llvm::TypeSize Size, llvm::Value *Addr,
+ bool isBypassed = false);
   void EmitLifetimeEnd(llvm::Value *Size, llvm::Value *Addr);
 
   llvm::Value *EmitCXXNewExpr(const CXXNewExpr *E);
Index: clang/lib/CodeGen/CodeGenFunction.cpp
===
--- clang/lib/CodeGen/CodeGenFunction.cpp
+++ clang/lib/CodeGen/CodeGenFunction.cpp
@@ -1233,6 +1233,8 @@
 EmitBranch(SkipCountBB);
   }
   EmitBlock(BB);
+  restartBypassedVariable();
+
   uint64_t CurrentCount = getCurrentProfileCount();
   incrementProfileCounter(S);
   setCurrentProfileCount(getCurrentProfileCount() + CurrentCount);
@@ -1299,6 +1301,14 @@
   return ResTy;
 }
 
+void CodeGenFunction::restartBypassedVariable() {
+  if (BypassedLifetimeStartMarkers.count(CurLexicalScope))
+llvm::for_each(BypassedLifetimeStartMarkers[CurLexicalScope],
+   [this](const llvm::CallInst *LifetimeStartMarker) {
+ Builder.Insert(LifetimeStartMarker->clone());
+   });
+}
+
 void CodeGenFunction::GenerateCode(GlobalDecl GD, llvm::Function *Fn,
const CGFunctionInfo ) {
   assert(Fn && "generating code for null Function");
@@ -1454,6 +1464,8 @@
   // a quick pass now to see if we can.
   if (!CurFn->doesNotThrow())
 TryMarkNoThrow(CurFn);
+
+  BypassedLifetimeStartMarkers.clear();
 }
 
 /// ContainsLabel - Return true if the statement contains a label in it.  If
Index: clang/lib/CodeGen/CGStmt.cpp
===
--- clang/lib/CodeGen/CGStmt.cpp
+++ clang/lib/CodeGen/CGStmt.cpp
@@ -646,6 +646,7 @@
   }
 
   EmitBlock(Dest.getBlock());
+  restartBypassedVariable();
 
   // Emit debug info for labels.
   if (CGDebugInfo *DI = getDebugInfo()) {
Index: clang/lib/CodeGen/CGDecl.cpp
===
--- 

[PATCH] D126742: [RISCV][Clang] Support RVV policy functions.

[luxufan via Phabricator via cfe-commits]

StephenFan added inline comments.
Herald added a subscriber: nlopes.



Comment at: clang/lib/Sema/SemaRVVLookup.cpp:378-388
+} else {
+  if (IsPrototypeDefaultTU) {
+DefaultPolicy = Policy::TU;
+if (HasPolicy)
+  BuiltinName += "_tu";
+  } else {
+DefaultPolicy = Policy::TA;

Reduce indentation.


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[PATCH] D129448: [CodeGen][Asan] Emit lifetime intrinsic for bypassed label

[luxufan via Phabricator via cfe-commits]

StephenFan created this revision.
StephenFan added reviewers: MaskRay, vitalybuka, rsmith.
Herald added a project: All.
StephenFan requested review of this revision.
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Herald added a subscriber: cfe-commits.

Fix https://github.com/llvm/llvm-project/issues/56356
For following test case:

  extern int bar(char *A, int n);
  void goto_bypass(void) {
{
  char x;
l1:
  bar(, 1);
}
goto l1;
  }

And using `clang -cc1 -O2 -S -emit-llvm` to compile it.

  In the past, due to the existence of bypassed label, the lifetime

intrinsic would not be generated. This was also the cause of pr56356.

  In this patch, if the variable is bypassed, we do variable

allocation, emit lifetime-start intrinsic and record the lifetime-start
intrinsic in LexicalScope. Then When emitting the bypass label, we emit
the lifetime instrinsic again to make sure the lifetime of the bypassed
variable is start again. Address sanitizer will capture these lifetime
intrinsics and instrument poison and unpoison code. Finally pr56356 can
be resolved.

Here is the new llvm-ir of the test case above.

  define dso_local void @goto_bypass() local_unnamed_addr #0 {
  entry:
%x = alloca i8, align 1
call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %x) #3
br label %l1
  
  l1:   ; preds = %l1, %entry
call void @llvm.lifetime.start.p0(i64 1, ptr nonnull %x) #3
%call = call i32 @bar(ptr noundef nonnull %x, i32 noundef 1) #3
call void @llvm.lifetime.end.p0(i64 1, ptr nonnull %x) #3
br label %l1
  }


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Files:
  clang/lib/CodeGen/CGDecl.cpp
  clang/lib/CodeGen/CGStmt.cpp
  clang/lib/CodeGen/CodeGenFunction.h
  clang/test/CodeGen/lifetime2.c

Index: clang/test/CodeGen/lifetime2.c
===
--- clang/test/CodeGen/lifetime2.c
+++ clang/test/CodeGen/lifetime2.c
@@ -35,11 +35,12 @@
 // CHECK-LABEL: @goto_bypass
 void goto_bypass(void) {
   {
-// O2-NOT: @llvm.lifetime.start.p0i8(i64 1
-// O2-NOT: @llvm.lifetime.end.p0i8(i64 1
+// O2: @llvm.lifetime.start.p0i8(i64 1
 char x;
   l1:
+// O2: @llvm.lifetime.start.p0i8(i64 1
 bar(, 1);
+// O2: @llvm.lifetime.end.p0i8(i64 1
   }
   goto l1;
 }
@@ -69,8 +70,8 @@
   switch (n) {
   case 1:
 n = n;
-// O2-NOT: @llvm.lifetime.start.p0i8(i64 1
-// O2-NOT: @llvm.lifetime.end.p0i8(i64 1
+// O2: @llvm.lifetime.start.p0i8(i64 1
+// O2: @llvm.lifetime.end.p0i8(i64 1
 char x;
 bar(, 1);
 break;
@@ -83,7 +84,7 @@
 // CHECK-LABEL: @indirect_jump
 void indirect_jump(int n) {
   char x;
-  // O2-NOT: @llvm.lifetime
+  // O2: @llvm.lifetime
   void *T[] = {&};
   goto *T[n];
 L:
Index: clang/lib/CodeGen/CodeGenFunction.h
===
--- clang/lib/CodeGen/CodeGenFunction.h
+++ clang/lib/CodeGen/CodeGenFunction.h
@@ -38,6 +38,7 @@
 #include "llvm/ADT/MapVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Frontend/OpenMP/OMPIRBuilder.h"
+#include "llvm/IR/IntrinsicInst.h"
 #include "llvm/IR/ValueHandle.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Transforms/Utils/SanitizerStats.h"
@@ -931,6 +932,7 @@
   class LexicalScope : public RunCleanupsScope {
 SourceRange Range;
 SmallVector Labels;
+SmallVector LifetimeStartMarkers;
 LexicalScope *ParentScope;
 
 LexicalScope(const LexicalScope &) = delete;
@@ -950,6 +952,19 @@
   Labels.push_back(label);
 }
 
+void addLifetimeStartMarker(const llvm::CallInst *LifetimeStartMarker) {
+  assert(isa(LifetimeStartMarker) &&
+ cast(LifetimeStartMarker)->getIntrinsicID() ==
+ llvm::Intrinsic::lifetime_start &&
+ "LifetimeStartMarker Is not a lifetime start intrinsic");
+  LifetimeStartMarkers.push_back(LifetimeStartMarker);
+}
+
+const SmallVector &
+getLifetimeStartMarkers() const {
+  return LifetimeStartMarkers;
+}
+
 /// Exit this cleanup scope, emitting any accumulated
 /// cleanups.
 ~LexicalScope() {
@@ -2922,7 +2937,8 @@
   void EmitSehTryScopeBegin();
   void EmitSehTryScopeEnd();
 
-  llvm::Value *EmitLifetimeStart(llvm::TypeSize Size, llvm::Value *Addr);
+  llvm::Value *EmitLifetimeStart(llvm::TypeSize Size, llvm::Value *Addr,
+ bool isBypassed = false);
   void EmitLifetimeEnd(llvm::Value *Size, llvm::Value *Addr);
 
   llvm::Value *EmitCXXNewExpr(const CXXNewExpr *E);
Index: clang/lib/CodeGen/CGStmt.cpp
===
--- clang/lib/CodeGen/CGStmt.cpp
+++ clang/lib/CodeGen/CGStmt.cpp
@@ -647,6 +647,12 @@
 
   EmitBlock(Dest.getBlock());
 
+  if (CurLexicalScope)
+llvm::for_each(CurLexicalScope->getLifetimeStartMarkers(),
+   [this](const llvm::CallInst *LifetimeStartMarker) {
+  

[PATCH] D127589: [RISCV] Compatible with more RISCV related ld in the test

[luxufan via Phabricator via cfe-commits]

StephenFan added a comment.

Why not use `env PATH=` in the lit run line to clear the `PATH` env variable?


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[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

[luxufan via Phabricator via cfe-commits]

StephenFan added a comment.

Thanks @MaskRay, @asb !


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[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

[luxufan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG429cbac03906: [RISCV] Pass -mno-relax to assembler when 
-fno-integrated-as specified (authored by StephenFan).

Changed prior to commit:
  https://reviews.llvm.org/D120639?vs=418774=423327#toc

Repository:
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Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/test/Driver/riscv-gnutools.c


Index: clang/test/Driver/riscv-gnutools.c
===
--- clang/test/Driver/riscv-gnutools.c
+++ clang/test/Driver/riscv-gnutools.c
@@ -16,9 +16,14 @@
 // RUN: %clang --target=riscv32-unknown-elf 
--gcc-toolchain=%S/Inputs/basic_riscv32_tree -fno-integrated-as %s -### -c 
-march=rv32g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s
 
+// Check -mno-relax is passed when -fno-integrated-as specified
+// RUN: %clang -target riscv32-unknown-elf 
--gcc-toolchain=%S/Inputs/basic_riscv32_tree -mno-relax -fno-integrated-as %s 
-### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
+
 // CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" 
"rv32imac"
 // CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" 
"rv32imafdc"
 // CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
+// CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "{{.*}}" "-mno-relax"
 
 
 // 64-bit checks
@@ -35,6 +40,12 @@
 // RUN: %clang --target=riscv64-unknown-elf 
--gcc-toolchain=%S/Inputs/basic_riscv64_tree -fno-integrated-as %s -### -c 
-march=rv64g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s
 
+// Check -mno-relax is not passed when -fno-integrated-as specified
+// RUN: %clang -target riscv64-unknown-elf 
--gcc-toolchain=%S/Inputs/basic_riscv64_tree -mno-relax -mrelax 
-fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-RELAX %s
+
 // CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" 
"rv64imac"
 // CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" 
"rv64imafdc"
 // CHECK-RV64G-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64g"
+// CHECK-RV64-RELAX: "{{.*}}as{{(.exe)?}}"
+// CHECK-RV64-RELAX-NOT: "-mno-relax"
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -764,6 +764,8 @@
 StringRef MArchName = riscv::getRISCVArch(Args, 
getToolChain().getTriple());
 CmdArgs.push_back("-march");
 CmdArgs.push_back(MArchName.data());
+if (!Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true))
+  Args.addOptOutFlag(CmdArgs, options::OPT_mrelax, options::OPT_mno_relax);
 break;
   }
   case llvm::Triple::sparc:


Index: clang/test/Driver/riscv-gnutools.c
===
--- clang/test/Driver/riscv-gnutools.c
+++ clang/test/Driver/riscv-gnutools.c
@@ -16,9 +16,14 @@
 // RUN: %clang --target=riscv32-unknown-elf --gcc-toolchain=%S/Inputs/basic_riscv32_tree -fno-integrated-as %s -### -c -march=rv32g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s
 
+// Check -mno-relax is passed when -fno-integrated-as specified
+// RUN: %clang -target riscv32-unknown-elf --gcc-toolchain=%S/Inputs/basic_riscv32_tree -mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
+
 // CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" "rv32imac"
 // CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32imafdc"
 // CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
+// CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "{{.*}}" "-mno-relax"
 
 
 // 64-bit checks
@@ -35,6 +40,12 @@
 // RUN: %clang --target=riscv64-unknown-elf --gcc-toolchain=%S/Inputs/basic_riscv64_tree -fno-integrated-as %s -### -c -march=rv64g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s
 
+// Check -mno-relax is not passed when -fno-integrated-as specified
+// RUN: %clang -target riscv64-unknown-elf --gcc-toolchain=%S/Inputs/basic_riscv64_tree -mno-relax -mrelax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-RELAX %s
+
 // CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" "rv64imac"
 // CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64imafdc"
 // CHECK-RV64G-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64g"
+// CHECK-RV64-RELAX: "{{.*}}as{{(.exe)?}}"
+// CHECK-RV64-RELAX-NOT: "-mno-relax"
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ 

[PATCH] D122556: [RISCV] Add definitions for Xiangshan processors.

[luxufan via Phabricator via cfe-commits]

StephenFan added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCV.td:547
+def : ProcessorModel<"xiangshan-nanhu", NoSchedModel, [Feature64Bit,
+   FeatureStdExtM,
+   FeatureStdExtA,

The document says that `xiangshan-nanhu` cpu support 
`RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval` . 
And it seems that `svinval` extension is not supported by llvm.


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[PATCH] D122588: [RISCV][test] Make PATH empty when testing --gcc-toolchain is multilib_riscv_elf_sdk

[luxufan via Phabricator via cfe-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa5900401b147: [RISCV][test] Make PATH empty when testing 
--gcc-toolchain is… (authored by StephenFan).

Repository:
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Files:
  clang/test/Driver/riscv32-toolchain.c
  clang/test/Driver/riscv64-toolchain.c


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@@ -1,3 +1,4 @@
+// UNSUPPORTED: system-windows
 // A basic clang -cc1 command-line, and simple environment check.
 
 // RUN: %clang %s -### -no-canonical-prefixes --target=riscv64 \
@@ -104,7 +105,7 @@
 // C-RV64-LINUX-MULTI-LP64D: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/lib64/lp64d"
 // C-RV64-LINUX-MULTI-LP64D: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64d"
 
-// RUN: %clang %s -### -fuse-ld=ld \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform --sysroot= \
 // RUN:   -march=rv64imac -mabi=lp64\
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk 2>&1 \
@@ -119,7 +120,7 @@
 // C-RV64IMAC-BAREMETAL-MULTI-LP64: "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // C-RV64IMAC-BAREMETAL-MULTI-LP64: 
"{{.*}}/Inputs/multilib_riscv_elf_sdk/lib/gcc/riscv64-unknown-elf/8.2.0/rv64imac/lp64{{/|}}crtend.o"
 
-// RUN: %clang %s -### -fuse-ld=ld \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform --sysroot= \
 // RUN:   -march=rv64imafdc -mabi=lp64d \
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk 2>&1 \
Index: clang/test/Driver/riscv32-toolchain.c
===
--- clang/test/Driver/riscv32-toolchain.c
+++ clang/test/Driver/riscv32-toolchain.c
@@ -1,3 +1,4 @@
+// UNSUPPORTED: system-windows
 // A basic clang -cc1 command-line, and simple environment check.
 
 // RUN: %clang %s -### -no-canonical-prefixes --target=riscv32 \
@@ -74,7 +75,7 @@
 // CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "-lstdc++" "--start-group" "-lc" 
"-lgloss" "--end-group" "-lgcc"
 // CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: 
"{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clang %s -### -fuse-ld=ld -no-pie \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld -no-pie \
 // RUN:   --target=riscv32-unknown-linux-gnu --rtlib=platform -mabi=ilp32 \
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
@@ -89,7 +90,7 @@
 // C-RV32-LINUX-MULTI-ILP32: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/lib32/ilp32"
 // C-RV32-LINUX-MULTI-ILP32: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib32/ilp32"
 
-// RUN: %clang %s -### -fuse-ld=ld -no-pie \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld -no-pie \
 // RUN:   --target=riscv32-unknown-linux-gnu --rtlib=platform -march=rv32imafd 
\
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
@@ -104,7 +105,7 @@
 // C-RV32-LINUX-MULTI-ILP32D: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/lib32/ilp32d"
 // C-RV32-LINUX-MULTI-ILP32D: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib32/ilp32d"
 
-// RUN: %clang %s -### -fuse-ld=ld \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld \
 // RUN:   --target=riscv32-unknown-elf --rtlib=platform --sysroot= \
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV32I-BAREMETAL-MULTI-ILP32 %s
@@ -118,7 +119,7 @@
 // C-RV32I-BAREMETAL-MULTI-ILP32: "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // C-RV32I-BAREMETAL-MULTI-ILP32: 
"{{.*}}/Inputs/multilib_riscv_elf_sdk/lib/gcc/riscv64-unknown-elf/8.2.0/rv32imac/ilp32{{/|}}crtend.o"
 
-// RUN: %clang %s -### -fuse-ld=ld \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld \
 // RUN:   --target=riscv32-unknown-elf --rtlib=platform --sysroot= \
 // RUN:   -march=rv32im -mabi=ilp32\
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk 2>&1 \
@@ -133,7 +134,7 @@
 // C-RV32IM-BAREMETAL-MULTI-ILP32: "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // C-RV32IM-BAREMETAL-MULTI-ILP32: 
"{{.*}}/Inputs/multilib_riscv_elf_sdk/lib/gcc/riscv64-unknown-elf/8.2.0/rv32im/ilp32{{/|}}crtend.o"
 
-// RUN: %clang %s -### -fuse-ld=ld \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld \
 // RUN:   --target=riscv32-unknown-elf --rtlib=platform --sysroot= \
 // RUN:   -march=rv32iac -mabi=ilp32\
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk 2>&1 \
@@ -148,7 +149,7 @@
 // C-RV32IAC-BAREMETAL-MULTI-ILP32: "--start-group" "-lc" "-lgloss" 

[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

[luxufan via Phabricator via cfe-commits]

StephenFan updated this revision to Diff 418774.
StephenFan added a comment.
Herald added a subscriber: sunshaoce.

Address @MaskRay 's comments.

1. explicit default-argument to avoid error-prone
2. change riscv64 test to test the case when `-mno-relax -mrelax` specified.

Is the change of riscv64 test match your requirements?


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Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/test/Driver/riscv-gnutools.c


Index: clang/test/Driver/riscv-gnutools.c
===
--- clang/test/Driver/riscv-gnutools.c
+++ clang/test/Driver/riscv-gnutools.c
@@ -16,9 +16,14 @@
 // RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree 
-fno-integrated-as %s -### -c -march=rv32g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s
 
+// Check -mno-relax is passed when -fno-integrated-as specified
+// RUN: %clang -target riscv32-unknown-elf 
--gcc-toolchain=%S/Inputs/basic_riscv32_tree -mno-relax -fno-integrated-as %s 
-### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
+
 // CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" 
"rv32imac"
 // CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" 
"rv32imafdc"
 // CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
+// CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "{{.*}}" "-mno-relax"
 
 
 // 64-bit checks
@@ -35,6 +40,12 @@
 // RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree 
-fno-integrated-as %s -### -c -march=rv64g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s
 
+// Check -mno-relax is not passed when -fno-integrated-as specified
+// RUN: %clang -target riscv64-unknown-elf 
--gcc-toolchain=%S/Inputs/basic_riscv64_tree -mno-relax -mrelax 
-fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-RELAX %s
+
 // CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" 
"rv64imac"
 // CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" 
"rv64imafdc"
 // CHECK-RV64G-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64g"
+// CHECK-RV64-RELAX: "{{.*}}as{{(.exe)?}}"
+// CHECK-RV64-RELAX-NOT: "-mno-relax"
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -761,6 +761,8 @@
 StringRef MArchName = riscv::getRISCVArch(Args, 
getToolChain().getTriple());
 CmdArgs.push_back("-march");
 CmdArgs.push_back(MArchName.data());
+if (!Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true))
+  CmdArgs.push_back("-mno-relax");
 break;
   }
   case llvm::Triple::sparc:


Index: clang/test/Driver/riscv-gnutools.c
===
--- clang/test/Driver/riscv-gnutools.c
+++ clang/test/Driver/riscv-gnutools.c
@@ -16,9 +16,14 @@
 // RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree -fno-integrated-as %s -### -c -march=rv32g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s
 
+// Check -mno-relax is passed when -fno-integrated-as specified
+// RUN: %clang -target riscv32-unknown-elf --gcc-toolchain=%S/Inputs/basic_riscv32_tree -mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
+
 // CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" "rv32imac"
 // CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32imafdc"
 // CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
+// CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "{{.*}}" "-mno-relax"
 
 
 // 64-bit checks
@@ -35,6 +40,12 @@
 // RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree -fno-integrated-as %s -### -c -march=rv64g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s
 
+// Check -mno-relax is not passed when -fno-integrated-as specified
+// RUN: %clang -target riscv64-unknown-elf --gcc-toolchain=%S/Inputs/basic_riscv64_tree -mno-relax -mrelax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-RELAX %s
+
 // CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" "rv64imac"
 // CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64imafdc"
 // CHECK-RV64G-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64g"
+// CHECK-RV64-RELAX: "{{.*}}as{{(.exe)?}}"
+// CHECK-RV64-RELAX-NOT: "-mno-relax"
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -761,6 +761,8 @@
 StringRef MArchName = riscv::getRISCVArch(Args, 

[PATCH] D122588: [RISCV] Make PATH empty when testing --gcc-toolchain is multilib_riscv_elf_sdk

[luxufan via Phabricator via cfe-commits]

StephenFan updated this revision to Diff 418771.
StephenFan added a comment.
Herald added a subscriber: sunshaoce.

Address @MaskRay 's comments

Change log:

1. Update test in riscv32-toolchain.c
2. Make system-windows UNSUPPORTED


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Files:
  clang/test/Driver/riscv32-toolchain.c
  clang/test/Driver/riscv64-toolchain.c


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@@ -1,3 +1,4 @@
+// UNSUPPORTED: system-windows
 // A basic clang -cc1 command-line, and simple environment check.
 
 // RUN: %clang %s -### -no-canonical-prefixes --target=riscv64 \
@@ -104,7 +105,7 @@
 // C-RV64-LINUX-MULTI-LP64D: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/lib64/lp64d"
 // C-RV64-LINUX-MULTI-LP64D: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64d"
 
-// RUN: %clang %s -### -fuse-ld=ld \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform --sysroot= \
 // RUN:   -march=rv64imac -mabi=lp64\
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk 2>&1 \
@@ -119,7 +120,7 @@
 // C-RV64IMAC-BAREMETAL-MULTI-LP64: "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // C-RV64IMAC-BAREMETAL-MULTI-LP64: 
"{{.*}}/Inputs/multilib_riscv_elf_sdk/lib/gcc/riscv64-unknown-elf/8.2.0/rv64imac/lp64{{/|}}crtend.o"
 
-// RUN: %clang %s -### -fuse-ld=ld \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform --sysroot= \
 // RUN:   -march=rv64imafdc -mabi=lp64d \
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk 2>&1 \
Index: clang/test/Driver/riscv32-toolchain.c
===
--- clang/test/Driver/riscv32-toolchain.c
+++ clang/test/Driver/riscv32-toolchain.c
@@ -1,3 +1,4 @@
+// UNSUPPORTED: system-windows
 // A basic clang -cc1 command-line, and simple environment check.
 
 // RUN: %clang %s -### -no-canonical-prefixes --target=riscv32 \
@@ -74,7 +75,7 @@
 // CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: "-lstdc++" "--start-group" "-lc" 
"-lgloss" "--end-group" "-lgcc"
 // CXX-RV32-BAREMETAL-NOSYSROOT-ILP32: 
"{{.*}}/Inputs/basic_riscv32_tree/lib/gcc/riscv32-unknown-elf/8.0.1{{/|}}crtend.o"
 
-// RUN: %clang %s -### -fuse-ld=ld -no-pie \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld -no-pie \
 // RUN:   --target=riscv32-unknown-linux-gnu --rtlib=platform -mabi=ilp32 \
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
@@ -89,7 +90,7 @@
 // C-RV32-LINUX-MULTI-ILP32: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/lib32/ilp32"
 // C-RV32-LINUX-MULTI-ILP32: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib32/ilp32"
 
-// RUN: %clang %s -### -fuse-ld=ld -no-pie \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld -no-pie \
 // RUN:   --target=riscv32-unknown-linux-gnu --rtlib=platform -march=rv32imafd 
\
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_linux_sdk \
 // RUN:   --sysroot=%S/Inputs/multilib_riscv_linux_sdk/sysroot 2>&1 \
@@ -104,7 +105,7 @@
 // C-RV32-LINUX-MULTI-ILP32D: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/lib32/ilp32d"
 // C-RV32-LINUX-MULTI-ILP32D: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib32/ilp32d"
 
-// RUN: %clang %s -### -fuse-ld=ld \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld \
 // RUN:   --target=riscv32-unknown-elf --rtlib=platform --sysroot= \
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk 2>&1 \
 // RUN:   | FileCheck -check-prefix=C-RV32I-BAREMETAL-MULTI-ILP32 %s
@@ -118,7 +119,7 @@
 // C-RV32I-BAREMETAL-MULTI-ILP32: "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // C-RV32I-BAREMETAL-MULTI-ILP32: 
"{{.*}}/Inputs/multilib_riscv_elf_sdk/lib/gcc/riscv64-unknown-elf/8.2.0/rv32imac/ilp32{{/|}}crtend.o"
 
-// RUN: %clang %s -### -fuse-ld=ld \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld \
 // RUN:   --target=riscv32-unknown-elf --rtlib=platform --sysroot= \
 // RUN:   -march=rv32im -mabi=ilp32\
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk 2>&1 \
@@ -133,7 +134,7 @@
 // C-RV32IM-BAREMETAL-MULTI-ILP32: "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // C-RV32IM-BAREMETAL-MULTI-ILP32: 
"{{.*}}/Inputs/multilib_riscv_elf_sdk/lib/gcc/riscv64-unknown-elf/8.2.0/rv32im/ilp32{{/|}}crtend.o"
 
-// RUN: %clang %s -### -fuse-ld=ld \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld \
 // RUN:   --target=riscv32-unknown-elf --rtlib=platform --sysroot= \
 // RUN:   -march=rv32iac -mabi=ilp32\
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk 2>&1 \
@@ -148,7 +149,7 @@
 // C-RV32IAC-BAREMETAL-MULTI-ILP32: "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // 

[PATCH] D122588: [RISCV] Make PATH empty when testing --gcc-toolchain is multilib_riscv_elf_sdk

[luxufan via Phabricator via cfe-commits]

StephenFan created this revision.
StephenFan added reviewers: MaskRay, khchen, asb, jrtc27.
Herald added subscribers: s, VincentWu, luke957, vkmr, frasercrmck, evandro, 
luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, 
PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, 
kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, arichardson.
Herald added a project: All.
StephenFan requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD.
Herald added a project: clang.

Due to D79842 , clang dirver would search 
possible tool name in both possible
locations, then moving to the next name. The gcc toolchain 
`llvm-project/clang/test/Driver/
Inputs/multilib_riscv_elf_sdk` don't have a `riscv64-unknown-elf-ld` executable 
in
`llvm-project/clang/test/Driver/Inputs/multilib_riscv_elf_sdk/bin/`. So when 
searching
`riscv64-unknown-elf-ld`, if there is a `riscv64-unknown-elf-ld` in `PATH`, the
test would fail.

This patch makes the `PATH` empty when testing it.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D122588

Files:
  clang/test/Driver/riscv64-toolchain.c


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@@ -104,7 +104,7 @@
 // C-RV64-LINUX-MULTI-LP64D: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/lib64/lp64d"
 // C-RV64-LINUX-MULTI-LP64D: 
"-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64d"
 
-// RUN: %clang %s -### -fuse-ld=ld \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform --sysroot= \
 // RUN:   -march=rv64imac -mabi=lp64\
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk 2>&1 \
@@ -119,7 +119,7 @@
 // C-RV64IMAC-BAREMETAL-MULTI-LP64: "--start-group" "-lc" "-lgloss" 
"--end-group" "-lgcc"
 // C-RV64IMAC-BAREMETAL-MULTI-LP64: 
"{{.*}}/Inputs/multilib_riscv_elf_sdk/lib/gcc/riscv64-unknown-elf/8.2.0/rv64imac/lp64{{/|}}crtend.o"
 
-// RUN: %clang %s -### -fuse-ld=ld \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform --sysroot= \
 // RUN:   -march=rv64imafdc -mabi=lp64d \
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk 2>&1 \


Index: clang/test/Driver/riscv64-toolchain.c
===
--- clang/test/Driver/riscv64-toolchain.c
+++ clang/test/Driver/riscv64-toolchain.c
@@ -104,7 +104,7 @@
 // C-RV64-LINUX-MULTI-LP64D: "-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/lib64/lp64d"
 // C-RV64-LINUX-MULTI-LP64D: "-L{{.*}}/Inputs/multilib_riscv_linux_sdk/sysroot/usr/lib64/lp64d"
 
-// RUN: %clang %s -### -fuse-ld=ld \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform --sysroot= \
 // RUN:   -march=rv64imac -mabi=lp64\
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk 2>&1 \
@@ -119,7 +119,7 @@
 // C-RV64IMAC-BAREMETAL-MULTI-LP64: "--start-group" "-lc" "-lgloss" "--end-group" "-lgcc"
 // C-RV64IMAC-BAREMETAL-MULTI-LP64: "{{.*}}/Inputs/multilib_riscv_elf_sdk/lib/gcc/riscv64-unknown-elf/8.2.0/rv64imac/lp64{{/|}}crtend.o"
 
-// RUN: %clang %s -### -fuse-ld=ld \
+// RUN: env "PATH=" %clang %s -### -fuse-ld=ld \
 // RUN:   --target=riscv64-unknown-elf --rtlib=platform --sysroot= \
 // RUN:   -march=rv64imafdc -mabi=lp64d \
 // RUN:   --gcc-toolchain=%S/Inputs/multilib_riscv_elf_sdk 2>&1 \
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[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

[luxufan via Phabricator via cfe-commits]

StephenFan added a comment.

@jrtc27, @kito-cheng Do you have any other comments ? :)


Repository:
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[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

[luxufan via Phabricator via cfe-commits]

StephenFan updated this revision to Diff 418379.
StephenFan added a comment.
Herald added a subscriber: MaskRay.

Grammatical fix


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120639/new/

https://reviews.llvm.org/D120639

Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/test/Driver/riscv-gnutools.c


Index: clang/test/Driver/riscv-gnutools.c
===
--- clang/test/Driver/riscv-gnutools.c
+++ clang/test/Driver/riscv-gnutools.c
@@ -16,9 +16,14 @@
 // RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree 
-fno-integrated-as %s -### -c -march=rv32g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s
 
+// Check -mno-relax is passed when -fno-integrated-as specified
+// RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree 
-mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
+
 // CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" 
"rv32imac"
 // CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" 
"rv32imafdc"
 // CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
+// CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "{{.*}}" "-mno-relax"
 
 
 // 64-bit checks
@@ -35,6 +40,11 @@
 // RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree 
-fno-integrated-as %s -### -c -march=rv64g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s
 
+// Check -mno-relax is passed when -fno-integrated-as specified
+// RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree 
-mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-NO-RELAX %s
+
 // CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" 
"rv64imac"
 // CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" 
"rv64imafdc"
 // CHECK-RV64G-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64g"
+// CHECK-RV64-NO-RELAX: "{{.*}}as{{(.exe)?}}" "{{.*}}" "-mno-relax"
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -761,6 +761,8 @@
 StringRef MArchName = riscv::getRISCVArch(Args, 
getToolChain().getTriple());
 CmdArgs.push_back("-march");
 CmdArgs.push_back(MArchName.data());
+if (!Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax))
+  CmdArgs.push_back("-mno-relax");
 break;
   }
   case llvm::Triple::sparc:


Index: clang/test/Driver/riscv-gnutools.c
===
--- clang/test/Driver/riscv-gnutools.c
+++ clang/test/Driver/riscv-gnutools.c
@@ -16,9 +16,14 @@
 // RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree -fno-integrated-as %s -### -c -march=rv32g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s
 
+// Check -mno-relax is passed when -fno-integrated-as specified
+// RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree -mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
+
 // CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" "rv32imac"
 // CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32imafdc"
 // CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
+// CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "{{.*}}" "-mno-relax"
 
 
 // 64-bit checks
@@ -35,6 +40,11 @@
 // RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree -fno-integrated-as %s -### -c -march=rv64g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s
 
+// Check -mno-relax is passed when -fno-integrated-as specified
+// RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree -mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-NO-RELAX %s
+
 // CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" "rv64imac"
 // CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64imafdc"
 // CHECK-RV64G-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64g"
+// CHECK-RV64-NO-RELAX: "{{.*}}as{{(.exe)?}}" "{{.*}}" "-mno-relax"
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -761,6 +761,8 @@
 StringRef MArchName = riscv::getRISCVArch(Args, getToolChain().getTriple());
 CmdArgs.push_back("-march");
 CmdArgs.push_back(MArchName.data());
+if (!Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax))
+  CmdArgs.push_back("-mno-relax");
 break;
   }
   case llvm::Triple::sparc:
___
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[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

[luxufan via Phabricator via cfe-commits]

StephenFan added a comment.
Herald added subscribers: s, arichardson.

Ping :)


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[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

[luxufan via Phabricator via cfe-commits]

StephenFan added a comment.

Ping.


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[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

[luxufan via Phabricator via cfe-commits]

StephenFan updated this revision to Diff 413774.
StephenFan added a comment.

Address @kito-cheng 's comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
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Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/test/Driver/riscv-gnutools.c


Index: clang/test/Driver/riscv-gnutools.c
===
--- clang/test/Driver/riscv-gnutools.c
+++ clang/test/Driver/riscv-gnutools.c
@@ -16,9 +16,14 @@
 // RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree 
-fno-integrated-as %s -### -c -march=rv32g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s
 
+// Check -mno-relax has passed when -fno-integrated-as specified
+// RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree 
-mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
+
 // CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" 
"rv32imac"
 // CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" 
"rv32imafdc"
 // CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
+// CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "{{.*}}" "-mno-relax"
 
 
 // 64-bit checks
@@ -35,6 +40,11 @@
 // RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree 
-fno-integrated-as %s -### -c -march=rv64g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s
 
+// Check -mno-relax has passed when -fno-integrated-as specified
+// RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree 
-mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-NO-RELAX %s
+
 // CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" 
"rv64imac"
 // CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" 
"rv64imafdc"
 // CHECK-RV64G-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64g"
+// CHECK-RV64-NO-RELAX: "{{.*}}as{{(.exe)?}}" "{{.*}}" "-mno-relax"
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -761,6 +761,8 @@
 StringRef MArchName = riscv::getRISCVArch(Args, 
getToolChain().getTriple());
 CmdArgs.push_back("-march");
 CmdArgs.push_back(MArchName.data());
+if (!Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax))
+  CmdArgs.push_back("-mno-relax");
 break;
   }
   case llvm::Triple::sparc:


Index: clang/test/Driver/riscv-gnutools.c
===
--- clang/test/Driver/riscv-gnutools.c
+++ clang/test/Driver/riscv-gnutools.c
@@ -16,9 +16,14 @@
 // RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree -fno-integrated-as %s -### -c -march=rv32g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s
 
+// Check -mno-relax has passed when -fno-integrated-as specified
+// RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree -mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
+
 // CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" "rv32imac"
 // CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32imafdc"
 // CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
+// CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "{{.*}}" "-mno-relax"
 
 
 // 64-bit checks
@@ -35,6 +40,11 @@
 // RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree -fno-integrated-as %s -### -c -march=rv64g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s
 
+// Check -mno-relax has passed when -fno-integrated-as specified
+// RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree -mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-NO-RELAX %s
+
 // CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" "rv64imac"
 // CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64imafdc"
 // CHECK-RV64G-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64g"
+// CHECK-RV64-NO-RELAX: "{{.*}}as{{(.exe)?}}" "{{.*}}" "-mno-relax"
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -761,6 +761,8 @@
 StringRef MArchName = riscv::getRISCVArch(Args, getToolChain().getTriple());
 CmdArgs.push_back("-march");
 CmdArgs.push_back(MArchName.data());
+if (!Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax))
+  CmdArgs.push_back("-mno-relax");
 break;
   }
   case llvm::Triple::sparc:
___
cfe-commits mailing list

[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

[luxufan via Phabricator via cfe-commits]

StephenFan updated this revision to Diff 411730.
StephenFan added a comment.

Address @jrtc27 's comments


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120639/new/

https://reviews.llvm.org/D120639

Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/test/Driver/riscv-gnutools.c


Index: clang/test/Driver/riscv-gnutools.c
===
--- clang/test/Driver/riscv-gnutools.c
+++ clang/test/Driver/riscv-gnutools.c
@@ -16,9 +16,14 @@
 // RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree 
-fno-integrated-as %s -### -c -march=rv32g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s
 
+// Check default when -mno-relax specified
+// RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree 
-mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
+
 // CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" 
"rv32imac"
 // CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" 
"rv32imafdc"
 // CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
+// CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" 
"rv32imac" "-mno-relax"
 
 
 // 64-bit checks
@@ -35,6 +40,11 @@
 // RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree 
-fno-integrated-as %s -### -c -march=rv64g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s
 
+// Check default when -mno-relax specified
+// RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree 
-mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-NO-RELAX %s
+
 // CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" 
"rv64imac"
 // CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" 
"rv64imafdc"
 // CHECK-RV64G-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64g"
+// CHECK-RV64-NO-RELAX: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" 
"rv64imac" "-mno-relax"
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -761,6 +761,8 @@
 StringRef MArchName = riscv::getRISCVArch(Args, 
getToolChain().getTriple());
 CmdArgs.push_back("-march");
 CmdArgs.push_back(MArchName.data());
+if (!Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax))
+  CmdArgs.push_back("-mno-relax");
 break;
   }
   case llvm::Triple::sparc:


Index: clang/test/Driver/riscv-gnutools.c
===
--- clang/test/Driver/riscv-gnutools.c
+++ clang/test/Driver/riscv-gnutools.c
@@ -16,9 +16,14 @@
 // RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree -fno-integrated-as %s -### -c -march=rv32g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s
 
+// Check default when -mno-relax specified
+// RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree -mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
+
 // CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" "rv32imac"
 // CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32imafdc"
 // CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
+// CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" "rv32imac" "-mno-relax"
 
 
 // 64-bit checks
@@ -35,6 +40,11 @@
 // RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree -fno-integrated-as %s -### -c -march=rv64g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s
 
+// Check default when -mno-relax specified
+// RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree -mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-NO-RELAX %s
+
 // CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" "rv64imac"
 // CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64imafdc"
 // CHECK-RV64G-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64g"
+// CHECK-RV64-NO-RELAX: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" "rv64imac" "-mno-relax"
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -761,6 +761,8 @@
 StringRef MArchName = riscv::getRISCVArch(Args, getToolChain().getTriple());
 CmdArgs.push_back("-march");
 CmdArgs.push_back(MArchName.data());
+if (!Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax))
+  CmdArgs.push_back("-mno-relax");
 break;
   }
   case llvm::Triple::sparc:
___
cfe-commits 

[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

[luxufan via Phabricator via cfe-commits]

StephenFan updated this revision to Diff 411724.
StephenFan added a comment.

fix typo


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D120639/new/

https://reviews.llvm.org/D120639

Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/test/Driver/riscv-gnutools.c


Index: clang/test/Driver/riscv-gnutools.c
===
--- clang/test/Driver/riscv-gnutools.c
+++ clang/test/Driver/riscv-gnutools.c
@@ -16,9 +16,14 @@
 // RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree 
-fno-integrated-as %s -### -c -march=rv32g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s
 
+// Check default when -mno-relax and -fno-integrated-as specified
+// RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree 
-mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
+
 // CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" 
"rv32imac"
 // CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" 
"rv32imafdc"
 // CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
+// CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" 
"rv32imac" "-mno-relax"
 
 
 // 64-bit checks
@@ -35,6 +40,11 @@
 // RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree 
-fno-integrated-as %s -### -c -march=rv64g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s
 
+// Check default when -mno-relax and -fno-integrated-as specified
+// RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree 
-mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-NO-RELAX %s
+
 // CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" 
"rv64imac"
 // CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" 
"rv64imafdc"
 // CHECK-RV64G-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64g"
+// CHECK-RV64-NO-RELAX: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" 
"rv64imac" "-mno-relax"
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -761,6 +761,8 @@
 StringRef MArchName = riscv::getRISCVArch(Args, 
getToolChain().getTriple());
 CmdArgs.push_back("-march");
 CmdArgs.push_back(MArchName.data());
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("-mno-relax");
 break;
   }
   case llvm::Triple::sparc:


Index: clang/test/Driver/riscv-gnutools.c
===
--- clang/test/Driver/riscv-gnutools.c
+++ clang/test/Driver/riscv-gnutools.c
@@ -16,9 +16,14 @@
 // RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree -fno-integrated-as %s -### -c -march=rv32g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s
 
+// Check default when -mno-relax and -fno-integrated-as specified
+// RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree -mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
+
 // CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" "rv32imac"
 // CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32imafdc"
 // CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
+// CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" "rv32imac" "-mno-relax"
 
 
 // 64-bit checks
@@ -35,6 +40,11 @@
 // RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree -fno-integrated-as %s -### -c -march=rv64g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s
 
+// Check default when -mno-relax and -fno-integrated-as specified
+// RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree -mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-NO-RELAX %s
+
 // CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" "rv64imac"
 // CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64imafdc"
 // CHECK-RV64G-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64g"
+// CHECK-RV64-NO-RELAX: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" "rv64imac" "-mno-relax"
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -761,6 +761,8 @@
 StringRef MArchName = riscv::getRISCVArch(Args, getToolChain().getTriple());
 CmdArgs.push_back("-march");
 CmdArgs.push_back(MArchName.data());
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("-mno-relax");
 break;
   }
   case llvm::Triple::sparc:

[PATCH] D120639: [RISCV] Pass -mno-relax to assembler when -fno-integrated-as specified

[luxufan via Phabricator via cfe-commits]

StephenFan created this revision.
StephenFan added reviewers: asb, jrtc27, craig.topper.
Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, 
vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, 
Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, 
edward-jones, zzheng, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar.
StephenFan requested review of this revision.
Herald added subscribers: cfe-commits, pcwang-thead, eopXD.
Herald added a project: clang.

In the past, `clang --target=riscv64-unknown-linux-gnu -mno-relax -c hello.s` 
will assemble hello.s without relaxation, but `clang 
--target=riscv64-unknown-linux-gnu -mno-relax -fno-integrated-as -c hello.s` 
doesn't pass the `-mno-relax` option to assembler, and assemble with relaxation
This patch pass the -mno-relax option to assembler when -fno-integrated-as is 
specified.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D120639

Files:
  clang/lib/Driver/ToolChains/Gnu.cpp
  clang/test/Driver/riscv-gnutools.c


Index: clang/test/Driver/riscv-gnutools.c
===
--- clang/test/Driver/riscv-gnutools.c
+++ clang/test/Driver/riscv-gnutools.c
@@ -16,9 +16,14 @@
 // RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree 
-fno-integrated-as %s -### -c -march=rv32g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s
 
+// Check default when -mno-relax specified
+// RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree 
-mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
+
 // CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" 
"rv32imac"
 // CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" 
"rv32imafdc"
 // CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
+// CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" 
"rv32imac" "-mno-relax"
 
 
 // 64-bit checks
@@ -35,6 +40,11 @@
 // RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree 
-fno-integrated-as %s -### -c -march=rv64g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s
 
+// Check default when -mno-relax specified
+// RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree 
-mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-NO-RELAX %s
+
 // CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" 
"rv64imac"
 // CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" 
"rv64imafdc"
 // CHECK-RV64G-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64g"
+// CHECK-RV64-NO-RELAX: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" 
"rv64imac" "-mno-relax"
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -761,6 +761,8 @@
 StringRef MArchName = riscv::getRISCVArch(Args, 
getToolChain().getTriple());
 CmdArgs.push_back("-march");
 CmdArgs.push_back(MArchName.data());
+if (Args.hasArg(options::OPT_mno_relax))
+  CmdArgs.push_back("-mno-relax");
 break;
   }
   case llvm::Triple::sparc:


Index: clang/test/Driver/riscv-gnutools.c
===
--- clang/test/Driver/riscv-gnutools.c
+++ clang/test/Driver/riscv-gnutools.c
@@ -16,9 +16,14 @@
 // RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree -fno-integrated-as %s -### -c -march=rv32g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32G-ILP32D %s
 
+// Check default when -mno-relax specified
+// RUN: %clang -target riscv32 --gcc-toolchain=%S/Inputs/basic_riscv32_tree -mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
+
 // CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" "rv32imac"
 // CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32imafdc"
 // CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
+// CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" "rv32imac" "-mno-relax"
 
 
 // 64-bit checks
@@ -35,6 +40,11 @@
 // RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree -fno-integrated-as %s -### -c -march=rv64g \
 // RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64G-LP64D %s
 
+// Check default when -mno-relax specified
+// RUN: %clang -target riscv64 --gcc-toolchain=%S/Inputs/basic_riscv64_tree -mno-relax -fno-integrated-as %s -### -c \
+// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-NO-RELAX %s
+
 // CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" "rv64imac"
 // CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64imafdc"
 // CHECK-RV64G-LP64D: 

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

[luxufan via Phabricator via cfe-commits]

StephenFan added inline comments.



Comment at: llvm/lib/Support/RISCVISAInfo.cpp:115
+  return make_filter_range(SupportedExtensionInfos,
+   [&](const RISCVSupportedExtensionInfo ) {
+ return ExtInfo.Name == ExtName;

This lambda function will keep alive out of current scope.
Maybe the `[&]` should change to `[ExtName]`




Repository:
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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[luxufan via Phabricator via cfe-commits]

StephenFan added a comment.

In D93298#2544775 , @asb wrote:

> In D93298#2544459 , @StephenFan 
> wrote:
>
>> According to  @jrtc27 's review that is 
>> "As for Zfinx itself, well, the idea is fine, but I really detest the way 
>> it's being done as an extension to F/D/Zfh. Running F code on an FZfh core 
>> _does not work_ so it is not an _extension_. Instead it should really be a 
>> set of separate extensions to I/E that conflict with F/D/Zfh, i.e. Zfinx, 
>> Zdinx and Zfhinx, but apparently asking code that complies with a ratified 
>> standard to change itself in order to not break when a new extension is 
>> introduced is a-ok in the RISC-V world.". 
>> We split the Zfinx into 3 separate extensions which is Zfinx, Zdinx, and 
>> Zfhinx.
>
> Ah I see. I interpreted jrtc27's comment as a general gripe about the spec 
> (which perhaps could be relayed to those working on the zfinx spec) rather as 
> a direction for changing this patch in particular. Anyway, it's a detail that 
> shouldn't affect an initial review. Thanks for clarifying.

Oh, I'm sorry. It seems that I misunderstood @jrtc27 's comment. I will merge 
the Zfinx, Zdinx, Zfhinx into Zfinx if this patch is ready for accepting.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

[luxufan via Phabricator via cfe-commits]

StephenFan added a comment.

In D93298#253 , @asb wrote:

> I started reviewing this alongside the specification in 
> https://github.com/riscv/riscv-zfinx/blob/master/Zfinx_spec.adoc. At the time 
> of writing, it seems to define "zfinx" but not "zfhinx" and "zfdinx" as seem 
> to be used in this patch. I think intent is that rv32ifd_zfinx is the 
> equivalent of "zfdinx" in this patch. Is there a reason to go for different 
> naming, or a different version of the spec I should be looking at?

According to  @jrtc27 's review that is 
"As for Zfinx itself, well, the idea is fine, but I really detest the way it's 
being done as an extension to F/D/Zfh. Running F code on an FZfh core _does not 
work_ so it is not an _extension_. Instead it should really be a set of 
separate extensions to I/E that conflict with F/D/Zfh, i.e. Zfinx, Zdinx and 
Zfhinx, but apparently asking code that complies with a ratified standard to 
change itself in order to not break when a new extension is introduced is a-ok 
in the RISC-V world.". 
We split the Zfinx into 3 separate extensions which is Zfinx, Zdinx, and Zfhinx.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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StephenFan added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1663
 
+OperandMatchResultTy RISCVAsmParser::parseGPRasFPR(OperandVector ) {
+  switch (getLexer().getKind()) {

StephenFan wrote:
> jrtc27 wrote:
> > Why can't you just use parseRegister?
> use the default parseRegister will make the test cases in other files fail. 
> For example:
> 
> ```
> fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:10: error: invalid operand for 
> instruction
> ```
> this is the test case in rv64d-invalid.s. If uses the default parseRegister. 
> the invalid operand is in column 14 (ft3 operand) instead of 10 (a3 operand).
> Why can't you just use parseRegister?

use the default parseRegister will make the test cases in other files fail. For 
example:

```
fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
```
this is the test case in rv64d-invalid.s. If uses the default parseRegister. 
the invalid operand is in column 14 (ft3 operand) instead of 10 (a3 operand).



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:59
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPUnaryOpINX_r funct7, bits<3> funct3, RegisterOperand rdty,
+RegisterOperand rs1ty, string opcodestr>

StephenFan wrote:
> jrtc27 wrote:
> > Don't duplicate all these, they're identical to the normal floating point 
> > versions.
> Because of normal floating point version only support RegisterClass, but we 
> use the RegisterOperand, so we change this. Or if there is more convenient 
> way to resolve this?
> Because of normal floating point version only support RegisterClass, but we 
> use the RegisterOperand, so we change this. Or if there is more convenient 
> way to resolve this?

Because of normal floating point version only support RegisterClass, but we use 
the RegisterOperand, so we change this. Or if there is more convenient way to 
resolve this?



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:468
+   Reg.AltNames> {
+  let SubRegIndices = [sub_32, sub_32_hi];
+}

StephenFan wrote:
> jrtc27 wrote:
> > Does this hard-coding of 32 cause issues on RV64?
> I don't known if it will cause issues on RV64. But the zfinx spec specifies 
> that register pairs are only used in RV32
> Does this hard-coding of 32 cause issues on RV64?

I don't known if it will cause issues on RV64. But the zfinx spec specifies 
that register pairs are only used in RV32


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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StephenFan added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1663
 
+OperandMatchResultTy RISCVAsmParser::parseGPRasFPR(OperandVector ) {
+  switch (getLexer().getKind()) {

jrtc27 wrote:
> Why can't you just use parseRegister?
use the default parseRegister will make the test cases in other files fail. For 
example:

```
fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
```
this is the test case in rv64d-invalid.s. If uses the default parseRegister. 
the invalid operand is in column 14 (ft3 operand) instead of 10 (a3 operand).



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:59
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class FPUnaryOpINX_r funct7, bits<3> funct3, RegisterOperand rdty,
+RegisterOperand rs1ty, string opcodestr>

jrtc27 wrote:
> Don't duplicate all these, they're identical to the normal floating point 
> versions.
Because of normal floating point version only support RegisterClass, but we use 
the RegisterOperand, so we change this. Or if there is more convenient way to 
resolve this?



Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:468
+   Reg.AltNames> {
+  let SubRegIndices = [sub_32, sub_32_hi];
+}

jrtc27 wrote:
> Does this hard-coding of 32 cause issues on RV64?
I don't known if it will cause issues on RV64. But the zfinx spec specifies 
that register pairs are only used in RV32


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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StephenFan added inline comments.



Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:983
+  }
+
   return Match_InvalidOperand;

It seems like that this function is not useful.


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[PATCH] D93298: [RISCV] add the MC layer support of Zfinx extension

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StephenFan added inline comments.



Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfinx.td:102
+: InstAlias;
+

use GPR as instruction operand may cause the codegen part of zfinx report 
errors. Because the GPR has data type i32 or i64, However, the zfinx will deal 
with the data type f64 or f32.


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